--- /dev/null
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+ <storageModule moduleId="refreshScope" versionNumber="1">\r
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+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
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+</cproject>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+ <name>FreeRTOS_Demo</name>\r
+ <comment></comment>\r
+ <projects>\r
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+ <buildSpec>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
+ <triggers>clean,full,incremental,</triggers>\r
+ <arguments>\r
+ <dictionary>\r
+ <key>?name?</key>\r
+ <value></value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.append_environment</key>\r
+ <value>true</value>\r
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+ <dictionary>\r
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+ <value>all</value>\r
+ </dictionary>\r
+ <dictionary>\r
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+ <value></value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildCommand</key>\r
+ <value>make</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildLocation</key>\r
+ <value>${workspace_loc:/FreeRTOS_Demo/Debug}</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>\r
+ <value>clean</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.contents</key>\r
+ <value>org.eclipse.cdt.make.core.activeConfigSettings</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+ <value>false</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.fullBuildTarget</key>\r
+ <value>all</value>\r
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+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+ <triggers>full,incremental,</triggers>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ </buildSpec>\r
+ <natures>\r
+ <nature>org.eclipse.cdt.core.cnature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+ </natures>\r
+ <linkedResources>\r
+ <link>\r
+ <name>Source/FreeRTOS-Source</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/FreeRTOS-Source/Portable</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/FreeRTOS-Source/include</name>\r
+ <type>2</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Source/include</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/FreeRTOS-Source/list.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Source/list.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/FreeRTOS-Source/queue.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Source/queue.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/FreeRTOS-Source/tasks.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Source/tasks.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/FreeRTOS-Source/timers.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Source/timers.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/Common-Demo-Source</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/FreeRTOS-Plus-CLI</name>\r
+ <type>2</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/FreeRTOS-Plus-FAT-SL</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/FreeRTOS-Source/Portable/MemMang</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/FreeRTOS-Source/Portable/RVDS</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/Common-Demo-Source/BlockQ.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/BlockQ.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/Common-Demo-Source/GenQTest.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/GenQTest.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/Common-Demo-Source/TimerDemo.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/TimerDemo.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/Common-Demo-Source/blocktim.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/blocktim.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/Common-Demo-Source/comtest.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/comtest.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/Common-Demo-Source/countsem.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/countsem.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/Common-Demo-Source/death.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/death.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/Common-Demo-Source/dynamic.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/dynamic.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/Common-Demo-Source/flop.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/flop.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/Common-Demo-Source/include</name>\r
+ <type>2</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Demo/Common/include</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/Common-Demo-Source/recmutex.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/recmutex.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/Common-Demo-Source/semtest.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/semtest.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/FreeRTOS-Plus-FAT-SL/Media-Driver</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/FreeRTOS-Plus-FAT-SL/api</name>\r
+ <type>2</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-FAT-SL/api</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/FreeRTOS-Plus-FAT-SL/common</name>\r
+ <type>2</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-FAT-SL/fat_sl/common</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/FreeRTOS-Plus-FAT-SL/rtc</name>\r
+ <type>2</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-FAT-SL/psp/target/rtc</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/FreeRTOS-Source/Portable/MemMang/heap_4.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Source/portable/MemMang/heap_4.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/FreeRTOS-Source/Portable/RVDS/ARM_CA9</name>\r
+ <type>2</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS/Source/portable/RVDS/ARM_CA9</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Source/Full-Demo/FreeRTOS-Plus-FAT-SL/Media-Driver/ramdrv_f.c</name>\r
+ <type>1</type>\r
+ <locationURI>FreeRTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-FAT-SL/media-drv/ram/ramdrv_f.c</locationURI>\r
+ </link>\r
+ </linkedResources>\r
+ <variableList>\r
+ <variable>\r
+ <name>FreeRTOS_ROOT</name>\r
+ <value>$%7BPARENT-3-PROJECT_LOC%7D</value>\r
+ </variable>\r
+ </variableList>\r
+</projectDescription>\r
--- /dev/null
+#Sun Jun 16 20:16:37 BST 2013\r
+eclipse.preferences.version=1\r
+encoding//Source/RenesasFiles/handler/reset_handler.s=UTF-8\r
+encoding//Source/RenesasFiles/include/iodefine.h=UTF-8\r
--- /dev/null
+/*************************************************************************\r
+ *\r
+ * Used with ICCARM and AARM.\r
+ *\r
+ * (c) Copyright IAR Systems 2013\r
+ *\r
+ * File name : main.c\r
+ * Description : main module\r
+ **************************************************************************/\r
+\r
+/*\r
+ * Called from Cstart.s to configure the chip and board specific IO before\r
+ * main() is called.\r
+ */\r
+\r
+/** include files **/\r
+#include <Renesas/ior7s721000.h>\r
+#include <intrinsics.h>\r
+#include <stdint.h>\r
+#include "armv7a_cp15_drv.h"\r
+#include "devdrv_common.h"\r
+\r
+/* Renesas include files. */\r
+#include "stb_init.h"\r
+#include "port_init.h"\r
+#include "devdrv_intc.h"\r
+\r
+\r
+/** external data **/\r
+#pragma section = ".intvec"\r
+\r
+extern void Peripheral_BasicInit( void );\r
+void LowLevelInitialisation(void);\r
+unsigned long __write(int fildes, const void *buf, unsigned long nbytes);\r
+\r
+/* Called from cstartup.s before the kernel is started. */\r
+void LowLevelInitialisation(void)\r
+{\r
+ /* Chip configuration functions from IAR. ********************************/\r
+ /* Disable MMU, enable ICache */\r
+ CP15_Mmu(FALSE);\r
+ CP15_ICache(FALSE);\r
+ CP15_SetVectorBase( (uint32_t )__section_begin( ".intvec" ) );\r
+\r
+ /* Set Low vectors mode in CP15 Control Register */\r
+ CP15_SetHighVectors(FALSE);\r
+\r
+\r
+ /* Chip and board specific configuration functions from Renesas. *********/\r
+ Peripheral_BasicInit();\r
+ STB_Init();\r
+ PORT_Init();\r
+ R_BSC_Init( ( uint8_t ) ( BSC_AREA_CS2 | BSC_AREA_CS3 ) );\r
+ R_INTC_Init();\r
+\r
+\r
+ CP15_ICache(TRUE);\r
+\r
+ /* Start with interrupts enabled. */\r
+ __enable_irq();\r
+ __enable_fiq();\r
+}\r
+\r
+/* Keep the linker happy. */\r
+unsigned long __write(int fildes, const void *buf, unsigned long nbytes)\r
+{\r
+ return 0;\r
+}\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>RAM Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>21</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>RAM Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>RAM Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>RAM Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>20</version>\r
+ <state>51</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>3</version>\r
+ <state>6</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>2</version>\r
+ <state>5</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No specifier a, A, no specifier n, no float nor long long.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>2</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>5.10.0.159</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>6.50.6.4952</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>R7S721000 Renesas R7S721000</state>\r
+ </option>\r
+ <option>\r
+ <name>GenLowLevelInterface</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianModeBE</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGBufferedTerminalOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenStdoutInterface</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>20</version>\r
+ <state>51</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>20</version>\r
+ <state>51</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>28</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCOptimizationNoSizeConstraints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state>NOR_DEBUG</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state>Pa082, Pe191</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>1</version>\r
+ <state>0000000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IEndianMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangConformance</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSignedPlainChar</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>$FILE_BNAME$.o</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIncludePath2</name>\r
+ <state>$PROJ_DIR$\board\</state>\r
+ <state>$PROJ_DIR$\modules\</state>\r
+ <state>$PROJ_DIR$\..\Source</state>\r
+ <state>$PROJ_DIR$\..\Source\Full-Demo</state>\r
+ <state>$PROJ_DIR$\..\Source\RenesasFiles\include</state>\r
+ <state>$PROJ_DIR$\..\Source\RenesasFiles\include\iodefines</state>\r
+ <state>$PROJ_DIR$\..\..\..\Source\include</state>\r
+ <state>$PROJ_DIR$\..\..\..\Source\portable\IAR\ARM_CA9</state>\r
+ <state>$PROJ_DIR$\..\..\Common\include</state>\r
+ <state>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\api</state>\r
+ <state>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCodeSection</name>\r
+ <state>.text</state>\r
+ </option>\r
+ <option>\r
+ <name>IInterwork2</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessorMode2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptStrategy</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevelSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRopi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRwpi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndNoDynInit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLang</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccAllowVLA</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccExceptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccRTTI</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccStaticDestr</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppInlineSemantics</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>AARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>8</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>AObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ACaseSensitivity</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacroChars</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnWhat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnOne</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ADebug</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AltRegisterNames</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ADefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AListHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AListing</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>Includes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacDefs</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExps</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExec</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OnlyAssed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MultiLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>TabSpacing</name>\r
+ <state>8</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDefines</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefInternal</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDual</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>AProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AOutputFile</name>\r
+ <state>$FILE_BNAME$.o</state>\r
+ </option>\r
+ <option>\r
+ <name>AMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsEdit</name>\r
+ <state>100</state>\r
+ </option>\r
+ <option>\r
+ <name>AIgnoreStdInclude</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AUserIncludes</name>\r
+ <state>$PROJ_DIR$\..\Source</state>\r
+ <state>$PROJ_DIR$\..\..\..\Source\portable\IAR\ARM_CA9</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsCheckV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsV2</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>OBJCOPY</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OOCOutputFormat</name>\r
+ <version>2</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCOutputOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCOutputFile</name>\r
+ <state>RTOSDemo.srec</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCCommandLineProducer</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCObjCopyEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CUSTOM</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ <settings>\r
+ <name>BUILDACTION</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <prebuild></prebuild>\r
+ <postbuild></postbuild>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>15</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>IlinkLibIOConfig</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XLinkMisraHandler</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkInputFileSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOutputFile</name>\r
+ <state>RTOSDemo.out</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkDebugInfoEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkKeepSymbols</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinaryFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinarySymbol</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinarySegment</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinaryAlign</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkConfigDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkMapFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogInitialization</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogModule</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogSection</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogVeneer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfOverride</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfFile</name>\r
+ <state>$PROJ_DIR$\r7s721000.icf</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfFileSlave</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkSuppressDiags</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsRem</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsWarn</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsErr</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkWarningsAreErrors</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkUseExtraOptions</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLowLevelInterfaceSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkAutoLibEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkAdditionalLibs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOverrideProgramEntryLabel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkProgramEntryLabelSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkProgramEntryLabel</name>\r
+ <state>__iar_program_start</state>\r
+ </option>\r
+ <option>\r
+ <name>DoFill</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerByte</name>\r
+ <state>0xFF</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerStart</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerEnd</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcSize</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcPoly</name>\r
+ <state>0x11021</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcCompl</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcBitOrder</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcInitialValue</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoCrc</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkBE8Slave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkBufferedTerminalOutput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStdoutInterfaceSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcFullSize</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIElfToolPostProcess</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogAutoLibSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogRedirSymbols</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogUnusedFragments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcReverseByteOrder</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcUseAsInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptInline</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsAllow</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsForce</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStackAnalysisEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStackControlFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStackCallGraphFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlgorithm</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcUnitSize</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARCHIVE</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>IarchiveInputs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOutput</name>\r
+ <state>###Unitialized###</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ </configuration>\r
+ <group>\r
+ <name>Blinky-Demo</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\Blinky-Demo\main_blinky.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>board</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\board\board.h</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>FreeRTOS-Source</name>\r
+ <group>\r
+ <name>include</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\include\FreeRTOS.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\include\list.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\include\mpu_wrappers.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\include\portable.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\include\projdefs.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\include\queue.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\include\semphr.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\include\StackMacros.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\include\task.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\include\timers.h</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>portable</name>\r
+ <group>\r
+ <name>IAR</name>\r
+ <group>\r
+ <name>ARM_CA9</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\portable\IAR\ARM_CA9\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\portable\IAR\ARM_CA9\portASM.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\portable\IAR\ARM_CA9\portASM.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\portable\IAR\ARM_CA9\portmacro.h</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+ <group>\r
+ <name>MemMang</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\portable\MemMang\heap_4.c</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\tasks.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Source\timers.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Full-Demo</name>\r
+ <group>\r
+ <name>Common-Demo-Source</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Common\Minimal\BlockQ.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Common\Minimal\blocktim.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Common\Minimal\comtest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Common\Minimal\countsem.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Common\Minimal\death.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Common\Minimal\dynamic.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Common\Minimal\flop.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Common\Minimal\GenQTest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Common\Minimal\recmutex.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Common\Minimal\semtest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Common\Minimal\TimerDemo.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>FreeRTOS-Plus-CLI</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>FreeRTOS-Plus-FAT-SL</name>\r
+ <group>\r
+ <name>API</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\api\api_mdriver.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\api\api_mdriver_ram.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\api\fat_sl.h</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Common</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\dir.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\drv.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\f_lock.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\fat.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\file.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\util.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\util_sfn.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\volume.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Media-Driver</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\media-drv\ram\ramdrv_f.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>rtc</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\psp\target\rtc\psp_rtc.c</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\Full-Demo\File-releated-CLI-commands.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\Full-Demo\File-system-demo.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\Full-Demo\main_full.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\Full-Demo\reg_test.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\Full-Demo\Sample-CLI-commands.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\Full-Demo\serial.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\Full-Demo\UARTCommandConsole.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>IAR-Files</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\modules\armv7a_cp15_drv.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Renesas-Files</name>\r
+ <group>\r
+ <name>include</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\RenesasFiles\include\iodefine.h</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Initialisation and Drivers</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\RenesasFiles\drivers\common\common_driver\bsc.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\RenesasFiles\drivers\common\userdef\bsc_userdef.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\RenesasFiles\drivers\intc\intc_driver\intc.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\RenesasFiles\drivers\intc\intc_driver\intc_handler.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\RenesasFiles\drivers\intc\userdef\intc_userdef.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\RenesasFiles\drivers\ostm\ostm_driver\ostm.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\RenesasFiles\board_settings\peripheral_init_basic.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\RenesasFiles\board_settings\port_init.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\RenesasFiles\drivers\scif_uart\scif_uart_driver\scif_uart.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\RenesasFiles\drivers\scif_uart\userdef\scif_uart_userdef.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\RenesasFiles\board_settings\siochar.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\RenesasFiles\board_settings\stb_init.c</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\cstartup.s</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\FreeRTOS_tick_config.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\FreeRTOSConfig.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\LEDs.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\LowLevelInitialise.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Source\main.c</name>\r
+ </file>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+ </project>\r
+ <batchBuild>\r
+ <batchDefinition>\r
+ <name>All</name>\r
+ <member>\r
+ <project>RTOSDemo</project>\r
+ <configuration>NOR Debug</configuration>\r
+ </member>\r
+ <member>\r
+ <project>RTOSDemo</project>\r
+ <configuration>RAM Debug</configuration>\r
+ </member>\r
+ <member>\r
+ <project>RTOSDemo</project>\r
+ <configuration>SerialFlash Debug</configuration>\r
+ </member>\r
+ <member>\r
+ <project>RTOSDemo</project>\r
+ <configuration>SerialFlash for Bootloader</configuration>\r
+ </member>\r
+ <member>\r
+ <project>Bootloader</project>\r
+ <configuration>SerialFlash Bootloader</configuration>\r
+ </member>\r
+ </batchDefinition>\r
+ </batchBuild>\r
+</workspace>\r
+\r
+\r
--- /dev/null
+/***************************************************************************\r
+ **\r
+ ** Common definition for IAR EW ARM\r
+ **\r
+ ** Used with ARM IAR C/C++ Compiler and Assembler.\r
+ **\r
+ ** (c) Copyright IAR Systems 2006\r
+ **\r
+ ** $Revision: 52705 $\r
+ **\r
+ ***************************************************************************/\r
+#include <intrinsics.h>\r
+\r
+#ifndef __ARM_COMM_DEF_H\r
+#define __ARM_COMM_DEF_H\r
+\r
+#define MHZ *1000000l\r
+#define KHZ *1000l\r
+#define HZ *1l\r
+\r
+#ifndef FALSE\r
+#define FALSE (1 == 0)\r
+#endif\r
+\r
+#ifndef TRUE\r
+#define TRUE (1 == 1)\r
+#endif\r
+\r
+#ifndef NULL\r
+#define NULL ((void*)0)\r
+#endif\r
+\r
+typedef double Flo64; // Double precision floating point\r
+typedef double * pFlo64;\r
+typedef float Flo32; // Single precision floating point\r
+typedef float * pFlo32;\r
+typedef signed long long Int64S; // Signed 64 bit quantity\r
+typedef signed long long * pInt64S;\r
+typedef unsigned long long Int64U; // Unsigned 64 bit quantity\r
+typedef unsigned long long * pInt64U;\r
+typedef signed int Int32S; // Signed 32 bit quantity\r
+typedef signed int * pInt32S;\r
+typedef unsigned int Int32U; // Unsigned 32 bit quantity\r
+typedef unsigned int * pInt32U;\r
+typedef signed short Int16S; // Signed 16 bit quantity\r
+typedef signed short * pInt16S;\r
+typedef unsigned short Int16U; // Unsigned 16 bit quantity\r
+typedef unsigned short * pInt16U;\r
+typedef signed char Int8S; // Signed 8 bit quantity\r
+typedef signed char * pInt8S;\r
+typedef unsigned char Int8U; // Unsigned 8 bit quantity\r
+typedef unsigned char * pInt8U;\r
+typedef unsigned int Boolean; // Boolean\r
+typedef unsigned int * pBoolean;\r
+\r
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))\r
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))\r
+#define _2BL(a) (Int8U)(a),(Int8U)(a>>8)\r
+#define _2BB(a) (Int8U)(a>>8),(Int8U)(a),\r
+#define _3BL(a) (Int8U)(a),(Int8U)(a>>8),(Int8U)(a>>16)\r
+#define _3BB(a) (Int8U)(a>>16),(Int8U)(a>>8),(Int8U)(a)\r
+#define _4BL(a) (Int8U)(a),(Int8U)(a>>8),(Int8U)(a>>16),(Int8U)(a>>24)\r
+#define _4BB(a) (Int8U)(a>>24),(Int8U)(a>>16),(Int8U)(a>>8),(Int8U)(a)\r
+\r
+typedef void * (*CommUserFpnt_t)(void *);\r
+typedef void (*VoidFpnt_t)(void);\r
+\r
+// Atomic exchange of data between a memory cell and a register\r
+// return value of the memory cell\r
+#if __CORE__ < 7\r
+inline __arm Int32U AtomicExchange (Int32U State, pInt32U Flag)\r
+{\r
+ asm("swp r0, r0, [r1]");\r
+ return(State);\r
+}\r
+\r
+#define IRQ_FLAG 0x80\r
+#define FIQ_FLAG 0x40\r
+\r
+inline __arm Int32U EntrCritSection(void)\r
+{\r
+unsigned long tmp;\r
+ tmp = __get_CPSR();\r
+ __set_CPSR(tmp | IRQ_FLAG);\r
+ return(tmp);\r
+}\r
+\r
+inline __arm void ExtCritSection(Int32U Save)\r
+{\r
+unsigned long tmp;\r
+ tmp = __get_CPSR();\r
+ __set_CPSR(tmp & (Save | ~IRQ_FLAG));\r
+}\r
+\r
+inline __arm Int32U EntrCritSectionFiq(void)\r
+{\r
+unsigned long tmp;\r
+ tmp = __get_CPSR();\r
+ __set_CPSR(tmp | (IRQ_FLAG | FIQ_FLAG));\r
+ return(tmp);\r
+}\r
+\r
+inline __arm void ExtCritSectionFiq(Int32U Save)\r
+{\r
+unsigned long tmp;\r
+ tmp = __get_CPSR();\r
+ __set_CPSR(tmp & (Save | ~(IRQ_FLAG | FIQ_FLAG)));\r
+}\r
+\r
+#define ENTR_CRT_SECTION(Save) Save = EntrCritSection()\r
+#define EXT_CRT_SECTION(Save) ExtCritSection(Save)\r
+\r
+#define ENTR_CRT_SECTION_F(Save) Save = EntrCritSectionFiq()\r
+#define EXT_CRT_SECTION_F(Save) ExtCritSectionFiq(Save)\r
+\r
+#elif __CORE__ == 7\r
+\r
+extern Int32U CriticalSecCntr;\r
+\r
+inline void EntrCritSection(void)\r
+{\r
+ if(CriticalSecCntr == 0)\r
+ {\r
+ asm("CPSID i");\r
+ }\r
+ // avoid lost of one count in case of simultaneously calling from both places\r
+ ++CriticalSecCntr;\r
+}\r
+\r
+inline void ExtCritSection(void)\r
+{\r
+ if(--CriticalSecCntr == 0)\r
+ {\r
+ asm("CPSIE i");\r
+ }\r
+}\r
+\r
+inline Int32U AtomicExchange (Int32U State, pInt32U Flag)\r
+{\r
+Int32U Hold;\r
+ EntrCritSection();\r
+ Hold = *Flag;\r
+ *Flag = State;\r
+ ExtCritSection();\r
+ return(Hold);\r
+}\r
+\r
+#define ENTR_CRT_SECTION() EntrCritSection()\r
+#define EXT_CRT_SECTION() ExtCritSection()\r
+#endif\r
+\r
+#define LongToBin(n) (((n >> 21) & 0x80) | \\r
+ ((n >> 18) & 0x40) | \\r
+ ((n >> 15) & 0x20) | \\r
+ ((n >> 12) & 0x10) | \\r
+ ((n >> 9) & 0x08) | \\r
+ ((n >> 6) & 0x04) | \\r
+ ((n >> 3) & 0x02) | \\r
+ ((n ) & 0x01))\r
+\r
+#define __BIN(n) LongToBin(0x##n##l)\r
+\r
+#define BIN8(n) __BIN(n)\r
+#define BIN(n) __BIN(n)\r
+#define BIN16(b1,b2) (( __BIN(b1) << 8UL) + \\r
+ __BIN(b2))\r
+#define BIN32(b1,b2,b3,b4) ((((Int32U)__BIN(b1)) << 24UL) + \\r
+ (((Int32U)__BIN(b2)) << 16UL) + \\r
+ (((Int32U)__BIN(b3)) << 8UL) + \\r
+ (Int32U)__BIN(b4))\r
+\r
+#endif // __ARM_COMM_DEF_H\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000040;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x07FFFFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20020000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x8000;\r
+define symbol __ICFEDIT_size_svcstack__ = 0x40;\r
+define symbol __ICFEDIT_size_irqstack__ = 0x40;\r
+define symbol __ICFEDIT_size_fiqstack__ = 0x40;\r
+define symbol __ICFEDIT_size_undstack__ = 0x40;\r
+define symbol __ICFEDIT_size_abtstack__ = 0x40;\r
+define symbol __ICFEDIT_size_heap__ = 0x8000;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF;\r
+\r
+define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60020000;\r
+define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF;\r
+\r
+define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000;\r
+define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF;\r
+\r
+define memory mem with size = 4G;\r
+\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__];\r
+define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__];\r
+define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };\r
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };\r
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };\r
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };\r
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+do not initialize { section MMU_TT };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite,\r
+ block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,\r
+ block UND_STACK, block ABT_STACK, block HEAP };\r
+\r
+place in RetRAM_region { section .retram };\r
+place in MirrorRAM_region { section .mirrorram };\r
+place in MirrorRetRAM_region { section .mirrorretram };\r
--- /dev/null
+setup()\r
+{\r
+__var Reg;\r
+\r
+ // Enable I Cache\r
+ // Disable MMU and enable ICache\r
+ Reg = __jtagCP15ReadReg(1, 0, 0, 0);\r
+ Reg &= 0xFFFFFFFA;\r
+ Reg |= 1<<12;\r
+ __jtagCP15WriteReg(1, 0, 0, 0, Reg);\r
+\r
+ __writeMemory16(0x0000FF41, 0xFCFE721C, "Memory"); // set PIPC7.6 direction controlled by alt.WE0\r
+ __writeMemory16(0x0000FF41, 0xFCFE341C, "Memory"); // set PMC7.6 to be alt.WE0\r
+\r
+ __writeMemory16(0x0000FFFF, 0xFCFE7220, "Memory"); // set PIPC8 direction controlled by alt.A8-A23\r
+ __writeMemory16(0x0000FFFF, 0xFCFE3420, "Memory"); // set PMC8 to be alt.A8-A23\r
+\r
+ __writeMemory16(0x00000003, 0xFCFE7224, "Memory"); // set PIPC9 direction controlled by alt.A24-A25\r
+ __writeMemory16(0x00000003, 0xFCFE3424, "Memory"); // set PMC9 to be alt.A24-A25\r
+\r
+ __writeMemory16(0x00000080, 0xFCFE720C, "Memory"); // set PIPC3 direction controlled by alt.CS1\r
+ __writeMemory16(0x00000080, 0xFCFE340C, "Memory"); // set PMC3 to be alt.CS1\r
+ __writeMemory16(0x00000080, 0xFCFE360C, "Memory"); // set PFCE3 to be alt.CS1\r
+ __writeMemory16(0x00000080, 0xFCFE3A0C, "Memory"); // set PFCAE3 to be alt.CS1\r
+}\r
+\r
+execUserPreload()\r
+{\r
+ __message "----- Prepare hardware for debug -----\n";\r
+ __hwReset(0);\r
+ setup();\r
+}
\ No newline at end of file
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x18000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x18000040;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x1807FFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20020000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x8000;\r
+define symbol __ICFEDIT_size_svcstack__ = 0x40;\r
+define symbol __ICFEDIT_size_irqstack__ = 0x40;\r
+define symbol __ICFEDIT_size_fiqstack__ = 0x40;\r
+define symbol __ICFEDIT_size_undstack__ = 0x40;\r
+define symbol __ICFEDIT_size_abtstack__ = 0x40;\r
+define symbol __ICFEDIT_size_heap__ = 0x8000;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF;\r
+\r
+define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60020000;\r
+define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF;\r
+\r
+define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000;\r
+define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF;\r
+\r
+define memory mem with size = 4G;\r
+\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__];\r
+define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__];\r
+define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };\r
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };\r
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };\r
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };\r
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+do not initialize { section MMU_TT };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite,\r
+ block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,\r
+ block UND_STACK, block ABT_STACK, block HEAP };\r
+\r
+place in RetRAM_region { section .retram };\r
+place in MirrorRAM_region { section .mirrorram };\r
+place in MirrorRetRAM_region { section .mirrorretram };\r
--- /dev/null
+setup()\r
+{\r
+__var Reg;\r
+\r
+ // Enable I Cache\r
+ // Disable MMU and enable ICache\r
+ Reg = __jtagCP15ReadReg(1, 0, 0, 0);\r
+ Reg &= 0xFFFFFFFA;\r
+ Reg |= 1<<12;\r
+ __jtagCP15WriteReg(1, 0, 0, 0, Reg);\r
+\r
+ //__writeMemory16(0x0035, 0xFCFE0010, "Memory"); // FRQCR\r
+ //__writeMemory16(0x0001, 0xFCFE0014, "Memory"); // FRQCR2\r
+\r
+ // Turn on clock for SPI\r
+ __writeMemory8(0x00, 0xFCFE0438, "Memory"); // PDM_STBCR9\r
+\r
+ // Configure PORTS for SPI (serial flash 1)\r
+ __writeMemory16(0x00FC, 0xFCFE7224, "Memory"); // PIPC9 2-7 -> alt IO mode\r
+ __writeMemory16(0x00FC, 0xFCFE3424, "Memory"); // PMC9 2-7 -> alt mode\r
+ __writeMemory16(0x00FC, 0xFCFE3524, "Memory"); // PFC9 2-7 -> alt mode\r
+\r
+ // Configure PORTS for SPI (serial flash 2)\r
+ __writeMemory16(0xF000, 0xFCFE7208, "Memory"); // PIPC2 12-15 -> alt IO mode\r
+ __writeMemory16(0xF000, 0xFCFE3408, "Memory"); // PMC2 12-15 -> alt mode\r
+ __writeMemory16(0xF000, 0xFCFE3508, "Memory"); // PFC2 12-15 -> alt mode\r
+ __writeMemory16(0xF000, 0xFCFE3608, "Memory"); // PFCE2 12-15 -> alt mode\r
+\r
+ // Configure SPI for EXTREAD mode\r
+ __writeMemory32(0x01AA4020, 0x3FEFA000, "Memory"); // SPIBSC_CMNCR 1-memory, CPHA=0, CPOL=0, SFDE=1\r
+\r
+ // Configure SPI registers\r
+ __writeMemory32(0x00130000, 0x3FEFA010, "Memory"); // SPIBSC_DRCMR CMD = 0x13\r
+ __writeMemory32(0x00004F00, 0x3FEFA01C, "Memory"); // SPIBSC_DRENR ADE = 0xF, CDE=1\r
+ __writeMemory32(0x00010101, 0x3FEFA00C, "Memory"); // SPIBSC_DRCR enable burst\r
+ __writeMemory32(0x00000001, 0x3FEFA014, "Memory"); // SPIBSC_DREAR enable extended address range\r
+\r
+ // Set Bit Rate\r
+ __writeMemory32(0x00000003, 0x3FEFA008, "Memory"); // SPIBSC_SPBCR SPBR=0, BRDV=3\r
+\r
+ // Flush Read Cache\r
+ Reg = __readMemory32(0x3FEFA00C, "Memory"); // Read SPIBSC_DRCR_0\r
+ Reg |= 0x00000200; // Set RCF bit\r
+ __writeMemory32(Reg, 0x3FEFA00C, "Memory"); // Set SPIBSC_DRCR_0\r
+}\r
+\r
+execUserPreload()\r
+{\r
+ __message "----- Prepare hardware for debug -----\n";\r
+ __hwReset(0);\r
+ setup();\r
+}\r
+\r
+execUserReset()\r
+{\r
+ setup();\r
+}\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x18080000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x18080040;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x1BFFFFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20020000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x8000;\r
+define symbol __ICFEDIT_size_svcstack__ = 0x40;\r
+define symbol __ICFEDIT_size_irqstack__ = 0x40;\r
+define symbol __ICFEDIT_size_fiqstack__ = 0x40;\r
+define symbol __ICFEDIT_size_undstack__ = 0x40;\r
+define symbol __ICFEDIT_size_abtstack__ = 0x40;\r
+define symbol __ICFEDIT_size_heap__ = 0x8000;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF;\r
+\r
+define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60020000;\r
+define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF;\r
+\r
+define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000;\r
+define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF;\r
+\r
+define memory mem with size = 4G;\r
+\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__];\r
+define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__];\r
+define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };\r
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };\r
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };\r
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };\r
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+do not initialize { section MMU_TT };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite,\r
+ block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,\r
+ block UND_STACK, block ABT_STACK, block HEAP };\r
+\r
+place in RetRAM_region { section .retram };\r
+place in MirrorRAM_region { section .mirrorram };\r
+place in MirrorRetRAM_region { section .mirrorretram };\r
--- /dev/null
+setup()\r
+{\r
+__var Reg;\r
+\r
+ // Enable I Cache\r
+ // Disable MMU and enable ICache\r
+ Reg = __jtagCP15ReadReg(1, 0, 0, 0);\r
+ Reg &= 0xFFFFFFFA;\r
+ Reg |= 1<<12;\r
+ __jtagCP15WriteReg(1, 0, 0, 0, Reg);\r
+\r
+ //__writeMemory16(0x0035, 0xFCFE0010, "Memory"); // FRQCR\r
+ //__writeMemory16(0x0001, 0xFCFE0014, "Memory"); // FRQCR2\r
+\r
+ // Turn on clock for SPI\r
+ __writeMemory8(0x00, 0xFCFE0438, "Memory"); // PDM_STBCR9\r
+\r
+ // Configure PORTS for SPI (serial flash 1)\r
+ __writeMemory16(0x00FC, 0xFCFE7224, "Memory"); // PIPC9 2-7 -> alt IO mode\r
+ __writeMemory16(0x00FC, 0xFCFE3424, "Memory"); // PMC9 2-7 -> alt mode\r
+ __writeMemory16(0x00FC, 0xFCFE3524, "Memory"); // PFC9 2-7 -> alt mode\r
+\r
+ // Configure PORTS for SPI (serial flash 2)\r
+ __writeMemory16(0xF000, 0xFCFE7208, "Memory"); // PIPC2 12-15 -> alt IO mode\r
+ __writeMemory16(0xF000, 0xFCFE3408, "Memory"); // PMC2 12-15 -> alt mode\r
+ __writeMemory16(0xF000, 0xFCFE3508, "Memory"); // PFC2 12-15 -> alt mode\r
+ __writeMemory16(0xF000, 0xFCFE3608, "Memory"); // PFCE2 12-15 -> alt mode\r
+\r
+ // Configure SPI for EXTREAD mode\r
+ __writeMemory32(0x01AA4021, 0x3FEFA000, "Memory"); // SPIBSC_CMNCR 2-memory, CPHAT=0, CPHAR=1, CPOL=0, SFDE=1\r
+\r
+ // Configure SPIBSC 32-bit addressing\r
+ __writeMemory32(0x00130000, 0x3FEFA010, "Memory"); // SPIBSC_DRCMR CMD = 0x13\r
+ __writeMemory32(0x00004F00, 0x3FEFA01C, "Memory"); // SPIBSC_DRENR ADE = 0xF, CDE=1\r
+ __writeMemory32(0x00010101, 0x3FEFA00C, "Memory"); // SPIBSC_DRCR enable burst\r
+ __writeMemory32(0x00000001, 0x3FEFA014, "Memory"); // SPIBSC_DREAR enable extended address range\r
+\r
+ // Set Bit Rate\r
+ __writeMemory32(0x00000003, 0x3FEFA008, "Memory"); // SPIBSC_SPBCR SPBR=0, BRDV=3\r
+\r
+ // Flush Read Cache\r
+ Reg = __readMemory32(0x3FEFA00C, "Memory"); // Read SPIBSC_DRCR\r
+ Reg |= 0x00000200; // Set RCF bit\r
+ __writeMemory32(Reg, 0x3FEFA00C, "Memory"); // Set SPIBSC_DRCR\r
+}\r
+\r
+execUserPreload()\r
+{\r
+ __message "----- Prepare hardware for debug -----\n";\r
+ __hwReset(0);\r
+ setup();\r
+}\r
+\r
+execUserReset()\r
+{\r
+ setup();\r
+}\r
--- /dev/null
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Part one of the system initialization code,\r
+;; contains low-level\r
+;; initialization.\r
+;;\r
+;; Copyright 2007 IAR Systems. All rights reserved.\r
+;;\r
+;; $Revision: 49919 $\r
+;;\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION IRQ_STACK:DATA:NOROOT(3)\r
+ SECTION FIQ_STACK:DATA:NOROOT(3)\r
+ SECTION SVC_STACK:DATA:NOROOT(3)\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+;\r
+; The module in this file are included in the libraries, and may be\r
+; replaced by any user-defined modules that define the PUBLIC symbol\r
+; __iar_program_start or a user defined start symbol.\r
+;\r
+; To override the cstartup defined in the library, simply add your\r
+; modified version to the workbench project.\r
+\r
+ SECTION .intvec:CODE:NOROOT(2)\r
+\r
+ PUBLIC __vector\r
+ PUBLIC __iar_program_start\r
+ EXTERN Undefined_Handler\r
+ EXTERN SWI_Handler\r
+ EXTERN Prefetch_Handler\r
+ EXTERN Abort_Handler\r
+ EXTERN IRQ_Handler\r
+ EXTERN FIQ_Handler\r
+ EXTERN LowLevelInitialisation\r
+\r
+ DATA\r
+\r
+__iar_init$$done: ; The vector table is not needed\r
+ ; until after copy initialization is done\r
+\r
+__vector: ; Make this a DATA label, so that stack usage\r
+ ; analysis doesn't consider it an uncalled fun\r
+\r
+ ARM\r
+\r
+ ; All default exception handlers (except reset) are\r
+ ; defined as weak symbol definitions.\r
+ ; If a handler is defined by the application it will take precedence.\r
+ LDR PC,Reset_Addr ; Reset\r
+ LDR PC,Undefined_Addr ; Undefined instructions\r
+ LDR PC,SWI_Addr ; Software interrupt (SWI/SVC)\r
+ LDR PC,Prefetch_Addr ; Prefetch abort\r
+ LDR PC,Abort_Addr ; Data abort\r
+ DCD 0 ; RESERVED\r
+ LDR PC,IRQ_Addr ; IRQ\r
+ LDR PC,FIQ_Addr ; FIQ\r
+\r
+ DATA\r
+\r
+Reset_Addr: DCD __iar_program_start\r
+Undefined_Addr: DCD Undefined_Handler\r
+SWI_Addr: DCD SWI_Handler\r
+Prefetch_Addr: DCD Prefetch_Handler\r
+Abort_Addr: DCD Abort_Handler\r
+IRQ_Addr: DCD IRQ_Handler\r
+FIQ_Addr: DCD FIQ_Handler\r
+\r
+\r
+; --------------------------------------------------\r
+; ?cstartup -- low-level system initialization code.\r
+;\r
+; After a reset execution starts here, the mode is ARM, supervisor\r
+; with interrupts disabled.\r
+;\r
+\r
+\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+\r
+ EXTERN __cmain\r
+ REQUIRE __vector\r
+ EXTWEAK __iar_init_core\r
+ EXTWEAK __iar_init_vfp\r
+\r
+\r
+ ARM\r
+\r
+__iar_program_start:\r
+?cstartup:\r
+\r
+;\r
+; Add initialization needed before setup of stackpointers here.\r
+;\r
+\r
+;\r
+; Initialize the stack pointers.\r
+; The pattern below can be used for any of the exception stacks:\r
+; FIQ, IRQ, SVC, ABT, UND, SYS.\r
+; The USR mode uses the same stack as SYS.\r
+; The stack segments must be defined in the linker command file,\r
+; and be declared above.\r
+;\r
+\r
+\r
+; --------------------\r
+; Mode, correspords to bits 0-5 in CPSR\r
+\r
+#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR\r
+\r
+#define USR_MODE 0x10 ; User mode\r
+#define FIQ_MODE 0x11 ; Fast Interrupt Request mode\r
+#define IRQ_MODE 0x12 ; Interrupt Request mode\r
+#define SVC_MODE 0x13 ; Supervisor mode\r
+#define ABT_MODE 0x17 ; Abort mode\r
+#define UND_MODE 0x1B ; Undefined Instruction mode\r
+#define SYS_MODE 0x1F ; System mode\r
+\r
+\r
+ MRS r0, cpsr ; Original PSR value\r
+\r
+ ;; Set up the interrupt stack pointer.\r
+\r
+ BIC r0, r0, #MODE_MSK ; Clear the mode bits\r
+ ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits\r
+ MSR cpsr_c, r0 ; Change the mode\r
+ LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK\r
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned\r
+\r
+ ;; Set up the fast interrupt stack pointer.\r
+\r
+ BIC r0, r0, #MODE_MSK ; Clear the mode bits\r
+ ORR r0, r0, #FIQ_MODE ; Set FIR mode bits\r
+ MSR cpsr_c, r0 ; Change the mode\r
+ LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK\r
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned\r
+\r
+ ;; Set up the normal SVC pointer.\r
+;; FreeRTOS Note:\r
+;; FreeRTOS does not need a System/User mode stack as only tasks run in\r
+;; System/User mode, and their stack is allocated when the task is created.\r
+;; Therefore the CSTACK allocated in the linker script is instead given to\r
+;; Supervisor mode, and main() is called from Supervisor mode.\r
+ BIC r0 ,r0, #MODE_MSK ; Clear the mode bits\r
+ ORR r0 ,r0, #SVC_MODE ; Set System mode bits\r
+ MSR cpsr_c, r0 ; Change the mode\r
+ LDR sp, =SFE(CSTACK) ; End of CSTACK\r
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned\r
+\r
+ ;; Turn on core features assumed to be enabled.\r
+ FUNCALL __iar_program_start, __iar_init_core\r
+ BL __iar_init_core\r
+\r
+ ;; Initialize VFP (if needed).\r
+ FUNCALL __iar_program_start, __iar_init_vfp\r
+ BL __iar_init_vfp\r
+\r
+ ;; Chip and board specific configuration\r
+ BL LowLevelInitialisation\r
+\r
+;;;\r
+;;; Add more initialization here\r
+;;;\r
+\r
+;;; Continue to __cmain for C-level initialization.\r
+\r
+ FUNCALL __iar_program_start, __cmain\r
+ B __cmain\r
+\r
+ END\r
--- /dev/null
+/*************************************************************************\r
+ *\r
+ * Used with ICCARM and AARM.\r
+ *\r
+ * (c) Copyright IAR Systems 2012\r
+ *\r
+ * File name : armv7a_cp15_drv.c\r
+ * Description : Driver for the CP15 of ARMv7-A\r
+ *\r
+ * History :\r
+ * 1. Date : September, 8 2006\r
+ * Author : Stanimir Bonev\r
+ * Description : Driver for the ARM926EJ's CP15\r
+ *\r
+ * 2. Date : October, 2008\r
+ * Author : Stoyan Choynev\r
+ * Description : Port for ARM1136JF. The driver is backwards compatible\r
+ * with ARMv5 or earlier processors.\r
+ *\r
+ * 3. Date : March, 2012\r
+ * Author : Atanas Uzunov\r
+ * Description : Port for ARMv7-A architecture.\r
+ * Added cache maintenance functions.\r
+ *\r
+ * $Revision: 52705 $\r
+ **************************************************************************/\r
+\r
+#include "armv7a_cp15_drv.h"\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetID\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returns the ID register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetID (void)\r
+{\r
+ return(__MRC(15,0,CP15_ID,0,0));\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetCacheType\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returns the Cache type\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetCacheType (void)\r
+{\r
+ return(__MRC(15,0,CP15_ID,0,1));\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetTCM_Status\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returns the TCM status\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetTCM_Status (void)\r
+{\r
+ return(__MRC(15,0,CP15_ID,0,2));\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetTtb0\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returns the TTB0 register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetTtb0 (void)\r
+{\r
+ return(__MRC(15,0,CP15_TTB_ADDR,0,0));\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetTtb1\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returns the TTB1 register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetTtb1 (void)\r
+{\r
+ return(__MRC(15,0,CP15_TTB_ADDR,0,1));\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetStatus\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returns the MMU control register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetStatus (void)\r
+{\r
+ return(__MRC(15,0,CP15_CTRL,0,0));\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetDomain\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returns the MMU domain access register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetDomain (void)\r
+{\r
+ return(__MRC(15,0,CP15_DA_CTRL,0,0));\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetDomains\r
+ * Parameters: Int32U DomainAccess\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function set the MMU domain access register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetDomains (Int32U DomainAccess)\r
+{\r
+register Int32U Val = DomainAccess;\r
+ __MCR(15,0,Val,CP15_DA_CTRL,0,0);\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: log2_n_up\r
+ * Parameters: Int32U n\r
+ *\r
+ * Return: Int32S\r
+ *\r
+ * Description: Logarithm at base 2 , rounded up\r
+ *\r
+ *************************************************************************/\r
+Int32S log2_up(Int32U n)\r
+{\r
+ Int32S log = -1;\r
+ Int32U t = n;\r
+ while(t)\r
+ {\r
+ log++; t >>=1;\r
+ }\r
+ /* if n not power of 2 -> round up*/\r
+ if ( n & (n - 1) ) log++;\r
+ return log;\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_MaintainDCacheSetWay\r
+ * Parameters: Int32U level - level of cache, \r
+ * Int32U maint - maintenance type\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Maintain data cache line by Set/Way\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_MaintainDCacheSetWay(Int32U level, Int32U maint)\r
+{\r
+register volatile Int32U Dummy;\r
+register volatile Int32U ccsidr;\r
+Int32U num_sets;\r
+Int32U num_ways;\r
+Int32U shift_way;\r
+Int32U log2_linesize;\r
+Int32U log2_num_ways;\r
+\r
+ Dummy = level << 1;\r
+ /* set csselr, select ccsidr register */\r
+ __MCR(15,2,Dummy,0,0,0);\r
+ /* get current ccsidr register */\r
+ ccsidr = __MRC(15,1,0,0,0);\r
+ num_sets = ((ccsidr & 0x0FFFE000) >> 13) + 1;\r
+ num_ways = ((ccsidr & 0x00001FF8) >> 3) + 1;\r
+ log2_linesize = (ccsidr & 0x00000007) + 2 + 2;\r
+ log2_num_ways = log2_up(num_ways);\r
+ shift_way = 32 - log2_num_ways;\r
+ for(int way = num_ways-1; way >= 0; way--)\r
+ for(int set = num_sets-1; set >= 0; set--)\r
+ {\r
+ Dummy = (level << 1) | (set << log2_linesize) | (way << shift_way);\r
+ switch (maint)\r
+ {\r
+ case DCACHE_CLEAN_AND_INVALIDATE:\r
+ __MCR(15,0,Dummy,7,14,2);\r
+ break;\r
+ \r
+ case DCACHE_INVALIDATE:\r
+ __MCR(15,0,Dummy,7,6,2);\r
+ break;\r
+ }\r
+ }\r
+ __DMB();\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_MaintAllDCache\r
+ * Parameters: Int32U oper - type of maintenance, one of:\r
+ * DCACHE_CLEAN_AND_INVALIDATE\r
+ * DCACHE_INVALIDATE\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Maintenance of all data cache\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_MaintainAllDCache(Int32U oper)\r
+{\r
+register volatile Int32U clidr; \r
+Int32U cache_type;\r
+ clidr = __MRC(15,1,0,0,1);\r
+ for(Int32U i = 0; i<7; i++)\r
+ {\r
+ cache_type = (clidr >> i*3) & 0x7UL;\r
+ if ((cache_type >= 2) && (cache_type <= 4))\r
+ {\r
+ CP15_MaintainDCacheSetWay(i,oper);\r
+ }\r
+ }\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_InvalInstrCache\r
+ * Parameters: none\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Invalidate instruction cache\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_InvalInstrCache(void)\r
+{\r
+register volatile Int32U Dummy;\r
+ __MCR(15,0,Dummy,CP15_CACHE_OPR,5,0);\r
+ CP15_InvalPredictArray();\r
+ __DSB();\r
+ __ISB();\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_InvalPredictArray\r
+ * Parameters: none\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Invalidate prediction array\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_InvalPredictArray(void)\r
+{\r
+register volatile Int32U Dummy;\r
+ __MCR(15,0,Dummy,CP15_CACHE_OPR,5,6); __ISB();\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_InvalAllTbl\r
+ * Parameters: none\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Invalidate TLB\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_InvalAllTbl (void)\r
+{\r
+register volatile Int32U Dummy;\r
+ /* Invalidate entire unified TLB*/\r
+ __MCR(15,0,Dummy,CP15_TBL_OPR,7,0);\r
+ /* Invalidate entire data TLB*/\r
+ __MCR(15,0,Dummy,CP15_TBL_OPR,6,0);\r
+ /* Invalidate entire instruction TLB*/\r
+ __MCR(15,0,Dummy,CP15_TBL_OPR,5,0);\r
+ __DSB();\r
+ __ISB();\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetStatus\r
+ * Parameters: Int32U Ctrl\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Set CP15 CTR (control) register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetStatus (Int32U Ctrl)\r
+{\r
+register volatile Int32U Val = Ctrl;\r
+ __MCR(15,0,Val,CP15_CTRL,0,0);\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetTtb0\r
+ * Parameters: pInt32U pTtb\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Set CP15 TTB0 base address register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetTtb0 (pInt32U pTtb)\r
+{\r
+register volatile Int32U Val = (Int32U)pTtb;\r
+ __MCR(15,0,Val,CP15_TTB_ADDR,0,0);\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetTtb1\r
+ * Parameters: pInt32U pTtb\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Set CP15 TTB1 base address register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetTtb1 (pInt32U pTtb)\r
+{\r
+register volatile Int32U Val = (Int32U)pTtb;\r
+ __MCR(15,0,Val,CP15_TTB_ADDR,0,1);\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetDac\r
+ * Parameters: Int32U da\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Set CP15 domain access register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetDac (Int32U da)\r
+{\r
+register volatile Int32U Val = da;\r
+ __MCR(15,0,Val,CP15_DA_CTRL,0,0);\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_WriteBuffFlush\r
+ * Parameters: none\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Flush the write buffer and wait for completion\r
+ * of the flush.\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_WriteBuffFlush (void)\r
+{\r
+register volatile Int32U Val;\r
+ __MCR(15,0,Val,CP15_CACHE_OPR,10,4);\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetFaultStat\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returns the MMU fault status register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetFaultStat (void)\r
+{\r
+ return(__MRC(15,0,CP15_FAULT_STAT,0,0));\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetFaultAddr\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returns the MMU fault address register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetFaultAddr (void)\r
+{\r
+ return(__MRC(15,0,CP15_FAULT_ADDR,0,0));\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetFcsePid\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returns the MMU Process identifier\r
+ * FCSE PID register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetFcsePid (void)\r
+{\r
+ return(__MRC(15,0,CP15_PROCESS_IDNF,0,0));\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetPraceProcId\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returns the MMU Trace Process identifier\r
+ * register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetPraceProcId (void)\r
+{\r
+ return(__MRC(15,0,CP15_PROCESS_IDNF,0,1));\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetFcsePid\r
+ * Parameters: Int32U FcsePid\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Function set the MMU Process identifier\r
+ * FCSE PID register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetFcsePid (Int32U FcsePid)\r
+{\r
+register Int32U Val = FcsePid;\r
+ __MCR(15,0,Val,CP15_PROCESS_IDNF,0,0);\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetPraceProcId\r
+ * Parameters: Int32U\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Function set the MMU Trace Process identifier\r
+ * register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetPraceProcId(Int32U Trace)\r
+{\r
+register Int32U Val = Trace;\r
+ __MCR(15,0,Val,CP15_PROCESS_IDNF,0,1);\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_InitMmuTtb\r
+ * Parameters: pTtSectionBlock_t pTtSB, pTtTableBlock_t pTtTB\r
+ *\r
+ * Return: Boolean\r
+ *\r
+ * Returns error if MMU is enabled or if target\r
+ * Translation Table address is not 16K aligned. Clear the\r
+ * Translation Table area. Build the Translation Table from the\r
+ * initialization data in the Section Block array. Return no error.\r
+ *\r
+ * Description: Initializes the MMU tables.\r
+ *\r
+ *\r
+ *************************************************************************/\r
+Boolean CP15_InitMmuTtb(const TtSectionBlock_t * pTtSB,\r
+ const TtTableBlock_t * pTtTB)\r
+{\r
+Int32U i, pa, pa_inc, va_ind;\r
+pInt32U pTtb;\r
+TableType_t TableType;\r
+ while(1)\r
+ {\r
+ TableType = pTtTB->TableType;\r
+ switch(TableType)\r
+ {\r
+ case TableL1:\r
+ pTtb = pTtTB->TableAddr;\r
+ if((Int32U)pTtb & L1_ENTRIES_NUMB-1)\r
+ {\r
+ return(FALSE);\r
+ }\r
+ pa_inc = 0x100000;\r
+ pa = L1_ENTRIES_NUMB;\r
+ break;\r
+ case TableL2_PageTable:\r
+ pTtb = pTtTB->TableAddr;\r
+ if((Int32U)pTtb & L2_CP_ENTRIES_NUMB-1)\r
+ {\r
+ return(FALSE);\r
+ }\r
+ pa_inc = 0x1000;\r
+ pa = L2_CP_ENTRIES_NUMB;\r
+ break;\r
+ default:\r
+ return(TRUE);\r
+ }\r
+\r
+ // Clear the entire Translation Table This results in LxD_TYPE_FAULT\r
+ // being the default for any uninitialized entries.\r
+ for(i = 0; i < pa; ++i)\r
+ {\r
+ *(pTtb+i) = TT_ENTRY_INVALID;\r
+ }\r
+\r
+ // Build the translation table from user provided pTtSectionBlock_t array\r
+ while(pTtSB->NubrOfSections != 0)\r
+ {\r
+Int32U Entrys = pTtSB->NubrOfSections;\r
+Int32U Data = pTtSB->Entry.Data; \r
+ pa = pTtSB->PhysAddr;\r
+ \r
+ switch(TableType)\r
+ {\r
+ case TableL1:\r
+ va_ind = (pTtSB->VirtAddr >> 20) & (L1_ENTRIES_NUMB-1);\r
+ \r
+ if((va_ind + Entrys) > L1_ENTRIES_NUMB)\r
+ {\r
+ return(FALSE);\r
+ }\r
+ break;\r
+ case TableL2_PageTable:\r
+ va_ind = (pTtSB->VirtAddr >> 12) & (L2_CP_ENTRIES_NUMB-1);\r
+ if((va_ind + Entrys) > L2_CP_ENTRIES_NUMB)\r
+ {\r
+ return(FALSE);\r
+ }\r
+ break;\r
+ }\r
+ for(i = 0; i < Entrys; ++i, ++va_ind)\r
+ {\r
+ switch(TableType)\r
+ {\r
+ case TableL1:\r
+ switch(pTtSB->Entry.Type)\r
+ {\r
+ case TtL1PageTable:\r
+ *(pTtb+va_ind) |= Data | (pa & TTL1_PT_PADDR_MASK);\r
+ break;\r
+ case TtL1Section:\r
+ *(pTtb+va_ind) |= Data | (pa & TTL1_SECTION_PADDR_MASK);\r
+ break;\r
+ case TtL1SuperSection:\r
+ *(pTtb+va_ind) |= Data | (pa & TTL1_S_SECTION_PADDR_MASK);\r
+ break;\r
+ default:\r
+ return(FALSE);\r
+ }\r
+ break;\r
+ case TableL2_PageTable:\r
+ switch(pTtSB->Entry.Type)\r
+ {\r
+ case TtL2LargePage:\r
+ *(pTtb+va_ind) |= Data | (pa & TTL2_LP_PADDR_MASK);\r
+ break;\r
+ case TtL2SmallPage:\r
+ *(pTtb+va_ind) |= Data | (pa & TTL2_SP_PADDR_MASK);\r
+ break;\r
+ default:\r
+ return(FALSE);\r
+ }\r
+ break;\r
+ }\r
+ pa += pa_inc;\r
+ }\r
+ ++pTtSB;\r
+ }\r
+ ++pTtSB;\r
+ ++pTtTB;\r
+ }\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_Mmu\r
+ * Parameters: Boolean Enable\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Enable/Disable MMU\r
+ *\r
+ *************************************************************************/\r
+void CP15_Mmu(Boolean Enable)\r
+{\r
+Int32U Val = CP15_GetStatus();\r
+ if(Enable)\r
+ {\r
+ CP15_InvalAllTbl();\r
+ Val |= CP15_CTRL_M;\r
+ }\r
+ else\r
+ {\r
+ Val &= ~(CP15_CTRL_M | CP15_CTRL_C);\r
+ } \r
+ CP15_SetStatus(Val);\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_Cache\r
+ * Parameters: Boolean Enable\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Enable/Disable Both Cache\r
+ *\r
+ *************************************************************************/\r
+void CP15_Cache(Boolean Enable)\r
+{\r
+Int32U Val = CP15_GetStatus();\r
+ if(Enable)\r
+ { \r
+ Val |= CP15_CTRL_M | CP15_CTRL_C | CP15_CTRL_I;\r
+ }\r
+ else\r
+ {\r
+ Val &= ~CP15_CTRL_C;\r
+ }\r
+ CP15_SetStatus(Val); \r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_InvalidateCache\r
+ * Parameters: Boolean Enable\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Invalidate Cache\r
+ *\r
+ *************************************************************************/\r
+void CP15_InvalidateCache()\r
+{\r
+ CP15_MaintainAllDCache(DCACHE_INVALIDATE);\r
+ __DSB();\r
+ CP15_InvalInstrCache(); /* includes invalidation of branch predictor */\r
+ __DSB();\r
+ __ISB();\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_ICache\r
+ * Parameters: Boolean Enable\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Enable/Disable I cache\r
+ *\r
+ *************************************************************************/\r
+void CP15_ICache (Boolean Enable)\r
+{\r
+Int32U Val = CP15_GetStatus();\r
+ if(Enable)\r
+ {\r
+ Val |= CP15_CTRL_I;\r
+ }\r
+ else\r
+ {\r
+ Val &= ~CP15_CTRL_I;\r
+ }\r
+ CP15_SetStatus(Val);\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_DCache\r
+ * Parameters: Boolean Enable\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Enable/Disable D cache\r
+ *\r
+ *************************************************************************/\r
+void CP15_DCache (Boolean Enable)\r
+{\r
+Int32U Val = CP15_GetStatus();\r
+ if(Enable)\r
+ {\r
+ Val |= CP15_CTRL_M | CP15_CTRL_C;\r
+ }\r
+ else\r
+ {\r
+ Val &= ~CP15_CTRL_C;\r
+ }\r
+ CP15_SetStatus(Val);\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_ProgFlowPrediction\r
+ * Parameters: Boolean Enable\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Enable/Disable program flow prediction.\r
+ *\r
+ *************************************************************************/\r
+void CP15_ProgFlowPrediction (Boolean Enable)\r
+{\r
+Int32U Val = CP15_GetStatus();\r
+ if(Enable)\r
+ {\r
+ CP15_InvalPredictArray();\r
+ Val |= CP15_CTRL_Z;\r
+ }\r
+ else\r
+ {\r
+ Val &= ~CP15_CTRL_Z;\r
+ }\r
+ CP15_SetStatus(Val);\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetVectorBase\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Get Vector Base Register (VBAR)\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetVectorBase(void)\r
+{\r
+ return(__MRC(15,0,CP15_VBAR,0,0));\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetVectorBase\r
+ * Parameters: Int32U\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Set Vector Base Register (VBAR)\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetVectorBase(Int32U vector)\r
+{\r
+register volatile Int32U Val = vector;\r
+ __MCR(15,0,Val,CP15_VBAR,0,0);\r
+}\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetHighVectors\r
+ * Parameters: Boolean\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Select High or Low vectors base in CP15 control register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetHighVectors(Boolean Enable)\r
+{\r
+Int32U Val = CP15_GetStatus();\r
+ if(Enable)\r
+ {\r
+ Val |= CP15_CTRL_V;\r
+ }\r
+ else\r
+ {\r
+ Val &= ~CP15_CTRL_V;\r
+ }\r
+ CP15_SetStatus(Val);\r
+}\r
--- /dev/null
+/*************************************************************************\r
+ *\r
+ * Used with ICCARM and AARM.\r
+ *\r
+ * (c) Copyright IAR Systems 2012\r
+ *\r
+ * File name : armv7a_cp15_drv.h\r
+ * Description : Definitions of a driver for the CP15 of ARMv7-A\r
+ *\r
+ * History :\r
+ * 1. Date : September, 8 2006\r
+ * Author : Stanimir Bonev\r
+ * Description : Create\r
+ *\r
+ * 2. Date : October, 2008\r
+ * Author : Stoyan Choynev\r
+ * Description : Port for ARM1136JF. The driver is backwards compatible with ARMv5 or earlier\r
+ * processors\r
+ *\r
+ * 3. Date : March, 2012\r
+ * Author : Atanas Uzunov\r
+ * Description : Port for ARMv7-A architecture.\r
+ * Added cache maintenance functions.\r
+ *\r
+ * $Revision: 52705 $\r
+ **************************************************************************/\r
+#include <intrinsics.h>\r
+#include "arm_comm.h"\r
+\r
+#ifndef __ARMV7A_CP15_DRV_H\r
+#define __ARMV7A_CP15_DRV_H\r
+\r
+#define NON_CACHABLE_ADDR 0xFFFFFFFC\r
+\r
+#define L1_ENTRIES_NUMB 4096\r
+#define L2_CP_ENTRIES_NUMB 256\r
+\r
+#define DCACHE_CLEAN_AND_INVALIDATE 1\r
+#define DCACHE_INVALIDATE 2\r
+\r
+#define TSB_INVALID { 0, 0, 0, 0 }\r
+#define TTB_INVALID { 0, TableInvalid }\r
+\r
+#define L1_PAGE_TABLE_ENTRY(Numb, VirtAddr ,PhAddr, Domain, NS) \\r
+ { Numb, VirtAddr, PhAddr, \\r
+ ((Domain << 5) | (NS << 3) | \\r
+ TtL1PageTable)}\r
+\r
+#define L1_SECTION_ENTRY(Numb, VirtAddr ,PhAddr, NS, nG, S, AP2, TEX, AP01, Domain, XN, C, B) \\r
+ { Numb, VirtAddr, PhAddr, \\r
+ ((NS << 19) | (nG << 17) | (S << 16) | (AP2 << 15) | (TEX << 12) | (AP01 << 10) | (Domain << 5) | (XN << 4) | (C << 3) | (B << 2) | \\r
+ TtL1Section)}\r
+\r
+#define L1_SUPERSECTION_ENTRY(Numb, VirtAddr, PhAddr, ExtBaseAddr, NS, nG, S, AP2, TEX, AP01, Domain, XN, C, B) \\r
+ { Numb*16, VirtAddr, PhAddr, \\r
+ (((ExtBaseAddr&0x0FUL) << 20) | (((ExtBaseAddr&0xF0UL)>>4) << 5) | (NS << 19) | (nG << 17) | (S << 16) | (AP2 << 15) | (TEX << 12) | (AP01 << 10) | (Domain << 5) | (XN << 4) | (C << 3) | (B << 2) | \\r
+ TtL1SuperSection)}\r
+\r
+#define L2_LARGE_PAGE_ENTRY(Numb, VirtAddr ,PhAddr, XN, TEX, nG, S, AP2, AP01, C, B) \\r
+ { Numb*16, VirtAddr, PhAddr, \\r
+ ((XN << 15) | (TEX << 12) | (nG << 11) | (S << 10) | (AP2 << 9) | (AP01 << 4) | (C << 3) | (B << 2) | \\r
+ TtL2LargePage)}\r
+\r
+#define L2_SMALL_PAGE_ENTRY(Numb, VirtAddr ,PhAddr, XN, TEX, nG, S, AP2, AP01, C, B) \\r
+ { Numb, VirtAddr, PhAddr, \\r
+ ((nG << 11) | (S << 10) | (AP2 << 9) | (TEX<<6) | (AP01 << 4) | (C << 3) | (B << 2) | (XN << 0) | \\r
+ TtL2SmallPage)}\r
+\r
+// CP15 Registers\r
+// ID register\r
+#define CP15_ID 0\r
+\r
+// Control register\r
+#define CP15_CTRL 1\r
+// CP15 Control register bits\r
+#define CP15_CTRL_M (1UL << 0) // MMU enable/disable\r
+#define CP15_CTRL_A (1UL << 1) // Alignment fault enable/disable\r
+#define CP15_CTRL_C (1UL << 2) // DCache enable/disable\r
+#define CP15_CTRL_Z (1UL << 11) // Program flow prediction\r
+#define CP15_CTRL_I (1UL << 12) // ICache enable/disable\r
+#define CP15_CTRL_V (1UL << 13) // Location of exception vectors\r
+#define CP15_CTRL_EE (1UL << 25) // CPSR E bit on exception\r
+#define CP15_CTRL_NMFI (1UL << 27) // FIQ enable bit (1 - FIQ cannot be masked) READ-ONLY\r
+#define CP15_CTRL_TRE (1UL << 28) // TEX remap functionality bit. (TEX enabled/disabled)\r
+#define CP15_CTRL_AFE (1UL << 29) // Access Flag Enable bit.\r
+#define CP15_CTRL_TE (1UL << 30) // Thumb Exception enable bit.\r
+\r
+// Translation table base address (alignment 4KB)\r
+#define CP15_TTB_ADDR 2\r
+\r
+// Domain access control register\r
+#define CP15_DA_CTRL 3\r
+\r
+#define CP15_DA_CTRL_D0(Val) ((Val & 0x3) << 0)\r
+#define CP15_DA_CTRL_D1(Val) ((Val & 0x3) << 2)\r
+#define CP15_DA_CTRL_D2(Val) ((Val & 0x3) << 4)\r
+#define CP15_DA_CTRL_D3(Val) ((Val & 0x3) << 6)\r
+#define CP15_DA_CTRL_D4(Val) ((Val & 0x3) << 8)\r
+#define CP15_DA_CTRL_D5(Val) ((Val & 0x3) << 10)\r
+#define CP15_DA_CTRL_D6(Val) ((Val & 0x3) << 12)\r
+#define CP15_DA_CTRL_D7(Val) ((Val & 0x3) << 14)\r
+#define CP15_DA_CTRL_D8(Val) ((Val & 0x3) << 16)\r
+#define CP15_DA_CTRL_D9(Val) ((Val & 0x3) << 18)\r
+#define CP15_DA_CTRL_D10(Val) ((Val & 0x3) << 20)\r
+#define CP15_DA_CTRL_D11(Val) ((Val & 0x3) << 22)\r
+#define CP15_DA_CTRL_D12(Val) ((Val & 0x3) << 24)\r
+#define CP15_DA_CTRL_D13(Val) ((Val & 0x3) << 25)\r
+#define CP15_DA_CTRL_D14(Val) ((Val & 0x3) << 28)\r
+#define CP15_DA_CTRL_D15(Val) ((Val & 0x3) << 30)\r
+\r
+// CP15 fault status register\r
+#define CP15_FAULT_STAT 5\r
+\r
+// CP15 fault address register\r
+#define CP15_FAULT_ADDR 6\r
+\r
+// CP15 Cache operations\r
+#define CP15_CACHE_OPR 7\r
+\r
+// CP15 TLB operation\r
+#define CP15_TBL_OPR 8\r
+\r
+// CP15 Cache lockdown\r
+#define CP15_C_LD 9\r
+\r
+// CP15 TBL lockdown\r
+#define CP15_TBL_LD 10\r
+\r
+// CP15 VBAR\r
+#define CP15_VBAR 12\r
+\r
+// CP15 Process identifier register\r
+#define CP15_PROCESS_IDNF 13\r
+\r
+// CP15 Test\r
+#define CP15_TEST 15\r
+\r
+typedef enum {\r
+ DomainNoAccess = 0, DomainClient, DomainManager = 3,\r
+} MmuDomainType_t;\r
+\r
+typedef enum\r
+{\r
+ TtL1Invalid = 0, TtL1PageTable, TtL1Section, TtL1SuperSection = 0x40002,\r
+} TtL1EntryType_t;\r
+\r
+typedef enum\r
+{\r
+ TtL2Invalid = 0, TtL2LargePage, TtL2SmallPage,\r
+} TtL2EntryType_t;\r
+\r
+typedef enum\r
+{\r
+ TableInvalid = 0, TableL1, TableL2_PageTable,\r
+} TableType_t;\r
+\r
+typedef enum\r
+{\r
+ PC15_FASTBUS_MODE = 0, PC15_SYNC_MODE, PC15_ASYNC_MODE = 3\r
+} ClkMode_t;\r
+\r
+\r
+typedef union _TtEntry_t\r
+{\r
+ Int32U Data;\r
+ struct\r
+ {\r
+ Int32U Type : 2;\r
+ Int32U : 3;\r
+ Int32U Domain : 4;\r
+ Int32U :23;\r
+ };\r
+} TtEntry_t, *pTtEntry_t;\r
+\r
+typedef struct _TtSectionBlock_t\r
+{\r
+ Int32U NubrOfSections;\r
+ Int32U VirtAddr;\r
+ Int32U PhysAddr;\r
+ TtEntry_t Entry;\r
+} TtSectionBlock_t, * pTtSectionBlock_t;\r
+\r
+typedef struct _TtTableBlock_t\r
+{\r
+ pInt32U TableAddr;\r
+ TableType_t TableType;\r
+} TtTableBlock_t, * pTtTableBlock_t;\r
+\r
+#define TT_ENTRY_INVALID 0\r
+\r
+#define TTL1_SECTION_PADDR_MASK 0xFFF00000\r
+#define TTL1_S_SECTION_PADDR_MASK 0xFF000000\r
+#define TTL1_S_SECTION_EXT35_32_PADDR_MASK 0x00F00000\r
+#define TTL1_S_SECTION_EXT39_36_PADDR_MASK 0x000001E0\r
+#define TTL1_PT_PADDR_MASK 0xFFFFFC00\r
+\r
+#define TTL2_LP_PADDR_MASK 0xFFFF0000\r
+#define TTL2_SP_PADDR_MASK 0xFFFFF000\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetTtb0\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returning the TTB0 register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetTtb0 (void);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetTtb1\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returning the TTB1 register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetTtb1 (void);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetStatus\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returning the MMU control register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetStatus (void);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetDomain\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returning the MMU domain access register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetDomain (void);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetDomains\r
+ * Parameters: Int32U DomainAccess\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function set the MMU domain access register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetDomains (Int32U DomainAccess);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_MaintainDCacheSetWay\r
+ * Parameters: Int32U level - level of cache,\r
+ * Int32U maint - maintenance type\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Maintain data cache line by Set/Way\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_MaintainDCacheSetWay(Int32U level, Int32U maint);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_MaintAllDCache\r
+ * Parameters: Int32U oper - type of maintenance, one of:\r
+ * DCACHE_CLEAN_AND_INVALIDATE\r
+ * DCACHE_INVALIDATE\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Maintenance of all data cache\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_MaintainAllDCache(Int32U oper);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_InvalInstrCache\r
+ * Parameters: none\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Invalidate instruction cache\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_InvalInstrCache(void);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_InvalPredictArray\r
+ * Parameters: none\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Invalidate prediction array\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_InvalPredictArray(void);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_InvalAllTbl\r
+ * Parameters: none\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Invalidate TLB\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_InvalAllTbl (void);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetStatus\r
+ * Parameters: Int32U Ctrl\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Set CP15 CTR (control) register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetStatus (Int32U Ctrl);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetMmu\r
+ * Parameters: Int32U Ctrl\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Set CP15 control register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetMmu (Int32U Ctrl);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetTtb0\r
+ * Parameters: pInt32U pTtb\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Set CP15 TTB0 base address register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetTtb0 (pInt32U pTtb);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetTtb1\r
+ * Parameters: pInt32U pTtb\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Set CP15 TTB1 base address register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetTtb1 (pInt32U pTtb);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetDac\r
+ * Parameters: Int32U da\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Set CP15 domain access register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetDac (Int32U da);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_WriteBuffFlush\r
+ * Parameters: none\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Flush the write buffer and wait for completion\r
+ * of the flush.\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_WriteBuffFlush (void);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetFaultStat\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returning the MMU fault status register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetFaultStat (void);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetFaultAddr\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returning the MMU fault address register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetFaultAddr (void);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetFcsePid\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returning the MMU Process identifier\r
+ * FCSE PID register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetFcsePid (void);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetPraceProcId\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Function returning the MMU Trace Process identifier\r
+ * register\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetPraceProcId (void);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetFcsePid\r
+ * Parameters: Int32U FcsePid\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Function set the MMU Process identifier\r
+ * FCSE PID register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetFcsePid (Int32U FcsePid);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetPraceProcId\r
+ * Parameters: Int32U\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Function set the MMU Trace Process identifier\r
+ * register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetPraceProcId (Int32U Trace);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_WriteBuffFlush\r
+ * Parameters: pTtSectionBlock_t pTtSB, pTtTableBlock_t pTtTB\r
+ *\r
+ * Return: Boolean\r
+ *\r
+ * Return error if MMU is enabled. Return error if target\r
+ * Translation Table address is not 16K aligned. Clear the\r
+ * Translation Table area. Build the Translation Table from the\r
+ * initialization data in the Section Block array. Return no error.\r
+ *\r
+ * Description: Initializes the MMU tables.\r
+ *\r
+ *\r
+ *************************************************************************/\r
+Boolean CP15_InitMmuTtb(const TtSectionBlock_t * pTtSB,\r
+ const TtTableBlock_t * pTtTB);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_Mmu\r
+ * Parameters: Boolean Enable\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Enable/Disable MMU\r
+ *\r
+ *************************************************************************/\r
+void CP15_Mmu (Boolean Enable);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_Cache\r
+ * Parameters: Boolean Enable\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Enable/Disable Cache\r
+ *\r
+ *************************************************************************/\r
+void CP15_Cache (Boolean Enable);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_InvalidateCache\r
+ * Parameters: Boolean Enable\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Invalidate Cache\r
+ *\r
+ *************************************************************************/\r
+void CP15_InvalidateCache();\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_ICache\r
+ * Parameters: Boolean Enable\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Enable/Disable I cache\r
+ *\r
+ *************************************************************************/\r
+void CP15_ICache (Boolean Enable);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_DCache\r
+ * Parameters: Boolean Enable\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Enable/Disable D cache\r
+ *\r
+ *************************************************************************/\r
+void CP15_DCache (Boolean Enable);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_ProgFlowPredictioin\r
+ * Parameters: Boolean Enable\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Enable/Disable program flow prediction\r
+ *\r
+ *************************************************************************/\r
+void CP15_ProgFlowPrediction (Boolean Enable);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_GetVectorBase\r
+ * Parameters: none\r
+ *\r
+ * Return: Int32U\r
+ *\r
+ * Description: Get Vector Base Register (VBAR)\r
+ *\r
+ *************************************************************************/\r
+__arm Int32U CP15_GetVectorBase(void);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetVectorBase\r
+ * Parameters: Int32U\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Set Vector Base Register (VBAR)\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetVectorBase(Int32U vector);\r
+\r
+/*************************************************************************\r
+ * Function Name: CP15_SetHighVectors\r
+ * Parameters: Boolean\r
+ *\r
+ * Return: none\r
+ *\r
+ * Description: Select High or Low Vectors base in CP15 control register\r
+ *\r
+ *************************************************************************/\r
+__arm void CP15_SetHighVectors(Boolean Enable);\r
+\r
+#endif // __ARMV7A_CP15_DRV_H\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x20020000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x0;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x0;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20020040;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x800;\r
+define symbol __ICFEDIT_size_svcstack__ = 0x800;\r
+define symbol __ICFEDIT_size_irqstack__ = 0x800;\r
+define symbol __ICFEDIT_size_fiqstack__ = 0x40;\r
+define symbol __ICFEDIT_size_undstack__ = 0x40;\r
+define symbol __ICFEDIT_size_abtstack__ = 0x40;\r
+define symbol __ICFEDIT_size_heap__ = 0x8;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF;\r
+\r
+define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60020000;\r
+define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF;\r
+\r
+define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000;\r
+define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF;\r
+\r
+define memory mem with size = 4G;\r
+\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__];\r
+define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__];\r
+define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };\r
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };\r
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };\r
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };\r
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+do not initialize { section MMU_TT };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite,\r
+ block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,\r
+ block UND_STACK, block ABT_STACK, block HEAP };\r
+\r
+place in RetRAM_region { section .retram };\r
+place in MirrorRAM_region { section .mirrorram };\r
+place in MirrorRetRAM_region { section .mirrorretram };
\ No newline at end of file
--- /dev/null
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
+@REM\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM\r
+@REM Read about available command line parameters in the C-SPY Debugging\r
+@REM Guide. Hints about additional command line parameters that may be\r
+@REM useful in specific cases:\r
+@REM --download_only Downloads a code image without starting a debug\r
+@REM session afterwards.\r
+@REM --silent Omits the sign-on message.\r
+@REM --timeout Limits the maximum allowed execution time.\r
+@REM \r
+\r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armsim2.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armbat.dll" --backend -B "--endian=little" "--cpu=Cortex-A9" "--fpu=VFPv3Neon" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\Renesas\R7S721000.ddf" "--semihosting=none" "--device=R7S721000" \r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project>\r
+ <Desktop>\r
+ <Static>\r
+ <Debug-Log>\r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>\r
+ <Build>\r
+ \r
+ \r
+ \r
+ \r
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+ <Workspace>\r
+ <ColumnWidths>\r
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+ \r
+ \r
+ \r
+ <Column0>228</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Disassembly>\r
+ <col-names>\r
+ \r
+ \r
+ <item>Disassembly</item><item>_I0</item></col-names>\r
+ <col-widths>\r
+ \r
+ \r
+ <item>500</item><item>20</item></col-widths>\r
+ <DisasmHistory/>\r
+ \r
+ \r
+ <PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ShowCodeCoverage>1</ShowCodeCoverage><ShowInstrProfiling>1</ShowInstrProfiling></Disassembly>\r
+ <Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>WATCH_1</Factory></Window></Windows></PreferedWindows></Register><WATCH_1><expressions><item/></expressions><col-names><item>Expression</item><item>Location</item><item>Type</item><item>Value</item></col-names><col-widths><item>236</item><item>150</item><item>100</item><item>100</item></col-widths><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></WATCH_1><Auto><col-names><item>Expression</item><item>Location</item><item>Type</item><item>Value</item></col-names><col-widths><item>100</item><item>150</item><item>100</item><item>100</item></col-widths><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Auto><Find-in-Files><ColumnWidth0>580</ColumnWidth0><ColumnWidth1>82</ColumnWidth1><ColumnWidth2>994</ColumnWidth2></Find-in-Files><Breakpoints><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><col-names><item>Breakpoint</item><item>_I0</item></col-names><col-widths><item>500</item><item>35</item></col-widths></Breakpoints></Static>\r
+ <Windows>\r
+ \r
+ \r
+ \r
+ <Wnd2>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-6824-27546</Identity>\r
+ <TabName>Debug Log</TabName>\r
+ <Factory>Debug-Log</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab>\r
+ <Identity>TabID-17050-27559</Identity>\r
+ <TabName>Build</TabName>\r
+ <Factory>Build</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab><Identity>TabID-11794-23690</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab></Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd2><Wnd3>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-17573-27549</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Blinky-Demo</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS-Source</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS-Source/portable</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS-Source/portable/IAR</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS-Source/portable/IAR/ARM_CA9</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+ <Editor>\r
+ \r
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+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\Source\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>121</YPos2><SelStart2>6648</SelStart2><SelEnd2>6648</SelEnd2></Tab><ActiveTab>0</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\Source\Full-Demo\main_full.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>161</YPos2><SelStart2>9238</SelStart2><SelEnd2>9238</SelEnd2></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-0134b3c8><key>iaridepm.enu1</key></Toolbar-0134b3c8></Sizes></Row0><Row1><Sizes><Toolbar-1310c7c0><key>debuggergui.enu1</key></Toolbar-1310c7c0></Sizes></Row1></Top><Left><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>716</Bottom><Right>302</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>180952</sizeVertCX><sizeVertCY>731161</sizeVertCY></Rect></Wnd3></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd2></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Project>\r
+\r
+\r
--- /dev/null
+[Stack]\r
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+SpWarningsEnabled=0\r
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+[JLinkDriver]\r
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+Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0\r
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+[DebugChecksum]\r
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+[Jet]\r
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+JetConnFoundProbes=\r
+DisableInterrupts=0\r
+[PlDriver]\r
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+[ArmDriver]\r
+EnableCache=1\r
+[Exceptions]\r
+StopOnUncaught=_ 0\r
+StopOnThrow=_ 0\r
+[CallStack]\r
+ShowArgs=0\r
+[Disassembly]\r
+MixedMode=1\r
+[SWOManager]\r
+SamplingDivider=8192\r
+OverrideClock=0\r
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+SwoClock=-1\r
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+Title0=ITrgPwr\r
+Symbol0=0 4 1\r
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+LiveFile=PowerLogLive.log\r
+[Trace2]\r
+Enabled=0\r
+ShowSource=0\r
+[SWOTraceWindow]\r
+ForcedPcSampling=0\r
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+EventFOLD=0\r
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+EventSLEEP=0\r
+[PowerProbe]\r
+Frequency=10000\r
+Probe0=ITrgPwr\r
+ProbeSetup0=2 1 1 2 0 0\r
+[watch_formats]\r
+Fmt0={W}0:*(unsigned long *)0xE8202004 4 0\r
+Fmt1={W}0:*(unsigned long*)0xe8202004 4 0\r
+Fmt2={W}0:INTC_ICDIPR33 4 0\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+[CallStackLog]\r
+Enabled=0\r
+[DriverProfiling]\r
+Enabled=0\r
+Mode=0\r
+Graph=0\r
+Symbiont=0\r
+Exclusions=\r
+[InterruptLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
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+ShowTimeLog=1\r
+ShowTimeSum=1\r
+[Disassemble mode]\r
+mode=0\r
+[Breakpoints2]\r
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+[Interrupts]\r
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+[MemoryMap]\r
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+ActionState=1\r
+[Aliases]\r
+Count=0\r
+SuppressDialog=0\r
+[Trace1]\r
+Enabled=0\r
+ShowSource=1\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+ <ConfigDictionary>\r
+ \r
+ \r
+ \r
+ <CurrentConfigs><Project>RTOSDemo/RAM Debug</Project></CurrentConfigs></ConfigDictionary>\r
+ <Desktop>\r
+ <Static>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>306</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Debug-Log>\r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>\r
+ <Build>\r
+ \r
+ \r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build>\r
+ <TerminalIO/><Select-Ambiguous-Definitions><ColumnWidth0>580</ColumnWidth0><ColumnWidth1>82</ColumnWidth1><ColumnWidth2>994</ColumnWidth2></Select-Ambiguous-Definitions><Breakpoints><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><col-names><item>Breakpoint</item><item>_I0</item></col-names><col-widths><item>500</item><item>35</item></col-widths></Breakpoints><Find-All-Declarations><ColumnWidth0>580</ColumnWidth0><ColumnWidth1>82</ColumnWidth1><ColumnWidth2>994</ColumnWidth2></Find-All-Declarations></Static>\r
+ <Windows>\r
+ \r
+ \r
+ <Wnd2>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-16877-7786</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Full-Demo</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd2><Wnd3>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-27919-7988</Identity>\r
+ <TabName>Debug Log</TabName>\r
+ <Factory>Debug-Log</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab>\r
+ <Identity>TabID-13343-8671</Identity>\r
+ <TabName>Build</TabName>\r
+ <Factory>Build</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab><Identity>TabID-959-438</Identity><TabName>Ambiguous Definitions</TabName><Factory>Select-Ambiguous-Definitions</Factory><Session/></Tab><Tab><Identity>TabID-21579-10611</Identity><TabName>Find All Declarations</TabName><Factory>Find-All-Declarations</Factory><Session/></Tab></Tabs>\r
+ \r
+ <SelectedTab>1</SelectedTab></Wnd3></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\Source\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>67</YPos2><SelStart2>4910</SelStart2><SelEnd2>4910</SelEnd2></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-0134b580><key>iaridepm.enu1</key></Toolbar-0134b580></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>692</Bottom><Right>380</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>227381</sizeVertCX><sizeVertCY>706721</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>246</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>248</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>252546</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Workspace>\r
+\r
+\r
--- /dev/null
+[BREAKPOINTS]\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+CacheExcludeSize = 0x00\r
+CacheExcludeAddr = 0x00\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 1\r
+Device="Unspecified"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+RAMUsageLimit = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky(). Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds...and so on.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky(). When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, toggles an LED. The 'block\r
+ * time' parameter passed to the queue receive function specifies that the\r
+ * task should be held in the Blocked state indefinitely to wait for data to\r
+ * be available on the queue. The queue receive task will only leave the\r
+ * Blocked state when the queue send task writes to the queue. As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo includes. */\r
+#include "partest.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_RATE_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* The LED toggled by the Rx task. */\r
+#define mainTASK_LED ( 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * Called by main() to create the simply blinky style application if\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ NULL, /* The parameter passed to the task - not used in this case. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+const unsigned long ulExpectedValue = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == ulExpectedValue )\r
+ {\r
+ vParTestToggleLED( mainTASK_LED );\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+/*\r
+ * The FreeRTOS Cortex-A port implements a full interrupt nesting model.\r
+ *\r
+ * Interrupts that are assigned a priority at or below\r
+ * configMAX_API_CALL_INTERRUPT_PRIORITY (which counter-intuitively in the ARM\r
+ * generic interrupt controller [GIC] means a priority that has a numerical\r
+ * value above configMAX_API_CALL_INTERRUPT_PRIORITY) can call FreeRTOS safe API\r
+ * functions and will nest.\r
+ *\r
+ * Interrupts that are assigned a priority above\r
+ * configMAX_API_CALL_INTERRUPT_PRIORITY (which in the GIC means a numerical\r
+ * value below configMAX_API_CALL_INTERRUPT_PRIORITY) cannot call any FreeRTOS\r
+ * API functions, will nest, and will not be masked by FreeRTOS critical\r
+ * sections (although it is necessary for interrupts to be globally disabled\r
+ * extremely briefly as the interrupt mask is updated in the GIC).\r
+ *\r
+ * FreeRTOS functions that can be called from an interrupt are those that end in\r
+ * "FromISR". FreeRTOS maintains a separate interrupt safe API to enable\r
+ * interrupt entry to be shorter, faster, simpler and smaller.\r
+ *\r
+ * The Renesas RZ implements 32 unique interrupt priorities. For the purpose of\r
+ * setting configMAX_API_CALL_INTERRUPT_PRIORITY 31 represents the lowest\r
+ * priority.\r
+ */\r
+#define configMAX_API_CALL_INTERRUPT_PRIORITY 25\r
+\r
+\r
+#define configCPU_CLOCK_HZ 100000000UL\r
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#define configUSE_TICKLESS_IDLE 0\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configPERIPHERAL_CLOCK_HZ ( 33333000UL )\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 1\r
+#define configMAX_PRIORITIES ( 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 160 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 38912 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 0\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+/* Prevent C code being included in assembly files when the IAR compiler is\r
+used. */\r
+#ifndef __IASMARM__\r
+ /* Run time stats gathering definitions. */\r
+ unsigned long ulGetRunTimeCounterValue( void );\r
+ void vInitialiseRunTimeStats( void );\r
+\r
+ #define configGENERATE_RUN_TIME_STATS 1\r
+ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vInitialiseRunTimeStats()\r
+ #define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue()\r
+\r
+ /* The size of the global output buffer that is available for use when there\r
+ are multiple command interpreters running at once (for example, one on a UART\r
+ and one on TCP/IP). This is done to prevent an output buffer being defined by\r
+ each implementation - which would waste RAM. In this case, there is only one\r
+ command interpreter running. */\r
+ #define configCOMMAND_INT_MAX_OUTPUT_SIZE 2096\r
+\r
+ /* Normal assert() semantics without relying on the provision of an assert.h\r
+ header file. */\r
+ void vAssertCalled( const char * pcFile, unsigned long ulLine );\r
+ #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ );\r
+\r
+\r
+\r
+ /****** Hardware specific settings. *******************************************/\r
+\r
+ /*\r
+ * The application must provide a function that configures a peripheral to\r
+ * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()\r
+ * in FreeRTOSConfig.h to call the function. This file contains a function\r
+ * that is suitable for use on the Renesas RZ MPU. FreeRTOS_Tick_Handler() must\r
+ * be installed as the peripheral's interrupt handler.\r
+ */\r
+ void vConfigureTickInterrupt( void );\r
+ #define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt()\r
+#endif /* __ICCARM__ */\r
+\r
+/* The following constants describe the hardware, and are correct for the\r
+Renesas RZ MPU. */\r
+#define configINTERRUPT_CONTROLLER_BASE_ADDRESS 0xE8201000\r
+#define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET 0x1000\r
+#define configUNIQUE_INTERRUPT_PRIORITIES 32\r
+\r
+/* Map the FreeRTOS IRQ and SVC/SWI handlers to the names used in the C startup\r
+code (which is where the vector table is defined). */\r
+#define FreeRTOS_IRQ_Handler IRQ_Handler\r
+#define FreeRTOS_SWI_Handler SWI_Handler\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "Task.h"\r
+\r
+/* Renesas driver includes. */\r
+#include "stdint.h"\r
+#include "dev_drv.h"\r
+#include "devdrv_ostm.h"\r
+#include "devdrv_intc.h"\r
+#include "iodefine.h"\r
+\r
+#define runtimeCLOCK_SCALE_SHIFT ( 9UL )\r
+#define runtimeOVERFLOW_BIT ( 1UL << ( 32UL - runtimeCLOCK_SCALE_SHIFT ) )\r
+\r
+/* To make casting to the ISR prototype expected by the Renesas GIC drivers. */\r
+typedef void (*ISR_FUNCTION)( uint32_t );\r
+\r
+/*\r
+ * The application must provide a function that configures a peripheral to\r
+ * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()\r
+ * in FreeRTOSConfig.h to call the function. This file contains a function\r
+ * that is suitable for use on the Renesas RZ MPU.\r
+ */\r
+void vConfigureTickInterrupt( void )\r
+{\r
+ /* Stop the counter. */\r
+ OSTM0.OSTMnTT.BIT.OSTMnTT = 1;\r
+\r
+ /* Work in interval mode. */\r
+ OSTM0.OSTMnCTL.BIT.OSTMnMD1 = OSTM_MODE_INTERVAL;\r
+\r
+ /* Use interrupts after counting starts. */\r
+ OSTM0.OSTMnCTL.BIT.OSTMnMD0 = 1;\r
+\r
+ /* Start value for down counter. */\r
+ OSTM0.OSTMnCMP = configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ;\r
+\r
+ /* Configure the interrupt controller. */\r
+ R_INTC_RegistIntFunc( INTC_ID_OSTMI0, ( ISR_FUNCTION ) FreeRTOS_Tick_Handler );\r
+\r
+ /* Tick must be assigned the lowest interrupt priority. */\r
+ R_INTC_SetPriority( INTC_ID_OSTMI0, portLOWEST_USABLE_INTERRUPT_PRIORITY );\r
+\r
+ INTC.ICCBPR.BIT.Binarypoint = 0;\r
+ R_INTC_Enable( INTC_ID_OSTMI0 );\r
+\r
+ R_OSTM_Open( DEVDRV_CH_0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Crude implementation of a run time counter used to measure how much time\r
+ * each task spends in the Running state.\r
+ */\r
+unsigned long ulGetRunTimeCounterValue( void )\r
+{\r
+static unsigned long ulLastCounterValue = 0UL, ulOverflows = 0;\r
+unsigned long ulValueNow;\r
+\r
+ ulValueNow = OSTM1.OSTMnCNT;\r
+\r
+ /* Has the value overflowed since it was last read. */\r
+ if( ulValueNow < ulLastCounterValue )\r
+ {\r
+ ulOverflows++;\r
+ }\r
+ ulLastCounterValue = ulValueNow;\r
+\r
+ /* There is no prescale on the counter, so simulate in software. */\r
+ ulValueNow >>= runtimeCLOCK_SCALE_SHIFT + ( runtimeOVERFLOW_BIT * ulOverflows );\r
+\r
+ return ulValueNow;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vInitialiseRunTimeStats( void )\r
+{\r
+ /* OSTM1 is used as the run time stats counter. */\r
+\r
+ /* Stop the counter. */\r
+ OSTM1.OSTMnTT.BIT.OSTMnTT = 1;\r
+\r
+ /* Work in compare mode mode. */\r
+ OSTM1.OSTMnCTL.BIT.OSTMnMD1 = OSTM_MODE_COMPARE;\r
+\r
+ /* Don't use interrupts. */\r
+ OSTM1.OSTMnCTL.BIT.OSTMnMD0 = 0;\r
+\r
+ /* Compare is just set to 0. */\r
+ OSTM1.OSTMnCMP = 0;\r
+\r
+ R_OSTM_Open( DEVDRV_CH_1 );\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+/* FreeRTOS+CLI includes. */\r
+#include "FreeRTOS_CLI.h"\r
+\r
+/* File system includes. */\r
+#include "fat_sl.h"\r
+#include "api_mdriver_ram.h"\r
+\r
+#ifdef _WINDOWS_\r
+ #define snprintf _snprintf\r
+#endif\r
+\r
+#define cliNEW_LINE "\r\n"\r
+\r
+/*******************************************************************************\r
+ * See the URL in the comments within main.c for the location of the online\r
+ * documentation.\r
+ ******************************************************************************/\r
+\r
+/*\r
+ * Print out information on a single file.\r
+ */\r
+static void prvCreateFileInfoString( int8_t *pcBuffer, F_FIND *pxFindStruct );\r
+\r
+/*\r
+ * Copies an existing file into a newly created file.\r
+ */\r
+static portBASE_TYPE prvPerformCopy( int8_t *pcSourceFile,\r
+ int32_t lSourceFileLength,\r
+ int8_t *pcDestinationFile,\r
+ int8_t *pxWriteBuffer,\r
+ size_t xWriteBufferLen );\r
+\r
+/*\r
+ * Implements the DIR command.\r
+ */\r
+static portBASE_TYPE prvDIRCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Implements the CD command.\r
+ */\r
+static portBASE_TYPE prvCDCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Implements the DEL command.\r
+ */\r
+static portBASE_TYPE prvDELCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Implements the TYPE command.\r
+ */\r
+static portBASE_TYPE prvTYPECommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Implements the COPY command.\r
+ */\r
+static portBASE_TYPE prvCOPYCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Registers the CLI commands that are specific to the files system with the\r
+ * FreeRTOS+CLI command interpreter.\r
+ */\r
+void vRegisterFileSystemCLICommands( void );\r
+\r
+/* Structure that defines the DIR command line command, which lists all the\r
+files in the current directory. */\r
+static const CLI_Command_Definition_t xDIR =\r
+{\r
+ "dir", /* The command string to type. */\r
+ "\r\ndir:\r\n Lists the files in the current directory\r\n",\r
+ prvDIRCommand, /* The function to run. */\r
+ 0 /* No parameters are expected. */\r
+};\r
+\r
+/* Structure that defines the CD command line command, which changes the\r
+working directory. */\r
+static const CLI_Command_Definition_t xCD =\r
+{\r
+ "cd", /* The command string to type. */\r
+ "\r\ncd <dir name>:\r\n Changes the working directory\r\n",\r
+ prvCDCommand, /* The function to run. */\r
+ 1 /* One parameter is expected. */\r
+};\r
+\r
+/* Structure that defines the TYPE command line command, which prints the\r
+contents of a file to the console. */\r
+static const CLI_Command_Definition_t xTYPE =\r
+{\r
+ "type", /* The command string to type. */\r
+ "\r\ntype <filename>:\r\n Prints file contents to the terminal\r\n",\r
+ prvTYPECommand, /* The function to run. */\r
+ 1 /* One parameter is expected. */\r
+};\r
+\r
+/* Structure that defines the DEL command line command, which deletes a file. */\r
+static const CLI_Command_Definition_t xDEL =\r
+{\r
+ "del", /* The command string to type. */\r
+ "\r\ndel <filename>:\r\n deletes a file or directory\r\n",\r
+ prvDELCommand, /* The function to run. */\r
+ 1 /* One parameter is expected. */\r
+};\r
+\r
+/* Structure that defines the COPY command line command, which deletes a file. */\r
+static const CLI_Command_Definition_t xCOPY =\r
+{\r
+ "copy", /* The command string to type. */\r
+ "\r\ncopy <source file> <dest file>:\r\n Copies <source file> to <dest file>\r\n",\r
+ prvCOPYCommand, /* The function to run. */\r
+ 2 /* Two parameters are expected. */\r
+};\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegisterFileSystemCLICommands( void )\r
+{\r
+ /* Register all the command line commands defined immediately above. */\r
+ FreeRTOS_CLIRegisterCommand( &xDIR );\r
+ FreeRTOS_CLIRegisterCommand( &xCD );\r
+ FreeRTOS_CLIRegisterCommand( &xTYPE );\r
+ FreeRTOS_CLIRegisterCommand( &xDEL );\r
+ FreeRTOS_CLIRegisterCommand( &xCOPY );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvTYPECommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+int8_t *pcParameter;\r
+portBASE_TYPE xParameterStringLength, xReturn = pdTRUE;\r
+static F_FILE *pxFile = NULL;\r
+int iChar;\r
+size_t xByte;\r
+size_t xColumns = 50U;\r
+\r
+ /* Ensure there is always a null terminator after each character written. */\r
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );\r
+\r
+ /* Ensure the buffer leaves space for the \r\n. */\r
+ configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) );\r
+ xWriteBufferLen -= strlen( cliNEW_LINE );\r
+\r
+ if( xWriteBufferLen < xColumns )\r
+ {\r
+ /* Ensure the loop that uses xColumns as an end condition does not\r
+ write off the end of the buffer. */\r
+ xColumns = xWriteBufferLen;\r
+ }\r
+\r
+ if( pxFile == NULL )\r
+ {\r
+ /* The file has not been opened yet. Find the file name. */\r
+ pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+ (\r
+ pcCommandString, /* The command string itself. */\r
+ 1, /* Return the first parameter. */\r
+ &xParameterStringLength /* Store the parameter string length. */\r
+ );\r
+\r
+ /* Sanity check something was returned. */\r
+ configASSERT( pcParameter );\r
+\r
+ /* Attempt to open the requested file. */\r
+ pxFile = f_open( ( const char * ) pcParameter, "r" );\r
+ }\r
+\r
+ if( pxFile != NULL )\r
+ {\r
+ /* Read the next chunk of data from the file. */\r
+ for( xByte = 0; xByte < xColumns; xByte++ )\r
+ {\r
+ iChar = f_getc( pxFile );\r
+\r
+ if( iChar == -1 )\r
+ {\r
+ /* No more characters to return. */\r
+ f_close( pxFile );\r
+ pxFile = NULL;\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ pcWriteBuffer[ xByte ] = ( int8_t ) iChar;\r
+ }\r
+ }\r
+ }\r
+\r
+ if( pxFile == NULL )\r
+ {\r
+ /* Either the file was not opened, or all the data from the file has\r
+ been returned and the file is now closed. */\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvCDCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+int8_t *pcParameter;\r
+portBASE_TYPE xParameterStringLength;\r
+unsigned char ucReturned;\r
+size_t xStringLength;\r
+\r
+ /* Obtain the parameter string. */\r
+ pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+ (\r
+ pcCommandString, /* The command string itself. */\r
+ 1, /* Return the first parameter. */\r
+ &xParameterStringLength /* Store the parameter string length. */\r
+ );\r
+\r
+ /* Sanity check something was returned. */\r
+ configASSERT( pcParameter );\r
+\r
+ /* Attempt to move to the requested directory. */\r
+ ucReturned = f_chdir( ( char * ) pcParameter );\r
+\r
+ if( ucReturned == F_NO_ERROR )\r
+ {\r
+ sprintf( ( char * ) pcWriteBuffer, "In: " );\r
+ xStringLength = strlen( ( const char * ) pcWriteBuffer );\r
+ f_getcwd( ( char * ) &( pcWriteBuffer[ xStringLength ] ), ( unsigned char ) ( xWriteBufferLen - xStringLength ) );\r
+ }\r
+ else\r
+ {\r
+ sprintf( ( char * ) pcWriteBuffer, "Error" );\r
+ }\r
+\r
+ strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );\r
+\r
+ return pdFALSE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvDIRCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+static F_FIND *pxFindStruct = NULL;\r
+unsigned char ucReturned;\r
+portBASE_TYPE xReturn = pdFALSE;\r
+\r
+ /* This assumes pcWriteBuffer is long enough. */\r
+ ( void ) pcCommandString;\r
+\r
+ /* Ensure the buffer leaves space for the \r\n. */\r
+ configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) );\r
+ xWriteBufferLen -= strlen( cliNEW_LINE );\r
+\r
+ if( pxFindStruct == NULL )\r
+ {\r
+ /* This is the first time this function has been executed since the Dir\r
+ command was run. Create the find structure. */\r
+ pxFindStruct = ( F_FIND * ) pvPortMalloc( sizeof( F_FIND ) );\r
+\r
+ if( pxFindStruct != NULL )\r
+ {\r
+ ucReturned = f_findfirst( "*.*", pxFindStruct );\r
+\r
+ if( ucReturned == F_NO_ERROR )\r
+ {\r
+ prvCreateFileInfoString( pcWriteBuffer, pxFindStruct );\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ snprintf( ( char * ) pcWriteBuffer, xWriteBufferLen, "Error: f_findfirst() failed." );\r
+ }\r
+ }\r
+ else\r
+ {\r
+ snprintf( ( char * ) pcWriteBuffer, xWriteBufferLen, "Failed to allocate RAM (using heap_4.c will prevent fragmentation)." );\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* The find struct has already been created. Find the next file in\r
+ the directory. */\r
+ ucReturned = f_findnext( pxFindStruct );\r
+\r
+ if( ucReturned == F_NO_ERROR )\r
+ {\r
+ prvCreateFileInfoString( pcWriteBuffer, pxFindStruct );\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ /* There are no more files. Free the find structure. */\r
+ vPortFree( pxFindStruct );\r
+ pxFindStruct = NULL;\r
+\r
+ /* No string to return. */\r
+ pcWriteBuffer[ 0 ] = 0x00;\r
+ }\r
+ }\r
+\r
+ strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvDELCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+int8_t *pcParameter;\r
+portBASE_TYPE xParameterStringLength;\r
+unsigned char ucReturned;\r
+\r
+ /* This function assumes xWriteBufferLen is large enough! */\r
+ ( void ) xWriteBufferLen;\r
+\r
+ /* Obtain the parameter string. */\r
+ pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+ (\r
+ pcCommandString, /* The command string itself. */\r
+ 1, /* Return the first parameter. */\r
+ &xParameterStringLength /* Store the parameter string length. */\r
+ );\r
+\r
+ /* Sanity check something was returned. */\r
+ configASSERT( pcParameter );\r
+\r
+ /* Attempt to delete the file. */\r
+ ucReturned = f_delete( ( const char * ) pcParameter );\r
+\r
+ if( ucReturned == F_NO_ERROR )\r
+ {\r
+ sprintf( ( char * ) pcWriteBuffer, "%s was deleted", pcParameter );\r
+ }\r
+ else\r
+ {\r
+ sprintf( ( char * ) pcWriteBuffer, "Error" );\r
+ }\r
+\r
+ strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );\r
+\r
+ return pdFALSE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvCOPYCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+int8_t *pcSourceFile, *pcDestinationFile;\r
+portBASE_TYPE xParameterStringLength;\r
+long lSourceLength, lDestinationLength = 0;\r
+\r
+ /* Obtain the name of the destination file. */\r
+ pcDestinationFile = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+ (\r
+ pcCommandString, /* The command string itself. */\r
+ 2, /* Return the second parameter. */\r
+ &xParameterStringLength /* Store the parameter string length. */\r
+ );\r
+\r
+ /* Sanity check something was returned. */\r
+ configASSERT( pcDestinationFile );\r
+\r
+ /* Obtain the name of the source file. */\r
+ pcSourceFile = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+ (\r
+ pcCommandString, /* The command string itself. */\r
+ 1, /* Return the first parameter. */\r
+ &xParameterStringLength /* Store the parameter string length. */\r
+ );\r
+\r
+ /* Sanity check something was returned. */\r
+ configASSERT( pcSourceFile );\r
+\r
+ /* Terminate the string. */\r
+ pcSourceFile[ xParameterStringLength ] = 0x00;\r
+\r
+ /* See if the source file exists, obtain its length if it does. */\r
+ lSourceLength = f_filelength( ( const char * ) pcSourceFile );\r
+\r
+ if( lSourceLength == 0 )\r
+ {\r
+ sprintf( ( char * ) pcWriteBuffer, "Source file does not exist" );\r
+ }\r
+ else\r
+ {\r
+ /* See if the destination file exists. */\r
+ lDestinationLength = f_filelength( ( const char * ) pcDestinationFile );\r
+\r
+ if( lDestinationLength != 0 )\r
+ {\r
+ sprintf( ( char * ) pcWriteBuffer, "Error: Destination file already exists" );\r
+ }\r
+ }\r
+\r
+ /* Continue only if the source file exists and the destination file does\r
+ not exist. */\r
+ if( ( lSourceLength != 0 ) && ( lDestinationLength == 0 ) )\r
+ {\r
+ if( prvPerformCopy( pcSourceFile, lSourceLength, pcDestinationFile, pcWriteBuffer, xWriteBufferLen ) == pdPASS )\r
+ {\r
+ sprintf( ( char * ) pcWriteBuffer, "Copy made" );\r
+ }\r
+ else\r
+ {\r
+ sprintf( ( char * ) pcWriteBuffer, "Error during copy" );\r
+ }\r
+ }\r
+\r
+ strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );\r
+\r
+ return pdFALSE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvPerformCopy( int8_t *pcSourceFile,\r
+ int32_t lSourceFileLength,\r
+ int8_t *pcDestinationFile,\r
+ int8_t *pxWriteBuffer,\r
+ size_t xWriteBufferLen )\r
+{\r
+int32_t lBytesRead = 0, lBytesToRead, lBytesRemaining;\r
+F_FILE *pxFile;\r
+portBASE_TYPE xReturn = pdPASS;\r
+\r
+ /* NOTE: Error handling has been omitted for clarity. */\r
+\r
+ while( lBytesRead < lSourceFileLength )\r
+ {\r
+ /* How many bytes are left? */\r
+ lBytesRemaining = lSourceFileLength - lBytesRead;\r
+\r
+ /* How many bytes should be read this time around the loop. Can't\r
+ read more bytes than will fit into the buffer. */\r
+ if( lBytesRemaining > ( long ) xWriteBufferLen )\r
+ {\r
+ lBytesToRead = ( long ) xWriteBufferLen;\r
+ }\r
+ else\r
+ {\r
+ lBytesToRead = lBytesRemaining;\r
+ }\r
+\r
+ /* Open the source file, seek past the data that has already been\r
+ read from the file, read the next block of data, then close the\r
+ file again so the destination file can be opened. */\r
+ pxFile = f_open( ( const char * ) pcSourceFile, "r" );\r
+ if( pxFile != NULL )\r
+ {\r
+ f_seek( pxFile, lBytesRead, F_SEEK_SET );\r
+ f_read( pxWriteBuffer, lBytesToRead, 1, pxFile );\r
+ f_close( pxFile );\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ break;\r
+ }\r
+\r
+ /* Open the destination file and write the block of data to the end of\r
+ the file. */\r
+ pxFile = f_open( ( const char * ) pcDestinationFile, "a" );\r
+ if( pxFile != NULL )\r
+ {\r
+ f_write( pxWriteBuffer, lBytesToRead, 1, pxFile );\r
+ f_close( pxFile );\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ break;\r
+ }\r
+\r
+ lBytesRead += lBytesToRead;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCreateFileInfoString( int8_t *pcBuffer, F_FIND *pxFindStruct )\r
+{\r
+const char *pcWritableFile = "writable file", *pcReadOnlyFile = "read only file", *pcDirectory = "directory";\r
+const char * pcAttrib;\r
+\r
+ /* Point pcAttrib to a string that describes the file. */\r
+ if( ( pxFindStruct->attr & F_ATTR_DIR ) != 0 )\r
+ {\r
+ pcAttrib = pcDirectory;\r
+ }\r
+ else if( pxFindStruct->attr & F_ATTR_READONLY )\r
+ {\r
+ pcAttrib = pcReadOnlyFile;\r
+ }\r
+ else\r
+ {\r
+ pcAttrib = pcWritableFile;\r
+ }\r
+\r
+ /* Create a string that includes the file name, the file size and the\r
+ attributes string. */\r
+ sprintf( ( char * ) pcBuffer, "%s [%s] [size=%d]", pxFindStruct->filename, pcAttrib, pxFindStruct->filesize );\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/*******************************************************************************\r
+ * See the URL in the comments within main.c for the location of the online\r
+ * documentation.\r
+ ******************************************************************************/\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* File system includes. */\r
+#include "fat_sl.h"\r
+#include "api_mdriver_ram.h"\r
+\r
+/* 8.3 format, plus null terminator. */\r
+#define fsMAX_FILE_NAME_LEN 13\r
+\r
+/* The number of bytes read/written to the example files at a time. */\r
+#define fsRAM_BUFFER_SIZE 200\r
+\r
+/* The number of bytes written to the file that uses f_putc() and f_getc(). */\r
+#define fsPUTC_FILE_SIZE 100\r
+\r
+/* The number of files created in root. */\r
+#define fsROOT_FILES 5\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Creates and verifies different files on the volume, demonstrating the use of\r
+ * various different API functions.\r
+ */\r
+void vCreateAndVerifySampleFiles( void );\r
+\r
+/*\r
+ * Create a set of example files in the root directory of the volume using\r
+ * f_write().\r
+ */\r
+static void prvCreateDemoFilesUsing_f_write( void );\r
+\r
+/*\r
+ * Use f_read() to read back and verify the files that were created by\r
+ * prvCreateDemoFilesUsing_f_write().\r
+ */\r
+static void prvVerifyDemoFileUsing_f_read( void );\r
+\r
+/*\r
+ * Create an example file in a sub-directory using f_putc().\r
+ */\r
+static void prvCreateDemoFileUsing_f_putc( void );\r
+\r
+/*\r
+ * Use f_getc() to read back and verify the file that was created by\r
+ * prvCreateDemoFileUsing_f_putc().\r
+ */\r
+static void prvVerifyDemoFileUsing_f_getc( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* A buffer used to both create content to write to disk, and read content back\r
+from a disk. Note there is no mutual exclusion on this buffer. */\r
+static char cRAMBuffer[ fsRAM_BUFFER_SIZE ];\r
+\r
+/* Names of directories that are created. */\r
+static const char *pcRoot = "/", *pcDirectory1 = "SUB1", *pcDirectory2 = "SUB2", *pcFullPath = "/SUB1/SUB2";\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vCreateAndVerifySampleFiles( void )\r
+{\r
+unsigned char ucStatus;\r
+\r
+ /* First create the volume. */\r
+ ucStatus = f_initvolume( ram_initfunc );\r
+\r
+ /* It is expected that the volume is not formatted. */\r
+ if( ucStatus == F_ERR_NOTFORMATTED )\r
+ {\r
+ /* Format the created volume. */\r
+ ucStatus = f_format( F_FAT12_MEDIA );\r
+ }\r
+\r
+ if( ucStatus == F_NO_ERROR )\r
+ {\r
+ /* Create a set of files using f_write(). */\r
+ prvCreateDemoFilesUsing_f_write();\r
+\r
+ /* Read back and verify the files that were created using f_write(). */\r
+ prvVerifyDemoFileUsing_f_read();\r
+\r
+ /* Create sub directories two deep then create a file using putc. */\r
+ prvCreateDemoFileUsing_f_putc();\r
+\r
+ /* Read back and verify the file created by\r
+ prvCreateDemoFileUsing_f_putc(). */\r
+ prvVerifyDemoFileUsing_f_getc();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCreateDemoFilesUsing_f_write( void )\r
+{\r
+portBASE_TYPE xFileNumber, xWriteNumber;\r
+char cFileName[ fsMAX_FILE_NAME_LEN ];\r
+long lItemsWritten;\r
+F_FILE *pxFile;\r
+\r
+ /* Create fsROOT_FILES files. Each created file will be\r
+ ( xFileNumber * fsRAM_BUFFER_SIZE ) bytes in length, and filled\r
+ with a different repeating character. */\r
+ for( xFileNumber = 1; xFileNumber <= fsROOT_FILES; xFileNumber++ )\r
+ {\r
+ /* Generate a file name. */\r
+ sprintf( cFileName, "root%03d.txt", xFileNumber );\r
+\r
+ /* Obtain the current working directory and print out the file name and\r
+ the directory into which the file is being written. */\r
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+ printf( "Creating file %s in %s\r\n", cFileName, cRAMBuffer );\r
+\r
+ /* Open the file, creating the file if it does not already exist. */\r
+ pxFile = f_open( cFileName, "w" );\r
+ configASSERT( pxFile );\r
+\r
+ /* Fill the RAM buffer with data that will be written to the file. This\r
+ is just a repeating ascii character that indicates the file number. */\r
+ memset( cRAMBuffer, ( int ) ( '0' + xFileNumber ), fsRAM_BUFFER_SIZE );\r
+\r
+ /* Write the RAM buffer to the opened file a number of times. The\r
+ number of times the RAM buffer is written to the file depends on the\r
+ file number, so the length of each created file will be different. */\r
+ for( xWriteNumber = 0; xWriteNumber < xFileNumber; xWriteNumber++ )\r
+ {\r
+ lItemsWritten = f_write( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile );\r
+ configASSERT( lItemsWritten == 1 );\r
+ }\r
+\r
+ /* Close the file so another file can be created. */\r
+ f_close( pxFile );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvVerifyDemoFileUsing_f_read( void )\r
+{\r
+portBASE_TYPE xFileNumber, xReadNumber;\r
+char cFileName[ fsMAX_FILE_NAME_LEN ];\r
+long lItemsRead, lChar;\r
+F_FILE *pxFile;\r
+\r
+ /* Read back the files that were created by\r
+ prvCreateDemoFilesUsing_f_write(). */\r
+ for( xFileNumber = 1; xFileNumber <= fsROOT_FILES; xFileNumber++ )\r
+ {\r
+ /* Generate the file name. */\r
+ sprintf( cFileName, "root%03d.txt", xFileNumber );\r
+\r
+ /* Obtain the current working directory and print out the file name and\r
+ the directory from which the file is being read. */\r
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+ printf( "Reading file %s from %s\r\n", cFileName, cRAMBuffer );\r
+\r
+ /* Open the file for reading. */\r
+ pxFile = f_open( cFileName, "r" );\r
+ configASSERT( pxFile );\r
+\r
+ /* Read the file into the RAM buffer, checking the file contents are as\r
+ expected. The size of the file depends on the file number. */\r
+ for( xReadNumber = 0; xReadNumber < xFileNumber; xReadNumber++ )\r
+ {\r
+ /* Start with the RAM buffer clear. */\r
+ memset( cRAMBuffer, 0x00, fsRAM_BUFFER_SIZE );\r
+\r
+ lItemsRead = f_read( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile );\r
+ configASSERT( lItemsRead == 1 );\r
+\r
+ /* Check the RAM buffer is filled with the expected data. Each\r
+ file contains a different repeating ascii character that indicates\r
+ the number of the file. */\r
+ for( lChar = 0; lChar < fsRAM_BUFFER_SIZE; lChar++ )\r
+ {\r
+ configASSERT( cRAMBuffer[ lChar ] == ( '0' + ( char ) xFileNumber ) );\r
+ }\r
+ }\r
+\r
+ /* Close the file. */\r
+ f_close( pxFile );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCreateDemoFileUsing_f_putc( void )\r
+{\r
+unsigned char ucReturn;\r
+int iByte, iReturned;\r
+F_FILE *pxFile;\r
+char cFileName[ fsMAX_FILE_NAME_LEN ];\r
+\r
+ /* Obtain and print out the working directory. */\r
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+ printf( "In directory %s\r\n", cRAMBuffer );\r
+\r
+ /* Create a sub directory. */\r
+ ucReturn = f_mkdir( pcDirectory1 );\r
+ configASSERT( ucReturn == F_NO_ERROR );\r
+\r
+ /* Move into the created sub-directory. */\r
+ ucReturn = f_chdir( pcDirectory1 );\r
+ configASSERT( ucReturn == F_NO_ERROR );\r
+\r
+ /* Obtain and print out the working directory. */\r
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+ printf( "In directory %s\r\n", cRAMBuffer );\r
+\r
+ /* Create a subdirectory in the new directory. */\r
+ ucReturn = f_mkdir( pcDirectory2 );\r
+ configASSERT( ucReturn == F_NO_ERROR );\r
+\r
+ /* Move into the directory just created - now two directories down from\r
+ the root. */\r
+ ucReturn = f_chdir( pcDirectory2 );\r
+ configASSERT( ucReturn == F_NO_ERROR );\r
+\r
+ /* Obtain and print out the working directory. */\r
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+ printf( "In directory %s\r\n", cRAMBuffer );\r
+ configASSERT( strcmp( ( const char * ) cRAMBuffer, pcFullPath ) == 0 );\r
+\r
+ /* Generate the file name. */\r
+ sprintf( cFileName, "%s.txt", pcDirectory2 );\r
+\r
+ /* Print out the file name and the directory into which the file is being\r
+ written. */\r
+ printf( "Writing file %s in %s\r\n", cFileName, cRAMBuffer );\r
+\r
+ pxFile = f_open( cFileName, "w" );\r
+\r
+ /* Create a file 1 byte at a time. The file is filled with incrementing\r
+ ascii characters starting from '0'. */\r
+ for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ )\r
+ {\r
+ iReturned = f_putc( ( ( int ) '0' + iByte ), pxFile );\r
+ configASSERT( iReturned == ( ( int ) '0' + iByte ) );\r
+ }\r
+\r
+ /* Finished so close the file. */\r
+ f_close( pxFile );\r
+\r
+ /* Move back to the root directory. */\r
+ ucReturn = f_chdir( "../.." );\r
+ configASSERT( ucReturn == F_NO_ERROR );\r
+\r
+ /* Obtain and print out the working directory. */\r
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+ printf( "Back in root directory %s\r\n", cRAMBuffer );\r
+ configASSERT( strcmp( ( const char * ) cRAMBuffer, pcRoot ) == 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvVerifyDemoFileUsing_f_getc( void )\r
+{\r
+unsigned char ucReturn;\r
+int iByte, iReturned;\r
+F_FILE *pxFile;\r
+char cFileName[ fsMAX_FILE_NAME_LEN ];\r
+\r
+ /* Move into the directory in which the file was created. */\r
+ ucReturn = f_chdir( pcFullPath );\r
+ configASSERT( ucReturn == F_NO_ERROR );\r
+\r
+ /* Obtain and print out the working directory. */\r
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+ printf( "Back in directory %s\r\n", cRAMBuffer );\r
+ configASSERT( strcmp( ( const char * ) cRAMBuffer, pcFullPath ) == 0 );\r
+\r
+ /* Generate the file name. */\r
+ sprintf( cFileName, "%s.txt", pcDirectory2 );\r
+\r
+ /* Print out the file name and the directory from which the file is being\r
+ read. */\r
+ printf( "Reading file %s in %s\r\n", cFileName, cRAMBuffer );\r
+\r
+ /* This time the file is opened for reading. */\r
+ pxFile = f_open( cFileName, "r" );\r
+\r
+ /* Read the file 1 byte at a time. */\r
+ for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ )\r
+ {\r
+ iReturned = f_getc( pxFile );\r
+ configASSERT( iReturned == ( ( int ) '0' + iByte ) );\r
+ }\r
+\r
+ /* Finished so close the file. */\r
+ f_close( pxFile );\r
+\r
+ /* Move back to the root directory. */\r
+ ucReturn = f_chdir( "../.." );\r
+ configASSERT( ucReturn == F_NO_ERROR );\r
+\r
+ /* Obtain and print out the working directory. */\r
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+ printf( "Back in root directory %s\r\n", cRAMBuffer );\r
+}\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+ /******************************************************************************\r
+ *\r
+ * See the following URL for information on the commands defined in this file:\r
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+/* FreeRTOS+CLI includes. */\r
+#include "FreeRTOS_CLI.h"\r
+\r
+#ifndef configINCLUDE_TRACE_RELATED_CLI_COMMANDS\r
+ #define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0\r
+#endif\r
+\r
+\r
+/*\r
+ * Implements the run-time-stats command.\r
+ */\r
+static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Implements the task-stats command.\r
+ */\r
+static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Implements the echo-three-parameters command.\r
+ */\r
+static portBASE_TYPE prvThreeParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Implements the echo-parameters command.\r
+ */\r
+static portBASE_TYPE prvParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Registers the CLI commands defined within this file with the FreeRTOS+CLI\r
+ * command line interface.\r
+ */\r
+void vRegisterSampleCLICommands( void );\r
+\r
+/*\r
+ * Implements the "trace start" and "trace stop" commands;\r
+ */\r
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1\r
+ static portBASE_TYPE prvStartStopTraceCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+#endif\r
+\r
+/* Structure that defines the "run-time-stats" command line command. This\r
+generates a table that shows how much run time each task has */\r
+static const CLI_Command_Definition_t xRunTimeStats =\r
+{\r
+ "run-time-stats", /* The command string to type. */\r
+ "\r\nrun-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n",\r
+ prvRunTimeStatsCommand, /* The function to run. */\r
+ 0 /* No parameters are expected. */\r
+};\r
+\r
+/* Structure that defines the "task-stats" command line command. This generates\r
+a table that gives information on each task in the system. */\r
+static const CLI_Command_Definition_t xTaskStats =\r
+{\r
+ "task-stats", /* The command string to type. */\r
+ "\r\ntask-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n",\r
+ prvTaskStatsCommand, /* The function to run. */\r
+ 0 /* No parameters are expected. */\r
+};\r
+\r
+/* Structure that defines the "echo_3_parameters" command line command. This\r
+takes exactly three parameters that the command simply echos back one at a\r
+time. */\r
+static const CLI_Command_Definition_t xThreeParameterEcho =\r
+{\r
+ "echo-3-parameters",\r
+ "\r\necho-3-parameters <param1> <param2> <param3>:\r\n Expects three parameters, echos each in turn\r\n",\r
+ prvThreeParameterEchoCommand, /* The function to run. */\r
+ 3 /* Three parameters are expected, which can take any value. */\r
+};\r
+\r
+/* Structure that defines the "echo_parameters" command line command. This\r
+takes a variable number of parameters that the command simply echos back one at\r
+a time. */\r
+static const CLI_Command_Definition_t xParameterEcho =\r
+{\r
+ "echo-parameters",\r
+ "\r\necho-parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n",\r
+ prvParameterEchoCommand, /* The function to run. */\r
+ -1 /* The user can enter any number of commands. */\r
+};\r
+\r
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1\r
+ /* Structure that defines the "trace" command line command. This takes a single\r
+ parameter, which can be either "start" or "stop". */\r
+ static const CLI_Command_Definition_t xStartStopTrace =\r
+ {\r
+ "trace",\r
+ "\r\ntrace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n",\r
+ prvStartStopTraceCommand, /* The function to run. */\r
+ 1 /* One parameter is expected. Valid values are "start" and "stop". */\r
+ };\r
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegisterSampleCLICommands( void )\r
+{\r
+ /* Register all the command line commands defined immediately above. */\r
+ FreeRTOS_CLIRegisterCommand( &xTaskStats );\r
+ FreeRTOS_CLIRegisterCommand( &xRunTimeStats );\r
+ FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho );\r
+ FreeRTOS_CLIRegisterCommand( &xParameterEcho );\r
+\r
+ #if( configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 )\r
+ {\r
+ FreeRTOS_CLIRegisterCommand( & xStartStopTrace );\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+const int8_t *const pcHeader = ( int8_t * ) "Task State Priority Stack #\r\n************************************************\r\n";\r
+\r
+ /* Remove compile time warnings about unused parameters, and check the\r
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the\r
+ write buffer length is adequate, so does not check for buffer overflows. */\r
+ ( void ) pcCommandString;\r
+ ( void ) xWriteBufferLen;\r
+ configASSERT( pcWriteBuffer );\r
+\r
+ /* Generate a table of task stats. */\r
+ strcpy( ( char * ) pcWriteBuffer, ( char * ) pcHeader );\r
+ vTaskList( pcWriteBuffer + strlen( ( char * ) pcHeader ) );\r
+\r
+ /* There is no more data to return after this single string, so return\r
+ pdFALSE. */\r
+ return pdFALSE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+const int8_t * const pcHeader = ( int8_t * ) "Task Abs Time % Time\r\n****************************************\r\n";\r
+\r
+ /* Remove compile time warnings about unused parameters, and check the\r
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the\r
+ write buffer length is adequate, so does not check for buffer overflows. */\r
+ ( void ) pcCommandString;\r
+ ( void ) xWriteBufferLen;\r
+ configASSERT( pcWriteBuffer );\r
+\r
+ /* Generate a table of task stats. */\r
+ strcpy( ( char * ) pcWriteBuffer, ( char * ) pcHeader );\r
+ vTaskGetRunTimeStats( pcWriteBuffer + strlen( ( char * ) pcHeader ) );\r
+\r
+ /* There is no more data to return after this single string, so return\r
+ pdFALSE. */\r
+ return pdFALSE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvThreeParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+int8_t *pcParameter;\r
+portBASE_TYPE xParameterStringLength, xReturn;\r
+static portBASE_TYPE lParameterNumber = 0;\r
+\r
+ /* Remove compile time warnings about unused parameters, and check the\r
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the\r
+ write buffer length is adequate, so does not check for buffer overflows. */\r
+ ( void ) pcCommandString;\r
+ ( void ) xWriteBufferLen;\r
+ configASSERT( pcWriteBuffer );\r
+\r
+ if( lParameterNumber == 0 )\r
+ {\r
+ /* The first time the function is called after the command has been\r
+ entered just a header string is returned. */\r
+ sprintf( ( char * ) pcWriteBuffer, "The three parameters were:\r\n" );\r
+\r
+ /* Next time the function is called the first parameter will be echoed\r
+ back. */\r
+ lParameterNumber = 1L;\r
+\r
+ /* There is more data to be returned as no parameters have been echoed\r
+ back yet. */\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ /* Obtain the parameter string. */\r
+ pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+ (\r
+ pcCommandString, /* The command string itself. */\r
+ lParameterNumber, /* Return the next parameter. */\r
+ &xParameterStringLength /* Store the parameter string length. */\r
+ );\r
+\r
+ /* Sanity check something was returned. */\r
+ configASSERT( pcParameter );\r
+\r
+ /* Return the parameter string. */\r
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );\r
+ sprintf( ( char * ) pcWriteBuffer, "%d: ", ( int ) lParameterNumber );\r
+ strncat( ( char * ) pcWriteBuffer, ( const char * ) pcParameter, xParameterStringLength );\r
+ strncat( ( char * ) pcWriteBuffer, "\r\n", strlen( "\r\n" ) );\r
+\r
+ /* If this is the last of the three parameters then there are no more\r
+ strings to return after this one. */\r
+ if( lParameterNumber == 3L )\r
+ {\r
+ /* If this is the last of the three parameters then there are no more\r
+ strings to return after this one. */\r
+ xReturn = pdFALSE;\r
+ lParameterNumber = 0L;\r
+ }\r
+ else\r
+ {\r
+ /* There are more parameters to return after this one. */\r
+ xReturn = pdTRUE;\r
+ lParameterNumber++;\r
+ }\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+int8_t *pcParameter;\r
+portBASE_TYPE xParameterStringLength, xReturn;\r
+static portBASE_TYPE lParameterNumber = 0;\r
+\r
+ /* Remove compile time warnings about unused parameters, and check the\r
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the\r
+ write buffer length is adequate, so does not check for buffer overflows. */\r
+ ( void ) pcCommandString;\r
+ ( void ) xWriteBufferLen;\r
+ configASSERT( pcWriteBuffer );\r
+\r
+ if( lParameterNumber == 0 )\r
+ {\r
+ /* The first time the function is called after the command has been\r
+ entered just a header string is returned. */\r
+ sprintf( ( char * ) pcWriteBuffer, "The parameters were:\r\n" );\r
+\r
+ /* Next time the function is called the first parameter will be echoed\r
+ back. */\r
+ lParameterNumber = 1L;\r
+\r
+ /* There is more data to be returned as no parameters have been echoed\r
+ back yet. */\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ /* Obtain the parameter string. */\r
+ pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+ (\r
+ pcCommandString, /* The command string itself. */\r
+ lParameterNumber, /* Return the next parameter. */\r
+ &xParameterStringLength /* Store the parameter string length. */\r
+ );\r
+\r
+ if( pcParameter != NULL )\r
+ {\r
+ /* Return the parameter string. */\r
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );\r
+ sprintf( ( char * ) pcWriteBuffer, "%d: ", ( int ) lParameterNumber );\r
+ strncat( ( char * ) pcWriteBuffer, ( const char * ) pcParameter, xParameterStringLength );\r
+ strncat( ( char * ) pcWriteBuffer, "\r\n", strlen( "\r\n" ) );\r
+\r
+ /* There might be more parameters to return after this one. */\r
+ xReturn = pdTRUE;\r
+ lParameterNumber++;\r
+ }\r
+ else\r
+ {\r
+ /* No more parameters were found. Make sure the write buffer does\r
+ not contain a valid string. */\r
+ pcWriteBuffer[ 0 ] = 0x00;\r
+\r
+ /* No more data to return. */\r
+ xReturn = pdFALSE;\r
+\r
+ /* Start over the next time this command is executed. */\r
+ lParameterNumber = 0;\r
+ }\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1\r
+\r
+ static portBASE_TYPE prvStartStopTraceCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+ {\r
+ int8_t *pcParameter;\r
+ portBASE_TYPE lParameterStringLength;\r
+\r
+ /* Remove compile time warnings about unused parameters, and check the\r
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the\r
+ write buffer length is adequate, so does not check for buffer overflows. */\r
+ ( void ) pcCommandString;\r
+ ( void ) xWriteBufferLen;\r
+ configASSERT( pcWriteBuffer );\r
+\r
+ /* Obtain the parameter string. */\r
+ pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+ (\r
+ pcCommandString, /* The command string itself. */\r
+ 1, /* Return the first parameter. */\r
+ &lParameterStringLength /* Store the parameter string length. */\r
+ );\r
+\r
+ /* Sanity check something was returned. */\r
+ configASSERT( pcParameter );\r
+\r
+ /* There are only two valid parameter values. */\r
+ if( strncmp( ( const char * ) pcParameter, "start", strlen( "start" ) ) == 0 )\r
+ {\r
+ /* Start or restart the trace. */\r
+ vTraceStop();\r
+ vTraceClear();\r
+ vTraceStart();\r
+\r
+ sprintf( ( char * ) pcWriteBuffer, "Trace recording (re)started.\r\n" );\r
+ }\r
+ else if( strncmp( ( const char * ) pcParameter, "stop", strlen( "stop" ) ) == 0 )\r
+ {\r
+ /* End the trace, if one is running. */\r
+ vTraceStop();\r
+ sprintf( ( char * ) pcWriteBuffer, "Stopping trace recording.\r\n" );\r
+ }\r
+ else\r
+ {\r
+ sprintf( ( char * ) pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" );\r
+ }\r
+\r
+ /* There is no more data to return after this single string, so return\r
+ pdFALSE. */\r
+ return pdFALSE;\r
+ }\r
+\r
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include "string.h"\r
+#include "stdio.h"\r
+#include "stdint.h"\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Common demo includes. */\r
+#include "serial.h"\r
+\r
+/* Example includes. */\r
+#include "FreeRTOS_CLI.h"\r
+#include "UARTCommandConsole.h"\r
+\r
+/* Dimensions the buffer into which input characters are placed. */\r
+#define cmdMAX_INPUT_SIZE 50\r
+\r
+/* The maximum time in ticks to wait for the UART access mutex. */\r
+#define cmdMAX_MUTEX_WAIT ( 200 / portTICK_RATE_MS )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The task that implements the command console processing.\r
+ */\r
+static void prvUARTCommandConsoleTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Const messages output by the command console. */\r
+static const signed char * const pcWelcomeMessage = "FreeRTOS command server.\r\nType Help to view a list of registered commands.\r\n\r\n>";\r
+static const signed char * const pcEndOfOutputMessage = "\r\n[Press ENTER to execute the previous command again]\r\n>";\r
+static const signed char * const pcNewLine = "\r\n";\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUARTCommandConsoleStart( uint16_t usStackSize, unsigned portBASE_TYPE uxPriority )\r
+{\r
+ /* Create that task that handles the console itself. */\r
+ xTaskCreate( prvUARTCommandConsoleTask, /* The task that implements the command console. */\r
+ "CLI", /* Text name assigned to the task. This is just to assist debugging. The kernel does not use this name itself. */\r
+ usStackSize, /* The size of the stack allocated to the task. */\r
+ NULL, /* The parameter is not used, so NULL is passed. */\r
+ uxPriority, /* The priority allocated to the task. */\r
+ NULL ); /* A handle is not required, so just pass NULL. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvUARTCommandConsoleTask( void *pvParameters )\r
+{\r
+int8_t cRxedChar, cInputIndex = 0, *pcOutputString;\r
+static int8_t cInputString[ cmdMAX_INPUT_SIZE ], cLastInputString[ cmdMAX_INPUT_SIZE ];\r
+portBASE_TYPE xReturned;\r
+\r
+ ( void ) pvParameters;\r
+\r
+ /* Obtain the address of the output buffer. Note there is no mutual\r
+ exclusion on this buffer as it is assumed only one command console\r
+ interface will be used at any one time. */\r
+ pcOutputString = FreeRTOS_CLIGetOutputBuffer();\r
+\r
+ /* Send the welcome message. */\r
+ vSerialPutString( NULL, pcWelcomeMessage, strlen( ( char * ) pcWelcomeMessage ) );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Only interested in reading one character at a time. */\r
+ while( xSerialGetChar( NULL, &cRxedChar, portMAX_DELAY ) == pdFALSE );\r
+\r
+ /* Echo the character back. */\r
+ xSerialPutChar( NULL, cRxedChar, portMAX_DELAY );\r
+\r
+ /* Was it the end of the line? */\r
+ if( cRxedChar == '\n' || cRxedChar == '\r' )\r
+ {\r
+ /* Just to space the output from the input. */\r
+ vSerialPutString( NULL, pcNewLine, strlen( ( char * ) pcNewLine ) );\r
+\r
+ /* See if the command is empty, indicating that the last command is\r
+ to be executed again. */\r
+ if( cInputIndex == 0 )\r
+ {\r
+ /* Copy the last command back into the input string. */\r
+ strcpy( ( char * ) cInputString, ( char * ) cLastInputString );\r
+ }\r
+\r
+ /* Pass the received command to the command interpreter. The\r
+ command interpreter is called repeatedly until it returns pdFALSE\r
+ (indicating there is no more output) as it might generate more than\r
+ one string. */\r
+ do\r
+ {\r
+ /* Get the next output string from the command interpreter. */\r
+ xReturned = FreeRTOS_CLIProcessCommand( cInputString, pcOutputString, configCOMMAND_INT_MAX_OUTPUT_SIZE );\r
+\r
+ /* Write the generated string to the UART. */\r
+ vSerialPutString( NULL, pcOutputString, strlen( ( char * ) pcOutputString ) );\r
+\r
+ } while( xReturned != pdFALSE );\r
+\r
+ /* All the strings generated by the input command have been sent.\r
+ Clear the input string ready to receive the next command. Remember\r
+ the command that was just processed first in case it is to be\r
+ processed again. */\r
+ strcpy( ( char * ) cLastInputString, ( char * ) cInputString );\r
+ cInputIndex = 0;\r
+ memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );\r
+ vSerialPutString( NULL, pcEndOfOutputMessage, strlen( ( char * ) pcEndOfOutputMessage ) );\r
+ }\r
+ else\r
+ {\r
+ if( cRxedChar == '\r' )\r
+ {\r
+ /* Ignore the character. */\r
+ }\r
+ else if( cRxedChar == '\b' )\r
+ {\r
+ /* Backspace was pressed. Erase the last character in the\r
+ string - if any. */\r
+ if( cInputIndex > 0 )\r
+ {\r
+ cInputIndex--;\r
+ cInputString[ cInputIndex ] = '\0';\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* A character was entered. Add it to the string\r
+ entered so far. When a \n is entered the complete\r
+ string will be passed to the command interpreter. */\r
+ if( ( cRxedChar >= ' ' ) && ( cRxedChar <= '~' ) )\r
+ {\r
+ if( cInputIndex < cmdMAX_INPUT_SIZE )\r
+ {\r
+ cInputString[ cInputIndex ] = cRxedChar;\r
+ cInputIndex++;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+#ifndef UART_COMMAND_CONSOLE_H\r
+#define UART_COMMAND_CONSOLE_H\r
+\r
+/*\r
+ * Create the task that implements a command console using the USB virtual com\r
+ * port driver for intput and output.\r
+ */\r
+void vUARTCommandConsoleStart( unsigned short usStackSize, unsigned portBASE_TYPE uxPriority );\r
+\r
+#endif /* UART_COMMAND_CONSOLE_H */\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ * FreeRTOS+FAT FS V1.0.0 (C) 2013 HCC Embedded\r
+ *\r
+ * FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers\r
+ * Ltd. by HCC Embedded for use with FreeRTOS. It is not, in itself, part of\r
+ * the FreeRTOS kernel. FreeRTOS+FAT SL is licensed separately from FreeRTOS,\r
+ * and uses a different license to FreeRTOS. FreeRTOS+FAT SL uses a dual\r
+ * license model, information on which is provided below:\r
+ *\r
+ * - Open source licensing -\r
+ * FreeRTOS+FAT SL is a free download and may be used, modified and distributed\r
+ * without charge provided the user adheres to version two of the GNU General\r
+ * Public license (GPL) and does not remove the copyright notice or this text.\r
+ * The GPL V2 text is available on the gnu.org web site, and on the following\r
+ * URL: http://www.FreeRTOS.org/gpl-2.0.txt\r
+ *\r
+ * - Commercial licensing -\r
+ * Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into\r
+ * proprietary software for redistribution in any form must first obtain a\r
+ * commercial license - and in-so-doing support the maintenance, support and\r
+ * further development of the FreeRTOS+FAT SL product. Commercial licenses can\r
+ * be obtained from http://shop.freertos.org and do not require any source files\r
+ * to be changed.\r
+ *\r
+ * FreeRTOS+FAT SL is distributed in the hope that it will be useful. You\r
+ * cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as\r
+ * is'. FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the\r
+ * implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A\r
+ * PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all\r
+ * conditions and terms, be they implied, expressed, or statutory.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://www.FreeRTOS.org/FreeRTOS-Plus\r
+ *\r
+ */\r
+\r
+#ifndef _CONFIG_FAT_SL_H\r
+#define _CONFIG_FAT_SL_H\r
+\r
+#include "../version/ver_fat_sl.h"\r
+#if VER_FAT_SL_MAJOR != 3 || VER_FAT_SL_MINOR != 2\r
+ #error Incompatible FAT_SL version number!\r
+#endif\r
+\r
+#include "../api/api_mdriver.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/**************************************************************************\r
+**\r
+** FAT SL user settings\r
+**\r
+**************************************************************************/\r
+#define F_SECTOR_SIZE 512u /* Disk sector size. */\r
+#define F_FS_THREAD_AWARE 0 /* Set to one if the file system will be access from more than one task. */\r
+#define F_MAXPATH 64 /* Maximum length a file name (including its full path) can be. */\r
+#define F_MAX_LOCK_WAIT_TICKS 20 /* The maximum number of RTOS ticks to wait when attempting to obtain a lock on the file system when F_FS_THREAD_AWARE is set to 1. */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _CONFIG_FAT_SL_H */\r
+\r
--- /dev/null
+/*\r
+ * FreeRTOS+FAT FS V1.0.0 (C) 2013 HCC Embedded\r
+ *\r
+ * FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers\r
+ * Ltd. by HCC Embedded for use with FreeRTOS. It is not, in itself, part of\r
+ * the FreeRTOS kernel. FreeRTOS+FAT SL is licensed separately from FreeRTOS,\r
+ * and uses a different license to FreeRTOS. FreeRTOS+FAT SL uses a dual\r
+ * license model, information on which is provided below:\r
+ *\r
+ * - Open source licensing -\r
+ * FreeRTOS+FAT SL is a free download and may be used, modified and distributed\r
+ * without charge provided the user adheres to version two of the GNU General\r
+ * Public license (GPL) and does not remove the copyright notice or this text.\r
+ * The GPL V2 text is available on the gnu.org web site, and on the following\r
+ * URL: http://www.FreeRTOS.org/gpl-2.0.txt\r
+ *\r
+ * - Commercial licensing -\r
+ * Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into\r
+ * proprietary software for redistribution in any form must first obtain a\r
+ * commercial license - and in-so-doing support the maintenance, support and\r
+ * further development of the FreeRTOS+FAT SL product. Commercial licenses can\r
+ * be obtained from http://shop.freertos.org and do not require any source files\r
+ * to be changed.\r
+ *\r
+ * FreeRTOS+FAT SL is distributed in the hope that it will be useful. You\r
+ * cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as\r
+ * is'. FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the\r
+ * implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A\r
+ * PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all\r
+ * conditions and terms, be they implied, expressed, or statutory.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://www.FreeRTOS.org/FreeRTOS-Plus\r
+ *\r
+ */\r
+\r
+#ifndef _CONFIG_MDRIVER_RAM_H_\r
+#define _CONFIG_MDRIVER_RAM_H_\r
+\r
+#include "../version/ver_mdriver_ram.h"\r
+#if VER_MDRIVER_RAM_MAJOR != 1 || VER_MDRIVER_RAM_MINOR != 2\r
+ #error Incompatible MDRIVER_RAM version number!\r
+#endif\r
+\r
+#define MDRIVER_RAM_SECTOR_SIZE 512 /* Sector size */\r
+\r
+#define MDRIVER_RAM_VOLUME0_SIZE (64 * 1024) /* defintion for size of ramdrive0 */\r
+\r
+#define MDRIVER_MEM_LONG_ACCESS 1 /* set this value to 1 if 32bit access available */\r
+\r
+#endif /* ifndef _CONFIG_MDRIVER_RAM_H_ */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the comprehensive test and demo version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ *\r
+ * NOTE 3: If mainINCLUDE_FAT_SL_DEMO is set to 1 then the UART is used to\r
+ * interface to the FreeRTOS+CLI command line interface. If\r
+ * mainINCLUDE_FAT_SL_DEMO is set to 0 then the UART is used to run the standard\r
+ * COM test tasks and a loopback connector must be fitted to the UART port\r
+ * because the test expects to receive every character that is transmitted. A\r
+ * simple loopback connector can be created by linking pins 2 and 3 of the 9 way\r
+ * UART connector.\r
+ ******************************************************************************\r
+ *\r
+ * main_full() creates all the demo application tasks and software timers, then\r
+ * starts the scheduler. The web documentation provides more details of the\r
+ * standard demo application tasks, which provide no particular functionality,\r
+ * but do provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * FreeRTOS+CLI command console. The command console is access through UART2\r
+ * using 115200 baud if mainINCLUDE_FAT_SL_DEMO is set to 1. For reasons of\r
+ * robustness testing the UART driver is deliberately written to be inefficient\r
+ * and should not be used as a template for a production driver. Type "help" to\r
+ * see a list of registered commands. The FreeRTOS+CLI license is different to\r
+ * the FreeRTOS license, see http://www.FreeRTOS.org/cli for license and usage\r
+ * details.\r
+ *\r
+ * FreeRTOS+FAT SL. FreeRTOS+FAT SL is demonstrated using a RAM disk if\r
+ * mainINCLUDE_FAT_SL_DEMO is set to 1. [At the time of writing] The\r
+ * functionality of the file system demo is identical to the functionality of\r
+ * the FreeRTOS Win32 simulator file system demo, with the command console being\r
+ * accessed via the UART (as described above) instead of a network terminal.\r
+ * The FreeRTOS+FAT SL license is different to the FreeRTOS license, see\r
+ * http://www.FreeRTOS.org/fat_sl for license and usage details, and a\r
+ * description of the file system demo functionality.\r
+ *\r
+ * "Reg test" tasks - These fill both the core and floating point registers with\r
+ * known values, then check that each register maintains its expected value for\r
+ * the lifetime of the task. Each task uses a different set of values. The reg\r
+ * test tasks execute with a very low priority, so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ * "Check" task - The check task period is initially set to three seconds. The\r
+ * task checks that all the standard demo tasks, and the register check tasks,\r
+ * are not only still executing, but are executing without reporting any errors.\r
+ * If the check task discovers that a task has either stalled, or reported an\r
+ * error, then it changes its own execution period from the initial three\r
+ * seconds, to just 200ms. The check task also toggles an LED each time it is\r
+ * called. This provides a visual indication of the system status: If the LED\r
+ * toggles every three seconds, then no issues have been discovered. If the LED\r
+ * toggles every 200ms, then an issue has been discovered with at least one\r
+ * task.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo application includes. */\r
+#include "flop.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+#include "partest.h"\r
+#include "comtest2.h"\r
+#include "serial.h"\r
+#include "TimerDemo.h"\r
+\r
+/* FreeRTOS+CLI and FreeRTOS+FAT SL includes. */\r
+#include "UARTCommandConsole.h"\r
+\r
+/* Either the FreeRTOS+FAT SL demo or the COM test demo can be build into the\r
+project, not both (because they use the same UART). Set\r
+configINCLUDE_FAT_SL_DEMO to 1 to include the FreeRTOS+FAT SL (and therefore\r
+also FreeRTOS+CLI) demo in the build. Set configINCLUDE_FAT_SL_DEMO to 0 to\r
+include the COM test tasks. The COM test tasks require a loop back connector\r
+to be fitted to the UART port. */\r
+#define mainINCLUDE_FAT_SL_DEMO 0\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL )\r
+#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+\r
+/* The priority used by the UART command console task. */\r
+#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )\r
+\r
+/* The LED used by the check timer. */\r
+#define mainCHECK_LED ( 0 )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* In this example the baud rate is hard coded and there is no LED for use by\r
+the COM test tasks, so just set both to invalid values. */\r
+#define mainCOM_TEST_LED ( 100 )\r
+#define mainBAUD_RATE ( 0 )\r
+\r
+/* The period after which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_RATE_MS constant. */\r
+#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_RATE_MS constant. */\r
+#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_RATE_MS )\r
+\r
+/* Parameters that are passed into the register check tasks solely for the\r
+purpose of ensuring parameters are passed into tasks correctly. */\r
+#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )\r
+#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )\r
+\r
+/* The base period used by the timer test tasks. */\r
+#define mainTIMER_TEST_PERIOD ( 50 )\r
+\r
+/* The length of queues used to pass characters into and out of the UART\r
+interrupt. Note the comments above about the UART driver being implemented in\r
+this way to test the kernel robustness rather than to provide a template for an\r
+efficient production driver. */\r
+#define mainUART_QUEUE_LENGTHS 10\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by main() to run the full demo (as opposed to the blinky demo) when\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+void main_full( void );\r
+\r
+/*\r
+ * The check task, as described at the top of this file.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * Register check tasks, and the tasks used to write over and check the contents\r
+ * of the FPU registers, as described at the top of this file. The nature of\r
+ * these files necessitates that they are written in an assembly file, but the\r
+ * entry points are kept in the C file for the convenience of checking the task\r
+ * parameter.\r
+ */\r
+static void prvRegTestTaskEntry1( void *pvParameters );\r
+extern void vRegTest1Implementation( void );\r
+static void prvRegTestTaskEntry2( void *pvParameters );\r
+extern void vRegTest2Implementation( void );\r
+\r
+/*\r
+ * Register commands that can be used with FreeRTOS+CLI. The commands are\r
+ * defined in CLI-Commands.c and File-Related-CLI-Command.c respectively.\r
+ */\r
+extern void vRegisterSampleCLICommands( void );\r
+extern void vRegisterFileSystemCLICommands( void );\r
+\r
+/*\r
+ * Creates and verifies different files on the volume, demonstrating the use of\r
+ * various different API functions.\r
+ */\r
+extern void vCreateAndVerifySampleFiles( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The following two variables are used to communicate the status of the\r
+register check tasks to the check software timer. If the variables keep\r
+incrementing, then the register check tasks has not discovered any errors. If\r
+a variable stops incrementing, then an error has been found. */\r
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+ /* The baud rate setting here has no effect, hence it is set to 0 to\r
+ make that obvious. */\r
+ xSerialPortInitMinimal( 0, mainUART_QUEUE_LENGTHS );\r
+\r
+ /* If the file system is only going to be accessed from one task then\r
+ F_FS_THREAD_AWARE can be set to 0 and the set of example files are created\r
+ before the RTOS scheduler is started. If the file system is going to be\r
+ access from more than one task then F_FS_THREAD_AWARE must be set to 1 and\r
+ the set of sample files are created from the idle task hook function\r
+ vApplicationIdleHook() - which is defined in this file. */\r
+ #if ( mainINCLUDE_FAT_SL_DEMO == 1 )&& ( F_FS_THREAD_AWARE == 0 )\r
+ {\r
+ /* Initialise the drive and file system, then create a few example\r
+ files. The output from this function just goes to the stdout window,\r
+ allowing the output to be viewed when the UDP command console is not\r
+ connected. */\r
+ vCreateAndVerifySampleFiles();\r
+ }\r
+ #endif\r
+\r
+ /* Start all the other standard demo/test tasks. The have not particular\r
+ functionality, but do demonstrate how to use the FreeRTOS API and test the\r
+ kernel port. */\r
+ vStartDynamicPriorityTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
+ vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
+\r
+ #if mainINCLUDE_FAT_SL_DEMO == 1\r
+ {\r
+ /* Start the tasks that implements the command console on the UART, as\r
+ described above. */\r
+ vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY );\r
+\r
+ /* Register both the standard and file system related CLI commands. */\r
+ vRegisterSampleCLICommands();\r
+ vRegisterFileSystemCLICommands();\r
+ }\r
+ #else\r
+ {\r
+ /* The COM test tasks can use the UART if the CLI is not used by the\r
+ FAT SL demo. The COM test tasks require a UART connector to be fitted\r
+ to the UART port. */\r
+ vAltStartComTestTasks( mainCOM_TEST_TASK_PRIORITY, mainBAUD_RATE, mainCOM_TEST_LED );\r
+ }\r
+ #endif\r
+\r
+\r
+ /* Create the register check tasks, as described at the top of this\r
+ file */\r
+ xTaskCreate( prvRegTestTaskEntry1, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTestTaskEntry2, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the task that performs the 'check' functionality, as described at\r
+ the top of this file. */\r
+ xTaskCreate( prvCheckTask, ( signed char * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* The set of tasks created by the following function call have to be\r
+ created last as they keep account of the number of tasks they expect to see\r
+ running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;\r
+portTickType xLastExecutionTime;\r
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
+ works correctly. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. The onboard LED is toggled on each iteration.\r
+ If an error is detected then the delay period is decreased from\r
+ mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the\r
+ effect of increasing the rate at which the onboard LED toggles, and in so\r
+ doing gives visual feedback of the system status. */\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. */\r
+ vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none have detected an error. */\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreTimerDemoTasksStillRunning( ( portTickType ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ #if mainINCLUDE_FAT_SL_DEMO == 0\r
+ {\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+ }\r
+ #endif\r
+\r
+ /* Check that the register test 1 task is still running. */\r
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+ ulLastRegTest1Value = ulRegTest1LoopCounter;\r
+\r
+ /* Check that the register test 2 task is still running. */\r
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+ ulLastRegTest2Value = ulRegTest2LoopCounter;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash the LED\r
+ at a higher frequency to give visible feedback that something has\r
+ gone wrong (it might just be that the loop back connector required\r
+ by the comtest tasks has not been fitted). */\r
+ xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTestTaskEntry1( void *pvParameters )\r
+{\r
+ /* Although the regtest task is written in assembler, its entry point is\r
+ written in C for convenience of checking the task parameter is being passed\r
+ in correctly. */\r
+ if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )\r
+ {\r
+ /* The reg test task also tests the floating point registers. Tasks\r
+ that use the floating point unit must call vPortTaskUsesFPU() before\r
+ any floating point instructions are executed. */\r
+ vPortTaskUsesFPU();\r
+\r
+ /* Start the part of the test that is written in assembler. */\r
+ vRegTest1Implementation();\r
+ }\r
+\r
+ /* The following line will only execute if the task parameter is found to\r
+ be incorrect. The check timer will detect that the regtest loop counter is\r
+ not being incremented and flag an error. */\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTestTaskEntry2( void *pvParameters )\r
+{\r
+ /* Although the regtest task is written in assembler, its entry point is\r
+ written in C for convenience of checking the task parameter is being passed\r
+ in correctly. */\r
+ if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )\r
+ {\r
+ /* The reg test task also tests the floating point registers. Tasks\r
+ that use the floating point unit must call vPortTaskUsesFPU() before\r
+ any floating point instructions are executed. */\r
+ vPortTaskUsesFPU();\r
+\r
+ /* Start the part of the test that is written in assembler. */\r
+ vRegTest2Implementation();\r
+ }\r
+\r
+ /* The following line will only execute if the task parameter is found to\r
+ be incorrect. The check timer will detect that the regtest loop counter is\r
+ not being incremented and flag an error. */\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
--- /dev/null
+;/*\r
+; FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+;\r
+; FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+; http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * FreeRTOS tutorial books are available in pdf and paperback. *\r
+; * Complete, revised, and edited pdf reference manuals are also *\r
+; * available. *\r
+; * *\r
+; * Purchasing FreeRTOS documentation will not only help you, by *\r
+; * ensuring you get running as quickly as possible and with an *\r
+; * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+; * the FreeRTOS project to continue with its mission of providing *\r
+; * professional grade, cross platform, de facto standard solutions *\r
+; * for microcontrollers - completely free of charge! *\r
+; * *\r
+; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+; * *\r
+; * Thank you for using FreeRTOS, and thank you for your support! *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+;\r
+; This file is part of the FreeRTOS distribution.\r
+;\r
+; FreeRTOS is free software; you can redistribute it and/or modify it under\r
+; the terms of the GNU General Public License (version 2) as published by the\r
+; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+;\r
+; >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+; distribute a combined work that includes FreeRTOS without being obliged to\r
+; provide the source code for proprietary components outside of the FreeRTOS\r
+; kernel.\r
+;\r
+; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+; FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+; details. You should have received a copy of the GNU General Public License\r
+; and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+; viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+; writing to Real Time Engineers Ltd., contact details for whom are available\r
+; on the FreeRTOS WEB site.\r
+;\r
+; 1 tab == 4 spaces!\r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * Having a problem? Start by reading the FAQ "My application does *\r
+; * not run, what could be wrong?" *\r
+; * *\r
+; * http://www.FreeRTOS.org/FAQHelp.html *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+;\r
+; http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+; license and Real Time Engineers Ltd. contact details.\r
+;\r
+; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+; including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+; fully thread aware and reentrant UDP/IP stack.\r
+;\r
+; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+; Integrity Systems, who sell the code with commercial support,\r
+; indemnification and middleware, under the OpenRTOS brand.\r
+;\r
+; http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+; engineered and independently SIL3 certified version for use in safety and\r
+; mission critical applications that require provable dependability.\r
+;*/\r
+\r
+ EXPORT vRegTest1Implementation\r
+ EXPORT vRegTest2Implementation\r
+\r
+ ; This file is built with IAR and ARM compilers. When the ARM compiler\r
+ ; is used the compiler options must define __IASMARM__ as 0 using the\r
+ ; --predefine "__IASMARM__ SETA 0" command line option. When compiling\r
+ ; with IAR __IASMARM__ is automatically set to 1 so no additional assembler\r
+ ; options are required.\r
+ if __IASMARM__ == 1\r
+ ; Syntax for IAR compiler.\r
+ SECTION .text:CODE:ROOT(2)\r
+ else\r
+ ; Syntax for ARM compiler.\r
+ AREA RegTest, CODE, READONLY\r
+ endif\r
+ ARM\r
+\r
+ ; This function is explained in the comments at the top of main-full.c.\r
+vRegTest1Implementation\r
+\r
+ PRESERVE8\r
+ IMPORT ulRegTest1LoopCounter\r
+\r
+ ; Fill each general purpose register with a known value.\r
+ mov r0, #0xFF\r
+ mov r1, #0x11\r
+ mov r2, #0x22\r
+ mov r3, #0x33\r
+ mov r4, #0x44\r
+ mov r5, #0x55\r
+ mov r6, #0x66\r
+ mov r7, #0x77\r
+ mov r8, #0x88\r
+ mov r9, #0x99\r
+ mov r10, #0xAA\r
+ mov r11, #0xBB\r
+ mov r12, #0xCC\r
+ mov r14, #0xEE\r
+\r
+ ; Fill each FPU register with a known value.\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+ vmov d16, r0, r1\r
+ vmov d17, r2, r3\r
+ vmov d18, r4, r5\r
+ vmov d19, r6, r7\r
+ vmov d20, r8, r9\r
+ vmov d21, r10, r11\r
+ vmov d22, r0, r1\r
+ vmov d23, r2, r3\r
+ vmov d24, r4, r5\r
+ vmov d25, r6, r7\r
+ vmov d26, r8, r9\r
+ vmov d27, r10, r11\r
+ vmov d28, r0, r1\r
+ vmov d29, r2, r3\r
+ vmov d30, r4, r5\r
+ vmov d31, r6, r7\r
+\r
+ ; Loop, checking each itteration that each register still contains the\r
+ ; expected value.\r
+reg1_loop\r
+ ; Yield to increase test coverage\r
+ svc 0\r
+\r
+ ; Check all the VFP registers still contain the values set above.\r
+ ; First save registers that are clobbered by the test.\r
+ push { r0-r1 }\r
+\r
+ vmov r0, r1, d0\r
+ cmp r0, #0xFF\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x11\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #0x22\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x33\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #0x44\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x55\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #0x66\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x77\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #0x88\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x99\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #0xAA\r
+ bne reg1_error_loopf\r
+ cmp r1, #0xBB\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #0xFF\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x11\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #0x22\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x33\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #0x44\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x55\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #0x66\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x77\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #0x88\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x99\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #0xAA\r
+ bne reg1_error_loopf\r
+ cmp r1, #0xBB\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #0xFF\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x11\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #0x22\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x33\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #0x44\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x55\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #0x66\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x77\r
+ bne reg1_error_loopf\r
+\r
+ vmov r0, r1, d16\r
+ cmp r0, #0xFF\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x11\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d17\r
+ cmp r0, #0x22\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x33\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d18\r
+ cmp r0, #0x44\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x55\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d19\r
+ cmp r0, #0x66\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x77\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d20\r
+ cmp r0, #0x88\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x99\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d21\r
+ cmp r0, #0xAA\r
+ bne reg1_error_loopf\r
+ cmp r1, #0xBB\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d22\r
+ cmp r0, #0xFF\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x11\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d23\r
+ cmp r0, #0x22\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x33\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d24\r
+ cmp r0, #0x44\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x55\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d25\r
+ cmp r0, #0x66\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x77\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d26\r
+ cmp r0, #0x88\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x99\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d27\r
+ cmp r0, #0xAA\r
+ bne reg1_error_loopf\r
+ cmp r1, #0xBB\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d28\r
+ cmp r0, #0xFF\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x11\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d29\r
+ cmp r0, #0x22\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x33\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d30\r
+ cmp r0, #0x44\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x55\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d31\r
+ cmp r0, #0x66\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x77\r
+ bne reg1_error_loopf\r
+\r
+ ; Restore the registers that were clobbered by the test.\r
+ pop {r0-r1}\r
+\r
+ ; VFP register test passed. Jump to the core register test.\r
+ b reg1_loopf_pass\r
+\r
+reg1_error_loopf\r
+ ; If this line is hit then a VFP register value was found to be\r
+ ; incorrect.\r
+ b reg1_error_loopf\r
+\r
+reg1_loopf_pass\r
+\r
+ ; Test each general purpose register to check that it still contains the\r
+ ; expected known value, jumping to reg1_error_loop if any register contains\r
+ ; an unexpected value.\r
+ cmp r0, #0xFF\r
+ bne reg1_error_loop\r
+ cmp r1, #0x11\r
+ bne reg1_error_loop\r
+ cmp r2, #0x22\r
+ bne reg1_error_loop\r
+ cmp r3, #0x33\r
+ bne reg1_error_loop\r
+ cmp r4, #0x44\r
+ bne reg1_error_loop\r
+ cmp r5, #0x55\r
+ bne reg1_error_loop\r
+ cmp r6, #0x66\r
+ bne reg1_error_loop\r
+ cmp r7, #0x77\r
+ bne reg1_error_loop\r
+ cmp r8, #0x88\r
+ bne reg1_error_loop\r
+ cmp r9, #0x99\r
+ bne reg1_error_loop\r
+ cmp r10, #0xAA\r
+ bne reg1_error_loop\r
+ cmp r11, #0xBB\r
+ bne reg1_error_loop\r
+ cmp r12, #0xCC\r
+ bne reg1_error_loop\r
+ cmp r14, #0xEE\r
+ bne reg1_error_loop\r
+\r
+ ; Everything passed, increment the loop counter.\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest1LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+\r
+ ; Start again.\r
+ b reg1_loop\r
+\r
+reg1_error_loop\r
+ ; If this line is hit then there was an error in a core register value.\r
+ ; The loop ensures the loop counter stops incrementing.\r
+ b reg1_error_loop\r
+ nop\r
+\r
+;/*-----------------------------------------------------------*/\r
+\r
+vRegTest2Implementation\r
+\r
+ PRESERVE8\r
+ IMPORT ulRegTest2LoopCounter\r
+\r
+ ; Put a known value in each register.\r
+ mov r0, #0xFF000000\r
+ mov r1, #0x11000000\r
+ mov r2, #0x22000000\r
+ mov r3, #0x33000000\r
+ mov r4, #0x44000000\r
+ mov r5, #0x55000000\r
+ mov r6, #0x66000000\r
+ mov r7, #0x77000000\r
+ mov r8, #0x88000000\r
+ mov r9, #0x99000000\r
+ mov r10, #0xAA000000\r
+ mov r11, #0xBB000000\r
+ mov r12, #0xCC000000\r
+ mov r14, #0xEE000000\r
+\r
+ ; Likewise the floating point registers\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+ vmov d16, r0, r1\r
+ vmov d17, r2, r3\r
+ vmov d18, r4, r5\r
+ vmov d19, r6, r7\r
+ vmov d20, r8, r9\r
+ vmov d21, r10, r11\r
+ vmov d22, r0, r1\r
+ vmov d23, r2, r3\r
+ vmov d24, r4, r5\r
+ vmov d25, r6, r7\r
+ vmov d26, r8, r9\r
+ vmov d27, r10, r11\r
+ vmov d28, r0, r1\r
+ vmov d29, r2, r3\r
+ vmov d30, r4, r5\r
+ vmov d31, r6, r7\r
+\r
+ ; Loop, checking each itteration that each register still contains the\r
+ ; expected value.\r
+reg2_loop\r
+ ; Check all the VFP registers still contain the values set above.\r
+ ; First save registers that are clobbered by the test.\r
+ push { r0-r1 }\r
+\r
+ vmov r0, r1, d0\r
+ cmp r0, #0xFF000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x11000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #0x22000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x33000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #0x44000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x55000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #0x66000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x77000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #0x88000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x99000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #0xAA000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0xBB000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #0xFF000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x11000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #0x22000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x33000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #0x44000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x55000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #0x66000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x77000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #0x88000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x99000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #0xAA000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0xBB000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #0xFF000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x11000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #0x22000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x33000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #0x44000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x55000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #0x66000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x77000000\r
+ bne reg2_error_loopf\r
+\r
+ vmov r0, r1, d16\r
+ cmp r0, #0xFF000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x11000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d17\r
+ cmp r0, #0x22000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x33000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d18\r
+ cmp r0, #0x44000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x55000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d19\r
+ cmp r0, #0x66000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x77000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d20\r
+ cmp r0, #0x88000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x99000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d21\r
+ cmp r0, #0xAA000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0xBB000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d22\r
+ cmp r0, #0xFF000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x11000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d23\r
+ cmp r0, #0x22000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x33000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d24\r
+ cmp r0, #0x44000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x55000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d25\r
+ cmp r0, #0x66000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x77000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d26\r
+ cmp r0, #0x88000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x99000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d27\r
+ cmp r0, #0xAA000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0xBB000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d28\r
+ cmp r0, #0xFF000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x11000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d29\r
+ cmp r0, #0x22000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x33000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d30\r
+ cmp r0, #0x44000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x55000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d31\r
+ cmp r0, #0x66000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x77000000\r
+ bne reg2_error_loopf\r
+\r
+ ; Restore the registers that were clobbered by the test.\r
+ pop {r0-r1}\r
+\r
+ ; VFP register test passed. Jump to the core register test.\r
+ b reg2_loopf_pass\r
+\r
+reg2_error_loopf\r
+ ; If this line is hit then a VFP register value was found to be\r
+ ; incorrect.\r
+ b reg2_error_loopf\r
+\r
+reg2_loopf_pass\r
+\r
+ cmp r0, #0xFF000000\r
+ bne reg2_error_loop\r
+ cmp r1, #0x11000000\r
+ bne reg2_error_loop\r
+ cmp r2, #0x22000000\r
+ bne reg2_error_loop\r
+ cmp r3, #0x33000000\r
+ bne reg2_error_loop\r
+ cmp r4, #0x44000000\r
+ bne reg2_error_loop\r
+ cmp r5, #0x55000000\r
+ bne reg2_error_loop\r
+ cmp r6, #0x66000000\r
+ bne reg2_error_loop\r
+ cmp r7, #0x77000000\r
+ bne reg2_error_loop\r
+ cmp r8, #0x88000000\r
+ bne reg2_error_loop\r
+ cmp r9, #0x99000000\r
+ bne reg2_error_loop\r
+ cmp r10, #0xAA000000\r
+ bne reg2_error_loop\r
+ cmp r11, #0xBB000000\r
+ bne reg2_error_loop\r
+ cmp r12, #0xCC000000\r
+ bne reg2_error_loop\r
+ cmp r14, #0xEE000000\r
+ bne reg2_error_loop\r
+\r
+ ; Everything passed, increment the loop counter.\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest2LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+\r
+ ; Start again.\r
+ b reg2_loop\r
+\r
+reg2_error_loop\r
+ ; If this line is hit then there was an error in a core register value.\r
+ ; The loop ensures the loop counter stops incrementing.\r
+ b reg2_error_loop\r
+ nop\r
+\r
+\r
+ END\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/*\r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART2.\r
+\r
+ ***Note*** This example uses queues to send each character into an interrupt\r
+ service routine and out of an interrupt service routine individually. This\r
+ is done to demonstrate queues being used in an interrupt, and to deliberately\r
+ load the system to test the FreeRTOS port. It is *NOT* meant to be an\r
+ example of an efficient implementation. An efficient implementation should\r
+ use the DMA, and only use FreeRTOS API functions when enough has been\r
+ received to warrant a task being unblocked to process the data.\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+#include "comtest2.h"\r
+\r
+/* Driver includes. */\r
+#include "r_typedefs.h"\r
+#include "dev_drv.h"\r
+#include "devdrv_scif_uart.h"\r
+#include "sio_char.h"\r
+#include "iodefine.h"\r
+#include "devdrv_intc.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Misc defines. */\r
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Handlers for the Rx and Tx interrupts respectively. */\r
+static void prvRXI_Handler( uint32_t ulUnusedParameter );\r
+static void prvTXI_Handler( uint32_t ulUnusedParameter );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to hold received characters. */\r
+static xQueueHandle xRxedChars;\r
+static xQueueHandle xCharsForTx;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See the serial2.h header file.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+ /* Baud is set in IoInitScif2(), called in prvSetupHardware() in main.c. */\r
+ ( void ) ulWantedBaud;\r
+\r
+ /* Create the queues used to hold Rx/Tx characters. Note the comments at\r
+ the top of this file regarding the use of queues in this manner. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
+\r
+ /* If the queues were created correctly then setup the serial port\r
+ hardware. */\r
+ if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )\r
+ {\r
+ /* Register RXI and TXI handlers. */\r
+ R_INTC_RegistIntFunc( INTC_ID_RXI2, prvRXI_Handler );\r
+ R_INTC_RegistIntFunc( INTC_ID_TXI2, prvTXI_Handler );\r
+\r
+ /* Set both interrupts such that they can interrupt the tick. Also\r
+ set the Rx interrupt above the Tx interrupt in the hope that (for test\r
+ purposes) the Tx interrupt will interrupt the Rx interrupt. */\r
+ R_INTC_SetPriority( INTC_ID_RXI2, configMAX_API_CALL_INTERRUPT_PRIORITY );\r
+ R_INTC_SetPriority( INTC_ID_TXI2, ( configMAX_API_CALL_INTERRUPT_PRIORITY + 1 ) );\r
+\r
+ /* This driver is intended to test interrupt interactions, and not\r
+ intended to be efficient. Therefore set the RX trigger level to 1. */\r
+ SCIF2.SCFCR.BIT.RTRG = 0;\r
+ SCIF2.SCFCR.BIT.TTRG = 3;\r
+\r
+ /* Enable Rx interrupt. Tx interrupt will be enabled when a Tx is\r
+ performed. */\r
+ SCIF2.SCSCR.BIT.RIE = 1;\r
+ R_INTC_Enable( INTC_ID_RXI2 );\r
+ R_INTC_Enable( INTC_ID_TXI2 );\r
+ }\r
+\r
+ /* This demo file only supports a single port but we have to return\r
+ something to comply with the standard demo header file. */\r
+ return ( xComPortHandle ) 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports one port. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+signed char *pxNext;\r
+\r
+ /* A couple of parameters that this port does not use. */\r
+ ( void ) usStringLength;\r
+ ( void ) pxPort;\r
+\r
+ /* Send each character in the string, one at a time. */\r
+ pxNext = ( signed char * ) pcString;\r
+ while( *pxNext )\r
+ {\r
+ xSerialPutChar( pxPort, *pxNext, portMAX_DELAY );\r
+ pxNext++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* Note the comments at the top of this file regarding the use of queues in\r
+ this manner. */\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )\r
+ {\r
+ xReturn = pdPASS;\r
+\r
+ /* Enable the interrupt which will remove the character from the\r
+ queue. */\r
+ SCIF2.SCSCR.BIT.TIE = 1;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ /* Not supported as not required by the demo application. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRXI_Handler( uint32_t ulUnusedParameter )\r
+{\r
+unsigned char ucRxedByte;\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* The parameter is not used. It is only present because Renesas drivers\r
+ are used to install the interrupt handlers, and the drivers expect the\r
+ parameter to be present. */\r
+ ( void ) ulUnusedParameter;\r
+\r
+ /* Note the comments at the top of this file regarding the use of queues in\r
+ this manner. */\r
+ while( ( SCIF2.SCFDR.WORD & 0x1F ) != 0 )\r
+ {\r
+ ucRxedByte = SCIF2.SCFRDR.BYTE;\r
+ xQueueSendFromISR( xRxedChars, &ucRxedByte, &lHigherPriorityTaskWoken );\r
+ }\r
+\r
+ SCIF2.SCFSR.BIT.RDF = 0;\r
+\r
+ /* If sending to the queue has caused a task to unblock, and the unblocked\r
+ task has a priority equal to or higher than the currently running task (the\r
+ task this ISR interrupted), then lHigherPriorityTaskWoken will have\r
+ automatically been set to pdTRUE within the queue send function.\r
+ portYIELD_FROM_ISR() will then ensure that this ISR returns directly to the\r
+ higher priority unblocked task. */\r
+ portYIELD_FROM_ISR( lHigherPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTXI_Handler( uint32_t ulUnusedParameter )\r
+{\r
+unsigned char ucByte;\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* The parameter is not used. It is only present because Renesas drivers\r
+ are used to install the interrupt handlers, and the drivers expect the\r
+ parameter to be present. */\r
+ ( void ) ulUnusedParameter;\r
+\r
+ /* Note the comments at the top of this file regarding the use of queues in\r
+ this manner. */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &ucByte, &lHigherPriorityTaskWoken ) == pdPASS )\r
+ {\r
+ SCIF2.SCFTDR.BYTE = ucByte;\r
+\r
+ /* Clear TDRE and TEND flag */\r
+ SCIF2.SCFSR.WORD &= ~0x0060;\r
+ }\r
+ else\r
+ {\r
+ /* No more characters. Disable the interrupt. */\r
+ SCIF2.SCSCR.BIT.TIE = 0;\r
+ }\r
+\r
+ /* If receiving from the queue has caused a task to unblock, and the\r
+ unblocked task has a priority equal to or higher than the currently running\r
+ task (the task this ISR interrupted), then lHigherPriorityTaskWoken will\r
+ have automatically been set to pdTRUE within the queue receive function.\r
+ portYIELD_FROM_ISR() will then ensure that this ISR returns directly to the\r
+ higher priority unblocked task. */\r
+ portYIELD_FROM_ISR( lHigherPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple IO routines to control the LEDs.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* Hardware specifics. */\r
+#include "iodefine.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Initialise P4_10 for LED1. */\r
+ PORT4.PMCn.BIT.PMCn10 = 0;\r
+ PORT4.Pn.BIT.Pn10 = 1;\r
+ PORT4.PMn.BIT.PMn10 = 0;\r
+ PORT4.PIPCn.BIT.PIPCn10 = 0;\r
+\r
+ /* Initialise P4_11 for LED2. */\r
+ PORT4.PMCn.BIT.PMCn11 = 0;\r
+ PORT4.Pn.BIT.Pn11 = 1;\r
+ PORT4.PMn.BIT.PMn11 = 0;\r
+ PORT4.PIPCn.BIT.PIPCn11 = 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned long ulLED, signed long xValue )\r
+{\r
+ /* A high value turns the LED off. */\r
+ xValue = !xValue;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( ulLED == 0 )\r
+ {\r
+ PORT4.Pn.BIT.Pn10 = xValue;\r
+ }\r
+\r
+ if( ulLED == 1 )\r
+ {\r
+ PORT4.Pn.BIT.Pn11 = xValue;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned long ulLED )\r
+{\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( ulLED == 0 )\r
+ {\r
+ PORT4.Pn.BIT.Pn10 = !PORT4.Pn.BIT.Pn10;\r
+ }\r
+\r
+ if( ulLED == 1 )\r
+ {\r
+ PORT4.Pn.BIT.Pn11 = !PORT4.Pn.BIT.Pn11;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : peripheral_init_basic.c\r
+* $Rev: 17531 $\r
+* $Date:: 2013-04-10 12:58:44 +0100#$\r
+* Device(s) : Aragon\r
+* Tool-Chain : DS-5 Ver 5.8\r
+* : ARM Complier\r
+* OS :\r
+* H/W Platform : Aragon CPU Board\r
+* Description : Aragon Sample Program - Initialize peripheral function sample\r
+* Operation :\r
+* Limitations :\r
+*******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "r_typedefs.h"\r
+#include "devdrv_common.h" /* Common Driver Header */\r
+#include "iodefine.h"\r
+\r
+/* Do not include the following pragmas when compiling with IAR. */\r
+#ifndef __ICCARM__\r
+ #pragma arm section code = "CODE_BASIC_SETUP"\r
+ #pragma arm section rodata = "CONST_BASIC_SETUP"\r
+ #pragma arm section rwdata = "DATA_BASIC_SETUP"\r
+ #pragma arm section zidata = "BSS_BASIC_SETUP"\r
+#endif\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+void Peripheral_BasicInit(void);\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+static void CPG_Init(void);\r
+static void CS0_PORTInit(void);\r
+\r
+\r
+/******************************************************************************\r
+* Function Name: PeripheralBasicInit\r
+* Description :\r
+* :\r
+* :\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void Peripheral_BasicInit(void)\r
+{\r
+ /* ==== Clock Pulse Generator (CPG) setting ====*/\r
+ CPG_Init();\r
+\r
+ /* ==== Port setting ==== */\r
+ CS0_PORTInit();\r
+\r
+ /* ==== Bus State Controller (BSC) setting ==== */\r
+ R_BSC_Init((uint8_t)(BSC_AREA_CS0 | BSC_AREA_CS1));\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: CPG_Init\r
+* Description :\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+static void CPG_Init(void)\r
+{\r
+ volatile uint32_t dummy_buf_32b;\r
+ volatile uint8_t dummy_buf_8b;\r
+\r
+ *(volatile uint32_t *)(0x3fffff80) = 0x00000001;\r
+ dummy_buf_32b = *(volatile uint32_t *)(0x3fffff80);\r
+\r
+ /* ==== CPG Settings ==== */\r
+ CPG.FRQCR.WORD = 0x1035u; /* PLL(x30), I:G:B:P1:P0 = 30:20:10:5:5/2 */\r
+ CPG.FRQCR2.WORD = 0x0001u; /* CKIO:Output at time usually, */\r
+ /* Output when bus right is opened, */\r
+ /* output at standby"L" */\r
+ /* Clockin = 13.33MHz, CKIO = 66.67MHz, */\r
+ /* I Clock = 400.00MHz, */\r
+ /* G Clock = 266.67MHz, */\r
+ /* B Clock = 133.33MHz, */\r
+ /* P1 Clock = 66.67MHz, */\r
+ /* P0 Clock = 33.33MHz */\r
+\r
+ /* ---- Writing to On-Chip Data-Retention RAM is enabled. ---- */\r
+ CPG.SYSCR3.BYTE = 0x0Fu;\r
+ dummy_buf_8b = CPG.SYSCR3.BYTE;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: CS0_PORTInit\r
+* Description :\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+static void CS0_PORTInit(void)\r
+{\r
+ /* ==== BSC settings ==== */\r
+\r
+ /* ---- P9_1 : A25 ---- */\r
+ PORT9.PMCn.BIT.PMCn1 = 1;\r
+ PORT9.PFCAEn.BIT.PFCAEn1 = 0;\r
+ PORT9.PFCEn.BIT.PFCEn1 = 0;\r
+ PORT9.PFCn.BIT.PFCn1 = 0;\r
+ PORT9.PIPCn.BIT.PIPCn1 = 1;\r
+\r
+ /* ---- P9_0 : A24 ---- */\r
+ PORT9.PMCn.BIT.PMCn0 = 1;\r
+ PORT9.PFCAEn.BIT.PFCAEn0 = 0;\r
+ PORT9.PFCEn.BIT.PFCEn0 = 0;\r
+ PORT9.PFCn.BIT.PFCn0 = 0;\r
+ PORT9.PIPCn.BIT.PIPCn0 = 1;\r
+\r
+ /* ---- P8_15 : A23 ---- */\r
+ PORT8.PMCn.BIT.PMCn15 = 1;\r
+ PORT8.PFCAEn.BIT.PFCAEn15 = 0;\r
+ PORT8.PFCEn.BIT.PFCEn15 = 0;\r
+ PORT8.PFCn.BIT.PFCn15 = 0;\r
+ PORT8.PIPCn.BIT.PIPCn15 = 1;\r
+\r
+ /* ---- P8_14 : A22 ---- */\r
+ PORT8.PMCn.BIT.PMCn14 = 1;\r
+ PORT8.PFCAEn.BIT.PFCAEn14 = 0;\r
+ PORT8.PFCEn.BIT.PFCEn14 = 0;\r
+ PORT8.PFCn.BIT.PFCn14 = 0;\r
+ PORT8.PIPCn.BIT.PIPCn14 = 1;\r
+\r
+ /* ---- P8_13 : A21 ---- */\r
+ PORT8.PMCn.BIT.PMCn13 = 1;\r
+ PORT8.PFCAEn.BIT.PFCAEn13 = 0;\r
+ PORT8.PFCEn.BIT.PFCEn13 = 0;\r
+ PORT8.PFCn.BIT.PFCn13 = 0;\r
+ PORT8.PIPCn.BIT.PIPCn13 = 1;\r
+\r
+ /* ---- P7_6 : WE0# / DQMLL# ---- */\r
+ PORT7.PMCn.BIT.PMCn6 = 1;\r
+ PORT7.PFCAEn.BIT.PFCAEn6 = 0;\r
+ PORT7.PFCEn.BIT.PFCEn6 = 0;\r
+ PORT7.PFCn.BIT.PFCn6 = 0;\r
+ PORT7.PIPCn.BIT.PIPCn6 = 1;\r
+\r
+ /* ---- P7_8 : RD ---- */\r
+ PORT7.PMCn.BIT.PMCn8 = 1;\r
+ PORT7.PFCAEn.BIT.PFCAEn8 = 0;\r
+ PORT7.PFCEn.BIT.PFCEn8 = 0;\r
+ PORT7.PFCn.BIT.PFCn8 = 0;\r
+ PORT7.PIPCn.BIT.PIPCn8 = 1;\r
+\r
+ /* ---- P7_0 : CS0 ---- */\r
+ PORT7.PMCn.BIT.PMCn0 = 1;\r
+ PORT7.PFCAEn.BIT.PFCAEn0 = 0;\r
+ PORT7.PFCEn.BIT.PFCEn0 = 0;\r
+ PORT7.PFCn.BIT.PFCn0 = 0;\r
+ PORT7.PIPCn.BIT.PIPCn0 = 1;\r
+\r
+ /* ---- P3_7 : CS1 ---- */\r
+ PORT3.PMCn.BIT.PMCn7 = 1;\r
+ PORT3.PFCAEn.BIT.PFCAEn7 = 1;\r
+ PORT3.PFCEn.BIT.PFCEn7 = 1;\r
+ PORT3.PFCn.BIT.PFCn7 = 0;\r
+ PORT3.PIPCn.BIT.PIPCn7 = 1;\r
+}\r
+\r
+/* End of File */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : port_init.c\r
+* $Rev: 17531 $\r
+* $Date:: 2013-04-10 12:58:44 +0100#$\r
+* Device(s) : Aragon\r
+* Tool-Chain : DS-5 Ver 5.8\r
+* : ARM Complier\r
+* OS :\r
+* H/W Platform : Aragon CPU Board\r
+* Description : Aragon Sample Program - Initialize peripheral function sample\r
+* Operation :\r
+* Limitations :\r
+*******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "r_typedefs.h"\r
+#include "devdrv_common.h" /* Common Driver Header */\r
+#include "port_init.h"\r
+#include "iodefine.h"\r
+\r
+/* Do not include the following pragmas when compiling with IAR. */\r
+#ifndef __ICCARM__\r
+ #pragma arm section code = "CODE_RESET"\r
+ #pragma arm section rodata = "CONST_RESET"\r
+ #pragma arm section rwdata = "DATA_RESET"\r
+ #pragma arm section zidata = "BSS_RESET"\r
+#endif\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* Function Name: PORT_Init\r
+* Description :\r
+* :\r
+* :\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void PORT_Init(void)\r
+{\r
+ /* ==== BSC settings ==== */\r
+\r
+ /* ---- P7_2 : RAS# ---- */\r
+ PORT7.PMCn.BIT.PMCn2 = 1;\r
+ PORT7.PFCAEn.BIT.PFCAEn2 = 0;\r
+ PORT7.PFCEn.BIT.PFCEn2 = 0;\r
+ PORT7.PFCn.BIT.PFCn2 = 0;\r
+ PORT7.PIPCn.BIT.PIPCn2 = 1;\r
+\r
+ /* ---- P7_3 : CAS# ---- */\r
+ PORT7.PMCn.BIT.PMCn3 = 1;\r
+ PORT7.PFCAEn.BIT.PFCAEn3 = 0;\r
+ PORT7.PFCEn.BIT.PFCEn3 = 0;\r
+ PORT7.PFCn.BIT.PFCn3 = 0;\r
+ PORT7.PIPCn.BIT.PIPCn3 = 1;\r
+\r
+ /* ---- P7_4 : CKE ---- */\r
+ PORT7.PMCn.BIT.PMCn4 = 1;\r
+ PORT7.PFCAEn.BIT.PFCAEn4 = 0;\r
+ PORT7.PFCEn.BIT.PFCEn4 = 0;\r
+ PORT7.PFCn.BIT.PFCn4 = 0;\r
+ PORT7.PIPCn.BIT.PIPCn4 = 1;\r
+\r
+ /* ---- P7_5 : RD/WR# ---- */\r
+ PORT7.PMCn.BIT.PMCn5 = 1;\r
+ PORT7.PFCAEn.BIT.PFCAEn5 = 0;\r
+ PORT7.PFCEn.BIT.PFCEn5 = 0;\r
+ PORT7.PFCn.BIT.PFCn5 = 0;\r
+ PORT7.PIPCn.BIT.PIPCn5 = 1;\r
+\r
+ /* ---- P7_7 : DQMLU# ---- */\r
+ PORT7.PMCn.BIT.PMCn7 = 1;\r
+ PORT7.PFCAEn.BIT.PFCAEn7 = 0;\r
+ PORT7.PFCEn.BIT.PFCEn7 = 0;\r
+ PORT7.PFCn.BIT.PFCn7 = 0;\r
+ PORT7.PIPCn.BIT.PIPCn7 = 1;\r
+\r
+ /* ---- P5_8 : CS2 ---- */\r
+ PORT5.PMCn.BIT.PMCn8 = 1;\r
+ PORT5.PFCAEn.BIT.PFCAEn8 = 1;\r
+ PORT5.PFCEn.BIT.PFCEn8 = 0;\r
+ PORT5.PFCn.BIT.PFCn8 = 1;\r
+ PORT5.PIPCn.BIT.PIPCn8 = 1;\r
+\r
+ /* ---- P7_1 : CS3 ---- */\r
+ PORT7.PMCn.BIT.PMCn1 = 1;\r
+ PORT7.PFCAEn.BIT.PFCAEn1 = 0;\r
+ PORT7.PFCEn.BIT.PFCEn1 = 0;\r
+ PORT7.PFCn.BIT.PFCn1 = 0;\r
+ PORT7.PIPCn.BIT.PIPCn1 = 1;\r
+}\r
+\r
+/* End of File */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : siochar.c\r
+* $Rev: 17531 $\r
+* $Date:: 2013-04-10 12:58:44 +0100#$\r
+* Device(s) : Aragon\r
+* Tool-Chain : DS-5 Ver 5.8\r
+* : ARM Complier\r
+* OS : \r
+* H/W Platform : Aragon CPU Board\r
+* Description : Aragon Sample Program - Serial I/O character R/W (SCIF 2-ch process)\r
+* Operation : \r
+* Limitations : \r
+*******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "r_typedefs.h"\r
+#include "dev_drv.h" /* Device Driver common header */\r
+#include "devdrv_scif_uart.h" /* UART Driver header */\r
+#include "sio_char.h"\r
+#include "iodefine.h"\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* Function Name: IoInitScif2\r
+* Description : This function initializes SCIF channel 2 as UART mode.\r
+* : The transmit and the receive of SCIF channel 2 are enabled.\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void IoInitScif2(void)\r
+{\r
+ /* P1=66.67MHz CKS=0 SCBRR=17 Bit rate error=0.46% => Baud rate=115200bps */\r
+ R_SCIF_UART_Init(DEVDRV_CH_2, SCIF_UART_MODE_RW, 0, 17);\r
+\r
+ /* === PORT ==== */\r
+ /* ---- P3_0 : TxD2 ---- */\r
+ PORT3.PMCn.BIT.PMCn0 = 1;\r
+ PORT3.PFCAEn.BIT.PFCAEn0 = 1;\r
+ PORT3.PFCEn.BIT.PFCEn0 = 0;\r
+ PORT3.PFCn.BIT.PFCn0 = 1;\r
+ PORT3.PIPCn.BIT.PIPCn0 = 1;\r
+\r
+ /* ---- P3_2 : RxD2 ---- */\r
+ PORT3.PMCn.BIT.PMCn2 = 1;\r
+ PORT3.PFCAEn.BIT.PFCAEn2 = 0;\r
+ PORT3.PFCEn.BIT.PFCEn2 = 1;\r
+ PORT3.PFCn.BIT.PFCn2 = 1;\r
+ PORT3.PIPCn.BIT.PIPCn2 = 1;\r
+\r
+ /* ---- Serial control register (SCSCRi) setting ---- */\r
+ SCIF2.SCSCR.WORD = 0x0030;\r
+ /* SCIF2 transmitting and receiving operations are enabled */\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: IoGetchar\r
+* Description : One character is received from SCIF2, and it's data is returned.\r
+* : This function keeps waiting until it can obtain the receiving data.\r
+* Arguments : none\r
+* Return Value : Character to receive (Byte).\r
+******************************************************************************/\r
+char_t IoGetchar(void)\r
+{\r
+ char_t data;\r
+\r
+ /* Confirming receive error(ER,DR,BRK) */\r
+ if (SCIF2.SCFSR.WORD & 0x09C)\r
+ {\r
+ /* Detect receive error */\r
+ SCIF2.SCSCR.BIT.RE = 0; /* Disable reception */\r
+ SCIF2.SCFCR.BIT.RFRST = 1; /* Reset receiving FIFO */\r
+ SCIF2.SCFCR.BIT.RFRST = 0; /* Clearing FIFO reception reset */\r
+ SCIF2.SCFSR.WORD &= ~0x9C; /* Error bit clear */\r
+ SCIF2.SCSCR.BIT.RE = 1; /* Enable reception */\r
+ return 0;\r
+ }\r
+\r
+ /* Is there receive FIFO data? */\r
+ while (0 == SCIF2.SCFSR.BIT.RDF)\r
+ {\r
+ /* WAIT */\r
+ }\r
+\r
+ /* Read receive data */\r
+ data = SCIF2.SCFRDR.BYTE;\r
+ /* Clear RDF */\r
+ SCIF2.SCFSR.BIT.RDF = 0;\r
+\r
+ /* Is it overflowed? */\r
+ if (1 == SCIF2.SCLSR.BIT.ORER)\r
+ {\r
+ SCIF2.SCLSR.BIT.ORER = 0; /* ORER clear */\r
+ }\r
+\r
+ return data;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: IoPutchar\r
+* Description : Character "buffer" is output to SCIF2.\r
+* : This function keeps waiting until it becomes the transmission\r
+* : enabled state.\r
+* Arguments : char_t buffer : character to output\r
+* Return Value : None\r
+******************************************************************************/\r
+void IoPutchar(char_t buffer)\r
+{\r
+ /* Check if it is possible to transmit (TDFE flag) */\r
+ while (0 == SCIF2.SCFSR.BIT.TDFE)\r
+ {\r
+ /* Wait */\r
+ }\r
+\r
+ /* Write the receiving data in TDR */\r
+ SCIF2.SCFTDR.BYTE = buffer;\r
+\r
+ /* Clear TDRE and TEND flag */\r
+ SCIF2.SCFSR.WORD &= ~0x0060;\r
+}\r
+\r
+\r
+/* End of File */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : stb_init.c\r
+* $Rev: 17531 $\r
+* $Date:: 2013-04-10 12:58:44 +0100#$\r
+* Device(s) : Aragon\r
+* Tool-Chain : DS-5 Ver 5.8\r
+* : ARM Complier\r
+* OS :\r
+* H/W Platform : Aragon CPU Board\r
+* Description : Aragon Sample Program - Initialize peripheral function sample\r
+* Operation :\r
+* Limitations :\r
+*******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "r_typedefs.h"\r
+#include "devdrv_common.h" /* Common Driver Header */\r
+#include "stb_init.h"\r
+#include "iodefine.h"\r
+\r
+/* Do not include the following pragmas when compiling with IAR. */\r
+#ifndef __ICCARM__\r
+ #pragma arm section code = "CODE_RESET"\r
+ #pragma arm section rodata = "CONST_RESET"\r
+ #pragma arm section rwdata = "DATA_RESET"\r
+ #pragma arm section zidata = "BSS_RESET"\r
+#endif\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* Function Name: StbInit\r
+* Description :\r
+* :\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void STB_Init(void)\r
+{\r
+ volatile uint8_t dummy_buf;\r
+\r
+ /* ---- The clock of all modules is permitted. ---- */\r
+ CPG.STBCR2.BYTE = 0x6Au; /* Port level is keep in standby mode, [1], [1], [0], */\r
+ /* [1], [0], [1], CoreSight */\r
+ dummy_buf = CPG.STBCR2.BYTE; /* (Dummy read) */\r
+ CPG.STBCR3.BYTE = 0x00u; /* IEBus, IrDA, LIN0, LIN1, MTU2, RSCAN2, [0], PWM */\r
+ dummy_buf = CPG.STBCR3.BYTE; /* (Dummy read) */\r
+ CPG.STBCR4.BYTE = 0x00u; /* SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 */\r
+ dummy_buf = CPG.STBCR4.BYTE; /* (Dummy read) */\r
+ CPG.STBCR5.BYTE = 0x00u; /* SCIM0, SCIM1, SDG0, SDG1, SDG2, SDG3, OSTM0, OSTM1 */\r
+ dummy_buf = CPG.STBCR5.BYTE; /* (Dummy read) */\r
+ CPG.STBCR6.BYTE = 0x00u; /* A/D, CEU, DISCOM0, DISCOM1, DRC0, DRC1, JCU, RTClock */\r
+ dummy_buf = CPG.STBCR6.BYTE; /* (Dummy read) */\r
+ CPG.STBCR7.BYTE = 0x24u; /* DVDEC0, DVDEC1, [1], ETHER, FLCTL, [1], USB0, USB1 */\r
+ dummy_buf = CPG.STBCR7.BYTE; /* (Dummy read) */\r
+ CPG.STBCR8.BYTE = 0x05u; /* IMR-LS20, IMR-LS21, IMR-LSD, MMCIF, MOST50, [1], SCUX, [1] */\r
+ dummy_buf = CPG.STBCR8.BYTE; /* (Dummy read) */\r
+ CPG.STBCR9.BYTE = 0x00u; /* I2C0, I2C1, I2C2, I2C3, SPIBSC0, SPIBSC1, VDC50, VDC51 */\r
+ dummy_buf = CPG.STBCR9.BYTE; /* (Dummy read) */\r
+ CPG.STBCR10.BYTE = 0x00u; /* RSPI0, RSPI1, RSPI2, RSPI3, RSPI4, CD-ROMDEC, RSPDIF, RGPVG */\r
+ dummy_buf = CPG.STBCR10.BYTE; /* (Dummy read) */\r
+ CPG.STBCR11.BYTE = 0xC0u; /* [1], [1], SSIF0, SSIF1, SSIF2, SSIF3, SSIF4, SSIF5 */\r
+ dummy_buf = CPG.STBCR11.BYTE; /* (Dummy read) */\r
+ CPG.STBCR12.BYTE = 0xF0u; /* [1], [1], [1], [1], SDHI00, SDHI01, SDHI10, SDHI11 */\r
+ dummy_buf = CPG.STBCR12.BYTE; /* (Dummy read) */\r
+}\r
+\r
+\r
+/* End of File */\r
+\r
--- /dev/null
+;/*******************************************************************************\r
+;* DISCLAIMER\r
+;* This software is supplied by Renesas Electronics Corporation and is only\r
+;* intended for use with Renesas products. No other uses are authorized. This\r
+;* software is owned by Renesas Electronics Corporation and is protected under\r
+;* all applicable laws, including copyright laws.\r
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+;* Renesas reserves the right, without notice, to make changes to this software\r
+;* and to discontinue the availability of this software. By using this software,\r
+;* you agree to the additional terms and conditions found by accessing the\r
+;* following link:\r
+;* http://www.renesas.com/disclaimer\r
+;*\r
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* File Name : ttb_init.s\r
+;* Version : 0.01\r
+;* Device(s) : Aragon\r
+;* Tool-Chain : DS-5 Ver 5.8\r
+;* ARM Complier \r
+;* : \r
+;* H/W Platform : Aragon CPU Board\r
+;* Description : Aragon Sample Program - TTB initialize\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* History : DD.MM.YYYY Version Description\r
+;* : 23.05.2012 0.01\r
+;*******************************************************************************/\r
+\r
+; ---- Parameter setting to level1 descriptor (bits 19:0) ----\r
+; setting for Strongly-ordered memory\r
+TTB_PARA_STRGLY EQU 2_00000000000000000000110111100010\r
+; setting for Outer and inner not cache normal memory\r
+TTB_PARA_NORMAL_NOT_CACHE EQU 2_00000000000000000001110111100010\r
+; setting for Outer and inner write back, write allocate normal memory (Cacheable)\r
+TTB_PARA_NORMAL_CACHE EQU 2_00000000000000000001110111101110\r
+; setting for Outer and inner write back, write allocate normal memory (Cacheable)\r
+;TTB_PARA_NORMAL_CACHE EQU 2_00000000000000000101110111100110\r
+\r
+; ---- Memory area size (MB) ----\r
+M_SIZE_NOR EQU 128 ; [Area00] CS0, CS1 area (for NOR flash)\r
+M_SIZE_SDRAM EQU 128 ; [Area01] CS2, CS3 area (for SDRAM)\r
+M_SIZE_CS45 EQU 128 ; [Area02] CS4, CS5 area\r
+M_SIZE_SPI EQU 128 ; [Area03] SPI, SP2 area (for Serial flash)\r
+M_SIZE_RAM EQU 10 ; [Area04] Internal RAM\r
+M_SIZE_IO_1 EQU 502 ; [Area05] I/O area 1\r
+M_SIZE_NOR_M EQU 128 ; [Area06] CS0, CS1 area (for NOR flash) (mirror)\r
+M_SIZE_SDRAM_M EQU 128 ; [Area07] CS2, CS3 area (for SDRAM) (mirror)\r
+M_SIZE_CS45_M EQU 128 ; [Area08] CS4, CS5 area (mirror)\r
+M_SIZE_SPI_M EQU 128 ; [Area09] SPI, SP2 area (for Serial flash) (mirror)\r
+M_SIZE_RAM_M EQU 10 ; [Area10] Internal RAM (mirror)\r
+M_SIZE_IO_2 EQU 2550 ; [Area11] I/O area 2\r
+\r
+;==================================================================\r
+; This code provides basic global enable for Cortex-A9 cache.\r
+; It also enables branch prediction\r
+; This code must be run from a privileged mode\r
+;==================================================================\r
+ AREA INIT_TTB, CODE, READONLY\r
+\r
+ IMPORT ||Image$$TTB$$ZI$$Base|| ;;; From scatter file\r
+ \r
+ EXPORT init_TTB\r
+\r
+init_TTB FUNCTION\r
+\r
+;===================================================================\r
+; Cortex-A9 MMU Configuration\r
+; Set translation table base\r
+;===================================================================\r
+ ;;; Cortex-A9 supports two translation tables\r
+ ;;; Configure translation table base (TTB) control register cp15,c2\r
+ ;;; to a value of all zeros, indicates we are using TTB register 0.\r
+ MOV r0,#0x0\r
+ MCR p15, 0, r0, c2, c0, 2 ;;; TTBCR\r
+\r
+ ;;; write the address of our page table base to TTB register 0\r
+ LDR r0,=||Image$$TTB$$ZI$$Base||\r
+ MOV r1, #0x08 ;;; RGN=b01 (outer cacheable write-back cached, write allocate)\r
+ ;;; S=0 (translation table walk to non-shared memory)\r
+ ORR r1,r1,#0x40 ;;; IRGN=b01 (inner cacheability for the translation table walk is Write-back Write-allocate)\r
+ ORR r0,r0,r1\r
+ MCR p15, 0, r0, c2, c0, 0 ;;; TTBR0\r
+\r
+;===================================================================\r
+; PAGE TABLE generation \r
+; Generate the page tables\r
+; Build a flat translation table for the whole address space.\r
+; ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx\r
+; 31 20 19 18 17 16 15 14 12 11 10 9 8 5 4 3 2 1 0\r
+; |section base address| 0 0 |nG| S |AP2| TEX | AP | P | Domain | XN | C B | 1 0|\r
+;\r
+; Bits[31:20] - Top 12 bits of VA is pointer into table\r
+; nG[17]=0 - Non global, enables matching against ASID in the TLB when set.\r
+; S[16]=0 - Indicates normal memory is shared when set.\r
+; AP2[15]=0 \r
+; AP[11:10]=11 - Configure for full read/write access in all modes\r
+; TEX[14:12]=000\r
+; CB[3:2]= 00 - Set attributes to Strongly-ordered memory.\r
+; (except for the descriptor where code segment is based, see below)\r
+; IMPP[9]=0 - Ignored\r
+; Domain[5:8]=1111 - Set all pages to use domain 15\r
+; XN[4]=0 - Execute never disabled\r
+; Bits[1:0]=10 - Indicate entry is a 1MB section\r
+;===================================================================\r
+ LDR r0,=||Image$$TTB$$ZI$$Base||\r
+ LDR r1,=0xFFF\r
+ LDR r2,=11\r
+ LDR r3,=0\r
+ LDR r4,=0\r
+ LDR r5,=0\r
+\r
+ ;;; r0 contains the address of the translation table base\r
+ ;;; r1 is loop counter\r
+ ;;; r2 is target area counter (Initialize value = Last area No.)\r
+ ;;; r3 is loop counter by area\r
+\r
+ ;;; use loop counter to create 4096 individual table entries.\r
+ ;;; this writes from address 'Image$$TTB$$ZI$$Base' + \r
+ ;;; offset 0x3FFC down to offset 0x0 in word steps (4 bytes)\r
+\r
+set_mem_accsess\r
+ CMP r2, #11\r
+ BEQ setting_area11\r
+ CMP r2, #10\r
+ BEQ setting_area10\r
+ CMP r2, #9\r
+ BEQ setting_area9\r
+ CMP r2, #8\r
+ BEQ setting_area8\r
+ CMP r2, #7\r
+ BEQ setting_area7\r
+ CMP r2, #6\r
+ BEQ setting_area6\r
+ CMP r2, #5\r
+ BEQ setting_area5\r
+ CMP r2, #4\r
+ BEQ setting_area4\r
+ CMP r2, #3\r
+ BEQ setting_area3\r
+ CMP r2, #2\r
+ BEQ setting_area2\r
+ CMP r2, #1\r
+ BEQ setting_area1\r
+ CMP r2, #0\r
+ BEQ setting_area0\r
+setting_area11 ;;; [area11] I/O area 2\r
+ LDR r3, =M_SIZE_IO_2\r
+ LDR r4, =TTB_PARA_STRGLY ;;; Strongly-ordered\r
+ BAL init_counter\r
+setting_area10 ;;; [area10] Internal RAM (mirror)\r
+ LDR r3, =M_SIZE_RAM_M\r
+ LDR r4, =TTB_PARA_NORMAL_NOT_CACHE ;;; Normal (not cache)\r
+ BAL init_counter\r
+setting_area9 ;;; [area09] SPI, SP2 area (for Serial flash) (mirror)\r
+ LDR r3, =M_SIZE_SPI_M\r
+ LDR r4, =TTB_PARA_NORMAL_NOT_CACHE ;;; Normal (not cache)\r
+ BAL init_counter\r
+setting_area8 ;;; [area08] CS4, CS5 area (mirror)\r
+ LDR r3, =M_SIZE_CS45_M\r
+ LDR r4, =TTB_PARA_STRGLY ;;; Strongly-ordered\r
+ BAL init_counter \r
+setting_area7 ;;; [area07] CS2, CS3 area (for SDRAM) (mirror)\r
+ LDR r3, =M_SIZE_SDRAM_M\r
+ LDR r4, =TTB_PARA_NORMAL_NOT_CACHE ;;; Normal (not cache)\r
+ BAL init_counter\r
+setting_area6 ;;; [area06] CS0, CS1 area (for NOR flash) (mirror)\r
+ LDR r3, =M_SIZE_NOR_M\r
+ LDR r4, =TTB_PARA_NORMAL_NOT_CACHE ;;; Normal (not cache)\r
+ BAL init_counter\r
+setting_area5 ;;; [area05] I/O area 1\r
+ LDR r3, =M_SIZE_IO_1\r
+ LDR r4, =TTB_PARA_STRGLY ;;; Strongly-ordered\r
+ BAL init_counter\r
+setting_area4 ;;; [area04] Internal RAM\r
+ LDR r3, =M_SIZE_RAM\r
+ LDR r4, =TTB_PARA_NORMAL_CACHE ;;; Normal (Cacheable)\r
+ BAL init_counter\r
+setting_area3 ;;; [area03] SPI, SP2 area (for Serial flash)\r
+ LDR r3, =M_SIZE_SPI\r
+ LDR r4, =TTB_PARA_NORMAL_CACHE ;;; Normal (Cacheable)\r
+ BAL init_counter\r
+setting_area2 ;;; [area02] CS4, CS5 area\r
+ LDR r3, =M_SIZE_CS45\r
+ LDR r4, =TTB_PARA_STRGLY ;;; Strongly-ordered\r
+ BAL init_counter\r
+setting_area1 ;;; [area01] CS2, CS3 area (for SDRAM)\r
+ LDR r3, =M_SIZE_SDRAM\r
+ LDR r4, =TTB_PARA_NORMAL_CACHE ;;; Normal (Cacheable)\r
+ BAL init_counter \r
+setting_area0 ;;; [area00] CS0, CS1 area (for NOR flash)\r
+ LDR r3, =M_SIZE_NOR\r
+ LDR r4, =TTB_PARA_NORMAL_CACHE ;;; Normal (Cacheable)\r
+ BAL init_counter\r
+init_counter\r
+ SUBS r3, r3, #1 ;;; memory size -> loop counter value\r
+write_ttb\r
+ ORR r5, r4, r1, LSL#20 ;;; R5 now contains full level1 descriptor to write\r
+ STR r5, [r0, r1, LSL#2] ;;; Str table entry at TTB base + loopcount*4\r
+ SUB r1, r1, #1 ;;; Decrement loop counter\r
+ SUBS r3, r3, #1 ;;; Decrement loop counter by area\r
+ BPL write_ttb\r
+ SUBS r2, r2, #1 ;;; target area counter\r
+ BPL set_mem_accsess ;;; To the next area\r
+\r
+ BX lr\r
+\r
+ ENDFUNC\r
+\r
+\r
+ END\r
--- /dev/null
+;/*******************************************************************************\r
+;* DISCLAIMER\r
+;* This software is supplied by Renesas Electronics Corporation and is only\r
+;* intended for use with Renesas products. No other uses are authorized. This\r
+;* software is owned by Renesas Electronics Corporation and is protected under\r
+;* all applicable laws, including copyright laws.\r
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+;* Renesas reserves the right, without notice, to make changes to this software\r
+;* and to discontinue the availability of this software. By using this software,\r
+;* you agree to the additional terms and conditions found by accessing the\r
+;* following link:\r
+;* http://www.renesas.com/disclaimer\r
+;*\r
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* File Name : l1_cache_init.s\r
+;* Version : 0.01\r
+;* Device(s) : Aragon\r
+;* Tool-Chain : DS-5 Ver 5.8\r
+;* ARM Complier \r
+;* : \r
+;* H/W Platform : Aragon CPU Board\r
+;* Description : Aragon Sample Program vecotr.s\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* History : DD.MM.YYYY Version Description\r
+;* : 23.05.2012 0.01\r
+;*******************************************************************************/\r
+\r
+;==================================================================\r
+; This code provides basic global enable for Cortex-A9 cache.\r
+; It also enables branch prediction\r
+; This code must be run from a privileged mode\r
+;==================================================================\r
+ AREA INITCA9CACHE, CODE, READONLY\r
+ EXPORT L1CacheInit\r
+\r
+L1CacheInit FUNCTION\r
+\r
+;==================================================================\r
+; Enable caches\r
+; Caches are controlled by the System Control Register:\r
+;==================================================================\r
+ ;;; I-cache is controlled by bit 12\r
+ ;;; D-cache is controlled by bit 2\r
+\r
+ MRC p15, 0, r0, c1, c0, 0 ;;; Read CP15 register 1\r
+ ORR r0, r0, #(0x1 << 12) ;;; Enable I Cache\r
+ ORR r0, r0, #(0x1 << 2) ;;; Enable D Cache\r
+ MCR p15, 0, r0, c1, c0, 0 ;;; Write CP15 register 1\r
+\r
+;==================================================================\r
+; Enable Program Flow Prediction\r
+;\r
+; Branch prediction is controlled by the System Control Register:\r
+; Set Bit 11 to enable branch prediction and return \r
+;==================================================================\r
+ ;;; Turning on branch prediction requires a general enable\r
+ ;;; CP15, c1. Control Register\r
+\r
+ ;;; Bit 11 [Z] bit Program flow prediction:\r
+ ;;; 0 = Program flow prediction disabled\r
+ ;;; 1 = Program flow prediction enabled.\r
+\r
+ MRC p15, 0, r0, c1, c0, 0 ;;; Read System Control Register\r
+ ORR r0, r0, #(0x1 << 11)\r
+ MCR p15, 0, r0, c1, c0, 0 ;;; Write System Control Register\r
+\r
+;==================================================================\r
+; Enable D-side prefetch\r
+;==================================================================\r
+ ;;; Bit 2 [DP] Dside prefetch:\r
+ ;;; 0 = Dside prefetch disabled\r
+ ;;; 1 = Dside prefetch enabled.\r
+\r
+ MRC p15, 0, r0, c1, c0, 1 ;;; Read Auxiliary Control Register\r
+ ORR r0, r0, #(0x1 << 2) ;;; Enable Dside prefetch\r
+ MCR p15, 0, r0, c1, c0, 1 ;;; Write Auxiliary Control Register\r
+\r
+ BX lr\r
+\r
+ ENDFUNC\r
+\r
+\r
+\r
+\r
+ END\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : resetprg.c\r
+* $Rev: 17531 $\r
+* $Date:: 2013-04-10 12:58:44 +0100#$\r
+* Device(s) : Aragon\r
+* Tool-Chain : DS-5 Ver 5.8\r
+* : ARM Complier\r
+* OS : \r
+* H/W Platform : Aragon CPU Board\r
+* Description : Aragon Sample Program - Sub Main\r
+* Operation : \r
+* Limitations : \r
+*******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "r_typedefs.h"\r
+#include "devdrv_common.h" /* Common Driver Header */\r
+#include "devdrv_intc.h" /* INTC Driver Header */\r
+#include "resetprg.h"\r
+#include "sio_char.h"\r
+#include "stb_init.h"\r
+#include "port_init.h"\r
+\r
+#pragma arm section code = "CODE_RESET"\r
+#pragma arm section rodata = "CONST_RESET"\r
+#pragma arm section rwdata = "DATA_RESET"\r
+#pragma arm section zidata = "BSS_RESET"\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+extern void VbarInit(void);\r
+extern void L1CacheInit(void);\r
+extern int32_t $Super$$main(void);\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: $Sub$$main\r
+* Description : \r
+* Arguments : none\r
+* Return Value : none\r
+*******************************************************************************/\r
+void $Sub$$main(void)\r
+{\r
+ STB_Init();\r
+\r
+ /* ==== PORT setting ==== */\r
+ PORT_Init();\r
+\r
+ /* ==== BSC setting ==== */\r
+ R_BSC_Init((uint8_t)(BSC_AREA_CS2 | BSC_AREA_CS3));\r
+\r
+ /* ==== INTC setting ==== */\r
+ R_INTC_Init();\r
+\r
+ /* ==== Cache setting ==== */\r
+// io_init_cache();\r
+\r
+ /* ==== Writeback Cache ==== */\r
+// io_cache_writeback();\r
+\r
+ L1CacheInit();\r
+\r
+ /* ==== Vector base address setting ==== */\r
+ VbarInit();\r
+\r
+ __enable_irq();\r
+ __enable_fiq();\r
+\r
+ /* ==== Function call of main function ==== */\r
+ $Super$$main();\r
+}\r
+\r
+\r
+/* END of File */\r
+\r
--- /dev/null
+;/*******************************************************************************\r
+;* DISCLAIMER\r
+;* This software is supplied by Renesas Electronics Corporation and is only\r
+;* intended for use with Renesas products. No other uses are authorized. This\r
+;* software is owned by Renesas Electronics Corporation and is protected under\r
+;* all applicable laws, including copyright laws.\r
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+;* Renesas reserves the right, without notice, to make changes to this software\r
+;* and to discontinue the availability of this software. By using this software,\r
+;* you agree to the additional terms and conditions found by accessing the\r
+;* following link:\r
+;* http://www.renesas.com/disclaimer\r
+;*\r
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* File Name : vbar_init.s\r
+;* Version : 0.01\r
+;* Device(s) : Aragon\r
+;* Tool-Chain : DS-5 Ver 5.8\r
+;* ARM Complier \r
+;* : \r
+;* H/W Platform : Aragon CPU Board\r
+;* Description : Aragon Sample Program\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* History : DD.MM.YYYY Version Description\r
+;* : 23.05.2012 0.01\r
+;*******************************************************************************/\r
+\r
+;==================================================================\r
+; This code provides basic global enable for Cortex-A9 cache.\r
+; It also enables branch prediction\r
+; This code must be run from a privileged mode\r
+;==================================================================\r
+ AREA INIT_VBAR, CODE, READONLY\r
+ \r
+ IMPORT ||Image$$VECTOR_MIRROR_TABLE$$Base||\r
+; IMPORT ||Image$$VECTOR_TABLE$$Base||\r
+ \r
+ EXPORT VbarInit\r
+\r
+VbarInit FUNCTION\r
+\r
+;===================================================================\r
+; Set Vector Base Address Register (VBAR) to point to this application's vector table\r
+;===================================================================\r
+ LDR r0, =||Image$$VECTOR_MIRROR_TABLE$$Base||\r
+; LDR r0, =||Image$$VECTOR_TABLE$$Base||\r
+ MCR p15, 0, r0, c12, c0, 0\r
+\r
+ BX lr\r
+\r
+ ENDFUNC\r
+\r
+\r
+\r
+\r
+ END\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : bsc.c\r
+* $Rev: $\r
+* $Date:: $\r
+* Description : Aragon Sample Program - BSC initialize\r
+*******************************************************************************/\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "r_typedefs.h"\r
+#include "dev_drv.h" /* Device Driver common header */\r
+#include "devdrv_common.h" /* Common Driver Header */\r
+\r
+/* Do not include the following pragmas when compiling with IAR. */\r
+#ifndef __ICCARM__\r
+ #pragma arm section code = "CODE_RESET"\r
+ #pragma arm section rodata = "CONST_RESET"\r
+ #pragma arm section rwdata = "DATA_RESET"\r
+ #pragma arm section zidata = "BSS_RESET"\r
+#endif\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+* Function Name: R_BSC_Init\r
+* Description :\r
+* Arguments : uint8 area\r
+* : B'xxxxxxxx\r
+* : |||||||+--- [0] CS0\r
+* : ||||||+---- [1] CS1\r
+* : |||||+----- [2] CS2\r
+* : ||||+------ [3] CS3\r
+* : |||+------- [4] CS4\r
+* : ||+-------- [5] CS5\r
+* : ++--------- [6-7] n/a\r
+* Return Value : none\r
+******************************************************************************/\r
+void R_BSC_Init(uint8_t area)\r
+{\r
+ /* ==== BSC initialize ==== */\r
+ if ((area & BSC_AREA_CS0) != 0) /* CS0 */\r
+ {\r
+ Userdef_BSC_CS0Init();\r
+ }\r
+ if ((area & BSC_AREA_CS1) != 0) /* CS1 */\r
+ {\r
+ Userdef_BSC_CS1Init();\r
+ }\r
+ if ((area & BSC_AREA_CS2) != 0) /* CS2 */\r
+ {\r
+ Userdef_BSC_CS2Init();\r
+ }\r
+ if ((area & BSC_AREA_CS3) != 0) /* CS3 */\r
+ {\r
+ Userdef_BSC_CS3Init();\r
+ }\r
+ if ((area & BSC_AREA_CS4) != 0) /* CS4 */\r
+ {\r
+ Userdef_BSC_CS4Init();\r
+ }\r
+ if ((area & BSC_AREA_CS5) != 0) /* CS5 */\r
+ {\r
+ Userdef_BSC_CS5Init();\r
+ }\r
+}\r
+\r
+/* End of File */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : bsc_userdef.c\r
+* $Rev: 17531 $\r
+* $Date:: 2013-04-10 12:58:44 +0100#$\r
+* Device(s) : Aragon\r
+* Tool-Chain : DS-5 Ver 5.8\r
+* : ARM Complier\r
+* OS :\r
+* H/W Platform : Aragon CPU Board\r
+* Description : Aragon Sample Program - Common driver (User define function)\r
+* Operation :\r
+* Limitations :\r
+*******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "r_typedefs.h"\r
+#include "dev_drv.h" /* Device Driver common header */\r
+#include "devdrv_common.h" /* Common Driver Header */\r
+#include "iodefine.h"\r
+\r
+/* Do not include the following pragmas when compiling with IAR. */\r
+#ifndef __ICCARM__\r
+ #pragma arm section code = "CODE_RESET"\r
+ #pragma arm section rodata = "CONST_RESET"\r
+ #pragma arm section rwdata = "DATA_RESET"\r
+ #pragma arm section zidata = "BSS_RESET"\r
+#endif\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+/* The address when writing in a SDRAM mode register */\r
+#define SDRAM_MODE_CS2 (*(volatile uint16_t *)(0x3FFFD040))\r
+#define SDRAM_MODE_CS3 (*(volatile uint16_t *)(0x3FFFE040))\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_BSC_CS0Init\r
+* Description :\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void Userdef_BSC_CS0Init(void)\r
+{\r
+ /* ---- CS0BCR settings ---- */\r
+ BSC.CS0BCR.LONG = 0x10000C00ul;\r
+ /* Idle Cycles between Write-read Cycles */\r
+ /* and Write-write Cycles : 1 idle cycle */\r
+ /* Data Bus Size: 16-bit */\r
+\r
+ /* ---- CS0WCR settings ---- */\r
+ BSC.CS0WCR.NORMAL.LONG = 0x00000B40ul;\r
+ /* Number of Delay Cycles from Address, */\r
+ /* CS0# Assertion to RD#,WEn Assertion */\r
+ /* : 1.5 cycles */\r
+ /* Number of Access Wait Cycles: 6 cycles */\r
+ /* Delay Cycles from RD,WEn# negation to */\r
+ /* Address,CSn# negation: 0.5 cycles */\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_BSC_CS1Init\r
+* Description :\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void Userdef_BSC_CS1Init(void)\r
+{\r
+ /* ---- CS1BCR settings ---- */\r
+ BSC.CS1BCR.LONG = 0x10000C00ul;\r
+ /* Idle Cycles between Write-read Cycles */\r
+ /* and Write-write Cycles : 1 idle cycle */\r
+ /* Data Bus Size: 16-bit */\r
+\r
+ /* ---- CS1WCR settings ---- */\r
+ BSC.CS1WCR.LONG = 0x00000B40ul;\r
+ /* Number of Delay Cycles from Address, */\r
+ /* CS0# Assertion to RD#,WEn Assertion */\r
+ /* : 1.5 cycles */\r
+ /* Number of Access Wait Cycles: 6 cycles */\r
+ /* Delay Cycles from RD,WEn# negation to */\r
+ /* Address,CSn# negation: 0.5 cycles */\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_BSC_CS2Init\r
+* Description :\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void Userdef_BSC_CS2Init(void)\r
+{\r
+ /* ==== CS2BCR settings ==== */\r
+ BSC.CS2BCR.LONG = 0x00004C00ul;\r
+ /* Idle Cycles between Write-read Cycles */\r
+ /* and Write-write Cycles : 0 idle cycles */\r
+ /* Memory type :SDRAM */\r
+ /* Data Bus Size : 16-bit */\r
+\r
+ /* ==== CS2WCR settings ==== */\r
+ BSC.CS2WCR.SDRAM.LONG = 0x00000480ul;\r
+ /* CAS latency for Area 2 : 2 cycles */\r
+\r
+\r
+ /* ==== Written in SDRAM Mode Register ==== */\r
+ SDRAM_MODE_CS2 = 0;\r
+ /* The writing data is arbitrary */\r
+ /* SDRAM mode register setting CS2 space */\r
+ /* Burst read (burst length 1)./Burst write */\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_BSC_CS3Init\r
+* Description :\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void Userdef_BSC_CS3Init(void)\r
+{\r
+ volatile int32_t cnt;\r
+\r
+ cnt = 150;\r
+ while (cnt-- > 0)\r
+ {\r
+ /* wait */\r
+ }\r
+\r
+ /* ==== CS3BCR settings ==== */\r
+ BSC.CS3BCR.LONG = 0x00004C00ul;\r
+ /* Idle Cycles between Write-read Cycles */\r
+ /* and Write-write Cycles : 0 idle cycles */\r
+ /* Memory type :SDRAM */\r
+ /* Data Bus Size : 16-bit */\r
+\r
+ /* ==== CS3WCR settings ==== */\r
+ BSC.CS3WCR.SDRAM.LONG = 0x00002492ul;\r
+ /* Precharge completion wait cycles: 1 cycle */\r
+ /* Wait cycles between ACTV command */\r
+ /* and READ(A)/WRITE(A) command : 1 cycles */\r
+ /* CAS latency for Area 3 : 2 cycles */\r
+ /* Auto-precharge startup wait cycles : 2 cycles */\r
+ /* Idle cycles from REF command/self-refresh */\r
+ /* Release to ACTV/REF/MRS command : 5 cycles */\r
+\r
+ /* ==== SDCR settings ==== */\r
+ BSC.SDCR.LONG = 0x00120812ul;\r
+ /* Row address for Area 2 : 13-bit */\r
+ /* Column Address for Area 2 : 10-bit */\r
+ /* Refresh Control :Refresh */\r
+ /* RMODE :Auto-refresh is performed */\r
+ /* BACTV :Auto-precharge mode */\r
+ /* Row address for Area 3 : 13-bit */\r
+ /* Column Address for Area 3 : 10-bit */\r
+\r
+ /* ==== RTCOR settings ==== */\r
+ BSC.RTCOR.LONG = 0xA55A0020ul;\r
+ /* 7.813usec /240nsec */\r
+ /* = 32(0x20)cycles per refresh */\r
+\r
+ /* ==== RTCSR settings ==== */\r
+ BSC.RTCSR.LONG = 0xA55A0010ul;\r
+ /* Initialization sequence start */\r
+ /* Clock select B-phy/16 */\r
+ /* Refresh count :Once */\r
+\r
+ /* ==== Written in SDRAM Mode Register ==== */\r
+ SDRAM_MODE_CS3 = 0;\r
+ /* The writing data is arbitrary */\r
+ /* SDRAM mode register setting CS3 space */\r
+ /* Burst read (burst length 1)./Burst write */\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_BSC_CS4Init\r
+* Description :\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void Userdef_BSC_CS4Init(void)\r
+{\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_BSC_CS5Init\r
+* Description :\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void Userdef_BSC_CS5Init(void)\r
+{\r
+}\r
+\r
+\r
+/* End of File */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : intc.c\r
+* $Rev: 17531 $\r
+* $Date:: 2013-04-10 12:58:44 +0100#$\r
+* Description : Aragon Sample Program - Interrupt process\r
+*******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "r_typedefs.h"\r
+#include "dev_drv.h" /* Device Driver common header */\r
+#include "devdrv_intc.h" /* INTC Driver Header */\r
+#include "iodefine.h"\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+#define INTC_ICDISR_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 32) + 1) /* ICDISR */\r
+#define INTC_ICDICFR_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 16) + 1) /* ICDICFR */\r
+#define INTC_ICDIPR_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 4) + 1) /* ICDIPR */\r
+#define INTC_ICDIPTR_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 4) + 1) /* ICDIPTR */\r
+#define INTC_ICDISER_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 32) + 1) /* ICDISER */\r
+#define INTC_ICDICER_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 32) + 1) /* ICDICER */\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+/* ==== Global variable ==== */\r
+static uint32_t intc_icdicfrn_table[] =\r
+{\r
+ 0xAAAAAAAA, /* ICDICFR0 : 15 - 0 */\r
+ 0x00000055, /* ICDICFR1 : 19 - 16 */\r
+ 0xFFFD5555, /* ICDICFR2 : 47 - 32 */\r
+ 0x555FFFFF, /* ICDICFR3 : 63 - 48 */\r
+ 0x55555555, /* ICDICFR4 : 79 - 64 */\r
+ 0x55555555, /* ICDICFR5 : 95 - 80 */\r
+ 0x55555555, /* ICDICFR6 : 111 - 96 */\r
+ 0x55555555, /* ICDICFR7 : 127 - 112 */\r
+ 0x5555F555, /* ICDICFR8 : 143 - 128 */\r
+ 0x55555555, /* ICDICFR9 : 159 - 144 */\r
+ 0x55555555, /* ICDICFR10 : 175 - 160 */\r
+ 0xF5555555, /* ICDICFR11 : 191 - 176 */\r
+ 0xF555F555, /* ICDICFR12 : 207 - 192 */\r
+ 0x5555F555, /* ICDICFR13 : 223 - 208 */\r
+ 0x55555555, /* ICDICFR14 : 239 - 224 */\r
+ 0x55555555, /* ICDICFR15 : 255 - 240 */\r
+ 0x55555555, /* ICDICFR16 : 271 - 256 */\r
+ 0xFD555555, /* ICDICFR17 : 287 - 272 */\r
+ 0x55555557, /* ICDICFR18 : 303 - 288 */\r
+ 0x55555555, /* ICDICFR19 : 319 - 304 */\r
+ 0x55555555, /* ICDICFR20 : 335 - 320 */\r
+ 0x5F555555, /* ICDICFR21 : 351 - 336 */\r
+ 0xFD55555F, /* ICDICFR22 : 367 - 352 */\r
+ 0x55555557, /* ICDICFR23 : 383 - 368 */\r
+ 0x55555555, /* ICDICFR24 : 399 - 384 */\r
+ 0x55555555, /* ICDICFR25 : 415 - 400 */\r
+ 0x55555555, /* ICDICFR26 : 431 - 416 */\r
+ 0x55555555, /* ICDICFR27 : 447 - 432 */\r
+ 0x55555555, /* ICDICFR28 : 463 - 448 */\r
+ 0x55555555, /* ICDICFR29 : 479 - 464 */\r
+ 0x55555555, /* ICDICFR30 : 495 - 480 */\r
+ 0x55555555, /* ICDICFR31 : 511 - 496 */\r
+ 0x55555555, /* ICDICFR32 : 527 - 512 */\r
+ 0x55555555, /* ICDICFR33 : 543 - 528 */\r
+ 0x55555555, /* ICDICFR34 : 559 - 544 */\r
+ 0x55555555, /* ICDICFR35 : 575 - 560 */\r
+ 0x00155555 /* ICDICFR36 : 586 - 576 */\r
+};\r
+\r
+\r
+/******************************************************************************\r
+* Function Name: R_INTC_RegistIntFunc\r
+* Description :\r
+* Arguments : uint16_t int_id\r
+* : void (* func)(uint32_t)\r
+* Return Value : DEVDRV_SUCCESS\r
+* : DEVDRV_ERROR\r
+******************************************************************************/\r
+int32_t R_INTC_RegistIntFunc(uint16_t int_id, void (* func)(uint32_t int_sense))\r
+{\r
+ if (int_id >= INTC_ID_TOTAL)\r
+ {\r
+ return DEVDRV_ERROR;\r
+ }\r
+\r
+ Userdef_INTC_RegistIntFunc(int_id, func);\r
+\r
+ return DEVDRV_SUCCESS;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: R_INTC_Init\r
+* Description :\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void R_INTC_Init(void)\r
+{\r
+ uint16_t offset;\r
+ volatile uint32_t * addr;\r
+\r
+ for (offset = 0; offset < INTC_ICDICFR_REG_TOTAL; offset++)\r
+ {\r
+ INTC.ICDICFR.LONG[offset] = intc_icdicfrn_table[offset];\r
+ }\r
+\r
+ addr = (volatile uint32_t *)&INTC.ICDIPR0.LONG;\r
+ for (offset = 0; offset < INTC_ICDIPR_REG_TOTAL; offset++)\r
+ {\r
+ *(addr + offset) = 0xF8F8F8F8;\r
+ }\r
+\r
+ addr = (volatile uint32_t *)&INTC.ICDIPTR0.LONG;\r
+ for (offset = 8; offset < INTC_ICDIPTR_REG_TOTAL; offset++)\r
+ {\r
+ *(addr + offset) = 0x01010101;\r
+ }\r
+\r
+ for (offset = 0; offset < INTC_ICDICER_REG_TOTAL; offset++)\r
+ {\r
+ INTC.ICDICER.LONG[offset] = 0xFFFFFFFF;\r
+ }\r
+\r
+ R_INTC_SetMaskLevel(31);\r
+\r
+ INTC.ICCBPR.BIT.Binarypoint = 0;\r
+\r
+ INTC.ICCICR.LONG = 3;\r
+\r
+ /* Distributor Control Register */\r
+ INTC.ICDDCR.BIT.Enable = 1;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: R_INTC_Enable\r
+* Description :\r
+* Arguments : uint16_t int_id\r
+* Return Value : DEVDRV_SUCCESS\r
+* : DEVDRV_ERROR\r
+******************************************************************************/\r
+int32_t R_INTC_Enable(uint16_t int_id)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t mask;\r
+\r
+ if (int_id >= INTC_ID_TOTAL)\r
+ {\r
+ return DEVDRV_ERROR;\r
+ }\r
+\r
+ mask = 1;\r
+ mask = mask << (int_id % 32);\r
+\r
+ reg_value = INTC.ICDISER.LONG[int_id / 32];\r
+ reg_value |= mask;\r
+ INTC.ICDISER.LONG[int_id / 32] = reg_value;\r
+\r
+ return DEVDRV_SUCCESS;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: R_INTC_Disable\r
+* Description :\r
+* Arguments : uint16_t int_id\r
+* Return Value : DEVDRV_SUCCESS\r
+* : DEVDRV_ERROR\r
+******************************************************************************/\r
+int32_t R_INTC_Disable(uint16_t int_id)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t mask;\r
+\r
+ if (int_id >= INTC_ID_TOTAL)\r
+ {\r
+ return DEVDRV_ERROR;\r
+ }\r
+\r
+ mask = 1;\r
+ mask = mask << (int_id % 32);\r
+\r
+ reg_value = INTC.ICDICER.LONG[int_id / 32];\r
+ reg_value |= mask;\r
+ INTC.ICDICER.LONG[int_id / 32] = reg_value;\r
+\r
+ return DEVDRV_SUCCESS;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: R_INTC_SetPriority\r
+* Description :\r
+* Arguments : uint16_t int_id\r
+* : uint8_t priority\r
+* Return Value : DEVDRV_SUCCESS\r
+* : DEVDRV_ERROR\r
+******************************************************************************/\r
+int32_t R_INTC_SetPriority(uint16_t int_id, uint8_t priority)\r
+{\r
+ uint32_t icdipr;\r
+ uint32_t mask;\r
+ volatile uint32_t * addr;\r
+\r
+ if ((int_id >= INTC_ID_TOTAL) || priority >= 32)\r
+ {\r
+ return DEVDRV_ERROR;\r
+ }\r
+\r
+ priority = priority << 3;\r
+\r
+ addr = (volatile uint32_t *)&INTC.ICDIPR0.LONG;\r
+\r
+ icdipr = *(addr + (int_id / 4));\r
+\r
+ mask = (uint32_t)0x000000FF;\r
+ mask = mask << ((int_id % 4) * 8);\r
+ icdipr &= ~mask;\r
+ mask = (uint32_t)priority;\r
+ mask = mask << ((int_id % 4) * 8);\r
+ icdipr |= mask;\r
+\r
+ *(addr + (int_id / 4)) = icdipr;\r
+\r
+ return DEVDRV_SUCCESS;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: R_INTC_SetMaskLevel\r
+* Description :\r
+* Arguments : uint8_t mask_level\r
+* Return Value : DEVDRV_SUCCESS\r
+* : DEVDRV_ERROR\r
+******************************************************************************/\r
+int32_t R_INTC_SetMaskLevel(uint8_t mask_level)\r
+{\r
+ if (mask_level >= 32)\r
+ {\r
+ return DEVDRV_ERROR;\r
+ }\r
+\r
+ mask_level = mask_level << 3;\r
+ INTC.ICCPMR.BIT.Priority = mask_level;\r
+\r
+ return DEVDRV_SUCCESS;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: R_INTC_GetMaskLevel\r
+* Description :\r
+* Arguments : uint8_t * mask_level\r
+* Return Value : none\r
+******************************************************************************/\r
+void R_INTC_GetMaskLevel(uint8_t * mask_level)\r
+{\r
+ *mask_level = INTC.ICCPMR.BIT.Priority;\r
+ *mask_level = *mask_level >> 3;\r
+}\r
+\r
+/* END of File */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : intc_handler.c\r
+* $Rev: 17531 $\r
+* $Date:: 2013-04-10 12:58:44 +0100#$\r
+* Description : Aragon Sample Program - Handler process\r
+*******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "FreeRTOS.h"\r
+#include <stdio.h>\r
+#include "r_typedefs.h"\r
+#include "devdrv_intc.h" /* INTC Driver Header */\r
+#include "iodefine.h"\r
+\r
+/* Do not include the following pragmas when compiling with IAR. */\r
+#ifndef __ICCARM__\r
+ #pragma arm section code = "CODE_HANDLER"\r
+ #pragma arm section rodata = "CONST_HANDLER"\r
+ #pragma arm section rwdata = "DATA_HANDLER"\r
+ #pragma arm section zidata = "BSS_HANDLER"\r
+#endif\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+/* ==== Prototype declaration ==== */\r
+__irq void FiqHandler_Interrupt(void);\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: FiqHandler_Interrupt\r
+* Description :\r
+* Arguments : none\r
+* Return Value : none\r
+*******************************************************************************/\r
+__irq void FiqHandler_Interrupt(void)\r
+{\r
+ Userdef_FIQ_HandlerExe();\r
+}\r
+\r
+\r
+/* END of File */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : intc_userdef.c\r
+* $Rev: 17531 $\r
+* $Date:: 2013-04-10 12:58:44 +0100#$\r
+* Device(s) : Aragon\r
+* Tool-Chain : DS-5 Ver 5.8\r
+* : ARM Complier\r
+* OS :\r
+* H/W Platform : Aragon CPU Board\r
+* Description : Aragon Sample Program - Interrupt func table\r
+* Operation :\r
+* Limitations :\r
+*******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "r_typedefs.h"\r
+#include "devdrv_intc.h" /* INTC Driver Header */\r
+#include "iodefine.h"\r
+\r
+/* Do not include the following pragmas when compiling with IAR. */\r
+#ifndef __ICCARM__\r
+ #pragma arm section code = "CODE_HANDLER_JMPTBL"\r
+ #pragma arm section rodata = "CONST_HANDLER_JMPTBL"\r
+ #pragma arm section rwdata = "DATA_HANDLER_JMPTBL"\r
+ #pragma arm section zidata = "BSS_HANDLER_JMPTBL"\r
+#else\r
+ /* IAR requires intrinsics.h for the __enable_irq() function. */\r
+ #include <intrinsics.h>\r
+#endif\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+/* ==== Prototype function ==== */\r
+static void Userdef_INTC_Dummy_Interrupt(uint32_t int_sense);\r
+\r
+/* ==== Global variable ==== */\r
+static void (* intc_func_table[INTC_ID_TOTAL])(uint32_t int_sense) =\r
+{\r
+ Userdef_INTC_Dummy_Interrupt, /* 0 : SW0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 1 : SW1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 2 : SW2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 3 : SW3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 4 : SW4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 5 : SW5 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 6 : SW6 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 7 : SW7 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 8 : SW8 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 9 : SW9 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 10 : SW10 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 11 : SW11 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 12 : SW12 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 13 : SW13 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 14 : SW14 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 15 : SW15 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 16 : PMUIRQ0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 17 : COMMRX0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 18 : COMMTX0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 19 : CTIIRQ0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 20 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 21 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 22 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 23 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 24 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 25 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 26 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 27 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 28 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 29 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 30 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 31 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 32 : IRQ0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 33 : IRQ1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 34 : IRQ2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 35 : IRQ3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 36 : IRQ4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 37 : IRQ5 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 38 : IRQ6 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 39 : IRQ7 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 40 : PL310ERR */\r
+ Userdef_INTC_Dummy_Interrupt, /* 41 : DMAINT0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 42 : DMAINT1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 43 : DMAINT2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 44 : DMAINT3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 45 : DMAINT4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 46 : DMAINT5 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 47 : DMAINT6 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 48 : DMAINT7 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 49 : DMAINT8 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 50 : DMAINT9 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 51 : DMAINT10 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 52 : DMAINT11 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 53 : DMAINT12 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 54 : DMAINT13 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 55 : DMAINT14 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 56 : DMAINT15 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 57 : DMAERR */\r
+ Userdef_INTC_Dummy_Interrupt, /* 58 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 59 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 60 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 61 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 62 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 63 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 64 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 65 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 66 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 67 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 68 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 69 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 70 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 71 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 72 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 73 : USBI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 74 : USBI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 75 : S0_VI_VSYNC0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 76 : S0_LO_VSYNC0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 77 : S0_VSYNCERR0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 78 : GR3_VLINE0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 79 : S0_VFIELD0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 80 : IV1_VBUFERR0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 81 : IV3_VBUFERR0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 82 : IV5_VBUFERR0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 83 : IV6_VBUFERR0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 84 : S0_WLINE0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 85 : S1_VI_VSYNC0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 86 : S1_LO_VSYNC0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 87 : S1_VSYNCERR0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 88 : S1_VFIELD0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 89 : IV2_VBUFERR0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 90 : IV4_VBUFERR0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 91 : S1_WLINE0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 92 : OIR_VI_VSYNC0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 93 : OIR_LO_VSYNC0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 94 : OIR_VSYNCERR0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 95 : OIR_VFIELD0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 96 : IV7_VBUFERR0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 97 : IV8_VBUFERR0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 98 : OIR_WLINE0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 99 : S0_VI_VSYNC1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 100 : S0_LO_VSYNC1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 101 : S0_VSYNCERR1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 102 : GR3_VLINE1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 103 : S0_VFIELD1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 104 : IV1_VBUFERR1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 105 : IV3_VBUFERR1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 106 : IV5_VBUFERR1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 107 : IV6_VBUFERR1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 108 : S0_WLINE1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 109 : S1_VI_VSYNC1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 110 : S1_LO_VSYNC1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 111 : S1_VSYNCERR1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 112 : S1_VFIELD1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 113 : IV2_VBUFERR1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 114 : IV4_VBUFERR1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 115 : S1_WLINE1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 116 : OIR_VI_VSYNC1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 117 : OIR_LO_VSYNC1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 118 : OIR_VLINE1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 119 : OIR_VFIELD1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 120 : IV7_VBUFERR1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 121 : IV8_VBUFERR1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 122 : OIR_WLINE1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 123 : IMRDI */\r
+ Userdef_INTC_Dummy_Interrupt, /* 124 : IMR2I0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 125 : IMR2I1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 126 : JEDI */\r
+ Userdef_INTC_Dummy_Interrupt, /* 127 : JDTI */\r
+ Userdef_INTC_Dummy_Interrupt, /* 128 : CMP0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 129 : CMP1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 130 : INT0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 131 : INT1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 132 : INT2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 133 : INT3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 134 : OSTMI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 135 : OSTMI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 136 : CMI */\r
+ Userdef_INTC_Dummy_Interrupt, /* 137 : WTOUT */\r
+ Userdef_INTC_Dummy_Interrupt, /* 138 : ITI */\r
+ Userdef_INTC_Dummy_Interrupt, /* 139 : TGI0A */\r
+ Userdef_INTC_Dummy_Interrupt, /* 140 : TGI0B */\r
+ Userdef_INTC_Dummy_Interrupt, /* 141 : TGI0C */\r
+ Userdef_INTC_Dummy_Interrupt, /* 142 : TGI0D */\r
+ Userdef_INTC_Dummy_Interrupt, /* 143 : TGI0V */\r
+ Userdef_INTC_Dummy_Interrupt, /* 144 : TGI0E */\r
+ Userdef_INTC_Dummy_Interrupt, /* 145 : TGI0F */\r
+ Userdef_INTC_Dummy_Interrupt, /* 146 : TGI1A */\r
+ Userdef_INTC_Dummy_Interrupt, /* 147 : TGI1B */\r
+ Userdef_INTC_Dummy_Interrupt, /* 148 : TGI1V */\r
+ Userdef_INTC_Dummy_Interrupt, /* 149 : TGI1U */\r
+ Userdef_INTC_Dummy_Interrupt, /* 150 : TGI2A */\r
+ Userdef_INTC_Dummy_Interrupt, /* 151 : TGI2B */\r
+ Userdef_INTC_Dummy_Interrupt, /* 152 : TGI2V */\r
+ Userdef_INTC_Dummy_Interrupt, /* 153 : TGI2U */\r
+ Userdef_INTC_Dummy_Interrupt, /* 154 : TGI3A */\r
+ Userdef_INTC_Dummy_Interrupt, /* 155 : TGI3B */\r
+ Userdef_INTC_Dummy_Interrupt, /* 156 : TGI3C */\r
+ Userdef_INTC_Dummy_Interrupt, /* 157 : TGI3D */\r
+ Userdef_INTC_Dummy_Interrupt, /* 158 : TGI3V */\r
+ Userdef_INTC_Dummy_Interrupt, /* 159 : TGI4A */\r
+ Userdef_INTC_Dummy_Interrupt, /* 160 : TGI4B */\r
+ Userdef_INTC_Dummy_Interrupt, /* 161 : TGI4C */\r
+ Userdef_INTC_Dummy_Interrupt, /* 162 : TGI4D */\r
+ Userdef_INTC_Dummy_Interrupt, /* 163 : TGI4V */\r
+ Userdef_INTC_Dummy_Interrupt, /* 164 : CMI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 165 : CMI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 166 : SGDEI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 167 : SGDEI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 168 : SGDEI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 169 : SGDEI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 170 : ADI */\r
+ Userdef_INTC_Dummy_Interrupt, /* 171 : ADWAR */\r
+ Userdef_INTC_Dummy_Interrupt, /* 172 : SSII0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 173 : SSIRXI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 174 : SSITXI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 175 : SSII1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 176 : SSIRXI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 177 : SSITXI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 178 : SSII2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 179 : SSIRTI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 180 : SSII3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 181 : SSIRXI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 182 : SSITXI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 183 : SSII4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 184 : SSIRTI4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 185 : SSII5 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 186 : SSIRXI5 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 187 : SSITXI5 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 188 : SPDIFI */\r
+ Userdef_INTC_Dummy_Interrupt, /* 189 : TEI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 190 : RI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 191 : TI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 192 : SPI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 193 : STI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 194 : NAKI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 195 : ALI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 196 : TMOI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 197 : TEI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 198 : RI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 199 : TI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 200 : SPI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 201 : STI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 202 : NAKI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 203 : ALI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 204 : TMOI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 205 : TEI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 206 : RI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 207 : TI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 208 : SPI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 209 : STI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 210 : NAKI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 211 : ALI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 212 : TMOI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 213 : TEI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 214 : RI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 215 : TI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 216 : SPI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 217 : STI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 218 : NAKI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 219 : ALI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 220 : TMOI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 221 : BRI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 222 : ERI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 223 : RXI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 224 : TXI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 225 : BRI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 226 : ERI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 227 : RXI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 228 : TXI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 229 : BRI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 230 : ERI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 231 : RXI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 232 : TXI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 233 : BRI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 234 : ERI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 235 : RXI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 236 : TXI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 237 : BRI4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 238 : ERI4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 239 : RXI4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 240 : TXI4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 241 : BRI5 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 242 : ERI5 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 243 : RXI5 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 244 : TXI5 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 245 : BRI6 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 246 : ERI6 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 247 : RXI6 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 248 : TXI6 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 249 : BRI7 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 250 : ERI7 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 251 : RXI7 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 252 : TXI7 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 253 : GERI */\r
+ Userdef_INTC_Dummy_Interrupt, /* 254 : RFI */\r
+ Userdef_INTC_Dummy_Interrupt, /* 255 : CFRXI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 256 : CERI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 257 : CTXI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 258 : CFRXI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 259 : CERI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 260 : CTXI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 261 : CFRXI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 262 : CERI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 263 : CTXI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 264 : CFRXI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 265 : CERI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 266 : CTXI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 267 : CFRXI4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 268 : CERI4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 269 : CTXI4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 270 : SPEI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 271 : SPRI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 272 : SPTI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 273 : SPEI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 274 : SPRI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 275 : SPTI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 276 : SPEI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 277 : SPRI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 278 : SPTI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 279 : SPEI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 280 : SPRI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 281 : SPTI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 282 : SPEI4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 283 : SPRI4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 284 : SPTI4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 285 : IEBBTD */\r
+ Userdef_INTC_Dummy_Interrupt, /* 286 : IEBBTERR */\r
+ Userdef_INTC_Dummy_Interrupt, /* 287 : IEBBTSTA */\r
+ Userdef_INTC_Dummy_Interrupt, /* 288 : IEBBTV */\r
+ Userdef_INTC_Dummy_Interrupt, /* 289 : ISY */\r
+ Userdef_INTC_Dummy_Interrupt, /* 290 : IERR */\r
+ Userdef_INTC_Dummy_Interrupt, /* 291 : ITARG */\r
+ Userdef_INTC_Dummy_Interrupt, /* 292 : ISEC */\r
+ Userdef_INTC_Dummy_Interrupt, /* 293 : IBUF */\r
+ Userdef_INTC_Dummy_Interrupt, /* 294 : IREADY */\r
+ Userdef_INTC_Dummy_Interrupt, /* 295 : FLSTE */\r
+ Userdef_INTC_Dummy_Interrupt, /* 296 : FLTENDI */\r
+ Userdef_INTC_Dummy_Interrupt, /* 297 : FLTREQ0I */\r
+ Userdef_INTC_Dummy_Interrupt, /* 298 : FLTREQ1I */\r
+ Userdef_INTC_Dummy_Interrupt, /* 299 : MMC0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 300 : MMC1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 301 : MMC2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 302 : SDHI0_3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 303 : SDHI0_0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 304 : SDHI0_1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 305 : SDHI1_3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 306 : SDHI1_0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 307 : SDHI1_1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 308 : ARM */\r
+ Userdef_INTC_Dummy_Interrupt, /* 309 : PRD */\r
+ Userdef_INTC_Dummy_Interrupt, /* 310 : CUP */\r
+ Userdef_INTC_Dummy_Interrupt, /* 311 : SCUAI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 312 : SCUAI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 313 : SCUFDI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 314 : SCUFDI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 315 : SCUFDI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 316 : SCUFDI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 317 : SCUFUI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 318 : SCUFUI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 319 : SCUFUI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 320 : SCUFUI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 321 : SCUDVI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 322 : SCUDVI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 323 : SCUDVI2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 324 : SCUDVI3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 325 : MLBCI */\r
+ Userdef_INTC_Dummy_Interrupt, /* 326 : MLBSI */\r
+ Userdef_INTC_Dummy_Interrupt, /* 327 : DRC0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 328 : DRC1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 329 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 330 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 331 : LINI0_INT_T */\r
+ Userdef_INTC_Dummy_Interrupt, /* 332 : LINI0_INT_R */\r
+ Userdef_INTC_Dummy_Interrupt, /* 333 : LINI0_INT_S */\r
+ Userdef_INTC_Dummy_Interrupt, /* 334 : LINI0_INT_M */\r
+ Userdef_INTC_Dummy_Interrupt, /* 335 : LINI1_INT_T */\r
+ Userdef_INTC_Dummy_Interrupt, /* 336 : LINI1_INT_R */\r
+ Userdef_INTC_Dummy_Interrupt, /* 337 : LINI1_INT_S */\r
+ Userdef_INTC_Dummy_Interrupt, /* 338 : LINI1_INT_M */\r
+ Userdef_INTC_Dummy_Interrupt, /* 339 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 340 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 341 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 342 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 343 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 344 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 345 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 346 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 347 : ERI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 348 : RXI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 349 : TXI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 350 : TEI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 351 : ERI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 352 : RXI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 353 : TXI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 354 : TEI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 355 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 356 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 357 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 358 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 359 : ETHERI */\r
+ Userdef_INTC_Dummy_Interrupt, /* 360 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 361 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 362 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 363 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 364 : CEUI */\r
+ Userdef_INTC_Dummy_Interrupt, /* 365 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 366 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 367 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 368 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 369 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 370 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 371 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 372 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 373 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 374 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 375 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 376 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 377 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 378 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 379 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 380 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 381 : H2XMLB_ERRINT */\r
+ Userdef_INTC_Dummy_Interrupt, /* 382 : H2XIC1_ERRINT */\r
+ Userdef_INTC_Dummy_Interrupt, /* 383 : X2HPERI1_ERRINT*/\r
+ Userdef_INTC_Dummy_Interrupt, /* 384 : X2HPERI2_ERRINT*/\r
+ Userdef_INTC_Dummy_Interrupt, /* 385 : X2HPERI34_ERRINT*/\r
+ Userdef_INTC_Dummy_Interrupt, /* 386 : X2HPERI5_ERRINT*/\r
+ Userdef_INTC_Dummy_Interrupt, /* 387 : X2HPERI67_ERRINT*/\r
+ Userdef_INTC_Dummy_Interrupt, /* 388 : X2HDBGR_ERRINT*/\r
+ Userdef_INTC_Dummy_Interrupt, /* 389 : X2HBSC_ERRINT */\r
+ Userdef_INTC_Dummy_Interrupt, /* 390 : X2HSPI1_ERRINT*/\r
+ Userdef_INTC_Dummy_Interrupt, /* 391 : X2HSPI2_ERRINT*/\r
+ Userdef_INTC_Dummy_Interrupt, /* 392 : PRRI */\r
+ Userdef_INTC_Dummy_Interrupt, /* 393 : IFEI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 394 : OFFI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 395 : PFVEI0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 396 : IFEI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 397 : OFFI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 398 : PFVEI1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 399 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 400 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 401 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 402 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 403 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 404 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 405 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 406 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 407 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 408 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 409 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 410 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 411 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 412 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 413 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 414 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 415 : <reserved> */\r
+ Userdef_INTC_Dummy_Interrupt, /* 416 : TINT0 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 417 : TINT1 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 418 : TINT2 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 419 : TINT3 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 420 : TINT4 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 421 : TINT5 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 422 : TINT6 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 423 : TINT7 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 424 : TINT8 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 425 : TINT9 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 426 : TINT10 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 427 : TINT11 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 428 : TINT12 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 429 : TINT13 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 430 : TINT14 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 431 : TINT15 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 432 : TINT16 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 433 : TINT17 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 434 : TINT18 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 435 : TINT19 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 436 : TINT20 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 437 : TINT21 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 438 : TINT22 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 439 : TINT23 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 440 : TINT24 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 441 : TINT25 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 442 : TINT26 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 443 : TINT27 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 444 : TINT28 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 445 : TINT29 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 446 : TINT30 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 447 : TINT31 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 448 : TINT32 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 449 : TINT33 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 450 : TINT34 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 451 : TINT35 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 452 : TINT36 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 453 : TINT37 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 454 : TINT38 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 455 : TINT39 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 456 : TINT40 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 457 : TINT41 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 458 : TINT42 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 459 : TINT43 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 460 : TINT44 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 461 : TINT45 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 462 : TINT46 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 463 : TINT47 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 464 : TINT48 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 465 : TINT49 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 466 : TINT50 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 467 : TINT51 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 468 : TINT52 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 469 : TINT53 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 470 : TINT54 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 471 : TINT55 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 472 : TINT56 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 473 : TINT57 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 474 : TINT58 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 475 : TINT59 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 476 : TINT60 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 477 : TINT61 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 478 : TINT62 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 479 : TINT63 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 480 : TINT64 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 481 : TINT65 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 482 : TINT66 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 483 : TINT67 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 484 : TINT68 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 485 : TINT69 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 486 : TINT70 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 487 : TINT71 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 488 : TINT72 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 489 : TINT73 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 490 : TINT74 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 491 : TINT75 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 492 : TINT76 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 493 : TINT77 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 494 : TINT78 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 495 : TINT79 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 496 : TINT80 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 497 : TINT81 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 498 : TINT82 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 499 : TINT83 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 500 : TINT84 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 501 : TINT85 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 502 : TINT86 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 503 : TINT87 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 504 : TINT88 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 505 : TINT89 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 506 : TINT90 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 507 : TINT91 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 508 : TINT92 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 509 : TINT93 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 510 : TINT94 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 511 : TINT95 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 512 : TINT96 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 513 : TINT97 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 514 : TINT98 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 515 : TINT99 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 516 : TINT100 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 517 : TINT101 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 518 : TINT102 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 519 : TINT103 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 520 : TINT104 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 521 : TINT105 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 522 : TINT106 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 523 : TINT107 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 524 : TINT108 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 525 : TINT109 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 526 : TINT110 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 527 : TINT111 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 528 : TINT112 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 529 : TINT113 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 530 : TINT114 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 531 : TINT115 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 532 : TINT116 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 533 : TINT117 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 534 : TINT118 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 535 : TINT119 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 536 : TINT120 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 537 : TINT121 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 538 : TINT122 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 539 : TINT123 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 540 : TINT124 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 541 : TINT125 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 542 : TINT126 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 543 : TINT127 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 544 : TINT128 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 545 : TINT129 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 546 : TINT130 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 547 : TINT131 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 548 : TINT132 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 549 : TINT133 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 550 : TINT134 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 551 : TINT135 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 552 : TINT136 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 553 : TINT137 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 554 : TINT138 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 555 : TINT139 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 556 : TINT140 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 557 : TINT141 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 558 : TINT142 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 559 : TINT143 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 560 : TINT144 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 561 : TINT145 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 562 : TINT146 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 563 : TINT147 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 564 : TINT148 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 565 : TINT149 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 566 : TINT150 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 567 : TINT151 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 568 : TINT152 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 569 : TINT153 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 570 : TINT154 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 571 : TINT155 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 572 : TINT156 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 573 : TINT157 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 574 : TINT158 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 575 : TINT159 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 576 : TINT160 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 577 : TINT161 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 578 : TINT162 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 579 : TINT163 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 580 : TINT164 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 581 : TINT165 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 582 : TINT166 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 583 : TINT167 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 584 : TINT168 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 585 : TINT169 */\r
+ Userdef_INTC_Dummy_Interrupt, /* 586 : TINT170 */\r
+};\r
+\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_INTC_RegistIntFunc\r
+* Description :\r
+* Arguments : uint16_t int_id\r
+* : void (* func)(uint32_t)\r
+* Return Value : none\r
+******************************************************************************/\r
+void Userdef_INTC_RegistIntFunc(uint16_t int_id, void (* func)(uint32_t int_sense))\r
+{\r
+ intc_func_table[int_id] = func;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_INTC_UndefId\r
+* Description :\r
+* Arguments : uint16_t int_id\r
+* Return Value : none\r
+******************************************************************************/\r
+void Userdef_INTC_UndefId(uint16_t int_id)\r
+{\r
+ while (1)\r
+ {\r
+ /* Do Nothing */\r
+ }\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_INTC_Dummy_Interrupt\r
+* Description :\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+static void Userdef_INTC_Dummy_Interrupt(uint32_t int_sense)\r
+{\r
+ /* Do Nothing */\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_FIQ_HandlerExe\r
+* Description :\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void Userdef_FIQ_HandlerExe(void)\r
+{\r
+}\r
+\r
+/* The function called by the RTOS port layer after it has managed interrupt\r
+entry. */\r
+void vApplicationIRQHandler( uint32_t ulICCIAR )\r
+{\r
+uint32_t ulInterruptID;\r
+\r
+ /* Re-enable interrupts. */\r
+ __enable_irq();\r
+\r
+ /* The ID of the interrupt can be obtained by bitwise anding the ICCIAR value\r
+ with 0x3FF. */\r
+ ulInterruptID = ulICCIAR & 0x3FFUL;\r
+\r
+ /* Call the function installed in the array of installed handler functions. */\r
+ intc_func_table[ ulInterruptID ]( 0 );\r
+}\r
+\r
+\r
+/* END of File */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : ostm.c\r
+* $Rev: $\r
+* $Date:: $\r
+* Description : Aragon Sample Program - OS timer device driver (Initialize process)\r
+*******************************************************************************/\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "r_typedefs.h"\r
+#include "dev_drv.h" /* Device Driver common header */\r
+#include "devdrv_ostm.h" /* OSTM Driver header */\r
+#include "iodefine.h"\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+/* ==== OSTM H/W ==== */\r
+#define OSTM_CH_TOTAL (2)\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+static void OSTM_Open(volatile struct st_ostm_n * ostm);\r
+static void OSTM_Close(volatile struct st_ostm_n * ostm, uint32_t * count);\r
+\r
+/******************************************************************************\r
+* Function Name: R_OSTM_Init\r
+* Description :\r
+* Arguments : uint32_t channel\r
+* : uint32_t mode\r
+* : uint32_t cycle\r
+* Return Value : DEVDRV_SUCCESS\r
+* : DEVDRV_ERROR\r
+******************************************************************************/\r
+int32_t R_OSTM_Init(uint32_t channel, uint32_t mode, uint32_t cycle)\r
+{\r
+ int32_t ret;\r
+\r
+ if ((channel >= OSTM_CH_TOTAL) || (mode > OSTM_MODE_COMPARE))\r
+ {\r
+ return DEVDRV_ERROR;\r
+ }\r
+\r
+ switch (channel)\r
+ {\r
+ case DEVDRV_CH_0:\r
+ ret = Userdef_OSTM0_Init(mode, cycle);\r
+ break;\r
+ case DEVDRV_CH_1:\r
+ ret = Userdef_OSTM1_Init(mode, cycle);\r
+ break;\r
+ default:\r
+ ret = DEVDRV_ERROR;\r
+ break;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: R_OSTM_Open\r
+* Description :\r
+* Arguments : int32_t channel\r
+* Return Value : DEVDRV_SUCCESS\r
+* : DEVDRV_ERROR\r
+******************************************************************************/\r
+int32_t R_OSTM_Open(uint32_t channel)\r
+{\r
+ if (channel >= OSTM_CH_TOTAL)\r
+ {\r
+ return DEVDRV_ERROR;\r
+ }\r
+\r
+ switch (channel)\r
+ {\r
+ case DEVDRV_CH_0:\r
+ OSTM_Open(&OSTM0);\r
+ break;\r
+ case DEVDRV_CH_1:\r
+ OSTM_Open(&OSTM1);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return DEVDRV_SUCCESS;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: R_OSTM_Close\r
+* Description :\r
+* Arguments : uint32_t channel\r
+* Return Value : DEVDRV_SUCCESS\r
+* : DEVDRV_ERROR\r
+******************************************************************************/\r
+int32_t R_OSTM_Close(uint32_t channel, uint32_t * count)\r
+{\r
+ if (channel >= OSTM_CH_TOTAL)\r
+ {\r
+ return DEVDRV_ERROR;\r
+ }\r
+\r
+ switch (channel)\r
+ {\r
+ case DEVDRV_CH_0:\r
+ OSTM_Close(&OSTM0, count);\r
+ break;\r
+ case DEVDRV_CH_1:\r
+ OSTM_Close(&OSTM1, count);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return DEVDRV_SUCCESS;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: int_ostm0_interrupt\r
+* Description :\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+int32_t R_OSTM_Interrupt(uint32_t channel)\r
+{\r
+ if (channel >= OSTM_CH_TOTAL)\r
+ {\r
+ return DEVDRV_ERROR;\r
+ }\r
+\r
+ switch (channel)\r
+ {\r
+ case DEVDRV_CH_0:\r
+ Userdef_OSTM0_Int();\r
+ break;\r
+ case DEVDRV_CH_1:\r
+ Userdef_OSTM1_Int();\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return DEVDRV_SUCCESS;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name: OSTM_Open\r
+* Description : This function opens OSTM.\r
+* Arguments : volatile struct st_scif_n * ostm\r
+* Return Value : none\r
+*******************************************************************************/\r
+static void OSTM_Open(volatile struct st_ostm_n * ostm)\r
+{\r
+ ostm->OSTMnTS.BIT.OSTMnTS = 1;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: OSTM_Close\r
+* Description : This function closes OSTM.\r
+* Arguments : volatile struct st_scif_n * ostm\r
+* Return Value : none\r
+******************************************************************************/\r
+static void OSTM_Close(volatile struct st_ostm_n * ostm, uint32_t * count)\r
+{\r
+ ostm->OSTMnTT.BIT.OSTMnTT = 1;\r
+ *count = ostm->OSTMnCNT;\r
+}\r
+\r
+/* End of File */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : ostm_userdef.c\r
+* $Rev: $\r
+* $Date:: $\r
+* Device(s) : Aragon\r
+* Tool-Chain : DS-5 Ver 5.13\r
+* : ARM Complier\r
+* OS : \r
+* H/W Platform : Aragon CPU Board\r
+* Description : Aragon Sample Program - OS timer device driver (User define function)\r
+* Operation : \r
+* Limitations : \r
+*******************************************************************************/\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "r_typedefs.h"\r
+#include "dev_drv.h" /* Device Driver common header */\r
+#include "devdrv_ostm.h" /* OSTM Driver header */\r
+#include "devdrv_intc.h" /* INTC Driver Header */\r
+#include "iodefine.h"\r
+#include "main.h"\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+#define P0_CLOCK_FREQUENCY_kHz (33.333 * 1000) /* 33.333MHz */\r
+#define MAX_CYCLE_msec (0xFFFFFFFF / P0_CLOCK_FREQUENCY_kHz)\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+static volatile uint8_t ostm_int_flg;\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_OSTM0_Init\r
+* Description :\r
+* Arguments : uint32_t mode\r
+* : uint32_t cycle\r
+* Return Value : DEVDRV_SUCCESS\r
+* : DEVDRV_ERROR\r
+******************************************************************************/\r
+int32_t Userdef_OSTM0_Init(uint32_t mode, uint32_t cycle)\r
+{\r
+ return DEVDRV_SUCCESS;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_OSTM1_Init\r
+* Description :\r
+* Arguments : uint32_t mode\r
+* : uint32_t cycle\r
+* Return Value : DEVDRV_SUCCESS\r
+* : DEVDRV_ERROR\r
+******************************************************************************/\r
+int32_t Userdef_OSTM1_Init(uint32_t mode, uint32_t cycle)\r
+{\r
+ return 0;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_OSTM0_Int\r
+* Description : \r
+* Arguments : \r
+* Return Value : none\r
+******************************************************************************/\r
+void Userdef_OSTM0_Int(void)\r
+{\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_OSTM1_Int\r
+* Description : \r
+* Arguments : \r
+* Return Value : none\r
+******************************************************************************/\r
+void Userdef_OSTM1_Int(void)\r
+{\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_OSTM0_WaitInt\r
+* Description : \r
+* Arguments : \r
+* Return Value : none\r
+******************************************************************************/\r
+void Userdef_OSTM0_WaitInt(void)\r
+{\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_OSTM1_WaitInt\r
+* Description : \r
+* Arguments : \r
+* Return Value : none\r
+******************************************************************************/\r
+void Userdef_OSTM1_WaitInt(void)\r
+{\r
+}\r
+\r
+/* End of File */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : scif_uart_initialize.c\r
+* $Rev: $\r
+* $Date:: $\r
+* Description : Aragon Sample Program - SCIF UART device driver (Initialize process)\r
+*******************************************************************************/\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "r_typedefs.h"\r
+#include "dev_drv.h" /* Device Driver common header */\r
+#include "devdrv_scif_uart.h" /* UART Driver header */\r
+#include "iodefine.h"\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+#define SCIF_UART_CH_TOTAL (8)\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+* Function Name: R_SCIF_UART_Init\r
+* Description :\r
+* Arguments : uint32_t channel\r
+* : uint32_t mode\r
+* : : SCIF_UART_MODE_W\r
+* : : SCIF_UART_MODE_R\r
+* : : SCIF_UART_MODE_RW\r
+* : uint16_t cks\r
+* : uint8_t scbrr\r
+* Return Value : DEVDRV_SUCCESS : Success\r
+* : DEVDRV_ERROR : Error\r
+******************************************************************************/\r
+int32_t R_SCIF_UART_Init(uint32_t channel, uint32_t mode, uint16_t cks, uint8_t scbrr)\r
+{\r
+ if ((channel >= SCIF_UART_CH_TOTAL) || (mode < SCIF_UART_MODE_W) || (mode > SCIF_UART_MODE_RW) || (cks > 3))\r
+ {\r
+ return DEVDRV_ERROR;\r
+ }\r
+\r
+ switch (channel)\r
+ {\r
+ case DEVDRV_CH_2:\r
+ Userdef_SCIF2_UART_Init(mode, cks, scbrr);\r
+ break;\r
+ default:\r
+ /* Do Nothing */\r
+ break;\r
+ }\r
+\r
+ return DEVDRV_SUCCESS;\r
+}\r
+\r
+/* End of File */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : scif_uart_userdef.c\r
+* $Rev: $\r
+* $Date:: $\r
+* Device(s) : Aragon\r
+* Tool-Chain : DS-5 Ver 5.13\r
+* : ARM Complier\r
+* OS : \r
+* H/W Platform : Aragon CPU Board\r
+* Description : Aragon Sample Program - SCIF UART device driver (User define function)\r
+* Operation : \r
+* Limitations : \r
+*******************************************************************************/\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include <stdio.h>\r
+#include "r_typedefs.h"\r
+#include "dev_drv.h" /* Device Driver common header */\r
+#include "devdrv_scif_uart.h" /* UART Driver header */\r
+#include "devdrv_intc.h" /* INTC Driver Header */\r
+#include "iodefine.h"\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+* Function Name: Userdef_SCIF2_UART_Init\r
+* Description :\r
+* Arguments : uint8_t mode\r
+* : uint16_t cks\r
+* : uint8_t scbrr\r
+* Return Value : none\r
+******************************************************************************/\r
+void Userdef_SCIF2_UART_Init(uint8_t mode, uint16_t cks, uint8_t scbrr)\r
+{\r
+ /* ==== SCIF initial setting ==== */\r
+ /* ---- Serial control register (SCSCR2) setting ---- */\r
+ /* SCIF transmitting and receiving operations stop */\r
+ SCIF2.SCSCR.WORD = 0x0000;\r
+\r
+ if (SCIF_UART_MODE_W == (mode & SCIF_UART_MODE_W))\r
+ {\r
+ /* ---- FIFO control register (SCFCR2) setting ---- */\r
+ SCIF2.SCFCR.BIT.TFRST = 1; /* Transmit FIFO reset */\r
+ }\r
+\r
+ if (SCIF_UART_MODE_R == (mode & SCIF_UART_MODE_R))\r
+ {\r
+ /* ---- FIFO control register (SCFCR2) setting ---- */\r
+ /* SCIF transmitting and receiving operations stop */\r
+ SCIF2.SCFCR.BIT.RFRST = 1;\r
+\r
+ /* Receive FIFO data register reset */\r
+ }\r
+\r
+ /* ---- Serial status register(SCFSR2) setting ---- */\r
+ /* ER,BRK,DR bit clear */\r
+ SCIF2.SCFSR.WORD &= 0xFF6E;\r
+\r
+ /* ---- Line status register (SCLSR2) setting ---- */\r
+ /* ORER bit clear */\r
+ SCIF2.SCLSR.BIT.ORER = 0;\r
+\r
+ /* ---- Serial control register (SCSCR2) setting ---- */\r
+ /* B'00 : Internal CLK */\r
+ SCIF2.SCSCR.BIT.CKE = 0x0;\r
+\r
+ /* ---- Serial mode register (SCSMR2) setting ---- */\r
+ /* Communication mode 0: Asynchronous mode */\r
+ /* Character length 0: 8-bit data */\r
+ /* Parity enable 0: Add and check are disabled */\r
+ /* Stop bit length 0: 1 stop bit */\r
+ /* Clock select cks(argument) */\r
+ SCIF2.SCSMR.WORD = cks & 0x0003;\r
+\r
+ /* ---- Sets the Serial extension mode register (SCEMR2) ---- */\r
+ /* Baud rate generator double-speed mode, 0: Normal mode */\r
+ /* Base clock select in asynchronous mode, */\r
+ /* 0: Base clock is 16 times the bit rate */\r
+ SCIF2.SCEMR.WORD = 0x0000;\r
+\r
+ /* ---- Bit rate register (SCBRR2) setting ---- */\r
+ SCIF2.SCBRR.BYTE = scbrr;\r
+\r
+ /* ---- FIFO control register (SCFCR2) setting ---- */\r
+ /* RTS output active trigger :Initial value */\r
+ /* Receive FIFO data trigger :1-data */\r
+ /* Transmit FIFO data trigger :0-data */\r
+ /* Modem control enable :Disabled */\r
+ /* Receive FIFO data register reset :Disabled */\r
+ /* Loop-back test :Disabled */\r
+ SCIF2.SCFCR.WORD = 0x0030;\r
+\r
+ /* ---- Serial port register (SCSPTR2) setting ---- */\r
+ /* Serial port break output(SPB2IO) 1: Enabled */\r
+ /* Serial port break data(SPB2DT) 1: High-level */\r
+ SCIF2.SCSPTR.WORD |= 0x0003;\r
+}\r
+\r
+/* End of File */\r
+\r
--- /dev/null
+;/*******************************************************************************\r
+;* DISCLAIMER\r
+;* This software is supplied by Renesas Electronics Corporation and is only\r
+;* intended for use with Renesas products. No other uses are authorized. This\r
+;* software is owned by Renesas Electronics Corporation and is protected under\r
+;* all applicable laws, including copyright laws.\r
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+;* Renesas reserves the right, without notice, to make changes to this software\r
+;* and to discontinue the availability of this software. By using this software,\r
+;* you agree to the additional terms and conditions found by accessing the\r
+;* following link:\r
+;* http://www.renesas.com/disclaimer\r
+;*\r
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* File Name : irqfiq_handler.s\r
+;* Version : 0.01\r
+;* Device(s) : Aragon\r
+;* Tool-Chain : DS-5 Ver 5.13\r
+;* ARM Complier\r
+;* :\r
+;* H/W Platform : Aragon CPU Board\r
+;* Description : Aragon Sample Program - IRQ, FIQ handler\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* History : DD.MM.YYYY Version Description\r
+;* : 23.05.2012 0.01\r
+;*******************************************************************************/\r
+\r
+; Standard definitions of mode bits and interrupt (I & F) flags in PSRs\r
+INTC_ICCIAR_ADDR EQU 0xE820200C\r
+INTC_ICCEOIR_ADDR EQU 0xE8202010\r
+\r
+\r
+;==================================================================\r
+; Entry point for the FIQ handler\r
+;==================================================================\r
+ PRESERVE8\r
+ AREA IRQ_FIQ_HANDLER, CODE, READONLY\r
+\r
+ IMPORT FiqHandler_Interrupt\r
+\r
+ EXPORT fiq_handler\r
+\r
+fiq_handler\r
+ BL FiqHandler_Interrupt\r
+\r
+fiq_handler_end\r
+ B fiq_handler_end\r
+\r
+\r
+Literals3\r
+ LTORG\r
+\r
+ END\r
--- /dev/null
+;/*******************************************************************************\r
+;* DISCLAIMER\r
+;* This software is supplied by Renesas Electronics Corporation and is only\r
+;* intended for use with Renesas products. No other uses are authorized. This\r
+;* software is owned by Renesas Electronics Corporation and is protected under\r
+;* all applicable laws, including copyright laws.\r
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+;* Renesas reserves the right, without notice, to make changes to this software\r
+;* and to discontinue the availability of this software. By using this software,\r
+;* you agree to the additional terms and conditions found by accessing the\r
+;* following link:\r
+;* http://www.renesas.com/disclaimer\r
+;*\r
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* File Name : reset_handler.s\r
+;* Version : 0.01\r
+;* Device(s) : Aragon\r
+;* Tool-Chain : DS-5 Ver 5.8\r
+;* ARM Complier \r
+;* : \r
+;* H/W Platform : Aragon CPU Board\r
+;* Description : Aragon Sample Program - Reset handler\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* History : DD.MM.YYYY Version Description\r
+;* : 23.05.2012 0.01\r
+;*******************************************************************************/\r
+\r
+; Standard definitions of mode bits and interrupt (I & F) flags in PSRs\r
+USR_MODE EQU 0x10\r
+FIQ_MODE EQU 0x11\r
+IRQ_MODE EQU 0x12\r
+SVC_MODE EQU 0x13\r
+ABT_MODE EQU 0x17\r
+UND_MODE EQU 0x1b\r
+SYS_MODE EQU 0x1f\r
+Thum_bit EQU 0x20 ; CPSR/SPSR Thumb bit\r
+\r
+\r
+;==================================================================\r
+; Entry point for the Reset handler\r
+;==================================================================\r
+ PRESERVE8\r
+ AREA RESET_HANDLER, CODE, READONLY\r
+\r
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Linker symbol from scatter file\r
+ IMPORT ||Image$$IRQ_STACK$$ZI$$Limit|| ; Linker symbol from scatter file\r
+ IMPORT ||Image$$FIQ_STACK$$ZI$$Limit|| ; Linker symbol from scatter file\r
+ IMPORT ||Image$$SVC_STACK$$ZI$$Limit|| ; Linker symbol from scatter file\r
+ IMPORT ||Image$$ABT_STACK$$ZI$$Limit|| ; Linker symbol from scatter file\r
+\r
+ IMPORT Peripheral_BasicInit\r
+ IMPORT init_TTB\r
+ IMPORT __main\r
+\r
+ EXPORT reset_handler\r
+ EXPORT undefined_handler\r
+ EXPORT svc_handler\r
+ EXPORT prefetch_handler\r
+ EXPORT abort_handler\r
+ EXPORT reserved_handler\r
+\r
+;==================================================================\r
+; Reset Handler\r
+;==================================================================\r
+reset_handler FUNCTION {}\r
+\r
+;==================================================================\r
+; Disable cache and MMU in case it was left enabled from an earlier run\r
+; This does not need to be done from a cold reset \r
+;==================================================================\r
+ MRC p15, 0, r0, c1, c0, 0 ;;; Read CP15 System Control register (SCTLR)\r
+ BIC r0, r0, #(0x1 << 12) ;;; Clear I bit 12 to disable I Cache\r
+ BIC r0, r0, #(0x1 << 2) ;;; Clear C bit 2 to disable D Cache\r
+ BIC r0, r0, #0x1 ;;; Clear M bit 0 to disable MMU\r
+ MCR p15, 0, r0, c1, c0, 0 ;;; Write value back to CP15 System Control register\r
+\r
+;==================================================================\r
+; Setting up Stack Area\r
+;==================================================================\r
+ ;;; SVC Mode(Default)\r
+ LDR sp, =||Image$$SVC_STACK$$ZI$$Limit||\r
+\r
+ CPS #IRQ_MODE ;;; IRQ Mode\r
+ LDR sp, =||Image$$IRQ_STACK$$ZI$$Limit||\r
+\r
+ CPS #FIQ_MODE ;;; FIQ Mode\r
+ LDR sp, =||Image$$FIQ_STACK$$ZI$$Limit||\r
+\r
+ CPS #ABT_MODE ;;; ABT Mode\r
+ LDR sp, =||Image$$ABT_STACK$$ZI$$Limit||\r
+\r
+;; FreeRTOS Note:\r
+;; FreeRTOS does not need a System/User mode stack as only tasks run in\r
+;; System/User mode, and their stack is allocated when the task is created.\r
+;; Therefore the CSTACK allocated in the linker script is instead given to\r
+;; Supervisor mode, and main() is called from Supervisor mode.\r
+\r
+ CPS #SVC_MODE ;;; SVC Mode\r
+\r
+;; SVC mode Stack pointer is set up ARM_LIB_STACK in the __main()->__entry()\r
+ LDR sp, =||Image$$ARM_LIB_STACK$$ZI$$Limit||\r
+\r
+;==================================================================\r
+; TLB maintenance, Invalidate Data and Instruction TLBs\r
+;==================================================================\r
+ MOV r0,#0\r
+ MCR p15, 0, r0, c8, c7, 0 ;;; Cortex-A9 I-TLB and D-TLB invalidation (TLBIALL)\r
+\r
+;===================================================================\r
+; Invalidate instruction cache, also flushes BTAC\r
+;===================================================================\r
+ MOV r0, #0 ;;; SBZ\r
+ MCR p15, 0, r0, c7, c5, 0 ;;; ICIALLU - Invalidate entire I Cache, and flushes branch target cache\r
+\r
+;==================================================================\r
+; Cache Invalidation code for Cortex-A9\r
+;==================================================================\r
+ ;;; Invalidate L1 Instruction Cache\r
+ MRC p15, 1, r0, c0, c0, 1 ;;; Read Cache Level ID Register (CLIDR)\r
+ TST r0, #0x3 ;;; Harvard Cache?\r
+ MOV r0, #0\r
+ MCRNE p15, 0, r0, c7, c5, 0 ;;; Invalidate Instruction Cache\r
+\r
+ ;;; Invalidate Data/Unified Caches\r
+ MRC p15, 1, r0, c0, c0, 1 ;;; Read CLIDR\r
+ ANDS r3, r0, #0x07000000 ;;; Extract coherency level\r
+ MOV r3, r3, LSR #23 ;;; Total cache levels << 1\r
+ BEQ Finished ;;; If 0, no need to clean\r
+\r
+ MOV r10, #0 ;;; R10 holds current cache level << 1\r
+Loop1\r
+ ADD r2, r10, r10, LSR #1 ;;; R2 holds cache "Set" position \r
+ MOV r1, r0, LSR r2 ;;; Bottom 3 bits are the Cache-type for this level\r
+ AND r1, r1, #7 ;;; Isolate those lower 3 bits\r
+ CMP r1, #2\r
+ BLT Skip ;;; No cache or only instruction cache at this level\r
+\r
+ MCR p15, 2, r10, c0, c0, 0 ;;; Write the Cache Size selection register (CSSELR)\r
+ ISB ;;; ISB to sync the change to the CacheSizeID reg\r
+ MRC p15, 1, r1, c0, c0, 0 ;;; Reads current Cache Size ID register (CCSIDR)\r
+ AND r2, r1, #7 ;;; Extract the line length field\r
+ ADD r2, r2, #4 ;;; Add 4 for the line length offset (log2 16 bytes)\r
+ LDR r4, =0x3FF\r
+ ANDS r4, r4, r1, LSR #3 ;;; R4 is the max number on the way size (right aligned)\r
+ CLZ r5, r4 ;;; R5 is the bit position of the way size increment\r
+ LDR r7, =0x7FFF\r
+ ANDS r7, r7, r1, LSR #13 ;;; R7 is the max number of the index size (right aligned)\r
+Loop2\r
+ MOV r9, r4 ;;; R9 working copy of the max way size (right aligned)\r
+\r
+Loop3\r
+ ORR r11, r10, r9, LSL r5 ;;; Factor in the Way number and cache number into R11\r
+ ORR r11, r11, r7, LSL r2 ;;; Factor in the Set number\r
+ MCR p15, 0, r11, c7, c6, 2 ;;; Invalidate by Set/Way (DCISW)\r
+ SUBS r9, r9, #1 ;;; Decrement the Way number\r
+ BGE Loop3\r
+ SUBS r7, r7, #1 ;;; Decrement the Set number\r
+ BGE Loop2\r
+Skip\r
+ ADD r10, r10, #2 ;;; increment the cache number\r
+ CMP r3, r10\r
+ BGT Loop1\r
+\r
+Finished\r
+\r
+;==================================================================\r
+; TTB initialize\r
+;==================================================================\r
+ BL init_TTB ;;; Initialize TTB\r
+\r
+;===================================================================\r
+; Setup domain control register - Enable all domains to client mode\r
+;===================================================================\r
+ MRC p15, 0, r0, c3, c0, 0 ;;; Read Domain Access Control Register (DACR)\r
+ LDR r0, =0x55555555 ;;; Initialize every domain entry to b01 (client)\r
+ MCR p15, 0, r0, c3, c0, 0 ;;; Write Domain Access Control Register\r
+\r
+ IF {TARGET_FEATURE_NEON} || {TARGET_FPU_VFP}\r
+;==================================================================\r
+; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.\r
+; Enables Full Access i.e. in both privileged and non privileged modes\r
+;==================================================================\r
+ MRC p15, 0, r0, c1, c0, 2 ;;; Read Coprocessor Access Control Register (CPACR)\r
+ ORR r0, r0, #(0xF << 20) ;;; Enable access to CP 10 & 11\r
+ MCR p15, 0, r0, c1, c0, 2 ;;; Write Coprocessor Access Control Register (CPACR)\r
+ ISB\r
+\r
+;=================================================================\r
+; Switch on the VFP and NEON hardware\r
+;=================================================================\r
+ MOV r0, #0x40000000\r
+ VMSR FPEXC, r0 ;;; Write FPEXC register, EN bit set\r
+\r
+ ENDIF\r
+\r
+;===================================================================\r
+; Enable MMU\r
+; Leaving the caches disabled until after scatter loading(__main).\r
+;===================================================================\r
+ MRC p15, 0, r0, c1, c0, 0 ;;; Read CP15 System Control register (SCTLR)\r
+ BIC r0, r0, #(0x1 << 12) ;;; Clear I bit 12 to disable I Cache\r
+ BIC r0, r0, #(0x1 << 2) ;;; Clear C bit 2 to disable D Cache\r
+ BIC r0, r0, #0x2 ;;; Clear A bit 1 to disable strict alignment fault checking\r
+ ORR r0, r0, #0x1 ;;; Set M bit 0 to enable MMU before scatter loading\r
+ MCR p15, 0, r0, c1, c0, 0 ;;; Write CP15 System Control register\r
+\r
+;==================================================================\r
+; Hardware initialize\r
+; Initialize CPG, BSC for CS0 and CS1, and enable On-Chip Data-Retention RAM\r
+;==================================================================\r
+ LDR r12,=Peripheral_BasicInit ;;; Save this in register for possible long jump\r
+ BLX r12 ;;; Hardware Initialize\r
+\r
+;===================================================================\r
+; Branch to __main\r
+;===================================================================\r
+ LDR r12,=__main ;;; Save this in register for possible long jump\r
+ BX r12 ;;; Branch to __main C library entry point\r
+\r
+\r
+ ENDFUNC\r
+\r
+Literals2\r
+ LTORG\r
+\r
+\r
+;==================================================================\r
+; Other Handler\r
+;==================================================================\r
+undefined_handler\r
+ B undefined_handler ;;; Ž©”Ô’nƒ‹�[ƒv\r
+\r
+svc_handler\r
+ B svc_handler ;;; Ž©”Ô’nƒ‹�[ƒv\r
+\r
+prefetch_handler\r
+ B prefetch_handler ;;; Ž©”Ô’nƒ‹�[ƒv\r
+\r
+abort_handler\r
+ B abort_handler ;;; Ž©”Ô’nƒ‹�[ƒv\r
+\r
+reserved_handler\r
+ B reserved_handler ;;; Ž©”Ô’nƒ‹�[ƒv\r
+\r
+\r
+ END\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/******************************************************************************\r
+* File Name : command.h\r
+* $Rev: $\r
+* $Date:: $\r
+* Description : Aragon Sample Program - Command header\r
+******************************************************************************/\r
+#ifndef _COMMAND_H_\r
+#define _COMMAND_H_\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+typedef struct command_list\r
+{\r
+ char_t *cmd_str;\r
+ int32_t (*cmdexe)(int32_t, char_t **);\r
+ int32_t (*helpexe)(void);\r
+} command_list_t;\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+/* Maximum number of characters for arguments */\r
+#define COMMAND_MAX_ARGLENGTH (256)\r
+\r
+#define COMMAND_EXIT (-100)\r
+#define COMMAND_SUCCESS (0)\r
+#define COMMAND_ERROR (-1)\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+int32_t CommandExe(char_t * buff);\r
+void CommandSetCmdList(const command_list_t * cmd);\r
+\r
+#endif /* _COMMAND_H_ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/******************************************************************************\r
+* File Name : dev_drv.h\r
+* $Rev: $\r
+* $Date:: $\r
+* Description : Aragon Sample Program - Device driver header\r
+******************************************************************************/\r
+#ifndef _DEV_DRV_H_\r
+#define _DEV_DRV_H_\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+#define DEVDRV_SUCCESS (0) /* Success */\r
+#define DEVDRV_ERROR (-1) /* Failure */\r
+\r
+#define DEVDRV_FLAG_OFF (0) /* Flag OFF */\r
+#define DEVDRV_FLAG_ON (1) /* Flag ON */\r
+\r
+typedef enum devdrv_ch\r
+{\r
+ DEVDRV_CH_0, /* Channel 0 */\r
+ DEVDRV_CH_1, /* Channel 1 */\r
+ DEVDRV_CH_2, /* Channel 2 */\r
+ DEVDRV_CH_3, /* Channel 3 */\r
+ DEVDRV_CH_4, /* Channel 4 */\r
+ DEVDRV_CH_5, /* Channel 5 */\r
+ DEVDRV_CH_6, /* Channel 6 */\r
+ DEVDRV_CH_7, /* Channel 7 */\r
+ DEVDRV_CH_8, /* Channel 8 */\r
+ DEVDRV_CH_9, /* Channel 9 */\r
+ DEVDRV_CH_10, /* Channel 10 */\r
+ DEVDRV_CH_11, /* Channel 11 */\r
+ DEVDRV_CH_12, /* Channel 12 */\r
+ DEVDRV_CH_13, /* Channel 13 */\r
+ DEVDRV_CH_14, /* Channel 14 */\r
+ DEVDRV_CH_15 /* Channel 15 */\r
+} devdrv_ch_t;\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+\r
+#endif /* _DEV_DRV_H_ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/******************************************************************************\r
+* File Name : devdrv_common.h\r
+* $Rev: $\r
+* $Date:: $\r
+* Description : Aragon Sample Program - Common driver header\r
+******************************************************************************/\r
+#ifndef _DEVDRV_COMMON_H_\r
+#define _DEVDRV_COMMON_H_\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+#define BSC_AREA_CS0 (0x01) /* CS0 */\r
+#define BSC_AREA_CS1 (0x02) /* CS1 */\r
+#define BSC_AREA_CS2 (0x04) /* CS2 */\r
+#define BSC_AREA_CS3 (0x08) /* CS3 */\r
+#define BSC_AREA_CS4 (0x10) /* CS4 */\r
+#define BSC_AREA_CS5 (0x20) /* CS5 */\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+void R_BSC_Init(uint8_t area);\r
+void Userdef_BSC_CS0Init(void);\r
+void Userdef_BSC_CS1Init(void);\r
+void Userdef_BSC_CS2Init(void);\r
+void Userdef_BSC_CS3Init(void);\r
+void Userdef_BSC_CS4Init(void);\r
+void Userdef_BSC_CS5Init(void);\r
+\r
+#endif /* _DEVDRV_COMMON_H_ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/******************************************************************************\r
+* File Name : devdrv_intc.h\r
+* $Rev: 17531 $\r
+* $Date:: 2013-04-10 12:58:44 +0100#$\r
+* Description : Aragon Sample Program - INTC device driver header\r
+******************************************************************************/\r
+#ifndef _DEVDRV_INTC_H_\r
+#define _DEVDRV_INTC_H_\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+#define INTC_ID_TOTAL (587)\r
+\r
+#define INTC_ID_SW0 (0)\r
+#define INTC_ID_SW1 (1) /* */\r
+#define INTC_ID_SW2 (2) /* */\r
+#define INTC_ID_SW3 (3) /* */\r
+#define INTC_ID_SW4 (4) /* */\r
+#define INTC_ID_SW5 (5) /* */\r
+#define INTC_ID_SW6 (6) /* */\r
+#define INTC_ID_SW7 (7) /* */\r
+#define INTC_ID_SW8 (8) /* */\r
+#define INTC_ID_SW9 (9) /* */\r
+#define INTC_ID_SW10 (10) /* */\r
+#define INTC_ID_SW11 (11) /* */\r
+#define INTC_ID_SW12 (12) /* */\r
+#define INTC_ID_SW13 (13) /* */\r
+#define INTC_ID_SW14 (14) /* */\r
+#define INTC_ID_SW15 (15) /* */\r
+#define INTC_ID_PMUIRQ0 (16) /* CPU */\r
+#define INTC_ID_COMMRX0 (17) /* */\r
+#define INTC_ID_COMMTX0 (18) /* */\r
+#define INTC_ID_CTIIRQ0 (19) /* */\r
+#define INTC_ID_IRQ0 (32) /* IRQ */\r
+#define INTC_ID_IRQ1 (33) /* */\r
+#define INTC_ID_IRQ2 (34) /* */\r
+#define INTC_ID_IRQ3 (35) /* */\r
+#define INTC_ID_IRQ4 (36) /* */\r
+#define INTC_ID_IRQ5 (37) /* */\r
+#define INTC_ID_IRQ6 (38) /* */\r
+#define INTC_ID_IRQ7 (39) /* */\r
+#define INTC_ID_PL310ERR (40)\r
+#define INTC_ID_DMAINT0 (41)\r
+#define INTC_ID_DMAINT1 (42) /* */\r
+#define INTC_ID_DMAINT2 (43) /* */\r
+#define INTC_ID_DMAINT3 (44) /* */\r
+#define INTC_ID_DMAINT4 (45) /* */\r
+#define INTC_ID_DMAINT5 (46) /* */\r
+#define INTC_ID_DMAINT6 (47) /* */\r
+#define INTC_ID_DMAINT7 (48) /* */\r
+#define INTC_ID_DMAINT8 (49) /* */\r
+#define INTC_ID_DMAINT9 (50) /* */\r
+#define INTC_ID_DMAINT10 (51) /* */\r
+#define INTC_ID_DMAINT11 (52) /* */\r
+#define INTC_ID_DMAINT12 (53) /* */\r
+#define INTC_ID_DMAINT13 (54) /* */\r
+#define INTC_ID_DMAINT14 (55) /* */\r
+#define INTC_ID_DMAINT15 (56) /* */\r
+#define INTC_ID_DMAERR (57) /* */\r
+#define INTC_ID_USBI0 (73)\r
+#define INTC_ID_USBI1 (74) /* */\r
+#define INTC_ID_S0_VI_VSYNC0 (75)\r
+#define INTC_ID_S0_LO_VSYNC0 (76) /* */\r
+#define INTC_ID_S0_VSYNCERR0 (77) /* */\r
+#define INTC_ID_GR3_VLINE0 (78) /* */\r
+#define INTC_ID_S0_VFIELD0 (79) /* */\r
+#define INTC_ID_IV1_VBUFERR0 (80) /* */\r
+#define INTC_ID_IV3_VBUFERR0 (81) /* */\r
+#define INTC_ID_IV5_VBUFERR0 (82) /* */\r
+#define INTC_ID_IV6_VBUFERR0 (83) /* */\r
+#define INTC_ID_S0_WLINE0 (84) /* */\r
+#define INTC_ID_S1_VI_VSYNC0 (85) /* */\r
+#define INTC_ID_S1_LO_VSYNC0 (86) /* */\r
+#define INTC_ID_S1_VSYNCERR0 (87) /* */\r
+#define INTC_ID_S1_VFIELD0 (88) /* */\r
+#define INTC_ID_IV2_VBUFERR0 (89) /* */\r
+#define INTC_ID_IV4_VBUFERR0 (90) /* */\r
+#define INTC_ID_S1_WLINE0 (91) /* */\r
+#define INTC_ID_OIR_VI_VSYNC0 (92) /* */\r
+#define INTC_ID_OIR_LO_VSYNC0 (93) /* */\r
+#define INTC_ID_OIR_VSYNCERR0 (94) /* */\r
+#define INTC_ID_OIR_VFIELD0 (95) /* */\r
+#define INTC_ID_IV7_VBUFERR0 (96) /* */\r
+#define INTC_ID_IV8_VBUFERR0 (97) /* */\r
+#define INTC_ID_OIR_WLINE0 (98) /* */\r
+#define INTC_ID_S0_VI_VSYNC1 (99) /* */\r
+#define INTC_ID_S0_LO_VSYNC1 (100) /* */\r
+#define INTC_ID_S0_VSYNCERR1 (101) /* */\r
+#define INTC_ID_GR3_VLINE1 (102) /* */\r
+#define INTC_ID_S0_VFIELD1 (103) /* */\r
+#define INTC_ID_IV1_VBUFERR1 (104) /* */\r
+#define INTC_ID_IV3_VBUFERR1 (105) /* */\r
+#define INTC_ID_IV5_VBUFERR1 (106) /* */\r
+#define INTC_ID_IV6_VBUFERR1 (107) /* */\r
+#define INTC_ID_S0_WLINE1 (108) /* */\r
+#define INTC_ID_S1_VI_VSYNC1 (109) /* */\r
+#define INTC_ID_S1_LO_VSYNC1 (110) /* */\r
+#define INTC_ID_S1_VSYNCERR1 (111) /* */\r
+#define INTC_ID_S1_VFIELD1 (112) /* */\r
+#define INTC_ID_IV2_VBUFERR1 (113) /* */\r
+#define INTC_ID_IV4_VBUFERR1 (114) /* */\r
+#define INTC_ID_S1_WLINE1 (115) /* */\r
+#define INTC_ID_OIR_VI_VSYNC1 (116) /* */\r
+#define INTC_ID_OIR_LO_VSYNC1 (117) /* */\r
+#define INTC_ID_OIR_VLINE1 (118) /* */\r
+#define INTC_ID_OIR_VFIELD1 (119) /* */\r
+#define INTC_ID_IV7_VBUFERR1 (120) /* */\r
+#define INTC_ID_IV8_VBUFERR1 (121) /* */\r
+#define INTC_ID_OIR_WLINE1 (122) /* */\r
+#define INTC_ID_IMRDI (123)\r
+#define INTC_ID_IMR2I0 (124) /* */\r
+#define INTC_ID_IMR2I1 (125) /* */\r
+#define INTC_ID_JEDI (126)\r
+#define INTC_ID_JDTI (127) /* */\r
+#define INTC_ID_CMP0 (128)\r
+#define INTC_ID_CMP1 (129) /* */\r
+#define INTC_ID_INT0 (130)\r
+#define INTC_ID_INT1 (131) /* */\r
+#define INTC_ID_INT2 (132) /* */\r
+#define INTC_ID_INT3 (133) /* */\r
+#define INTC_ID_OSTMI0 (134)\r
+#define INTC_ID_OSTMI1 (135) /* */\r
+#define INTC_ID_CMI (136)\r
+#define INTC_ID_WTOUT (137) /* */\r
+#define INTC_ID_ITI (138)\r
+#define INTC_ID_TGI0A (139)\r
+#define INTC_ID_TGI0B (140) /* */\r
+#define INTC_ID_TGI0C (141) /* */\r
+#define INTC_ID_TGI0D (142) /* */\r
+#define INTC_ID_TGI0V (143) /* */\r
+#define INTC_ID_TGI0E (144) /* */\r
+#define INTC_ID_TGI0F (145) /* */\r
+#define INTC_ID_TGI1A (146) /* */\r
+#define INTC_ID_TGI1B (147) /* */\r
+#define INTC_ID_TGI1V (148) /* */\r
+#define INTC_ID_TGI1U (149) /* */\r
+#define INTC_ID_TGI2A (150) /* */\r
+#define INTC_ID_TGI2B (151) /* */\r
+#define INTC_ID_TGI2V (152) /* */\r
+#define INTC_ID_TGI2U (153) /* */\r
+#define INTC_ID_TGI3A (154) /* */\r
+#define INTC_ID_TGI3B (155) /* */\r
+#define INTC_ID_TGI3C (156) /* */\r
+#define INTC_ID_TGI3D (157) /* */\r
+#define INTC_ID_TGI3V (158) /* */\r
+#define INTC_ID_TGI4A (159) /* */\r
+#define INTC_ID_TGI4B (160) /* */\r
+#define INTC_ID_TGI4C (161) /* */\r
+#define INTC_ID_TGI4D (162) /* */\r
+#define INTC_ID_TGI4V (163) /* */\r
+#define INTC_ID_CMI1 (164)\r
+#define INTC_ID_CMI2 (165) /* */\r
+#define INTC_ID_SGDEI0 (166)\r
+#define INTC_ID_SGDEI1 (167) /* */\r
+#define INTC_ID_SGDEI2 (168) /* */\r
+#define INTC_ID_SGDEI3 (169) /* */\r
+#define INTC_ID_ADI (170)\r
+#define INTC_ID_ADWAR (171) /* */\r
+#define INTC_ID_SSII0 (172)\r
+#define INTC_ID_SSIRXI0 (173) /* */\r
+#define INTC_ID_SSITXI0 (174) /* */\r
+#define INTC_ID_SSII1 (175) /* */\r
+#define INTC_ID_SSIRXI1 (176) /* */\r
+#define INTC_ID_SSITXI1 (177) /* */\r
+#define INTC_ID_SSII2 (178) /* */\r
+#define INTC_ID_SSIRTI2 (179) /* */\r
+#define INTC_ID_SSII3 (180) /* */\r
+#define INTC_ID_SSIRXI3 (181) /* */\r
+#define INTC_ID_SSITXI3 (182) /* */\r
+#define INTC_ID_SSII4 (183) /* */\r
+#define INTC_ID_SSIRTI4 (184) /* */\r
+#define INTC_ID_SSII5 (185) /* */\r
+#define INTC_ID_SSIRXI5 (186) /* */\r
+#define INTC_ID_SSITXI5 (187) /* */\r
+#define INTC_ID_SPDIFI (188)\r
+#define INTC_ID_TEI0 (189)\r
+#define INTC_ID_RI0 (190) /* */\r
+#define INTC_ID_TI0 (191) /* */\r
+#define INTC_ID_SPI0 (192) /* */\r
+#define INTC_ID_STI0 (193) /* */\r
+#define INTC_ID_NAKI0 (194) /* */\r
+#define INTC_ID_ALI0 (195) /* */\r
+#define INTC_ID_TMOI0 (196) /* */\r
+#define INTC_ID_TEI1 (197) /* */\r
+#define INTC_ID_RI1 (198) /* */\r
+#define INTC_ID_TI1 (199) /* */\r
+#define INTC_ID_SPI1 (200) /* */\r
+#define INTC_ID_STI1 (201) /* */\r
+#define INTC_ID_NAKI1 (202) /* */\r
+#define INTC_ID_ALI1 (203) /* */\r
+#define INTC_ID_TMOI1 (204) /* */\r
+#define INTC_ID_TEI2 (205) /* */\r
+#define INTC_ID_RI2 (206) /* */\r
+#define INTC_ID_TI2 (207) /* */\r
+#define INTC_ID_SPI2 (208) /* */\r
+#define INTC_ID_STI2 (209) /* */\r
+#define INTC_ID_NAKI2 (210) /* */\r
+#define INTC_ID_ALI2 (211) /* */\r
+#define INTC_ID_TMOI2 (212) /* */\r
+#define INTC_ID_TEI3 (213) /* */\r
+#define INTC_ID_RI3 (214) /* */\r
+#define INTC_ID_TI3 (215) /* */\r
+#define INTC_ID_SPI3 (216) /* */\r
+#define INTC_ID_STI3 (217) /* */\r
+#define INTC_ID_NAKI3 (218) /* */\r
+#define INTC_ID_ALI3 (219) /* */\r
+#define INTC_ID_TMOI3 (220) /* */\r
+#define INTC_ID_BRI0 (221)\r
+#define INTC_ID_ERI0 (222) /* */\r
+#define INTC_ID_RXI0 (223) /* */\r
+#define INTC_ID_TXI0 (224) /* */\r
+#define INTC_ID_BRI1 (225) /* */\r
+#define INTC_ID_ERI1 (226) /* */\r
+#define INTC_ID_RXI1 (227) /* */\r
+#define INTC_ID_TXI1 (228) /* */\r
+#define INTC_ID_BRI2 (229) /* */\r
+#define INTC_ID_ERI2 (230) /* */\r
+#define INTC_ID_RXI2 (231) /* */\r
+#define INTC_ID_TXI2 (232) /* */\r
+#define INTC_ID_BRI3 (233) /* */\r
+#define INTC_ID_ERI3 (234) /* */\r
+#define INTC_ID_RXI3 (235) /* */\r
+#define INTC_ID_TXI3 (236) /* */\r
+#define INTC_ID_BRI4 (237) /* */\r
+#define INTC_ID_ERI4 (238) /* */\r
+#define INTC_ID_RXI4 (239) /* */\r
+#define INTC_ID_TXI4 (240) /* */\r
+#define INTC_ID_BRI5 (241) /* */\r
+#define INTC_ID_ERI5 (242) /* */\r
+#define INTC_ID_RXI5 (243) /* */\r
+#define INTC_ID_TXI5 (244) /* */\r
+#define INTC_ID_BRI6 (245) /* */\r
+#define INTC_ID_ERI6 (246) /* */\r
+#define INTC_ID_RXI6 (247) /* */\r
+#define INTC_ID_TXI6 (248) /* */\r
+#define INTC_ID_BRI7 (249) /* */\r
+#define INTC_ID_ERI7 (250) /* */\r
+#define INTC_ID_RXI7 (251) /* */\r
+#define INTC_ID_TXI7 (252) /* */\r
+#define INTC_ID_GERI (253)\r
+#define INTC_ID_RFI (254) /* */\r
+#define INTC_ID_CFRXI0 (255) /* */\r
+#define INTC_ID_CERI0 (256) /* */\r
+#define INTC_ID_CTXI0 (257) /* */\r
+#define INTC_ID_CFRXI1 (258) /* */\r
+#define INTC_ID_CERI1 (259) /* */\r
+#define INTC_ID_CTXI1 (260) /* */\r
+#define INTC_ID_CFRXI2 (261) /* */\r
+#define INTC_ID_CERI2 (262) /* */\r
+#define INTC_ID_CTXI2 (263) /* */\r
+#define INTC_ID_CFRXI3 (264) /* */\r
+#define INTC_ID_CERI3 (265) /* */\r
+#define INTC_ID_CTXI3 (266) /* */\r
+#define INTC_ID_CFRXI4 (267) /* */\r
+#define INTC_ID_CERI4 (268) /* */\r
+#define INTC_ID_CTXI4 (269) /* */\r
+#define INTC_ID_SPEI0 (270)\r
+#define INTC_ID_SPRI0 (271) /* */\r
+#define INTC_ID_SPTI0 (272) /* */\r
+#define INTC_ID_SPEI1 (273) /* */\r
+#define INTC_ID_SPRI1 (274) /* */\r
+#define INTC_ID_SPTI1 (275) /* */\r
+#define INTC_ID_SPEI2 (276) /* */\r
+#define INTC_ID_SPRI2 (277) /* */\r
+#define INTC_ID_SPTI2 (278) /* */\r
+#define INTC_ID_SPEI3 (279) /* */\r
+#define INTC_ID_SPRI3 (280) /* */\r
+#define INTC_ID_SPTI3 (281) /* */\r
+#define INTC_ID_SPEI4 (282) /* */\r
+#define INTC_ID_SPRI4 (283) /* */\r
+#define INTC_ID_SPTI4 (284) /* */\r
+#define INTC_ID_IEBBTD (285)\r
+#define INTC_ID_IEBBTERR (286) /* */\r
+#define INTC_ID_IEBBTSTA (287) /* */\r
+#define INTC_ID_IEBBTV (288) /* */\r
+#define INTC_ID_ISY (289)\r
+#define INTC_ID_IERR (290) /* */\r
+#define INTC_ID_ITARG (291) /* */\r
+#define INTC_ID_ISEC (292) /* */\r
+#define INTC_ID_IBUF (293) /* */\r
+#define INTC_ID_IREADY (294) /* */\r
+#define INTC_ID_FLSTE (295)\r
+#define INTC_ID_FLTENDI (296) /* */\r
+#define INTC_ID_FLTREQ0I (297) /* */\r
+#define INTC_ID_FLTREQ1I (298) /* */\r
+#define INTC_ID_MMC0 (299)\r
+#define INTC_ID_MMC1 (300) /* */\r
+#define INTC_ID_MMC2 (301) /* */\r
+#define INTC_ID_SDHI0_3 (302)\r
+#define INTC_ID_SDHI0_0 (303) /* */\r
+#define INTC_ID_SDHI0_1 (304) /* */\r
+#define INTC_ID_SDHI1_3 (305) /* */\r
+#define INTC_ID_SDHI1_0 (306) /* */\r
+#define INTC_ID_SDHI1_1 (307) /* */\r
+#define INTC_ID_ARM (308)\r
+#define INTC_ID_PRD (309) /* */\r
+#define INTC_ID_CUP (310) /* */\r
+#define INTC_ID_SCUAI0 (311) /* SCUX */\r
+#define INTC_ID_SCUAI1 (312) /* */\r
+#define INTC_ID_SCUFDI0 (313) /* */\r
+#define INTC_ID_SCUFDI1 (314) /* */\r
+#define INTC_ID_SCUFDI2 (315) /* */\r
+#define INTC_ID_SCUFDI3 (316) /* */\r
+#define INTC_ID_SCUFUI0 (317) /* */\r
+#define INTC_ID_SCUFUI1 (318) /* */\r
+#define INTC_ID_SCUFUI2 (319) /* */\r
+#define INTC_ID_SCUFUI3 (320) /* */\r
+#define INTC_ID_SCUDVI0 (321) /* */\r
+#define INTC_ID_SCUDVI1 (322) /* */\r
+#define INTC_ID_SCUDVI2 (323) /* */\r
+#define INTC_ID_SCUDVI3 (324) /* */\r
+#define INTC_ID_MLBCI (325)\r
+#define INTC_ID_MLBSI (326) /* */\r
+#define INTC_ID_DRC0 (327)\r
+#define INTC_ID_DRC1 (328) /* */\r
+#define INTC_ID_LINI0_INT_T (331) /* Renesas LIN3 */\r
+#define INTC_ID_LINI0_INT_R (332) /* */\r
+#define INTC_ID_LINI0_INT_S (333) /* */\r
+#define INTC_ID_LINI0_INT_M (334) /* */\r
+#define INTC_ID_LINI1_INT_T (335) /* */\r
+#define INTC_ID_LINI1_INT_R (336) /* */\r
+#define INTC_ID_LINI1_INT_S (337) /* */\r
+#define INTC_ID_LINI1_INT_M (338) /* */\r
+#define INTC_ID_SCI_ERI0 (347)\r
+#define INTC_ID_SCI_RXI0 (348) /* */\r
+#define INTC_ID_SCI_TXI0 (349) /* */\r
+#define INTC_ID_SCI_TEI0 (350) /* */\r
+#define INTC_ID_SCI_ERI1 (351) /* */\r
+#define INTC_ID_SCI_RXI1 (352) /* */\r
+#define INTC_ID_SCI_TXI1 (353) /* */\r
+#define INTC_ID_SCI_TEI1 (354) /* */\r
+#define INTC_ID_ETHERI (359)\r
+#define INTC_ID_CEUI (364)\r
+#define INTC_ID_H2XMLB_ERRINT (381)\r
+#define INTC_ID_H2XIC1_ERRINT (382) /* */\r
+#define INTC_ID_X2HPERI1_ERRINT (383) /* */\r
+#define INTC_ID_X2HPERI2_ERRINT (384) /* */\r
+#define INTC_ID_X2HPERI34_ERRINT (385) /* */\r
+#define INTC_ID_X2HPERI5_ERRINT (386) /* */\r
+#define INTC_ID_X2HPERI67_ERRINT (387) /* */\r
+#define INTC_ID_X2HDBGR_ERRINT (388) /* */\r
+#define INTC_ID_X2HBSC_ERRINT (389) /* */\r
+#define INTC_ID_X2HSPI1_ERRINT (390) /* */\r
+#define INTC_ID_X2HSPI2_ERRINT (391) /* */\r
+#define INTC_ID_PRRI (392) /* */\r
+#define INTC_ID_IFEI0 (393)\r
+#define INTC_ID_OFFI0 (394) /* */\r
+#define INTC_ID_PFVEI0 (395) /* */\r
+#define INTC_ID_IFEI1 (396) /* */\r
+#define INTC_ID_OFFI1 (397) /* */\r
+#define INTC_ID_PFVEI1 (398) /* */\r
+#define INTC_ID_TINT0 (416)\r
+#define INTC_ID_TINT1 (417) /* */\r
+#define INTC_ID_TINT2 (418) /* */\r
+#define INTC_ID_TINT3 (419) /* */\r
+#define INTC_ID_TINT4 (420) /* */\r
+#define INTC_ID_TINT5 (421) /* */\r
+#define INTC_ID_TINT6 (422) /* */\r
+#define INTC_ID_TINT7 (423) /* */\r
+#define INTC_ID_TINT8 (424) /* */\r
+#define INTC_ID_TINT9 (425) /* */\r
+#define INTC_ID_TINT10 (426) /* */\r
+#define INTC_ID_TINT11 (427) /* */\r
+#define INTC_ID_TINT12 (428) /* */\r
+#define INTC_ID_TINT13 (429) /* */\r
+#define INTC_ID_TINT14 (430) /* */\r
+#define INTC_ID_TINT15 (431) /* */\r
+#define INTC_ID_TINT16 (432) /* */\r
+#define INTC_ID_TINT17 (433) /* */\r
+#define INTC_ID_TINT18 (434) /* */\r
+#define INTC_ID_TINT19 (435) /* */\r
+#define INTC_ID_TINT20 (436) /* */\r
+#define INTC_ID_TINT21 (437) /* */\r
+#define INTC_ID_TINT22 (438) /* */\r
+#define INTC_ID_TINT23 (439) /* */\r
+#define INTC_ID_TINT24 (440) /* */\r
+#define INTC_ID_TINT25 (441) /* */\r
+#define INTC_ID_TINT26 (442) /* */\r
+#define INTC_ID_TINT27 (443) /* */\r
+#define INTC_ID_TINT28 (444) /* */\r
+#define INTC_ID_TINT29 (445) /* */\r
+#define INTC_ID_TINT30 (446) /* */\r
+#define INTC_ID_TINT31 (447) /* */\r
+#define INTC_ID_TINT32 (448) /* */\r
+#define INTC_ID_TINT33 (449) /* */\r
+#define INTC_ID_TINT34 (450) /* */\r
+#define INTC_ID_TINT35 (451) /* */\r
+#define INTC_ID_TINT36 (452) /* */\r
+#define INTC_ID_TINT37 (453) /* */\r
+#define INTC_ID_TINT38 (454) /* */\r
+#define INTC_ID_TINT39 (455) /* */\r
+#define INTC_ID_TINT40 (456) /* */\r
+#define INTC_ID_TINT41 (457) /* */\r
+#define INTC_ID_TINT42 (458) /* */\r
+#define INTC_ID_TINT43 (459) /* */\r
+#define INTC_ID_TINT44 (460) /* */\r
+#define INTC_ID_TINT45 (461) /* */\r
+#define INTC_ID_TINT46 (462) /* */\r
+#define INTC_ID_TINT47 (463) /* */\r
+#define INTC_ID_TINT48 (464) /* */\r
+#define INTC_ID_TINT49 (465) /* */\r
+#define INTC_ID_TINT50 (466) /* */\r
+#define INTC_ID_TINT51 (467) /* */\r
+#define INTC_ID_TINT52 (468) /* */\r
+#define INTC_ID_TINT53 (469) /* */\r
+#define INTC_ID_TINT54 (470) /* */\r
+#define INTC_ID_TINT55 (471) /* */\r
+#define INTC_ID_TINT56 (472) /* */\r
+#define INTC_ID_TINT57 (473) /* */\r
+#define INTC_ID_TINT58 (474) /* */\r
+#define INTC_ID_TINT59 (475) /* */\r
+#define INTC_ID_TINT60 (476) /* */\r
+#define INTC_ID_TINT61 (477) /* */\r
+#define INTC_ID_TINT62 (478) /* */\r
+#define INTC_ID_TINT63 (479) /* */\r
+#define INTC_ID_TINT64 (480) /* */\r
+#define INTC_ID_TINT65 (481) /* */\r
+#define INTC_ID_TINT66 (482) /* */\r
+#define INTC_ID_TINT67 (483) /* */\r
+#define INTC_ID_TINT68 (484) /* */\r
+#define INTC_ID_TINT69 (485) /* */\r
+#define INTC_ID_TINT70 (486) /* */\r
+#define INTC_ID_TINT71 (487) /* */\r
+#define INTC_ID_TINT72 (488) /* */\r
+#define INTC_ID_TINT73 (489) /* */\r
+#define INTC_ID_TINT74 (490) /* */\r
+#define INTC_ID_TINT75 (491) /* */\r
+#define INTC_ID_TINT76 (492) /* */\r
+#define INTC_ID_TINT77 (493) /* */\r
+#define INTC_ID_TINT78 (494) /* */\r
+#define INTC_ID_TINT79 (495) /* */\r
+#define INTC_ID_TINT80 (496) /* */\r
+#define INTC_ID_TINT81 (497) /* */\r
+#define INTC_ID_TINT82 (498) /* */\r
+#define INTC_ID_TINT83 (499) /* */\r
+#define INTC_ID_TINT84 (500) /* */\r
+#define INTC_ID_TINT85 (501) /* */\r
+#define INTC_ID_TINT86 (502) /* */\r
+#define INTC_ID_TINT87 (503) /* */\r
+#define INTC_ID_TINT88 (504) /* */\r
+#define INTC_ID_TINT89 (505) /* */\r
+#define INTC_ID_TINT90 (506) /* */\r
+#define INTC_ID_TINT91 (507) /* */\r
+#define INTC_ID_TINT92 (508) /* */\r
+#define INTC_ID_TINT93 (509) /* */\r
+#define INTC_ID_TINT94 (510) /* */\r
+#define INTC_ID_TINT95 (511) /* */\r
+#define INTC_ID_TINT96 (512) /* */\r
+#define INTC_ID_TINT97 (513) /* */\r
+#define INTC_ID_TINT98 (514) /* */\r
+#define INTC_ID_TINT99 (515) /* */\r
+#define INTC_ID_TINT100 (516) /* */\r
+#define INTC_ID_TINT101 (517) /* */\r
+#define INTC_ID_TINT102 (518) /* */\r
+#define INTC_ID_TINT103 (519) /* */\r
+#define INTC_ID_TINT104 (520) /* */\r
+#define INTC_ID_TINT105 (521) /* */\r
+#define INTC_ID_TINT106 (522) /* */\r
+#define INTC_ID_TINT107 (523) /* */\r
+#define INTC_ID_TINT108 (524) /* */\r
+#define INTC_ID_TINT109 (525) /* */\r
+#define INTC_ID_TINT110 (526) /* */\r
+#define INTC_ID_TINT111 (527) /* */\r
+#define INTC_ID_TINT112 (528) /* */\r
+#define INTC_ID_TINT113 (529) /* */\r
+#define INTC_ID_TINT114 (530) /* */\r
+#define INTC_ID_TINT115 (531) /* */\r
+#define INTC_ID_TINT116 (532) /* */\r
+#define INTC_ID_TINT117 (533) /* */\r
+#define INTC_ID_TINT118 (534) /* */\r
+#define INTC_ID_TINT119 (535) /* */\r
+#define INTC_ID_TINT120 (536) /* */\r
+#define INTC_ID_TINT121 (537) /* */\r
+#define INTC_ID_TINT122 (538) /* */\r
+#define INTC_ID_TINT123 (539) /* */\r
+#define INTC_ID_TINT124 (540) /* */\r
+#define INTC_ID_TINT125 (541) /* */\r
+#define INTC_ID_TINT126 (542) /* */\r
+#define INTC_ID_TINT127 (543) /* */\r
+#define INTC_ID_TINT128 (544) /* */\r
+#define INTC_ID_TINT129 (545) /* */\r
+#define INTC_ID_TINT130 (546) /* */\r
+#define INTC_ID_TINT131 (547) /* */\r
+#define INTC_ID_TINT132 (548) /* */\r
+#define INTC_ID_TINT133 (549) /* */\r
+#define INTC_ID_TINT134 (550) /* */\r
+#define INTC_ID_TINT135 (551) /* */\r
+#define INTC_ID_TINT136 (552) /* */\r
+#define INTC_ID_TINT137 (553) /* */\r
+#define INTC_ID_TINT138 (554) /* */\r
+#define INTC_ID_TINT139 (555) /* */\r
+#define INTC_ID_TINT140 (556) /* */\r
+#define INTC_ID_TINT141 (557) /* */\r
+#define INTC_ID_TINT142 (558) /* */\r
+#define INTC_ID_TINT143 (559) /* */\r
+#define INTC_ID_TINT144 (560) /* */\r
+#define INTC_ID_TINT145 (561) /* */\r
+#define INTC_ID_TINT146 (562) /* */\r
+#define INTC_ID_TINT147 (563) /* */\r
+#define INTC_ID_TINT148 (564) /* */\r
+#define INTC_ID_TINT149 (565) /* */\r
+#define INTC_ID_TINT150 (566) /* */\r
+#define INTC_ID_TINT151 (567) /* */\r
+#define INTC_ID_TINT152 (568) /* */\r
+#define INTC_ID_TINT153 (569) /* */\r
+#define INTC_ID_TINT154 (570) /* */\r
+#define INTC_ID_TINT155 (571) /* */\r
+#define INTC_ID_TINT156 (572) /* */\r
+#define INTC_ID_TINT157 (573) /* */\r
+#define INTC_ID_TINT158 (574) /* */\r
+#define INTC_ID_TINT159 (575) /* */\r
+#define INTC_ID_TINT160 (576) /* */\r
+#define INTC_ID_TINT161 (577) /* */\r
+#define INTC_ID_TINT162 (578) /* */\r
+#define INTC_ID_TINT163 (579) /* */\r
+#define INTC_ID_TINT164 (580) /* */\r
+#define INTC_ID_TINT165 (581) /* */\r
+#define INTC_ID_TINT166 (582) /* */\r
+#define INTC_ID_TINT167 (583) /* */\r
+#define INTC_ID_TINT168 (584) /* */\r
+#define INTC_ID_TINT169 (585) /* */\r
+#define INTC_ID_TINT170 (586) /* */\r
+\r
+#define INTC_LEVEL_SENSITIVE (0)\r
+#define INTC_EDGE_TRIGGER (1)\r
+\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+int32_t R_INTC_RegistIntFunc(uint16_t int_id, void (* func)(uint32_t int_sense));\r
+void R_INTC_Init(void);\r
+int32_t R_INTC_Enable(uint16_t int_id);\r
+int32_t R_INTC_Disable(uint16_t int_id);\r
+int32_t R_INTC_SetPriority(uint16_t int_id, uint8_t priority);\r
+int32_t R_INTC_SetMaskLevel(uint8_t mask_level);\r
+void R_INTC_GetMaskLevel(uint8_t * mask_level);\r
+\r
+void Userdef_INTC_RegistIntFunc(uint16_t int_id, void (* func)(uint32_t int_sense));\r
+void Userdef_INTC_UndefId(uint16_t int_id);\r
+void Userdef_INTC_HandlerExe(uint16_t int_id, uint32_t int_sense);\r
+void Userdef_FIQ_HandlerExe(void);\r
+\r
+#endif /* _DEVDRV_INTC_H_ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/******************************************************************************\r
+* File Name : devdrv_ostm.h\r
+* $Rev: $\r
+* $Date:: $\r
+* Description : Aragon Sample Program - OS timer device driver header\r
+******************************************************************************/\r
+#ifndef _DEVDRV_OSTM_H_\r
+#define _DEVDRV_OSTM_H_\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "iodefine.h"\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+#define OSTM_MODE_INTERVAL (0)\r
+#define OSTM_MODE_COMPARE (1)\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+int32_t R_OSTM_Init(uint32_t channel, uint32_t mode, uint32_t cycle);\r
+int32_t R_OSTM_Open(uint32_t channel);\r
+int32_t R_OSTM_Close(uint32_t channel, uint32_t * count);\r
+int32_t R_OSTM_Interrupt(uint32_t channel);\r
+\r
+int32_t Userdef_OSTM0_Init(uint32_t mode, uint32_t cycle);\r
+int32_t Userdef_OSTM1_Init(uint32_t mode, uint32_t cycle);\r
+void Userdef_OSTM0_Int(void);\r
+void Userdef_OSTM1_Int(void);\r
+void Userdef_OSTM0_WaitInt(void);\r
+void Userdef_OSTM1_WaitInt(void);\r
+\r
+#endif /* _DEVDRV_OSTM_H_ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/******************************************************************************\r
+* File Name : scif_uart.h\r
+* $Rev: $\r
+* $Date:: $\r
+* Description : Aragon Sample Program - SCIF UART device driver header\r
+******************************************************************************/\r
+#ifndef _DEVDRV_SCIF_UART_H_\r
+#define _DEVDRV_SCIF_UART_H_\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "iodefine.h"\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+#define SCIF_UART_MODE_W (1)\r
+#define SCIF_UART_MODE_R (2)\r
+#define SCIF_UART_MODE_RW (3)\r
+\r
+typedef enum scif_cks_division\r
+{\r
+ SCIF_CKS_DIVISION_1,\r
+ SCIF_CKS_DIVISION_4,\r
+ SCIF_CKS_DIVISION_16,\r
+ SCIF_CKS_DIVISION_64\r
+} scif_cks_division_t;\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+int32_t R_SCIF_UART_Init(uint32_t channel, uint32_t mode, uint16_t cks, uint8_t scbrr);\r
+\r
+void Userdef_SCIF2_UART_Init(uint8_t mode, uint16_t cks, uint8_t scbrr);\r
+\r
+#endif /* _DEVDRV_SCIF_UART_H_ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+*\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized.\r
+*\r
+* This software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+*\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES\r
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,\r
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A\r
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY\r
+* DISCLAIMED.\r
+*\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES\r
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS\r
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+*\r
+* Renesas reserves the right, without notice, to make changes to this\r
+* software and to discontinue the availability of this software.\r
+* By using this software, you agree to the additional terms and\r
+* conditions found by accessing the following link:\r
+* http://www.renesas.com/disclaimer\r
+********************************************************************************\r
+* Copyright (C) 2010(2011) Renesas Electronics Corporation. All rights reserved.\r
+**************************** Technical reference data **************************\r
+* System Name : SH7269 Sample Program\r
+* File Name : iodefine.h\r
+* Abstract : SH7269 IO define file\r
+* Version : 0.11.00\r
+* Device : SH7269\r
+\r
+* Tool-Chain : High-performance Embedded Workshop (Ver.4.07.00).\r
+* : C/C++ compiler package for the SuperH RISC engine family\r
+* : (Ver.9.03 Release02).\r
+* OS : None\r
+* H/W Platform: R0K57269(CPU board)\r
+* Description :\r
+********************************************************************************\r
+* History : Sep.02,2010 Ver.0.01.00 Preliminary version issued\r
+* : Oct.06.2010 Ver.0.02.00 VDC4.GR1_AB1 modified\r
+* : Oct.07.2010 Ver.0.03.00 VDC4.GR1_AB1 type definition modified\r
+* : Oct.19.2010 Ver.0.04.00 MMC.CE_DMA_MODE added\r
+* MMC.CE_BOOT deleted\r
+* : Nov.09.2010 Ver.0.05.00 VDC4.GR3_CLUT_INT.GR3_LINE added\r
+* : Jan.28.2011 Ver.0.06.00 DVDEC.ADDCR->ADCCR1 changed\r
+* DVDEC.ADCCR1.AGCMODEXA->AGCMODE changed\r
+* DVDEC.INSCR deleted\r
+* DVDEC.AGCCR2.AGCMAXGAIN deleted\r
+* DVDEC.AGCCR2.VIDEOGAIN deleted\r
+* DVDEC.AGCCR2.VIDEOGAIN deleted\r
+* DVDEC.CROMASR2.NCOMODE deleted\r
+* DVDEC.DCPSR3~5 deleted\r
+* DVDEC.YCSCR1 deleted\r
+* DVDEC.YCSCR3~7,9,11 added\r
+* DVDEC.YCSCR8.HFIL_TAP_SEL added\r
+* DVDEC.YCSCR12.DET2_MIX_C added\r
+* DVDEC.YCSCR12.DET2_MIX_Y added\r
+* DVDEC.DCPCR9.CLP_FIL_SEL deleted\r
+* DVDEC.DCPCR10~13 deleted\r
+* DVDEC.PGA_UPDATE added\r
+* DVDEC.PGACR added\r
+* DVDEC.ADCCR2 added\r
+* module SPIBSC added\r
+* : Feb.23.2011 Ver.0.07.00 CPG.STBCR7.MSTP75 added\r
+* : Feb.28.2011 Ver.0.08.00 PORT.PBCR5 modified\r
+* PORT.PBCR4 modified\r
+* PORT.PBCR3 modified\r
+* JCU.JCSTS deleted\r
+* VDC4.INP_SEL_CNT.INP_VSP_SYNC_SEL deleted\r
+* VDC4.SCL0_DS4.RES_DS_H_INIPHASE deleted\r
+* VDC4.GR1_AB1.GR1_ARC_ON deleted\r
+* VDC4.GR1_AB1.GR1_ARC_DISP_ON deleted\r
+* VDC4.GR1_AB4 deleted\r
+* VDC4.GR1_AB5 deleted\r
+* VDC4.GR1_AB6 deleted\r
+* VDC4.GR1_AB7.GR1_ARC_DEF deleted\r
+* VDC4.GR1_MON deleted\r
+* VDC4.ADJ_MTX_MODE.MTX_MD->ADJ_MTX_MD changed\r
+* VDC4.OUT_SET.OUT_PIXEL_INV_ON deleted\r
+* VDC4.OUT_SET.OUT_SUM_MOVE deleted\r
+* : Mar.02.2011 Ver.0.09.00 JCU.JCQTBL0 modified\r
+* JCU.JCQTBL1 modified\r
+* JCU.JCQTBL2 modified\r
+* JCU.JCQTBL3 modified\r
+* JCU.JCHTBD0 modified\r
+* JCU.JCHTBA0 modified\r
+* JCU.JCHTBD1 modified\r
+* JCU.JCHTBA1 modified\r
+* : Apr.04.2011 Ver.0.10.00 CPG.SWRSTCR2.JCUSRST added\r
+* : May.09.2011 Ver.0.11.00 BSC.ACSWR deleted\r
+* BSC.ACKEYR deleted\r
+* USB.USBACSWR1 deleted\r
+*******************************************************************************/\r
+#ifndef _IODEFINE_H_\r
+#define _IODEFINE_H_\r
+\r
+#include "typedefine.h"\r
+\r
+/* new iodefine ADC */\r
+\r
+struct st_adc\r
+{ /* ADC */\r
+ unsigned short DRA; /* DRA */\r
+ unsigned short DRB; /* DRB */\r
+ unsigned short DRC; /* DRC */\r
+ unsigned short DRD; /* DRD */\r
+ unsigned short DRE; /* DRE */\r
+ unsigned short DRF; /* DRF */\r
+ unsigned short DRG; /* DRG */\r
+ unsigned short DRH; /* DRH */\r
+ unsigned char dummy32[16]; /* */\r
+ unsigned short MPHA; /* MPHA */\r
+ unsigned short MPLA; /* MPLA */\r
+ unsigned short MPHB; /* MPHB */\r
+ unsigned short MPLB; /* MPLB */\r
+ unsigned short MPHC; /* MPHC */\r
+ unsigned short MPLC; /* MPLC */\r
+ unsigned short MPHD; /* MPHD */\r
+ unsigned short MPLD; /* MPLD */\r
+ unsigned short MPHE; /* MPHE */\r
+ unsigned short MPLE; /* MPLE */\r
+ unsigned short MPHF; /* MPHF */\r
+ unsigned short MPLF; /* MPLF */\r
+ unsigned short MPHG; /* MPHG */\r
+ unsigned short MPLG; /* MPLG */\r
+ unsigned short MPHH; /* MPHH */\r
+ unsigned short MPLH; /* MPLH */\r
+ unsigned char dummy33[32]; /* */\r
+ unsigned short SR; /* SR */\r
+ unsigned short MPER; /* MPER */\r
+ unsigned short MPSR; /* MPSR */\r
+};\r
+\r
+#define ADCDRA ADC.DRA\r
+#define ADCDRB ADC.DRB\r
+#define ADCDRC ADC.DRC\r
+#define ADCDRD ADC.DRD\r
+#define ADCDRE ADC.DRE\r
+#define ADCDRF ADC.DRF\r
+#define ADCDRG ADC.DRG\r
+#define ADCDRH ADC.DRH\r
+#define ADCMPHA ADC.MPHA\r
+#define ADCMPLA ADC.MPLA\r
+#define ADCMPHB ADC.MPHB\r
+#define ADCMPLB ADC.MPLB\r
+#define ADCMPHC ADC.MPHC\r
+#define ADCMPLC ADC.MPLC\r
+#define ADCMPHD ADC.MPHD\r
+#define ADCMPLD ADC.MPLD\r
+#define ADCMPHE ADC.MPHE\r
+#define ADCMPLE ADC.MPLE\r
+#define ADCMPHF ADC.MPHF\r
+#define ADCMPLF ADC.MPLF\r
+#define ADCMPHG ADC.MPHG\r
+#define ADCMPLG ADC.MPLG\r
+#define ADCMPHH ADC.MPHH\r
+#define ADCMPLH ADC.MPLH\r
+#define ADCSR ADC.SR\r
+#define ADCMPER ADC.MPER\r
+#define ADCMPSR ADC.MPSR\r
+\r
+#define ADC (*(volatile struct st_adc *)0xE8005800) /* ADC */\r
+\r
+/* new iodefine ADC */\r
+\r
+\r
+ #if 0\r
+struct st_cpg { /* struct CPG */\r
+ union { /* FRQCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD CKOEN2:1; /* CKOEN2 */\r
+ _UWORD CKOEN:2; /* CKOEN */\r
+ _UWORD :2; /* */\r
+ _UWORD IFC:2; /* IFC */\r
+ _UWORD :2; /* */\r
+ _UWORD BFC:2; /* BFC */\r
+ _UWORD :4; /* */\r
+ } BIT; /* */\r
+ } FRQCR; /* */\r
+ _UBYTE wk0[2]; /* */\r
+ union { /* STBCR1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE STBY:1; /* STBY */\r
+ _UBYTE DEEP:1; /* DEEP */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } STBCR1; /* */\r
+ _UBYTE wk1[3]; /* */\r
+ union { /* STBCR2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP10:1; /* MSTP10 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE MSTP8:1; /* MSTP8 */\r
+ _UBYTE MSTP7:1; /* MSTP7 */\r
+ _UBYTE :4; /* */\r
+ } BIT; /* */\r
+ } STBCR2; /* */\r
+ _UBYTE wk2[999]; /* */\r
+ union { /* SYSCR1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE RAME3:1; /* RAME3 */\r
+ _UBYTE RAME2:1; /* RAME2 */\r
+ _UBYTE RAME1:1; /* RAME1 */\r
+ _UBYTE RAME0:1; /* RAME0 */\r
+ } BIT; /* */\r
+ } SYSCR1; /* */\r
+ _UBYTE wk3[3]; /* */\r
+ union { /* SYSCR2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE RAMWE3:1; /* RAMWE3 */\r
+ _UBYTE RAMWE2:1; /* RAMWE2 */\r
+ _UBYTE RAMWE1:1; /* RAMWE1 */\r
+ _UBYTE RAMWE0:1; /* RAMWE0 */\r
+ } BIT; /* */\r
+ } SYSCR2; /* */\r
+ _UBYTE wk4[3]; /* */\r
+ union { /* STBCR3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE HIZ:1; /* HIZ */\r
+ _UBYTE MSTP36:1; /* MSTP36 */\r
+ _UBYTE MSTP35:1; /* MSTP35 */\r
+ _UBYTE :1; /* MSTP34 */\r
+ _UBYTE :1; /* MSTP33 */\r
+ _UBYTE MSTP32:1; /* MSTP32 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE MSTP30:1; /* MSTP30 */\r
+ } BIT; /* */\r
+ } STBCR3; /* */\r
+ _UBYTE wk5[3]; /* */\r
+ union { /* STBCR4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP47:1; /* MSTP47 */\r
+ _UBYTE MSTP46:1; /* MSTP46 */\r
+ _UBYTE MSTP45:1; /* MSTP45 */\r
+ _UBYTE MSTP44:1; /* MSTP44 */\r
+ _UBYTE MSTP43:1; /* MSTP43 */\r
+ _UBYTE MSTP42:1; /* MSTP42 */\r
+ _UBYTE MSTP41:1; /* MSTP41 */\r
+ _UBYTE MSTP40:1; /* MSTP40 */\r
+ } BIT; /* */\r
+ } STBCR4; /* */\r
+ _UBYTE wk6[3]; /* */\r
+ union { /* STBCR5 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP57:1; /* MSTP57 */\r
+ _UBYTE MSTP56:1; /* MSTP56 */\r
+ _UBYTE MSTP55:1; /* MSTP55 */\r
+ _UBYTE MSTP54:1; /* MSTP54 */\r
+ _UBYTE MSTP53:1; /* MSTP53 */\r
+ _UBYTE MSTP52:1; /* MSTP52 */\r
+ _UBYTE MSTP51:1; /* MSTP51 */\r
+ _UBYTE MSTP50:1; /* MSTP50 */\r
+ } BIT; /* */\r
+ } STBCR5; /* */\r
+ _UBYTE wk7[3]; /* */\r
+ union { /* STBCR6 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP67:1; /* MSTP67 */\r
+ _UBYTE MSTP66:1; /* MSTP66 */\r
+ _UBYTE MSTP65:1; /* MSTP65 */\r
+ _UBYTE MSTP64:1; /* MSTP64 */\r
+ _UBYTE MSTP63:1; /* MSTP63 */\r
+ _UBYTE MSTP62:1; /* MSTP62 */\r
+ _UBYTE MSTP61:1; /* MSTP61 */\r
+ _UBYTE MSTP60:1; /* MSTP60 */\r
+ } BIT; /* */\r
+ } STBCR6; /* */\r
+ _UBYTE wk8[3]; /* */\r
+ union { /* STBCR7 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP77:1; /* MSTP77 */\r
+ _UBYTE MSTP76:1; /* MSTP76 */\r
+ _UBYTE MSTP75:1; /* MSTP75 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE MSTP73:1; /* MSTP73 */\r
+ _UBYTE MSTP72:1; /* MSTP72 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE MSTP70:1; /* MSTP70 */\r
+ } BIT; /* */\r
+ } STBCR7; /* */\r
+ _UBYTE wk9[3]; /* */\r
+ union { /* STBCR8 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP87:1; /* MSTP87 */\r
+ _UBYTE MSTP86:1; /* MSTP86 */\r
+ _UBYTE MSTP85:1; /* MSTP85 */\r
+ _UBYTE MSTP84:1; /* MSTP84 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE MSTP82:1; /* MSTP82 */\r
+ _UBYTE MSTP81:1; /* MSTP81 */\r
+ _UBYTE :1; /* */\r
+ } BIT; /* */\r
+ } STBCR8; /* */\r
+ _UBYTE wk10[3]; /* */\r
+ union { /* SYSCR3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE VRAME5:1; /* VRAME5 */\r
+ _UBYTE VRAME4:1; /* VRAME4 */\r
+ _UBYTE VRAME3:1; /* VRAME3 */\r
+ _UBYTE VRAME2:1; /* VRAME2 */\r
+ _UBYTE VRAME1:1; /* VRAME1 */\r
+ _UBYTE VRAME0:1; /* VRAME0 */\r
+ } BIT; /* */\r
+ } SYSCR3; /* */\r
+ _UBYTE wk11[3]; /* */\r
+ union { /* SYSCR4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE VRAMWE5:1; /* VRAMWE5 */\r
+ _UBYTE VRAMWE4:1; /* VRAMWE4 */\r
+ _UBYTE VRAMWE3:1; /* VRAMWE3 */\r
+ _UBYTE VRAMWE2:1; /* VRAMWE2 */\r
+ _UBYTE VRAMWE1:1; /* VRAMWE1 */\r
+ _UBYTE VRAMWE0:1; /* VRAMWE0 */\r
+ } BIT; /* */\r
+ } SYSCR4; /* */\r
+ _UBYTE wk12[3]; /* */\r
+ union { /* SYSCR5 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE RRAMWE3:1; /* RRAMWE3 */\r
+ _UBYTE RRAMWE2:1; /* RRAMWE2 */\r
+ _UBYTE RRAMWE1:1; /* RRAMWE1 */\r
+ _UBYTE RRAMWE0:1; /* RRAMWE0 */\r
+ } BIT; /* */\r
+ } SYSCR5; /* */\r
+ _UBYTE wk13[7]; /* */\r
+ union { /* SWRSTCR1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE AXTALE:1; /* AXTALE */\r
+ _UBYTE SSIF5SRST:1; /* SSIF5SRST */\r
+ _UBYTE SSIF4SRST:1; /* SSIF4SRST */\r
+ _UBYTE IEBSRST:1; /* IEBSRST */\r
+ _UBYTE SSIF3SRST:1; /* SSIF3SRST */\r
+ _UBYTE SSIF2SRST:1; /* SSIF2SRST */\r
+ _UBYTE SSIF1SRST:1; /* SSIF1SRST */\r
+ _UBYTE SSIF0SRST:1; /* SSIF0SRST */\r
+ } BIT; /* */\r
+ } SWRSTCR1; /* */\r
+ _UBYTE wk14[3]; /* */\r
+ union { /* SWRSTCR2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :3; /* */\r
+ _UBYTE JCUSRST:1; /* JCUSRST */\r
+ _UBYTE RGPVGSRST:1; /* SSIF3SRST */\r
+ _UBYTE :3; /* */\r
+ } BIT; /* */\r
+ } SWRSTCR2; /* */\r
+ _UBYTE wk15[11]; /* */\r
+ union { /* STBCR9 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP97:1; /* MSTP97 */\r
+ _UBYTE MSTP96:1; /* MSTP96 */\r
+ _UBYTE MSTP95:1; /* MSTP95 */\r
+ _UBYTE MSTP94:1; /* MSTP94 */\r
+ _UBYTE MSTP93:1; /* MSTP93 */\r
+ _UBYTE MSTP92:1; /* MSTP92 */\r
+ _UBYTE MSTP91:1; /* MSTP91 */\r
+ _UBYTE MSTP90:1; /* MSTP90 */\r
+ } BIT; /* */\r
+ } STBCR9; /* */\r
+ _UBYTE wk16[3]; /* */\r
+ union { /* STBCR10 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP107:1; /* MSTP107 */\r
+ _UBYTE MSTP106:1; /* MSTP106 */\r
+ _UBYTE MSTP105:1; /* MSTP105 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE MSTP103:1; /* MSTP103 */\r
+ _UBYTE MSTP102:1; /* MSTP102 */\r
+ _UBYTE MSTP101:1; /* MSTP101 */\r
+ _UBYTE MSTP100:1; /* MSTP100 */\r
+ } BIT; /* */\r
+ } STBCR10; /* */\r
+ _UBYTE wk17[25531]; /* */\r
+ union { /* RRAMKP */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE RRAMKP3:1; /* RRAMKP3 */\r
+ _UBYTE RRAMKP2:1; /* RRAMKP2 */\r
+ _UBYTE RRAMKP1:1; /* RRAMKP1 */\r
+ _UBYTE RRAMKP0:1; /* RRAMKP0 */\r
+ } BIT; /* */\r
+ } RRAMKP; /* */\r
+ _UBYTE wk18[1]; /* */\r
+ union { /* DSCTR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE EBUSKEEPE:1; /* EBUSKEEPE */\r
+ _UBYTE RAMBOOT:1; /* RAMBOOT */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } DSCTR; /* */\r
+ _UBYTE wk19[1]; /* */\r
+ union { /* DSSSR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD PJ23:1; /* PJ23 */\r
+ _UWORD PJ22:1; /* PJ22 */\r
+ _UWORD PJ21:1; /* PJ21 */\r
+ _UWORD PJ20:1; /* PJ20 */\r
+ _UWORD PG3:1; /* PG3 */\r
+ _UWORD PG2:1; /* PG2 */\r
+ _UWORD NMI:1; /* NMI */\r
+ _UWORD :1; /* */\r
+ _UWORD RTCAR:1; /* RTCAR */\r
+ _UWORD PF19:1; /* PF19 */\r
+ _UWORD PF18:1; /* PF18 */\r
+ _UWORD PF17:1; /* PF17 */\r
+ _UWORD PF16:1; /* PF16 */\r
+ _UWORD PC7:1; /* PC7 */\r
+ _UWORD PC5:1; /* PC5 */\r
+ } BIT; /* */\r
+ } DSSSR; /* */\r
+ union { /* DSESR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD PJ23E:1; /* PJ23E */\r
+ _UWORD PJ22E:1; /* PJ22E */\r
+ _UWORD PJ21E:1; /* PJ21E */\r
+ _UWORD PJ20E:1; /* PJ20E */\r
+ _UWORD PG3E:1; /* PG3E */\r
+ _UWORD PG2E:1; /* PG2E */\r
+ _UWORD NMIE:1; /* NMIE */\r
+ _UWORD :1; /* */\r
+ _UWORD :1; /* */\r
+ _UWORD PF19E:1; /* PF19E */\r
+ _UWORD PF18E:1; /* PF18E */\r
+ _UWORD PF17E:1; /* PF17E */\r
+ _UWORD PF16E:1; /* PF16E */\r
+ _UWORD PC7E:1; /* PC7E */\r
+ _UWORD PC5E:1; /* PC5E */\r
+ } BIT; /* */\r
+ } DSESR; /* */\r
+ union { /* DSFR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD IOKEEP:1; /* IOKEEP */\r
+ _UWORD PJ23F:1; /* PJ23F */\r
+ _UWORD PJ22F:1; /* PJ22F */\r
+ _UWORD PJ21F:1; /* PJ21F */\r
+ _UWORD PJ20F:1; /* PJ20F */\r
+ _UWORD PG3F:1; /* PG3F */\r
+ _UWORD PG2F:1; /* PG2F */\r
+ _UWORD NMIF:1; /* NMIF */\r
+ _UWORD :1; /* */\r
+ _UWORD RTCARF:1; /* RTCARF */\r
+ _UWORD PF19F:1; /* PF19F */\r
+ _UWORD PF18F:1; /* PF18F */\r
+ _UWORD PF17F:1; /* PF17F */\r
+ _UWORD PF16F:1; /* PF16F */\r
+ _UWORD PC7F:1; /* PC7F */\r
+ _UWORD PC5F:1; /* PC5F */\r
+ } BIT; /* */\r
+ } DSFR; /* */\r
+ _UBYTE wk20[6]; /* */\r
+ union { /* XTALCTR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :7; /* */\r
+ _UBYTE GAIN:1; /* GAIN */\r
+ } BIT; /* */\r
+ } XTALCTR; /* */\r
+}; /* */\r
+struct st_intc { /* struct INTC */\r
+ union { /* ICR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD NMIL:1; /* NMIL */\r
+ _UWORD :6; /* */\r
+ _UWORD NMIE:1; /* NMIE */\r
+ _UWORD :6; /* */\r
+ _UWORD NMIF:1; /* NMIF */\r
+ _UWORD NMIM:1; /* NMIM */\r
+ } BIT; /* */\r
+ } ICR0; /* */\r
+ union { /* ICR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD IRQ71S:1; /* IRQ71S */\r
+ _UWORD IRQ70S:1; /* IRQ70S */\r
+ _UWORD IRQ61S:1; /* IRQ61S */\r
+ _UWORD IRQ60S:1; /* IRQ60S */\r
+ _UWORD IRQ51S:1; /* IRQ51S */\r
+ _UWORD IRQ50S:1; /* IRQ50S */\r
+ _UWORD IRQ41S:1; /* IRQ41S */\r
+ _UWORD IRQ40S:1; /* IRQ40S */\r
+ _UWORD IRQ31S:1; /* IRQ31S */\r
+ _UWORD IRQ30S:1; /* IRQ30S */\r
+ _UWORD IRQ21S:1; /* IRQ21S */\r
+ _UWORD IRQ20S:1; /* IRQ20S */\r
+ _UWORD IRQ11S:1; /* IRQ11S */\r
+ _UWORD IRQ10S:1; /* IRQ10S */\r
+ _UWORD IRQ01S:1; /* IRQ01S */\r
+ _UWORD IRQ00S:1; /* IRQ00S */\r
+ } BIT; /* */\r
+ } ICR1; /* */\r
+ union { /* ICR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD PINT7S:1; /* PINT7S */\r
+ _UWORD PINT6S:1; /* PINT6S */\r
+ _UWORD PINT5S:1; /* PINT5S */\r
+ _UWORD PINT4S:1; /* PINT4S */\r
+ _UWORD PINT3S:1; /* PINT3S */\r
+ _UWORD PINT2S:1; /* PINT2S */\r
+ _UWORD PINT1S:1; /* PINT1S */\r
+ _UWORD PINT0S:1; /* PINT0S */\r
+ } BIT; /* */\r
+ } ICR2; /* */\r
+ union { /* IRQRR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD IRQ7F:1; /* IRQ7F */\r
+ _UWORD IRQ6F:1; /* IRQ6F */\r
+ _UWORD IRQ5F:1; /* IRQ5F */\r
+ _UWORD IRQ4F:1; /* IRQ4F */\r
+ _UWORD IRQ3F:1; /* IRQ3F */\r
+ _UWORD IRQ2F:1; /* IRQ2F */\r
+ _UWORD IRQ1F:1; /* IRQ1F */\r
+ _UWORD IRQ0F:1; /* IRQ0F */\r
+ } BIT; /* */\r
+ } IRQRR; /* */\r
+ union { /* PINTER */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD PINT7E:1; /* PINT7E */\r
+ _UWORD PINT6E:1; /* PINT6E */\r
+ _UWORD PINT5E:1; /* PINT5E */\r
+ _UWORD PINT4E:1; /* PINT4E */\r
+ _UWORD PINT3E:1; /* PINT3E */\r
+ _UWORD PINT2E:1; /* PINT2E */\r
+ _UWORD PINT1E:1; /* PINT1E */\r
+ _UWORD PINT0E:1; /* PINT0E */\r
+ } BIT; /* */\r
+ } PINTER; /* */\r
+ union { /* PIRR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD PINT7R:1; /* PINT7R */\r
+ _UWORD PINT6R:1; /* PINT6R */\r
+ _UWORD PINT5R:1; /* PINT5R */\r
+ _UWORD PINT4R:1; /* PINT4R */\r
+ _UWORD PINT3R:1; /* PINT3R */\r
+ _UWORD PINT2R:1; /* PINT2R */\r
+ _UWORD PINT1R:1; /* PINT1R */\r
+ _UWORD PINT0R:1; /* PINT0R */\r
+ } BIT; /* */\r
+ } PIRR; /* */\r
+ union { /* IBCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD E15:1; /* E15 */\r
+ _UWORD E14:1; /* E14 */\r
+ _UWORD E13:1; /* E13 */\r
+ _UWORD E12:1; /* E12 */\r
+ _UWORD E11:1; /* E11 */\r
+ _UWORD E10:1; /* E10 */\r
+ _UWORD E9:1; /* E9 */\r
+ _UWORD E8:1; /* E8 */\r
+ _UWORD E7:1; /* E7 */\r
+ _UWORD E6:1; /* E6 */\r
+ _UWORD E5:1; /* E5 */\r
+ _UWORD E4:1; /* E4 */\r
+ _UWORD E3:1; /* E3 */\r
+ _UWORD E2:1; /* E2 */\r
+ _UWORD E1:1; /* E1 */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } IBCR; /* */\r
+ union { /* IBNR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BE:2; /* BE */\r
+ _UWORD BOVE:1; /* BOVE */\r
+ _UWORD :9; /* */\r
+ _UWORD BN:4; /* BN */\r
+ } BIT; /* */\r
+ } IBNR; /* */\r
+ _UBYTE wk0[8]; /* */\r
+ union { /* IPR01 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _IRQ0:4; /* _IRQ0 */\r
+ _UWORD _IRQ1:4; /* _IRQ1 */\r
+ _UWORD _IRQ2:4; /* _IRQ2 */\r
+ _UWORD _IRQ3:4; /* _IRQ3 */\r
+ } BIT; /* */\r
+ } IPR01; /* */\r
+ union { /* IPR02 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _IRQ4:4; /* _IRQ4 */\r
+ _UWORD _IRQ5:4; /* _IRQ5 */\r
+ _UWORD _IRQ6:4; /* _IRQ6 */\r
+ _UWORD _IRQ7:4; /* _IRQ7 */\r
+ } BIT; /* */\r
+ } IPR02; /* */\r
+ _UBYTE wk1[4]; /* */\r
+ union { /* IPR05 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _PINT:4; /* PINT7-0 */\r
+ _UWORD :12; /* */\r
+ } BIT; /* */\r
+ } IPR05; /* */\r
+ _UBYTE wk2[990]; /* */\r
+ union { /* IPR06 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _DMAC0:4; /* _DMAC0 */\r
+ _UWORD _DMAC1:4; /* _DMAC1 */\r
+ _UWORD _DMAC2:4; /* _DMAC2 */\r
+ _UWORD _DMAC3:4; /* _DMAC3 */\r
+ } BIT; /* */\r
+ } IPR06; /* */\r
+ union { /* IPR07 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _DMAC4:4; /* _DMAC4 */\r
+ _UWORD _DMAC5:4; /* _DMAC5 */\r
+ _UWORD _DMAC6:4; /* _DMAC6 */\r
+ _UWORD _DMAC7:4; /* _DMAC7 */\r
+ } BIT; /* */\r
+ } IPR07; /* */\r
+ union { /* IPR08 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _DMAC8:4; /* _DMAC8 */\r
+ _UWORD _DMAC9:4; /* _DMAC9 */\r
+ _UWORD _DMAC10:4; /* _DMAC10 */\r
+ _UWORD _DMAC11:4; /* _DMAC11 */\r
+ } BIT; /* */\r
+ } IPR08; /* */\r
+ union { /* IPR09 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _DMAC12:4; /* _DMAC12 */\r
+ _UWORD _DMAC13:4; /* _DMAC13 */\r
+ _UWORD _DMAC14:4; /* _DMAC14 */\r
+ _UWORD _DMAC15:4; /* _DMAC15 */\r
+ } BIT; /* */\r
+ } IPR09; /* */\r
+ union { /* IPR10 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _USB:4; /* _USB */\r
+ _UWORD _VDC40:4; /* _VDC40 */\r
+ _UWORD _VDC41:4; /* _VDC41 */\r
+ _UWORD _VDC42:4; /* _VDC42 */\r
+ } BIT; /* */\r
+ } IPR10; /* */\r
+ union { /* IPR11 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _IMRLS:4; /* IMRLS */\r
+ _UWORD _JCU:4; /* JCU */\r
+ _UWORD _DISCOM:4; /* DISCOM */\r
+ _UWORD _RGPVG:4; /* RGPVG */\r
+ } BIT; /* */\r
+ } IPR11; /* */\r
+ union { /* IPR12 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _CMT0:4; /* _CMT0 */\r
+ _UWORD _CMT1:4; /* _CMT1 */\r
+ _UWORD _BSC:4; /* _BSC */\r
+ _UWORD _WDT:4; /* _WDT */\r
+ } BIT; /* */\r
+ } IPR12; /* */\r
+ union { /* IPR13 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _MTU00:4; /* _MTU00 */\r
+ _UWORD _MTU01:4; /* _MTU01 */\r
+ _UWORD _MTU10:4; /* _MTU10 */\r
+ _UWORD _MTU11:4; /* _MTU11 */\r
+ } BIT; /* */\r
+ } IPR13; /* */\r
+ union { /* IPR14 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _MTU20:4; /* _MTU20 */\r
+ _UWORD _MTU21:4; /* _MTU21 */\r
+ _UWORD _MTU30:4; /* _MTU30 */\r
+ _UWORD _MTU31:4; /* _MTU31 */\r
+ } BIT; /* */\r
+ } IPR14; /* */\r
+ union { /* IPR15 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _MTU40:4; /* _MTU40 */\r
+ _UWORD _MTU41:4; /* _MTU41 */\r
+ _UWORD _PWM1:4; /* _PWM1 */\r
+ _UWORD _PWM2:4; /* _PWM2 */\r
+ } BIT; /* */\r
+ } IPR15; /* */\r
+ union { /* IPR16 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _SDG0:4; /* _SDG0 */\r
+ _UWORD _SDG1:4; /* _SDG1 */\r
+ _UWORD _SDG2:4; /* _SDG2 */\r
+ _UWORD _SDG3:4; /* _SDG3 */\r
+ } BIT; /* */\r
+ } IPR16; /* */\r
+ union { /* IPR17 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _ADC:4; /* _ADC */\r
+ _UWORD _SSI0:4; /* _SSI0 */\r
+ _UWORD _SSI1:4; /* _SSI1 */\r
+ _UWORD _SSI2:4; /* _SSI2 */\r
+ } BIT; /* */\r
+ } IPR17; /* */\r
+ union { /* IPR18 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _SSI3:4; /* _SSI3 */\r
+ _UWORD _SSI4:4; /* _SSI4 */\r
+ _UWORD _SSI5:4; /* _SSI5 */\r
+ _UWORD _SPDIF:4; /* _SPDIF */\r
+ } BIT; /* */\r
+ } IPR18; /* */\r
+ union { /* IPR19 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _IIC30:4; /* _IIC30 */\r
+ _UWORD _IIC31:4; /* _IIC31 */\r
+ _UWORD _IIC32:4; /* _IIC32 */\r
+ _UWORD _IIC33:4; /* _IIC33 */\r
+ } BIT; /* */\r
+ } IPR19; /* */\r
+ union { /* IPR20 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _SCIF0:4; /* _SCIF0 */\r
+ _UWORD _SCIF1:4; /* _SCIF1 */\r
+ _UWORD _SCIF2:4; /* _SCIF2 */\r
+ _UWORD _SCIF3:4; /* _SCIF3 */\r
+ } BIT; /* */\r
+ } IPR20; /* */\r
+ union { /* IPR21 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _SCIF4:4; /* _SCIF4 */\r
+ _UWORD _SCIF5:4; /* _SCIF5 */\r
+ _UWORD _SCIF6:4; /* _SCIF6 */\r
+ _UWORD _SCIF7:4; /* _SCIF7 */\r
+ } BIT; /* */\r
+ } IPR21; /* */\r
+ union { /* IPR22 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _SIOF:4; /* _SIOF */\r
+ _UWORD _RCAN0:4; /* _RCAN0 */\r
+ _UWORD _RCAN1:4; /* _RCAN1 */\r
+ _UWORD _RCAN2:4; /* _RCAN2 */\r
+ } BIT; /* */\r
+ } IPR22; /* */\r
+ union { /* IPR23 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _RSPI0:4; /* _RSPI0 */\r
+ _UWORD _RSPI1:4; /* _RSPI1 */\r
+ _UWORD _RQSPI0:4; /* _RQSPI0 */\r
+ _UWORD _RQSPI1:4; /* _RQSPI1 */\r
+ } BIT; /* */\r
+ } IPR23; /* */\r
+ union { /* IPR24 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _IEB:4; /* _IEB */\r
+ _UWORD _ROMDEC:4; /* _ROMDEC */\r
+ _UWORD _FLCTL:4; /* _FLCTL */\r
+ _UWORD _MMC:4; /* _MMC */\r
+ } BIT; /* */\r
+ } IPR24; /* */\r
+ union { /* IPR25 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _SDHI0:4; /* _SDHI0 */\r
+ _UWORD _SDHI1:4; /* _SDHI1 */\r
+ _UWORD _RTC:4; /* _RTC */\r
+ _UWORD :4; /* */\r
+ } BIT; /* */\r
+ } IPR25; /* */\r
+ union { /* IPR26 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD _SRC0:4; /* _SRC0 */\r
+ _UWORD _SRC1:4; /* _SRC1 */\r
+ _UWORD _SRC2:4; /* _SRC2 */\r
+ _UWORD :4; /* */\r
+ } BIT; /* */\r
+ } IPR26; /* */\r
+}; /* */\r
+ #endif\r
+struct st_ccnt { /* struct CCNT */\r
+ union { /* CCR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :20; /* */\r
+ _UDWORD ICF:1; /* ICF */\r
+ _UDWORD :2; /* */\r
+ _UDWORD ICE:1; /* ICE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD OCF:1; /* OCF */\r
+ _UDWORD :1; /* */\r
+ _UDWORD WT:1; /* WT */\r
+ _UDWORD OCE:1; /* OCE */\r
+ } BIT; /* */\r
+ } CCR1; /* */\r
+ union { /* CCR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :15; /* */\r
+ _UDWORD LE:1; /* LE */\r
+ _UDWORD :6; /* */\r
+ _UDWORD W3LOAD:1; /* W3LOAD */\r
+ _UDWORD W3LOCK:1; /* W3LOCK */\r
+ _UDWORD :6; /* */\r
+ _UDWORD W2LOAD:1; /* W2LOAD */\r
+ _UDWORD W2LOCK:1; /* W2LOCK */\r
+ } BIT; /* */\r
+ } CCR2; /* */\r
+};\r
+ #if 0\r
+union CSnBCR{ /* CSnBCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :1; /* */\r
+ _UDWORD IWW:3; /* IWW */\r
+ _UDWORD IWRWD:3; /* IWRWD */\r
+ _UDWORD IWRWS:3; /* IWRWS */\r
+ _UDWORD IWRRD:3; /* IWRRD */\r
+ _UDWORD IWRRS:3; /* IWRRS */\r
+ _UDWORD :1; /* */\r
+ _UDWORD TYPE:3; /* TYPE */\r
+ _UDWORD ENDIAN:1; /* ENDIAN */\r
+ _UDWORD BSZ:2; /* BSZ */\r
+ _UDWORD :9; /* */\r
+ } BIT; /* */\r
+}; /* */\r
+struct st_bsc { /* struct BSC */\r
+ union { /* CMNCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :20; /* */\r
+ _UDWORD BLOCK:1; /* BLOCK */\r
+ _UDWORD DPRTY:2; /* DPRTY */\r
+ _UDWORD DMAIW:3; /* DMAIW */\r
+ _UDWORD DMAIWA:1; /* DMAIWA */\r
+ _UDWORD :3; /* */\r
+ _UDWORD HIZMEM:1; /* HIZMEM */\r
+ _UDWORD HIZCNT:1; /* HIZCNT */\r
+ } BIT; /* */\r
+ } CMNCR; /* */\r
+ union CSnBCR CS0BCR; /* CS0BCR */\r
+ union CSnBCR CS1BCR; /* CS1BCR */\r
+ union CSnBCR CS2BCR; /* CS2BCR */\r
+ union CSnBCR CS3BCR; /* CS3BCR */\r
+ union CSnBCR CS4BCR; /* CS4BCR */\r
+ union CSnBCR CS5BCR; /* CS5BCR */\r
+ _UBYTE wk0[12]; /* */\r
+ union { /* CS0WCR */\r
+ union { /* CS0WCR(NORMAL) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :11; /* */\r
+ _UDWORD BAS:1; /* BAS */\r
+ _UDWORD :7; /* */\r
+ _UDWORD SW:2; /* SW */\r
+ _UDWORD WR:4; /* WR */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD :4; /* */\r
+ _UDWORD HW:2; /* HW */\r
+ } BIT; /* */\r
+ } NORMAL; /* */\r
+ union { /* CS0WCR(BROM_ASY) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :10; /* */\r
+ _UDWORD BST:2; /* BST */\r
+ _UDWORD :2; /* */\r
+ _UDWORD BW:2; /* BW */\r
+ _UDWORD :5; /* */\r
+ _UDWORD W:4; /* W */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD :6; /* */\r
+ } BIT; /* */\r
+ } BROM_ASY; /* */\r
+ union { /* CS0WCR(BROM_SY) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :14; /* */\r
+ _UDWORD BW:2; /* BW */\r
+ _UDWORD :5; /* */\r
+ _UDWORD W:4; /* W */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD :6; /* */\r
+ } BIT; /* */\r
+ } BROM_SY; /* */\r
+ } CS0WCR;\r
+ union { /* CS1WCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :11; /* */\r
+ _UDWORD BAS:1; /* BAS */\r
+ _UDWORD :1; /* */\r
+ _UDWORD WW:3; /* WW */\r
+ _UDWORD :3; /* */\r
+ _UDWORD SW:2; /* SW */\r
+ _UDWORD WR:4; /* WR */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD :4; /* */\r
+ _UDWORD HW:2; /* HW */\r
+ } BIT; /* */\r
+ } CS1WCR; /* */\r
+ union { /* CS2WCR */\r
+ union { /* CS2WCR(NORMAL) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :11; /* */\r
+ _UDWORD BAS:1; /* BAS */\r
+ _UDWORD :9; /* */\r
+ _UDWORD WR:4; /* WR */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD :6; /* */\r
+ } BIT; /* */\r
+ } NORMAL; /* */\r
+ union { /* CS2WCR(SDRAM) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :23; /* */\r
+ _UDWORD A2CL:2; /* A2CL */\r
+ _UDWORD :7; /* */\r
+ } BIT; /* */\r
+ } SDRAM; /* */\r
+ } CS2WCR; /* */\r
+ union { /* CS3WCR */\r
+ union { /* CS3WCR(NORMAL) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :11; /* */\r
+ _UDWORD BAS:1; /* BAS */\r
+ _UDWORD :9; /* */\r
+ _UDWORD WR:4; /* WR */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD :6; /* */\r
+ } BIT; /* */\r
+ } NORMAL; /* */\r
+ union { /* CS3WCR(SDRAM) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :17; /* */\r
+ _UDWORD WTRP:2; /* WTRP */\r
+ _UDWORD :1; /* */\r
+ _UDWORD WTRCD:2; /* WTRCD */\r
+ _UDWORD :1; /* */\r
+ _UDWORD A3CL:2; /* A3CL */\r
+ _UDWORD :2; /* */\r
+ _UDWORD TRWL:2; /* TRWL */\r
+ _UDWORD :1; /* */\r
+ _UDWORD WTRC:2; /* WTRC */\r
+ } BIT; /* */\r
+ } SDRAM; /* */\r
+ } CS3WCR; /* */\r
+ union { /* CS4WCR */\r
+ union { /* CS4WCR(NORMAL) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :11; /* */\r
+ _UDWORD BAS:1; /* BAS */\r
+ _UDWORD :1; /* */\r
+ _UDWORD WW:3; /* WW */\r
+ _UDWORD :3; /* */\r
+ _UDWORD SW:2; /* SW */\r
+ _UDWORD WR:4; /* WR */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD :4; /* */\r
+ _UDWORD HW:2; /* HW */\r
+ } BIT; /* */\r
+ } NORMAL; /* */\r
+ union { /* CS4WCR(BROM_ASY) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :10; /* */\r
+ _UDWORD BST:2; /* BST */\r
+ _UDWORD :2; /* */\r
+ _UDWORD BW:2; /* BW */\r
+ _UDWORD :3; /* */\r
+ _UDWORD SW:2; /* SW */\r
+ _UDWORD W:4; /* W */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD :4; /* */\r
+ _UDWORD HW:2; /* HW */\r
+ } BIT; /* */\r
+ } BROM_ASY; /* */\r
+ } CS4WCR; /* */\r
+ union { /* CS5WCR */\r
+ union { /* CS5WCR(NORMAL) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :10; /* */\r
+ _UDWORD SZSEL:1; /* SZSEL */\r
+ _UDWORD MPXWBAS:1; /* MPXW/BAS */\r
+ _UDWORD :1; /* */\r
+ _UDWORD WW:3; /* WW */\r
+ _UDWORD :3; /* */\r
+ _UDWORD SW:2; /* SW */\r
+ _UDWORD WR:4; /* WR */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD :4; /* */\r
+ _UDWORD HW:2; /* HW */\r
+ } BIT; /* */\r
+ } NORMAL; /* */\r
+ union { /* CS5WCR(PCMCIA) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :10; /* */\r
+ _UDWORD SA:2; /* SA */\r
+ _UDWORD :5; /* */\r
+ _UDWORD TED:4; /* TED */\r
+ _UDWORD PCW:4; /* PCW */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD :2; /* */\r
+ _UDWORD TEH:4; /* TEH */\r
+ } BIT; /* */\r
+ } PCMCIA; /* */\r
+ } CS5WCR; /* */\r
+ _UBYTE wk1[12]; /* */\r
+ union { /* SDCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :11; /* */\r
+ _UDWORD A2ROW:2; /* A2ROW */\r
+ _UDWORD :1; /* */\r
+ _UDWORD A2COL:2; /* A2COL */\r
+ _UDWORD :2; /* */\r
+ _UDWORD DEEP:1; /* DEEP */\r
+ _UDWORD :1; /* */\r
+ _UDWORD RFSH:1; /* RFSH */\r
+ _UDWORD RMODE:1; /* RMODE */\r
+ _UDWORD PDOWN:1; /* PDOWN */\r
+ _UDWORD BACTV:1; /* BACTV */\r
+ _UDWORD :3; /* */\r
+ _UDWORD A3ROW:2; /* A3ROW */\r
+ _UDWORD :1; /* */\r
+ _UDWORD A3COL:2; /* A3COL */\r
+ } BIT; /* */\r
+ } SDCR; /* */\r
+ union { /* RTCSR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :24; /* */\r
+ _UDWORD CMF:1; /* CMF */\r
+ _UDWORD CMIE:1; /* CMIE */\r
+ _UDWORD CKS:3; /* CKS */\r
+ _UDWORD RRC:3; /* RRC */\r
+ } BIT; /* */\r
+ } RTCSR; /* */\r
+ union { /* RTCNT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RTCNT; /* */\r
+ union { /* RTCOR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RTCOR; /* */\r
+}; /* */\r
+struct st_dmac { /* struct DMAC */\r
+ union { /* SAR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR0; /* */\r
+ union { /* DAR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR0; /* */\r
+ union { /* DMATCR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR0; /* */\r
+ union { /* CHCR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DO:1; /* DO */\r
+ _UBYTE TL:1; /* TL */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE AM:1; /* AM */\r
+ _UBYTE AL:1; /* AL */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE DL:1; /* DL */\r
+ _UBYTE DS:1; /* DS */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR0; /* */\r
+ union { /* SAR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR1; /* */\r
+ union { /* DAR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR1; /* */\r
+ union { /* DMATCR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR1; /* */\r
+ union { /* CHCR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :3; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE :2; /* */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR1; /* */\r
+ union { /* SAR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR2; /* */\r
+ union { /* DAR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR2; /* */\r
+ union { /* DMATCR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR2; /* */\r
+ union { /* CHCR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR2; /* */\r
+ union { /* SAR3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR3; /* */\r
+ union { /* DAR3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR3; /* */\r
+ union { /* DMATCR3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR3; /* */\r
+ union { /* CHCR3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR3; /* */\r
+ union { /* SAR4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR4; /* */\r
+ union { /* DAR4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR4; /* */\r
+ union { /* DMATCR4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR4; /* */\r
+ union { /* CHCR4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR4; /* */\r
+ union { /* SAR5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR5; /* */\r
+ union { /* DAR5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR5; /* */\r
+ union { /* DMATCR5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR5; /* */\r
+ union { /* CHCR5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR5; /* */\r
+ union { /* SAR6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR6; /* */\r
+ union { /* DAR6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR6; /* */\r
+ union { /* DMATCR6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR6; /* */\r
+ union { /* CHCR6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR6; /* */\r
+ union { /* SAR7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR7; /* */\r
+ union { /* DAR7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR7; /* */\r
+ union { /* DMATCR7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR7; /* */\r
+ union { /* CHCR7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR7; /* */\r
+ union { /* SAR8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR8; /* */\r
+ union { /* DAR8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR8; /* */\r
+ union { /* DMATCR8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR8; /* */\r
+ union { /* CHCR8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR8; /* */\r
+ union { /* SAR9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR9; /* */\r
+ union { /* DAR9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR9; /* */\r
+ union { /* DMATCR9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR9; /* */\r
+ union { /* CHCR9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR9; /* */\r
+ union { /* SAR10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR10; /* */\r
+ union { /* DAR10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR10; /* */\r
+ union { /* DMATCR10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR10; /* */\r
+ union { /* CHCR10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR10; /* */\r
+ union { /* SAR11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR11; /* */\r
+ union { /* DAR11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR11; /* */\r
+ union { /* DMATCR11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR11; /* */\r
+ union { /* CHCR11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR11; /* */\r
+ union { /* SAR12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR12; /* */\r
+ union { /* DAR12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR12; /* */\r
+ union { /* DMATCR12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR12; /* */\r
+ union { /* CHCR12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR12; /* */\r
+ union { /* SAR13 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR13; /* */\r
+ union { /* DAR13 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR13; /* */\r
+ union { /* DMATCR13 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR13; /* */\r
+ union { /* CHCR13 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR13; /* */\r
+ union { /* SAR14 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR14; /* */\r
+ union { /* DAR14 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR14; /* */\r
+ union { /* DMATCR14 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR14; /* */\r
+ union { /* CHCR14 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR14; /* */\r
+ union { /* SAR15 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } SAR15; /* */\r
+ union { /* DAR15 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DAR15; /* */\r
+ union { /* DMATCR15 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } DMATCR15; /* */\r
+ union { /* CHCR15 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE TC:1; /* TC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RLDSAR:1; /* RLDSAR */\r
+ _UBYTE RLDDAR:1; /* RLDDAR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DAF:1; /* DAF */\r
+ _UBYTE SAF:1; /* SAF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TEMASK:1; /* TEMASK */\r
+ _UBYTE HE:1; /* HE */\r
+ _UBYTE HIE:1; /* HIE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE DM:2; /* DM */\r
+ _UBYTE SM:2; /* SM */\r
+ _UBYTE RS:4; /* RS */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TB:1; /* TB */\r
+ _UBYTE TS:2; /* TS */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE TE:1; /* TE */\r
+ _UBYTE DE:1; /* DE */\r
+ } BIT; /* */\r
+ } CHCR15; /* */\r
+ union { /* RSAR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR0; /* */\r
+ union { /* RDAR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR0; /* */\r
+ union { /* RDMATCR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR0; /* */\r
+ _UBYTE wk0[4]; /* */\r
+ union { /* RSAR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR1; /* */\r
+ union { /* RDAR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR1; /* */\r
+ union { /* RDMATCR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR1; /* */\r
+ _UBYTE wk1[4]; /* */\r
+ union { /* RSAR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR2; /* */\r
+ union { /* RDAR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR2; /* */\r
+ union { /* RDMATCR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR2; /* */\r
+ _UBYTE wk2[4]; /* */\r
+ union { /* RSAR3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR3; /* */\r
+ union { /* RDAR3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR3; /* */\r
+ union { /* RDMATCR3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR3; /* */\r
+ _UBYTE wk3[4]; /* */\r
+ union { /* RSAR4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR4; /* */\r
+ union { /* RDAR4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR4; /* */\r
+ union { /* RDMATCR4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR4; /* */\r
+ _UBYTE wk4[4]; /* */\r
+ union { /* RSAR5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR5; /* */\r
+ union { /* RDAR5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR5; /* */\r
+ union { /* RDMATCR5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR5; /* */\r
+ _UBYTE wk5[4]; /* */\r
+ union { /* RSAR6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR6; /* */\r
+ union { /* RDAR6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR6; /* */\r
+ union { /* RDMATCR6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR6; /* */\r
+ _UBYTE wk6[4]; /* */\r
+ union { /* RSAR7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR7; /* */\r
+ union { /* RDAR7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR7; /* */\r
+ union { /* RDMATCR7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR7; /* */\r
+ _UBYTE wk7[4]; /* */\r
+ union { /* RSAR8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR8; /* */\r
+ union { /* RDAR8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR8; /* */\r
+ union { /* RDMATCR8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR8; /* */\r
+ _UBYTE wk8[4]; /* */\r
+ union { /* RSAR9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR9; /* */\r
+ union { /* RDAR9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR9; /* */\r
+ union { /* RDMATCR9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR9; /* */\r
+ _UBYTE wk9[4]; /* */\r
+ union { /* RSAR10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR10; /* */\r
+ union { /* RDAR10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR10; /* */\r
+ union { /* RDMATCR10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR10; /* */\r
+ _UBYTE wk10[4]; /* */\r
+ union { /* RSAR11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR11; /* */\r
+ union { /* RDAR11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR11; /* */\r
+ union { /* RDMATCR11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR11; /* */\r
+ _UBYTE wk11[4]; /* */\r
+ union { /* RSAR12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR12; /* */\r
+ union { /* RDAR12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR12; /* */\r
+ union { /* RDMATCR12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR12; /* */\r
+ _UBYTE wk12[4]; /* */\r
+ union { /* RSAR13 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR13; /* */\r
+ union { /* RDAR13 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR13; /* */\r
+ union { /* RDMATCR13 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR13; /* */\r
+ _UBYTE wk13[4]; /* */\r
+ union { /* RSAR14 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR14; /* */\r
+ union { /* RDAR14 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR14; /* */\r
+ union { /* RDMATCR14 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR14; /* */\r
+ _UBYTE wk14[4]; /* */\r
+ union { /* RSAR15 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RSAR15; /* */\r
+ union { /* RDAR15 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDAR15; /* */\r
+ union { /* RDMATCR15 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RDMATCR15; /* */\r
+ _UBYTE wk15[4]; /* */\r
+ union { /* DMAOR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :2; /* */\r
+ _UWORD CMS:2; /* CMS */\r
+ _UWORD :2; /* */\r
+ _UWORD PR:2; /* PR */\r
+ _UWORD :5; /* */\r
+ _UWORD AE:1; /* AE */\r
+ _UWORD NMIF:1; /* NMIF */\r
+ _UWORD DME:1; /* DME */\r
+ } BIT; /* */\r
+ } DMAOR; /* */\r
+ _UBYTE wk16[254]; /* */\r
+ union { /* DMARS0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UWORD CH1:8; /* CH1 */\r
+ _UWORD CH0:8; /* CH0 */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD CH1MID:6; /* CH1MID */\r
+ _UWORD CH1RID:2; /* CH1RID */\r
+ _UWORD CH0MID:6; /* CH0MID */\r
+ _UWORD CH0RID:2; /* CH0RID */\r
+ } BIT; /* */\r
+ } DMARS0; /* */\r
+ _UBYTE wk17[2]; /* */\r
+ union { /* DMARS1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UWORD CH3:8; /* CH3 */\r
+ _UWORD CH2:8; /* CH2 */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD CH3MID:6; /* CH3ID */\r
+ _UWORD CH3RID:2; /* CH3RID */\r
+ _UWORD CH2MID:6; /* CH2MID */\r
+ _UWORD CH2RID:2; /* CH2RID */\r
+ } BIT; /* */\r
+ } DMARS1; /* */\r
+ _UBYTE wk18[2]; /* */\r
+ union { /* DMARS2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UWORD CH5:8; /* CH5 */\r
+ _UWORD CH4:8; /* CH4 */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD CH5MID:6; /* CH5MID */\r
+ _UWORD CH5RID:2; /* CH5RID */\r
+ _UWORD CH4MID:6; /* CH4MID */\r
+ _UWORD CH4RID:2; /* CH4RID */\r
+ } BIT; /* */\r
+ } DMARS2; /* */\r
+ _UBYTE wk19[2]; /* */\r
+ union { /* DMARS3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UWORD CH7:8; /* CH7 */\r
+ _UWORD CH6:8; /* CH6 */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD CH7MID:6; /* CH7MID */\r
+ _UWORD CH7RID:2; /* CH7RID */\r
+ _UWORD CH6MID:6; /* CH6MID */\r
+ _UWORD CH6RID:2; /* CH6RID */\r
+ } BIT; /* */\r
+ } DMARS3; /* */\r
+ _UBYTE wk20[2]; /* */\r
+ union { /* DMARS4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UWORD CH9:8; /* CH9 */\r
+ _UWORD CH8:8; /* CH8 */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD CH9MID:6; /* CH9MID */\r
+ _UWORD CH9RID:2; /* CH9RID */\r
+ _UWORD CH8MID:6; /* CH8MID */\r
+ _UWORD CH8RID:2; /* CH8RID */\r
+ } BIT; /* */\r
+ } DMARS4; /* */\r
+ _UBYTE wk21[2]; /* */\r
+ union { /* DMARS5 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UWORD CH11:8; /* CH11 */\r
+ _UWORD CH10:8; /* CH10 */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD CH11MID:6; /* CH11MID */\r
+ _UWORD CH11RID:2; /* CH11RID */\r
+ _UWORD CH10MID:6; /* CH10MID */\r
+ _UWORD CH10RID:2; /* CH10RID */\r
+ } BIT; /* */\r
+ } DMARS5; /* */\r
+ _UBYTE wk22[2]; /* */\r
+ union { /* DMARS6 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UWORD CH13:8; /* CH13 */\r
+ _UWORD CH12:8; /* CH12 */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD CH13MID:6; /* CH13MID */\r
+ _UWORD CH13RID:2; /* CH13RID */\r
+ _UWORD CH12MID:6; /* CH12MID */\r
+ _UWORD CH12RID:2; /* CH12RID */\r
+ } BIT; /* */\r
+ } DMARS6; /* */\r
+ _UBYTE wk23[2]; /* */\r
+ union { /* DMARS7 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UWORD CH15:8; /* CH15 */\r
+ _UWORD CH14:8; /* CH14 */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD CH15MID:6; /* CH15MID */\r
+ _UWORD CH15RID:2; /* CH15RID */\r
+ _UWORD CH14MID:6; /* CH14MID */\r
+ _UWORD CH14RID:2; /* CH14RID */\r
+ } BIT; /* */\r
+ } DMARS7; /* */\r
+}; /* */\r
+ #endif\r
+#if 0\r
+struct st_mtu2 { /* struct MTU2 */\r
+ union { /* TCR_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE CCLR:2; /* CCLR */\r
+ _UBYTE CKEG:2; /* CKEG */\r
+ _UBYTE TPSC:3; /* TPSC */\r
+ } BIT; /* */\r
+ } TCR_2; /* */\r
+ union { /* TMDR_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE MD:4; /* MD */\r
+ } BIT; /* */\r
+ } TMDR_2; /* */\r
+ union { /* TIOR_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOB:4; /* IOB */\r
+ _UBYTE IOA:4; /* IOA */\r
+ } BIT; /* */\r
+ } TIOR_2; /* */\r
+ _UBYTE wk0[1]; /* */\r
+ union { /* TIER_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TTGE:1; /* TTGE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TCIEU:1; /* TCIEU */\r
+ _UBYTE TCIEV:1; /* TCIEV */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TGIEB:1; /* TGIEB */\r
+ _UBYTE TGIEA:1; /* TGIEA */\r
+ } BIT; /* */\r
+ } TIER_2; /* */\r
+ union { /* TSR_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TCFD:1; /* TCFD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TCFU:1; /* TCFU */\r
+ _UBYTE TCFV:1; /* TCFV */\r
+ _UBYTE TGFD:1; /* TGFD */\r
+ _UBYTE TGFC:1; /* TGFC */\r
+ _UBYTE TGFB:1; /* TGFB */\r
+ _UBYTE TGFA:1; /* TGFA */\r
+ } BIT; /* */\r
+ } TSR_2; /* */\r
+ union { /* TCNT_2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCNT_2; /* */\r
+ union { /* TGRA_2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRA_2; /* */\r
+ union { /* TGRB_2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRB_2; /* */\r
+ _UBYTE wk1[500]; /* */\r
+ union { /* TCR_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE CCLR:3; /* CCLR */\r
+ _UBYTE CKEG:2; /* CKEG */\r
+ _UBYTE TPSC:3; /* TPSC */\r
+ } BIT; /* */\r
+ } TCR_3; /* */\r
+ union { /* TCR_4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE CCLR:3; /* CCLR */\r
+ _UBYTE CKEG:2; /* CKEG */\r
+ _UBYTE TPSC:3; /* TPSC */\r
+ } BIT; /* */\r
+ } TCR_4; /* */\r
+ union { /* TMDR_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE BFB:1; /* BFB */\r
+ _UBYTE BFA:1; /* BFA */\r
+ _UBYTE MD:4; /* MD */\r
+ } BIT; /* */\r
+ } TMDR_3; /* */\r
+ union { /* TMDR_4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE BFB:1; /* BFB */\r
+ _UBYTE BFA:1; /* BFA */\r
+ _UBYTE MD:4; /* MD */\r
+ } BIT; /* */\r
+ } TMDR_4; /* */\r
+ union { /* TIORH_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOB:4; /* IOB */\r
+ _UBYTE IOA:4; /* IOA */\r
+ } BIT; /* */\r
+ } TIORH_3; /* */\r
+ union { /* TIORL_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOD:4; /* IOD */\r
+ _UBYTE IOC:4; /* IOC */\r
+ } BIT; /* */\r
+ } TIORL_3; /* */\r
+ union { /* TIORH_4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOB:4; /* IOB */\r
+ _UBYTE IOA:4; /* IOA */\r
+ } BIT; /* */\r
+ } TIORH_4; /* */\r
+ union { /* TIORL_4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOD:4; /* IOD */\r
+ _UBYTE IOC:4; /* IOC */\r
+ } BIT; /* */\r
+ } TIORL_4; /* */\r
+ union { /* TIER_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TTGE:1; /* TTGE */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TCIEV:1; /* TCIEV */\r
+ _UBYTE TGIED:1; /* TGIED */\r
+ _UBYTE TGIEC:1; /* TGIEC */\r
+ _UBYTE TGIEB:1; /* TGIEB */\r
+ _UBYTE TGIEA:1; /* TGIEA */\r
+ } BIT; /* */\r
+ } TIER_3; /* */\r
+ union { /* TIER_4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TTGE:1; /* TTGE */\r
+ _UBYTE TTGE2:1; /* TTGE2 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TCIEV:1; /* TCIEV */\r
+ _UBYTE TGIED:1; /* TGIED */\r
+ _UBYTE TGIEC:1; /* TGIEC */\r
+ _UBYTE TGIEB:1; /* TGIEB */\r
+ _UBYTE TGIEA:1; /* TGIEA */\r
+ } BIT; /* */\r
+ } TIER_4; /* */\r
+ union { /* TOER */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE OE4D:1; /* OE4D */\r
+ _UBYTE OE4C:1; /* OE4C */\r
+ _UBYTE OE3D:1; /* OE3D */\r
+ _UBYTE OE4B:1; /* OE4B */\r
+ _UBYTE OE4A:1; /* OE4A */\r
+ _UBYTE OE3B:1; /* OE3B */\r
+ } BIT; /* */\r
+ } TOER; /* */\r
+ _UBYTE wk2[2]; /* */\r
+ union { /* TGCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE BDC:1; /* BDC */\r
+ _UBYTE N:1; /* N */\r
+ _UBYTE P:1; /* P */\r
+ _UBYTE FB:1; /* FB */\r
+ _UBYTE WF:1; /* WF */\r
+ _UBYTE VF:1; /* VF */\r
+ _UBYTE UF:1; /* UF */\r
+ } BIT; /* */\r
+ } TGCR; /* */\r
+ union { /* TOCR1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PSYE:1; /* PSYE */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TOCL:1; /* TOCL */\r
+ _UBYTE TOCS:1; /* TOCS */\r
+ _UBYTE OLSN:1; /* OLSN */\r
+ _UBYTE OLSP:1; /* OLSP */\r
+ } BIT; /* */\r
+ } TOCR1; /* */\r
+ union { /* TOCR2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE BF:2; /* BF */\r
+ _UBYTE OLS3N:1; /* OLS3N */\r
+ _UBYTE OLS3P:1; /* OLS3P */\r
+ _UBYTE OLS2N:1; /* OLS2N */\r
+ _UBYTE OLS2P:1; /* OLS2P */\r
+ _UBYTE OLS1N:1; /* OLS1N */\r
+ _UBYTE OLS1P:1; /* OLS1P */\r
+ } BIT; /* */\r
+ } TOCR2; /* */\r
+ union { /* TCNT_3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCNT_3; /* */\r
+ union { /* TCNT_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCNT_4; /* */\r
+ union { /* TCDR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCDR; /* */\r
+ union { /* TDDR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TDDR; /* */\r
+ union { /* TGRA_3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRA_3; /* */\r
+ union { /* TGRB_3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRB_3; /* */\r
+ union { /* TGRA_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRA_4; /* */\r
+ union { /* TGRB_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRB_4; /* */\r
+ union { /* TCNTS */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCNTS; /* */\r
+ union { /* TCBR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCBR; /* */\r
+ union { /* TGRC_3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRC_3; /* */\r
+ union { /* TGRD_3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRD_3; /* */\r
+ union { /* TGRC_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRC_4; /* */\r
+ union { /* TGRD_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRD_4; /* */\r
+ union { /* TSR_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TCFD:1; /* TCFD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TCFV:1; /* TCFV */\r
+ _UBYTE TGFD:1; /* TGFD */\r
+ _UBYTE TGFC:1; /* TGFC */\r
+ _UBYTE TGFB:1; /* TGFB */\r
+ _UBYTE TGFA:1; /* TGFA */\r
+ } BIT; /* */\r
+ } TSR_3; /* */\r
+ union { /* TSR_4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TCFD:1; /* TCFD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TCFV:1; /* TCFV */\r
+ _UBYTE TGFD:1; /* TGFD */\r
+ _UBYTE TGFC:1; /* TGFC */\r
+ _UBYTE TGFB:1; /* TGFB */\r
+ _UBYTE TGFA:1; /* TGFA */\r
+ } BIT; /* */\r
+ } TSR_4; /* */\r
+ _UBYTE wk3[2]; /* */\r
+ union { /* TITCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE T3AEN:1; /* T3AEN */\r
+ _UBYTE _3ACOR:3; /* _3ACOR */\r
+ _UBYTE T4VEN:1; /* T4VEN */\r
+ _UBYTE _4VCOR:3; /* _4VCOR */\r
+ } BIT; /* */\r
+ } TITCR; /* */\r
+ union { /* TITCNT */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE _3ACNT:3; /* _3ACNT */\r
+ _UBYTE :1; /* */\r
+ _UBYTE _4VCNT:3; /* _4VCNT */\r
+ } BIT; /* */\r
+ } TITCNT; /* */\r
+ union { /* TBTER */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :6; /* */\r
+ _UBYTE BTE:2; /* BTE */\r
+ } BIT; /* */\r
+ } TBTER; /* */\r
+ _UBYTE wk4[1]; /* */\r
+ union { /* TDER */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :7; /* */\r
+ _UBYTE TDER:1; /* TDER */\r
+ } BIT; /* */\r
+ } TDER; /* */\r
+ _UBYTE wk5[1]; /* */\r
+ union { /* TOLBR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE OLS3N:1; /* OLS3N */\r
+ _UBYTE OLS3P:1; /* OLS3P */\r
+ _UBYTE OLS2N:1; /* OLS2N */\r
+ _UBYTE OLS2P:1; /* OLS2P */\r
+ _UBYTE OLS1N:1; /* OLS1N */\r
+ _UBYTE OLS1P:1; /* OLS1P */\r
+ } BIT; /* */\r
+ } TOLBR; /* */\r
+ _UBYTE wk6[1]; /* */\r
+ union { /* TBTM_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :6; /* */\r
+ _UBYTE TTSB:1; /* TTSB */\r
+ _UBYTE TTSA:1; /* TTSA */\r
+ } BIT; /* */\r
+ } TBTM_3; /* */\r
+ union { /* TBTM_4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :6; /* */\r
+ _UBYTE TTSB:1; /* TTSB */\r
+ _UBYTE TTSA:1; /* TTSA */\r
+ } BIT; /* */\r
+ } TBTM_4; /* */\r
+ _UBYTE wk7[6]; /* */\r
+ union { /* TADCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BF:2; /* BF */\r
+ _UWORD :6; /* */\r
+ _UWORD UT4AE:1; /* UT4AE */\r
+ _UWORD DT4AE:1; /* DT4AE */\r
+ _UWORD UT4BE:1; /* UT4BE */\r
+ _UWORD DT4BE:1; /* DT4BE */\r
+ _UWORD ITA3AE:1; /* ITA3AE */\r
+ _UWORD ITA4VE:1; /* ITA4VE */\r
+ _UWORD ITB3AE:1; /* ITB3AE */\r
+ _UWORD ITB4VE:1; /* ITB4VE */\r
+ } BIT; /* */\r
+ } TADCR; /* */\r
+ _UBYTE wk8[2]; /* */\r
+ union { /* TADCORA_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TADCORA_4; /* */\r
+ union { /* TADCORB_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TADCORB_4; /* */\r
+ union { /* TADCOBRA_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TADCOBRA_4; /* */\r
+ union { /* TADCOBRB_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TADCOBRB_4; /* */\r
+ _UBYTE wk9[20]; /* */\r
+ union { /* TWCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE CCE:1; /* CCE */\r
+ _UBYTE :6; /* */\r
+ _UBYTE WRE:1; /* WRE */\r
+ } BIT; /* */\r
+ } TWCR; /* */\r
+ _UBYTE wk10[31]; /* */\r
+ union { /* TSTR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE CST4:1; /* CST4 */\r
+ _UBYTE CST3:1; /* CST3 */\r
+ _UBYTE :3; /* */\r
+ _UBYTE CST2:1; /* CST2 */\r
+ _UBYTE CST1:1; /* CST1 */\r
+ _UBYTE CST0:1; /* CST0 */\r
+ } BIT; /* */\r
+ } TSTR; /* */\r
+ union { /* TSYR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SYNC4:1; /* SYNC4 */\r
+ _UBYTE SYNC3:1; /* SYNC3 */\r
+ _UBYTE :3; /* */\r
+ _UBYTE SYNC2:1; /* SYNC2 */\r
+ _UBYTE SYNC1:1; /* SYNC1 */\r
+ _UBYTE SYNC0:1; /* SYNC0 */\r
+ } BIT; /* */\r
+ } TSYR; /* */\r
+ _UBYTE wk11[2]; /* */\r
+ union { /* TRWER */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :7; /* */\r
+ _UBYTE RWE:1; /* RWE */\r
+ } BIT; /* */\r
+ } TRWER; /* */\r
+ _UBYTE wk12[123]; /* */\r
+ union { /* TCR_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE CCLR:3; /* CCLR */\r
+ _UBYTE CKEG:2; /* CKEG */\r
+ _UBYTE TPSC:3; /* TPSC */\r
+ } BIT; /* */\r
+ } TCR_0; /* */\r
+ union { /* TMDR_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE BFE:1; /* BFE */\r
+ _UBYTE BFB:1; /* BFB */\r
+ _UBYTE BFA:1; /* BFA */\r
+ _UBYTE MD:4; /* MD */\r
+ } BIT; /* */\r
+ } TMDR_0; /* */\r
+ union { /* TIORH_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOB:4; /* IOB */\r
+ _UBYTE IOA:4; /* IOA */\r
+ } BIT; /* */\r
+ } TIORH_0; /* */\r
+ union { /* TIORL_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOD:4; /* IOD */\r
+ _UBYTE IOC:4; /* IOC */\r
+ } BIT; /* */\r
+ } TIORL_0; /* */\r
+ union { /* TIER_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TTGE:1; /* TTGE */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TCIEV:1; /* TCIEV */\r
+ _UBYTE TGIED:1; /* TGIED */\r
+ _UBYTE TGIEC:1; /* TGIEC */\r
+ _UBYTE TGIEB:1; /* TGIEB */\r
+ _UBYTE TGIEA:1; /* TGIEA */\r
+ } BIT; /* */\r
+ } TIER_0; /* */\r
+ union { /* TSR_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TCFD:1; /* TCFD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TCFV:1; /* TCFV */\r
+ _UBYTE TGFD:1; /* TGFD */\r
+ _UBYTE TGFC:1; /* TGFC */\r
+ _UBYTE TGFB:1; /* TGFB */\r
+ _UBYTE TGFA:1; /* TGFA */\r
+ } BIT; /* */\r
+ } TSR_0; /* */\r
+ union { /* TCNT_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCNT_0; /* */\r
+ union { /* TGRA_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRA_0; /* */\r
+ union { /* TGRB_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRB_0; /* */\r
+ union { /* TGRC_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRC_0; /* */\r
+ union { /* TGRD_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRD_0; /* */\r
+ _UBYTE wk13[16]; /* */\r
+ union { /* TGRE_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRE_0; /* */\r
+ union { /* TGRF_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRF_0; /* */\r
+ union { /* TIER2_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TTGE2:1; /* TTGE2 */\r
+ _UBYTE :5; /* */\r
+ _UBYTE TGIEF:1; /* TGIEF */\r
+ _UBYTE TGIEE:1; /* TGIEE */\r
+ } BIT; /* */\r
+ } TIER2_0; /* */\r
+ union { /* TSR2_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :6; /* */\r
+ _UBYTE TGFF:1; /* TGFF */\r
+ _UBYTE TGFE:1; /* TGFE */\r
+ } BIT; /* */\r
+ } TSR2_0; /* */\r
+ union { /* TBTM_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :5; /* */\r
+ _UBYTE TTSE:1; /* TTSE */\r
+ _UBYTE TTSB:1; /* TTSB */\r
+ _UBYTE TTSA:1; /* TTSA */\r
+ } BIT; /* */\r
+ } TBTM_0; /* */\r
+ _UBYTE wk14[89]; /* */\r
+ union { /* TCR_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE CCLR:2; /* CCLR */\r
+ _UBYTE CKEG:2; /* CKEG */\r
+ _UBYTE TPSC:3; /* TPSC */\r
+ } BIT; /* */\r
+ } TCR_1; /* */\r
+ union { /* TMDR_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE MD:4; /* MD */\r
+ } BIT; /* */\r
+ } TMDR_1; /* */\r
+ union { /* TIOR_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOB:4; /* IOB */\r
+ _UBYTE IOA:4; /* IOA */\r
+ } BIT; /* */\r
+ } TIOR_1; /* */\r
+ _UBYTE wk15[1]; /* */\r
+ union { /* TIER_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TTGE:1; /* TTGE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TCIEU:1; /* TCIEU */\r
+ _UBYTE TCIEV:1; /* TCIEV */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TGIEB:1; /* TGIEB */\r
+ _UBYTE TGIEA:1; /* TGIEA */\r
+ } BIT; /* */\r
+ } TIER_1; /* */\r
+ union { /* TSR_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TCFD:1; /* TCFD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TCFU:1; /* TCFU */\r
+ _UBYTE TCFV:1; /* TCFV */\r
+ _UBYTE TGFD:1; /* TGFD */\r
+ _UBYTE TGFC:1; /* TGFC */\r
+ _UBYTE TGFB:1; /* TGFB */\r
+ _UBYTE TGFA:1; /* TGFA */\r
+ } BIT; /* */\r
+ } TSR_1; /* */\r
+ union { /* TCNT_1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCNT_1; /* */\r
+ union { /* TGRA_1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRA_1; /* */\r
+ union { /* TGRB_1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRB_1; /* */\r
+ _UBYTE wk16[4]; /* */\r
+ union { /* TICCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE I2BE:1; /* I2BE */\r
+ _UBYTE I2AE:1; /* I2AE */\r
+ _UBYTE I1BE:1; /* I1BE */\r
+ _UBYTE I1AE:1; /* I1AE */\r
+ } BIT; /* */\r
+ } TICCR; /* */\r
+}; /* */\r
+#endif\r
+\r
+struct st_cmt { /* struct CMT */\r
+ union { /* CMSTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :14; /* */\r
+ _UWORD STR1:1; /* STR1 */\r
+ _UWORD STR0:1; /* STR0 */\r
+ } BIT; /* */\r
+ } CMSTR; /* */\r
+ union { /* CMCSR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD CMF:1; /* CMF */\r
+ _UWORD CMIE:1; /* CMIE */\r
+ _UWORD :4; /* */\r
+ _UWORD CKS:2; /* CKS */\r
+ } BIT; /* */\r
+ } CMCSR0; /* */\r
+ union { /* CMCNT0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } CMCNT0; /* */\r
+ union { /* CMCOR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } CMCOR0; /* */\r
+ union { /* CMCSR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD CMF:1; /* CMF */\r
+ _UWORD CMIE:1; /* CMIE */\r
+ _UWORD :4; /* */\r
+ _UWORD CKS:2; /* CKS */\r
+ } BIT; /* */\r
+ } CMCSR1; /* */\r
+ union { /* CMCNT1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } CMCNT1; /* */\r
+ union { /* CMCOR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } CMCOR1; /* */\r
+}; /* */\r
+union un_wdt { /* union WDT */\r
+ struct { /* Read Access */\r
+ union { /* WTCSR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOVF:1; /* IOVF */\r
+ _UBYTE WTIT:1; /* WT/IT */\r
+ _UBYTE TME:1; /* TME */\r
+ _UBYTE :2; /* */\r
+ _UBYTE CKS:3; /* CKS */\r
+ } BIT; /* */\r
+ } WTCSR; /* */\r
+ _UBYTE wk1; /* */\r
+ _UBYTE WTCNT; /* WTCNT */\r
+ _UBYTE wk2; /* */\r
+ union { /* WRCSR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE WOVF:1; /* WOVF */\r
+ _UBYTE RSTE:1; /* RSTE */\r
+ _UBYTE RSTS:1; /* RSTS */\r
+ _UBYTE :5; /* */\r
+ } BIT; /* */\r
+ } WRCSR; /* */\r
+ } READ; /* */\r
+ struct { /* Write Access */\r
+ _UWORD WTCSR; /* WTCSR */\r
+ _UWORD WTCNT; /* WTCNT */\r
+ _UWORD WRCSR; /* WRCSR */\r
+ } WRITE; /* */\r
+}; /* */\r
+struct st_rtc { /* struct RTC */\r
+ union { /* R64CNT */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE _1Hz:1; /* _1Hz */\r
+ _UBYTE _2Hz:1; /* _2Hz */\r
+ _UBYTE _4Hz:1; /* _4Hz */\r
+ _UBYTE _8Hz:1; /* _8Hz */\r
+ _UBYTE _16Hz:1; /* _16Hz */\r
+ _UBYTE _32Hz:1; /* _32Hz */\r
+ _UBYTE _64Hz:1; /* _64Hz */\r
+ } BIT; /* */\r
+ } R64CNT; /* */\r
+ _UBYTE wk0[1]; /* */\r
+ _UBYTE RSECCNT; /* RSECCNT */\r
+ _UBYTE wk1[1]; /* */\r
+ _UBYTE RMINCNT; /* RMINCNT */\r
+ _UBYTE wk2[1]; /* */\r
+ _UBYTE RHRCNT; /* RHRCNT */\r
+ _UBYTE wk3[1]; /* */\r
+ _UBYTE RWKCNT; /* RWKCNT */\r
+ _UBYTE wk4[1]; /* */\r
+ _UBYTE RDAYCNT; /* RDAYCNT */\r
+ _UBYTE wk5[1]; /* */\r
+ _UBYTE RMONCNT; /* RMONCNT */\r
+ _UBYTE wk6[1]; /* */\r
+ _UWORD RYRCNT; /* RYRCNT */\r
+ union { /* RSECAR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE ENB:1; /* ENB */\r
+ _UBYTE :7; /* */\r
+ } BIT; /* */\r
+ } RSECAR; /* */\r
+ _UBYTE wk7[1]; /* */\r
+ union { /* RMINAR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE ENB:1; /* ENB */\r
+ _UBYTE :7; /* */\r
+ } BIT; /* */\r
+ } RMINAR; /* */\r
+ _UBYTE wk8[1]; /* */\r
+ union { /* RHRAR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE ENB:1; /* ENB */\r
+ _UBYTE :7; /* */\r
+ } BIT; /* */\r
+ } RHRAR; /* */\r
+ _UBYTE wk9[1]; /* */\r
+ union { /* RWKAR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE ENB:1; /* ENB */\r
+ _UBYTE :7; /* */\r
+ } BIT; /* */\r
+ } RWKAR; /* */\r
+ _UBYTE wk10[1]; /* */\r
+ union { /* RDAYAR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE ENB:1; /* ENB */\r
+ _UBYTE :7; /* */\r
+ } BIT; /* */\r
+ } RDAYAR; /* */\r
+ _UBYTE wk11[1]; /* */\r
+ union { /* RMONAR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE ENB:1; /* ENB */\r
+ _UBYTE :7; /* */\r
+ } BIT; /* */\r
+ } RMONAR; /* */\r
+ _UBYTE wk12[1]; /* */\r
+ union { /* RCR1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE CF:1; /* CF */\r
+ _UBYTE :2; /* */\r
+ _UBYTE CIE:1; /* CIE */\r
+ _UBYTE AIE:1; /* AIE */\r
+ _UBYTE :2; /* */\r
+ _UBYTE AF:1; /* AF */\r
+ } BIT; /* */\r
+ } RCR1; /* */\r
+ _UBYTE wk13[1]; /* */\r
+ union { /* RCR2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE PEF:1; /* PEF */\r
+ _UBYTE PES:3; /* PES */\r
+ _UBYTE RTCEN:1; /* RTCEN */\r
+ _UBYTE ADJ:1; /* ADJ */\r
+ _UBYTE RESET:1; /* RESET */\r
+ _UBYTE START:1; /* START */\r
+ } BIT; /* */\r
+ } RCR2; /* */\r
+ _UBYTE wk14[1]; /* */\r
+ _UWORD RYRAR; /* RYRAR */\r
+ _UBYTE wk15[2]; /* */\r
+ union { /* RCR3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE ENB:1; /* ENB */\r
+ _UBYTE :7; /* */\r
+ } BIT; /* */\r
+ } RCR3; /* */\r
+ _UBYTE wk16[1]; /* */\r
+ union { /* RCR5 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :6; /* */\r
+ _UBYTE RCKSEL:2; /* RCKSEL */\r
+ } BIT; /* */\r
+ } RCR5; /* */\r
+ _UBYTE wk17[2]; /* */\r
+ _UBYTE wk18[1]; /* */\r
+ union { /* RFRH */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD SEL64:1; /* SEL64 */\r
+ _UWORD :12; /* */\r
+ _UWORD RFC18:1; /* RFC[18] */\r
+ _UWORD RFC17:1; /* RFC[17] */\r
+ _UWORD RFC16:1; /* RFC[16] */\r
+ } BIT; /* */\r
+ } RFRH; /* */\r
+ union { /* RFRL */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD RFC15:1; /* RFC[15] */\r
+ _UWORD RFC14:1; /* RFC[14] */\r
+ _UWORD RFC13:1; /* RFC[13] */\r
+ _UWORD RFC12:1; /* RFC[12] */\r
+ _UWORD RFC11:1; /* RFC[11] */\r
+ _UWORD RFC10:1; /* RFC[10] */\r
+ _UWORD RFC9:1; /* RFC[9] */\r
+ _UWORD RFC8:1; /* RFC[8] */\r
+ _UWORD RFC7:1; /* RFC[7] */\r
+ _UWORD RFC6:1; /* RFC[6] */\r
+ _UWORD RFC5:1; /* RFC[5] */\r
+ _UWORD RFC4:1; /* RFC[4] */\r
+ _UWORD RFC3:1; /* RFC[3] */\r
+ _UWORD RFC2:1; /* RFC[2] */\r
+ _UWORD RFC1:1; /* RFC[1] */\r
+ _UWORD RFC0:1; /* RFC[0] */\r
+ } BIT; /* */\r
+ } RFRL; /* */\r
+}; /* */\r
+ #if 0\r
+struct st_scif02346 { /* struct SCIF */\r
+ union { /* SCSMR_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD CA:1; /* C/A */\r
+ _UWORD CHR:1; /* CHR */\r
+ _UWORD PE:1; /* PE */\r
+ _UWORD OE:1; /* O/E */\r
+ _UWORD STOP:1; /* STOP */\r
+ _UWORD :1; /* */\r
+ _UWORD CKS:2; /* CKS */\r
+ } BIT; /* */\r
+ } SCSMR; /* */\r
+ _UBYTE wk0[2]; /* */\r
+ union { /* SCBRR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE D:8; /* D */\r
+ } BIT; /* */\r
+ } SCBRR; /* */\r
+ _UBYTE wk1[3]; /* */\r
+ union { /* SCSCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD TIE:1; /* TIE */\r
+ _UWORD RIE:1; /* RIE */\r
+ _UWORD TE:1; /* TE */\r
+ _UWORD RE:1; /* RE */\r
+ _UWORD REIE:1; /* REIE */\r
+ _UWORD :1; /* */\r
+ _UWORD CKE:2; /* CKE */\r
+ } BIT; /* */\r
+ } SCSCR; /* */\r
+ _UBYTE wk2[2]; /* */\r
+ union { /* SCFTDR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE D:8; /* D */\r
+ } BIT; /* */\r
+ } SCFTDR; /* */\r
+ _UBYTE wk3[3]; /* */\r
+ union { /* SCFSR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PERN:4; /* PERN */\r
+ _UWORD FERN:4; /* FERN */\r
+ _UWORD ER:1; /* ER */\r
+ _UWORD TEND:1; /* TEND */\r
+ _UWORD TDFE:1; /* TDFE */\r
+ _UWORD BRK:1; /* BRK */\r
+ _UWORD FER:1; /* FER */\r
+ _UWORD PER:1; /* PER */\r
+ _UWORD RDF:1; /* RDF */\r
+ _UWORD DR:1; /* DR */\r
+ } BIT; /* */\r
+ } SCFSR; /* */\r
+ _UBYTE wk4[2]; /* */\r
+ union { /* SCFRDR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE D:8; /* D */\r
+ } BIT; /* */\r
+ } SCFRDR; /* */\r
+ _UBYTE wk5[3]; /* */\r
+ union { /* SCFCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD RSTRG:3; /* RSTRG */\r
+ _UWORD RTRG:2; /* RTRG */\r
+ _UWORD TTRG:2; /* TTRG */\r
+ _UWORD MCE:1; /* MCE */\r
+ _UWORD TFRST:1; /* TFRST */\r
+ _UWORD RFRST:1; /* RFRST */\r
+ _UWORD LOOP:1; /* LOOP */\r
+ } BIT; /* */\r
+ } SCFCR; /* */\r
+ _UBYTE wk6[2]; /* */\r
+ union { /* SCFDR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD T:5; /* T */\r
+ _UWORD :3; /* */\r
+ _UWORD R:5; /* R */\r
+ } BIT; /* */\r
+ } SCFDR; /* */\r
+ _UBYTE wk7[2]; /* */\r
+ union { /* SCSPTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :12; /* */\r
+ _UWORD SCKIO:1; /* SCKIO */\r
+ _UWORD SCKDT:1; /* SCKDT */\r
+ _UWORD SPB2IO:1; /* SPB2IO */\r
+ _UWORD SPB2DT:1; /* SPB2DT */\r
+ } BIT; /* */\r
+ } SCSPTR; /* */\r
+ _UBYTE wk8[2]; /* */\r
+ union { /* SCLSR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :15; /* */\r
+ _UWORD ORER:1; /* ORER */\r
+ } BIT; /* */\r
+ } SCLSR; /* */\r
+ _UBYTE wk9[2]; /* */\r
+ union { /* SCEMR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD BGDM:1; /* BGDM */\r
+ _UWORD :6; /* */\r
+ _UWORD ABCS:1; /* ABCS */\r
+ } BIT; /* */\r
+ } SCEMR; /* */\r
+}; /* */\r
+struct st_scif157 { /* struct SCIF */\r
+ union { /* SCSMR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD CA:1; /* C/A */\r
+ _UWORD CHR:1; /* CHR */\r
+ _UWORD PE:1; /* PE */\r
+ _UWORD OE:1; /* O/E */\r
+ _UWORD STOP:1; /* STOP */\r
+ _UWORD :1; /* */\r
+ _UWORD CKS:2; /* CKS */\r
+ } BIT; /* */\r
+ } SCSMR; /* */\r
+ _UBYTE wk0[2]; /* */\r
+ union { /* SCBRR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE D:8; /* D */\r
+ } BIT; /* */\r
+ } SCBRR; /* */\r
+ _UBYTE wk1[3]; /* */\r
+ union { /* SCSCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD TIE:1; /* TIE */\r
+ _UWORD RIE:1; /* RIE */\r
+ _UWORD TE:1; /* TE */\r
+ _UWORD RE:1; /* RE */\r
+ _UWORD REIE:1; /* REIE */\r
+ _UWORD :1; /* */\r
+ _UWORD CKE:2; /* CKE */\r
+ } BIT; /* */\r
+ } SCSCR ; /* */\r
+ _UBYTE wk2[2]; /* */\r
+ union { /* SCFTDR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE D:8; /* D */\r
+ } BIT; /* */\r
+ } SCFTDR; /* */\r
+ _UBYTE wk3[3]; /* */\r
+ union { /* SCFSR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PERN:4; /* PERN */\r
+ _UWORD FERN:4; /* FERN */\r
+ _UWORD ER:1; /* ER */\r
+ _UWORD TEND:1; /* TEND */\r
+ _UWORD TDFE:1; /* TDFE */\r
+ _UWORD BRK:1; /* BRK */\r
+ _UWORD FER:1; /* FER */\r
+ _UWORD PER:1; /* PER */\r
+ _UWORD RDF:1; /* RDF */\r
+ _UWORD DR:1; /* DR */\r
+ } BIT; /* */\r
+ } SCFSR ; /* */\r
+ _UBYTE wk4[2]; /* */\r
+ union { /* SCFRDR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE D:8; /* D */\r
+ } BIT; /* */\r
+ } SCFRDR; /* */\r
+ _UBYTE wk5[3]; /* */\r
+ union { /* SCFCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD RSTRG:3; /* RSTRG */\r
+ _UWORD RTRG:2; /* RTRG */\r
+ _UWORD TTRG:2; /* TTRG */\r
+ _UWORD MCE:1; /* MCE */\r
+ _UWORD TFRST:1; /* TFRST */\r
+ _UWORD RFRST:1; /* RFRST */\r
+ _UWORD LOOP:1; /* LOOP */\r
+ } BIT; /* */\r
+ } SCFCR; /* */\r
+ _UBYTE wk6[2]; /* */\r
+ union { /* SCFDR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD T:5; /* T */\r
+ _UWORD :3; /* */\r
+ _UWORD R:5; /* R */\r
+ } BIT; /* */\r
+ } SCFDR; /* */\r
+ _UBYTE wk7[2]; /* */\r
+ union { /* SCSPTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD RTSIO:1; /* RTSIO */\r
+ _UWORD RTSDT:1; /* RTSDT */\r
+ _UWORD CTSIO:1; /* CTSIO */\r
+ _UWORD CTSDT:1; /* CTSDT */\r
+ _UWORD SCKIO:1; /* SCKIO */\r
+ _UWORD SCKDT:1; /* SCKDT */\r
+ _UWORD SPB2IO:1; /* SPB2IO */\r
+ _UWORD SPB2DT:1; /* SPB2DT */\r
+ } BIT; /* */\r
+ } SCSPTR; /* */\r
+ _UBYTE wk8[2]; /* */\r
+ union { /* SCLSR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :15; /* */\r
+ _UWORD ORER:1; /* ORER */\r
+ } BIT; /* */\r
+ } SCLSR; /* */\r
+ _UBYTE wk9[2]; /* */\r
+ union { /* SCEMR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD BGDM:1; /* BGDM */\r
+ _UWORD :6; /* */\r
+ _UWORD ABCS:1; /* ABCS */\r
+ } BIT; /* */\r
+ } SCEMR; /* */\r
+}; /* */\r
+ #endif\r
+struct st_rspi { /* struct RSPI */\r
+ union { /* SPCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SPRIE:1; /* SPRIE */\r
+ _UBYTE SPE:1; /* SPE */\r
+ _UBYTE SPTIE:1; /* SPTIE */\r
+ _UBYTE SPEIE:1; /* SPEIE */\r
+ _UBYTE MSTR:1; /* MSTR */\r
+ _UBYTE MODFEN:1; /* MODFEN */\r
+ _UBYTE :2; /* */\r
+ } BIT; /* */\r
+ } SPCR; /* */\r
+ union { /* SSLP */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :7; /* */\r
+ _UBYTE SSL0P:1; /* SSL0P */\r
+ } BIT; /* */\r
+ } SSLP; /* */\r
+ union { /* SPPCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE MOIFE:1; /* MOIFE */\r
+ _UBYTE MOIFV:1; /* MOIFV */\r
+ _UBYTE :3; /* */\r
+ _UBYTE SPLP:1; /* SPLP */\r
+ } BIT; /* */\r
+ } SPPCR; /* */\r
+ union { /* SPSR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SPRF:1; /* SPRF */\r
+ _UBYTE TEND:1; /* TEND */\r
+ _UBYTE SPTEF:1; /* SPTEF */\r
+ _UBYTE :2; /* */\r
+ _UBYTE MODF:1; /* MODF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE OVRF:1; /* OVRF */\r
+ } BIT; /* */\r
+ } SPSR; /* */\r
+ union { /* SPDR */\r
+ _UDWORD LONG; /* Long Access */\r
+ _UWORD WORD; /* Word Access */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ } SPDR; /* */\r
+ union { /* SPSCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :6; /* */\r
+ _UBYTE SPSLN:2; /* SPSLN */\r
+ } BIT; /* */\r
+ } SPSCR; /* */\r
+ union { /* SPSSR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :6; /* */\r
+ _UBYTE SPCP:2; /* SPCP */\r
+ } BIT; /* */\r
+ } SPSSR; /* */\r
+ union { /* SPBR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SPR:8; /* SPR */\r
+ } BIT; /* */\r
+ } SPBR; /* */\r
+ union { /* SPDCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TXDMY:1; /* TXDMY */\r
+ _UBYTE SPLW:2; /* SPLW */\r
+ _UBYTE :5; /* */\r
+ } BIT; /* */\r
+ } SPDCR; /* */\r
+ union { /* SPCKD */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :5; /* */\r
+ _UBYTE SCKDL:3; /* SCKDL */\r
+ } BIT; /* */\r
+ } SPCKD; /* */\r
+ union { /* SSLND */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :5; /* */\r
+ _UBYTE SLNDL:3; /* SLNDL */\r
+ } BIT; /* */\r
+ } SSLND; /* */\r
+ union { /* SPND */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :5; /* */\r
+ _UBYTE SPNDL:3; /* SPNDL */\r
+ } BIT; /* */\r
+ } SPND; /* */\r
+ _UBYTE wk0[1]; /* */\r
+ union { /* SPCMD0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD SCKDEN:1; /* SCKDEN */\r
+ _UWORD SLNDEN:1; /* SLNDEN */\r
+ _UWORD SPNDEN:1; /* SPNDEN */\r
+ _UWORD LSBF:1; /* LSBF */\r
+ _UWORD SPB:4; /* SPB */\r
+ _UWORD SSLKP:1; /* SSLKP */\r
+ _UWORD :3; /* */\r
+ _UWORD BRDV:2; /* BRDV */\r
+ _UWORD CPOL:1; /* CPOL */\r
+ _UWORD CPHA:1; /* CPHA */\r
+ } BIT; /* */\r
+ } SPCMD0; /* */\r
+ union { /* SPCMD1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD SCKDEN:1; /* SCKDEN */\r
+ _UWORD SLNDEN:1; /* SLNDEN */\r
+ _UWORD SPNDEN:1; /* SPNDEN */\r
+ _UWORD LSBF:1; /* LSBF */\r
+ _UWORD SPB:4; /* SPB */\r
+ _UWORD SSLKP:1; /* SSLKP */\r
+ _UWORD :3; /* */\r
+ _UWORD BRDV:2; /* BRDV */\r
+ _UWORD CPOL:1; /* CPOL */\r
+ _UWORD CPHA:1; /* CPHA */\r
+ } BIT; /* */\r
+ } SPCMD1 ; /* */\r
+ union { /* SPCMD2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD SCKDEN:1; /* SCKDEN */\r
+ _UWORD SLNDEN:1; /* SLNDEN */\r
+ _UWORD SPNDEN:1; /* SPNDEN */\r
+ _UWORD LSBF:1; /* LSBF */\r
+ _UWORD SPB:4; /* SPB */\r
+ _UWORD SSLKP:1; /* SSLKP */\r
+ _UWORD :3; /* */\r
+ _UWORD BRDV:2; /* BRDV */\r
+ _UWORD CPOL:1; /* CPOL */\r
+ _UWORD CPHA:1; /* CPHA */\r
+ } BIT; /* */\r
+ } SPCMD2 ; /* */\r
+ union { /* SPCMD3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD SCKDEN:1; /* SCKDEN */\r
+ _UWORD SLNDEN:1; /* SLNDEN */\r
+ _UWORD SPNDEN:1; /* SPNDEN */\r
+ _UWORD LSBF:1; /* LSBF */\r
+ _UWORD SPB:4; /* SPB */\r
+ _UWORD SSLKP:1; /* SSLKP */\r
+ _UWORD :3; /* */\r
+ _UWORD BRDV:2; /* BRDV */\r
+ _UWORD CPOL:1; /* CPOL */\r
+ _UWORD CPHA:1; /* CPHA */\r
+ } BIT; /* */\r
+ } SPCMD3 ; /* */\r
+ _UBYTE wk1[8]; /* */\r
+ union { /* SPBFCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TXRST:1; /* TXRST */\r
+ _UBYTE RXRST:1; /* RXRST */\r
+ _UBYTE TXTRG:2; /* TXTRG */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RXTRG:3; /* RXTRG */\r
+ } BIT; /* */\r
+ } SPBFCR; /* */\r
+ _UBYTE wk2[1]; /* */\r
+ union { /* SPBFDR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :4; /* */\r
+ _UWORD T:4 ; /* T */\r
+ _UWORD :2; /* */\r
+ _UWORD R:6; /* R */\r
+ } BIT; /* */\r
+ } SPBFDR; /* */\r
+}; /* */\r
+ #if 0\r
+struct st_iic3 { /* struct IIC3 */\r
+ union { /* ICCR1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE ICE:1; /* ICE */\r
+ _UBYTE RCVD:1; /* RCVD */\r
+ _UBYTE MST:1; /* MST */\r
+ _UBYTE TRS:1; /* TRS */\r
+ _UBYTE CKS:4; /* CKS */\r
+ } BIT; /* */\r
+ } ICCR1; /* */\r
+ union { /* ICCR2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE BBSY:1; /* BBSY */\r
+ _UBYTE SCP:1; /* SCP */\r
+ _UBYTE SDAO:1; /* SDAO */\r
+ _UBYTE SDAOP:1; /* SDAOP */\r
+ _UBYTE SCLO:1; /* SCLO */\r
+ _UBYTE :1; /* */\r
+ _UBYTE IICRST:1; /* IICRST */\r
+ _UBYTE :1; /* */\r
+ } BIT; /* */\r
+ } ICCR2; /* */\r
+ union { /* ICMR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MLS:1; /* MLS */\r
+ _UBYTE :3; /* */\r
+ _UBYTE BCWP:1; /* BCWP */\r
+ _UBYTE BC:3; /* BC */\r
+ } BIT; /* */\r
+ } ICMR; /* */\r
+ union { /* ICIER */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TIE:1; /* TIE */\r
+ _UBYTE TEIE:1; /* TEIE */\r
+ _UBYTE RIE:1; /* RIE */\r
+ _UBYTE NAKIE:1; /* NAKIE */\r
+ _UBYTE STIE:1; /* STIE */\r
+ _UBYTE ACKE:1; /* ACKE */\r
+ _UBYTE ACKBR:1; /* ACKBR */\r
+ _UBYTE ACKBT:1; /* ACKBT */\r
+ } BIT; /* */\r
+ } ICIER; /* */\r
+ union { /* ICSR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TDRE:1; /* TDRE */\r
+ _UBYTE TEND:1; /* TEND */\r
+ _UBYTE RDRF:1; /* RDRF */\r
+ _UBYTE NACKF:1; /* NACKF */\r
+ _UBYTE STOP:1; /* STOP */\r
+ _UBYTE ALOVE:1; /* AL/OVE */\r
+ _UBYTE AAS:1; /* AAS */\r
+ _UBYTE ADZ:1; /* ADZ */\r
+ } BIT; /* */\r
+ } ICSR; /* */\r
+ union { /* SAR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SVA:7; /* SVA */\r
+ _UBYTE FS:1; /* FS */\r
+ } BIT; /* */\r
+ } SAR; /* */\r
+ _UBYTE ICDRT; /* ICDRT */\r
+ _UBYTE ICDRR; /* ICDRR */\r
+ union { /* NF2CYC */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :3; /* */\r
+ _UBYTE CKS4:1; /* CKS4 */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PRS:1; /* PRS */\r
+ _UBYTE NF2CYC:1; /* NF2CYC */\r
+ } BIT; /* */\r
+ } NF2CYC; /* */\r
+}; /* */\r
+ #endif\r
+struct st_ssif { /* struct SSIF */\r
+ union { /* SSICR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :1; /* */\r
+ _UDWORD CKS:1; /* CKS */\r
+ _UDWORD TUIEN:1; /* TUIEN */\r
+ _UDWORD TOIEN:1; /* TOIEN */\r
+ _UDWORD RUIEN:1; /* RUIEN */\r
+ _UDWORD ROIEN:1; /* ROIEN */\r
+ _UDWORD IIEN:1; /* IIEN */\r
+ _UDWORD :1; /* */\r
+ _UDWORD CHNL:2; /* CHNL */\r
+ _UDWORD DWL:3; /* DWL */\r
+ _UDWORD SWL:3; /* SWL */\r
+ _UDWORD SCKD:1; /* SCKD */\r
+ _UDWORD SWSD:1; /* SWSD */\r
+ _UDWORD SCKP:1; /* SCKP */\r
+ _UDWORD SWSP:1; /* SWSP */\r
+ _UDWORD SPDP:1; /* SPDP */\r
+ _UDWORD SDTA:1; /* SDTA */\r
+ _UDWORD PDTA:1; /* PDTA */\r
+ _UDWORD DEL:1; /* DEL */\r
+ _UDWORD CKDV:4; /* CKDV */\r
+ _UDWORD MUEN:1; /* MUEN */\r
+ _UDWORD :1; /* */\r
+ _UDWORD TEN:1; /* TEN */\r
+ _UDWORD REN:1; /* REN */\r
+ } BIT; /* */\r
+ } SSICR; /* */\r
+ union { /* SSISR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :2; /* */\r
+ _UDWORD TUIRQ:1; /* TUIRQ */\r
+ _UDWORD TOIRQ:1; /* TOIRQ */\r
+ _UDWORD RUIRQ:1; /* RUIRQ */\r
+ _UDWORD ROIRQ:1; /* ROIRQ */\r
+ _UDWORD IIRQ:1; /* IIRQ */\r
+ _UDWORD :18; /* */\r
+ _UDWORD TCHNO:2; /* TCHNO */\r
+ _UDWORD TSWNO:1; /* TSWNO */\r
+ _UDWORD RCHNO:2; /* RCHNO */\r
+ _UDWORD RSWNO:1; /* RSWNO */\r
+ _UDWORD IDST:1; /* IDST */\r
+ } BIT; /* */\r
+ } SSISR; /* */\r
+ _UBYTE wk0[8]; /* */\r
+ union { /* SSIFCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :24; /* */\r
+ _UDWORD TTRG:2; /* TTRG */\r
+ _UDWORD RTRG:2; /* RTRG */\r
+ _UDWORD TIE:1; /* TIE */\r
+ _UDWORD RIE:1; /* RIE */\r
+ _UDWORD TFRST:1; /* TFRST */\r
+ _UDWORD RFRST:1; /* RFRST */\r
+ } BIT; /* */\r
+ } SSIFCR; /* */\r
+ union { /* SSIFSR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :4; /* */\r
+ _UDWORD TDC:4; /* TDC */\r
+ _UDWORD :7; /* */\r
+ _UDWORD TDE:1; /* TDE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD RDC:4; /* RDC */\r
+ _UDWORD :7; /* */\r
+ _UDWORD RDF:1; /* RDF */\r
+ } BIT; /* */\r
+ } SSIFSR; /* */\r
+ _UDWORD SSIFTDR; /* SSIFTDR */\r
+ _UDWORD SSIFRDR; /* SSIFRDR */\r
+ union { /* SSITDMR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :23; /* */\r
+ _UDWORD CONT:1; /* CONT */\r
+ _UDWORD :7; /* */\r
+ _UDWORD TDM:1; /* TDM */\r
+ } BIT; /* */\r
+ } SSITDMR; /* */\r
+}; /* */\r
+struct st_siof { /* struct SIOF */\r
+ union { /* SIMDR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD TRMD:2; /* TRMD */\r
+ _UWORD SYNCAT:1; /* SYNCAT */\r
+ _UWORD REDG:1; /* REDG */\r
+ _UWORD FL:4; /* FL */\r
+ _UWORD TXDIZ:1; /* TXDIZ */\r
+ _UWORD :1; /* */\r
+ _UWORD SYNCAC:1; /* SYNCAC */\r
+ _UWORD SYNCDL:1; /* SYNCDL */\r
+ _UWORD :4; /* */\r
+ } BIT; /* */\r
+ } SIMDR; /* */\r
+ union { /* SISCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD MSSEL:1; /* MSSEL */\r
+ _UWORD :2; /* */\r
+ _UWORD BRPS:5; /* BRPS */\r
+ _UWORD :5; /* */\r
+ _UWORD BRDV:3; /* BRDV */\r
+ } BIT; /* */\r
+ } SISCR; /* */\r
+ union { /* SITDAR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD TDLE:1; /* TDLE */\r
+ _UWORD :3; /* */\r
+ _UWORD TDLA:4; /* TDLA */\r
+ _UWORD TDRE:1; /* TDRE */\r
+ _UWORD TLREP:1; /* TLREP */\r
+ _UWORD :2; /* */\r
+ _UWORD TDRA:4; /* TDRA */\r
+ } BIT; /* */\r
+ } SITDAR; /* */\r
+ union { /* SIRDAR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD RDLE:1; /* RDLE */\r
+ _UWORD :3; /* */\r
+ _UWORD RDLA:4; /* RDLA */\r
+ _UWORD RDRE:1; /* RDRE */\r
+ _UWORD :3; /* */\r
+ _UWORD RDRA:4; /* RDRA */\r
+ } BIT; /* */\r
+ } SIRDAR; /* */\r
+ _UBYTE wk0[4]; /* */\r
+ union { /* SICTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD SCKE:1; /* SCKE */\r
+ _UWORD FSE:1; /* FSE */\r
+ _UWORD :4; /* */\r
+ _UWORD TXE:1; /* TXE */\r
+ _UWORD RXE:1; /* RXE */\r
+ _UWORD :6; /* */\r
+ _UWORD TXRST:1; /* TXRST */\r
+ _UWORD RXRST:1; /* RXRST */\r
+ } BIT; /* */\r
+ } SICTR; /* */\r
+ _UBYTE wk1[2]; /* */\r
+ union { /* SIFCTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD TFWM:3; /* TFWM */\r
+ _UWORD TFUA:5; /* TFUA */\r
+ _UWORD RFWM:3; /* RFWM */\r
+ _UWORD RFUA:5; /* RFUA */\r
+ } BIT; /* */\r
+ } SIFCTR; /* */\r
+ _UBYTE wk2[2]; /* */\r
+ union { /* SISTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :2; /* */\r
+ _UWORD TFEMP:1; /* TFEMP */\r
+ _UWORD TDREQ:1; /* TDREQ */\r
+ _UWORD :2; /* */\r
+ _UWORD RFFUL:1 ; /* RFFUL */\r
+ _UWORD RDREQ:1; /* RDREQ */\r
+ _UWORD :3; /* */\r
+ _UWORD FSERR:1; /* FSERR */\r
+ _UWORD TFOVF:1; /* TFOVF */\r
+ _UWORD TFUDF:1; /* TFUDF */\r
+ _UWORD RFUDF:1; /* RFUDF */\r
+ _UWORD RFOVF:1; /* RFOVF */\r
+ } BIT; /* */\r
+ } SISTR; /* */\r
+ union { /* SIIER */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD TDMAE:1; /* TDMAE */\r
+ _UWORD :1; /* */\r
+ _UWORD TFEMPE:1; /* TFEMPE */\r
+ _UWORD TDREQE:1; /* TDREQE */\r
+ _UWORD RDMAE:1; /* RDMAE */\r
+ _UWORD :1; /* */\r
+ _UWORD RFFULE:1; /* RFFULE */\r
+ _UWORD RDREQE:1; /* RDREQE */\r
+ _UWORD :3; /* */\r
+ _UWORD FSERRE:1; /* FSERRE */\r
+ _UWORD TFOVFE:1; /* TFOVFE */\r
+ _UWORD TFUDFE:1; /* TFUDFE */\r
+ _UWORD RFUDFE:1; /* RFUDFE */\r
+ _UWORD RFOVFE:1; /* RFOVFE */\r
+ } BIT; /* */\r
+ } SIIER; /* */\r
+ _UBYTE wk3[8]; /* */\r
+ union { /* SITDR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD SITDL:16; /* SITDL */\r
+ _UWORD SITDR:16; /* SITDR */\r
+ } BIT; /* */\r
+ } SITDR; /* */\r
+ union { /* SIRDR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD SIRDL:16; /* SIRDL */\r
+ _UWORD SIRDR:16; /* SIRDR */\r
+ } BIT; /* */\r
+ } SIRDR; /* */\r
+};\r
+union un_mb3116{ /* MB31-MB16 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD MB31:1; /* MB31 */\r
+ _UWORD MB30:1; /* MB30 */\r
+ _UWORD MB29:1; /* MB29 */\r
+ _UWORD MB28:1; /* MB28 */\r
+ _UWORD MB27:1; /* MB27 */\r
+ _UWORD MB26:1; /* MB26 */\r
+ _UWORD MB25:1; /* MB25 */\r
+ _UWORD MB24:1; /* MB24 */\r
+ _UWORD MB23:1; /* MB23 */\r
+ _UWORD MB22:1; /* MB22 */\r
+ _UWORD MB21:1; /* MB21 */\r
+ _UWORD MB20:1; /* MB20 */\r
+ _UWORD MB19:1; /* MB19 */\r
+ _UWORD MB18:1; /* MB18 */\r
+ _UWORD MB17:1; /* MB17 */\r
+ _UWORD MB16:1; /* MB16 */\r
+ } BIT; /* */\r
+};\r
+union un_mb15_0{ /* MB15-MB0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD MB15:1; /* MB15 */\r
+ _UWORD MB14:1; /* MB14 */\r
+ _UWORD MB13:1; /* MB13 */\r
+ _UWORD MB12:1; /* MB12 */\r
+ _UWORD MB11:1; /* MB11 */\r
+ _UWORD MB10:1; /* MB10 */\r
+ _UWORD MB9:1; /* MB9 */\r
+ _UWORD MB8:1; /* MB8 */\r
+ _UWORD MB7:1; /* MB7 */\r
+ _UWORD MB6:1; /* MB6 */\r
+ _UWORD MB5:1; /* MB5 */\r
+ _UWORD MB4:1; /* MB4 */\r
+ _UWORD MB3:1; /* MB3 */\r
+ _UWORD MB2:1; /* MB2 */\r
+ _UWORD MB1:1; /* MB1 */\r
+ _UWORD MB0:1; /* MB0 */\r
+ } BIT; /* */\r
+};\r
+union un_mb15_1{ /* MB15-MB1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD MB15:1; /* MB15 */\r
+ _UWORD MB14:1; /* MB14 */\r
+ _UWORD MB13:1; /* MB13 */\r
+ _UWORD MB12:1; /* MB12 */\r
+ _UWORD MB11:1; /* MB11 */\r
+ _UWORD MB10:1; /* MB10 */\r
+ _UWORD MB9:1; /* MB9 */\r
+ _UWORD MB8:1; /* MB8 */\r
+ _UWORD MB7:1; /* MB7 */\r
+ _UWORD MB6:1; /* MB6 */\r
+ _UWORD MB5:1; /* MB5 */\r
+ _UWORD MB4:1; /* MB4 */\r
+ _UWORD MB3:1; /* MB3 */\r
+ _UWORD MB2:1; /* MB2 */\r
+ _UWORD MB1:1; /* MB1 */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+};\r
+struct st_rcan { /* struct RCAN */\r
+ union { /* MCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD IDR :1; /* IDR */\r
+ _UWORD AHBO :1; /* AHBO */\r
+ _UWORD :3; /* */\r
+ _UWORD TST :3; /* TST */\r
+ _UWORD AWM :1; /* AWM */\r
+ _UWORD HTBO :1; /* HTBO */\r
+ _UWORD SLPM :1; /* SLPM */\r
+ _UWORD :2; /* */\r
+ _UWORD MTP :1; /* MTP */\r
+ _UWORD HLTRQ:1; /* HLTRQ */\r
+ _UWORD RSTRQ:1; /* RSTRQ */\r
+ } BIT; /* */\r
+ } MCR; /* */\r
+ union { /* GSR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :10; /* */\r
+ _UWORD EPS:1; /* EPS */\r
+ _UWORD HSS:1; /* HSS */\r
+ _UWORD RS:1; /* RS */\r
+ _UWORD MTPF:1; /* MTPF */\r
+ _UWORD TRWF:1; /* TRWF */\r
+ _UWORD BOF:1; /* BOF */\r
+ } BIT; /* */\r
+ } GSR; /* */\r
+ union { /* BCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD TSG1:4; /* TSG1 */\r
+ _UWORD :1; /* */\r
+ _UWORD TSG2:3; /* TSG2 */\r
+ _UWORD :2; /* */\r
+ _UWORD SJW:2; /* SJW */\r
+ _UWORD :3; /* */\r
+ _UWORD BSP:1; /* BSP */\r
+ } BIT; /* */\r
+ } BCR1; /* */\r
+ union { /* BCR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD BRP:8; /* BRP */\r
+ } BIT; /* */\r
+ } BCR0; /* */\r
+ union { /* IRR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD TCMI1 :1; /* TCMI1 */\r
+ _UWORD TCMI0 :1; /* TCMI0 */\r
+ _UWORD TOI :1; /* TOI */\r
+ _UWORD BASMIF:1; /* BASMIF */\r
+ _UWORD TCMI2 :1; /* TCMI2 */\r
+ _UWORD SNSMI :1; /* SNSMI */\r
+ _UWORD MOOIF :1; /* MOOIF */\r
+ _UWORD MBEIF :1; /* MBEIF */\r
+ _UWORD OLF :1; /* OLF */\r
+ _UWORD BOFIF :1; /* BOFIF */\r
+ _UWORD EPIF :1; /* EPIF */\r
+ _UWORD RECWIF:1; /* RECWIF */\r
+ _UWORD TECWIF:1; /* TECWIF */\r
+ _UWORD RFRIF :1; /* RFRIF */\r
+ _UWORD DFRIF :1; /* DFRIF */\r
+ _UWORD RSTIF :1; /* RSTIF */\r
+ } BIT; /* */\r
+ } IRR; /* */\r
+ union { /* IMR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD TCMI1M:1; /* TCMI1M */\r
+ _UWORD TCMI0M:1; /* TCMI0M */\r
+ _UWORD TOIM :1; /* TOIM */\r
+ _UWORD BASMIM:1; /* BASMIM */\r
+ _UWORD TCMI2M:1; /* TCMI2M */\r
+ _UWORD SNSMIM:1; /* SNSMIM */\r
+ _UWORD MOOIM :1; /* MOOIM */\r
+ _UWORD MBEIM :1; /* MBEIM */\r
+ _UWORD OLFM :1; /* OLFM */\r
+ _UWORD BOFIM :1; /* BOFIM */\r
+ _UWORD EPIM :1; /* EPIM */\r
+ _UWORD RECWIM:1; /* RECWIM */\r
+ _UWORD TECWIM:1; /* TECWIM */\r
+ _UWORD RFRIM :1; /* RFRIM */\r
+ _UWORD DFRIM :1; /* DFRIM */\r
+ _UWORD RSTIM :1; /* RSTIM */\r
+ } BIT; /* */\r
+ } IMR; /* */\r
+ union { /* TEC_REC */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD TEC:8; /* TEC */\r
+ _UWORD REC:8; /* REC */\r
+ } BIT; /* */\r
+ } TEC_REC ; /* */\r
+ _UBYTE wk0[18]; /* */\r
+ union{ /* TXPR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD MB31:1; /* MB31 */\r
+ _UDWORD MB30:1; /* MB30 */\r
+ _UDWORD MB29:1; /* MB29 */\r
+ _UDWORD MB28:1; /* MB28 */\r
+ _UDWORD MB27:1; /* MB27 */\r
+ _UDWORD MB26:1; /* MB26 */\r
+ _UDWORD MB25:1; /* MB25 */\r
+ _UDWORD MB24:1; /* MB24 */\r
+ _UDWORD MB23:1; /* MB23 */\r
+ _UDWORD MB22:1; /* MB22 */\r
+ _UDWORD MB21:1; /* MB21 */\r
+ _UDWORD MB20:1; /* MB20 */\r
+ _UDWORD MB19:1; /* MB19 */\r
+ _UDWORD MB18:1; /* MB18 */\r
+ _UDWORD MB17:1; /* MB17 */\r
+ _UDWORD MB16:1; /* MB16 */\r
+ _UDWORD MB15:1; /* MB15 */\r
+ _UDWORD MB14:1; /* MB14 */\r
+ _UDWORD MB13:1; /* MB13 */\r
+ _UDWORD MB12:1; /* MB12 */\r
+ _UDWORD MB11:1; /* MB11 */\r
+ _UDWORD MB10:1; /* MB10 */\r
+ _UDWORD MB9:1; /* MB9 */\r
+ _UDWORD MB8:1; /* MB8 */\r
+ _UDWORD MB7:1; /* MB7 */\r
+ _UDWORD MB6:1; /* MB6 */\r
+ _UDWORD MB5:1; /* MB5 */\r
+ _UDWORD MB4:1; /* MB4 */\r
+ _UDWORD MB3:1; /* MB3 */\r
+ _UDWORD MB2:1; /* MB2 */\r
+ _UDWORD MB1:1; /* MB1 */\r
+ } BIT; /* */\r
+ } TXPR0 ; /* */\r
+ _UBYTE wk1[4]; /* */\r
+ union un_mb3116 TXCR1; /* TXCR1 */\r
+ union un_mb15_1 TXCR0; /* TXCR0 */\r
+ _UBYTE wk2[4]; /* */\r
+ union un_mb3116 TXACK1; /* TXACK1 */\r
+ union un_mb15_1 TXACK0; /* TXACK0 */\r
+ _UBYTE wk3[4]; /* */\r
+ union un_mb3116 ABACK1; /* ABACK1 */\r
+ union un_mb15_1 ABACK0; /* ABACK0 */\r
+ _UBYTE wk4[4]; /* */\r
+ union un_mb3116 RXPR1; /* RXPR1 */\r
+ union un_mb15_0 RXPR0; /* RXPR0 */\r
+ _UBYTE wk5[4]; /* */\r
+ union un_mb3116 RFPR1; /* RFPR1 */\r
+ union un_mb15_0 RFPR0; /* RFPR0 */\r
+ _UBYTE wk6[4]; /* */\r
+ union un_mb3116 MBIMR1; /* MBIMR1 */\r
+ union un_mb15_0 MBIMR0; /* MBIMR0 */\r
+ _UBYTE wk7[4]; /* */\r
+ union un_mb3116 UMSR1; /* UMSR1 */\r
+ union un_mb15_0 UMSR0; /* UMSR0 */\r
+ _UBYTE wk8[36]; /* */\r
+ union { /* TTCR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD TE:1; /* TE */\r
+ _UWORD TS:1; /* TS */\r
+ _UWORD CANC :1; /* CANC */\r
+ _UWORD CME2:1; /* CME2 */\r
+ _UWORD CME1:1; /* CME1 */\r
+ _UWORD CME0:1; /* CME0 */\r
+ _UWORD :3; /* */\r
+ _UWORD TCSC:1; /* TCSC */\r
+ _UWORD TPSC :6; /* TPSC */\r
+ } BIT; /* */\r
+ } TTCR0; /* */\r
+ _UBYTE wk9[2]; /* */\r
+ union { /* CMAX_TEW */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD CMAX:3; /* CMAX */\r
+ _UWORD :4; /* */\r
+ _UWORD TEW:4 ; /* TEW */\r
+ } BIT; /* */\r
+ } CMAX_TEW; /* */\r
+ _UWORD RFTROFF; /* RFTROFF */\r
+ union { /* TSR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :11; /* */\r
+ _UWORD SNSM:1; /* SNSM */\r
+ _UWORD TCMF2:1; /* TCMF2 */\r
+ _UWORD TCMF1:1; /* TCMF1 */\r
+ _UWORD TCMF0:1; /* TCMF0 */\r
+ _UWORD TO_NGR_ME:1; /* TO_NGR_ME */\r
+ } BIT; /* */\r
+ } TSR; /* */\r
+ _UWORD CCR; /* CCR */\r
+ _UWORD TCNTR; /* TCNTR */\r
+ _UBYTE wk10[2]; /* */\r
+ _UWORD CYCTR; /* CYCTR */\r
+ _UBYTE wk11[2]; /* */\r
+ _UWORD RFMK; /* RFMK */\r
+ _UBYTE wk12[2]; /* */\r
+ _UWORD TCMR0; /* TCMR0 */\r
+ _UBYTE wk13[2]; /* */\r
+ _UWORD TCMR1; /* TCMR1 */\r
+ _UBYTE wk14[2]; /* */\r
+ _UWORD TCMR2; /* TCMR2 */\r
+ _UBYTE wk15[2]; /* */\r
+ _UWORD TTTSEL; /* TTTSEL */\r
+ _UBYTE wk16[90]; /* */\r
+ struct {\r
+ union { /* CONTROL0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD IDE:1; /* IDE */\r
+ _UDWORD RTR:1; /* RTR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD STDID:11; /* STDID */\r
+ _UDWORD EXTID:18; /* EXTID */\r
+ } BIT; /* */\r
+ } CONTROL0; /* */\r
+ union { /* LAFM */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD IDE:1; /* IDE */\r
+ _UDWORD :2; /* */\r
+ _UDWORD STDID_LAFM:11;/* STDID_LAFM */\r
+ _UDWORD EXTID_LAFM:18;/* EXTID_LAFM */\r
+ } BIT; /* */\r
+ } LAFM; /* */\r
+ _UBYTE MSG_DATA[8]; /* MSG_DATA */\r
+ union { /* CONTROL1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :2; /* */\r
+ _UWORD NMC:1; /* NMC */\r
+ _UWORD ATX:1; /* ATX */\r
+ _UWORD DART:1; /* DART */\r
+ _UWORD MBC:3; /* MBC */\r
+ _UWORD :4; /* */\r
+ _UWORD DLC:4; /* DLC */\r
+ } BIT; /* */\r
+ } CONTROL1; /* */\r
+ _UWORD TIMESTAMP; /* TIMESTAMP */\r
+ _UWORD TTT; /* TTT */\r
+ union { /* TTC */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD TTW:2; /* TTW */\r
+ _UWORD Offset:6; /* Offset */\r
+ _UWORD :5; /* */\r
+ _UWORD rep_factor:3; /* rep_factor */\r
+ } BIT; /* */\r
+ } TTC; /* */\r
+ _UBYTE wk17[8]; /* */\r
+ } MB[32]; /* */\r
+}; /* */\r
+struct st_ieb { /* struct IEB */\r
+ union { /* IECTR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE IOL:1; /* IOL */\r
+ _UBYTE DEE:1; /* DEE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RE:1; /* RE */\r
+ _UBYTE :3; /* */\r
+ } BIT; /* */\r
+ } IECTR; /* */\r
+ union { /* IECMR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :5; /* */\r
+ _UBYTE CMD:3; /* CMD */\r
+ } BIT; /* */\r
+ } IECMR; /* */\r
+ union { /* IEMCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SS:1; /* SS */\r
+ _UBYTE RN:3; /* RN */\r
+ _UBYTE CTL:4; /* CTL */\r
+ } BIT; /* */\r
+ } IEMCR; /* */\r
+ union { /* IEAR1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IARL4:4; /* IARL4 */\r
+ _UBYTE IMD:2; /* IMD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE STE:1; /* STE */\r
+ } BIT; /* */\r
+ } IEAR1; /* */\r
+ union { /* IEAR2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IARU8:8; /* IARU8 */\r
+ } BIT; /* */\r
+ } IEAR2; /* */\r
+ union { /* IESA1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE ISAL4:4; /* ISAL4 */\r
+ _UBYTE :4; /* */\r
+ } BIT; /* */\r
+ } IESA1; /* */\r
+ union { /* IESA2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE ISAU8:8; /* ISAU8 */\r
+ } BIT; /* */\r
+ } IESA2; /* */\r
+ _UBYTE IETBFL; /* IETBFL */\r
+ _UBYTE wk0[1]; /* */\r
+ union { /* IEMA1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IMAL4:4; /* IMAL4 */\r
+ _UBYTE :4; /* */\r
+ } BIT; /* */\r
+ } IEMA1; /* */\r
+ union { /* IEMA2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IMAU8:8; /* IMAU8 */\r
+ } BIT; /* */\r
+ } IEMA2; /* */\r
+ union { /* IERCTL */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE RCTL:4; /* RCTL */\r
+ } BIT; /* */\r
+ } IERCTL; /* */\r
+ _UBYTE IERBFL; /* IERBFL */\r
+ _UBYTE wk1[1]; /* */\r
+ union { /* IELA1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE ILAL8:8; /* ILAL8 */\r
+ } BIT; /* */\r
+ } IELA1; /* */\r
+ union { /* IELA2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE ILAU4:4; /* ILAU4 */\r
+ } BIT; /* */\r
+ } IELA2; /* */\r
+ union { /* IEFLG */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE CMX:1; /* CMX */\r
+ _UBYTE MRQ:1; /* MRQ */\r
+ _UBYTE SRQ:1; /* SRQ */\r
+ _UBYTE SRE:1; /* SRE */\r
+ _UBYTE LCK:1; /* LCK */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RSS:1; /* RSS */\r
+ _UBYTE GG:1; /* GG */\r
+ } BIT; /* */\r
+ } IEFLG; /* */\r
+ union { /* IETSR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TXS:1; /* TXS */\r
+ _UBYTE TXF:1; /* TXF */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TXEAL:1; /* TXEAL */\r
+ _UBYTE TXETTME:1; /* TXETTME */\r
+ _UBYTE TXERO:1; /* TXERO */\r
+ _UBYTE TXEACK:1; /* TXEACK */\r
+ } BIT; /* */\r
+ } IETSR; /* */\r
+ union { /* IEIET */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TXSE:1; /* TXSE */\r
+ _UBYTE TXFE:1; /* TXFE */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TXEALE:1; /* TXEALE */\r
+ _UBYTE TXETTMEE:1; /* TXETTMEE */\r
+ _UBYTE TXEROE:1; /* TXEROE */\r
+ _UBYTE TXEACKE:1; /* TXEACKE */\r
+ } BIT; /* */\r
+ } IEIET; /* */\r
+ _UBYTE wk2[1]; /* */\r
+ union { /* IERSR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE RXBSY:1; /* RXBSY */\r
+ _UBYTE RXS:1; /* RXS */\r
+ _UBYTE RXF:1; /* RXF */\r
+ _UBYTE RXEDE:1; /* RXEDE */\r
+ _UBYTE RXEOVE:1; /* RXEOVE */\r
+ _UBYTE RXERTME:1; /* RXERTME */\r
+ _UBYTE RXEDLE:1; /* RXEDLE */\r
+ _UBYTE RXEPE:1; /* RXEPE */\r
+ } BIT; /* */\r
+ } IERSR; /* */\r
+ union { /* IEIER */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE RXBSYE:1; /* RXBSYE */\r
+ _UBYTE RXSE:1; /* RXSE */\r
+ _UBYTE RXFE:1; /* RXFE */\r
+ _UBYTE RXEDEE:1; /* RXEDEE */\r
+ _UBYTE RXEOVEE:1; /* RXEOVEE */\r
+ _UBYTE RXERTMEE:1; /* RXERTMEE */\r
+ _UBYTE RXEDLEE:1; /* RXEDLEE */\r
+ _UBYTE RXEPEE:1; /* RXEPEE */\r
+ } BIT; /* */\r
+ } IEIER; /* */\r
+ _UBYTE wk3[2]; /* */\r
+ union { /* IECKSR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :3; /* */\r
+ _UBYTE CKS3:1; /* CKS3 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE CKS:3; /* CKS */\r
+ } BIT; /* */\r
+ } IECKSR; /* */\r
+ _UBYTE wk4[231]; /* */\r
+ union { /* IETB001-128 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TB:8; /* TB */\r
+ } BIT; /* */\r
+ } IETB[128]; /* */\r
+ _UBYTE wk5[128]; /* */\r
+ union { /* IERB001-128 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE RB:8; /* RB */\r
+ } BIT; /* */\r
+ } IERB[128]; /* */\r
+}; /* */\r
+struct st_spdif { /* struct SPDIF */\r
+ _UDWORD TLCA; /* TLCA */\r
+ _UDWORD TRCA; /* TRCA */\r
+ union { /* TLCS */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :2; /* */\r
+ _UDWORD CLAC:2; /* CLAC */\r
+ _UDWORD FS:4; /* FS */\r
+ _UDWORD CHNO:4; /* CHNO */\r
+ _UDWORD SRCNO:4; /* SRCNO */\r
+ _UDWORD CATCD:8; /* CATCD */\r
+ _UDWORD :2; /* */\r
+ _UDWORD CTL:5; /* CTL */\r
+ _UDWORD :1; /* */\r
+ } BIT; /* */\r
+ } TLCS; /* */\r
+ union { /* TRCS */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :2; /* */\r
+ _UDWORD CLAC:2; /* CLAC */\r
+ _UDWORD FS:4; /* FS */\r
+ _UDWORD CHNO:4; /* CHNO */\r
+ _UDWORD SRCNO:4; /* SRCNO */\r
+ _UDWORD CATCD:8; /* CATCD */\r
+ _UDWORD :2; /* */\r
+ _UDWORD CTL:5; /* CTL */\r
+ _UDWORD :1; /* */\r
+ } BIT; /* */\r
+ } TRCS; /* */\r
+ _UDWORD TUI; /* TUI */\r
+ _UDWORD RLCA; /* RLCA */\r
+ _UDWORD RRCA; /* RRCA */\r
+ union { /* RLCS */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :2; /* */\r
+ _UDWORD CLAC:2; /* CLAC */\r
+ _UDWORD FS:4; /* FS */\r
+ _UDWORD CHNO:4; /* CHNO */\r
+ _UDWORD SRCNO:4; /* SRCNO */\r
+ _UDWORD CATCD:8; /* CATCD */\r
+ _UDWORD :2; /* */\r
+ _UDWORD CTL:5; /* CTL */\r
+ _UDWORD :1; /* */\r
+ } BIT; /* */\r
+ } RLCS; /* */\r
+ union { /* RRCS */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :2; /* */\r
+ _UDWORD CLAC:2; /* CLAC */\r
+ _UDWORD FS:4; /* FS */\r
+ _UDWORD CHNO:4; /* CHNO */\r
+ _UDWORD SRCNO:4; /* SRCNO */\r
+ _UDWORD CATCD:8; /* CATCD */\r
+ _UDWORD :2; /* */\r
+ _UDWORD CTL:5; /* CTL */\r
+ _UDWORD :1; /* */\r
+ } BIT; /* */\r
+ } RRCS; /* */\r
+ _UDWORD RUI; /* RUI */\r
+ union { /* CTRL */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :3; /* */\r
+ _UDWORD CKS:1; /* CKS */\r
+ _UDWORD :1; /* */\r
+ _UDWORD PB:1; /* PB */\r
+ _UDWORD RASS:2; /* RASS */\r
+ _UDWORD TASS:2; /* TASS */\r
+ _UDWORD RDE:1; /* RDE */\r
+ _UDWORD TDE:1; /* TDE */\r
+ _UDWORD NCSI:1; /* NCSI */\r
+ _UDWORD AOS:1; /* AOS */\r
+ _UDWORD RME:1; /* RME */\r
+ _UDWORD TME:1; /* TME */\r
+ _UDWORD REIE:1; /* REIE */\r
+ _UDWORD TEIE:1; /* TEIE */\r
+ _UDWORD UBOI:1; /* UBOI */\r
+ _UDWORD UBUI:1; /* UBUI */\r
+ _UDWORD CREI:1; /* CREI */\r
+ _UDWORD PAEI:1; /* PAEI */\r
+ _UDWORD PREI:1; /* PREI */\r
+ _UDWORD CSEI:1; /* CSEI */\r
+ _UDWORD ABOI:1; /* ABOI */\r
+ _UDWORD ABUI:1; /* ABUI */\r
+ _UDWORD RUII:1; /* RUII */\r
+ _UDWORD TUII:1; /* TUII */\r
+ _UDWORD RCSI:1; /* RCSI */\r
+ _UDWORD RCBI:1; /* RCBI */\r
+ _UDWORD TCSI:1; /* TCSI */\r
+ _UDWORD TCBI:1; /* TCBI */\r
+ } BIT; /* */\r
+ } CTRL; /* */\r
+ union { /* STAT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :15; /* */\r
+ _UDWORD CMD:1; /* CMD */\r
+ _UDWORD RIS:1; /* RIS */\r
+ _UDWORD TIS:1; /* TIS */\r
+ _UDWORD UBO:1; /* UBO */\r
+ _UDWORD UBU:1; /* UBU */\r
+ _UDWORD CE:1; /* CE */\r
+ _UDWORD PARE:1; /* PARE */\r
+ _UDWORD PREE:1; /* PREE */\r
+ _UDWORD CSE:1; /* CSE */\r
+ _UDWORD ABO:1; /* ABO */\r
+ _UDWORD ABU:1; /* ABU */\r
+ _UDWORD RUIR:1; /* RUIR */\r
+ _UDWORD TUIR:1; /* TUIR */\r
+ _UDWORD CSRX:1; /* CSRX */\r
+ _UDWORD CBRX:1; /* CBRX */\r
+ _UDWORD CSTX:1; /* CSTX */\r
+ _UDWORD CBTX:1; /* CBTX */\r
+ } BIT; /* */\r
+ } STAT; /* */\r
+ _UDWORD TDAD; /* TDAD */\r
+ _UDWORD RDAD; /* RDAD */\r
+}; /* */\r
+struct st_romdec { /* struct ROMDEC */\r
+ union { /* CROMEN */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SUBC_EN:1; /* SUBC_EN */\r
+ _UBYTE CROM_EN:1; /* CROM_EN */\r
+ _UBYTE CROM_STP:1; /* CROM_STP */\r
+ _UBYTE :5; /* */\r
+ } BIT; /* */\r
+ } CROMEN; /* */\r
+ union { /* CROMSY0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SY_AUT:1; /* SY_AUT */\r
+ _UBYTE SY_IEN:1; /* SY_IEN */\r
+ _UBYTE SY_DEN:1; /* SY_DEN */\r
+ _UBYTE :5; /* */\r
+ } BIT; /* */\r
+ } CROMSY0; /* */\r
+ union { /* CROMCTL0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MD_DESC:1; /* MD_DESC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE MD_AUTO:1; /* MD_AUTO */\r
+ _UBYTE MD_AUTOS1:1; /* MD_AUTOS1 */\r
+ _UBYTE MD_AUTOS2:1; /* MD_AUTOS2 */\r
+ _UBYTE MD_SEC:3; /* MD_SEC */\r
+ } BIT; /* */\r
+ } CROMCTL0; /* */\r
+ union { /* CROMCTL1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE M2F2EDC:1; /* M2F2EDC */\r
+ _UBYTE MD_DEC:3; /* MD_DEC */\r
+ _UBYTE :2; /* */\r
+ _UBYTE MD_PQREP:2; /* MD_PQREP */\r
+ } BIT; /* */\r
+ } CROMCTL1; /* */\r
+ _UBYTE wk0[1]; /* */\r
+ union { /* CROMCTL3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE STP_ECC:1; /* STP_ECC */\r
+ _UBYTE STP_EDC:1; /* STP_EDC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE STP_MD:1; /* STP_MD */\r
+ _UBYTE STP_MIN:1; /* STP_MIN */\r
+ _UBYTE :3; /* */\r
+ } BIT; /* */\r
+ } CROMCTL3; /* */\r
+ union { /* CROMCTL4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE LINKOFF:1; /* LINKOFF */\r
+ _UBYTE LINK2:1; /* LINK2 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE EROSEL:1; /* EROSEL */\r
+ _UBYTE NO_ECC:1; /* NO_ECC */\r
+ _UBYTE :3; /* */\r
+ } BIT; /* */\r
+ } CROMCTL4; /* */\r
+ union { /* CROMCTL5 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :7; /* */\r
+ _UBYTE MSF_LBA_SEL:1; /* MSF_LBA_SEL */\r
+ } BIT; /* */\r
+ } CROMCTL5; /* */\r
+ union { /* CROMST0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE ST_SYIL:1; /* ST_SYIL */\r
+ _UBYTE ST_SYNO:1; /* ST_SYNO */\r
+ _UBYTE ST_BLKS:1; /* ST_BLKS */\r
+ _UBYTE ST_BLKL:1; /* ST_BLKL */\r
+ _UBYTE ST_SECS:1; /* ST_SECS */\r
+ _UBYTE ST_SECL:1; /* ST_SECL */\r
+ } BIT; /* */\r
+ } CROMST0; /* */\r
+ union { /* CROMST1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE ER2_HEAD0:1; /* ER2_HEAD0 */\r
+ _UBYTE ER2_HEAD1:1; /* ER2_HEAD1 */\r
+ _UBYTE ER2_HEAD2:1; /* ER2_HEAD2 */\r
+ _UBYTE ER2_HEAD3:1; /* ER2_HEAD3 */\r
+ } BIT; /* */\r
+ } CROMST1; /* */\r
+ _UBYTE wk1[1]; /* */\r
+ union { /* CROMST3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE ER2_SHEAD0:1; /* ER2_SHEAD0 */\r
+ _UBYTE ER2_SHEAD1:1; /* ER2_SHEAD1 */\r
+ _UBYTE ER2_SHEAD2:1; /* ER2_SHEAD2 */\r
+ _UBYTE ER2_SHEAD3:1; /* ER2_SHEAD3 */\r
+ _UBYTE ER2_SHEAD4:1; /* ER2_SHEAD4 */\r
+ _UBYTE ER2_SHEAD5:1; /* ER2_SHEAD5 */\r
+ _UBYTE ER2_SHEAD6:1; /* ER2_SHEAD6 */\r
+ _UBYTE ER2_SHEAD7:1; /* ER2_SHEAD7 */\r
+ } BIT; /* */\r
+ } CROMST3; /* */\r
+ union { /* CROMST4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE NG_MD:1; /* NG_MD */\r
+ _UBYTE NG_MDCMP1:1; /* NG_MDCMP1 */\r
+ _UBYTE NG_MDCMP2:1; /* NG_MDCMP2 */\r
+ _UBYTE NG_MDCMP3:1; /* NG_MDCMP3 */\r
+ _UBYTE NG_MDCMP4:1; /* NG_MDCMP4 */\r
+ _UBYTE NG_MDDEF:1; /* NG_MDDEF */\r
+ _UBYTE NG_MDTIM1:1; /* NG_MDTIM1 */\r
+ _UBYTE NG_MDTIM2:1; /* NG_MDTIM2 */\r
+ } BIT; /* */\r
+ } CROMST4; /* */\r
+ union { /* CROMST5 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE ST_AMD:3; /* ST_AMD */\r
+ _UBYTE ST_MDX:1; /* ST_MDX */\r
+ _UBYTE LINK_ON:1; /* LINK_ON */\r
+ _UBYTE LINK_DET:1; /* LINK_DET */\r
+ _UBYTE LINK_SDET:1; /* LINK_SDET */\r
+ _UBYTE LINK_OUT1:1; /* LINK_OUT1 */\r
+ } BIT; /* */\r
+ } CROMST5; /* */\r
+ union { /* CROMST6 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE ST_ERR:1; /* ST_ERR */\r
+ _UBYTE :1; /* */\r
+ _UBYTE ST_ECCABT:1; /* ST_ECCABT */\r
+ _UBYTE ST_ECCNG:1; /* ST_ECCNG */\r
+ _UBYTE ST_ECCP:1; /* ST_ECCP */\r
+ _UBYTE ST_ECCQ:1; /* ST_ECCQ */\r
+ _UBYTE ST_EDC1:1; /* ST_EDC1 */\r
+ _UBYTE ST_EDC2:1; /* ST_EDC2 */\r
+ } BIT; /* */\r
+ } CROMST6; /* */\r
+ _UBYTE wk2[5]; /* */\r
+ union { /* CBUFST0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE BUF_REF:1; /* BUF_REF */\r
+ _UBYTE BUF_ACT:1; /* BUF_ACT */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } CBUFST0; /* */\r
+ union { /* CBUFST1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE BUF_ECC:1; /* BUF_ECC */\r
+ _UBYTE BUF_EDC:1; /* BUF_EDC */\r
+ _UBYTE :1; /* */\r
+ _UBYTE BUF_MD:1; /* BUF_MD */\r
+ _UBYTE BUF_MIN:1; /* BUF_MIN */\r
+ _UBYTE :3; /* */\r
+ } BIT; /* */\r
+ } CBUFST1; /* */\r
+ union { /* CBUFST2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE BUF_NG:1; /* BUF_NG */\r
+ _UBYTE :7; /* */\r
+ } BIT; /* */\r
+ } CBUFST2; /* */\r
+ _UBYTE wk3[1]; /* */\r
+ _UBYTE HEAD00; /* HEAD00 */\r
+ _UBYTE HEAD01; /* HEAD01 */\r
+ _UBYTE HEAD02; /* HEAD02 */\r
+ _UBYTE HEAD03; /* HEAD03 */\r
+ _UBYTE SHEAD00; /* SHEAD00 */\r
+ _UBYTE SHEAD01; /* SHEAD01 */\r
+ _UBYTE SHEAD02; /* SHEAD02 */\r
+ _UBYTE SHEAD03; /* SHEAD03 */\r
+ _UBYTE SHEAD04; /* SHEAD04 */\r
+ _UBYTE SHEAD05; /* SHEAD05 */\r
+ _UBYTE SHEAD06; /* SHEAD06 */\r
+ _UBYTE SHEAD07; /* SHEAD07 */\r
+ _UBYTE HEAD20; /* HEAD20 */\r
+ _UBYTE HEAD21; /* HEAD21 */\r
+ _UBYTE HEAD22; /* HEAD22 */\r
+ _UBYTE HEAD23; /* HEAD23 */\r
+ _UBYTE SHEAD20; /* SHEAD20 */\r
+ _UBYTE SHEAD21; /* SHEAD21 */\r
+ _UBYTE SHEAD22; /* SHEAD22 */\r
+ _UBYTE SHEAD23; /* SHEAD23 */\r
+ _UBYTE SHEAD24; /* SHEAD24 */\r
+ _UBYTE SHEAD25; /* SHEAD25 */\r
+ _UBYTE SHEAD26; /* SHEAD26 */\r
+ _UBYTE SHEAD27; /* SHEAD27 */\r
+ _UBYTE wk4[16]; /* */\r
+ union { /* CBUFCTL0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE CBUF_AUT:1; /* CBUF_AUT */\r
+ _UBYTE CBUF_EN:1; /* CBUF_EN */\r
+ _UBYTE CBUF_LINK:1; /* CBUF_LINK */\r
+ _UBYTE CBUF_MD:2; /* CBUF_MD */\r
+ _UBYTE CBUF_TS:1; /* CBUF_TS */\r
+ _UBYTE CBUF_Q:1; /* CBUF_Q */\r
+ _UBYTE :1; /* */\r
+ } BIT; /* */\r
+ } CBUFCTL0; /* */\r
+ _UBYTE CBUFCTL1; /* CBUFCTL1 */\r
+ _UBYTE CBUFCTL2; /* CBUFCTL2 */\r
+ _UBYTE CBUFCTL3; /* CBUFCTL3 */\r
+ _UBYTE wk5[1]; /* */\r
+ union { /* CROMST0M */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE ST_SYILM:1; /* ST_SYILM */\r
+ _UBYTE ST_SYNOM:1; /* ST_SYNOM */\r
+ _UBYTE ST_BLKSM:1; /* ST_BLKSM */\r
+ _UBYTE ST_BLKLM:1; /* ST_BLKLM */\r
+ _UBYTE ST_SECSM:1; /* ST_SECSM */\r
+ _UBYTE ST_SECLM:1; /* ST_SECLM */\r
+ } BIT; /* */\r
+ } CROMST0M; /* */\r
+ _UBYTE wk6[186]; /* */\r
+ union { /* ROMDECRST */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE LOGICRST:1; /* LOGICRST */\r
+ _UBYTE RAMRST:1; /* RAMRST */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } ROMDECRST; /* */\r
+ union { /* RSTSTAT */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE RAMCLRST:1; /* RAMCLRST */\r
+ _UBYTE :7; /* */\r
+ } BIT; /* */\r
+ } RSTSTAT; /* */\r
+ union { /* SSI */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE BYTEND:1; /* BYTEND */\r
+ _UBYTE BITEND:1; /* BITEND */\r
+ _UBYTE BUFEND0:2; /* BUFEND0 */\r
+ _UBYTE BUFEND1:2; /* BUFEND1 */\r
+ _UBYTE :2; /* */\r
+ } BIT; /* */\r
+ } SSI; /* */\r
+ _UBYTE wk7[5]; /* */\r
+ union { /* INTHOLD */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE ISEC:1; /* ISEC */\r
+ _UBYTE ITARG:1; /* ITARG */\r
+ _UBYTE ISY:1; /* ISY */\r
+ _UBYTE IERR:1; /* IERR */\r
+ _UBYTE IBUF:1; /* IBUF */\r
+ _UBYTE IREADY:1; /* IREADY */\r
+ _UBYTE :2; /* */\r
+ } BIT; /* */\r
+ } INTHOLD; /* */\r
+ union { /* INHINT */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE INHISEC:1; /* INHISEC */\r
+ _UBYTE INHITARG:1; /* INHITARG */\r
+ _UBYTE INHISY:1; /* INHISY */\r
+ _UBYTE INHIERR:1; /* INHIERR */\r
+ _UBYTE INHIBUF:1; /* INHIBUF */\r
+ _UBYTE INHIREADY:1; /* INHIREADY */\r
+ _UBYTE PREINHREQDM:1; /* PREINHREQDM */\r
+ _UBYTE PREINHIREADY:1; /* PREINHIREADY */\r
+ } BIT; /* */\r
+ } INHINT; /* */\r
+ _UBYTE wk8[246]; /* */\r
+ _UDWORD STRMDIN; /* STRMDIN */\r
+ _UWORD STRMDOUT; /* STRMDOUT */\r
+};\r
+\r
+\r
+#if 0 /* \90Viodefine.h\82ÌADC\92è\8b`\82ð\97p\82¢\82é\82½\82ß\95s\97v */\r
+ /* */\r
+struct st_adc { /* struct ADC */\r
+ union { /* ADDRA */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } ADDRA; /* */\r
+ union { /* ADDRB */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } ADDRB; /* */\r
+ union { /* ADDRC */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } ADDRC; /* */\r
+ union { /* ADDRD */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } ADDRD; /* */\r
+ union { /* ADDRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } ADDRE; /* */\r
+ union { /* ADDRF */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } ADDRF; /* */\r
+ union { /* ADDRG */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } ADDRG; /* */\r
+ union { /* ADDRH */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } ADDRH; /* */\r
+ _UBYTE wk0[16]; /* */\r
+ union { /* ADCSR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD ADF:1; /* ADF */\r
+ _UWORD ADIE:1; /* ADIE */\r
+ _UWORD ADST:1; /* ADST */\r
+ _UWORD TRGS:4; /* TRGS */\r
+ _UWORD CKS:3; /* CKS */\r
+ _UWORD MDS:3; /* MDS */\r
+ _UWORD CH:3; /* CH */\r
+ } BIT; /* */\r
+ } ADCSR; /* */\r
+}; /* */\r
+#endif\r
+\r
+\r
+\r
+struct st_flctl { /* struct FLCTL */\r
+ union { /* FLCMNCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :10; /* */\r
+ _UDWORD BUSYON:1; /* BUSYON */\r
+ _UDWORD :2; /* */\r
+ _UDWORD SNAND:1; /* SNAND */\r
+ _UDWORD QTSEL:1; /* QTSEL */\r
+ _UDWORD :5; /* */\r
+ _UDWORD ACM:2; /* ACM */\r
+ _UDWORD NANDWF:1; /* NANDWF */\r
+ _UDWORD :5; /* */\r
+ _UDWORD CE:1; /* CE */\r
+ _UDWORD :3; /* */\r
+ } BIT; /* */\r
+ } FLCMNCR; /* */\r
+ union { /* FLCMDCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ADRCNT2:1; /* ADRCNT2 */\r
+ _UDWORD SCTCNT_:4; /* SCTCNT */\r
+ _UDWORD ADRMD:1; /* ADRMD */\r
+ _UDWORD CDSRC:1; /* CDSRC */\r
+ _UDWORD DOSR:1; /* DOSR */\r
+ _UDWORD :2; /* */\r
+ _UDWORD SELRW:1; /* SELRW */\r
+ _UDWORD DOADR:1; /* DOADR */\r
+ _UDWORD ADRCNT:2; /* ADRCNT */\r
+ _UDWORD DOCMD2:1; /* DOCMD2 */\r
+ _UDWORD DOCMD1:1; /* DOCMD1 */\r
+ _UDWORD SCTCNT:16; /* SCTCNT */\r
+ } BIT; /* */\r
+ } FLCMDCR; /* */\r
+ union { /* FLCMCDR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :16; /* */\r
+ _UDWORD CMD2:8; /* CMD2 */\r
+ _UDWORD CMD1:8; /* CMD1 */\r
+ } BIT; /* */\r
+ } FLCMCDR; /* */\r
+ _UDWORD FLADR; /* FLADR */\r
+ _UDWORD FLDATAR; /* FLDATAR */\r
+ union { /* FLDTCNTR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ECFLW:8; /* ECFLW */\r
+ _UDWORD DTFLW:8; /* DTFLW */\r
+ _UDWORD :4; /* */\r
+ _UDWORD DTCNT:12; /* DTCNT */\r
+ } BIT; /* */\r
+ } FLDTCNTR; /* */\r
+ union { /* FLINTDMACR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :10; /* */\r
+ _UDWORD FIFOTRG:2; /* FIFOTRG */\r
+ _UDWORD AC1CLR:1; /* AC1CLR */\r
+ _UDWORD AC0CLR:1; /* AC0CLR */\r
+ _UDWORD DREQ1EN:1; /* DREQ1EN */\r
+ _UDWORD DREQ0EN:1; /* DREQ0EN */\r
+ _UDWORD :7; /* */\r
+ _UDWORD STERB:1; /* STERB */\r
+ _UDWORD BTOERB:1; /* BTOERB */\r
+ _UDWORD TRREQF1:1; /* TRREQF1 */\r
+ _UDWORD TRREQF0:1; /* TRREQF0 */\r
+ _UDWORD STERINTE:1; /* STERINTE */\r
+ _UDWORD RBERINTE:1; /* RBERINTE */\r
+ _UDWORD TEINTE:1; /* TEINTE */\r
+ _UDWORD TRINTE1:1; /* TRINTE1 */\r
+ _UDWORD TRINTE0:1; /* TRINTE0 */\r
+ } BIT; /* */\r
+ } FLINTDMACR; /* */\r
+ union { /* FLBSYTMR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :12; /* */\r
+ _UDWORD RBTMOUT:20; /* RBTMOUT */\r
+ } BIT; /* */\r
+ } FLBSYTMR; /* */\r
+ union { /* FLBSYCNT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD STAT:8; /* STAT */\r
+ _UDWORD :4; /* */\r
+ _UDWORD RBTIMCNT:20; /* RBTIMCNT */\r
+ } BIT; /* */\r
+ } FLBSYCNT; /* */\r
+ _UBYTE wk0[8]; /* */\r
+ union { /* FLTRCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :5; /* */\r
+ _UBYTE TRSTAT:1; /* TRSTAT */\r
+ _UBYTE TREND:1; /* TREND */\r
+ _UBYTE TRSTRT:1; /* TRSTRT */\r
+ } BIT; /* */\r
+ } FLTRCR; /* */\r
+ _UBYTE wk1[11]; /* */\r
+ union { /* FLHOLDCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD HOLDEN:1; /* HOLDEN */\r
+ } BIT; /* */\r
+ } FLHOLDCR; /* */\r
+ _UDWORD FLADR2; /* FLADR2 */\r
+ _UBYTE wk2[16]; /* */\r
+ _UDWORD FLDTFIFO; /* FLDTFIFO */\r
+ _UBYTE wk3[12]; /* */\r
+ _UDWORD FLECFIFO; /* FLECFIFO */\r
+}; /* */\r
+ #if 0\r
+struct st_usb { /* struct USB */\r
+ union { /* SYSCFG */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD SCKE:1; /* SCKE */\r
+ _UWORD :2; /* */\r
+ _UWORD HSE:1; /* HSE */\r
+ _UWORD DCFM:1; /* DCFM */\r
+ _UWORD DRPD:1; /* DRPD */\r
+ _UWORD DPRPU:1; /* DPRPU */\r
+ _UWORD UCKFSEL:1; /* UCKFSEL */\r
+ _UWORD UCKPSEL:1; /* UCKPSEL */\r
+ _UWORD UPLLE:1; /* UPLLE */\r
+ _UWORD USBE:1; /* USBE */\r
+ } BIT; /* */\r
+ } SYSCFG; /* */\r
+ union { /* BUSWAIT */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :12; /* */\r
+ _UWORD BWAIT:4; /* BWAIT */\r
+ } BIT; /* */\r
+ } BUSWAIT; /* */\r
+ union { /* SYSSTS */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :14; /* */\r
+ _UWORD LNST:2; /* LNST */\r
+ } BIT; /* */\r
+ } SYSSTS; /* */\r
+ _UBYTE wk0[2]; /* */\r
+ union { /* DVSTCTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :7; /* */\r
+ _UWORD WKUP:1; /* WKUP */\r
+ _UWORD RWUPE:1; /* RWUPE */\r
+ _UWORD USBRST:1; /* USBRST */\r
+ _UWORD RESUME:1; /* RESUME */\r
+ _UWORD UACT:1; /* UACT */\r
+ _UWORD :1; /* */\r
+ _UWORD RHST:3; /* RHST */\r
+ } BIT; /* */\r
+ } DVSTCTR; /* */\r
+ _UBYTE wk1[2]; /* */\r
+ union { /* TESTMODE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :12; /* */\r
+ _UWORD UTST:4; /* UTST */\r
+ } BIT; /* */\r
+ } TESTMODE; /* */\r
+ _UBYTE wk2[2]; /* */\r
+ union { /* D0FBCFG */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :11; /* */\r
+ _UWORD TENDE:1; /* TENDE */\r
+ _UWORD :4; /* */\r
+ } BIT; /* */\r
+ } D0FBCFG; /* */\r
+ union { /* D1FBCFG */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :11; /* */\r
+ _UWORD TENDE:1; /* TENDE */\r
+ _UWORD :4; /* */\r
+ } BIT; /* */\r
+ } D1FBCFG; /* */\r
+ union { /* CFIFO */\r
+ _UDWORD LONG; /* Long Access */\r
+ _UWORD WORD; /* Word Access */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } CFIFO; /* */\r
+ union { /* D0FIFO */\r
+ _UDWORD LONG; /* Long Access */\r
+ _UWORD WORD; /* Word Access */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D0FIFO; /* */\r
+ union { /* D1FIFO */\r
+ _UDWORD LONG; /* Long Access */\r
+ _UWORD WORD; /* Word Access */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D1FIFO; /* */\r
+ union { /* CFIFOSEL */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD RCNT:1; /* RCNT */\r
+ _UWORD REW:1; /* REW */\r
+ _UWORD :2; /* */\r
+ _UWORD MBW:2; /* MBW */\r
+ _UWORD :1; /* */\r
+ _UWORD BIGEND:1; /* BIGEND */\r
+ _UWORD :2; /* */\r
+ _UWORD ISEL:1; /* ISEL */\r
+ _UWORD :1; /* */\r
+ _UWORD CURPIPE:4; /* CURPIPE */\r
+ } BIT; /* */\r
+ } CFIFOSEL; /* */\r
+ union { /* CFIFOCTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BVAL:1; /* BVAL */\r
+ _UWORD BCLR:1; /* BCLR */\r
+ _UWORD FRDY:1; /* FRDY */\r
+ _UWORD :1; /* */\r
+ _UWORD DTLN:12; /* DTLN */\r
+ } BIT; /* */\r
+ } CFIFOCTR; /* */\r
+ _UBYTE wk3[4]; /* */\r
+ union { /* D0FIFOSEL */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD RCNT:1; /* RCNT */\r
+ _UWORD REW:1; /* REW */\r
+ _UWORD DCLRM:1; /* DCLRM */\r
+ _UWORD DREQE:1; /* DREQE */\r
+ _UWORD MBW:2; /* MBW */\r
+ _UWORD :1; /* */\r
+ _UWORD BIGEND:1; /* BIGEND */\r
+ _UWORD :4; /* */\r
+ _UWORD CURPIPE:4; /* CURPIPE */\r
+ } BIT; /* */\r
+ } D0FIFOSEL; /* */\r
+ union { /* D0FIFOCTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BVAL:1; /* BVAL */\r
+ _UWORD BCLR:1; /* BCLR */\r
+ _UWORD FRDY:1; /* FRDY */\r
+ _UWORD :1; /* */\r
+ _UWORD DTLN:12; /* DTLN */\r
+ } BIT; /* */\r
+ } D0FIFOCTR; /* */\r
+ union { /* D1FIFOSEL */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD RCNT:1; /* RCNT */\r
+ _UWORD REW:1; /* REW */\r
+ _UWORD DCLRM:1; /* DCLRM */\r
+ _UWORD DREQE:1; /* DREQE */\r
+ _UWORD MBW:2; /* MBW */\r
+ _UWORD :1; /* */\r
+ _UWORD BIGEND:1; /* BIGEND */\r
+ _UWORD :4; /* */\r
+ _UWORD CURPIPE:4; /* CURPIPE */\r
+ } BIT; /* */\r
+ } D1FIFOSEL; /* */\r
+ union { /* D1FIFOCTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BVAL:1; /* BVAL */\r
+ _UWORD BCLR:1; /* BCLR */\r
+ _UWORD FRDY:1; /* FRDY */\r
+ _UWORD :1; /* */\r
+ _UWORD DTLN:12; /* DTLN */\r
+ } BIT; /* */\r
+ } D1FIFOCTR; /* */\r
+ union { /* INTENB0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD VBSE:1; /* VBSE */\r
+ _UWORD RSME:1; /* RSME */\r
+ _UWORD SOFE:1; /* SOFE */\r
+ _UWORD DVSE:1; /* DVSE */\r
+ _UWORD CTRE:1; /* CTRE */\r
+ _UWORD BEMPE:1; /* BEMPE */\r
+ _UWORD NRDYE:1; /* NRDYE */\r
+ _UWORD BRDYE:1; /* BRDYE */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } INTENB0; /* */\r
+ union { /* INTENB1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD BCHGE:1; /* BCHGE */\r
+ _UWORD :1; /* */\r
+ _UWORD DTCHE:1; /* DTCHE */\r
+ _UWORD ATTCHE:1; /* ATTCHE */\r
+ _UWORD :4; /* */\r
+ _UWORD EOFERRE:1; /* EOFERRE */\r
+ _UWORD SIGNE:1; /* SIGNE */\r
+ _UWORD SACKE:1; /* SACKE */\r
+ _UWORD :4; /* */\r
+ } BIT; /* */\r
+ } INTENB1; /* */\r
+ _UBYTE wk4[2]; /* */\r
+ union { /* BRDYENB */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD PIPE9BRDYE:1; /* PIPE9BRDYE */\r
+ _UWORD PIPE8BRDYE:1; /* PIPE8BRDYE */\r
+ _UWORD PIPE7BRDYE:1; /* PIPE7BRDYE */\r
+ _UWORD PIPE6BRDYE:1; /* PIPE6BRDYE */\r
+ _UWORD PIPE5BRDYE:1; /* PIPE5BRDYE */\r
+ _UWORD PIPE4BRDYE:1; /* PIPE4BRDYE */\r
+ _UWORD PIPE3BRDYE:1; /* PIPE3BRDYE */\r
+ _UWORD PIPE2BRDYE:1; /* PIPE2BRDYE */\r
+ _UWORD PIPE1BRDYE:1; /* PIPE1BRDYE */\r
+ _UWORD PIPE0BRDYE:1; /* PIPE0BRDYE */\r
+ } BIT; /* */\r
+ } BRDYENB; /* */\r
+ union { /* NRDYENB */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD PIPE9NRDYE:1; /* PIPE9NRDYE */\r
+ _UWORD PIPE8NRDYE:1; /* PIPE8NRDYE */\r
+ _UWORD PIPE7NRDYE:1; /* PIPE7NRDYE */\r
+ _UWORD PIPE6NRDYE:1; /* PIPE6NRDYE */\r
+ _UWORD PIPE5NRDYE:1; /* PIPE5NRDYE */\r
+ _UWORD PIPE4NRDYE:1; /* PIPE4NRDYE */\r
+ _UWORD PIPE3NRDYE:1; /* PIPE3NRDYE */\r
+ _UWORD PIPE2NRDYE:1; /* PIPE2NRDYE */\r
+ _UWORD PIPE1NRDYE:1; /* PIPE1NRDYE */\r
+ _UWORD PIPE0NRDYE:1; /* PIPE0NRDYE */\r
+ } BIT; /* */\r
+ } NRDYENB; /* */\r
+ union { /* BEMPENB */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD PIPE9BEMPE:1; /* PIPE9BEMPE */\r
+ _UWORD PIPE8BEMPE:1; /* PIPE8BEMPE */\r
+ _UWORD PIPE7BEMPE:1; /* PIPE7BEMPE */\r
+ _UWORD PIPE6BEMPE:1; /* PIPE6BEMPE */\r
+ _UWORD PIPE5BEMPE:1; /* PIPE5BEMPE */\r
+ _UWORD PIPE4BEMPE:1; /* PIPE4BEMPE */\r
+ _UWORD PIPE3BEMPE:1; /* PIPE3BEMPE */\r
+ _UWORD PIPE2BEMPE:1; /* PIPE2BEMPE */\r
+ _UWORD PIPE1BEMPE:1; /* PIPE1BEMPE */\r
+ _UWORD PIPE0BEMPE:1; /* PIPE0BEMPE */\r
+ } BIT; /* */\r
+ } BEMPENB; /* */\r
+ union { /* SOFCFG */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :7; /* */\r
+ _UWORD TRNENSEL:1; /* TRNENSEL */\r
+ _UWORD :1; /* */\r
+ _UWORD BRDYM:1; /* BRDYM */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } SOFCFG; /* */\r
+ _UBYTE wk5[2]; /* */\r
+ union { /* INTSTS0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD VBINT:1; /* VBINT */\r
+ _UWORD RESM:1; /* RESM */\r
+ _UWORD SOFR:1; /* SOFR */\r
+ _UWORD DVST:1; /* DVST */\r
+ _UWORD CTRT:1; /* CTRT */\r
+ _UWORD BEMP:1; /* BEMP */\r
+ _UWORD NRDY:1; /* NRDY */\r
+ _UWORD BRDY:1; /* BRDY */\r
+ _UWORD VBSTS:1; /* VBSTS */\r
+ _UWORD DVSQ:3; /* DVSQ */\r
+ _UWORD VALID:1; /* VALID */\r
+ _UWORD CTSQ:3; /* CTSQ */\r
+ } BIT; /* */\r
+ } INTSTS0; /* */\r
+ union { /* INTSTS1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD BCHG:1; /* BCHG */\r
+ _UWORD :1; /* */\r
+ _UWORD DTCH:1; /* DTCH */\r
+ _UWORD ATTCH:1; /* ATTCH */\r
+ _UWORD :4; /* */\r
+ _UWORD EOFERR:1; /* EOFERR */\r
+ _UWORD SIGN:1; /* SIGN */\r
+ _UWORD SACK:1; /* SACK */\r
+ _UWORD :4; /* */\r
+ } BIT; /* */\r
+ } INTSTS1; /* */\r
+ _UBYTE wk6[2]; /* */\r
+ union { /* BRDYSTS */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD PIPE9BRDY:1; /* PIPE9BRDY */\r
+ _UWORD PIPE8BRDY:1; /* PIPE8BRDY */\r
+ _UWORD PIPE7BRDY:1; /* PIPE7BRDY */\r
+ _UWORD PIPE6BRDY:1; /* PIPE6BRDY */\r
+ _UWORD PIPE5BRDY:1; /* PIPE5BRDY */\r
+ _UWORD PIPE4BRDY:1; /* PIPE4BRDY */\r
+ _UWORD PIPE3BRDY:1; /* PIPE3BRDY */\r
+ _UWORD PIPE2BRDY:1; /* PIPE2BRDY */\r
+ _UWORD PIPE1BRDY:1; /* PIPE1BRDY */\r
+ _UWORD PIPE0BRDY:1; /* PIPE0BRDY */\r
+ } BIT; /* */\r
+ } BRDYSTS; /* */\r
+ union { /* NRDYSTS */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD PIPE9NRDY:1; /* PIPE9NRDY */\r
+ _UWORD PIPE8NRDY:1; /* PIPE8NRDY */\r
+ _UWORD PIPE7NRDY:1; /* PIPE7NRDY */\r
+ _UWORD PIPE6NRDY:1; /* PIPE6NRDY */\r
+ _UWORD PIPE5NRDY:1; /* PIPE5NRDY */\r
+ _UWORD PIPE4NRDY:1; /* PIPE4NRDY */\r
+ _UWORD PIPE3NRDY:1; /* PIPE3NRDY */\r
+ _UWORD PIPE2NRDY:1; /* PIPE2NRDY */\r
+ _UWORD PIPE1NRDY:1; /* PIPE1NRDY */\r
+ _UWORD PIPE0NRDY:1; /* PIPE0NRDY */\r
+ } BIT; /* */\r
+ } NRDYSTS; /* */\r
+ union { /* BEMPSTS */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD PIPE9BEMP:1; /* PIPE9BEMP */\r
+ _UWORD PIPE8BEMP:1; /* PIPE8BEMP */\r
+ _UWORD PIPE7BEMP:1; /* PIPE7BEMP */\r
+ _UWORD PIPE6BEMP:1; /* PIPE6BEMP */\r
+ _UWORD PIPE5BEMP:1; /* PIPE5BEMP */\r
+ _UWORD PIPE4BEMP:1; /* PIPE4BEMP */\r
+ _UWORD PIPE3BEMP:1; /* PIPE3BEMP */\r
+ _UWORD PIPE2BEMP:1; /* PIPE2BEMP */\r
+ _UWORD PIPE1BEMP:1; /* PIPE1BEMP */\r
+ _UWORD PIPE0BEMP:1; /* PIPE0BEMP */\r
+ } BIT; /* */\r
+ } BEMPSTS; /* */\r
+ union { /* FRMNUM */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD OVRN:1; /* OVRN */\r
+ _UWORD CRCE:1; /* CRCE */\r
+ _UWORD :3; /* */\r
+ _UWORD FRNM:11; /* FRNM */\r
+ } BIT; /* */\r
+ } FRMNUM; /* */\r
+ union { /* UFRMNUM */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :13; /* */\r
+ _UWORD UFRNM:3; /* UFRNM */\r
+ } BIT; /* */\r
+ } UFRMNUM; /* */\r
+ union { /* USBADDR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :9; /* */\r
+ _UWORD USBADDR:7; /* USBADDR */\r
+ } BIT; /* */\r
+ } USBADDR; /* */\r
+ _UBYTE wk7[2]; /* */\r
+ union { /* USBREQ */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BREQUEST:8; /* BREQUEST */\r
+ _UWORD BMREQUESTTYPE:8; /* BMREQUESTTYPE */\r
+ } BIT; /* */\r
+ } USBREQ; /* */\r
+ _UWORD USBVAL; /* USBVAL */\r
+ _UWORD USBINDX; /* USBINDX */\r
+ _UWORD USBLENG; /* USBLENG */\r
+ union { /* DCPCFG */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :11; /* */\r
+ _UWORD DIR:1; /* DIR */\r
+ _UWORD :4; /* */\r
+ } BIT; /* */\r
+ } DCPCFG; /* */\r
+ union { /* DCPMAXP */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD DEVSEL:4; /* DEVSEL */\r
+ _UWORD :5; /* */\r
+ _UWORD MXPS:7; /* MXPS */\r
+ } BIT; /* */\r
+ } DCPMAXP; /* */\r
+ union { /* DCPCTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ _UWORD SUREQ:1; /* SUREQ */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD SUREQCLR:1; /* SUREQCLR */\r
+ _UWORD :2; /* */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD PINGE:1; /* PINGE */\r
+ _UWORD :1; /* */\r
+ _UWORD CCPL:1; /* CCPL */\r
+ _UWORD PID:2; /* PID */\r
+ } BIT; /* */\r
+ } DCPCTR; /* */\r
+ _UBYTE wk8[2]; /* */\r
+ union { /* PIPESEL */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :12; /* */\r
+ _UWORD PIPESEL:4; /* PIPESEL */\r
+ } BIT; /* */\r
+ } PIPESEL; /* */\r
+ _UBYTE wk9[2]; /* */\r
+ union { /* PIPECFG */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD TYPE:2; /* TYPE */\r
+ _UWORD :3; /* */\r
+ _UWORD BFRE:1; /* BFRE */\r
+ _UWORD DBLB:1; /* DBLB */\r
+ _UWORD CNTMD:1; /* CNTMD */\r
+ _UWORD SHTNAK:1; /* SHTNAK */\r
+ _UWORD :2; /* */\r
+ _UWORD DIR:1; /* DIR */\r
+ _UWORD EPNUM:4; /* EPNUM */\r
+ } BIT; /* */\r
+ } PIPECFG; /* */\r
+ union { /* PIPEBUF */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD BUFSIZE:5; /* BUFSIZE */\r
+ _UWORD :3; /* */\r
+ _UWORD BUFNMB:7; /* BUFNMB */\r
+ } BIT; /* */\r
+ } PIPEBUF; /* */\r
+ union { /* PIPEMAXP */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD DEVSEL:4; /* DEVSEL */\r
+ _UWORD :1; /* */\r
+ _UWORD MXPS:11; /* MXPS */\r
+ } BIT; /* */\r
+ } PIPEMAXP; /* */\r
+ union { /* PIPEPERI */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD IFIS:1; /* IFIS */\r
+ _UWORD :9; /* */\r
+ _UWORD IITV:3; /* IITV */\r
+ } BIT; /* */\r
+ } PIPEPERI; /* */\r
+ union { /* PIPE1CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD :1; /* */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD :3; /* */\r
+ _UWORD PID:2; /* PID */\r
+ } BIT; /* */\r
+ } PIPE1CTR; /* */\r
+ union { /* PIPE2CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD :1; /* */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD :3; /* */\r
+ _UWORD PID:2; /* PID */\r
+ } BIT; /* */\r
+ } PIPE2CTR; /* */\r
+ union { /* PIPE3CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD :1; /* */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD :3; /* */\r
+ _UWORD PID:2; /* PID */\r
+ } BIT; /* */\r
+ } PIPE3CTR; /* */\r
+ union { /* PIPE4CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD :1; /* */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD :3; /* */\r
+ _UWORD PID:2; /* PID */\r
+ } BIT; /* */\r
+ } PIPE4CTR; /* */\r
+ union { /* PIPE5CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD :1; /* */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD :3; /* */\r
+ _UWORD PID:2; /* PID */\r
+ } BIT; /* */\r
+ } PIPE5CTR; /* */\r
+ union { /* PIPE6CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ _UWORD :1; /* */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD :2; /* */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD :3; /* */\r
+ _UWORD PID:2; /* PID */\r
+ } BIT; /* */\r
+ } PIPE6CTR; /* */\r
+ union { /* PIPE7CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ _UWORD :1; /* */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD :2; /* */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD :3; /* */\r
+ _UWORD PID:2; /* PID */\r
+ } BIT; /* */\r
+ } PIPE7CTR; /* */\r
+ union { /* PIPE8CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ _UWORD :1; /* */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD :2; /* */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD :3; /* */\r
+ _UWORD PID:2; /* PID */\r
+ } BIT; /* */\r
+ } PIPE8CTR; /* */\r
+ union { /* PIPE9CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ _UWORD :1; /* */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD :2; /* */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD :3; /* */\r
+ _UWORD PID:2; /* PID */\r
+ } BIT; /* */\r
+ } PIPE9CTR; /* */\r
+ _UBYTE wk10[14]; /* */\r
+ union { /* PIPE1TRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } PIPE1TRE; /* */\r
+ _UWORD PIPE1TRN; /* PIPE1TRN */\r
+ union { /* PIPE2TRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } PIPE2TRE; /* */\r
+ _UWORD PIPE2TRN; /* PIPE2TRN */\r
+ union { /* PIPE3TRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } PIPE3TRE; /* */\r
+ _UWORD PIPE3TRN; /* PIPE3TRN */\r
+ union { /* PIPE4TRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } PIPE4TRE; /* */\r
+ _UWORD PIPE4TRN; /* PIPE4TRN */\r
+ union { /* PIPE5TRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } PIPE5TRE; /* */\r
+ _UWORD PIPE5TRN; /* PIPE5TRN */\r
+ _UBYTE wk11[44]; /* */\r
+ union { /* DEVADD0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } DEVADD0; /* */\r
+ union { /* DEVADD1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } DEVADD1; /* */\r
+ union { /* DEVADD2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } DEVADD2; /* */\r
+ union { /* DEVADD3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } DEVADD3; /* */\r
+ union { /* DEVADD4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } DEVADD4; /* */\r
+ union { /* DEVADD5 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } DEVADD5; /* */\r
+ union { /* DEVADD6 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } DEVADD6; /* */\r
+ union { /* DEVADD7 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } DEVADD7; /* */\r
+ union { /* DEVADD8 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } DEVADD8; /* */\r
+ union { /* DEVADD9 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } DEVADD9; /* */\r
+ union { /* DEVADDA */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } DEVADDA; /* */\r
+}; /* */\r
+ #endif\r
+struct st_vdc4 { /* struct VDC4 */\r
+ union { /* INP_UPDATE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD INP_EXT_UPDATE:1; /* INP_EXT_UPDATE */\r
+ _UDWORD :3; /* */\r
+ _UDWORD INP_IMG_UPDATE:1; /* INP_IMG_UPDATE */\r
+ } BIT; /* */\r
+ } INP_UPDATE; /* */\r
+ union { /* INP_SEL_CNT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :11; /* */\r
+ _UWORD INP_SEL:1; /* INP_SEL */\r
+ _UWORD :4; /* */\r
+ _UWORD :1; /* */\r
+ _UWORD INP_FORMAT:3; /* INP_FORMAT */\r
+ _UWORD :3; /* */\r
+ _UWORD INP_PXD_EDGE:1; /* INP_PXD_EDGE */\r
+ _UWORD :3; /* */\r
+ _UWORD INP_VS_EDGE:1; /* INP_VS_EDGE */\r
+ _UWORD :3; /* */\r
+ _UWORD INP_HS_EDGE:1; /* INP_HS_EDGE */\r
+ } BIT; /* */\r
+ } INP_SEL_CNT; /* */\r
+ union { /* INP_EXT_SYNC_CNT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD INP_ENDIAN_ON:1; /* INP_ENDIAN_ON */\r
+ _UWORD :3; /* */\r
+ _UWORD INP_SWAP_ON:1; /* INP_SWAP_ON */\r
+ _UWORD :3; /* */\r
+ _UWORD INP_VS_INV:1; /* INP_VS_INV */\r
+ _UWORD :3; /* */\r
+ _UWORD INP_HS_INV:1; /* INP_HS_INV */\r
+ _UWORD :7; /* */\r
+ _UWORD INP_H_EDGE_SEL:1; /* INP_H_EDGE_SEL */\r
+ _UWORD :3; /* */\r
+ _UWORD INP_F525_625:1; /* INP_F525_625 */\r
+ _UWORD :2; /* */\r
+ _UWORD INP_H_POS:2; /* INP_H_POS */\r
+ } BIT; /* */\r
+ } INP_EXT_SYNC_CNT; /* */\r
+ union { /* INP_VSYNC_PH_ADJ */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD INP_FH50:10; /* INP_FH50 */\r
+ _UWORD :6; /* */\r
+ _UWORD INP_FH25:10; /* INP_FH25 */\r
+ } BIT; /* */\r
+ } INP_VSYNC_PH_ADJ; /* */\r
+ union { /* INP_DLY_ADJ */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD INP_VS_DLY_L:3; /* INP_VS_DLY_L */\r
+ _UWORD INP_FLD_DLY:8; /* INP_FLD_DLY */\r
+ _UWORD INP_VS_DLY:8; /* INP_VS_DLY */\r
+ _UWORD INP_HS_DLY:8; /* INP_HS_DLY */\r
+ } BIT; /* */\r
+ } INP_DLY_ADJ; /* */\r
+ _UBYTE wk0[108]; /* */\r
+ union { /* IMGCNT_UPDATE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD IMGCNT_VEN:1; /* IMGCNT_VEN */\r
+ } BIT; /* */\r
+ } IMGCNT_UPDATE; /* */\r
+ union { /* IMGCNT_NR_CNT0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :11; /* */\r
+ _UWORD NR1D_MD:1; /* NR1D_MD */\r
+ _UWORD :3; /* */\r
+ _UWORD NR1D_ON:1; /* NR1D_ON */\r
+ _UWORD :1; /* */\r
+ _UWORD NR1D_Y_TH:7; /* NR1D_Y_TH */\r
+ _UWORD :2; /* */\r
+ _UWORD NR1D_Y_TAP:2; /* NR1D_Y_TAP */\r
+ _UWORD :2; /* */\r
+ _UWORD NR1D_Y_GAIN:2; /* NR1D_Y_GAIN */\r
+ } BIT; /* */\r
+ } IMGCNT_NR_CNT0; /* */\r
+ union { /* IMGCNT_NR_CNT1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD NR1D_CB_TH:7; /* NR1D_CB_TH */\r
+ _UWORD :2; /* */\r
+ _UWORD NR1D_CB_TAP:2; /* NR1D_CB_TAP */\r
+ _UWORD :2; /* */\r
+ _UWORD NR1D_CB_GAIN:2; /* NR1D_CB_GAIN */\r
+ _UWORD :1; /* */\r
+ _UWORD NR1D_CR_TH:7; /* NR1D_CR_TH */\r
+ _UWORD :2; /* */\r
+ _UWORD NR1D_CR_TAP:2; /* NR1D_CR_TAP */\r
+ _UWORD :2; /* */\r
+ _UWORD NR1D_CR_GAIN:2; /* NR1D_CR_GAIN */\r
+ } BIT; /* */\r
+ } IMGCNT_NR_CNT1; /* */\r
+ _UBYTE wk1[20]; /* */\r
+ union { /* IMGCNT_MTX_MODE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :30; /* */\r
+ _UDWORD IMGCNT_MTX_MD:2; /* IMGCNT_MTX_MD */\r
+ } BIT; /* */\r
+ } IMGCNT_MTX_MODE; /* */\r
+ union { /* IMGCNT_MTX_YG_ADJ0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD IMGCNT_MTX_YG:8; /* IMGCNT_MTX_YG */\r
+ _UWORD :5; /* */\r
+ _UWORD IMGCNT_MTX_GG:11; /* IMGCNT_MTX_GG */\r
+ } BIT; /* */\r
+ } IMGCNT_MTX_YG_ADJ0; /* */\r
+ union { /* IMGCNT_MTX_YG_ADJ1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD IMGCNT_MTX_GB:11; /* IMGCNT_MTX_GB */\r
+ _UWORD :5; /* */\r
+ _UWORD IMGCNT_MTX_GR:11; /* IMGCNT_MTX_GR */\r
+ } BIT; /* */\r
+ } IMGCNT_MTX_YG_ADJ1; /* */\r
+ union { /* IMGCNT_MTX_CBB_ADJ0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD IMGCNT_MTX_B:8; /* IMGCNT_MTX_B */\r
+ _UWORD :5; /* */\r
+ _UWORD IMGCNT_MTX_BG:11; /* IMGCNT_MTX_BG */\r
+ } BIT; /* */\r
+ } IMGCNT_MTX_CBB_ADJ0; /* */\r
+ union { /* IMGCNT_MTX_CBB_ADJ1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD IMGCNT_MTX_BB:11; /* IMGCNT_MTX_BB */\r
+ _UWORD :5; /* */\r
+ _UWORD IMGCNT_MTX_BR:11; /* IMGCNT_MTX_BR */\r
+ } BIT; /* */\r
+ } IMGCNT_MTX_CBB_ADJ1; /* */\r
+ union { /* IMGCNT_MTX_CRR_ADJ0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD IMGCNT_MTX_R:8; /* IMGCNT_MTX_R */\r
+ _UWORD :5; /* */\r
+ _UWORD IMGCNT_MTX_RG:11; /* IMGCNT_MTX_RG */\r
+ } BIT; /* */\r
+ } IMGCNT_MTX_CRR_ADJ0; /* */\r
+ union { /* IMGCNT_MTX_CRR_ADJ1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD IMGCNT_MTX_RB:11; /* IMGCNT_MTX_RB */\r
+ _UWORD :5; /* */\r
+ _UWORD IMGCNT_MTX_RR:11; /* IMGCNT_MTX_RR */\r
+ } BIT; /* */\r
+ } IMGCNT_MTX_CRR_ADJ1; /* */\r
+ _UBYTE wk2[68]; /* */\r
+ union { /* SCL0_UPDATE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :18; /* */\r
+ _UDWORD SCL0_VEN_D:1; /* SCL0_VEN_D */\r
+ _UDWORD SCL0_VEN_C:1; /* SCL0_VEN_C */\r
+ _UDWORD :3; /* */\r
+ _UDWORD SCL0_UPDATE:1; /* SCL0_UPDATE */\r
+ _UDWORD :3; /* */\r
+ _UDWORD SCL0_VEN_B:1; /* SCL0_VEN_B */\r
+ _UDWORD :3; /* */\r
+ _UDWORD SCL0_VEN_A:1; /* SCL0_VEN_A */\r
+ } BIT; /* */\r
+ } SCL0_UPDATE; /* */\r
+ union { /* SCL0_FRC1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD RES_VMASK:16; /* RES_VMASK */\r
+ _UWORD :15; /* */\r
+ _UWORD RES_VMASK_ON:1; /* RES_VMASK_ON */\r
+ } BIT; /* */\r
+ } SCL0_FRC1; /* */\r
+ union { /* SCL0_FRC2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD RES_VLACK:16; /* RES_VLACK */\r
+ _UWORD :15; /* */\r
+ _UWORD RES_VLACK_ON:1; /* RES_VLACK_ON */\r
+ } BIT; /* */\r
+ } SCL0_FRC2; /* */\r
+ union { /* SCL0_FRC3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD RES_VS_SEL:1; /* RES_VS_SEL */\r
+ } BIT; /* */\r
+ } SCL0_FRC3; /* */\r
+ union { /* SCL0_FRC4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_FV:11; /* RES_FV */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_FH:11; /* RES_FH */\r
+ } BIT; /* */\r
+ } SCL0_FRC4; /* */\r
+ union { /* SCL0_FRC5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :23; /* */\r
+ _UDWORD RES_FLD_DLY_SEL:1; /* RES_FLD_DLY_SEL */\r
+ _UDWORD RES_VSDLY:8; /* RES_VSDLY */\r
+ } BIT; /* */\r
+ } SCL0_FRC5; /* */\r
+ union { /* SCL0_FRC6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_F_VS:11; /* RES_F_VS */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_F_VW:11; /* RES_F_VW */\r
+ } BIT; /* */\r
+ } SCL0_FRC6; /* */\r
+ union { /* SCL0_FRC7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_F_HS:11; /* RES_F_HS */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_F_HW:11; /* RES_F_HW */\r
+ } BIT; /* */\r
+ } SCL0_FRC7; /* */\r
+ _UBYTE wk3[4]; /* */\r
+ union { /* SCL0_FRC9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD RES_QVLOCK:1; /* RES_QVLOCK */\r
+ _UDWORD :3; /* */\r
+ _UDWORD RES_QVLACK:1; /* RES_QVLACK */\r
+ } BIT; /* */\r
+ } SCL0_FRC9; /* */\r
+ _UBYTE wk4[4]; /* */\r
+ union { /* SCL0_DS1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD RES_DS_V_ON:1; /* RES_DS_V_ON */\r
+ _UDWORD :3; /* */\r
+ _UDWORD RES_DS_H_ON:1; /* RES_DS_H_ON */\r
+ } BIT; /* */\r
+ } SCL0_DS1; /* */\r
+ union { /* SCL0_DS2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_VS:11; /* RES_VS */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_VW:11; /* RES_VW */\r
+ } BIT; /* */\r
+ } SCL0_DS2; /* */\r
+ union { /* SCL0_DS3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_HS:11; /* RES_HS */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_HW:11; /* RES_HW */\r
+ } BIT; /* */\r
+ } SCL0_DS3; /* */\r
+ union { /* SCL0_DS4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :2; /* */\r
+ _UWORD RES_PFIL_SEL:1; /* RES_PFIL_SEL */\r
+ _UWORD RES_DS_H_INTERPOTYP:1; /* RES_DS_H_INTERPOTYP */\r
+ _UWORD :12; /* */\r
+ _UWORD RES_DS_H_RATIO:16; /* RES_DS_H_RATIO */\r
+ } BIT; /* */\r
+ } SCL0_DS4; /* */\r
+ union { /* SCL0_DS5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD RES_V_INTERPOTYP:1; /* RES_V_INTERPOTYP */\r
+ _UWORD RES_TOP_INIPHASE:12; /* RES_TOP_INIPHASE */\r
+ _UWORD :4; /* */\r
+ _UWORD RES_BTM_INIPHASE:12; /* RES_BTM_INIPHASE */\r
+ } BIT; /* */\r
+ } SCL0_DS5; /* */\r
+ union { /* SCL0_DS6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :16; /* */\r
+ _UWORD RES_V_RATIO:16; /* RES_V_RATIO */\r
+ } BIT; /* */\r
+ } SCL0_DS6; /* */\r
+ union { /* SCL0_DS7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_OUT_VW:11; /* RES_OUT_VW */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_OUT_HW:11; /* RES_OUT_HW */\r
+ } BIT; /* */\r
+ } SCL0_DS7; /* */\r
+ union { /* SCL0_US1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD RES_US_V_ON:1; /* RES_US_V_ON */\r
+ _UDWORD :3; /* */\r
+ _UDWORD RES_US_H_ON:1; /* RES_US_H_ON */\r
+ } BIT; /* */\r
+ } SCL0_US1; /* */\r
+ union { /* SCL0_US2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_P_VS:11; /* RES_P_VS */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_P_VW:11; /* RES_P_VW */\r
+ } BIT; /* */\r
+ } SCL0_US2; /* */\r
+ union { /* SCL0_US3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_P_HS:11; /* RES_P_HS */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_P_HW:11; /* RES_P_HW */\r
+ } BIT; /* */\r
+ } SCL0_US3; /* */\r
+ union { /* SCL0_US4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_IN_VW:11; /* RES_IN_VW */\r
+ _UWORD :5; /* */\r
+ _UWORD RES_IN_HW:11; /* RES_IN_HW */\r
+ } BIT; /* */\r
+ } SCL0_US4; /* */\r
+ union { /* SCL0_US5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :16; /* */\r
+ _UWORD RES_US_H_RATIO:16; /* RES_US_H_RATIO */\r
+ } BIT; /* */\r
+ } SCL0_US5; /* */\r
+ union { /* SCL0_US6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD RES_US_H_INTERPOTYP:1; /* RES_US_H_INTERPOTYP */\r
+ _UWORD RES_US_HT_INIPHASE:12; /* RES_US_HT_INIPHASE */\r
+ _UWORD :4; /* */\r
+ _UWORD RES_US_HB_INIPHASE:12; /* RES_US_HB_INIPHASE */\r
+ } BIT; /* */\r
+ } SCL0_US6; /* */\r
+ union { /* SCL0_US7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :16; /* */\r
+ _UWORD RES_HCUT:8; /* RES_HCUT */\r
+ _UWORD RES_VCUT:8; /* RES_VCUT */\r
+ } BIT; /* */\r
+ } SCL0_US7; /* */\r
+ union { /* SCL0_US8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD RES_IBUS_SYNC_SEL:1; /* RES_IBUS_SYNC_SEL */\r
+ _UDWORD :3; /* */\r
+ _UDWORD RES_DISP_ON:1; /* RES_DISP_ON */\r
+ } BIT; /* */\r
+ } SCL0_US8; /* */\r
+ _UBYTE wk5[4]; /* */\r
+ union { /* SCL0_OVR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD RES_BK_COL_R:8; /* RES_BK_COL_R */\r
+ _UWORD RES_BK_COL_G:8; /* RES_BK_COL_G */\r
+ _UWORD RES_BK_COL_B:8; /* RES_BK_COL_B */\r
+ } BIT; /* */\r
+ } SCL0_OVR1; /* */\r
+ _UBYTE wk6[16]; /* */\r
+ union { /* SCL1_UPDATE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD SCL1_VEN_B:1; /* SCL1_VEN_B */\r
+ _UDWORD :3; /* */\r
+ _UDWORD SCL1_VEN_A:1; /* SCL1_VEN_A */\r
+ } BIT; /* */\r
+ } SCL1_UPDATE; /* */\r
+ _UBYTE wk7[4]; /* */\r
+ union { /* SCL1_WR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :25; /* */\r
+ _UDWORD RES_DS_WR_MD:3; /* RES_DS_WR_MD */\r
+ _UDWORD RES_MD:2; /* RES_MD */\r
+ _UDWORD RES_LOOP:1; /* RES_LOOP */\r
+ _UDWORD RES_BST_MD:1; /* RES_BST_MD */\r
+ } BIT; /* */\r
+ } SCL1_WR1; /* */\r
+ union { /* SCL1_WR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD RES_BASE:32; /* RES_BASE */\r
+ } BIT; /* */\r
+ } SCL1_WR2; /* */\r
+ union { /* SCL1_WR3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD RES_LN_OFF:15; /* RES_LN_OFF */\r
+ _UWORD :6; /* */\r
+ _UWORD RES_FLM_NUM:10; /* RES_FLM_NUM */\r
+ } BIT; /* */\r
+ } SCL1_WR3; /* */\r
+ union { /* SCL1_WR4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :9; /* */\r
+ _UDWORD RES_FLM_OFF:23; /* RES_FLM_OFF */\r
+ } BIT; /* */\r
+ } SCL1_WR4; /* */\r
+ _UBYTE wk8[4]; /* */\r
+ union { /* SCL1_WR5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :19; /* */\r
+ _UDWORD RES_INTER:1; /* RES_INTER */\r
+ _UDWORD :2; /* */\r
+ _UDWORD RES_FS_RATE:2; /* RES_FS_RATE */\r
+ _UDWORD :3; /* */\r
+ _UDWORD RES_FLD_SEL:1; /* RES_FLD_SEL */\r
+ _UDWORD :3; /* */\r
+ _UDWORD RES_WENB:1; /* RES_WENB */\r
+ } BIT; /* */\r
+ } SCL1_WR5; /* */\r
+ union { /* SCL1_WR6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD RES_DTH_ON:1; /* RES_DTH_ON */\r
+ _UDWORD :3; /* */\r
+ _UDWORD RES_BITDEC_ON:1; /* RES_BITDEC_ON */\r
+ } BIT; /* */\r
+ } SCL1_WR6; /* */\r
+ union { /* SCL1_WR7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :15; /* */\r
+ _UWORD RES_OVERFLOW:1; /* RES_OVERFLOW */\r
+ _UWORD :6; /* */\r
+ _UWORD RES_FLM_CNT:10; /* RES_FLM_CNT */\r
+ } BIT; /* */\r
+ } SCL1_WR7; /* */\r
+ _UBYTE wk9[88]; /* */\r
+ union { /* GR1_UPDATE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD GR1_P_VEN:1; /* GR1_P_VEN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD GR1_IBUS_VEN:1; /* GR1_IBUS_VEN */\r
+ } BIT; /* */\r
+ } GR1_UPDATE; /* */\r
+ union { /* GR1_FLM_RD */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD GR1_R_ENB:1; /* GR1_R_ENB */\r
+ } BIT; /* */\r
+ } GR1_FLM_RD; /* */\r
+ union { /* GR1_FLM1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :15; /* */\r
+ _UWORD GR1_LN_OFF_DIR:1; /* GR1_LN_OFF_DIR */\r
+ _UWORD :6; /* */\r
+ _UWORD GR1_FLM_SEL:2; /* GR1_FLM_SEL */\r
+ _UWORD :3; /* */\r
+ _UWORD GR1_IMR_FLM_INV:1; /* GR1_IMR_FLM_INV */\r
+ _UWORD :3; /* */\r
+ _UWORD GR1_BST_MD:1; /* GR1_BST_MD */\r
+ } BIT; /* */\r
+ } GR1_FLM1; /* */\r
+ union { /* GR1_FLM2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD GR1_BASE:32; /* GR1_BASE */\r
+ } BIT; /* */\r
+ } GR1_FLM2; /* */\r
+ union { /* GR1_FLM3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD GR1_LN_OFF:15; /* GR1_LN_OFF */\r
+ _UWORD :6; /* */\r
+ _UWORD GR1_FLM_NUM:10; /* GR1_FLM_NUM */\r
+ } BIT; /* */\r
+ } GR1_FLM3; /* */\r
+ union { /* GR1_FLM4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :9; /* */\r
+ _UDWORD GR1_FLM_OFF:23; /* GR1_FLM_OFF */\r
+ } BIT; /* */\r
+ } GR1_FLM4; /* */\r
+ union { /* GR1_FLM5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD GR1_FLM_LNUM:10; /* GR1_FLM_LNUM */\r
+ _UWORD :6; /* */\r
+ _UWORD GR1_FLM_LOOP:10; /* GR1_FLM_LOOP */\r
+ } BIT; /* */\r
+ } GR1_FLM5; /* */\r
+ union { /* GR1_FLM6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GR1_FORMAT:4; /* GR1_FORMAT */\r
+ _UWORD :2; /* */\r
+ _UWORD GR1_HW:10; /* GR1_HW */\r
+ _UWORD GR1_YCC_SWAP:3; /* GR1_YCC_SWAP */\r
+ _UWORD GR1_ENDIAN_ON:1; /* GR1_ENDIAN_ON */\r
+ _UWORD :3; /* */\r
+ _UWORD GR1_CNV444_MD:1; /* GR1_CNV444_MD */\r
+ _UWORD :2; /* */\r
+ _UWORD GR1_STA_POS:6; /* GR1_STA_POS */\r
+ } BIT; /* */\r
+ } GR1_FLM6; /* */\r
+ union { /* GR1_AB1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :16; /* */\r
+ _UWORD :11; /* */\r
+ _UWORD GR1_GRC_DISP_ON:1; /* GR1_GRC_DISP_ON */\r
+ _UWORD :2; /* */\r
+ _UWORD GR1_DISP_SEL:2; /* GR1_DISP_SEL */\r
+ } BIT; /* */\r
+ } GR1_AB1; /* */\r
+ union { /* GR1_AB2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GR1_GRC_VS:11; /* GR1_GRC_VS */\r
+ _UWORD :5; /* */\r
+ _UWORD GR1_GRC_VW:11; /* GR1_GRC_VW */\r
+ } BIT; /* */\r
+ } GR1_AB2; /* */\r
+ union { /* GR1_AB3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GR1_GRC_HS:11; /* GR1_GRC_HS */\r
+ _UWORD :5; /* */\r
+ _UWORD GR1_GRC_HW:11; /* GR1_GRC_HW */\r
+ } BIT; /* */\r
+ } GR1_AB3; /* */\r
+ _UBYTE wk10_0[12]; /* */\r
+ union { /* GR1_AB7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :16; /* */\r
+ _UWORD :15; /* */\r
+ _UWORD GR1_CK_ON:1; /* GR1_CK_ON */\r
+ } BIT; /* */\r
+ } GR1_AB7; /* */\r
+ union { /* GR1_AB8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GR1_CK_KCLUT:8; /* GR1_CK_KCLUT */\r
+ _UWORD GR1_CK_KG:8; /* GR1_CK_KG */\r
+ _UWORD GR1_CK_KB:8; /* GR1_CK_KB */\r
+ _UWORD GR1_CK_KR:8; /* GR1_CK_KR */\r
+ } BIT; /* */\r
+ } GR1_AB8; /* */\r
+ union { /* GR1_AB9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GR1_CK_A:8; /* GR1_CK_A */\r
+ _UWORD GR1_CK_G:8; /* GR1_CK_G */\r
+ _UWORD GR1_CK_B:8; /* GR1_CK_B */\r
+ _UWORD GR1_CK_R:8; /* GR1_CK_R */\r
+ } BIT; /* */\r
+ } GR1_AB9; /* */\r
+ union { /* GR1_AB10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GR1_A0:8; /* GR1_A0 */\r
+ _UWORD GR1_G0:8; /* GR1_G0 */\r
+ _UWORD GR1_B0:8; /* GR1_B0 */\r
+ _UWORD GR1_R0:8; /* GR1_R0 */\r
+ } BIT; /* */\r
+ } GR1_AB10; /* */\r
+ union { /* GR1_AB11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GR1_A1:8; /* GR1_A1 */\r
+ _UWORD GR1_G1:8; /* GR1_G1 */\r
+ _UWORD GR1_B1:8; /* GR1_B1 */\r
+ _UWORD GR1_R1:8; /* GR1_R1 */\r
+ } BIT; /* */\r
+ } GR1_AB11; /* */\r
+ union { /* GR1_BASE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD GR1_BASE_G:8; /* GR1_BASE_G */\r
+ _UWORD GR1_BASE_B:8; /* GR1_BASE_B */\r
+ _UWORD GR1_BASE_R:8; /* GR1_BASE_R */\r
+ } BIT; /* */\r
+ } GR1_BASE; /* */\r
+ union { /* GR1_CLUT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :15; /* */\r
+ _UWORD GR1_CLT_SEL:1; /* GR1_CLT_SEL */\r
+ _UWORD :16; /* */\r
+ } BIT; /* */\r
+ } GR1_CLUT; /* */\r
+ _UBYTE wk10[44]; /* */\r
+ union { /* ADJ_UPDATE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD ADJ_VEN:1; /* ADJ_VEN */\r
+ } BIT; /* */\r
+ } ADJ_UPDATE; /* */\r
+ union { /* ADJ_BKSTR_SET */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :7; /* */\r
+ _UWORD BKSTR_ON:1; /* BKSTR_ON */\r
+ _UWORD BKSTR_ST:4; /* BKSTR_ST */\r
+ _UWORD BKSTR_D:4; /* BKSTR_D */\r
+ _UWORD :3; /* */\r
+ _UWORD BKSTR_T1:5; /* BKSTR_T1 */\r
+ _UWORD :3; /* */\r
+ _UWORD BKSTR_T2:5; /* BKSTR_T2 */\r
+ } BIT; /* */\r
+ } ADJ_BKSTR_SET; /* */\r
+ union { /* ADJ_ENH_TIM1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD ENH_MD:1; /* ENH_MD */\r
+ _UDWORD :3; /* */\r
+ _UDWORD ENH_DISP_ON:1; /* ENH_DISP_ON */\r
+ } BIT; /* */\r
+ } ADJ_ENH_TIM1; /* */\r
+ union { /* ADJ_ENH_TIM2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD ENH_VS:11; /* ENH_VS */\r
+ _UWORD :5; /* */\r
+ _UWORD ENH_VW:11; /* ENH_VW */\r
+ } BIT; /* */\r
+ } ADJ_ENH_TIM2; /* */\r
+ union { /* ADJ_ENH_TIM3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD ENH_HS:11; /* ENH_HS */\r
+ _UWORD :5; /* */\r
+ _UWORD ENH_HW:11; /* ENH_HW */\r
+ } BIT; /* */\r
+ } ADJ_ENH_TIM3; /* */\r
+ union { /* ADJ_ENH_SHP1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :15; /* */\r
+ _UWORD SHP_H_ON:1; /* SHP_H_ON */\r
+ _UWORD :9; /* */\r
+ _UWORD SHP_H1_CORE:7; /* SHP_H1_CORE */\r
+ } BIT; /* */\r
+ } ADJ_ENH_SHP1; /* */\r
+ union { /* ADJ_ENH_SHP2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD SHP_H1_CLIP_O:8; /* SHP_H1_CLIP_O */\r
+ _UWORD SHP_H1_CLIP_U:8; /* SHP_H1_CLIP_U */\r
+ _UWORD SHP_H1_GAIN_O:8; /* SHP_H1_GAIN_O */\r
+ _UWORD SHP_H1_GAIN_U:8; /* SHP_H1_GAIN_U */\r
+ } BIT; /* */\r
+ } ADJ_ENH_SHP2; /* */\r
+ union { /* ADJ_ENH_SHP3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :15; /* */\r
+ _UWORD SHP_H2_LPF_SEL:1; /* SHP_H2_LPF_SEL */\r
+ _UWORD :9; /* */\r
+ _UWORD SHP_H2_CORE:7; /* SHP_H2_CORE */\r
+ } BIT; /* */\r
+ } ADJ_ENH_SHP3; /* */\r
+ union { /* ADJ_ENH_SHP4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD SHP_H2_CLIP_O:8; /* SHP_H2_CLIP_O */\r
+ _UWORD SHP_H2_CLIP_U:8; /* SHP_H2_CLIP_U */\r
+ _UWORD SHP_H2_GAIN_O:8; /* SHP_H2_GAIN_O */\r
+ _UWORD SHP_H2_GAIN_U:8; /* SHP_H2_GAIN_U */\r
+ } BIT; /* */\r
+ } ADJ_ENH_SHP4; /* */\r
+ union { /* ADJ_ENH_SHP5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :25; /* */\r
+ _UDWORD SHP_H3_CORE:7; /* SHP_H3_CORE */\r
+ } BIT; /* */\r
+ } ADJ_ENH_SHP5; /* */\r
+ union { /* ADJ_ENH_SHP6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD SHP_H3_CLIP_O:8; /* SHP_H3_CLIP_O */\r
+ _UWORD SHP_H3_CLIP_U:8; /* SHP_H3_CLIP_U */\r
+ _UWORD SHP_H3_GAIN_O:8; /* SHP_H3_GAIN_O */\r
+ _UWORD SHP_H3_GAIN_U:8; /* SHP_H3_GAIN_U */\r
+ } BIT; /* */\r
+ } ADJ_ENH_SHP6; /* */\r
+ union { /* ADJ_ENH_LTI1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD LTI_H_ON:1; /* LTI_H_ON */\r
+ _UWORD :6; /* */\r
+ _UWORD LTI_H2_LPF_SEL:1; /* LTI_H2_LPF_SEL */\r
+ _UWORD LTI_H2_INC_ZERO:8; /* LTI_H2_INC_ZERO */\r
+ _UWORD LTI_H2_GAIN:8; /* LTI_H2_GAIN */\r
+ _UWORD LTI_H2_CORE:8; /* LTI_H2_CORE */\r
+ } BIT; /* */\r
+ } ADJ_ENH_LTI1; /* */\r
+ union { /* ADJ_ENH_LTI2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :7; /* */\r
+ _UWORD LTI_H4_MEDIAN_TAP_SEL:1; /* LTI_H4_MEDIAN_TAP_SEL */\r
+ _UWORD LTI_H4_INC_ZERO:8; /* LTI_H4_INC_ZERO */\r
+ _UWORD LTI_H4_GAIN:8; /* LTI_H4_GAIN */\r
+ _UWORD LTI_H4_CORE:8; /* LTI_H4_CORE */\r
+ } BIT; /* */\r
+ } ADJ_ENH_LTI2; /* */\r
+ union { /* ADJ_MTX_MODE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :30; /* */\r
+ _UDWORD ADJ_MTX_MD:2; /* ADJ_MTX_MD */\r
+ } BIT; /* */\r
+ } ADJ_MTX_MODE; /* */\r
+ union { /* ADJ_MTX_YG_ADJ0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD ADJ_MTX_YG:8; /* ADJ_MTX_YG */\r
+ _UWORD :5; /* */\r
+ _UWORD ADJ_MTX_GG:11; /* ADJ_MTX_GG */\r
+ } BIT; /* */\r
+ } ADJ_MTX_YG_ADJ0; /* */\r
+ union { /* ADJ_MTX_YG_ADJ1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD ADJ_MTX_GB:11; /* ADJ_MTX_GB */\r
+ _UWORD :5; /* */\r
+ _UWORD ADJ_MTX_GR:11; /* ADJ_MTX_GR */\r
+ } BIT; /* */\r
+ } ADJ_MTX_YG_ADJ1; /* */\r
+ union { /* ADJ_MTX_CBB_ADJ0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD ADJ_MTX_B:8; /* ADJ_MTX_B */\r
+ _UWORD :5; /* */\r
+ _UWORD ADJ_MTX_BG:11; /* ADJ_MTX_BG */\r
+ } BIT; /* */\r
+ } ADJ_MTX_CBB_ADJ0; /* */\r
+ union { /* ADJ_MTX_CBB_ADJ1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD ADJ_MTX_BB:11; /* ADJ_MTX_BB */\r
+ _UWORD :5; /* */\r
+ _UWORD ADJ_MTX_BR:11; /* ADJ_MTX_BR */\r
+ } BIT; /* */\r
+ } ADJ_MTX_CBB_ADJ1; /* */\r
+ union { /* ADJ_MTX_CRR_ADJ0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD ADJ_MTX_R:8; /* ADJ_MTX_R */\r
+ _UWORD :5; /* */\r
+ _UWORD ADJ_MTX_RG:11; /* ADJ_MTX_RG */\r
+ } BIT; /* */\r
+ } ADJ_MTX_CRR_ADJ0; /* */\r
+ union { /* ADJ_MTX_CRR_ADJ1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD ADJ_MTX_RB:11; /* ADJ_MTX_RB */\r
+ _UWORD :5; /* */\r
+ _UWORD ADJ_MTX_RR:11; /* ADJ_MTX_RR */\r
+ } BIT; /* */\r
+ } ADJ_MTX_CRR_ADJ1; /* */\r
+ _UBYTE wk11[48]; /* */\r
+ union { /* GR2_UPDATE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD GR2_P_VEN:1; /* GR2_P_VEN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD GR2_IBUS_VEN:1; /* GR2_IBUS_VEN */\r
+ } BIT; /* */\r
+ } GR2_UPDATE; /* */\r
+ union { /* GR2_FLM_RD */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD GR2_R_ENB:1; /* GR2_R_ENB */\r
+ } BIT; /* */\r
+ } GR2_FLM_RD; /* */\r
+ union { /* GR2_FLM1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :15; /* */\r
+ _UWORD GR2_LN_OFF_DIR:1; /* GR2_LN_OFF_DIR */\r
+ _UWORD :6; /* */\r
+ _UWORD GR2_FLM_SEL:2; /* GR2_FLM_SEL */\r
+ _UWORD :7; /* */\r
+ _UWORD GR2_BST_MD:1; /* GR2_BST_MD */\r
+ } BIT; /* */\r
+ } GR2_FLM1; /* */\r
+ union { /* GR2_FLM2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD GR2_BASE:32; /* GR2_BASE */\r
+ } BIT; /* */\r
+ } GR2_FLM2; /* */\r
+ union { /* GR2_FLM3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD GR2_LN_OFF:15; /* GR2_LN_OFF */\r
+ _UWORD :6; /* */\r
+ _UWORD GR2_FLM_NUM:10; /* GR2_FLM_NUM */\r
+ } BIT; /* */\r
+ } GR2_FLM3; /* */\r
+ union { /* GR2_FLM4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :9; /* */\r
+ _UDWORD GR2_FLM_OFF:23; /* GR2_FLM_OFF */\r
+ } BIT; /* */\r
+ } GR2_FLM4; /* */\r
+ union { /* GR2_FLM5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD GR2_FLM_LNUM:10; /* GR2_FLM_LNUM */\r
+ _UWORD :6; /* */\r
+ _UWORD GR2_FLM_LOOP:10; /* GR2_FLM_LOOP */\r
+ } BIT; /* */\r
+ } GR2_FLM5; /* */\r
+ union { /* GR2_FLM6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GR2_FORMAT:4; /* GR2_FORMAT */\r
+ _UWORD :2; /* */\r
+ _UWORD GR2_HW:10; /* GR2_HW */\r
+ _UWORD :3; /* */\r
+ _UWORD GR2_ENDIAN_ON:1; /* GR2_ENDIAN_ON */\r
+ _UWORD :6; /* */\r
+ _UWORD GR2_STA_POS:6; /* GR2_STA_POS */\r
+ } BIT; /* */\r
+ } GR2_FLM6; /* */\r
+ union { /* GR2_AB1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :19; /* */\r
+ _UDWORD GR2_ARC_ON:1; /* GR2_ARC_ON */\r
+ _UDWORD :3; /* */\r
+ _UDWORD GR2_ARC_DISP_ON:1; /* GR2_ARC_DISP_ON */\r
+ _UDWORD :3; /* */\r
+ _UDWORD GR2_GRC_DISP_ON:1; /* GR2_GRC_DISP_ON */\r
+ _UDWORD :2; /* */\r
+ _UDWORD GR2_DISP_SEL:2; /* GR2_DISP_SEL */\r
+ } BIT; /* */\r
+ } GR2_AB1; /* */\r
+ union { /* GR2_AB2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GR2_GRC_VS:11; /* GR2_GRC_VS */\r
+ _UWORD :5; /* */\r
+ _UWORD GR2_GRC_VW:11; /* GR2_GRC_VW */\r
+ } BIT; /* */\r
+ } GR2_AB2; /* */\r
+ union { /* GR2_AB3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GR2_GRC_HS:11; /* GR2_GRC_HS */\r
+ _UWORD :5; /* */\r
+ _UWORD GR2_GRC_HW:11; /* GR2_GRC_HW */\r
+ } BIT; /* */\r
+ } GR2_AB3; /* */\r
+ union { /* GR2_AB4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GR2_ARC_VS:11; /* GR2_ARC_VS */\r
+ _UWORD :5; /* */\r
+ _UWORD GR2_ARC_VW:11; /* GR2_ARC_VW */\r
+ } BIT; /* */\r
+ } GR2_AB4; /* */\r
+ union { /* GR2_AB5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GR2_ARC_HS:11; /* GR2_ARC_HS */\r
+ _UWORD :5; /* */\r
+ _UWORD GR2_ARC_HW:11; /* GR2_ARC_HW */\r
+ } BIT; /* */\r
+ } GR2_AB5; /* */\r
+ union { /* GR2_AB6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :7; /* */\r
+ _UWORD GR2_ARC_MODE:1; /* GR2_ARC_MODE */\r
+ _UWORD GR2_ARC_COEF:8; /* GR2_ARC_COEF */\r
+ _UWORD :8; /* */\r
+ _UWORD GR2_ARC_RATE:8; /* GR2_ARC_RATE */\r
+ } BIT; /* */\r
+ } GR2_AB6; /* */\r
+ union { /* GR2_AB7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD GR2_ARC_DEF:8; /* GR2_ARC_DEF */\r
+ _UWORD :15; /* */\r
+ _UWORD GR2_CK_ON:1; /* GR2_CK_ON */\r
+ } BIT; /* */\r
+ } GR2_AB7; /* */\r
+ union { /* GR2_AB8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GR2_CK_KCLUT:8; /* GR2_CK_KCLUT */\r
+ _UWORD GR2_CK_KG:8; /* GR2_CK_KG */\r
+ _UWORD GR2_CK_KB:8; /* GR2_CK_KB */\r
+ _UWORD GR2_CK_KR:8; /* GR2_CK_KR */\r
+ } BIT; /* */\r
+ } GR2_AB8; /* */\r
+ union { /* GR2_AB9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GR2_CK_A:8; /* GR2_CK_A */\r
+ _UWORD GR2_CK_G:8; /* GR2_CK_G */\r
+ _UWORD GR2_CK_B:8; /* GR2_CK_B */\r
+ _UWORD GR2_CK_R:8; /* GR2_CK_R */\r
+ } BIT; /* */\r
+ } GR2_AB9; /* */\r
+ union { /* GR2_AB10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GR2_A0:8; /* GR2_A0 */\r
+ _UWORD GR2_G0:8; /* GR2_G0 */\r
+ _UWORD GR2_B0:8; /* GR2_B0 */\r
+ _UWORD GR2_R0:8; /* GR2_R0 */\r
+ } BIT; /* */\r
+ } GR2_AB10; /* */\r
+ union { /* GR2_AB11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GR2_A1:8; /* GR2_A1 */\r
+ _UWORD GR2_G1:8; /* GR2_G1 */\r
+ _UWORD GR2_B1:8; /* GR2_B1 */\r
+ _UWORD GR2_R1:8; /* GR2_R1 */\r
+ } BIT; /* */\r
+ } GR2_AB11; /* */\r
+ union { /* GR2_BASE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD GR2_BASE_G:8; /* GR2_BASE_G */\r
+ _UWORD GR2_BASE_B:8; /* GR2_BASE_B */\r
+ _UWORD GR2_BASE_R:8; /* GR2_BASE_R */\r
+ } BIT; /* */\r
+ } GR2_BASE; /* */\r
+ union { /* GR2_CLUT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :15; /* */\r
+ _UWORD GR2_CLT_SEL:1; /* GR2_CLT_SEL */\r
+ _UWORD :16; /* */\r
+ } BIT; /* */\r
+ } GR2_CLUT; /* */\r
+ union { /* GR2_MON */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD GR2_ARC_ST:1; /* GR2_ARC_ST */\r
+ } BIT; /* */\r
+ } GR2_MON; /* */\r
+ _UBYTE wk12[40]; /* */\r
+ union { /* GR3_UPDATE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD GR3_P_VEN:1; /* GR3_P_VEN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD GR3_IBUS_VEN:1; /* GR3_IBUS_VEN */\r
+ } BIT; /* */\r
+ } GR3_UPDATE; /* */\r
+ union { /* GR3_FLM_RD */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD GR3_R_ENB:1; /* GR3_R_ENB */\r
+ } BIT; /* */\r
+ } GR3_FLM_RD; /* */\r
+ union { /* GR3_FLM1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :15; /* */\r
+ _UWORD GR3_LN_OFF_DIR:1; /* GR3_LN_OFF_DIR */\r
+ _UWORD :6; /* */\r
+ _UWORD GR3_FLM_SEL:2; /* GR3_FLM_SEL */\r
+ _UWORD :7; /* */\r
+ _UWORD GR3_BST_MD:1; /* GR3_BST_MD */\r
+ } BIT; /* */\r
+ } GR3_FLM1; /* */\r
+ union { /* GR3_FLM2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD GR3_BASE:32; /* GR3_BASE */\r
+ } BIT; /* */\r
+ } GR3_FLM2; /* */\r
+ union { /* GR3_FLM3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD GR3_LN_OFF:15; /* GR3_LN_OFF */\r
+ _UWORD :6; /* */\r
+ _UWORD GR3_FLM_NUM:10; /* GR3_FLM_NUM */\r
+ } BIT; /* */\r
+ } GR3_FLM3; /* */\r
+ union { /* GR3_FLM4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :9; /* */\r
+ _UDWORD GR3_FLM_OFF:23; /* GR3_FLM_OFF */\r
+ } BIT; /* */\r
+ } GR3_FLM4; /* */\r
+ union { /* GR3_FLM5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD GR3_FLM_LNUM:10; /* GR3_FLM_LNUM */\r
+ _UWORD :6; /* */\r
+ _UWORD GR3_FLM_LOOP:10; /* GR3_FLM_LOOP */\r
+ } BIT; /* */\r
+ } GR3_FLM5; /* */\r
+ union { /* GR3_FLM6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GR3_FORMAT:4; /* GR3_FORMAT */\r
+ _UWORD :2; /* */\r
+ _UWORD GR3_HW:10; /* GR3_HW */\r
+ _UWORD :3; /* */\r
+ _UWORD GR3_ENDIAN_ON:1; /* GR3_ENDIAN_ON */\r
+ _UWORD :6; /* */\r
+ _UWORD GR3_STA_POS:6; /* GR3_STA_POS */\r
+ } BIT; /* */\r
+ } GR3_FLM6; /* */\r
+ union { /* GR3_AB1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :19; /* */\r
+ _UDWORD GR3_ARC_ON:1; /* GR3_ARC_ON */\r
+ _UDWORD :3; /* */\r
+ _UDWORD GR3_ARC_DISP_ON:1; /* GR3_ARC_DISP_ON */\r
+ _UDWORD :3; /* */\r
+ _UDWORD GR3_GRC_DISP_ON:1; /* GR3_GRC_DISP_ON */\r
+ _UDWORD :2; /* */\r
+ _UDWORD GR3_DISP_SEL:2; /* GR3_DISP_SEL */\r
+ } BIT; /* */\r
+ } GR3_AB1; /* */\r
+ union { /* GR3_AB2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GR3_GRC_VS:11; /* GR3_GRC_VS */\r
+ _UWORD :5; /* */\r
+ _UWORD GR3_GRC_VW:11; /* GR3_GRC_VW */\r
+ } BIT; /* */\r
+ } GR3_AB2; /* */\r
+ union { /* GR3_AB3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GR3_GRC_HS:11; /* GR3_GRC_HS */\r
+ _UWORD :5; /* */\r
+ _UWORD GR3_GRC_HW:11; /* GR3_GRC_HW */\r
+ } BIT; /* */\r
+ } GR3_AB3; /* */\r
+ union { /* GR3_AB4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GR3_ARC_VS:11; /* GR3_ARC_VS */\r
+ _UWORD :5; /* */\r
+ _UWORD GR3_ARC_VW:11; /* GR3_ARC_VW */\r
+ } BIT; /* */\r
+ } GR3_AB4; /* */\r
+ union { /* GR3_AB5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GR3_ARC_HS:11; /* GR3_ARC_HS */\r
+ _UWORD :5; /* */\r
+ _UWORD GR3_ARC_HW:11; /* GR3_ARC_HW */\r
+ } BIT; /* */\r
+ } GR3_AB5; /* */\r
+ union { /* GR3_AB6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :7; /* */\r
+ _UWORD GR3_ARC_MODE:1; /* GR3_ARC_MODE */\r
+ _UWORD GR3_ARC_COEF:8; /* GR3_ARC_COEF */\r
+ _UWORD :8; /* */\r
+ _UWORD GR3_ARC_RATE:8; /* GR3_ARC_RATE */\r
+ } BIT; /* */\r
+ } GR3_AB6; /* */\r
+ union { /* GR3_AB7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD GR3_ARC_DEF:8; /* GR3_ARC_DEF */\r
+ _UWORD :15; /* */\r
+ _UWORD GR3_CK_ON:1; /* GR3_CK_ON */\r
+ } BIT; /* */\r
+ } GR3_AB7; /* */\r
+ union { /* GR3_AB8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GR3_CK_KCLUT:8; /* GR3_CK_KCLUT */\r
+ _UWORD GR3_CK_KG:8; /* GR3_CK_KG */\r
+ _UWORD GR3_CK_KB:8; /* GR3_CK_KB */\r
+ _UWORD GR3_CK_KR:8; /* GR3_CK_KR */\r
+ } BIT; /* */\r
+ } GR3_AB8; /* */\r
+ union { /* GR3_AB9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GR3_CK_A:8; /* GR3_CK_A */\r
+ _UWORD GR3_CK_G:8; /* GR3_CK_G */\r
+ _UWORD GR3_CK_B:8; /* GR3_CK_B */\r
+ _UWORD GR3_CK_R:8; /* GR3_CK_R */\r
+ } BIT; /* */\r
+ } GR3_AB9; /* */\r
+ union { /* GR3_AB10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GR3_A0:8; /* GR3_A0 */\r
+ _UWORD GR3_G0:8; /* GR3_G0 */\r
+ _UWORD GR3_B0:8; /* GR3_B0 */\r
+ _UWORD GR3_R0:8; /* GR3_R0 */\r
+ } BIT; /* */\r
+ } GR3_AB10; /* */\r
+ union { /* GR3_AB11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GR3_A1:8; /* GR3_A1 */\r
+ _UWORD GR3_G1:8; /* GR3_G1 */\r
+ _UWORD GR3_B1:8; /* GR3_B1 */\r
+ _UWORD GR3_R1:8; /* GR3_R1 */\r
+ } BIT; /* */\r
+ } GR3_AB11; /* */\r
+ union { /* GR3_BASE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD GR3_BASE_G:8; /* GR3_BASE_G */\r
+ _UWORD GR3_BASE_B:8; /* GR3_BASE_B */\r
+ _UWORD GR3_BASE_R:8; /* GR3_BASE_R */\r
+ } BIT; /* */\r
+ } GR3_BASE; /* */\r
+ union { /* GR3_CLUT_INT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :15; /* */\r
+ _UWORD GR3_CLT_SEL:1; /* GR3_CLT_SEL */\r
+ _UWORD :5; /* */\r
+ _UWORD GR3_LINE:11; /* */\r
+ } BIT; /* */\r
+ } GR3_CLUT_INT; /* */\r
+ union { /* GR3_MON */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD GR3_ARC_ST:1; /* GR3_ARC_ST */\r
+ } BIT; /* */\r
+ } GR3_MON; /* */\r
+ _UBYTE wk13[40]; /* */\r
+ union { /* GAM_G_UPDATE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD GAM_G_VEN:1; /* GAM_G_VEN */\r
+ } BIT; /* */\r
+ } GAM_G_UPDATE; /* */\r
+ union { /* GAM_SW */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD GAM_ON:1; /* GAM_ON */\r
+ } BIT; /* */\r
+ } GAM_SW; /* */\r
+ union { /* GAM_G_LUT1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_00:11; /* GAM_G_GAIN_00 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_01:11; /* GAM_G_GAIN_01 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT1; /* */\r
+ union { /* GAM_G_LUT2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_02:11; /* GAM_G_GAIN_02 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_03:11; /* GAM_G_GAIN_03 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT2; /* */\r
+ union { /* GAM_G_LUT3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_04:11; /* GAM_G_GAIN_04 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_05:11; /* GAM_G_GAIN_05 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT3; /* */\r
+ union { /* GAM_G_LUT4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_06:11; /* GAM_G_GAIN_06 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_07:11; /* GAM_G_GAIN_07 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT4; /* */\r
+ union { /* GAM_G_LUT5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_08:11; /* GAM_G_GAIN_08 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_09:11; /* GAM_G_GAIN_09 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT5; /* */\r
+ union { /* GAM_G_LUT6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_10:11; /* GAM_G_GAIN_10 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_11:11; /* GAM_G_GAIN_11 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT6; /* */\r
+ union { /* GAM_G_LUT7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_12:11; /* GAM_G_GAIN_12 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_13:11; /* GAM_G_GAIN_13 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT7; /* */\r
+ union { /* GAM_G_LUT8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_14:11; /* GAM_G_GAIN_14 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_15:11; /* GAM_G_GAIN_15 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT8; /* */\r
+ union { /* GAM_G_LUT9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_16:11; /* GAM_G_GAIN_16 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_17:11; /* GAM_G_GAIN_17 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT9; /* */\r
+ union { /* GAM_G_LUT10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_18:11; /* GAM_G_GAIN_18 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_19:11; /* GAM_G_GAIN_19 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT10; /* */\r
+ union { /* GAM_G_LUT11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_20:11; /* GAM_G_GAIN_20 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_21:11; /* GAM_G_GAIN_21 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT11; /* */\r
+ union { /* GAM_G_LUT12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_22:11; /* GAM_G_GAIN_22 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_23:11; /* GAM_G_GAIN_23 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT12; /* */\r
+ union { /* GAM_G_LUT13 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_24:11; /* GAM_G_GAIN_24 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_25:11; /* GAM_G_GAIN_25 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT13; /* */\r
+ union { /* GAM_G_LUT14 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_26:11; /* GAM_G_GAIN_26 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_27:11; /* GAM_G_GAIN_27 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT14; /* */\r
+ union { /* GAM_G_LUT15 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_28:11; /* GAM_G_GAIN_28 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_29:11; /* GAM_G_GAIN_29 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT15; /* */\r
+ union { /* GAM_G_LUT16 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_30:11; /* GAM_G_GAIN_30 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_G_GAIN_31:11; /* GAM_G_GAIN_31 */\r
+ } BIT; /* */\r
+ } GAM_G_LUT16; /* */\r
+ union { /* GAM_G_AREA1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD GAM_G_TH_01:8; /* GAM_G_TH_01 */\r
+ _UWORD GAM_G_TH_02:8; /* GAM_G_TH_02 */\r
+ _UWORD GAM_G_TH_03:8; /* GAM_G_TH_03 */\r
+ } BIT; /* */\r
+ } GAM_G_AREA1; /* */\r
+ union { /* GAM_G_AREA2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_G_TH_04:8; /* GAM_G_TH_04 */\r
+ _UWORD GAM_G_TH_05:8; /* GAM_G_TH_05 */\r
+ _UWORD GAM_G_TH_06:8; /* GAM_G_TH_06 */\r
+ _UWORD GAM_G_TH_07:8; /* GAM_G_TH_07 */\r
+ } BIT; /* */\r
+ } GAM_G_AREA2; /* */\r
+ union { /* GAM_G_AREA3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_G_TH_08:8; /* GAM_G_TH_08 */\r
+ _UWORD GAM_G_TH_09:8; /* GAM_G_TH_09 */\r
+ _UWORD GAM_G_TH_10:8; /* GAM_G_TH_10 */\r
+ _UWORD GAM_G_TH_11:8; /* GAM_G_TH_11 */\r
+ } BIT; /* */\r
+ } GAM_G_AREA3; /* */\r
+ union { /* GAM_G_AREA4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_G_TH_12:8; /* GAM_G_TH_12 */\r
+ _UWORD GAM_G_TH_13:8; /* GAM_G_TH_13 */\r
+ _UWORD GAM_G_TH_14:8; /* GAM_G_TH_14 */\r
+ _UWORD GAM_G_TH_15:8; /* GAM_G_TH_15 */\r
+ } BIT; /* */\r
+ } GAM_G_AREA4; /* */\r
+ union { /* GAM_G_AREA5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_G_TH_16:8; /* GAM_G_TH_16 */\r
+ _UWORD GAM_G_TH_17:8; /* GAM_G_TH_17 */\r
+ _UWORD GAM_G_TH_18:8; /* GAM_G_TH_18 */\r
+ _UWORD GAM_G_TH_19:8; /* GAM_G_TH_19 */\r
+ } BIT; /* */\r
+ } GAM_G_AREA5; /* */\r
+ union { /* GAM_G_AREA6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_G_TH_20:8; /* GAM_G_TH_20 */\r
+ _UWORD GAM_G_TH_21:8; /* GAM_G_TH_21 */\r
+ _UWORD GAM_G_TH_22:8; /* GAM_G_TH_22 */\r
+ _UWORD GAM_G_TH_23:8; /* GAM_G_TH_23 */\r
+ } BIT; /* */\r
+ } GAM_G_AREA6; /* */\r
+ union { /* GAM_G_AREA7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_G_TH_24:8; /* GAM_G_TH_24 */\r
+ _UWORD GAM_G_TH_25:8; /* GAM_G_TH_25 */\r
+ _UWORD GAM_G_TH_26:8; /* GAM_G_TH_26 */\r
+ _UWORD GAM_G_TH_27:8; /* GAM_G_TH_27 */\r
+ } BIT; /* */\r
+ } GAM_G_AREA7; /* */\r
+ union { /* GAM_G_AREA8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_G_TH_28:8; /* GAM_G_TH_28 */\r
+ _UWORD GAM_G_TH_29:8; /* GAM_G_TH_29 */\r
+ _UWORD GAM_G_TH_30:8; /* GAM_G_TH_30 */\r
+ _UWORD GAM_G_TH_31:8; /* GAM_G_TH_31 */\r
+ } BIT; /* */\r
+ } GAM_G_AREA8; /* */\r
+ _UBYTE wk14[24]; /* */\r
+ union { /* GAM_B_UPDATE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD GAM_B_VEN:1; /* GAM_B_VEN */\r
+ } BIT; /* */\r
+ } GAM_B_UPDATE; /* */\r
+ _UBYTE wk15[4]; /* */\r
+ union { /* GAM_B_LUT1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_00:11; /* GAM_B_GAIN_00 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_01:11; /* GAM_B_GAIN_01 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT1; /* */\r
+ union { /* GAM_B_LUT2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_02:11; /* GAM_B_GAIN_02 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_03:11; /* GAM_B_GAIN_03 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT2; /* */\r
+ union { /* GAM_B_LUT3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_04:11; /* GAM_B_GAIN_04 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_05:11; /* GAM_B_GAIN_05 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT3; /* */\r
+ union { /* GAM_B_LUT4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_06:11; /* GAM_B_GAIN_06 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_07:11; /* GAM_B_GAIN_07 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT4; /* */\r
+ union { /* GAM_B_LUT5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_08:11; /* GAM_B_GAIN_08 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_09:11; /* GAM_B_GAIN_09 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT5; /* */\r
+ union { /* GAM_B_LUT6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_10:11; /* GAM_B_GAIN_10 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_11:11; /* GAM_B_GAIN_11 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT6; /* */\r
+ union { /* GAM_B_LUT7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_12:11; /* GAM_B_GAIN_12 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_13:11; /* GAM_B_GAIN_13 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT7; /* */\r
+ union { /* GAM_B_LUT8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_14:11; /* GAM_B_GAIN_14 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_15:11; /* GAM_B_GAIN_15 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT8; /* */\r
+ union { /* GAM_B_LUT9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_16:11; /* GAM_B_GAIN_16 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_17:11; /* GAM_B_GAIN_17 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT9; /* */\r
+ union { /* GAM_B_LUT10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_18:11; /* GAM_B_GAIN_18 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_19:11; /* GAM_B_GAIN_19 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT10; /* */\r
+ union { /* GAM_B_LUT11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_20:11; /* GAM_B_GAIN_20 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_21:11; /* GAM_B_GAIN_21 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT11; /* */\r
+ union { /* GAM_B_LUT12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_22:11; /* GAM_B_GAIN_22 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_23:11; /* GAM_B_GAIN_23 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT12; /* */\r
+ union { /* GAM_B_LUT13 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_24:11; /* GAM_B_GAIN_24 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_25:11; /* GAM_B_GAIN_25 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT13; /* */\r
+ union { /* GAM_B_LUT14 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_26:11; /* GAM_B_GAIN_26 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_27:11; /* GAM_B_GAIN_27 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT14; /* */\r
+ union { /* GAM_B_LUT15 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_28:11; /* GAM_B_GAIN_28 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_29:11; /* GAM_B_GAIN_29 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT15; /* */\r
+ union { /* GAM_B_LUT16 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_30:11; /* GAM_B_GAIN_30 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_B_GAIN_31:11; /* GAM_B_GAIN_31 */\r
+ } BIT; /* */\r
+ } GAM_B_LUT16; /* */\r
+ union { /* GAM_B_AREA1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD GAM_B_TH_01:8; /* GAM_B_TH_01 */\r
+ _UWORD GAM_B_TH_02:8; /* GAM_B_TH_02 */\r
+ _UWORD GAM_B_TH_03:8; /* GAM_B_TH_03 */\r
+ } BIT; /* */\r
+ } GAM_B_AREA1; /* */\r
+ union { /* GAM_B_AREA2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_B_TH_04:8; /* GAM_B_TH_04 */\r
+ _UWORD GAM_B_TH_05:8; /* GAM_B_TH_05 */\r
+ _UWORD GAM_B_TH_06:8; /* GAM_B_TH_06 */\r
+ _UWORD GAM_B_TH_07:8; /* GAM_B_TH_07 */\r
+ } BIT; /* */\r
+ } GAM_B_AREA2; /* */\r
+ union { /* GAM_B_AREA3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_B_TH_08:8; /* GAM_B_TH_08 */\r
+ _UWORD GAM_B_TH_09:8; /* GAM_B_TH_09 */\r
+ _UWORD GAM_B_TH_10:8; /* GAM_B_TH_10 */\r
+ _UWORD GAM_B_TH_11:8; /* GAM_B_TH_11 */\r
+ } BIT; /* */\r
+ } GAM_B_AREA3; /* */\r
+ union { /* GAM_B_AREA4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_B_TH_12:8; /* GAM_B_TH_12 */\r
+ _UWORD GAM_B_TH_13:8; /* GAM_B_TH_13 */\r
+ _UWORD GAM_B_TH_14:8; /* GAM_B_TH_14 */\r
+ _UWORD GAM_B_TH_15:8; /* GAM_B_TH_15 */\r
+ } BIT; /* */\r
+ } GAM_B_AREA4; /* */\r
+ union { /* GAM_B_AREA5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_B_TH_16:8; /* GAM_B_TH_16 */\r
+ _UWORD GAM_B_TH_17:8; /* GAM_B_TH_17 */\r
+ _UWORD GAM_B_TH_18:8; /* GAM_B_TH_18 */\r
+ _UWORD GAM_B_TH_19:8; /* GAM_B_TH_19 */\r
+ } BIT; /* */\r
+ } GAM_B_AREA5; /* */\r
+ union { /* GAM_B_AREA6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_B_TH_20:8; /* GAM_B_TH_20 */\r
+ _UWORD GAM_B_TH_21:8; /* GAM_B_TH_21 */\r
+ _UWORD GAM_B_TH_22:8; /* GAM_B_TH_22 */\r
+ _UWORD GAM_B_TH_23:8; /* GAM_B_TH_23 */\r
+ } BIT; /* */\r
+ } GAM_B_AREA6; /* */\r
+ union { /* GAM_B_AREA7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_B_TH_24:8; /* GAM_B_TH_24 */\r
+ _UWORD GAM_B_TH_25:8; /* GAM_B_TH_25 */\r
+ _UWORD GAM_B_TH_26:8; /* GAM_B_TH_26 */\r
+ _UWORD GAM_B_TH_27:8; /* GAM_B_TH_27 */\r
+ } BIT; /* */\r
+ } GAM_B_AREA7; /* */\r
+ union { /* GAM_B_AREA8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_B_TH_28:8; /* GAM_B_TH_28 */\r
+ _UWORD GAM_B_TH_29:8; /* GAM_B_TH_29 */\r
+ _UWORD GAM_B_TH_30:8; /* GAM_B_TH_30 */\r
+ _UWORD GAM_B_TH_31:8; /* GAM_B_TH_31 */\r
+ } BIT; /* */\r
+ } GAM_B_AREA8; /* */\r
+ _UBYTE wk16[24]; /* */\r
+ union { /* GAM_R_UPDATE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD GAM_R_VEN:1; /* GAM_R_VEN */\r
+ } BIT; /* */\r
+ } GAM_R_UPDATE; /* */\r
+ _UBYTE wk17[4]; /* */\r
+ union { /* GAM_R_LUT1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_00:11; /* GAM_R_GAIN_00 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_01:11; /* GAM_R_GAIN_01 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT1; /* */\r
+ union { /* GAM_R_LUT2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_02:11; /* GAM_R_GAIN_02 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_03:11; /* GAM_R_GAIN_03 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT2; /* */\r
+ union { /* GAM_R_LUT3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_04:11; /* GAM_R_GAIN_04 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_05:11; /* GAM_R_GAIN_05 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT3; /* */\r
+ union { /* GAM_R_LUT4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_06:11; /* GAM_R_GAIN_06 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_07:11; /* GAM_R_GAIN_07 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT4; /* */\r
+ union { /* GAM_R_LUT5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_08:11; /* GAM_R_GAIN_08 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_09:11; /* GAM_R_GAIN_09 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT5; /* */\r
+ union { /* GAM_R_LUT6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_10:11; /* GAM_R_GAIN_10 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_11:11; /* GAM_R_GAIN_11 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT6; /* */\r
+ union { /* GAM_R_LUT7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_12:11; /* GAM_R_GAIN_12 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_13:11; /* GAM_R_GAIN_13 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT7; /* */\r
+ union { /* GAM_R_LUT8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_14:11; /* GAM_R_GAIN_14 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_15:11; /* GAM_R_GAIN_15 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT8; /* */\r
+ union { /* GAM_R_LUT9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_16:11; /* GAM_R_GAIN_16 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_17:11; /* GAM_R_GAIN_17 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT9; /* */\r
+ union { /* GAM_R_LUT10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_18:11; /* GAM_R_GAIN_18 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_19:11; /* GAM_R_GAIN_19 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT10; /* */\r
+ union { /* GAM_R_LUT11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_20:11; /* GAM_R_GAIN_20 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_21:11; /* GAM_R_GAIN_21 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT11; /* */\r
+ union { /* GAM_R_LUT12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_22:11; /* GAM_R_GAIN_22 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_23:11; /* GAM_R_GAIN_23 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT12; /* */\r
+ union { /* GAM_R_LUT13 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_24:11; /* GAM_R_GAIN_24 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_25:11; /* GAM_R_GAIN_25 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT13; /* */\r
+ union { /* GAM_R_LUT14 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_26:11; /* GAM_R_GAIN_26 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_27:11; /* GAM_R_GAIN_27 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT14; /* */\r
+ union { /* GAM_R_LUT15 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_28:11; /* GAM_R_GAIN_28 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_29:11; /* GAM_R_GAIN_29 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT15; /* */\r
+ union { /* GAM_R_LUT16 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_30:11; /* GAM_R_GAIN_30 */\r
+ _UWORD :5; /* */\r
+ _UWORD GAM_R_GAIN_31:11; /* GAM_R_GAIN_31 */\r
+ } BIT; /* */\r
+ } GAM_R_LUT16; /* */\r
+ union { /* GAM_R_AREA1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD GAM_R_TH_01:8; /* GAM_R_TH_01 */\r
+ _UWORD GAM_R_TH_02:8; /* GAM_R_TH_02 */\r
+ _UWORD GAM_R_TH_03:8; /* GAM_R_TH_03 */\r
+ } BIT; /* */\r
+ } GAM_R_AREA1; /* */\r
+ union { /* GAM_R_AREA2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_R_TH_04:8; /* GAM_R_TH_04 */\r
+ _UWORD GAM_R_TH_05:8; /* GAM_R_TH_05 */\r
+ _UWORD GAM_R_TH_06:8; /* GAM_R_TH_06 */\r
+ _UWORD GAM_R_TH_07:8; /* GAM_R_TH_07 */\r
+ } BIT; /* */\r
+ } GAM_R_AREA2; /* */\r
+ union { /* GAM_R_AREA3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_R_TH_08:8; /* GAM_R_TH_08 */\r
+ _UWORD GAM_R_TH_09:8; /* GAM_R_TH_09 */\r
+ _UWORD GAM_R_TH_10:8; /* GAM_R_TH_10 */\r
+ _UWORD GAM_R_TH_11:8; /* GAM_R_TH_11 */\r
+ } BIT; /* */\r
+ } GAM_R_AREA3; /* */\r
+ union { /* GAM_R_AREA4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_R_TH_12:8; /* GAM_R_TH_12 */\r
+ _UWORD GAM_R_TH_13:8; /* GAM_R_TH_13 */\r
+ _UWORD GAM_R_TH_14:8; /* GAM_R_TH_14 */\r
+ _UWORD GAM_R_TH_15:8; /* GAM_R_TH_15 */\r
+ } BIT; /* */\r
+ } GAM_R_AREA4; /* */\r
+ union { /* GAM_R_AREA5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_R_TH_16:8; /* GAM_R_TH_16 */\r
+ _UWORD GAM_R_TH_17:8; /* GAM_R_TH_17 */\r
+ _UWORD GAM_R_TH_18:8; /* GAM_R_TH_18 */\r
+ _UWORD GAM_R_TH_19:8; /* GAM_R_TH_19 */\r
+ } BIT; /* */\r
+ } GAM_R_AREA5; /* */\r
+ union { /* GAM_R_AREA6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_R_TH_20:8; /* GAM_R_TH_20 */\r
+ _UWORD GAM_R_TH_21:8; /* GAM_R_TH_21 */\r
+ _UWORD GAM_R_TH_22:8; /* GAM_R_TH_22 */\r
+ _UWORD GAM_R_TH_23:8; /* GAM_R_TH_23 */\r
+ } BIT; /* */\r
+ } GAM_R_AREA6; /* */\r
+ union { /* GAM_R_AREA7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_R_TH_24:8; /* GAM_R_TH_24 */\r
+ _UWORD GAM_R_TH_25:8; /* GAM_R_TH_25 */\r
+ _UWORD GAM_R_TH_26:8; /* GAM_R_TH_26 */\r
+ _UWORD GAM_R_TH_27:8; /* GAM_R_TH_27 */\r
+ } BIT; /* */\r
+ } GAM_R_AREA7; /* */\r
+ union { /* GAM_R_AREA8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD GAM_R_TH_28:8; /* GAM_R_TH_28 */\r
+ _UWORD GAM_R_TH_29:8; /* GAM_R_TH_29 */\r
+ _UWORD GAM_R_TH_30:8; /* GAM_R_TH_30 */\r
+ _UWORD GAM_R_TH_31:8; /* GAM_R_TH_31 */\r
+ } BIT; /* */\r
+ } GAM_R_AREA8; /* */\r
+ _UBYTE wk18[24]; /* */\r
+ union { /* TCON_UPDATE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD TCON_VEN:1; /* TCON_VEN */\r
+ } BIT; /* */\r
+ } TCON_UPDATE; /* */\r
+ union { /* TCON_TIM */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_HALF:11; /* TCON_HALF */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_OFFSET:11; /* TCON_OFFSET */\r
+ } BIT; /* */\r
+ } TCON_TIM; /* */\r
+ union { /* TCON_TIM_STVA1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_STVA_VS:11; /* TCON_STVA_VS */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_STVA_VW:11; /* TCON_STVA_VW */\r
+ } BIT; /* */\r
+ } TCON_TIM_STVA1; /* */\r
+ union { /* TCON_TIM_STVA2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD TCON_STVA_INV:1; /* TCON_STVA_INV */\r
+ _UDWORD :1; /* */\r
+ _UDWORD TCON_STVA_SEL:3; /* TCON_STVA_SEL */\r
+ } BIT; /* */\r
+ } TCON_TIM_STVA2; /* */\r
+ union { /* TCON_TIM_STVB1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_STVB_VS:11; /* TCON_STVB_VS */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_STVB_VW:11; /* TCON_STVB_VW */\r
+ } BIT; /* */\r
+ } TCON_TIM_STVB1; /* */\r
+ union { /* TCON_TIM_STVB2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD TCON_STVB_INV:1; /* TCON_STVB_INV */\r
+ _UDWORD :1; /* */\r
+ _UDWORD TCON_STVB_SEL:3; /* TCON_STVB_SEL */\r
+ } BIT; /* */\r
+ } TCON_TIM_STVB2; /* */\r
+ union { /* TCON_TIM_STH1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_STH_HS:11; /* TCON_STH_HS */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_STH_HW:11; /* TCON_STH_HW */\r
+ } BIT; /* */\r
+ } TCON_TIM_STH1; /* */\r
+ union { /* TCON_TIM_STH2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :23; /* */\r
+ _UDWORD TCON_STH_HS_SEL:1; /* TCON_STH_HS_SEL */\r
+ _UDWORD :3; /* */\r
+ _UDWORD TCON_STH_INV:1; /* TCON_STH_INV */\r
+ _UDWORD :1; /* */\r
+ _UDWORD TCON_STH_SEL:3; /* TCON_STH_SEL */\r
+ } BIT; /* */\r
+ } TCON_TIM_STH2; /* */\r
+ union { /* TCON_TIM_STB1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_STB_HS:11; /* TCON_STB_HS */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_STB_HW:11; /* TCON_STB_HW */\r
+ } BIT; /* */\r
+ } TCON_TIM_STB1; /* */\r
+ union { /* TCON_TIM_STB2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :23; /* */\r
+ _UDWORD TCON_STB_HS_SEL:1; /* TCON_STB_HS_SEL */\r
+ _UDWORD :3; /* */\r
+ _UDWORD TCON_STB_INV:1; /* TCON_STB_INV */\r
+ _UDWORD :1; /* */\r
+ _UDWORD TCON_STB_SEL:3; /* TCON_STB_SEL */\r
+ } BIT; /* */\r
+ } TCON_TIM_STB2; /* */\r
+ union { /* TCON_TIM_CPV1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_CPV_HS:11; /* TCON_CPV_HS */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_CPV_HW:11; /* TCON_CPV_HW */\r
+ } BIT; /* */\r
+ } TCON_TIM_CPV1; /* */\r
+ union { /* TCON_TIM_CPV2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :23; /* */\r
+ _UDWORD TCON_CPV_HS_SEL:1; /* TCON_CPV_HS_SEL */\r
+ _UDWORD :3; /* */\r
+ _UDWORD TCON_CPV_INV:1; /* TCON_CPV_INV */\r
+ _UDWORD :1; /* */\r
+ _UDWORD TCON_CPV_SEL:3; /* TCON_CPV_SEL */\r
+ } BIT; /* */\r
+ } TCON_TIM_CPV2; /* */\r
+ union { /* TCON_TIM_POLA1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_POLA_HS:11; /* TCON_POLA_HS */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_POLA_HW:11; /* TCON_POLA_HW */\r
+ } BIT; /* */\r
+ } TCON_TIM_POLA1; /* */\r
+ union { /* TCON_TIM_POLA2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :18; /* */\r
+ _UDWORD TCON_POLA_MD:2; /* TCON_POLA_MD */\r
+ _UDWORD :3; /* */\r
+ _UDWORD TCON_POLA_HS_SEL:1; /* TCON_POLA_HS_SEL */\r
+ _UDWORD :3; /* */\r
+ _UDWORD TCON_POLA_INV:1; /* TCON_POLA_INV */\r
+ _UDWORD :1; /* */\r
+ _UDWORD TCON_POLA_SEL:3; /* TCON_POLA_SEL */\r
+ } BIT; /* */\r
+ } TCON_TIM_POLA2; /* */\r
+ union { /* TCON_TIM_POLB1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_POLB_HS:11; /* TCON_POLB_HS */\r
+ _UWORD :5; /* */\r
+ _UWORD TCON_POLB_HW:11; /* TCON_POLB_HW */\r
+ } BIT; /* */\r
+ } TCON_TIM_POLB1; /* */\r
+ union { /* TCON_TIM_POLB2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :18; /* */\r
+ _UDWORD TCON_POLB_MD:2; /* TCON_POLB_MD */\r
+ _UDWORD :3; /* */\r
+ _UDWORD TCON_POLB_HS_SEL:1; /* TCON_POLB_HS_SEL */\r
+ _UDWORD :3; /* */\r
+ _UDWORD TCON_POLB_INV:1; /* TCON_POLB_INV */\r
+ _UDWORD :1; /* */\r
+ _UDWORD TCON_POLB_SEL:3; /* TCON_POLB_SEL */\r
+ } BIT; /* */\r
+ } TCON_TIM_POLB2; /* */\r
+ union { /* TCON_TIM_DE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD TCON_DE_INV:1; /* TCON_DE_INV */\r
+ } BIT; /* */\r
+ } TCON_TIM_DE; /* */\r
+ _UBYTE wk19[60]; /* */\r
+ union { /* OUT_UPDATE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD OUTCNT_VEN:1; /* OUTCNT_VEN */\r
+ } BIT; /* */\r
+ } OUT_UPDATE; /* */\r
+ union { /* OUT_SET */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD OUT_ENDIAN_ON:1; /* OUT_ENDIAN_ON */\r
+ _UWORD :3; /* */\r
+ _UWORD OUT_SWAP_ON:1; /* OUT_SWAP_ON */\r
+ _UWORD :8; /* */\r
+ _UWORD :2; /* */\r
+ _UWORD OUT_FORMAT:2; /* OUT_FORMAT */\r
+ _UWORD :2; /* */\r
+ _UWORD OUT_FRQ_SEL:2; /* OUT_FRQ_SEL */\r
+ _UWORD :3; /* */\r
+ _UWORD OUT_DIR_SEL:1; /* OUT_DIR_SEL */\r
+ _UWORD :2; /* */\r
+ _UWORD OUT_PHASE:2; /* OUT_PHASE */\r
+ } BIT; /* */\r
+ } OUT_SET; /* */\r
+ union { /* OUT_BRIGHT1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :22; /* */\r
+ _UDWORD PBRT_G:10; /* PBRT_G */\r
+ } BIT; /* */\r
+ } OUT_BRIGHT1; /* */\r
+ union { /* OUT_BRIGHT2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD PBRT_B:10; /* PBRT_B */\r
+ _UWORD :6; /* */\r
+ _UWORD PBRT_R:10; /* PBRT_R */\r
+ } BIT; /* */\r
+ } OUT_BRIGHT2; /* */\r
+ union { /* OUT_CONTRAST */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD CONT_G:8; /* CONT_G */\r
+ _UWORD CONT_B:8; /* CONT_B */\r
+ _UWORD CONT_R:8; /* CONT_R */\r
+ } BIT; /* */\r
+ } OUT_CONTRAST; /* */\r
+ union { /* OUT_PDTHA */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :10; /* */\r
+ _UWORD PDTH_SEL:2; /* PDTH_SEL */\r
+ _UWORD :2; /* */\r
+ _UWORD PDTH_FORMAT:2; /* PDTH_FORMAT */\r
+ _UWORD :2; /* */\r
+ _UWORD PDTH_PA:2; /* PDTH_PA */\r
+ _UWORD :2; /* */\r
+ _UWORD PDTH_PB:2; /* PDTH_PB */\r
+ _UWORD :2; /* */\r
+ _UWORD PDTH_PC:2; /* PDTH_PC */\r
+ _UWORD :2; /* */\r
+ _UWORD PDTH_PD:2; /* PDTH_PD */\r
+ } BIT; /* */\r
+ } OUT_PDTHA; /* */\r
+ _UBYTE wk20[12]; /* */\r
+ union { /* OUT_CLK_PHASE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :19; /* */\r
+ _UDWORD OUTCNT_FRONT_GAM:1; /* OUTCNT_FRONT_GAM */\r
+ _UDWORD :3; /* */\r
+ _UDWORD OUTCNT_LCD_EDGE:1; /* OUTCNT_LCD_EDGE */\r
+ _UDWORD :1; /* */\r
+ _UDWORD OUTCNT_STVA_EDGE:1; /* OUTCNT_STVA_EDGE */\r
+ _UDWORD OUTCNT_STVB_EDGE:1; /* OUTCNT_STVB_EDGE */\r
+ _UDWORD OUTCNT_STH_EDGE:1; /* OUTCNT_STH_EDGE */\r
+ _UDWORD OUTCNT_STB_EDGE:1; /* OUTCNT_STB_EDGE */\r
+ _UDWORD OUTCNT_CPV_EDGE:1; /* OUTCNT_CPV_EDGE */\r
+ _UDWORD OUTCNT_POLA_EDGE:1; /* OUTCNT_POLA_EDGE */\r
+ _UDWORD OUTCNT_POLB_EDGE:1; /* OUTCNT_POLB_EDGE */\r
+ } BIT; /* */\r
+ } OUT_CLK_PHASE; /* */\r
+ _UBYTE wk21[88]; /* */\r
+ union { /* SYSCNT_INT1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD INT_STA8:1; /* INT_STA8 */\r
+ } BIT; /* */\r
+ } SYSCNT_INT1; /* */\r
+ union { /* SYSCNT_INT2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_STA7:1; /* INT_STA7 */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_STA6:1; /* INT_STA6 */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_STA5:1; /* INT_STA5 */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_STA4:1; /* INT_STA4 */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_STA3:1; /* INT_STA3 */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_STA2:1; /* INT_STA2 */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_STA1:1; /* INT_STA1 */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_STA0:1; /* INT_STA0 */\r
+ } BIT; /* */\r
+ } SYSCNT_INT2; /* */\r
+ union { /* SYSCNT_INT3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD INT_OUT8_ON:1; /* INT_OUT8_ON */\r
+ } BIT; /* */\r
+ } SYSCNT_INT3; /* */\r
+ union { /* SYSCNT_INT4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_OUT7_ON:1; /* INT_OUT7_ON */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_OUT6_ON:1; /* INT_OUT6_ON */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_OUT5_ON:1; /* INT_OUT5_ON */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_OUT4_ON:1; /* INT_OUT4_ON */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_OUT3_ON:1; /* INT_OUT3_ON */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_OUT2_ON:1; /* INT_OUT2_ON */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_OUT1_ON:1; /* INT_OUT1_ON */\r
+ _UWORD :3; /* */\r
+ _UWORD INT_OUT0_ON:1; /* INT_OUT0_ON */\r
+ } BIT; /* */\r
+ } SYSCNT_INT4; /* */\r
+ union { /* SYSCNT_PANEL_CLK */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :2; /* */\r
+ _UWORD PANEL_ICKSEL:2; /* PANEL_ICKSEL */\r
+ _UWORD :3; /* */\r
+ _UWORD PANEL_ICKEN:1; /* PANEL_ICKEN */\r
+ _UWORD :2; /* */\r
+ _UWORD PANEL_DCDR:6; /* PANEL_DCDR */\r
+ } BIT; /* */\r
+ } SYSCNT_PANEL_CLK; /* */\r
+ union { /* SYSCNT_CLUT */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :7; /* */\r
+ _UWORD GR3_CLT_SEL_ST:1; /* GR3_CLT_SEL_ST */\r
+ _UWORD :3; /* */\r
+ _UWORD GR2_CLT_SEL_ST:1; /* GR2_CLT_SEL_ST */\r
+ _UWORD :3; /* */\r
+ _UWORD GR1_CLT_SEL_ST:1; /* GR1_CLT_SEL_ST */\r
+ } BIT; /* */\r
+ } SYSCNT_CLUT; /* */\r
+}; /* */\r
+struct st_src { /* struct SRC */\r
+ union { /* SRCID */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ } SRCID; /* */\r
+ union { /* SRCOD */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ } SRCOD; /* */\r
+ union { /* SRCIDCTRL */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD IED:1; /* IED */\r
+ _UWORD IEN:1; /* IEN */\r
+ _UWORD :6; /* */\r
+ _UWORD IFTRG:2; /* IFTRG */\r
+ } BIT; /* */\r
+ } SRCIDCTRL; /* */\r
+ union { /* SRCODCTRL */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD OCH:1; /* OCH */\r
+ _UWORD OED:1; /* OED */\r
+ _UWORD OEN:1; /* OEN */\r
+ _UWORD :6; /* */\r
+ _UWORD OFTRG:2; /* OFTRG */\r
+ } BIT; /* */\r
+ } SRCODCTRL; /* */\r
+ union { /* SRCCTRL */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :2; /* */\r
+ _UWORD CEEN:1; /* CEEN */\r
+ _UWORD SRCEN:1; /* SRCEN */\r
+ _UWORD UDEN:1; /* UDEN */\r
+ _UWORD OVEN:1; /* OVEN */\r
+ _UWORD FL:1; /* FL */\r
+ _UWORD CL:1; /* CL */\r
+ _UWORD IFS:4; /* IFS */\r
+ _UWORD :1; /* */\r
+ _UWORD OFS:3; /* OFS */\r
+ } BIT; /* */\r
+ } SRCCTRL; /* */\r
+ union { /* SRCSTAT */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD OFDN:5; /* OFDN */\r
+ _UWORD IFDN:4; /* IFDN */\r
+ _UWORD :1; /* */\r
+ _UWORD CEF:1; /* CEF */\r
+ _UWORD FLF:1; /* FLF */\r
+ _UWORD UDF:1; /* UDF */\r
+ _UWORD OVF:1; /* OVF */\r
+ _UWORD IINT:1; /* IINT */\r
+ _UWORD OINT:1; /* OINT */\r
+ } BIT; /* */\r
+ } SRCSTAT; /* */\r
+}; /* */\r
+ #if 0\r
+struct st_gpio { /* struct GPIO */\r
+ _UBYTE wk0[2]; /* */\r
+ union { /* PAIOR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :7; /* */\r
+ _UBYTE PA1IOR:1; /* PA1IOR */\r
+ _UBYTE :7; /* */\r
+ _UBYTE PA0IOR:1; /* PA0IOR */\r
+ } BIT; /* */\r
+ } PAIOR0; /* */\r
+ _UBYTE wk1[2]; /* */\r
+ union { /* PADR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :7; /* */\r
+ _UBYTE PA1DR:1; /* PA1DR */\r
+ _UBYTE :7; /* */\r
+ _UBYTE PA0DR:1; /* PA0DR */\r
+ } BIT; /* */\r
+ } PADR0; /* */\r
+ _UBYTE wk2[2]; /* */\r
+ union { /* PAPR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :8; /* */\r
+ _UBYTE :6; /* */\r
+ _UBYTE PA1PR:1; /* PA1PR */\r
+ _UBYTE PA0PR:1; /* PA0PR */\r
+ } BIT; /* */\r
+ } PAPR0; /* */\r
+ _UBYTE wk3[8]; /* */\r
+ union { /* PBCR5 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :5; /* */\r
+ _UBYTE PB22MD:3; /* PB22MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PB21MD:2; /* PB21MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PB20MD:3; /* PB20MD */\r
+ } BIT; /* */\r
+ } PBCR5; /* */\r
+ union { /* PBCR4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PB19MD:3; /* PB19MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PB18MD:3; /* PB18MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PB17MD:3; /* PB17MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PB16MD:3; /* PB16MD */\r
+ } BIT; /* */\r
+ } PBCR4; /* */\r
+ union { /* PBCR3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PB15MD:3; /* PB15MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PB14MD:3; /* PB14MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PB13MD:3; /* PB13MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PB12MD:2; /* PB12MD */\r
+ } BIT; /* */\r
+ } PBCR3; /* */\r
+ union { /* PBCR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PB11MD:2; /* PB11MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PB10MD:2; /* PB10MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PB9MD:2; /* PB9MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PB8MD:2; /* PB8MD */\r
+ } BIT; /* */\r
+ } PBCR2; /* */\r
+ union { /* PBCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PB7MD:2; /* PB7MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PB6MD:2; /* PB6MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PB5MD:2; /* PB5MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PB4MD:2; /* PB4MD */\r
+ } BIT; /* */\r
+ } PBCR1; /* */\r
+ union { /* PBCR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PB3MD:2; /* PB3MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PB2MD:2; /* PB2MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PB1MD:2; /* PB1MD */\r
+ _UBYTE :4; /* */\r
+ } BIT; /* */\r
+ } PBCR0; /* */\r
+ union { /* PBIOR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :8; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PB22IOR:1; /* PB22IOR */\r
+ _UBYTE PB21IOR:1; /* PB21IOR */\r
+ _UBYTE PB20IOR:1; /* PB20IOR */\r
+ _UBYTE PB19IOR:1; /* PB19IOR */\r
+ _UBYTE PB18IOR:1; /* PB18IOR */\r
+ _UBYTE PB17IOR:1; /* PB17IOR */\r
+ _UBYTE PB16IOR:1; /* PB16IOR */\r
+ } BIT; /* */\r
+ } PBIOR1; /* */\r
+ union { /* PBIOR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PB15IOR:1; /* PB15IOR */\r
+ _UBYTE PB14IOR:1; /* PB14IOR */\r
+ _UBYTE PB13IOR:1; /* PB13IOR */\r
+ _UBYTE PB12IOR:1; /* PB12IOR */\r
+ _UBYTE PB11IOR:1; /* PB11IOR */\r
+ _UBYTE PB10IOR:1; /* PB10IOR */\r
+ _UBYTE PB9IOR:1; /* PB9IOR */\r
+ _UBYTE PB8IOR:1; /* PB8IOR */\r
+ _UBYTE PB7IOR:1; /* PB7IOR */\r
+ _UBYTE PB6IOR:1; /* PB6IOR */\r
+ _UBYTE PB5IOR:1; /* PB5IOR */\r
+ _UBYTE PB4IOR:1; /* PB4IOR */\r
+ _UBYTE PB3IOR:1; /* PB3IOR */\r
+ _UBYTE PB2IOR:1; /* PB2IOR */\r
+ _UBYTE PB1IOR:1; /* PB1IOR */\r
+ _UBYTE :1; /* */\r
+ } BIT; /* */\r
+ } PBIOR0; /* */\r
+ union { /* PBDR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :8; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PB22DR:1; /* PB22DR */\r
+ _UBYTE PB21DR:1; /* PB21DR */\r
+ _UBYTE PB20DR:1; /* PB20DR */\r
+ _UBYTE PB19DR:1; /* PB19DR */\r
+ _UBYTE PB18DR:1; /* PB18DR */\r
+ _UBYTE PB17DR:1; /* PB17DR */\r
+ _UBYTE PB16DR:1; /* PB16DR */\r
+ } BIT; /* */\r
+ } PBDR1; /* */\r
+ union { /* PBDR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PB15DR:1; /* PB15DR */\r
+ _UBYTE PB14DR:1; /* PB14DR */\r
+ _UBYTE PB13DR:1; /* PB13DR */\r
+ _UBYTE PB12DR:1; /* PB12DR */\r
+ _UBYTE PB11DR:1; /* PB11DR */\r
+ _UBYTE PB10DR:1; /* PB10DR */\r
+ _UBYTE PB9DR:1; /* PB9DR */\r
+ _UBYTE PB8DR:1; /* PB8DR */\r
+ _UBYTE PB7DR:1; /* PB7DR */\r
+ _UBYTE PB6DR:1; /* PB6DR */\r
+ _UBYTE PB5DR:1; /* PB5DR */\r
+ _UBYTE PB4DR:1; /* PB4DR */\r
+ _UBYTE PB3DR:1; /* PB3DR */\r
+ _UBYTE PB2DR:1; /* PB2DR */\r
+ _UBYTE PB1DR:1; /* PB1DR */\r
+ _UBYTE :1; /* */\r
+ } BIT; /* */\r
+ } PBDR0; /* */\r
+ union { /* PBPR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :8; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PB22PR:1; /* PB22PR */\r
+ _UBYTE PB21PR:1; /* PB21PR */\r
+ _UBYTE PB20PR:1; /* PB20PR */\r
+ _UBYTE PB19PR:1; /* PB19PR */\r
+ _UBYTE PB18PR:1; /* PB18PR */\r
+ _UBYTE PB17PR:1; /* PB17PR */\r
+ _UBYTE PB16PR:1; /* PB16PR */\r
+ } BIT; /* */\r
+ } PBPR1; /* */\r
+ union { /* PBPR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PB15PR:1; /* PB15PR */\r
+ _UBYTE PB14PR:1; /* PB14PR */\r
+ _UBYTE PB13PR:1; /* PB13PR */\r
+ _UBYTE PB12PR:1; /* PB12PR */\r
+ _UBYTE PB11PR:1; /* PB11PR */\r
+ _UBYTE PB10PR:1; /* PB10PR */\r
+ _UBYTE PB9PR:1; /* PB9PR */\r
+ _UBYTE PB8PR:1; /* PB8PR */\r
+ _UBYTE PB7PR:1; /* PB7PR */\r
+ _UBYTE PB6PR:1; /* PB6PR */\r
+ _UBYTE PB5PR:1; /* PB5PR */\r
+ _UBYTE PB4PR:1; /* PB4PR */\r
+ _UBYTE PB3PR:1; /* PB3PR */\r
+ _UBYTE PB2PR:1; /* PB2PR */\r
+ _UBYTE PB1PR:1; /* PB1PR */\r
+ _UBYTE :1; /* */\r
+ } BIT; /* */\r
+ } PBPR0; /* */\r
+ _UBYTE wk4[14]; /* */\r
+ union { /* PCCR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :8; /* */\r
+ _UBYTE :5; /* */\r
+ _UBYTE PC8MD:3; /* PC8MD */\r
+ } BIT; /* */\r
+ } PCCR2; /* */\r
+ union { /* PCCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PC7MD:3; /* PC7MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PC6MD:3; /* PC6MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PC5MD:3; /* PC5MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PC4MD:2; /* PC4MD */\r
+ } BIT; /* */\r
+ } PCCR1; /* */\r
+ union { /* PCCR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PC3MD:2; /* PC3MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PC2MD:2; /* PC2MD */\r
+ _UBYTE :3; /* */\r
+ _UBYTE PC1MD:1; /* PC1MD */\r
+ _UBYTE :3; /* */\r
+ _UBYTE PC0MD:1; /* PC0MD */\r
+ } BIT; /* */\r
+ } PCCR0; /* */\r
+ _UBYTE wk5[2]; /* */\r
+ union { /* PCIOR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :7; /* */\r
+ _UBYTE PC8IOR:1; /* PC8IOR */\r
+ _UBYTE PC7IOR:1; /* PC7IOR */\r
+ _UBYTE PC6IOR:1; /* PC6IOR */\r
+ _UBYTE PC5IOR:1; /* PC5IOR */\r
+ _UBYTE PC4IOR:1; /* PC4IOR */\r
+ _UBYTE PC3IOR:1; /* PC3IOR */\r
+ _UBYTE PC2IOR:1; /* PC2IOR */\r
+ _UBYTE PC1IOR:1; /* PC1IOR */\r
+ _UBYTE PC0IOR:1; /* PC0IOR */\r
+ } BIT; /* */\r
+ } PCIOR0; /* */\r
+ _UBYTE wk6[2]; /* */\r
+ union { /* PCDR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :7; /* */\r
+ _UBYTE PC8DR:1; /* PC8DR */\r
+ _UBYTE PC7DR:1; /* PC7DR */\r
+ _UBYTE PC6DR:1; /* PC6DR */\r
+ _UBYTE PC5DR:1; /* PC5DR */\r
+ _UBYTE PC4DR:1; /* PC4DR */\r
+ _UBYTE PC3DR:1; /* PC3DR */\r
+ _UBYTE PC2DR:1; /* PC2DR */\r
+ _UBYTE PC1DR:1; /* PC1DR */\r
+ _UBYTE PC0DR:1; /* PC0DR */\r
+ } BIT; /* */\r
+ } PCDR0; /* */\r
+ _UBYTE wk7[2]; /* */\r
+ union { /* PCPR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :7; /* */\r
+ _UBYTE PC8PR:1; /* PC8PR */\r
+ _UBYTE PC7PR:1; /* PC7PR */\r
+ _UBYTE PC6PR:1; /* PC6PR */\r
+ _UBYTE PC5PR:1; /* PC5PR */\r
+ _UBYTE PC4PR:1; /* PC4PR */\r
+ _UBYTE PC3PR:1; /* PC3PR */\r
+ _UBYTE PC2PR:1; /* PC2PR */\r
+ _UBYTE PC1PR:1; /* PC1PR */\r
+ _UBYTE PC0PR:1; /* PC0PR */\r
+ } BIT; /* */\r
+ } PCPR0; /* */\r
+ _UBYTE wk8[12]; /* */\r
+ union { /* PDCR3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD15MD:2; /* PD15MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD14MD:2; /* PD14MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD13MD:2; /* PD13MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD12MD:2; /* PD12MD */\r
+ } BIT; /* */\r
+ } PDCR3; /* */\r
+ union { /* PDCR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD11MD:2; /* PD11MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD10MD:2; /* PD10MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD9MD:2; /* PD9MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD8MD:2; /* PD8MD */\r
+ } BIT; /* */\r
+ } PDCR2; /* */\r
+ union { /* PDCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD7MD:2; /* PD7MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD6MD:2; /* PD6MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD5MD:2; /* PD5MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD4MD:2; /* PD4MD */\r
+ } BIT; /* */\r
+ } PDCR1; /* */\r
+ union { /* PDCR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD3MD:2; /* PD3MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD2MD:2; /* PD2MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD1MD:2; /* PD1MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PD0MD:2; /* PD0MD */\r
+ } BIT; /* */\r
+ } PDCR0; /* */\r
+ _UBYTE wk9[2]; /* */\r
+ union { /* PDIOR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PD15IOR:1; /* PD15IOR */\r
+ _UBYTE PD14IOR:1; /* PD14IOR */\r
+ _UBYTE PD13IOR:1; /* PD13IOR */\r
+ _UBYTE PD12IOR:1; /* PD12IOR */\r
+ _UBYTE PD11IOR:1; /* PD11IOR */\r
+ _UBYTE PD10IOR:1; /* PD10IOR */\r
+ _UBYTE PD9IOR:1; /* PD9IOR */\r
+ _UBYTE PD8IOR:1; /* PD8IOR */\r
+ _UBYTE PD7IOR:1; /* PD7IOR */\r
+ _UBYTE PD6IOR:1; /* PD6IOR */\r
+ _UBYTE PD5IOR:1; /* PD5IOR */\r
+ _UBYTE PD4IOR:1; /* PD4IOR */\r
+ _UBYTE PD3IOR:1; /* PD3IOR */\r
+ _UBYTE PD2IOR:1; /* PD2IOR */\r
+ _UBYTE PD1IOR:1; /* PD1IOR */\r
+ _UBYTE PD0IOR:1; /* PD0IOR */\r
+ } BIT; /* */\r
+ } PDIOR0; /* */\r
+ _UBYTE wk10[2]; /* */\r
+ union { /* PDDR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PD15DR:1; /* PD15DR */\r
+ _UBYTE PD14DR:1; /* PD14DR */\r
+ _UBYTE PD13DR:1; /* PD13DR */\r
+ _UBYTE PD12DR:1; /* PD12DR */\r
+ _UBYTE PD11DR:1; /* PD11DR */\r
+ _UBYTE PD10DR:1; /* PD10DR */\r
+ _UBYTE PD9DR:1; /* PD9DR */\r
+ _UBYTE PD8DR:1; /* PD8DR */\r
+ _UBYTE PD7DR:1; /* PD7DR */\r
+ _UBYTE PD6DR:1; /* PD6DR */\r
+ _UBYTE PD5DR:1; /* PD5DR */\r
+ _UBYTE PD4DR:1; /* PD4DR */\r
+ _UBYTE PD3DR:1; /* PD3DR */\r
+ _UBYTE PD2DR:1; /* PD2DR */\r
+ _UBYTE PD1DR:1; /* PD1DR */\r
+ _UBYTE PD0DR:1; /* PD0DR */\r
+ } BIT; /* */\r
+ } PDDR0; /* */\r
+ _UBYTE wk11[2]; /* */\r
+ union { /* PDPR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PD15PR:1; /* PD15PR */\r
+ _UBYTE PD14PR:1; /* PD14PR */\r
+ _UBYTE PD13PR:1; /* PD13PR */\r
+ _UBYTE PD12PR:1; /* PD12PR */\r
+ _UBYTE PD11PR:1; /* PD11PR */\r
+ _UBYTE PD10PR:1; /* PD10PR */\r
+ _UBYTE PD9PR:1; /* PD9PR */\r
+ _UBYTE PD8PR:1; /* PD8PR */\r
+ _UBYTE PD7PR:1; /* PD7PR */\r
+ _UBYTE PD6PR:1; /* PD6PR */\r
+ _UBYTE PD5PR:1; /* PD5PR */\r
+ _UBYTE PD4PR:1; /* PD4PR */\r
+ _UBYTE PD3PR:1; /* PD3PR */\r
+ _UBYTE PD2PR:1; /* PD2PR */\r
+ _UBYTE PD1PR:1; /* PD1PR */\r
+ _UBYTE PD0PR:1; /* PD0PR */\r
+ } BIT; /* */\r
+ } PDPR0; /* */\r
+ _UBYTE wk12[16]; /* */\r
+ union { /* PECR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PE7MD:2; /* PE7MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PE6MD:2; /* PE6MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PE5MD:2; /* PE5MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PE4MD:2; /* PE4MD */\r
+ } BIT; /* */\r
+ } PECR1; /* */\r
+ union { /* PECR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PE3MD:3; /* PE3MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PE2MD:3; /* PE2MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PE1MD:3; /* PE1MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PE0MD:2; /* PE0MD */\r
+ } BIT; /* */\r
+ } PECR0; /* */\r
+ _UBYTE wk13[2]; /* */\r
+ union { /* PEIOR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :8; /* */\r
+ _UBYTE PE7IOR:1; /* PE7IOR */\r
+ _UBYTE PE6IOR:1; /* PE6IOR */\r
+ _UBYTE PE5IOR:1; /* PE5IOR */\r
+ _UBYTE PE4IOR:1; /* PE4IOR */\r
+ _UBYTE PE3IOR:1; /* PE3IOR */\r
+ _UBYTE PE2IOR:1; /* PE2IOR */\r
+ _UBYTE PE1IOR:1; /* PE1IOR */\r
+ _UBYTE PE0IOR:1; /* PE0IOR */\r
+ } BIT; /* */\r
+ } PEIOR0; /* */\r
+ _UBYTE wk14[2]; /* */\r
+ union { /* PEDR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :8; /* */\r
+ _UBYTE PE7DR:1; /* PE7DR */\r
+ _UBYTE PE6DR:1; /* PE6DR */\r
+ _UBYTE PE5DR:1; /* PE5DR */\r
+ _UBYTE PE4DR:1; /* PE4DR */\r
+ _UBYTE PE3DR:1; /* PE3DR */\r
+ _UBYTE PE2DR:1; /* PE2DR */\r
+ _UBYTE PE1DR:1; /* PE1DR */\r
+ _UBYTE PE0DR:1; /* PE0DR */\r
+ } BIT; /* */\r
+ } PEDR0; /* */\r
+ _UBYTE wk15[2]; /* */\r
+ union { /* PEPR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :8; /* */\r
+ _UBYTE PE7PR:1; /* PE7PR */\r
+ _UBYTE PE6PR:1; /* PE6PR */\r
+ _UBYTE PE5PR:1; /* PE5PR */\r
+ _UBYTE PE4PR:1; /* PE4PR */\r
+ _UBYTE PE3PR:1; /* PE3PR */\r
+ _UBYTE PE2PR:1; /* PE2PR */\r
+ _UBYTE PE1PR:1; /* PE1PR */\r
+ _UBYTE PE0PR:1; /* PE0PR */\r
+ } BIT; /* */\r
+ } PEPR0; /* */\r
+ _UBYTE wk16[6]; /* */\r
+ union { /* PFCR6 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF23MD :3; /* PF23MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF22MD :3; /* PF22MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF21MD :3; /* PF21MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF20MD :3; /* PF20MD */\r
+ } BIT; /* */\r
+ } PFCR6; /* */\r
+ union { /* PFCR5 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF19MD :3; /* PF19MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF18MD :3; /* PF18MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF17MD :3; /* PF17MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF16MD :3; /* PF16MD */\r
+ } BIT; /* */\r
+ } PFCR5; /* */\r
+ union { /* PFCR4 */\r
+ _UWORD WORD; /* Read/Write Access */\r
+ } PFCR4; /* Writing H'5A in the upper byte */\r
+ union { /* PFCR3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :5; /* */\r
+ _UBYTE PF14MD:3; /* PF14MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF13MD:3; /* PF13MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF12MD:3; /* PF12MD */\r
+ } BIT; /* */\r
+ } PFCR3; /* */\r
+ union { /* PFCR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF11MD:3; /* PF11MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF10MD:3; /* PF10MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF9MD:3; /* PF9MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF8MD:3; /* PF8MD */\r
+ } BIT; /* */\r
+ } PFCR2; /* */\r
+ union { /* PFCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF7MD:3; /* PF7MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF6MD:3; /* PF6MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF5MD:3; /* PF5MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF4MD:3; /* PF4MD */\r
+ } BIT; /* */\r
+ } PFCR1; /* */\r
+ union { /* PFCR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF3MD:3; /* PF3MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF2MD:3; /* PF2MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF1MD:3; /* PF1MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PF0MD:3; /* PF0MD */\r
+ } BIT; /* */\r
+ } PFCR0; /* */\r
+ union { /* PFIOR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :8; /* */\r
+ _UBYTE PF23IOR:1; /* PF23IOR */\r
+ _UBYTE PF22IOR:1; /* PF22IOR */\r
+ _UBYTE PF21IOR:1; /* PF21IOR */\r
+ _UBYTE PF20IOR:1; /* PF20IOR */\r
+ _UBYTE PF19IOR:1; /* PF19IOR */\r
+ _UBYTE PF18IOR:1; /* PF18IOR */\r
+ _UBYTE PF17IOR:1; /* PF17IOR */\r
+ _UBYTE PF16IOR:1; /* PF16IOR */\r
+ } BIT; /* */\r
+ } PFIOR1; /* */\r
+ union { /* PFIOR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PF15IOR:1; /* PF15IOR */\r
+ _UBYTE PF14IOR:1; /* PF14IOR */\r
+ _UBYTE PF13IOR:1; /* PF13IOR */\r
+ _UBYTE PF12IOR:1; /* PF12IOR */\r
+ _UBYTE PF11IOR:1; /* PF11IOR */\r
+ _UBYTE PF10IOR:1; /* PF10IOR */\r
+ _UBYTE PF9IOR:1; /* PF9IOR */\r
+ _UBYTE PF8IOR:1; /* PF8IOR */\r
+ _UBYTE PF7IOR:1; /* PF7IOR */\r
+ _UBYTE PF6IOR:1; /* PF6IOR */\r
+ _UBYTE PF5IOR:1; /* PF5IOR */\r
+ _UBYTE PF4IOR:1; /* PF4IOR */\r
+ _UBYTE PF3IOR:1; /* PF3IOR */\r
+ _UBYTE PF2IOR:1; /* PF2IOR */\r
+ _UBYTE PF1IOR:1; /* PF1IOR */\r
+ _UBYTE PF0IOR:1; /* PF0IOR */\r
+ } BIT; /* */\r
+ } PFIOR0; /* */\r
+ union { /* PFDR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :8; /* */\r
+ _UBYTE PF23DR:1; /* PF23DR */\r
+ _UBYTE PF22DR:1; /* PF22DR */\r
+ _UBYTE PF21DR:1; /* PF21DR */\r
+ _UBYTE PF20DR:1; /* PF20DR */\r
+ _UBYTE PF19DR:1; /* PF19DR */\r
+ _UBYTE PF18DR:1; /* PF18DR */\r
+ _UBYTE PF17DR:1; /* PF17DR */\r
+ _UBYTE PF16DR:1; /* PF16DR */\r
+ } BIT; /* */\r
+ } PFDR1; /* */\r
+ union { /* PFDR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PF15DR:1; /* PF15DR */\r
+ _UBYTE PF14DR:1; /* PF14DR */\r
+ _UBYTE PF13DR:1; /* PF13DR */\r
+ _UBYTE PF12DR:1; /* PF12DR */\r
+ _UBYTE PF11DR:1; /* PF11DR */\r
+ _UBYTE PF10DR:1; /* PF10DR */\r
+ _UBYTE PF9DR:1; /* PF9DR */\r
+ _UBYTE PF8DR:1; /* PF8DR */\r
+ _UBYTE PF7DR:1; /* PF7DR */\r
+ _UBYTE PF6DR:1; /* PF6DR */\r
+ _UBYTE PF5DR:1; /* PF5DR */\r
+ _UBYTE PF4DR:1; /* PF4DR */\r
+ _UBYTE PF3DR:1; /* PF3DR */\r
+ _UBYTE PF2DR:1; /* PF2DR */\r
+ _UBYTE PF1DR:1; /* PF1DR */\r
+ _UBYTE PF0DR:1; /* PF0DR */\r
+ } BIT; /* */\r
+ } PFDR0; /* */\r
+ union { /* PFPR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :8; /* */\r
+ _UBYTE PF23PR:1; /* PF23PR */\r
+ _UBYTE PF22PR:1; /* PF22PR */\r
+ _UBYTE PF21PR:1; /* PF21PR */\r
+ _UBYTE PF20PR:1; /* PF20PR */\r
+ _UBYTE PF19PR:1; /* PF19PR */\r
+ _UBYTE PF18PR:1; /* PF18PR */\r
+ _UBYTE PF17PR:1; /* PF17PR */\r
+ _UBYTE PF16PR:1; /* PF16PR */\r
+ } BIT; /* */\r
+ } PFPR1; /* */\r
+ union { /* PFPR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PF15PR:1; /* PF15PR */\r
+ _UBYTE PF14PR:1; /* PF14PR */\r
+ _UBYTE PF13PR:1; /* PF13PR */\r
+ _UBYTE PF12PR:1; /* PF12PR */\r
+ _UBYTE PF11PR:1; /* PF11PR */\r
+ _UBYTE PF10PR:1; /* PF10PR */\r
+ _UBYTE PF9PR:1; /* PF9PR */\r
+ _UBYTE PF8PR:1; /* PF8PR */\r
+ _UBYTE PF7PR:1; /* PF7PR */\r
+ _UBYTE PF6PR:1; /* PF6PR */\r
+ _UBYTE PF5PR:1; /* PF5PR */\r
+ _UBYTE PF4PR:1; /* PF4PR */\r
+ _UBYTE PF3PR:1; /* PF3PR */\r
+ _UBYTE PF2PR:1; /* PF2PR */\r
+ _UBYTE PF1PR:1; /* PF1PR */\r
+ _UBYTE PF0PR:1; /* PF0PR */\r
+ } BIT; /* */\r
+ } PFPR0; /* */\r
+ _UBYTE wk17[6]; /* */\r
+ union { /* PGCR6 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PG27MD:2; /* PG27MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PG26MD:2; /* PG26MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PG25MD:2; /* PG25MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PG24MD:2; /* PG24MD */\r
+ } BIT; /* */\r
+ } PGCR6; /* */\r
+ union { /* PGCR5 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG23MD:3; /* PG23MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG22MD:3; /* PG22MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG21MD:3; /* PG21MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG20MD:3; /* PG20MD */\r
+ } BIT; /* */\r
+ } PGCR5; /* */\r
+ union { /* PGCR4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG19MD:3; /* PG19MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG18MD:3; /* PG18MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PG17MD:2; /* PG17MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PG16MD:2; /* PG16MD */\r
+ } BIT; /* */\r
+ } PGCR4; /* */\r
+ union { /* PGCR3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PG15MD:2; /* PG15MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PG14MD:2; /* PG14MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PG13MD:2; /* PG13MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PG12MD:2; /* PG12MD */\r
+ } BIT; /* */\r
+ } PGCR3; /* */\r
+ union { /* PGCR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG11MD:3; /* PG11MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG10MD:3; /* PG10MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG9MD:3; /* PG9MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG8MD:3; /* PG8MD */\r
+ } BIT; /* */\r
+ } PGCR2; /* */\r
+ union { /* PGCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG7MD:3; /* PG7MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG6MD:3; /* PG6MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG5MD:3; /* PG5MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG4MD:3; /* PG4MD */\r
+ } BIT; /* */\r
+ } PGCR1; /* */\r
+ union { /* PGCR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG3MD:3; /* PG3MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG2MD:3; /* PG2MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG1MD:3; /* PG1MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PG0MD:3; /* PG0MD */\r
+ } BIT; /* */\r
+ } PGCR0; /* */\r
+ union { /* PGIOR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE PG27IOR:1; /* PG27IOR */\r
+ _UBYTE PG26IOR:1; /* PG26IOR */\r
+ _UBYTE PG25IOR:1; /* PG25IOR */\r
+ _UBYTE PG24IOR:1; /* PG24IOR */\r
+ _UBYTE PG23IOR:1; /* PG23IOR */\r
+ _UBYTE PG22IOR:1; /* PG22IOR */\r
+ _UBYTE PG21IOR:1; /* PG21IOR */\r
+ _UBYTE PG20IOR:1; /* PG20IOR */\r
+ _UBYTE PG19IOR:1; /* PG19IOR */\r
+ _UBYTE PG18IOR:1; /* PG18IOR */\r
+ _UBYTE PG17IOR:1; /* PG17IOR */\r
+ _UBYTE PG16IOR:1; /* PG16IOR */\r
+ } BIT; /* */\r
+ } PGIOR1; /* */\r
+ union { /* PGIOR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PG15IOR:1; /* PG15IOR */\r
+ _UBYTE PG14IOR:1; /* PG14IOR */\r
+ _UBYTE PG13IOR:1; /* PG13IOR */\r
+ _UBYTE PG12IOR:1; /* PG12IOR */\r
+ _UBYTE PG11IOR:1; /* PG11IOR */\r
+ _UBYTE PG10IOR:1; /* PG10IOR */\r
+ _UBYTE PG9IOR:1; /* PG9IOR */\r
+ _UBYTE PG8IOR:1; /* PG8IOR */\r
+ _UBYTE PG7IOR:1; /* PG7IOR */\r
+ _UBYTE PG6IOR:1; /* PG6IOR */\r
+ _UBYTE PG5IOR:1; /* PG5IOR */\r
+ _UBYTE PG4IOR:1; /* PG4IOR */\r
+ _UBYTE PG3IOR:1; /* PG3IOR */\r
+ _UBYTE PG2IOR:1; /* PG2IOR */\r
+ _UBYTE PG1IOR:1; /* PG1IOR */\r
+ _UBYTE PG0IOR:1; /* PG0IOR */\r
+ } BIT; /* */\r
+ } PGIOR0; /* */\r
+ union { /* PGDR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE PG27DR:1; /* PG27DR */\r
+ _UBYTE PG26DR:1; /* PG26DR */\r
+ _UBYTE PG25DR:1; /* PG25DR */\r
+ _UBYTE PG24DR:1; /* PG24DR */\r
+ _UBYTE PG23DR:1; /* PG23DR */\r
+ _UBYTE PG22DR:1; /* PG22DR */\r
+ _UBYTE PG21DR:1; /* PG21DR */\r
+ _UBYTE PG20DR:1; /* PG20DR */\r
+ _UBYTE PG19DR:1; /* PG19DR */\r
+ _UBYTE PG18DR:1; /* PG18DR */\r
+ _UBYTE PG17DR:1; /* PG17DR */\r
+ _UBYTE PG16DR:1; /* PG16DR */\r
+ } BIT; /* */\r
+ } PGDR1; /* */\r
+ union { /* PGDR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PG15DR:1; /* PG15DR */\r
+ _UBYTE PG14DR:1; /* PG14DR */\r
+ _UBYTE PG13DR:1; /* PG13DR */\r
+ _UBYTE PG12DR:1; /* PG12DR */\r
+ _UBYTE PG11DR:1; /* PG11DR */\r
+ _UBYTE PG10DR:1; /* PG10DR */\r
+ _UBYTE PG9DR:1; /* PG9DR */\r
+ _UBYTE PG8DR:1; /* PG8DR */\r
+ _UBYTE PG7DR:1; /* PG7DR */\r
+ _UBYTE PG6DR:1; /* PG6DR */\r
+ _UBYTE PG5DR:1; /* PG5DR */\r
+ _UBYTE PG4DR:1; /* PG4DR */\r
+ _UBYTE PG3DR:1; /* PG3DR */\r
+ _UBYTE PG2DR:1; /* PG2DR */\r
+ _UBYTE PG1DR:1; /* PG1DR */\r
+ _UBYTE PG0DR:1; /* PG0DR */\r
+ } BIT; /* */\r
+ } PGDR0; /* */\r
+ union { /* PGPR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE PG27PR:1; /* PG27PR */\r
+ _UBYTE PG26PR:1; /* PG26PR */\r
+ _UBYTE PG25PR:1; /* PG25PR */\r
+ _UBYTE PG24PR:1; /* PG24PR */\r
+ _UBYTE PG23PR:1; /* PG23PR */\r
+ _UBYTE PG22PR:1; /* PG22PR */\r
+ _UBYTE PG21PR:1; /* PG21PR */\r
+ _UBYTE PG20PR:1; /* PG20PR */\r
+ _UBYTE PG19PR:1; /* PG19PR */\r
+ _UBYTE PG18PR:1; /* PG18PR */\r
+ _UBYTE PG17PR:1; /* PG17PR */\r
+ _UBYTE PG16PR:1; /* PG16PR */\r
+ } BIT; /* */\r
+ } PGPR1; /* */\r
+ union { /* PGPR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PG15PR:1; /* PG15PR */\r
+ _UBYTE PG14PR:1; /* PG14PR */\r
+ _UBYTE PG13PR:1; /* PG13PR */\r
+ _UBYTE PG12PR:1; /* PG12PR */\r
+ _UBYTE PG11PR:1; /* PG11PR */\r
+ _UBYTE PG10PR:1; /* PG10PR */\r
+ _UBYTE PG9PR:1; /* PG9PR */\r
+ _UBYTE PG8PR:1; /* PG8PR */\r
+ _UBYTE PG7PR:1; /* PG7PR */\r
+ _UBYTE PG6PR:1; /* PG6PR */\r
+ _UBYTE PG5PR:1; /* PG5PR */\r
+ _UBYTE PG4PR:1; /* PG4PR */\r
+ _UBYTE PG3PR:1; /* PG3PR */\r
+ _UBYTE PG2PR:1; /* PG2PR */\r
+ _UBYTE PG1PR:1; /* PG1PR */\r
+ _UBYTE PG0PR:1; /* PG0PR */\r
+ } BIT; /* */\r
+ } PGPR0; /* */\r
+ _UBYTE wk18[16]; /* */\r
+ union { /* PHCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PH7MD:2; /* PH7MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PH6MD:2; /* PH6MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PH5MD:2; /* PH5MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PH4MD:2; /* PH4MD */\r
+ } BIT; /* */\r
+ } PHCR1; /* */\r
+ union { /* PHCR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PH3MD:2; /* PH3MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PH2MD:2; /* PH2MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PH1MD:2; /* PH1MD */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PH0MD:2; /* PH0MD */\r
+ } BIT; /* */\r
+ } PHCR0; /* */\r
+ _UBYTE wk19[10]; /* */\r
+ union { /* PHPR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :8; /* */\r
+ _UBYTE PH7PR:1; /* PH7PR */\r
+ _UBYTE PH6PR:1; /* PH6PR */\r
+ _UBYTE PH5PR:1; /* PH5PR */\r
+ _UBYTE PH4PR:1; /* PH4PR */\r
+ _UBYTE PH3PR:1; /* PH3PR */\r
+ _UBYTE PH2PR:1; /* PH2PR */\r
+ _UBYTE PH1PR:1; /* PH1PR */\r
+ _UBYTE PH0PR:1; /* PH0PR */\r
+ } BIT; /* */\r
+ } PHPR0; /* */\r
+ _UBYTE wk20[4]; /* */\r
+ union { /* PJCR7 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :3; /* */\r
+ _UBYTE PJ31MD:1; /* PJ31MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ30MD:3; /* PJ30MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ29MD:3; /* PJ29MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ28MD:3; /* PJ28MD */\r
+ } BIT; /* */\r
+ } PJCR7; /* */\r
+ union { /* PJCR6 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ27MD:3; /* PJ27MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ26MD:3; /* PJ26MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ25MD:3; /* PJ25MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ24MD:3; /* PJ24MD */\r
+ } BIT; /* */\r
+ } PJCR6; /* */\r
+ union { /* PJCR5 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ23MD:3; /* PJ23MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ22MD:3; /* PJ22MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ21MD:3; /* PJ21MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ20MD:3; /* PJ20MD */\r
+ } BIT; /* */\r
+ } PJCR5; /* */\r
+ union { /* PJCR4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ19MD:3; /* PJ19MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ18MD:3; /* PJ18MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ17MD:3; /* PJ17MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ16MD:3; /* PJ16MD */\r
+ } BIT; /* */\r
+ } PJCR4; /* */\r
+ union { /* PJCR3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ15MD:3; /* PJ15MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ14MD:3; /* PJ14MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ13MD:3; /* PJ13MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ12MD:3; /* PJ12MD */\r
+ } BIT; /* */\r
+ } PJCR3; /* */\r
+ union { /* PJCR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ11MD:3; /* PJ11MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ10MD:3; /* PJ10MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ9MD:3; /* PJ9MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ8MD:3; /* PJ8MD */\r
+ } BIT; /* */\r
+ } PJCR2; /* */\r
+ union { /* PJCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ7MD:3; /* PJ7MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ6MD:3; /* PJ6MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ5MD:3; /* PJ5MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ4MD:3; /* PJ4MD */\r
+ } BIT; /* */\r
+ } PJCR1; /* */\r
+ union { /* PJCR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ3MD:3; /* PJ3MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ2MD:3; /* PJ2MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ1MD:3; /* PJ1MD */\r
+ _UBYTE :1; /* */\r
+ _UBYTE PJ0MD:3; /* PJ0MD */\r
+ } BIT; /* */\r
+ } PJCR0; /* */\r
+ union { /* PJIOR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PJ31IOR:1; /* PJ31IOR */\r
+ _UBYTE PJ30IOR:1; /* PJ30IOR */\r
+ _UBYTE PJ29IOR:1; /* PJ29IOR */\r
+ _UBYTE PJ28IOR:1; /* PJ28IOR */\r
+ _UBYTE PJ27IOR:1; /* PJ27IOR */\r
+ _UBYTE PJ26IOR:1; /* PJ26IOR */\r
+ _UBYTE PJ25IOR:1; /* PJ25IOR */\r
+ _UBYTE PJ24IOR:1; /* PJ24IOR */\r
+ _UBYTE PJ23IOR:1; /* PJ23IOR */\r
+ _UBYTE PJ22IOR:1; /* PJ22IOR */\r
+ _UBYTE PJ21IOR:1; /* PJ21IOR */\r
+ _UBYTE PJ20IOR:1; /* PJ20IOR */\r
+ _UBYTE PJ19IOR:1; /* PJ19IOR */\r
+ _UBYTE PJ18IOR:1; /* PJ18IOR */\r
+ _UBYTE PJ17IOR:1; /* PJ17IOR */\r
+ _UBYTE PJ16IOR:1; /* PJ16IOR */\r
+ } BIT; /* */\r
+ } PJIOR1; /* */\r
+ union { /* PJIOR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PJ15IOR:1; /* PJ15IOR */\r
+ _UBYTE PJ14IOR:1; /* PJ14IOR */\r
+ _UBYTE PJ13IOR:1; /* PJ13IOR */\r
+ _UBYTE PJ12IOR:1; /* PJ12IOR */\r
+ _UBYTE PJ11IOR:1; /* PJ11IOR */\r
+ _UBYTE PJ10IOR:1; /* PJ10IOR */\r
+ _UBYTE PJ9IOR:1; /* PJ9IOR */\r
+ _UBYTE PJ8IOR:1; /* PJ8IOR */\r
+ _UBYTE PJ7IOR:1; /* PJ7IOR */\r
+ _UBYTE PJ6IOR:1; /* PJ6IOR */\r
+ _UBYTE PJ5IOR:1; /* PJ5IOR */\r
+ _UBYTE PJ4IOR:1; /* PJ4IOR */\r
+ _UBYTE PJ3IOR:1; /* PJ3IOR */\r
+ _UBYTE PJ2IOR:1; /* PJ2IOR */\r
+ _UBYTE PJ1IOR:1; /* PJ1IOR */\r
+ _UBYTE PJ0IOR:1; /* PJ0IOR */\r
+ } BIT; /* */\r
+ } PJIOR0; /* */\r
+ union { /* PJDR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PJ31DR:1; /* PJ31DR */\r
+ _UBYTE PJ30DR:1; /* PJ30DR */\r
+ _UBYTE PJ29DR:1; /* PJ29DR */\r
+ _UBYTE PJ28DR:1; /* PJ28DR */\r
+ _UBYTE PJ27DR:1; /* PJ27DR */\r
+ _UBYTE PJ26DR:1; /* PJ26DR */\r
+ _UBYTE PJ25DR:1; /* PJ25DR */\r
+ _UBYTE PJ24DR:1; /* PJ24DR */\r
+ _UBYTE PJ23DR:1; /* PJ23DR */\r
+ _UBYTE PJ22DR:1; /* PJ22DR */\r
+ _UBYTE PJ21DR:1; /* PJ21DR */\r
+ _UBYTE PJ20DR:1; /* PJ20DR */\r
+ _UBYTE PJ19DR:1; /* PJ19DR */\r
+ _UBYTE PJ18DR:1; /* PJ18DR */\r
+ _UBYTE PJ17DR:1; /* PJ17DR */\r
+ _UBYTE PJ16DR:1; /* PJ16DR */\r
+ } BIT; /* */\r
+ } PJDR1; /* */\r
+ union { /* PJDR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PJ15DR:1; /* PJ15DR */\r
+ _UBYTE PJ14DR:1; /* PJ14DR */\r
+ _UBYTE PJ13DR:1; /* PJ13DR */\r
+ _UBYTE PJ12DR:1; /* PJ12DR */\r
+ _UBYTE PJ11DR:1; /* PJ11DR */\r
+ _UBYTE PJ10DR:1; /* PJ10DR */\r
+ _UBYTE PJ9DR:1; /* PJ9DR */\r
+ _UBYTE PJ8DR:1; /* PJ8DR */\r
+ _UBYTE PJ7DR:1; /* PJ7DR */\r
+ _UBYTE PJ6DR:1; /* PJ6DR */\r
+ _UBYTE PJ5DR:1; /* PJ5DR */\r
+ _UBYTE PJ4DR:1; /* PJ4DR */\r
+ _UBYTE PJ3DR:1; /* PJ3DR */\r
+ _UBYTE PJ2DR:1; /* PJ2DR */\r
+ _UBYTE PJ1DR:1; /* PJ1DR */\r
+ _UBYTE PJ0DR:1; /* PJ0DR */\r
+ } BIT; /* */\r
+ } PJDR0; /* */\r
+ union { /* PJPR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PJ31PR:1; /* PJ31PR */\r
+ _UBYTE PJ30PR:1; /* PJ30PR */\r
+ _UBYTE PJ29PR:1; /* PJ29PR */\r
+ _UBYTE PJ28PR:1; /* PJ28PR */\r
+ _UBYTE PJ27PR:1; /* PJ27PR */\r
+ _UBYTE PJ26PR:1; /* PJ26PR */\r
+ _UBYTE PJ25PR:1; /* PJ25PR */\r
+ _UBYTE PJ24PR:1; /* PJ24PR */\r
+ _UBYTE PJ23PR:1; /* PJ23PR */\r
+ _UBYTE PJ22PR:1; /* PJ22PR */\r
+ _UBYTE PJ21PR:1; /* PJ21PR */\r
+ _UBYTE PJ20PR:1; /* PJ20PR */\r
+ _UBYTE PJ19PR:1; /* PJ19PR */\r
+ _UBYTE PJ18PR:1; /* PJ18PR */\r
+ _UBYTE PJ17PR:1; /* PJ17PR */\r
+ _UBYTE PJ16PR:1; /* PJ16PR */\r
+ } BIT; /* */\r
+ } PJPR1;\r
+ union { /* PJPR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE PJ15PR:1; /* PJ15PR */\r
+ _UBYTE PJ14PR:1; /* PJ14PR */\r
+ _UBYTE PJ13PR:1; /* PJ13PR */\r
+ _UBYTE PJ12PR:1; /* PJ12PR */\r
+ _UBYTE PJ11PR:1; /* PJ11PR */\r
+ _UBYTE PJ10PR:1; /* PJ10PR */\r
+ _UBYTE PJ9PR:1; /* PJ9PR */\r
+ _UBYTE PJ8PR:1; /* PJ8PR */\r
+ _UBYTE PJ7PR:1; /* PJ7PR */\r
+ _UBYTE PJ6PR:1; /* PJ6PR */\r
+ _UBYTE PJ5PR:1; /* PJ5PR */\r
+ _UBYTE PJ4PR:1; /* PJ4PR */\r
+ _UBYTE PJ3PR:1; /* PJ3PR */\r
+ _UBYTE PJ2PR:1; /* PJ2PR */\r
+ _UBYTE PJ1PR:1; /* PJ1PR */\r
+ _UBYTE PJ0PR:1; /* PJ0PR */\r
+ } BIT; /* */\r
+ } PJPR0; /* */\r
+ _UBYTE wk21[34]; /* */\r
+ union { /* SNCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Byte Access */\r
+ _UBYTE H; /* High */\r
+ _UBYTE L; /* Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UBYTE :8; /* */\r
+ _UBYTE :2; /* */\r
+ _UBYTE SSI5NCE:1; /* SSI5NCE */\r
+ _UBYTE SSI4NCE:1; /* SSI4NCE */\r
+ _UBYTE SSI3NCE:1; /* SSI3NCE */\r
+ _UBYTE SSI2NCE:1; /* SSI2NCE */\r
+ _UBYTE SSI1NCE:1; /* SSI1NCE */\r
+ _UBYTE SSI0NCE:1; /* SSI0NCE */\r
+ } BIT; /* */\r
+ }SNCR; /* */\r
+}; /* */\r
+ #endif\r
+struct st_hudi { /* struct HUDI */\r
+ union { /* SDIR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD TI:8; /* TI */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } SDIR; /* */\r
+}; /* */\r
+struct st_pwm { /* struct PWM */\r
+ union { /* PWBTCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE BTC2G:1; /* BTC2G */\r
+ _UBYTE BTC2E:1; /* BTC2E */\r
+ _UBYTE BTC2C:1; /* BTC2C */\r
+ _UBYTE BTC2A:1; /* BTC2A */\r
+ _UBYTE BTC1G:1; /* BTC1G */\r
+ _UBYTE BTC1E:1; /* BTC1E */\r
+ _UBYTE BTC1C:1; /* BTC1C */\r
+ _UBYTE BTC1A:1; /* BTC1A */\r
+ } BIT; /* */\r
+ } PWBTCR; /* */\r
+ _UBYTE wk0[217]; /* */\r
+ union { /* PWCR1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE CMF:1; /* CMF */\r
+ _UBYTE CST:1; /* CST */\r
+ _UBYTE CKS:3; /* CKS */\r
+ } BIT; /* */\r
+ } PWCR1; /* */\r
+ _UBYTE wk1[3]; /* */\r
+ union { /* PWPR1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE OPS1H:1; /* OPS1H */\r
+ _UBYTE OPS1G:1; /* OPS1G */\r
+ _UBYTE OPS1F:1; /* OPS1F */\r
+ _UBYTE OPS1E:1; /* OPS1E */\r
+ _UBYTE OPS1D:1; /* OPS1D */\r
+ _UBYTE OPS1C:1; /* OPS1C */\r
+ _UBYTE OPS1B:1; /* OPS1B */\r
+ _UBYTE OPS1A:1; /* OPS1A */\r
+ } BIT; /* */\r
+ } PWPR1; /* */\r
+ _UBYTE wk2[1]; /* */\r
+ union { /* PWCYR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PWCY15:1; /* PWCY15 */\r
+ _UWORD PWCY14:1; /* PWCY14 */\r
+ _UWORD PWCY13:1; /* PWCY13 */\r
+ _UWORD PWCY12:1; /* PWCY12 */\r
+ _UWORD PWCY11:1; /* PWCY11 */\r
+ _UWORD PWCY10:1; /* PWCY10 */\r
+ _UWORD PWCY9:1; /* PWCY9 */\r
+ _UWORD PWCY8:1; /* PWCY8 */\r
+ _UWORD PWCY7:1; /* PWCY7 */\r
+ _UWORD PWCY6:1; /* PWCY6 */\r
+ _UWORD PWCY5:1; /* PWCY5 */\r
+ _UWORD PWCY4:1; /* PWCY4 */\r
+ _UWORD PWCY3:1; /* PWCY3 */\r
+ _UWORD PWCY2:1; /* PWCY2 */\r
+ _UWORD PWCY1:1; /* PWCY1 */\r
+ _UWORD PWCY0:1; /* PWCY0 */\r
+ } BIT; /* */\r
+ } PWCYR1; /* */\r
+ union { /* PWBFR1A */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD OTS:1; /* OTS */\r
+ _UWORD :2; /* */\r
+ _UWORD DT9:1; /* DT9 */\r
+ _UWORD DT8:1; /* DT8 */\r
+ _UWORD DT7:1; /* DT7 */\r
+ _UWORD DT6:1; /* DT6 */\r
+ _UWORD DT5:1; /* DT5 */\r
+ _UWORD DT4:1; /* DT4 */\r
+ _UWORD DT3:1; /* DT3 */\r
+ _UWORD DT2:1; /* DT2 */\r
+ _UWORD DT1:1; /* DT1 */\r
+ _UWORD DT0:1; /* DT0 */\r
+ } BIT; /* */\r
+ } PWBFR1A; /* */\r
+ union { /* PWBFR1C */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD OTS:1; /* OTS */\r
+ _UWORD :2; /* */\r
+ _UWORD DT9:1; /* DT9 */\r
+ _UWORD DT8:1; /* DT8 */\r
+ _UWORD DT7:1; /* DT7 */\r
+ _UWORD DT6:1; /* DT6 */\r
+ _UWORD DT5:1; /* DT5 */\r
+ _UWORD DT4:1; /* DT4 */\r
+ _UWORD DT3:1; /* DT3 */\r
+ _UWORD DT2:1; /* DT2 */\r
+ _UWORD DT1:1; /* DT1 */\r
+ _UWORD DT0:1; /* DT0 */\r
+ } BIT; /* */\r
+ } PWBFR1C; /* */\r
+ union { /* PWBFR1E */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD OTS:1; /* OTS */\r
+ _UWORD :2; /* */\r
+ _UWORD DT9:1; /* DT9 */\r
+ _UWORD DT8:1; /* DT8 */\r
+ _UWORD DT7:1; /* DT7 */\r
+ _UWORD DT6:1; /* DT6 */\r
+ _UWORD DT5:1; /* DT5 */\r
+ _UWORD DT4:1; /* DT4 */\r
+ _UWORD DT3:1; /* DT3 */\r
+ _UWORD DT2:1; /* DT2 */\r
+ _UWORD DT1:1; /* DT1 */\r
+ _UWORD DT0:1; /* DT0 */\r
+ } BIT; /* */\r
+ } PWBFR1E; /* */\r
+ union { /* PWBFR1G */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD OTS:1; /* OTS */\r
+ _UWORD :2; /* */\r
+ _UWORD DT9:1; /* DT9 */\r
+ _UWORD DT8:1; /* DT8 */\r
+ _UWORD DT7:1; /* DT7 */\r
+ _UWORD DT6:1; /* DT6 */\r
+ _UWORD DT5:1; /* DT5 */\r
+ _UWORD DT4:1; /* DT4 */\r
+ _UWORD DT3:1; /* DT3 */\r
+ _UWORD DT2:1; /* DT2 */\r
+ _UWORD DT1:1; /* DT1 */\r
+ _UWORD DT0:1; /* DT0 */\r
+ } BIT; /* */\r
+ } PWBFR1G; /* */\r
+ union { /* PWCR2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE IE:1; /* IE */\r
+ _UBYTE CMF:1; /* CMF */\r
+ _UBYTE CST:1; /* CST */\r
+ _UBYTE CKS:3; /* CKS */\r
+ } BIT; /* */\r
+ } PWCR2; /* */\r
+ _UBYTE wk3[3]; /* */\r
+ union { /* PWPR2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE OPS2H:1; /* OPS2H */\r
+ _UBYTE OPS2G:1; /* OPS2G */\r
+ _UBYTE OPS2F:1; /* OPS2F */\r
+ _UBYTE OPS2E:1; /* OPS2E */\r
+ _UBYTE OPS2D:1; /* OPS2D */\r
+ _UBYTE OPS2C:1; /* OPS2C */\r
+ _UBYTE OPS2B:1; /* OPS2B */\r
+ _UBYTE OPS2A:1; /* OPS2A */\r
+ } BIT; /* */\r
+ } PWPR2; /* */\r
+ _UBYTE wk4[1]; /* */\r
+ union { /* PWCYR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PWCY15:1; /* PWCY15 */\r
+ _UWORD PWCY14:1; /* PWCY14 */\r
+ _UWORD PWCY13:1; /* PWCY13 */\r
+ _UWORD PWCY12:1; /* PWCY12 */\r
+ _UWORD PWCY11:1; /* PWCY11 */\r
+ _UWORD PWCY10:1; /* PWCY10 */\r
+ _UWORD PWCY9:1; /* PWCY9 */\r
+ _UWORD PWCY8:1; /* PWCY8 */\r
+ _UWORD PWCY7:1; /* PWCY7 */\r
+ _UWORD PWCY6:1; /* PWCY6 */\r
+ _UWORD PWCY5:1; /* PWCY5 */\r
+ _UWORD PWCY4:1; /* PWCY4 */\r
+ _UWORD PWCY3:1; /* PWCY3 */\r
+ _UWORD PWCY2:1; /* PWCY2 */\r
+ _UWORD PWCY1:1; /* PWCY1 */\r
+ _UWORD PWCY0:1; /* PWCY0 */\r
+ } BIT; /* */\r
+ } PWCYR2; /* */\r
+ union { /* PWBFR2A */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD OTS:1; /* OTS */\r
+ _UWORD :2; /* */\r
+ _UWORD DT9:1; /* DT9 */\r
+ _UWORD DT8:1; /* DT8 */\r
+ _UWORD DT7:1; /* DT7 */\r
+ _UWORD DT6:1; /* DT6 */\r
+ _UWORD DT5:1; /* DT5 */\r
+ _UWORD DT4:1; /* DT4 */\r
+ _UWORD DT3:1; /* DT3 */\r
+ _UWORD DT2:1; /* DT2 */\r
+ _UWORD DT1:1; /* DT1 */\r
+ _UWORD DT0:1; /* DT0 */\r
+ } BIT; /* */\r
+ } PWBFR2A; /* */\r
+ union { /* PWBFR2C */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD OTS:1; /* OTS */\r
+ _UWORD :2; /* */\r
+ _UWORD DT9:1; /* DT9 */\r
+ _UWORD DT8:1; /* DT8 */\r
+ _UWORD DT7:1; /* DT7 */\r
+ _UWORD DT6:1; /* DT6 */\r
+ _UWORD DT5:1; /* DT5 */\r
+ _UWORD DT4:1; /* DT4 */\r
+ _UWORD DT3:1; /* DT3 */\r
+ _UWORD DT2:1; /* DT2 */\r
+ _UWORD DT1:1; /* DT1 */\r
+ _UWORD DT0:1; /* DT0 */\r
+ } BIT; /* */\r
+ } PWBFR2C; /* */\r
+ union { /* PWBFR2E */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD OTS:1; /* OTS */\r
+ _UWORD :2; /* */\r
+ _UWORD DT9:1; /* DT9 */\r
+ _UWORD DT8:1; /* DT8 */\r
+ _UWORD DT7:1; /* DT7 */\r
+ _UWORD DT6:1; /* DT6 */\r
+ _UWORD DT5:1; /* DT5 */\r
+ _UWORD DT4:1; /* DT4 */\r
+ _UWORD DT3:1; /* DT3 */\r
+ _UWORD DT2:1; /* DT2 */\r
+ _UWORD DT1:1; /* DT1 */\r
+ _UWORD DT0:1; /* DT0 */\r
+ } BIT; /* */\r
+ } PWBFR2E; /* */\r
+ union { /* PWBFR2G */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD OTS:1; /* OTS */\r
+ _UWORD :2; /* */\r
+ _UWORD DT9:1; /* DT9 */\r
+ _UWORD DT8:1; /* DT8 */\r
+ _UWORD DT7:1; /* DT7 */\r
+ _UWORD DT6:1; /* DT6 */\r
+ _UWORD DT5:1; /* DT5 */\r
+ _UWORD DT4:1; /* DT4 */\r
+ _UWORD DT3:1; /* DT3 */\r
+ _UWORD DT2:1; /* DT2 */\r
+ _UWORD DT1:1; /* DT1 */\r
+ _UWORD DT0:1; /* DT0 */\r
+ } BIT; /* */\r
+ } PWBFR2G; /* */\r
+}; /* */\r
+struct st_rqspi { /* struct RQSPI */\r
+ union { /* SPCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SPRIE:1; /* SPRIE */\r
+ _UBYTE SPE:1; /* SPE */\r
+ _UBYTE SPTIE:1; /* SPTIE */\r
+ _UBYTE :5; /* */\r
+ } BIT; /* */\r
+ } SPCR; /* */\r
+ union { /* SSLP */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :7; /* */\r
+ _UBYTE SSLP:1; /* SSLP */\r
+ } BIT; /* */\r
+ } SSLP; /* */\r
+ union { /* SPPCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE MOIFE:1; /* MOIFE */\r
+ _UBYTE MOIFV:1; /* MOIFV */\r
+ _UBYTE :1; /* */\r
+ _UBYTE IO3FV:1; /* IO3FV */\r
+ _UBYTE IO2FV:1; /* IO2FV */\r
+ _UBYTE SPLP:1; /* SPLP */\r
+ } BIT; /* */\r
+ } SPPCR; /* */\r
+ union { /* SPSR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SPRFF:1; /* SPRFF */\r
+ _UBYTE TEND:1; /* TEND */\r
+ _UBYTE SPTEF:1; /* SPTEF */\r
+ _UBYTE :5; /* */\r
+ } BIT; /* */\r
+ } SPSR; /* */\r
+ union { /* SPDR */\r
+ _UDWORD LONG; /* Long Access */\r
+ _UWORD WORD; /* Word Access */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ } SPDR; /* */\r
+ union { /* SPSCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :6; /* */\r
+ _UBYTE SPSC:2; /* SPSC */\r
+ } BIT; /* */\r
+ } SPSCR; /* */\r
+ union { /* SPSSR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :6; /* */\r
+ _UBYTE SPSS:2; /* SPSS */\r
+ } BIT; /* */\r
+ } SPSSR; /* */\r
+ union { /* SPBR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SPBR:8; /* SPBR */\r
+ } BIT; /* */\r
+ } SPBR; /* */\r
+ union { /* SPDCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TXDMY:1; /* TXDMY */\r
+ _UBYTE :7; /* */\r
+ } BIT; /* */\r
+ } SPDCR; /* */\r
+ union { /* SPCKD */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :5; /* */\r
+ _UBYTE SCKDL:3; /* SCKDL */\r
+ } BIT; /* */\r
+ } SPCKD; /* */\r
+ union { /* SSLND */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :5; /* */\r
+ _UBYTE SLNDL:3; /* SLNDL */\r
+ } BIT; /* */\r
+ } SSLND; /* */\r
+ union { /* SPND */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :5; /* */\r
+ _UBYTE SPNDL:3; /* SPNDL */\r
+ } BIT; /* */\r
+ } SPND; /* */\r
+ _UBYTE wk0[1]; /* */\r
+ union { /* SPCMD0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD SCKDEN:1; /* SCKDEN */\r
+ _UWORD SLNDEN:1; /* SLNDEN */\r
+ _UWORD SPNDEN:1; /* SPNDEN */\r
+ _UWORD LSBF:1; /* LSBF */\r
+ _UWORD SPB:4; /* SPB */\r
+ _UWORD SSLKP:1; /* SSLKP */\r
+ _UWORD SPIMOD:2; /* SPIMOD */\r
+ _UWORD SPRW:1; /* SPRW */\r
+ _UWORD BRDV:2; /* BRDV */\r
+ _UWORD CPOL:1; /* CPOL */\r
+ _UWORD CPHA:1; /* CPHA */\r
+ } BIT; /* */\r
+ } SPCMD0; /* */\r
+ union { /* SPCMD1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD SCKDEN:1; /* SCKDEN */\r
+ _UWORD SLNDEN:1; /* SLNDEN */\r
+ _UWORD SPNDEN:1; /* SPNDEN */\r
+ _UWORD LSBF:1; /* LSBF */\r
+ _UWORD SPB:4; /* SPB */\r
+ _UWORD SSLKP:1; /* SSLKP */\r
+ _UWORD SPIMOD:2; /* SPIMOD */\r
+ _UWORD SPRW:1; /* SPRW */\r
+ _UWORD BRDV:2; /* BRDV */\r
+ _UWORD CPOL:1; /* CPOL */\r
+ _UWORD CPHA:1; /* CPHA */\r
+ } BIT; /* */\r
+ } SPCMD1 ; /* */\r
+ union { /* SPCMD2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD SCKDEN:1; /* SCKDEN */\r
+ _UWORD SLNDEN:1; /* SLNDEN */\r
+ _UWORD SPNDEN:1; /* SPNDEN */\r
+ _UWORD LSBF:1; /* LSBF */\r
+ _UWORD SPB:4; /* SPB */\r
+ _UWORD SSLKP:1; /* SSLKP */\r
+ _UWORD SPIMOD:2; /* SPIMOD */\r
+ _UWORD SPRW:1; /* SPRW */\r
+ _UWORD BRDV:2; /* BRDV */\r
+ _UWORD CPOL:1; /* CPOL */\r
+ _UWORD CPHA:1; /* CPHA */\r
+ } BIT; /* */\r
+ } SPCMD2 ; /* */\r
+ union { /* SPCMD3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD SCKDEN:1; /* SCKDEN */\r
+ _UWORD SLNDEN:1; /* SLNDEN */\r
+ _UWORD SPNDEN:1; /* SPNDEN */\r
+ _UWORD LSBF:1; /* LSBF */\r
+ _UWORD SPB:4; /* SPB */\r
+ _UWORD SSLKP:1; /* SSLKP */\r
+ _UWORD SPIMOD:2; /* SPIMOD */\r
+ _UWORD SPRW:1; /* SPRW */\r
+ _UWORD BRDV:2; /* BRDV */\r
+ _UWORD CPOL:1; /* CPOL */\r
+ _UWORD CPHA:1; /* CPHA */\r
+ } BIT; /* */\r
+ } SPCMD3 ; /* */\r
+ union { /* SPBFCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TXRST:1; /* TXRST */\r
+ _UBYTE RXRST:1; /* RXRST */\r
+ _UBYTE TXTRG:2; /* TXTRG */\r
+ _UBYTE :1; /* */\r
+ _UBYTE RXTRG:3; /* RXTRG */\r
+ } BIT; /* */\r
+ } SPBFCR; /* */\r
+ _UBYTE wk1[1]; /* */\r
+ union { /* SPBDCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :2; /* */\r
+ _UWORD TXBC:6 ; /* TXBC */\r
+ _UWORD :2; /* */\r
+ _UWORD RXBC:6; /* RXBC */\r
+ } BIT; /* */\r
+ } SPBDCR; /* */\r
+ union { /* SPBMUL0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ } SPBMUL0; /* */\r
+ union { /* SPBMUL1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ } SPBMUL1; /* */\r
+ union { /* SPBMUL2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ } SPBMUL2; /* */\r
+ union { /* SPBMUL3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ } SPBMUL3; /* */\r
+}; /* */\r
+struct st_imrls { /* struct IMRLS */\r
+ union { /* CR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :16; /* */\r
+ _UDWORD SWRST:1; /* SWRST */\r
+ _UDWORD :9; /* */\r
+ _UDWORD RESUME:1; /* RESUME */\r
+ _UDWORD STOP:1; /* STOP */\r
+ _UDWORD :1; /* */\r
+ _UDWORD SFE:1; /* SFE */\r
+ _UDWORD ARS:1; /* ARS */\r
+ _UDWORD RS:1; /* RS */\r
+ } BIT; /* */\r
+ } CR; /* */\r
+ union { /* SR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :25; /* */\r
+ _UDWORD DSA:1; /* DSA */\r
+ _UDWORD :1; /* */\r
+ _UDWORD STP:1; /* STP */\r
+ _UDWORD :1; /* */\r
+ _UDWORD INT:1; /* INT */\r
+ _UDWORD IER:1; /* IER */\r
+ _UDWORD TRA:1; /* TRA */\r
+ } BIT; /* */\r
+ } SR; /* */\r
+ union { /* SRCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD STPCLR:1; /* STPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD INTCLR:1; /* INTCLR */\r
+ _UDWORD IERCLR:1; /* IERCLR */\r
+ _UDWORD TRACLR:1; /* TRACLR */\r
+ } BIT; /* */\r
+ } SRCR; /* */\r
+ union { /* ICR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD STPENB:1; /* STPENB */\r
+ _UDWORD :1; /* */\r
+ _UDWORD INTENB:1; /* INTENB */\r
+ _UDWORD IERENB:1; /* IERENB */\r
+ _UDWORD TRAENB:1; /* TRAENB */\r
+ } BIT; /* */\r
+ } ICR; /* */\r
+ union { /* IMR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :27; /* */\r
+ _UDWORD STM:1; /* STM */\r
+ _UDWORD :1; /* */\r
+ _UDWORD INM:1; /* INM */\r
+ _UDWORD IEM:1; /* IEM */\r
+ _UDWORD TRAM:1; /* TRAM */\r
+ } BIT; /* */\r
+ } IMR; /* */\r
+ _UBYTE wk0[4]; /* */\r
+ union { /* DLPR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DLP:32; /* DLP */\r
+ } BIT; /* */\r
+ } DLPR; /* */\r
+ _UBYTE wk1[12]; /* */\r
+ union { /* DLSAR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DLSA:32; /* DLSA */\r
+ } BIT; /* */\r
+ } DLSAR; /* */\r
+ union { /* DSAR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DSAR:32; /* DSAR */\r
+ } BIT; /* */\r
+ } DSAR; /* */\r
+ _UBYTE wk2[4]; /* */\r
+ union { /* DSTR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :19; /* */\r
+ _UDWORD DSTR:13; /* DSTR */\r
+ } BIT; /* */\r
+ } DSTR; /* */\r
+ _UBYTE wk3[8]; /* */\r
+ union { /* DSAR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DSAR2:32; /* DSAR2 */\r
+ } BIT; /* */\r
+ } DSAR2; /* */\r
+ union { /* DLSAR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DLSA2:32; /* DLSA2 */\r
+ } BIT; /* */\r
+ } DLSAR2; /* */\r
+ _UBYTE wk4[16]; /* */\r
+ union { /* TRIMR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :25; /* */\r
+ _UDWORD TCM:1; /* TCM */\r
+ _UDWORD DUDVM:1; /* DUDVM */\r
+ _UDWORD DXDYM:1; /* DXDYM */\r
+ _UDWORD AUTOSG:1; /* AUTOSG */\r
+ _UDWORD AUTODG:1; /* AUTODG */\r
+ _UDWORD BFE:1; /* BFE */\r
+ _UDWORD TME:1; /* TME */\r
+ } BIT; /* */\r
+ } TRIMR; /* */\r
+ union { /* TRIMSR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :25; /* */\r
+ _UDWORD TCMS:1; /* TCMS */\r
+ _UDWORD DUDVMS:1; /* DUDVMS */\r
+ _UDWORD DXDYMS:1; /* DXDYMS */\r
+ _UDWORD AUTOSGS:1; /* AUTOSGS */\r
+ _UDWORD AUTODGS:1; /* AUTODGS */\r
+ _UDWORD BFES:1; /* BFES */\r
+ _UDWORD TMES:1; /* TMES */\r
+ } BIT; /* */\r
+ } TRIMSR; /* */\r
+ union { /* TRIMCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :25; /* */\r
+ _UDWORD TCMC:1; /* TCMC */\r
+ _UDWORD DUDVMC:1; /* DUDVMC */\r
+ _UDWORD DXDYMC:1; /* DXDYMC */\r
+ _UDWORD AUTOSGC:1; /* AUTOSGC */\r
+ _UDWORD AUTODGC:1; /* AUTODGC */\r
+ _UDWORD BFEC:1; /* BFEC */\r
+ _UDWORD TMEC:1; /* TMEC */\r
+ } BIT; /* */\r
+ } TRIMCR; /* */\r
+ union { /* TRICR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :8; /* */\r
+ _UDWORD TCV:8; /* TCV */\r
+ _UDWORD TCU:8; /* TCU */\r
+ _UDWORD TCY:8; /* TCY */\r
+ } BIT; /* */\r
+ } TRICR; /* */\r
+ union { /* UVDPOR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :23; /* */\r
+ _UDWORD DDP:1; /* DDP */\r
+ _UDWORD :5; /* */\r
+ _UDWORD UVDPO:3; /* UVDPO */\r
+ } BIT; /* */\r
+ } UVDPOR; /* */\r
+ union { /* SUSR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :6; /* */\r
+ _UDWORD SUW:10; /* SUW */\r
+ _UDWORD :6; /* */\r
+ _UDWORD SVW:10; /* SVW */\r
+ } BIT; /* */\r
+ } SUSR; /* */\r
+ union { /* SVSR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :22; /* */\r
+ _UDWORD SVSR:10; /* SVSR */\r
+ } BIT; /* */\r
+ } SVSR; /* */\r
+ _UBYTE wk5[4]; /* */\r
+ union { /* XMINR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :20; /* */\r
+ _UDWORD XMIN:12; /* XMIN */\r
+ } BIT; /* */\r
+ } XMINR; /* */\r
+ union { /* YMINR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :20; /* */\r
+ _UDWORD YMIN:12; /* YMIN */\r
+ } BIT; /* */\r
+ } YMINR; /* */\r
+ union { /* XMAXR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :20; /* */\r
+ _UDWORD XMAX:12; /* XMAX */\r
+ } BIT; /* */\r
+ } XMAXR; /* */\r
+ union { /* YMAXR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :20; /* */\r
+ _UDWORD YMAX:12; /* YMAX */\r
+ } BIT; /* */\r
+ } YMAXR; /* */\r
+ union { /* AMXSR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :22; /* */\r
+ _UDWORD AMXS:10; /* AMXS */\r
+ } BIT; /* */\r
+ } AMXSR; /* */\r
+ union { /* AMYSR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :22; /* */\r
+ _UDWORD AMYS:10; /* AMYS */\r
+ } BIT; /* */\r
+ } AMYSR; /* */\r
+ union { /* AMXOR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :22; /* */\r
+ _UDWORD AMXO:10; /* AMXO */\r
+ } BIT; /* */\r
+ } AMXOR; /* */\r
+ union { /* AMYOR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :22; /* */\r
+ _UDWORD AMYO:10; /* AMYO */\r
+ } BIT; /* */\r
+ } AMYOR; /* */\r
+ union { /* MACR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD QWSWPI:1; /* QWSWPI */\r
+ _UDWORD QWSWPC:1; /* QWSWPC */\r
+ _UDWORD :17; /* */\r
+ _UDWORD EMAM:1; /* EMAM */\r
+ _UDWORD :2; /* */\r
+ _UDWORD LWSWAP:1; /* LWSWAP */\r
+ _UDWORD :9; /* */\r
+ } BIT; /* */\r
+ } MACR1; /* */\r
+ _UBYTE wk6[2396]; /* */\r
+ union { /* LSPR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :22; /* */\r
+ _UDWORD LSPR:10; /* LSPR */\r
+ } BIT; /* */\r
+ } LSPR; /* */\r
+ union { /* LEPR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :22; /* */\r
+ _UDWORD LEPR:10; /* LEPR */\r
+ } BIT; /* */\r
+ } LEPR; /* */\r
+ union { /* LMSR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :29; /* */\r
+ _UDWORD LMSR:3; /* LMSR */\r
+ } BIT; /* */\r
+ } LMSR; /* */\r
+}; /* */\r
+struct st_sdg0 { /* struct SDG0 */\r
+ union { /* SGCR1_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SGST:1; /* SGST */\r
+ _UBYTE STPM:1; /* STPM */\r
+ _UBYTE :1; /* */\r
+ _UBYTE SGCK:2; /* SGCK */\r
+ _UBYTE DPF:3; /* DPF */\r
+ } BIT; /* */\r
+ } SGCR1_0; /* */\r
+ union { /* SGCSR_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SGIE:1; /* SGIE */\r
+ _UBYTE SGDEF:1; /* SGDEF */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } SGCSR_0; /* */\r
+ union { /* SGCR2_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SGEND:1; /* SGEND */\r
+ _UBYTE TCHG:1; /* TCHG */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } SGCR2_0; /* */\r
+ union { /* SGLR_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE LD:8; /* LD */\r
+ } BIT; /* */\r
+ } SGLR_0; /* */\r
+ union { /* SGTFR_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TONE:7; /* TONE */\r
+ } BIT; /* */\r
+ } SGTFR_0; /* */\r
+ union { /* SGSFR_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SFS:8; /* SFS */\r
+ } BIT; /* */\r
+ } SGSFR_0; /* */\r
+}; /* */\r
+struct st_sdg1 { /* struct SDG1 */\r
+ union { /* SGCR1_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SGST:1; /* SGST */\r
+ _UBYTE STPM:1; /* STPM */\r
+ _UBYTE :1; /* */\r
+ _UBYTE SGCK:2; /* SGCK */\r
+ _UBYTE DPF:3; /* DPF */\r
+ } BIT; /* */\r
+ } SGCR1_1; /* */\r
+ union { /* SGCSR_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SGIE:1; /* SGIE */\r
+ _UBYTE SGDEF:1; /* SGDEF */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } SGCSR_1; /* */\r
+ union { /* SGCR2_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SGEND:1; /* SGEND */\r
+ _UBYTE TCHG:1; /* TCHG */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } SGCR2_1; /* */\r
+ union { /* SGLR_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE LD:8; /* LD */\r
+ } BIT; /* */\r
+ } SGLR_1; /* */\r
+ union { /* SGTFR_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TONE:7; /* TONE */\r
+ } BIT; /* */\r
+ } SGTFR_1; /* */\r
+ union { /* SGSFR_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SFS:8; /* SFS */\r
+ } BIT; /* */\r
+ } SGSFR_1; /* */\r
+}; /* */\r
+struct st_sdg2 { /* struct SDG2 */\r
+ union { /* SGCR1_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SGST:1; /* SGST */\r
+ _UBYTE STPM:1; /* STPM */\r
+ _UBYTE :1; /* */\r
+ _UBYTE SGCK:2; /* SGCK */\r
+ _UBYTE DPF:3; /* DPF */\r
+ } BIT; /* */\r
+ } SGCR1_2; /* */\r
+ union { /* SGCSR_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SGIE:1; /* SGIE */\r
+ _UBYTE SGDEF:1; /* SGDEF */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } SGCSR_2; /* */\r
+ union { /* SGCR2_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SGEND:1; /* SGEND */\r
+ _UBYTE TCHG:1; /* TCHG */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } SGCR2_2; /* */\r
+ union { /* SGLR_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE LD:8; /* LD */\r
+ } BIT; /* */\r
+ } SGLR_2; /* */\r
+ union { /* SGTFR_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TONE:7; /* TONE */\r
+ } BIT; /* */\r
+ } SGTFR_2; /* */\r
+ union { /* SGSFR_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SFS:8; /* SFS */\r
+ } BIT; /* */\r
+ } SGSFR_2; /* */\r
+}; /* */\r
+struct st_sdg3 { /* struct SDG3 */\r
+ union { /* SGCR1_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SGST:1; /* SGST */\r
+ _UBYTE STPM:1; /* STPM */\r
+ _UBYTE :1; /* */\r
+ _UBYTE SGCK:2; /* SGCK */\r
+ _UBYTE DPF:3; /* DPF */\r
+ } BIT; /* */\r
+ } SGCR1_3; /* */\r
+ union { /* SGCSR_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SGIE:1; /* SGIE */\r
+ _UBYTE SGDEF:1; /* SGDEF */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } SGCSR_3; /* */\r
+ union { /* SGCR2_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SGEND:1; /* SGEND */\r
+ _UBYTE TCHG:1; /* TCHG */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } SGCR2_3; /* */\r
+ union { /* SGLR_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE LD:8; /* LD */\r
+ } BIT; /* */\r
+ } SGLR_3; /* */\r
+ union { /* SGTFR_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TONE:7; /* TONE */\r
+ } BIT; /* */\r
+ } SGTFR_3; /* */\r
+ union { /* SGSFR_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SFS:8; /* SFS */\r
+ } BIT; /* */\r
+ } SGSFR_3; /* */\r
+}; /* */\r
+struct st_mmc { /* struct MMC */\r
+ union { /* CE_CMD_SET */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD BOOT:1; /* BOOT */\r
+ _UWORD CMD:6; /* CMD */\r
+ _UWORD RTYP:2; /* RTYP */\r
+ _UWORD RBSY:1; /* RBSY */\r
+ _UWORD CCSEN:1; /* CCSEN */\r
+ _UWORD WDAT:1; /* WDAT */\r
+ _UWORD DWEN:1; /* DWEN */\r
+ _UWORD CMLTE:1; /* CMLTE */\r
+ _UWORD CMD12EN:1; /* CMD12EN */\r
+ _UWORD RIDXC:2; /* RIDXC */\r
+ _UWORD RCRC7C:2; /* RCRC7C */\r
+ _UWORD :1; /* */\r
+ _UWORD CRC16C:1; /* CRC16C */\r
+ _UWORD BOOTACK:1; /* BOOTACK */\r
+ _UWORD CRCSTE:1; /* CRCSTE */\r
+ _UWORD TBIT:1; /* TBIT */\r
+ _UWORD OPDM:1; /* OPDM */\r
+ _UWORD CCSH:1; /* CCSH */\r
+ _UWORD :3; /* */\r
+ _UWORD DATW:2; /* DATW */\r
+ } BIT; /* */\r
+ } CE_CMD_SET; /* */\r
+ _UBYTE wk0[4]; /* */\r
+ union { /* CE_ARG */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD ARG:32; /* ARG */\r
+ } BIT; /* */\r
+ } CE_ARG; /* */\r
+ union { /* CE_ARG_CMD12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD C12ARG:32; /* C12ARG */\r
+ } BIT; /* */\r
+ } CE_ARG_CMD12; /* */\r
+ union { /* CE_CMD_CTRL */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :30; /* */\r
+ _UDWORD CCSD:1; /* CCSD */\r
+ _UDWORD BREAK:1; /* BREAK */\r
+ } BIT; /* */\r
+ } CE_CMD_CTRL; /* */\r
+ union { /* CE_BLOCK_SET */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD BLKCNT:16; /* BLKCNT */\r
+ _UWORD BLKSIZ:16; /* BLKSIZ */\r
+ } BIT; /* */\r
+ } CE_BLOCK_SET; /* */\r
+ union { /* CE_CLK_CTRL */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :7; /* */\r
+ _UDWORD CLKEN:1; /* CLKEN */\r
+ _UDWORD :4; /* */\r
+ _UDWORD CLKDIV:4; /* CLKDIV */\r
+ _UDWORD :2; /* */\r
+ _UDWORD SRSPTO:2; /* SRSPTO */\r
+ _UDWORD SRBSYTO:4; /* SRBSYTO */\r
+ _UDWORD SRWDTO:4; /* SRWDTO */\r
+ _UDWORD SCCSTO:4; /* SCCSTO */\r
+ } BIT; /* */\r
+ } CE_CLK_CTRL; /* */\r
+ union { /* CE_BUF_ACC */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD DMAWEN:1; /* DMAWEN */\r
+ _UWORD DMAREN:1; /* DMAREN */\r
+ _UWORD :6; /* */\r
+ _UWORD BUSW:1; /* BUSW */\r
+ _UWORD ATYP:1; /* ATYP */\r
+ _UWORD :16; /* */\r
+ } BIT; /* */\r
+ } CE_BUF_ACC; /* */\r
+ union { /* CE_RESP3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD RSP:32; /* RSP */\r
+ } BIT; /* */\r
+ } CE_RESP3; /* */\r
+ union { /* CE_RESP2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD RSP:32; /* RSP */\r
+ } BIT; /* */\r
+ } CE_RESP2; /* */\r
+ union { /* CE_RESP1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD RSP:32; /* RSP */\r
+ } BIT; /* */\r
+ } CE_RESP1; /* */\r
+ union { /* CE_RESP0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD RSP:32; /* RSP */\r
+ } BIT; /* */\r
+ } CE_RESP0; /* */\r
+ union { /* CE_RESP_CMD12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD RSP12:32; /* RSP12 */\r
+ } BIT; /* */\r
+ } CE_RESP_CMD12; /* */\r
+ union { /* CE_DATA */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD DATA:32; /* DATA */\r
+ } BIT; /* */\r
+ } CE_DATA; /* */\r
+ _UBYTE wk1[8]; /* */\r
+ union { /* CE_INT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :2; /* */\r
+ _UWORD CCSDE:1; /* CCSDE */\r
+ _UWORD :2; /* */\r
+ _UWORD CMD12DRE:1; /* CMD12DRE */\r
+ _UWORD CMD12RBE:1; /* CMD12RBE */\r
+ _UWORD CMD12CRE:1; /* CMD12CRE */\r
+ _UWORD DTRANE:1; /* DTRANE */\r
+ _UWORD BUFRE:1; /* BUFRE */\r
+ _UWORD BUFWEN:1; /* BUFWEN */\r
+ _UWORD BUFREN:1; /* BUFREN */\r
+ _UWORD CCSRCV:1; /* CCSRCV */\r
+ _UWORD :1; /* */\r
+ _UWORD RBSYE:1; /* RBSYE */\r
+ _UWORD CRSPE:1; /* CRSPE */\r
+ _UWORD CMDVIO:1; /* CMDVIO */\r
+ _UWORD BUFVIO:1; /* BUFVIO */\r
+ _UWORD :2; /* */\r
+ _UWORD WDATERR:1; /* WDATERR */\r
+ _UWORD RDATERR:1; /* RDATERR */\r
+ _UWORD RIDXERR:1; /* RIDXERR */\r
+ _UWORD RSPERR:1; /* RSPERR */\r
+ _UWORD :2; /* */\r
+ _UWORD CCSTO:1; /* CCSTO */\r
+ _UWORD CRCSTO:1; /* CRCSTO */\r
+ _UWORD WDATTO:1; /* WDATTO */\r
+ _UWORD RDATTO:1; /* RDATTO */\r
+ _UWORD RBSYTO:1; /* RBSYTO */\r
+ _UWORD RSPTO:1; /* RSPTO */\r
+ } BIT; /* */\r
+ } CE_INT; /* */\r
+ union { /* CE_INT_EN */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD :2; /* */\r
+ _UWORD MCCSDE:1; /* MCCSDE */\r
+ _UWORD :2; /* */\r
+ _UWORD MCMD12DRE:1; /* MCMD12DRE */\r
+ _UWORD MCMD12RBE:1; /* MCMD12RBE */\r
+ _UWORD MCMD12CRE:1; /* MCMD12CRE */\r
+ _UWORD MDTRANE:1; /* MDTRANE */\r
+ _UWORD MBUFRE:1; /* MBUFRE */\r
+ _UWORD MBUFWEN:1; /* MBUFWEN */\r
+ _UWORD MBUFREN:1; /* MBUFREN */\r
+ _UWORD MCCSRCV:1; /* MCCSRCV */\r
+ _UWORD :1; /* */\r
+ _UWORD MRBSYE:1; /* MRBSYE */\r
+ _UWORD MCRSPE:1; /* MCRSPE */\r
+ _UWORD MCMDVIO:1; /* MCMDVIO */\r
+ _UWORD MBUFVIO:1; /* MBUFVIO */\r
+ _UWORD :2; /* */\r
+ _UWORD MWDATERR:1; /* MWDATERR */\r
+ _UWORD MRDATERR:1; /* MRDATERR */\r
+ _UWORD MRIDXERR:1; /* MRIDXERR */\r
+ _UWORD MRSPERR:1; /* MRSPERR */\r
+ _UWORD :2; /* */\r
+ _UWORD MCCSTO:1; /* MCCSTO */\r
+ _UWORD MCRCSTO:1; /* MCRCSTO */\r
+ _UWORD MWDATTO:1; /* MWDATTO */\r
+ _UWORD MRDATTO:1; /* MRDATTO */\r
+ _UWORD MRBSYTO:1; /* MRBSYTO */\r
+ _UWORD MRSPTO:1; /* MRSPTO */\r
+ } BIT; /* */\r
+ } CE_INT_EN; /* */\r
+ union { /* CE_HOST_STS1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD CMDSEQ:1; /* CMDSEQ */\r
+ _UWORD CMDSIG:1; /* CMDSIG */\r
+ _UWORD RSPIDX:6; /* RSPIDX */\r
+ _UWORD DATSIG:8; /* DATSIG */\r
+ _UWORD RCVBLK:16; /* RCVBLK */\r
+ } BIT; /* */\r
+ } CE_HOST_STS1; /* */\r
+ union { /* CE_HOST_STS2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD CRCSTE:1; /* CRCSTE */\r
+ _UWORD CRC16E:1; /* CRC16E */\r
+ _UWORD AC12CRCE:1; /* AC12CRCE */\r
+ _UWORD RSPCRC7E:1; /* RSPCRC7E */\r
+ _UWORD CRCSTEBE:1; /* CRCSTEBE */\r
+ _UWORD RDATEBE:1; /* RDATEBE */\r
+ _UWORD AC12REBE:1; /* AC12REBE */\r
+ _UWORD RSPEBE:1; /* RSPEBE */\r
+ _UWORD AC12IDXE:1; /* AC12IDXE */\r
+ _UWORD RSPIDXE:1; /* RSPIDXE */\r
+ _UWORD BTACKPATE:1; /* BTACKPATE */\r
+ _UWORD BTACKEBE:1; /* BTACKEBE */\r
+ _UWORD :1; /* */\r
+ _UWORD CRCST:3; /* CRCST */\r
+ _UWORD STCCSTO:1; /* STCCSTO */\r
+ _UWORD STRDATTO:1; /* STRDATTO */\r
+ _UWORD DATBSYTO:1; /* DATBSYTO */\r
+ _UWORD CRCSTTO:1; /* CRCSTTO */\r
+ _UWORD AC12BSYTO:1; /* AC12BSYTO */\r
+ _UWORD RSPBSYTO:1; /* RSPBSYTO */\r
+ _UWORD AC12RSPTO:1; /* AC12RSPTO */\r
+ _UWORD STRSPTO:1; /* STRSPTO */\r
+ _UWORD BTACKTO:1; /* BTACKTO */\r
+ _UWORD FSTBTDATTO:1; /* FSTBTDATTO */\r
+ _UWORD BTDATTO:1; /* BTDATTO */\r
+ _UWORD :5; /* */\r
+ } BIT; /* */\r
+ } CE_HOST_STS2; /* */\r
+ _UBYTE wk2_0[12]; /* */\r
+ union { /* CE_DMA_MODE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD DMASEL:1; /* DMASEL */\r
+ } BIT; /* */\r
+ } CE_DMA_MODE; /* */\r
+ _UBYTE wk2_1[16]; /* */\r
+ union { /* CE_DETECT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :17; /* */\r
+ _UDWORD CDSIG:1; /* CDSIG */\r
+ _UDWORD CDRISE:1; /* CDRISE */\r
+ _UDWORD CDFALL:1; /* CDFALL */\r
+ _UDWORD :6; /* */\r
+ _UDWORD MCDRISE:1; /* MCDRISE */\r
+ _UDWORD MCDFALL:1; /* MCDFALL */\r
+ _UDWORD :4; /* */\r
+ } BIT; /* */\r
+ } CE_DETECT; /* */\r
+ union { /* CE_ADD_MODE */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD :12; /* */\r
+ _UDWORD CLKMAIN:1; /* CLKMAIN */\r
+ _UDWORD :19; /* */\r
+ } BIT; /* */\r
+ } CE_ADD_MODE; /* */\r
+ _UBYTE wk3[4]; /* */\r
+ union { /* CE_VERSION */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Bit Access */\r
+ _UWORD SWRST:1; /* SWRST */\r
+ _UWORD :15; /* */\r
+ _UWORD VERSION:16; /* VERSION */\r
+ } BIT; /* */\r
+ } CE_VERSION; /* */\r
+}; /* */\r
+struct st_dvdec { /* struct DVDEC */\r
+ union { /* ADCCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :7; /* */\r
+ _UWORD AGCMODE:1; /* AGCMODE */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } ADCCR1; /* */\r
+ _UBYTE wk0[4]; /* */\r
+ union { /* TGCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :7; /* */\r
+ _UWORD SRCLEFT:9; /* SRCLEFT */\r
+ } BIT; /* */\r
+ } TGCR1; /* */\r
+ union { /* TGCR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD SRCTOP:6; /* SRCTOP */\r
+ _UWORD SRCHEIGHT:10; /* SRCHEIGHT */\r
+ } BIT; /* */\r
+ } TGCR2; /* */\r
+ union { /* TGCR3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD SRCWIDTH:11; /* SRCWIDTH */\r
+ } BIT; /* */\r
+ } TGCR3; /* */\r
+ _UBYTE wk1[6]; /* */\r
+ union { /* SYNSCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD LPFVSYNC:3; /* LPFVSYNC */\r
+ _UWORD LPFHSYNC:3; /* LPFHSYNC */\r
+ _UWORD :2; /* */\r
+ _UWORD VELOCITYSHIFT_H:4; /* VELOCITYSHIFT_H */\r
+ _UWORD SLICERMODE_H:2; /* SLICERMODE_H */\r
+ _UWORD SLICERMODE_V:2; /* SLICERMODE_V */\r
+ } BIT; /* */\r
+ } SYNSCR1; /* */\r
+ union { /* SYNSCR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :4; /* */\r
+ _UWORD SYNCMAXDUTY_H:6; /* SYNCMAXDUTY_H */\r
+ _UWORD SYNCMINDUTY_H:6; /* SYNCMINDUTY_H */\r
+ } BIT; /* */\r
+ } SYNSCR2; /* */\r
+ union { /* SYNSCR3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :2; /* */\r
+ _UWORD SSCLIPSEL:4; /* SSCLIPSEL */\r
+ _UWORD CSYNCSLICE_H:10; /* CSYNCSLICE_H */\r
+ } BIT; /* */\r
+ } SYNSCR3; /* */\r
+ union { /* SYNSCR4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :4; /* */\r
+ _UWORD SYNCMAXDUTY_V:6; /* SYNCMAXDUTY_V */\r
+ _UWORD SYNCMINDUTY_V:6; /* SYNCMINDUTY_V */\r
+ } BIT; /* */\r
+ } SYNSCR4; /* */\r
+ union { /* SYNSCR5 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD VSYNCDELAY:1; /* VSYNCDELAY */\r
+ _UWORD VSYNCSLICE:5; /* VSYNCSLICE */\r
+ _UWORD CSYNCSLICE_V:10; /* CSYNCSLICE_V */\r
+ } BIT; /* */\r
+ } SYNSCR5; /* */\r
+ union { /* HAFCCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD HAFCGAIN:4; /* HAFCGAIN */\r
+ _UWORD :1; /* */\r
+ _UWORD HAFCFREERUN:1; /* HAFCFREERUN */\r
+ _UWORD HAFCTYP:10; /* HAFCTYP */\r
+ } BIT; /* */\r
+ } HAFCCR1; /* */\r
+ union { /* HAFCCR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD HAFCSTART:4; /* HAFCSTART */\r
+ _UWORD NOX2HOSC:1; /* NOX2HOSC */\r
+ _UWORD DOX2HOSC:1; /* DOX2HOSC */\r
+ _UWORD HAFCMAX:10; /* HAFCMAX */\r
+ } BIT; /* */\r
+ } HAFCCR2; /* */\r
+ union { /* HAFCCR3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD HAFCEND:4; /* HAFCEND */\r
+ _UWORD HAFCMODE:2; /* HAFCMODE */\r
+ _UWORD HAFCMIN:10; /* HAFCMIN */\r
+ } BIT; /* */\r
+ } HAFCCR3; /* */\r
+ union { /* VCDWCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD VCDFREERUN:1; /* VCDFREERUN */\r
+ _UWORD NOVCD50:1; /* NOVCD50 */\r
+ _UWORD NOVCD60:1; /* NOVCD60 */\r
+ _UWORD VCDDEFAULT:2; /* VCDDEFAULT */\r
+ _UWORD VCDWINDOW:6; /* VCDWINDOW */\r
+ _UWORD VCDOFFSET:5; /* VCDOFFSET */\r
+ } BIT; /* */\r
+ } VCDWCR1; /* */\r
+ _UBYTE wk2[4]; /* */\r
+ union { /* DCPCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD DCPMODE_Y:1; /* DCPMODE_Y */\r
+ _UWORD :3; /* */\r
+ _UWORD DCPCHECK:1; /* DCPCHECK */\r
+ _UWORD :1; /* */\r
+ _UWORD BLANKLEVEL_Y:10; /* BLANKLEVEL_Y */\r
+ } BIT; /* */\r
+ } DCPCR1; /* */\r
+ union { /* DCPCR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD DCPMODE_C:1; /* DCPMODE_C */\r
+ _UWORD :3; /* */\r
+ _UWORD BLANKLEVEL_CB:6; /* BLANKLEVEL_CB */\r
+ _UWORD BLANKLEVEL_CR:6; /* BLANKLEVEL_CR */\r
+ } BIT; /* */\r
+ } DCPCR2; /* */\r
+ union { /* DCPCR3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD DCPRESPONSE:3; /* DCPRESPONSE */\r
+ _UWORD :12; /* */\r
+ } BIT; /* */\r
+ } DCPCR3; /* */\r
+ union { /* DCPCR4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD DCPSTART:6; /* DCPSTART */\r
+ _UWORD :10; /* */\r
+ } BIT; /* */\r
+ } DCPCR4; /* */\r
+ union { /* DCPCR5 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD DCPEND:6; /* DCPEND */\r
+ _UWORD :10; /* */\r
+ } BIT; /* */\r
+ } DCPCR5; /* */\r
+ union { /* DCPCR6 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD DCPWIDTH:7; /* DCPWIDTH */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } DCPCR6; /* */\r
+ union { /* DCPCR7 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD DCPPOS_Y:8; /* DCPPOS_Y */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } DCPCR7; /* */\r
+ union { /* DCPCR8 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD DCPPOS_C:8; /* DCPPOS_C */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } DCPCR8; /* */\r
+ union { /* NSDCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :2; /* */\r
+ _UWORD ACFINPUT:2; /* ACFINPUT */\r
+ _UWORD :3; /* */\r
+ _UWORD ACFLAGTIME:5; /* ACFLAGTIME */\r
+ _UWORD :2; /* */\r
+ _UWORD ACFFILTER:2; /* ACFFILTER */\r
+ } BIT; /* */\r
+ } NSDCR; /* */\r
+ union { /* BTLCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD LOCKRANGE:2; /* LOCKRANGE */\r
+ _UWORD LOOPGAIN:2; /* LOOPGAIN */\r
+ _UWORD LOCKLIMIT:2; /* LOCKLIMIT */\r
+ _UWORD BCOFREERUN:1; /* BCOFREERUN */\r
+ _UWORD :1; /* */\r
+ _UWORD DEFAULTSYS:2; /* DEFAULTSYS */\r
+ _UWORD NONTSC358:1; /* NONTSC358 */\r
+ _UWORD NONTSC443:1; /* NONTSC443 */\r
+ _UWORD NOPALM:1; /* NOPALM */\r
+ _UWORD NOPALN:1; /* NOPALN */\r
+ _UWORD NOPAL443:1; /* NOPAL443 */\r
+ _UWORD NOSECAM:1; /* NOSECAM */\r
+ } BIT; /* */\r
+ } BTLCR; /* */\r
+ union { /* BTGPCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BGPCHECK:1; /* BGPCHECK */\r
+ _UWORD BGPWIDTH:7; /* BGPWIDTH */\r
+ _UWORD BGPSTART:8; /* BGPSTART */\r
+ } BIT; /* */\r
+ } BTGPCR; /* */\r
+ union { /* ACCCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD KILLEROFFSET:4; /* KILLEROFFSET */\r
+ _UWORD ACCMODE:1; /* ACCMODE */\r
+ _UWORD ACCMAXGAIN:2; /* ACCMAXGAIN */\r
+ _UWORD ACCLEVEL:9; /* ACCLEVEL */\r
+ } BIT; /* */\r
+ } ACCCR1; /* */\r
+ union { /* ACCCR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :5; /* */\r
+ _UWORD CHROMASUBGAIN:2; /* CHROMASUBGAIN */\r
+ _UWORD CHROMAMAINGAIN:9; /* CHROMAMAINGAIN */\r
+ } BIT; /* */\r
+ } ACCCR2; /* */\r
+ union { /* ACCCR3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD ACCRESPONSE:2; /* ACCRESPONSE */\r
+ _UWORD ACCPRECIS:6; /* ACCPRECIS */\r
+ _UWORD KILLERMODE:1; /* KILLERMODE */\r
+ _UWORD KILLERLEVEL:6; /* KILLERLEVEL */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } ACCCR3; /* */\r
+ union { /* TINTCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD TINTSUB:6; /* TINTSUB */\r
+ _UWORD TINTMAIN:10; /* TINTMAIN */\r
+ } BIT; /* */\r
+ } TINTCR; /* */\r
+ union { /* YCDCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :7; /* */\r
+ _UWORD LUMADELAY:5; /* LUMADELAY */\r
+ _UWORD :1; /* */\r
+ _UWORD CHROMALPF:1; /* CHROMALPF */\r
+ _UWORD DEMODMODE:2; /* DEMODMODE */\r
+ } BIT; /* */\r
+ } YCDCR; /* */\r
+ union { /* AGCCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :2; /* */\r
+ _UWORD DOREDUCE:1; /* DOREDUCE */\r
+ _UWORD NOREDUCE:1; /* NOREDUCE */\r
+ _UWORD AGCRESPONSE:3; /* AGCRESPONSE */\r
+ _UWORD AGCLEVEL:9; /* AGCLEVEL */\r
+ } BIT; /* */\r
+ } AGCCR1; /* */\r
+ union { /* AGCCR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :2; /* */\r
+ _UWORD AGCPRECIS:6; /* AGCPRECIS */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } AGCCR2; /* */\r
+ union { /* PKLIMITCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PEAKLEVEL:2; /* PEAKLEVEL */\r
+ _UWORD PEAKATTACK:2; /* PEAKATTACK */\r
+ _UWORD PEAKRELEASE:2; /* PEAKRELEASE */\r
+ _UWORD PEAKRATIO:2; /* PEAKRATIO */\r
+ _UWORD MAXPEAKSAMPLES:8; /* MAXPEAKSAMPLES */\r
+ } BIT; /* */\r
+ } PKLIMITCR; /* */\r
+ union { /* RGORCR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD RADJ_O_LEVEL0:10; /* RADJ_O_LEVEL0 */\r
+ } BIT; /* */\r
+ } RGORCR1; /* */\r
+ union { /* RGORCR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD RADJ_U_LEVEL0:10; /* RADJ_U_LEVEL0 */\r
+ } BIT; /* */\r
+ } RGORCR2; /* */\r
+ union { /* RGORCR3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD RADJ_O_LEVEL1:10; /* RADJ_O_LEVEL1 */\r
+ } BIT; /* */\r
+ } RGORCR3; /* */\r
+ union { /* RGORCR4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD RADJ_U_LEVEL1:10; /* RADJ_U_LEVEL1 */\r
+ } BIT; /* */\r
+ } RGORCR4; /* */\r
+ union { /* RGORCR5 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD RADJ_O_LEVEL2:10; /* RADJ_O_LEVEL2 */\r
+ } BIT; /* */\r
+ } RGORCR5; /* */\r
+ union { /* RGORCR6 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD RADJ_U_LEVEL2:10; /* RADJ_U_LEVEL2 */\r
+ } BIT; /* */\r
+ } RGORCR6; /* */\r
+ union { /* RGORCR7 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD TEST_MONI:3; /* TEST_MONI */\r
+ _UWORD RADJ_MIX_K_FIX:3; /* RADJ_MIX_K_FIX */\r
+ _UWORD :6; /* */\r
+ _UWORD UCMP_SW:1; /* UCMP_SW */\r
+ _UWORD DCMP_SW:1; /* DCMP_SW */\r
+ _UWORD HWIDE_SW:1; /* HWIDE_SW */\r
+ } BIT; /* */\r
+ } RGORCR7; /* */\r
+ _UBYTE wk3[24]; /* */\r
+ union { /* AFCPFCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :11; /* */\r
+ _UWORD PHDET_FIX:1; /* PHDET_FIX */\r
+ _UWORD :1; /* */\r
+ _UWORD PHDET_DIV:3; /* PHDET_DIV */\r
+ } BIT; /* */\r
+ } AFCPFCR; /* */\r
+ union { /* RUPDCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD NEWSETTING:1; /* NEWSETTING */\r
+ _UWORD :15; /* */\r
+ } BIT; /* */\r
+ } RUPDCR; /* */\r
+ union { /* VSYNCSR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD FHCOUNT_L:1; /* FHCOUNT_L */\r
+ _UWORD FHLOCK:1; /* FHLOCK */\r
+ _UWORD ISNOISY:1; /* ISNOISY */\r
+ _UWORD FHMODE:1; /* FHMODE */\r
+ _UWORD NOSIGNAL:1; /* NOSIGNAL */\r
+ _UWORD FVLOCK:1; /* FVLOCK */\r
+ _UWORD FVMODE:1; /* FVMODE */\r
+ _UWORD INTERLACED:1; /* INTERLACED */\r
+ _UWORD FVCOUNT:8; /* FVCOUNT */\r
+ } BIT; /* */\r
+ } VSYNCSR; /* */\r
+ union { /* HSYNCSR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD FHCOUNT_H:16; /* FHCOUNT_H */\r
+ } BIT; /* */\r
+ } HSYNCSR; /* */\r
+ union { /* DCPSR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD CLAMPLEVEL_CB:6; /* CLAMPLEVEL_CB */\r
+ _UWORD CLAMPLEVEL_Y:10; /* CLAMPLEVEL_Y */\r
+ } BIT; /* */\r
+ } DCPSR1; /* */\r
+ union { /* DCPSR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD CLAMPLEVEL_CR:6; /* CLAMPLEVEL_CR */\r
+ _UWORD :10; /* */\r
+ } BIT; /* */\r
+ } DCPSR2; /* */\r
+ _UBYTE wk4[4]; /* */\r
+ union { /* NSDSR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD ACFSTRENGTH:16; /* ACFSTRENGTH */\r
+ } BIT; /* */\r
+ } NSDSR; /* */\r
+ union { /* CROMASR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD COLORSYS:2; /* COLORSYS */\r
+ _UWORD FSCMODE:1; /* FSCMODE */\r
+ _UWORD FSCLOCK:1; /* FSCLOCK */\r
+ _UWORD NOBURST:1; /* NOBURST */\r
+ _UWORD ACCSUBGAIN:2; /* ACCSUBGAIN */\r
+ _UWORD ACCMAINGAIN:9; /* ACCMAINGAIN */\r
+ } BIT; /* */\r
+ } CROMASR1; /* */\r
+ union { /* CROMASR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD ISSECAM:1; /* ISSECAM */\r
+ _UWORD ISPAL:1; /* ISPAL */\r
+ _UWORD ISNTSC:1; /* ISNTSC */\r
+ _UWORD :2; /* */\r
+ _UWORD LOCKLEVEL:8; /* LOCKLEVEL */\r
+ } BIT; /* */\r
+ } CROMASR2; /* */\r
+ union { /* SYNCSSR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD ISREDUCED:1; /* ISREDUCED */\r
+ _UWORD :2; /* */\r
+ _UWORD SYNCDEPTH:10; /* SYNCDEPTH */\r
+ } BIT; /* */\r
+ } SYNCSSR; /* */\r
+ union { /* AGCCSR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD HIGHSAMPLES:8; /* HIGHSAMPLES */\r
+ _UWORD PEAKSAMPLES:8; /* PEAKSAMPLES */\r
+ } BIT; /* */\r
+ } AGCCSR1; /* */\r
+ union { /* AGCCSR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :7; /* */\r
+ _UWORD AGCCONVERGE:1; /* AGCCONVERGE */\r
+ _UWORD AGCGAIN:8; /* AGCGAIN */\r
+ } BIT; /* */\r
+ } AGCCSR2; /* */\r
+ _UBYTE wk5[14]; /* */\r
+ _UBYTE wk6[90]; /* */\r
+ _UBYTE wk7[4]; /* */\r
+ union { /* YCSCR3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD K15:4; /* K15 */\r
+ _UWORD K13:6; /* K13 */\r
+ _UWORD K11:6; /* K11 */\r
+ } BIT; /* */\r
+ } YCSCR3; /* */\r
+ union { /* YCSCR4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD K16:4; /* K16 */\r
+ _UWORD K14:6; /* K14 */\r
+ _UWORD K12:6; /* K12 */\r
+ } BIT; /* */\r
+ } YCSCR4; /* */\r
+ union { /* YCSCR5 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD K22A:8; /* K22A */\r
+ _UWORD :2; /* */\r
+ _UWORD K21A:6; /* K21A */\r
+ } BIT; /* */\r
+ } YCSCR5; /* */\r
+ union { /* YCSCR6 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD K22B:8; /* K22B */\r
+ _UWORD :2; /* */\r
+ _UWORD K21B:6; /* K21B */\r
+ } BIT; /* */\r
+ } YCSCR6; /* */\r
+ union { /* YCSCR7 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD K23B:4; /* K23B */\r
+ _UWORD K23A:4; /* K23A */\r
+ _UWORD :3; /* */\r
+ _UWORD K24:5; /* K24 */\r
+ } BIT; /* */\r
+ } YCSCR7; /* */\r
+ union { /* YCSCR8 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD HBPF_NARROW:1; /* HBPF_NARROW */\r
+ _UWORD HVBPF_NARROW:1; /* HVBPF_NARROW */\r
+ _UWORD HBPF1_9TAP_ON:1; /* HBPF1_9TAP_ON */\r
+ _UWORD HVBPF1_9TAP_ON:1; /* HVBPF1_9TAP_ON */\r
+ _UWORD HFIL_TAP_SEL:1; /* HFIL_TAP_SEL */\r
+ _UWORD :11; /* */\r
+ } BIT; /* */\r
+ } YCSCR8; /* */\r
+ union { /* YCSCR9 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD DET2_ON:1; /* DET2_ON */\r
+ _UWORD :3; /* */\r
+ _UWORD HSEL_MIX_Y:4; /* HSEL_MIX_Y */\r
+ _UWORD VSEL_MIX_Y:4; /* VSEL_MIX_Y */\r
+ _UWORD HVSEL_MIX_Y:4; /* HVSEL_MIX_Y */\r
+ } BIT; /* */\r
+ } YCSCR9; /* */\r
+ _UBYTE wk8[2]; /* */\r
+ union { /* YCSCR11 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :7; /* */\r
+ _UWORD V_Y_LEVEL:9; /* V_Y_LEVEL */\r
+ } BIT; /* */\r
+ } YCSCR11; /* */\r
+ union { /* YCSCR12 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD DET2_MIX_C:4; /* DET2_MIX_C */\r
+ _UWORD DET2_MIX_Y:4; /* DET2_MIX_Y */\r
+ _UWORD :4; /* */\r
+ _UWORD FIL2_MODE_2D:2; /* FIL2_MODE_2D */\r
+ _UWORD :1; /* */\r
+ _UWORD FIL2_NARROW_2D:1; /* FIL2_NARROW_2D */\r
+ } BIT; /* */\r
+ } YCSCR12; /* */\r
+ _UBYTE wk9[104]; /* */\r
+ union { /* DCPCR9 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD CLP_HOLD_ON_Y:1; /* CLP_HOLD_ON_Y */\r
+ _UWORD CLP_HOLD_ON_CB:1; /* CLP_HOLD_ON_CB */\r
+ _UWORD CLP_HOLD_ON_CR:1; /* CLP_HOLD_ON_CR */\r
+ _UWORD :10; /* */\r
+ } BIT; /* */\r
+ } DCPCR9; /* */\r
+ _UBYTE wk10[12]; /* */\r
+ _UBYTE wk11[4]; /* */\r
+ union { /* YCTWA_F0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WA_F0:13; /* FIL2_2D_WA_F0 */\r
+ } BIT; /* */\r
+ } YCTWA_F0; /* */\r
+ union { /* YCTWA_F1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WA_F1:13; /* FIL2_2D_WA_F1 */\r
+ } BIT; /* */\r
+ } YCTWA_F1; /* */\r
+ union { /* YCTWA_F2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WA_F2:13; /* FIL2_2D_WA_F2 */\r
+ } BIT; /* */\r
+ } YCTWA_F2; /* */\r
+ union { /* YCTWA_F3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WA_F3:13; /* FIL2_2D_WA_F3 */\r
+ } BIT; /* */\r
+ } YCTWA_F3; /* */\r
+ union { /* YCTWA_F4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WA_F4:13; /* FIL2_2D_WA_F4 */\r
+ } BIT; /* */\r
+ } YCTWA_F4; /* */\r
+ union { /* YCTWA_F5 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WA_F5:13; /* FIL2_2D_WA_F5 */\r
+ } BIT; /* */\r
+ } YCTWA_F5; /* */\r
+ union { /* YCTWA_F6 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WA_F6:13; /* FIL2_2D_WA_F6 */\r
+ } BIT; /* */\r
+ } YCTWA_F6; /* */\r
+ union { /* YCTWA_F7 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WA_F7:13; /* FIL2_2D_WA_F7 */\r
+ } BIT; /* */\r
+ } YCTWA_F7; /* */\r
+ union { /* YCTWA_F8 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WA_F8:13; /* FIL2_2D_WA_F8 */\r
+ } BIT; /* */\r
+ } YCTWA_F8; /* */\r
+ union { /* YCTWB_F0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WB_F0:13; /* FIL2_2D_WB_F0 */\r
+ } BIT; /* */\r
+ } YCTWB_F0; /* */\r
+ union { /* YCTWB_F1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WB_F1:13; /* FIL2_2D_WB_F1 */\r
+ } BIT; /* */\r
+ } YCTWB_F1; /* */\r
+ union { /* YCTWB_F2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WB_F2:13; /* FIL2_2D_WB_F2 */\r
+ } BIT; /* */\r
+ } YCTWB_F2; /* */\r
+ union { /* YCTWB_F3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WB_F3:13; /* FIL2_2D_WB_F3 */\r
+ } BIT; /* */\r
+ } YCTWB_F3; /* */\r
+ union { /* YCTWB_F4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WB_F4:13; /* FIL2_2D_WB_F4 */\r
+ } BIT; /* */\r
+ } YCTWB_F4; /* */\r
+ union { /* YCTWB_F5 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WB_F5:13; /* FIL2_2D_WB_F5 */\r
+ } BIT; /* */\r
+ } YCTWB_F5; /* */\r
+ union { /* YCTWB_F6 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WB_F6:13; /* FIL2_2D_WB_F6 */\r
+ } BIT; /* */\r
+ } YCTWB_F6; /* */\r
+ union { /* YCTWB_F7 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WB_F7:13; /* FIL2_2D_WB_F7 */\r
+ } BIT; /* */\r
+ } YCTWB_F7; /* */\r
+ union { /* YCTWB_F8 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_WB_F8:13; /* FIL2_2D_WB_F8 */\r
+ } BIT; /* */\r
+ } YCTWB_F8; /* */\r
+ union { /* YCTNA_F0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NA_F0:13; /* FIL2_2D_NA_F0 */\r
+ } BIT; /* */\r
+ } YCTNA_F0; /* */\r
+ union { /* YCTNA_F1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NA_F1:13; /* FIL2_2D_NA_F1 */\r
+ } BIT; /* */\r
+ } YCTNA_F1; /* */\r
+ union { /* YCTNA_F2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NA_F2:13; /* FIL2_2D_NA_F2 */\r
+ } BIT; /* */\r
+ } YCTNA_F2; /* */\r
+ union { /* YCTNA_F3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NA_F3:13; /* FIL2_2D_NA_F3 */\r
+ } BIT; /* */\r
+ } YCTNA_F3; /* */\r
+ union { /* YCTNA_F4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NA_F4:13; /* FIL2_2D_NA_F4 */\r
+ } BIT; /* */\r
+ } YCTNA_F4; /* */\r
+ union { /* YCTNA_F5 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NA_F5:13; /* FIL2_2D_NA_F5 */\r
+ } BIT; /* */\r
+ } YCTNA_F5; /* */\r
+ union { /* YCTNA_F6 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NA_F6:13; /* FIL2_2D_NA_F6 */\r
+ } BIT; /* */\r
+ } YCTNA_F6; /* */\r
+ union { /* YCTNA_F7 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NA_F7:13; /* FIL2_2D_NA_F7 */\r
+ } BIT; /* */\r
+ } YCTNA_F7; /* */\r
+ union { /* YCTNA_F8 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NA_F8:13; /* FIL2_2D_NA_F8 */\r
+ } BIT; /* */\r
+ } YCTNA_F8; /* */\r
+ union { /* YCTNB_F0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NB_F0:13; /* FIL2_2D_NB_F0 */\r
+ } BIT; /* */\r
+ } YCTNB_F0; /* */\r
+ union { /* YCTNB_F1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NB_F1:13; /* FIL2_2D_NB_F1 */\r
+ } BIT; /* */\r
+ } YCTNB_F1; /* */\r
+ union { /* YCTNB_F2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NB_F2:13; /* FIL2_2D_NB_F2 */\r
+ } BIT; /* */\r
+ } YCTNB_F2; /* */\r
+ union { /* YCTNB_F3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NB_F3:13; /* FIL2_2D_NB_F3 */\r
+ } BIT; /* */\r
+ } YCTNB_F3; /* */\r
+ union { /* YCTNB_F4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NB_F4:13; /* FIL2_2D_NB_F4 */\r
+ } BIT; /* */\r
+ } YCTNB_F4; /* */\r
+ union { /* YCTNB_F5 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NB_F5:13; /* FIL2_2D_NB_F5 */\r
+ } BIT; /* */\r
+ } YCTNB_F5; /* */\r
+ union { /* YCTNB_F6 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NB_F6:13; /* FIL2_2D_NB_F6 */\r
+ } BIT; /* */\r
+ } YCTNB_F6; /* */\r
+ union { /* YCTNB_F7 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NB_F7:13; /* FIL2_2D_NB_F7 */\r
+ } BIT; /* */\r
+ } YCTNB_F7; /* */\r
+ union { /* YCTNB_F8 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :3; /* */\r
+ _UWORD FIL2_2D_NB_F8:13; /* FIL2_2D_NB_F8 */\r
+ } BIT; /* */\r
+ } YCTNB_F8; /* */\r
+ _UBYTE wk12[38]; /* */\r
+ union { /* YGAINCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD Y_GAIN2:10; /* Y_GAIN2 */\r
+ } BIT; /* */\r
+ } YGAINCR; /* */\r
+ union { /* CBGAINCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD CB_GAIN2:10; /* CB_GAIN2 */\r
+ } BIT; /* */\r
+ } CBGAINCR; /* */\r
+ union { /* CRGAINCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD CR_GAIN2:10; /* CR_GAIN2 */\r
+ } BIT; /* */\r
+ } CRGAINCR; /* */\r
+ _UBYTE wk13[122]; /* */\r
+ union { /* PGA_UPDATE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :15; /* */\r
+ _UWORD PGA_VEN:1; /* PGA_VEN */\r
+ } BIT; /* */\r
+ } PGA_UPDATE; /* */\r
+ union { /* PGACR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :2; /* */\r
+ _UWORD PGA_GAIN_SEL:1; /* PGA_GAIN_SEL */\r
+ _UWORD PGA_GAIN:5; /* PGA_GAIN */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } PGACR; /* */\r
+ union { /* ADCCR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :15; /* */\r
+ _UWORD ADC_VINSEL:1; /* ADC_VINSEL */\r
+ } BIT; /* */\r
+ } ADCCR2; /* */\r
+}; /* */\r
+struct st_ubc { /* struct UBC */\r
+ union { /* BAR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD BA0_:32; /* BA0_ */\r
+ } BIT; /* */\r
+ } BAR0; /* */\r
+ union { /* BAMR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD BAM0_:32; /* BAM0_ */\r
+ } BIT;\r
+ } BAMR0;\r
+ union { /* BDR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD BD0_:32; /* BD0_ */\r
+ } BIT;\r
+ } BDR0;\r
+ union { /* BDMR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD BDM0_:32; /* BDM0_ */\r
+ } BIT;\r
+ } BDMR0;\r
+ union { /* BAR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD BA1_:32; /* BA1_ */\r
+ } BIT;\r
+ } BAR1;\r
+ union { /* BAMR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD BAM1_:32; /* BAM1_ */\r
+ } BIT;\r
+ } BAMR1;\r
+ union { /* BDR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD BD1_:32; /* BD1_ */\r
+ } BIT;\r
+ } BDR1;\r
+ union { /* BDMR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD BDM1_:32; /* BDM1_ */\r
+ } BIT;\r
+ } BDMR1;\r
+ _UBYTE wk0[128];\r
+ union { /* BBR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :2;\r
+ _UWORD UBID0:1; /* UBID0 */\r
+ _UWORD DBE0:1; /* DBE0 */\r
+ _UWORD :2; /* */\r
+ _UWORD CP0_:2; /* CP0_ */\r
+ _UWORD CD0_:2; /* CD0_ */\r
+ _UWORD ID0_:2; /* ID0_ */\r
+ _UWORD RW0_:2; /* RW0_ */\r
+ _UWORD SZ0_:2; /* SZ0_ */\r
+ } BIT;\r
+ } BBR0;\r
+ _UBYTE wk1[14];\r
+ union { /* BBR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :2; /* */\r
+ _UWORD UBID1:1; /* UBID1 */\r
+ _UWORD DBE1:1; /* DBE1 */\r
+ _UWORD :2; /* */\r
+ _UWORD CP1_:2; /* CP1_ */\r
+ _UWORD CD1_:2; /* CD1_ */\r
+ _UWORD ID1_:2; /* ID1_ */\r
+ _UWORD RW1_:2; /* RW1_ */\r
+ _UWORD SZ1_:2; /* SZ1_ */\r
+ } BIT;\r
+ } BBR1;\r
+ _UBYTE wk2[14];\r
+ union { /* BRCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :12; /* */\r
+ _UDWORD UTOD1:1; /* UTOD1 */\r
+ _UDWORD UTOD0:1; /* UTOD0 */\r
+ _UDWORD CKS:2; /* CKS */\r
+ _UDWORD SCMFC0:1; /* SCMFC0 */\r
+ _UDWORD SCMFC1:1; /* SCMFC1 */\r
+ _UDWORD SCMFD0:1; /* SCMFD0 */\r
+ _UDWORD SCMFD1:1; /* SCMFD1 */\r
+ _UDWORD :5; /* */\r
+ _UDWORD PCB1:1; /* PCB1 */\r
+ _UDWORD PCB0:1; /* PCB0 */\r
+ _UDWORD :5; /* */\r
+ } BIT;\r
+ } BRCR;\r
+};\r
+struct st_disc { /* struct DISC */\r
+ union { /* DOCMCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :15; /* */\r
+ _UDWORD CMPRU:1; /* CMPRU */\r
+ _UDWORD :15; /* */\r
+ _UDWORD CMPR:1; /* CMPR */\r
+ } BIT; /* */\r
+ } DOCMCR; /* */\r
+ union { /* DOCMSTR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD CMPST:1; /* CMPST */\r
+ } BIT; /* */\r
+ } DOCMSTR; /* */\r
+ union { /* DOCMCLSTR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD CMPCLST:1; /* CMPCLST */\r
+ } BIT; /* */\r
+ } DOCMCLSTR; /* */\r
+ union { /* DOCMIENR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :31; /* */\r
+ _UDWORD CMPIEN:1; /* CMPIEN */\r
+ } BIT; /* */\r
+ } DOCMIENR; /* */\r
+ _UBYTE wk0[4]; /* */\r
+ union { /* DOCMPMR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :15; /* */\r
+ _UDWORD CMPBT:1; /* CMPBT */\r
+ _UDWORD CMPDFA:8; /* CMPDFA */\r
+ _UDWORD CMPDAUF:1; /* CMPDAUF */\r
+ _UDWORD :3; /* */\r
+ _UDWORD CMPSELP:4; /* CMPSELP */\r
+ } BIT; /* */\r
+ } DOCMPMR; /* */\r
+ union { /* DOCMECRCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CMPECRC:32; /* CMPECRC */\r
+ } BIT; /* */\r
+ } DOCMECRCR; /* */\r
+ union { /* DOCMCCRCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CMPCCRC:32; /* CMPCCRC */\r
+ } BIT; /* */\r
+ } DOCMCCRCR; /* */\r
+ union { /* DOCMSPXR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :21; /* */\r
+ _UDWORD CMPSPX:11; /* CMPSPX */\r
+ } BIT; /* */\r
+ } DOCMSPXR; /* */\r
+ union { /* DOCMSPYR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :21; /* */\r
+ _UDWORD CMPSPY:11; /* CMPSPY */\r
+ } BIT; /* */\r
+ } DOCMSPYR; /* */\r
+ union { /* DOCMSZXR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :21; /* */\r
+ _UDWORD CMPSZX:11; /* CMPSZX */\r
+ } BIT; /* */\r
+ } DOCMSZXR; /* */\r
+ union { /* DOCMSZYR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :21; /* */\r
+ _UDWORD CMPSZY:11; /* CMPSZY */\r
+ } BIT; /* */\r
+ } DOCMSZYR; /* */\r
+ union { /* DOCMCRCIR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CRCINI:32; /* CRCINI */\r
+ } BIT; /* */\r
+ } DOCMCRCIR; /* */\r
+}; /* */\r
+struct st_jcu { /* struct JCU */\r
+ union { /* JCMOD */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE DSP:1; /* DSP */\r
+ _UBYTE REDU:3; /* REDU */\r
+ } BIT; /* */\r
+ } JCMOD; /* */\r
+ union { /* JCCMD */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE BRST:1; /* BRST */\r
+ _UBYTE :4; /* */\r
+ _UBYTE JEND:1; /* JEND */\r
+ _UBYTE JRST:1; /* JRST */\r
+ _UBYTE JSRT:1; /* JSRT */\r
+ } BIT; /* */\r
+ } JCCMD; /* */\r
+ _UBYTE wk0_0[1]; /* */\r
+ union { /* JCQTN */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE QT3:2; /* QT3 */\r
+ _UBYTE QT2:2; /* QT2 */\r
+ _UBYTE QT1:2; /* QT1 */\r
+ } BIT; /* */\r
+ } JCQTN; /* */\r
+ union { /* JCHTN */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :2; /* */\r
+ _UBYTE HTA3:1; /* HTA3 */\r
+ _UBYTE HTD3:1; /* HTD3 */\r
+ _UBYTE HTA2:1; /* HTA2 */\r
+ _UBYTE HTD2:1; /* HTD2 */\r
+ _UBYTE HTA1:1; /* HTA1 */\r
+ _UBYTE HTD1:1; /* HTD1 */\r
+ } BIT; /* */\r
+ } JCHTN; /* */\r
+ union { /* JCDRIU */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE DRIU:8; /* DRIU */\r
+ } BIT; /* */\r
+ } JCDRIU; /* */\r
+ union { /* JCDRID */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE DRID:8; /* DRID */\r
+ } BIT; /* */\r
+ } JCDRID; /* */\r
+ union { /* JCVSZU */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE VSZU:8; /* VSZU */\r
+ } BIT; /* */\r
+ } JCVSZU; /* */\r
+ union { /* JCVSZD */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE VSZD:8; /* VSZD */\r
+ } BIT; /* */\r
+ } JCVSZD; /* */\r
+ union { /* JCHSZU */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE HSZU:8; /* HSZU */\r
+ } BIT; /* */\r
+ } JCHSZU; /* */\r
+ union { /* JCHSZD */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE HSZD:8; /* HSZD */\r
+ } BIT; /* */\r
+ } JCHSZD; /* */\r
+ union { /* JCDTCU */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE DCU:8; /* DCU */\r
+ } BIT; /* */\r
+ } JCDTCU; /* */\r
+ union { /* JCDTCM */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE DCM:8; /* DCM */\r
+ } BIT; /* */\r
+ } JCDTCM; /* */\r
+ union { /* JCDTCD */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE DCD:8; /* DCD */\r
+ } BIT; /* */\r
+ } JCDTCD; /* */\r
+ union { /* JINTE0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE INT7:1; /* INT7 */\r
+ _UBYTE INT6:1; /* INT6 */\r
+ _UBYTE INT5:1; /* INT5 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE INT3:1; /* INT3 */\r
+ _UBYTE :3; /* */\r
+ } BIT; /* */\r
+ } JINTE0; /* */\r
+ union { /* JINTS0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE INS6:1; /* INS6 */\r
+ _UBYTE INS5:1; /* INS5 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE INS3:1; /* INS3 */\r
+ _UBYTE :3; /* */\r
+ } BIT; /* */\r
+ } JINTS0; /* */\r
+ union { /* JCDERR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE ERR:4; /* ERR */\r
+ } BIT; /* */\r
+ } JCDERR; /* */\r
+ union { /* JCRST */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :7; /* */\r
+ _UBYTE RST:1; /* RST */\r
+ } BIT; /* */\r
+ } JCRST; /* */\r
+ _UBYTE wk0[46]; /* */\r
+ union { /* JIFECNT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :17; /* */\r
+ _UDWORD JOUTRINI:1; /* JOUTRINI */\r
+ _UDWORD JOUTRCMD:1; /* JOUTRCMD */\r
+ _UDWORD JOUTC:1; /* JOUTC */\r
+ _UDWORD :1; /* */\r
+ _UDWORD JOUTSWAP:3; /* JOUTSWAP */\r
+ _UDWORD :1; /* */\r
+ _UDWORD DINRINI:1; /* DINRINI */\r
+ _UDWORD DINRCMD:1; /* DINRCMD */\r
+ _UDWORD DINLC:1; /* DINLC */\r
+ _UDWORD :1; /* */\r
+ _UDWORD DINSWAP:3; /* DINSWAP */\r
+ } BIT; /* */\r
+ } JIFECNT; /* */\r
+ union { /* JIFESA */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ESA:32; /* ESA */\r
+ } BIT; /* */\r
+ } JIFESA; /* */\r
+ union { /* JIFESOFST */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :17; /* */\r
+ _UDWORD ESMW:15; /* ESMW */\r
+ } BIT; /* */\r
+ } JIFESOFST; /* */\r
+ union { /* JIFEDA */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD EDA:32; /* EDA */\r
+ } BIT; /* */\r
+ } JIFEDA; /* */\r
+ union { /* JIFESLC */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :16; /* */\r
+ _UDWORD LINES:16; /* LINES */\r
+ } BIT; /* */\r
+ } JIFESLC; /* */\r
+ union { /* JIFEDDC */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :16; /* */\r
+ _UDWORD JDATAS:16; /* JDATAS */\r
+ } BIT; /* */\r
+ } JIFEDDC; /* */\r
+ union { /* JIFDCNT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :2; /* */\r
+ _UDWORD VINTER:2; /* VINTER */\r
+ _UDWORD HINTER:2; /* HINTER */\r
+ _UDWORD OPF:2; /* OPF */\r
+ _UDWORD :9; /* */\r
+ _UDWORD JINRINI:1; /* JINRINI */\r
+ _UDWORD JINRCMD:1; /* JINRCMD */\r
+ _UDWORD JINC:1; /* JINC */\r
+ _UDWORD :1; /* */\r
+ _UDWORD JINSWAP:3; /* JINSWAP */\r
+ _UDWORD :1; /* */\r
+ _UDWORD DOUTRINI:1; /* DOUTRINI */\r
+ _UDWORD DOUTRCMD:1; /* DOUTRCMD */\r
+ _UDWORD DOUTLC:1; /* DOUTLC */\r
+ _UDWORD :1; /* */\r
+ _UDWORD DOUTSWAP:3; /* DOUTSWAP */\r
+ } BIT; /* */\r
+ } JIFDCNT; /* */\r
+ union { /* JIFDSA */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DSA:32; /* DSA */\r
+ } BIT; /* */\r
+ } JIFDSA; /* */\r
+ union { /* JIFDDOFST */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :17; /* */\r
+ _UDWORD DDMW:15; /* DDMW */\r
+ } BIT; /* */\r
+ } JIFDDOFST; /* */\r
+ union { /* JIFDDA */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DDA:32; /* DDA */\r
+ } BIT; /* */\r
+ } JIFDDA; /* */\r
+ union { /* JIFDSDC */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :16; /* */\r
+ _UDWORD JDATAS:16; /* JDATAS */\r
+ } BIT; /* */\r
+ } JIFDSDC; /* */\r
+ union { /* JIFDDLC */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :16; /* */\r
+ _UDWORD LINES:16; /* LINES */\r
+ } BIT; /* */\r
+ } JIFDDLC; /* */\r
+ union { /* JIFDADT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :24; /* */\r
+ _UDWORD ALPHA:8; /* ALPHA */\r
+ } BIT; /* */\r
+ } JIFDADT; /* */\r
+ _UBYTE wk1[24]; /* */\r
+ union { /* JINTE1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :25; /* */\r
+ _UDWORD CBTEN:1; /* CBTEN */\r
+ _UDWORD DINLEN:1; /* DINLEN */\r
+ _UDWORD JOUTEN:1; /* JOUTEN */\r
+ _UDWORD :1; /* */\r
+ _UDWORD DBTEN:1; /* DBTEN */\r
+ _UDWORD JINEN:1; /* JINEN */\r
+ _UDWORD DOUTLEN:1; /* DOUTLEN */\r
+ } BIT; /* */\r
+ } JINTE1; /* */\r
+ union { /* JINTS1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :25; /* */\r
+ _UDWORD CBTF:1; /* CBTF */\r
+ _UDWORD DINLF:1; /* DINLF */\r
+ _UDWORD JOUTF:1; /* JOUTF */\r
+ _UDWORD :1; /* */\r
+ _UDWORD DBTF:1; /* DBTF */\r
+ _UDWORD JINF:1; /* JINF */\r
+ _UDWORD DOUTLF:1; /* DOUTLF */\r
+ } BIT; /* */\r
+ } JINTS1; /* */\r
+ _UBYTE wk2[108]; /* */\r
+ _UBYTE JCQTBL0[64]; /* JCQTBL0 */\r
+ _UBYTE JCQTBL1[64]; /* JCQTBL1 */\r
+ _UBYTE JCQTBL2[64]; /* JCQTBL2 */\r
+ _UBYTE JCQTBL3[64]; /* JCQTBL3 */\r
+ _UBYTE JCHTBD0[28]; /* JCHTBD0 */\r
+ _UBYTE wk7[4]; /* */\r
+ _UBYTE JCHTBA0[178]; /* JCHTBA0 */\r
+ _UBYTE wk8[46]; /* */\r
+ _UBYTE JCHTBD1[28]; /* JCHTBD1 */\r
+ _UBYTE wk9[4]; /* */\r
+ _UBYTE JCHTBA1[178]; /* JCHTBA1 */\r
+}; /* */\r
+struct st_spibsc { /* struct SPIBSC */\r
+ union { /* CMNCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD MD:1; /* MD */\r
+ _UDWORD :7; /* */\r
+ _UDWORD MOIIO3:2; /* MOIIO3 */\r
+ _UDWORD MOIIO2:2; /* MOIIO2 */\r
+ _UDWORD MOIIO1:2; /* MOIIO1 */\r
+ _UDWORD MOIIO0:2; /* MOIIO0 */\r
+ _UDWORD IO3FV:2; /* IO3FV */\r
+ _UDWORD IO2FV:2; /* IO2FV */\r
+ _UDWORD :2; /* */\r
+ _UDWORD IO0FV:2; /* IO0FV */\r
+ _UDWORD :1; /* */\r
+ _UDWORD CPHAT:1; /* CPHAT */\r
+ _UDWORD CPHAR:1; /* CPHAR */\r
+ _UDWORD SSLP:1; /* SSLP */\r
+ _UDWORD CPOL:1; /* CPOL */\r
+ _UDWORD :1; /* */\r
+ _UDWORD BSZ:2; /* BSZ */\r
+ } BIT; /* */\r
+ } CMNCR; /* */\r
+ union { /* SSLDR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :13; /* */\r
+ _UDWORD SPNDL:3; /* SPNDL */\r
+ _UDWORD :5; /* */\r
+ _UDWORD SLNDL:3; /* SLNDL */\r
+ _UDWORD :5; /* */\r
+ _UDWORD SCKDL:3; /* SCKDL */\r
+ } BIT; /* */\r
+ } SSLDR; /* */\r
+ union { /* SPBCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :16; /* */\r
+ _UDWORD SPBR:8; /* SPBR */\r
+ _UDWORD :6; /* */\r
+ _UDWORD BRDV:2; /* BRDV */\r
+ } BIT; /* */\r
+ } SPBCR; /* */\r
+ union { /* DRCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :12; /* */\r
+ _UDWORD RBURST:4; /* RBURST */\r
+ _UDWORD :6; /* */\r
+ _UDWORD RCF:1; /* RCF */\r
+ _UDWORD RBE:1; /* RBE */\r
+ _UDWORD :7; /* */\r
+ _UDWORD SSLE:1; /* SSLE */\r
+ } BIT; /* */\r
+ } DRCR; /* */\r
+ union { /* DRCMR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :8; /* */\r
+ _UDWORD CMD:8; /* CMD */\r
+ _UDWORD :8; /* */\r
+ _UDWORD OCMD:8; /* OCMD */\r
+ } BIT; /* */\r
+ } DRCMR; /* */\r
+ union { /* DREAR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :8; /* */\r
+ _UDWORD EAV:8; /* EAV */\r
+ _UDWORD :13; /* */\r
+ _UDWORD EAC:3; /* EAC */\r
+ } BIT; /* */\r
+ } DREAR; /* */\r
+ union { /* DROPR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD OPD3:8; /* OPD3 */\r
+ _UDWORD OPD2:8; /* OPD2 */\r
+ _UDWORD OPD1:8; /* OPD1 */\r
+ _UDWORD OPD0:8; /* OPD0 */\r
+ } BIT; /* */\r
+ } DROPR; /* */\r
+ union { /* DRENR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CDB:2; /* CDB */\r
+ _UDWORD OCDB:2; /* OCDB */\r
+ _UDWORD :2; /* */\r
+ _UDWORD ADB:2; /* ADB */\r
+ _UDWORD :2; /* */\r
+ _UDWORD OPDB:2; /* OPDB */\r
+ _UDWORD :2; /* */\r
+ _UDWORD DRDB:2; /* DRDB */\r
+ _UDWORD :1; /* */\r
+ _UDWORD CDE:1; /* CDE */\r
+ _UDWORD :1; /* */\r
+ _UDWORD OCDE:1; /* OCDE */\r
+ _UDWORD ADE:4; /* ADE */\r
+ _UDWORD OPDE:4; /* OPDE */\r
+ _UDWORD :4; /* */\r
+ } BIT; /* */\r
+ } DRENR; /* */\r
+ union { /* SMCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :23; /* */\r
+ _UDWORD SSLKP:1; /* SSLKP */\r
+ _UDWORD :5; /* */\r
+ _UDWORD SPIRE:1; /* SPIRE */\r
+ _UDWORD SPIWE:1; /* SPIWE */\r
+ _UDWORD SPIE:1; /* SPIE */\r
+ } BIT; /* */\r
+ } SMCR; /* */\r
+ union { /* SMCMR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :8; /* */\r
+ _UDWORD CMD:8; /* CMD */\r
+ _UDWORD :8; /* */\r
+ _UDWORD OCMD:8; /* OCMD */\r
+ } BIT; /* */\r
+ } SMCMR; /* */\r
+ union { /* SMADR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ADR:32; /* ADR */\r
+ } BIT; /* */\r
+ } SMADR; /* */\r
+ union { /* SMOPR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD OPD3:8; /* OPD3 */\r
+ _UDWORD OPD2:8; /* OPD2 */\r
+ _UDWORD OPD1:8; /* OPD1 */\r
+ _UDWORD OPD0:8; /* OPD0 */\r
+ } BIT; /* */\r
+ } SMOPR; /* */\r
+ union { /* SMENR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CDB:2; /* CDB */\r
+ _UDWORD OCDB:2; /* OCDB */\r
+ _UDWORD :2; /* */\r
+ _UDWORD ADB:2; /* ADB */\r
+ _UDWORD :2; /* */\r
+ _UDWORD OPDB:2; /* OPDB */\r
+ _UDWORD :2; /* */\r
+ _UDWORD SPIDB:2; /* SPIDB */\r
+ _UDWORD :1; /* */\r
+ _UDWORD CDE:1; /* CDE */\r
+ _UDWORD :1; /* */\r
+ _UDWORD OCDE:1; /* OCDE */\r
+ _UDWORD ADE:4; /* ADE */\r
+ _UDWORD OPDE:4; /* OPDE */\r
+ _UDWORD SPIDE:4; /* SPIDE */\r
+ } BIT; /* */\r
+ } SMENR; /* */\r
+ _UBYTE wk0[4]; /* */\r
+ union { /* SMRDR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD RDATA0:32; /* RDATA0 */\r
+ } BIT; /* */\r
+ } SMRDR0; /* */\r
+ union { /* SMRDR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD RDATA1:32; /* RDATA1 */\r
+ } BIT; /* */\r
+ } SMRDR1; /* */\r
+ union { /* SMWDR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD WDATA0:32; /* WDATA0 */\r
+ } BIT; /* */\r
+ } SMWDR0; /* */\r
+ union { /* SMWDR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD H; /* High */\r
+ _UWORD L; /* Low */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE HH; /* High, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE LL; /* Low, Low */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD WDATA1:32; /* WDATA1 */\r
+ } BIT; /* */\r
+ } SMWDR1; /* */\r
+ union { /* CMNSR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :30; /* */\r
+ _UDWORD SSLF:1; /* SSLF */\r
+ _UDWORD TEND:1; /* TEND */\r
+ } BIT; /* */\r
+ } CMNSR; /* */\r
+}; /* */\r
+\r
+ #if 0\r
+#define CPG (*(volatile struct st_cpg *)0xFFFE0010) /* CPG Address */\r
+#define INTC (*(volatile struct st_intc *)0xFFFE0800) /* INTC Address */\r
+ #endif\r
+#define CCNT (*(volatile struct st_ccnt *)0xFFFC1000) /* CCNT Address */\r
+ #if 0\r
+#define BSC (*(volatile struct st_bsc *)0xFFFC0000) /* BSC Address */\r
+#define DMAC (*(volatile struct st_dmac *)0xFFFE1000) /* DMAC Address */\r
+ #endif\r
+ #if 0\r
+#define MTU2 (*(volatile struct st_mtu2 *)0xFFFE4000) /* MTU2 Address */\r
+ #endif\r
+#define CMT (*(volatile struct st_cmt *)0xFFFEC000) /* CMT Address */\r
+#define WDT (*(volatile union un_wdt *)0xFFFE0000) /* WDT Address */\r
+#define RTC (*(volatile struct st_rtc *)0xFFFE6000) /* RTC Address */\r
+ #if 0\r
+#define SCIF0 (*(volatile struct st_scif02346 *)0xE8007000)/* SCIF0 Address */\r
+#define SCIF1 (*(volatile struct st_scif157 *)0xE8007800)/* SCIF1 Address */\r
+#define SCIF2 (*(volatile struct st_scif02346 *)0xE8008000)/* SCIF2 Address */\r
+#define SCIF3 (*(volatile struct st_scif02346 *)0xE8008800)/* SCIF3 Address */\r
+#define SCIF4 (*(volatile struct st_scif02346 *)0xE8009000)/* SCIF4 Address */\r
+#define SCIF5 (*(volatile struct st_scif157 *)0xE8009800)/* SCIF5 Address */\r
+#define SCIF6 (*(volatile struct st_scif02346 *)0xE800A000)/* SCIF6 Address */\r
+#define SCIF7 (*(volatile struct st_scif157 *)0xE800A800)/* SCIF7 Address */\r
+ #endif\r
+#define RSPI0 (*(volatile struct st_rspi *)0xE800E000) /* RSPI0 Address */\r
+#define RSPI1 (*(volatile struct st_rspi *)0xE800E800) /* RSPI1 Address */\r
+ #if 0\r
+#define IIC3_0 (*(volatile struct st_iic3 *)0xFFFEE000)/* IIC3_0 Address */\r
+#define IIC3_1 (*(volatile struct st_iic3 *)0xFFFEE400)/* IIC3_1 Address */\r
+#define IIC3_2 (*(volatile struct st_iic3 *)0xFFFEE800)/* IIC3_2 Address */\r
+#define IIC3_3 (*(volatile struct st_iic3 *)0xFFFEEC00)/* IIC3_3 Address */\r
+ #endif\r
+#define SSIF0 (*(volatile struct st_ssif *)0xFFFF0000)/* SSIF0 Address */\r
+#define SSIF1 (*(volatile struct st_ssif *)0xFFFF0800)/* SSIF1 Address */\r
+#define SSIF2 (*(volatile struct st_ssif *)0xFFFF1000)/* SSIF2 Address */\r
+#define SSIF3 (*(volatile struct st_ssif *)0xFFFF1800)/* SSIF3 Address */\r
+#define SSIF4 (*(volatile struct st_ssif *)0xFFFF2000)/* SSIF4 Address */\r
+#define SSIF5 (*(volatile struct st_ssif *)0xFFFF2800)/* SSIF5 Address */\r
+#define SIOF (*(volatile struct st_siof *)0xFFFF4800) /* SIOF Address */\r
+#define RCAN0 (*(volatile struct st_rcan *)0xFFFE5000) /* RCAN0 Address */\r
+#define RCAN1 (*(volatile struct st_rcan *)0xFFFE5800) /* RCAN1 Address */\r
+#define RCAN2 (*(volatile struct st_rcan *)0xFFFED800) /* RCAN2 Address */\r
+#define IEB (*(volatile struct st_ieb *)0xFFFEF000) /* IEB Address */\r
+#define SPDIF (*(volatile struct st_spdif *)0xE8012000)/* SPDIF Address */\r
+#define ROMDEC (*(volatile struct st_romdec *)0xE8005000)/* ROMDEC Address */\r
+ #if 0 /* Old ADC iodefine */\r
+#define ADC (*(volatile struct st_adc *)0xE8005800) /* ADC Address */\r
+ #endif/* Old ADC iodefine */\r
+#define FLCTL (*(volatile struct st_flctl *)0xFFFF4000)/* FLCTL Address */\r
+ #if 0\r
+#define USB (*(volatile struct st_usb *)0xE8010000) /* USB Address */\r
+ #endif\r
+#define VDC4 (*(volatile struct st_vdc4 *)0xFFFF7400) /* VDC4 Address */\r
+#define SRC0 (*(volatile struct st_src *)0xFFFE7000) /* SRC0 Address */\r
+#define SRC1 (*(volatile struct st_src *)0xFFFE7800) /* SRC1 Address */\r
+#define SRC2 (*(volatile struct st_src *)0xFFFE8000) /* SRC2 Address */\r
+ #if 0\r
+#define PORT (*(volatile struct st_gpio *)0xFFFE3810) /* GPIO Address */\r
+ #endif\r
+#define HUDI (*(volatile struct st_hudi *)0xFFFE2000) /* HUDI Address */\r
+#define PWM (*(volatile struct st_pwm *)0xFFFEF406) /* PWM Address */\r
+#define QSPI0 (*(volatile struct st_rqspi *)0xE8033800) /* RQSPI0 Address */\r
+#define QSPI1 (*(volatile struct st_rqspi *)0xE8034000) /* RQSPI1 Address */\r
+#define IMRLS (*(volatile struct st_imrls *)0xFFFF3008)/* IMRLS Address */\r
+#define SDG0 (*(volatile struct st_sdg0 *)0xFFFEC800) /* SDG0 Address */\r
+#define SDG1 (*(volatile struct st_sdg1 *)0xFFFECA00) /* SDG1 Address */\r
+#define SDG2 (*(volatile struct st_sdg2 *)0xFFFECC00) /* SDG2 Address */\r
+#define SDG3 (*(volatile struct st_sdg3 *)0xFFFECE00) /* SDG3 Address */\r
+#define MMC (*(volatile struct st_mmc *)0xE8030800) /* MMC Address */\r
+#define DVDEC (*(volatile struct st_dvdec *)0xFFFFA008)/* DVDEC Address */\r
+#define UBC (*(volatile struct st_ubc *)0xFFFC0400) /* UBC Address */\r
+#define DISC (*(volatile struct st_disc *)0xFFFFA800) /* DISC Address */\r
+#define JCU (*(volatile struct st_jcu *)0xE8017000) /* JCU Address */\r
+#define SPIBSC (*(volatile struct st_spibsc *)0xFFFC1C00)/* SPIBSC Address */\r
+\r
+\r
+/* ==== includes each iodefine ==== */\r
+#include "usb_iodefine.h" /* for USB module */\r
+#include "scif_iodefine.h" /* for SCIF module */\r
+#include "pfc_iodefine.h" /* for PFC module */\r
+#include "bsc_iodefine.h" /* for BSC module */\r
+#include "cpg_iodefine.h" /* for CPG module */\r
+//#include "dmac_iodefine.h" /* for DMAC module */\r
+#include "intc_iodefine.h" /* for INTC module */\r
+#include "ostm_iodefine.h" /* for OSTM module */\r
+#include "riic_iodefine.h" /* for RIIC module */\r
+#include "prr_iodefine.h" /* for \90»\95i\83o\81[\83W\83\87\83\93\83\8c\83W\83X\83^ */\r
+#include "spibsc_iodefine.h" /* for SPIBSC module */\r
+#include "mtu2_iodefine.h" /* for MTU2 module */\r
+\r
+#endif /* _IODEFINE_H_ */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : bsc_iodefine.h\r
+* Version : 0.01\r
+* Device(s) : Aragon\r
+* Tool-Chain : DS-5 Ver 5.8\r
+* ARM Complier \r
+* : \r
+* H/W Platform : Aragon CPU Board\r
+* Description : Aragon Sample Program vecotr.s\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 27.07.2012 0.01 \8eQ\8dl\8e\91\97¿\81Fsec08_BSC_20120615.doc !!!TOSCORn\82É\8ed\97l\8f\91\82É\82È\82¢\83r\83b\83g\96¼\82 \82è!!!\r
+*******************************************************************************/\r
+#ifndef __BSC_IODEFINE_H__\r
+#define __BSC_IODEFINE_H__\r
+\r
+#include "typedefine.h"\r
+\r
+typedef union { /* CSnBCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :9; /* */\r
+ _UDWORD BSZ:2; /* BSZ */\r
+ _UDWORD :1; /* */\r
+ _UDWORD TYPE:3; /* TYPE */\r
+ _UDWORD :1; /* */\r
+ _UDWORD IWRRS:3; /* IWRRS */\r
+ _UDWORD IWRRD:3; /* IWRRD */\r
+ _UDWORD IWRWS:3; /* IWRWS */\r
+ _UDWORD IWRWD:3; /* IWRWD */\r
+ _UDWORD IWW:3; /* IWW */\r
+ _UDWORD :1; /* */\r
+ } BIT; /* */\r
+} CSnBCR; /* */\r
+typedef union { /* TOSCORn */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD xxx:16; /* xxx */ /* !!!\83r\83b\83g\96¼\8c\88\92è\8e\9f\91æ\81A\92è\8b`\82·\82é!!! */\r
+ _UDWORD :16; /* */\r
+ } BIT; /* */\r
+} TOSCORn; /* */\r
+\r
+struct st_bsc { /* struct BSC */\r
+ union { /* CMNCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD HIZCNT:1; /* HIZCNT */\r
+ _UDWORD HIZMEM:1; /* HIZMEM */\r
+ _UDWORD :7; /* */\r
+ _UDWORD DPRTY:2; /* DPRTY */\r
+ _UDWORD :13; /* */\r
+ _UDWORD AL0:1; /* AL0 */\r
+ _UDWORD :3; /* */\r
+ _UDWORD TL0:1; /* TL0 */\r
+ _UDWORD :3; /* */\r
+ } BIT; /* */\r
+ } CMNCR; /* */\r
+ CSnBCR CS0BCR; /* CS0BCR */\r
+ CSnBCR CS1BCR; /* CS1BCR */\r
+ CSnBCR CS2BCR; /* CS2BCR */\r
+ CSnBCR CS3BCR; /* CS3BCR */\r
+ CSnBCR CS4BCR; /* CS4BCR */\r
+ CSnBCR CS5BCR; /* CS5BCR */\r
+ _UBYTE wk0[12]; /* */\r
+ union { /* CS0WCR */\r
+ union { /* CS0WCR(NORMAL) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD HW:2; /* HW */\r
+ _UDWORD :4; /* */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD WR:4; /* WR */\r
+ _UDWORD SW:2; /* SW */\r
+ _UDWORD :7; /* */\r
+ _UDWORD BAS:1; /* BAS */\r
+ _UDWORD :11; /* */\r
+ } BIT; /* */\r
+ } NORMAL; /* */\r
+ union { /* CS0WCR(BROM_ASY) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :6; /* */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD W:4; /* W */\r
+ _UDWORD :5; /* */\r
+ _UDWORD BW:2; /* BW */\r
+ _UDWORD :2; /* */\r
+ _UDWORD BST:2; /* BST */\r
+ _UDWORD :10; /* */\r
+ } BIT; /* */\r
+ } BROM_ASY; /* */\r
+ union { /* CS0WCR(BROM_SY) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :6; /* */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD W:4; /* W */\r
+ _UDWORD :5; /* */\r
+ _UDWORD BW:2; /* BW */\r
+ _UDWORD :14; /* */\r
+ } BIT; /* */\r
+ } BROM_SY; /* */\r
+ } CS0WCR; /* */\r
+ union { /* CS1WCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD HW:2; /* HW */\r
+ _UDWORD :4; /* */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD WR:4; /* WR */\r
+ _UDWORD SW:2; /* SW */\r
+ _UDWORD :3; /* */\r
+ _UDWORD WW:3; /* WW */\r
+ _UDWORD :1; /* */\r
+ _UDWORD BAS:1; /* BAS */\r
+ _UDWORD :11; /* */\r
+ } BIT; /* */\r
+ } CS1WCR; /* */\r
+ union { /* CS2WCR */\r
+ union { /* CS2WCR(NORMAL) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :6; /* */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD WR:4; /* WR */\r
+ _UDWORD :9; /* */\r
+ _UDWORD BAS:1; /* BAS */\r
+ _UDWORD :11; /* */\r
+ } BIT; /* */\r
+ } NORMAL; /* */\r
+ union { /* CS2WCR(SDRAM) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :7; /* */\r
+ _UDWORD A2CL:2; /* A2CL */\r
+ _UDWORD :23; /* */\r
+ } BIT; /* */\r
+ } SDRAM; /* */\r
+ } CS2WCR; /* */\r
+ union { /* CS3WCR */\r
+ union { /* CS3WCR(NORMAL) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :6; /* */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD WR:4; /* WR */\r
+ _UDWORD :9; /* */\r
+ _UDWORD BAS:1; /* BAS */\r
+ _UDWORD :11; /* */\r
+ } BIT; /* */\r
+ } NORMAL; /* */\r
+ union { /* CS3WCR(SDRAM) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD WTRC:2; /* WTRC */\r
+ _UDWORD :1; /* */\r
+ _UDWORD TRWL:2; /* TRWL */\r
+ _UDWORD :2; /* */\r
+ _UDWORD A3CL:2; /* A3CL */\r
+ _UDWORD :1; /* */\r
+ _UDWORD WTRCD:2; /* WTRCD */\r
+ _UDWORD :1; /* */\r
+ _UDWORD WTRP:2; /* WTRP */\r
+ _UDWORD :17; /* */\r
+ } BIT; /* */\r
+ } SDRAM; /* */\r
+ } CS3WCR; /* */\r
+ union { /* CS4WCR */\r
+ union { /* CS4WCR(NORMAL) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD HW:2; /* HW */\r
+ _UDWORD :4; /* */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD WR:4; /* WR */\r
+ _UDWORD SW:2; /* SW */\r
+ _UDWORD :3; /* */\r
+ _UDWORD WW:3; /* WW */\r
+ _UDWORD :1; /* */\r
+ _UDWORD BAS:1; /* BAS */\r
+ _UDWORD :11; /* */\r
+ } BIT; /* */\r
+ } NORMAL; /* */\r
+ union { /* CS4WCR(BROM_ASY) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD HW:2; /* HW */\r
+ _UDWORD :4; /* */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD W:4; /* W */\r
+ _UDWORD SW:2; /* SW */\r
+ _UDWORD :3; /* */\r
+ _UDWORD BW:2; /* BW */\r
+ _UDWORD :2; /* */\r
+ _UDWORD BST:2; /* BST */\r
+ _UDWORD :10; /* */\r
+ } BIT; /* */\r
+ } BROM_ASY; /* */\r
+ } CS4WCR; /* */\r
+ union { /* CS5WCR */\r
+ union { /* CS5WCR(NORMAL) */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD HW:2; /* HW */\r
+ _UDWORD :4; /* */\r
+ _UDWORD WM:1; /* WM */\r
+ _UDWORD WR:4; /* WR */\r
+ _UDWORD SW:2; /* SW */\r
+ _UDWORD :3; /* */\r
+ _UDWORD WW:3; /* WW */\r
+ _UDWORD :1; /* */\r
+ _UDWORD MPXWBAS:1; /* MPXW/BAS */\r
+ _UDWORD SZSEL:1; /* SZSEL */\r
+ _UDWORD :10; /* */\r
+ } BIT; /* */\r
+ } NORMAL; /* */\r
+ } CS5WCR; /* */\r
+ _UBYTE wk1[12]; /* */\r
+ union { /* SDCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD A3COL:2; /* A3COL */\r
+ _UDWORD :1; /* */\r
+ _UDWORD A3ROW:2; /* A3ROW */\r
+ _UDWORD :3; /* */\r
+ _UDWORD BACTV:1; /* BACTV */\r
+ _UDWORD PDOWN:1; /* PDOWN */\r
+ _UDWORD RMODE:1; /* RMODE */\r
+ _UDWORD RFSH:1; /* RFSH */\r
+ _UDWORD :1; /* */\r
+ _UDWORD DEEP:1; /* DEEP */\r
+ _UDWORD :2; /* */\r
+ _UDWORD A2COL:2; /* A2COL */\r
+ _UDWORD :1; /* */\r
+ _UDWORD A2ROW:2; /* A2ROW */\r
+ _UDWORD :11; /* */\r
+ } BIT; /* */\r
+ } SDCR; /* */\r
+ union { /* RTCSR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD RRC:3; /* RRC */\r
+ _UDWORD CKS:3; /* CKS */\r
+ _UDWORD CMIE:1; /* CMIE */\r
+ _UDWORD CMF:1; /* CMF */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } RTCSR; /* */\r
+ union { /* RTCNT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RTCNT; /* */\r
+ union { /* RTCOR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD D:32; /* D */\r
+ } BIT; /* */\r
+ } RTCOR; /* */\r
+ _UBYTE wk2[4]; /* */\r
+ TOSCORn TOSCOR0; /* TOSCOR0 */\r
+ TOSCORn TOSCOR1; /* TOSCOR1 */\r
+ TOSCORn TOSCOR2; /* TOSCOR2 */\r
+ TOSCORn TOSCOR3; /* TOSCOR3 */\r
+ TOSCORn TOSCOR4; /* TOSCOR4 */\r
+ TOSCORn TOSCOR5; /* TOSCOR5 */\r
+ _UBYTE wk3[8]; /* */\r
+ union { /* TOSTR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CS0TOSTF:1; /* CS0TOSTF */\r
+ _UDWORD CS1TOSTF:1; /* CS1TOSTF */\r
+ _UDWORD CS2TOSTF:1; /* CS2TOSTF */\r
+ _UDWORD CS3TOSTF:1; /* CS3TOSTF */\r
+ _UDWORD CS4TOSTF:1; /* CS4TOSTF */\r
+ _UDWORD CS5TOSTF:1; /* CS5TOSTF */\r
+ _UDWORD :26; /* */\r
+ } BIT; /* */\r
+ } TOSTR; /* */\r
+ union { /* TOENR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CS0TOEN:1; /* CS0TOEN */\r
+ _UDWORD CS1TOEN:1; /* CS1TOEN */\r
+ _UDWORD CS2TOEN:1; /* CS2TOEN */\r
+ _UDWORD CS3TOEN:1; /* CS3TOEN */\r
+ _UDWORD CS4TOEN:1; /* CS4TOEN */\r
+ _UDWORD CS5TOEN:1; /* CS5TOEN */\r
+ _UDWORD :26; /* */\r
+ } BIT; /* */\r
+ } TOENR; /* */\r
+}; /* */\r
+\r
+#define BSC (*(volatile struct st_bsc *)0x3FFFC000) /* BSC Address */\r
+\r
+\r
+#endif /* __BSC_IODEFINE_H__ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : cpg_iodefine.h\r
+* Version : 0.01\r
+* Device(s) : Aragon\r
+* Tool-Chain : DS-5 Ver 5.8\r
+* ARM Complier \r
+* : \r
+* H/W Platform : Aragon CPU Board\r
+* Description : Aragon Sample Program vecotr.s\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 27.07.2012 0.01 \8eQ\8dl\8e\91\97¿\81FRZ_A1H_05J_121010_11.pdf\r
+*******************************************************************************/\r
+#ifndef __CPG_IODEFINE_H__\r
+#define __CPG_IODEFINE_H__\r
+\r
+#include "typedefine.h"\r
+\r
+struct st_cpg { /* struct CPG */\r
+ union { /* FRQCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD IFC:2; /* IFC */\r
+ _UWORD :2; /* */\r
+ _UWORD CKOEN:2; /* CKOEN */\r
+ _UWORD CKOEN2:1; /* CKOEN2 */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } FRQCR; /* */\r
+ _UBYTE wk0[2]; /* */\r
+ union { /* FRQCR2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD GFC:2; /* GFC */\r
+ _UWORD :14; /* */\r
+ } BIT; /* */\r
+ } FRQCR2; /* */\r
+ _UBYTE wk1[2]; /* */\r
+ union { /* CPUSTS */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :4; /* */\r
+ _UBYTE ISBUSY0:1; /* ISBUSY0 */\r
+ _UBYTE :3; /* */\r
+ } BIT; /* */\r
+ } CPUSTS; /* */\r
+ _UBYTE wk2[7]; /* */\r
+ union { /* STBCR1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :6; /* */\r
+ _UBYTE DEEP:1; /* DEEP */\r
+ _UBYTE STBY:1; /* STBY */\r
+ } BIT; /* */\r
+ } STBCR1; /* */\r
+ _UBYTE wk3[3]; /* */\r
+ union { /* STBCR2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP20:1; /* MSTP20 */\r
+ _UBYTE :6; /* */\r
+ _UBYTE HIZ:1; /* HIZ */\r
+ } BIT; /* */\r
+ } STBCR2; /* */\r
+ _UBYTE wk4[11]; /* */\r
+ union { /* STBREQ1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE STBRQ10:1; /* STBRQ10 */\r
+ _UBYTE :2; /* */\r
+ _UBYTE STBRQ13:1; /* STBRQ13 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE STBRQ15:1; /* STBRQ15 */\r
+ _UBYTE :2; /* */\r
+ } BIT; /* */\r
+ } STBREQ1; /* */\r
+ _UBYTE wk5[3]; /* */\r
+ union { /* STBREQ2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE STBRQ20:1; /* STBRQ20 */\r
+ _UBYTE STBRQ21:1; /* STBRQ21 */\r
+ _UBYTE STBRQ22:1; /* STBRQ22 */\r
+ _UBYTE STBRQ23:1; /* STBRQ23 */\r
+ _UBYTE STBRQ24:1; /* STBRQ24 */\r
+ _UBYTE STBRQ25:1; /* STBRQ25 */\r
+ _UBYTE STBRQ26:1; /* STBRQ26 */\r
+ _UBYTE STBRQ27:1; /* STBRQ27 */\r
+ } BIT; /* */\r
+ } STBREQ2; /* */\r
+ _UBYTE wk6[11]; /* */\r
+ union { /* STBACK1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE STBAK10:1; /* STBAK10 */\r
+ _UBYTE :2; /* */\r
+ _UBYTE STBAK13:1; /* STBAK13 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE STBAK15:1; /* STBAK15 */\r
+ _UBYTE :2; /* */\r
+ } BIT; /* */\r
+ } STBACK1; /* */\r
+ _UBYTE wk7[3]; /* */\r
+ union { /* STBACK2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE STBAK20:1; /* STBAK20 */\r
+ _UBYTE STBAK21:1; /* STBAK21 */\r
+ _UBYTE STBAK22:1; /* STBAK22 */\r
+ _UBYTE STBAK23:1; /* STBAK23 */\r
+ _UBYTE STBAK24:1; /* STBAK24 */\r
+ _UBYTE STBAK25:1; /* STBAK25 */\r
+ _UBYTE STBAK26:1; /* STBAK26 */\r
+ _UBYTE STBAK27:1; /* STBAK27 */\r
+ } BIT; /* */\r
+ } STBACK2; /* */\r
+ _UBYTE wk8[955]; /* */\r
+ union { /* SYSCR1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE VRAME0:1; /* VRAME0 */\r
+ _UBYTE VRAME1:1; /* VRAME1 */\r
+ _UBYTE VRAME2:1; /* VRAME2 */\r
+ _UBYTE VRAME3:1; /* VRAME3 */\r
+ _UBYTE VRAME4:1; /* VRAME4 */\r
+ _UBYTE :3; /* */\r
+ } BIT; /* */\r
+ } SYSCR1; /* */\r
+ _UBYTE wk9[3]; /* */\r
+ union { /* SYSCR2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE VRAMWE0:1; /* VRAMWE0 */\r
+ _UBYTE VRAMWE1:1; /* VRAMWE1 */\r
+ _UBYTE VRAMWE2:1; /* VRAMWE2 */\r
+ _UBYTE VRAMWE3:1; /* VRAMWE3 */\r
+ _UBYTE VRAMWE4:1; /* VRAMWE4 */\r
+ _UBYTE :3; /* */\r
+ } BIT; /* */\r
+ } SYSCR2; /* */\r
+ _UBYTE wk10[3]; /* */\r
+ union { /* SYSCR3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE RRAMWE0:1; /* RRAMWE0 */\r
+ _UBYTE RRAMWE1:1; /* RRAMWE1 */\r
+ _UBYTE RRAMWE2:1; /* RRAMWE2 */\r
+ _UBYTE RRAMWE3:1; /* RRAMWE3 */\r
+ _UBYTE :4; /* */\r
+ } BIT; /* */\r
+ } SYSCR3; /* */\r
+ _UBYTE wk11[23]; /* */\r
+ union { /* STBCR3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP30:1; /* MSTP30 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE MSTP32:1; /* MSTP32 */\r
+ _UBYTE MSTP33:1; /* MSTP33 */\r
+ _UBYTE MSTP34:1; /* MSTP34 */\r
+ _UBYTE MSTP35:1; /* MSTP35 */\r
+ _UBYTE MSTP36:1; /* MSTP36 */\r
+ _UBYTE MSTP37:1; /* MSTP37 */\r
+ } BIT; /* */\r
+ } STBCR3; /* */\r
+ _UBYTE wk12[3]; /* */\r
+ union { /* STBCR4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP40:1; /* MSTP40 */\r
+ _UBYTE MSTP41:1; /* MSTP41 */\r
+ _UBYTE MSTP42:1; /* MSTP42 */\r
+ _UBYTE MSTP43:1; /* MSTP43 */\r
+ _UBYTE MSTP44:1; /* MSTP44 */\r
+ _UBYTE MSTP45:1; /* MSTP45 */\r
+ _UBYTE MSTP46:1; /* MSTP46 */\r
+ _UBYTE MSTP47:1; /* MSTP47 */\r
+ } BIT; /* */\r
+ } STBCR4; /* */\r
+ _UBYTE wk13[3]; /* */\r
+ union { /* STBCR5 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP50:1; /* MSTP50 */\r
+ _UBYTE MSTP51:1; /* MSTP51 */\r
+ _UBYTE MSTP52:1; /* MSTP52 */\r
+ _UBYTE MSTP53:1; /* MSTP53 */\r
+ _UBYTE MSTP54:1; /* MSTP54 */\r
+ _UBYTE MSTP55:1; /* MSTP55 */\r
+ _UBYTE MSTP56:1; /* MSTP56 */\r
+ _UBYTE MSTP57:1; /* MSTP57 */\r
+ } BIT; /* */\r
+ } STBCR5; /* */\r
+ _UBYTE wk14[3]; /* */\r
+ union { /* STBCR6 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP60:1; /* MSTP60 */\r
+ _UBYTE MSTP61:1; /* MSTP61 */\r
+ _UBYTE MSTP62:1; /* MSTP62 */\r
+ _UBYTE MSTP63:1; /* MSTP63 */\r
+ _UBYTE MSTP64:1; /* MSTP64 */\r
+ _UBYTE MSTP65:1; /* MSTP65 */\r
+ _UBYTE MSTP66:1; /* MSTP66 */\r
+ _UBYTE MSTP67:1; /* MSTP67 */\r
+ } BIT; /* */\r
+ } STBCR6; /* */\r
+ _UBYTE wk15[3]; /* */\r
+ union { /* STBCR7 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP70:1; /* MSTP70 */\r
+ _UBYTE MSTP71:1; /* MSTP71 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE MSTP73:1; /* MSTP73 */\r
+ _UBYTE MSTP74:1; /* MSTP74 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE MSTP76:1; /* MSTP76 */\r
+ _UBYTE MSTP77:1; /* MSTP77 */\r
+ } BIT; /* */\r
+ } STBCR7; /* */\r
+ _UBYTE wk16[3]; /* */\r
+ union { /* STBCR8 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE MSTP81:1; /* MSTP81 */\r
+ _UBYTE :1; /* */\r
+ _UBYTE MSTP83:1; /* MSTP83 */\r
+ _UBYTE MSTP84:1; /* MSTP84 */\r
+ _UBYTE MSTP85:1; /* MSTP85 */\r
+ _UBYTE MSTP86:1; /* MSTP86 */\r
+ _UBYTE MSTP87:1; /* MSTP87 */\r
+ } BIT; /* */\r
+ } STBCR8; /* */\r
+ _UBYTE wk17[3]; /* */\r
+ union { /* STBCR9 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP90:1; /* MSTP60 */\r
+ _UBYTE MSTP91:1; /* MSTP61 */\r
+ _UBYTE MSTP92:1; /* MSTP62 */\r
+ _UBYTE MSTP93:1; /* MSTP63 */\r
+ _UBYTE MSTP94:1; /* MSTP64 */\r
+ _UBYTE MSTP95:1; /* MSTP65 */\r
+ _UBYTE MSTP96:1; /* MSTP66 */\r
+ _UBYTE MSTP97:1; /* MSTP67 */\r
+ } BIT; /* */\r
+ } STBCR9; /* */\r
+ _UBYTE wk18[3]; /* */\r
+ union { /* STBCR10 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP100:1; /* MSTP100 */\r
+ _UBYTE MSTP101:1; /* MSTP101 */\r
+ _UBYTE MSTP102:1; /* MSTP102 */\r
+ _UBYTE MSTP103:1; /* MSTP103 */\r
+ _UBYTE MSTP104:1; /* MSTP104 */\r
+ _UBYTE MSTP105:1; /* MSTP105 */\r
+ _UBYTE MSTP106:1; /* MSTP106 */\r
+ _UBYTE MSTP107:1; /* MSTP107 */\r
+ } BIT; /* */\r
+ } STBCR10; /* */\r
+ _UBYTE wk19[3]; /* */\r
+ union { /* STBCR11 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP110:1; /* MSTP110 */\r
+ _UBYTE MSTP111:1; /* MSTP111 */\r
+ _UBYTE MSTP112:1; /* MSTP112 */\r
+ _UBYTE MSTP113:1; /* MSTP113 */\r
+ _UBYTE MSTP114:1; /* MSTP114 */\r
+ _UBYTE MSTP115:1; /* MSTP115 */\r
+ _UBYTE :2; /* */\r
+ } BIT; /* */\r
+ } STBCR11; /* */\r
+ _UBYTE wk20[3]; /* */\r
+ union { /* STBCR12 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MSTP120:1; /* MSTP120 */\r
+ _UBYTE MSTP121:1; /* MSTP121 */\r
+ _UBYTE MSTP122:1; /* MSTP122 */\r
+ _UBYTE MSTP123:1; /* MSTP123 */\r
+ _UBYTE :4; /* */\r
+ } BIT; /* */\r
+ } STBCR12; /* */\r
+ _UBYTE wk21[27]; /* */\r
+ union { /* SWRSTCR1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE SRST11:1; /* SRST11 */\r
+ _UBYTE SRST12:1; /* SRST12 */\r
+ _UBYTE SRST13:1; /* SRST13 */\r
+ _UBYTE SRST14:1; /* SRST14 */\r
+ _UBYTE SRST15:1; /* SRST15 */\r
+ _UBYTE SRST16:1; /* SRST16 */\r
+ _UBYTE AXTALE:1; /* AXTALE */\r
+ } BIT; /* */\r
+ } SWRSTCR1; /* */\r
+ _UBYTE wk22[3]; /* */\r
+ union { /* SWRSTCR2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE SRST21:1; /* SRST21 */\r
+ _UBYTE SRST22:1; /* SRST22 */\r
+ _UBYTE SRST23:1; /* SRST23 */\r
+ _UBYTE SRST24:1; /* SRST24 */\r
+ _UBYTE SRST25:1; /* SRST25 */\r
+ _UBYTE SRST26:1; /* SRST26 */\r
+ _UBYTE SRST27:1; /* SRST27 */\r
+ } BIT; /* */\r
+ } SWRSTCR2; /* */\r
+ _UBYTE wk23[3]; /* */\r
+ union { /* SWRSTCR3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :1; /* */\r
+ _UBYTE SRST31:1; /* SRST31 */\r
+ _UBYTE SRST32:1; /* SRST32 */\r
+ _UBYTE SRST33:1; /* SRST33 */\r
+ _UBYTE SRST34:1; /* SRST34 */\r
+ _UBYTE SRST35:1; /* SRST35 */\r
+ _UBYTE SRST36:1; /* SRST36 */\r
+ _UBYTE :1; /* */\r
+ } BIT; /* */\r
+ } SWRSTCR3; /* */\r
+ _UBYTE wk24[3]; /* */\r
+ union { /* SWRSTCR4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SRST40:1; /* SRST40 */\r
+ _UBYTE SRST41:1; /* SRST41 */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } SWRSTCR4; /* */\r
+ _UBYTE wk25[70547]; /* */\r
+ union { /* RRAMKP */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE RRAMKP0:1; /* RRAMKP0 */\r
+ _UBYTE RRAMKP1:1; /* RRAMKP1 */\r
+ _UBYTE RRAMKP2:1; /* RRAMKP2 */\r
+ _UBYTE RRAMKP3:1; /* RRAMKP3 */\r
+ _UBYTE :4; /* */\r
+ } BIT; /* */\r
+ } RRAMKP; /* */\r
+ _UBYTE wk26[1]; /* */\r
+ union { /* DSCTR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE :6; /* */\r
+ _UBYTE RAMBOOT:1; /* RAMBOOT */\r
+ _UBYTE EBUSKEEPE:1; /* EBUSKEEPE */\r
+ } BIT; /* */\r
+ } DSCTR; /* */\r
+ _UBYTE wk27[1]; /* */\r
+ union { /* DSSSR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD P8_2:1; /* P8_2 */\r
+ _UWORD P9_1:1; /* P9_1 */\r
+ _UWORD P2_15:1; /* P2_15 */\r
+ _UWORD P7_8:1; /* P7_8 */\r
+ _UWORD P5_9:1; /* P5_9 */\r
+ _UWORD P6_4:1; /* P6_4 */\r
+ _UWORD RTCAR:1; /* RTCAR */\r
+ _UWORD :1; /* */\r
+ _UWORD NMI:1; /* NMI */\r
+ _UWORD P3_3:1; /* P3_3 */\r
+ _UWORD P8_7:1; /* P8_7 */\r
+ _UWORD P2_12:1; /* P2_12 */\r
+ _UWORD P3_1:1; /* P3_1 */\r
+ _UWORD P3_9:1; /* P3_9 */\r
+ _UWORD P6_2:1; /* P6_2 */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } DSSSR; /* */\r
+ union { /* DSESR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD P8_2E:1; /* P8_2E */\r
+ _UWORD P9_1E:1; /* P9_1E */\r
+ _UWORD P2_15E:1; /* P2_15E */\r
+ _UWORD P7_8E:1; /* P7_8E */\r
+ _UWORD P5_9E:1; /* P5_9E */\r
+ _UWORD P6_4E:1; /* P6_4E */\r
+ _UWORD :2; /* */\r
+ _UWORD NMIE:1; /* NMIE */\r
+ _UWORD P3_3E:1; /* P3_3E */\r
+ _UWORD P8_7E:1; /* P8_7E */\r
+ _UWORD P2_12E:1; /* P2_12E */\r
+ _UWORD P3_1E:1; /* P3_1E */\r
+ _UWORD P3_9E:1; /* P3_9E */\r
+ _UWORD P6_2E:1; /* P6_2E */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } DSESR; /* */\r
+ union { /* DSFR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD P8_2F:1; /* P8_2F */\r
+ _UWORD P9_1F:1; /* P9_1F */\r
+ _UWORD P2_15F:1; /* P2_15F */\r
+ _UWORD P7_8F:1; /* P7_8F */\r
+ _UWORD P5_9F:1; /* P5_9F */\r
+ _UWORD P6_4F:1; /* P6_4F */\r
+ _UWORD RTCARF:1; /* RTCARF */\r
+ _UWORD :1; /* */\r
+ _UWORD NMIF:1; /* NMIF */\r
+ _UWORD P3_3F:1; /* P3_3F */\r
+ _UWORD P8_7F:1; /* P8_7F */\r
+ _UWORD P2_12F:1; /* P2_12F */\r
+ _UWORD P3_1F:1; /* P3_1F */\r
+ _UWORD P3_9F:1; /* P3_9F */\r
+ _UWORD P6_2F:1; /* P6_2F */\r
+ _UWORD IOKEEP:1; /* IOKEEP */\r
+ } BIT; /* */\r
+ } DSFR; /* */\r
+ _UBYTE wk28[6]; /* */\r
+ union { /* XTALCTR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE GAIN0:1; /* GAIN0 */\r
+ _UBYTE GAIN1:1; /* GAIN1 */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } XTALCTR; /* */\r
+}; /* */\r
+\r
+#define CPG (*(volatile struct st_cpg *)0xFCFE0010) /* CPG Address */\r
+\r
+\r
+#endif /* __CPG_IODEFINE_H__ */\r
+\r
+/* End of File */\r
--- /dev/null
+/******************************************************************************\r
+* DISCLAIMER\r
+*\r
+* This software is supplied by Renesas Electronics Corporation and is only \r
+* intended for use with Renesas products. No other uses are authorized.\r
+*\r
+* This software is owned by Renesas Electronics Corporation and is protected under \r
+* all applicable laws, including copyright laws.\r
+*\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES \r
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, \r
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A \r
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY \r
+* DISCLAIMED.\r
+*\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES \r
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS\r
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+*\r
+* Renesas reserves the right, without notice, to make changes to this \r
+* software and to discontinue the availability of this software.\r
+* By using this software, you agree to the additional terms and \r
+* conditions found by accessing the following link: \r
+* http://www.renesas.com/disclaimer\r
+********************************************************************************\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+**************************** Technical reference data **************************\r
+* System Name : \r
+* File Name : dmac_iodefine.h\r
+* Abstract : \r
+* Version : 1.00.00\r
+* Device : ARM\r
+* Tool-Chain : \r
+* OS : None\r
+* H/W Platform: \r
+* Description : \r
+********************************************************************************\r
+* History : Mar.06,2012 Ver.1.00.00\r
+*******************************************************************************/\r
+#ifndef __DMAC_IODEFINE_H__\r
+#define __DMAC_IODEFINE_H__\r
+\r
+#include "typedefine.h"\r
+\r
+struct st_dmac_n { /* struct DMAC */\r
+ union { /* N0SA */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SA:32; /* SA */\r
+ } BIT; /* */\r
+ } N0SA; /* */\r
+ union { /* N0DA */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DA:32; /* DA */\r
+ } BIT; /* */\r
+ } N0DA; /* */\r
+ union { /* N0TB */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TB:32; /* TB */\r
+ } BIT; /* */\r
+ } N0TB; /* */\r
+ union { /* N1SA */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SA:32; /* SA */\r
+ } BIT; /* */\r
+ } N1SA; /* */\r
+ union { /* N1DA */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DA:32; /* DA */\r
+ } BIT; /* */\r
+ } N1DA; /* */\r
+ union { /* N1TB */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TB:32; /* TB */\r
+ } BIT; /* */\r
+ } N1TB; /* */\r
+ union { /* CRSA */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CRSA:32; /* CRSA */\r
+ } BIT; /* */\r
+ } CRSA; /* */\r
+ union { /* CRDA */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CRDA:32; /* CRDA */\r
+ } BIT; /* */\r
+ } CRDA; /* */\r
+ union { /* CRTB */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CRTB:32; /* CRTB */\r
+ } BIT; /* */\r
+ } CRTB; /* */\r
+ union { /* CHSTAT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD EN:1; /* EN */\r
+ _UDWORD RQST:1; /* RQST */\r
+ _UDWORD TACT:1; /* TACT */\r
+ _UDWORD SUS:1; /* SUS */\r
+ _UDWORD ER:1; /* ER */\r
+ _UDWORD END:1; /* END */\r
+ _UDWORD TC:1; /* TC */\r
+ _UDWORD SR:1; /* SR */\r
+ _UDWORD DL:1; /* DL */\r
+ _UDWORD DW:1; /* DW */\r
+ _UDWORD DER:1; /* DER */\r
+ _UDWORD MODE:1; /* MODE */\r
+ _UWORD :4; /* */\r
+ _UDWORD INTMSK:1; /* INTMSK */\r
+ _UWORD :15; /* */\r
+ } BIT; /* */\r
+ } CHSTAT; /* */\r
+ union { /* CHCTRL */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SETEN:1; /* SETEN */\r
+ _UDWORD CLREN:1; /* CLREN */\r
+ _UDWORD STG:1; /* STG */\r
+ _UDWORD SWRST:1; /* SWRST */\r
+ _UDWORD CLRRQ:1; /* CLRRQ */\r
+ _UDWORD CLREND:1; /* CLREND */\r
+ _UDWORD CLRTC:1; /* CLRTC */\r
+ _UWORD :1; /* */\r
+ _UDWORD SETSUS:1; /* SETSUS */\r
+ _UDWORD CLRSUS:1; /* CLRSUS */\r
+ _UWORD :6; /* */\r
+ _UDWORD SETINTMSK:1; /* SETINTMSK */\r
+ _UDWORD CLRINTMSK:1; /* CLRINTMSK */\r
+ _UWORD :14; /* */\r
+ } BIT; /* */\r
+ } CHCTRL; /* */\r
+ union { /* CHCFG */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SEL:3; /* SEL */\r
+ _UDWORD REQD:1; /* REQD */\r
+ _UDWORD LOEN:1; /* LOEN */\r
+ _UDWORD HIEN:1; /* HIEN */\r
+ _UDWORD LVL:1; /* LVL */\r
+ _UWORD :1; /* */\r
+ _UDWORD AM:3; /* AM */\r
+ _UWORD :1; /* */\r
+ _UDWORD SDS:4; /* SDS */\r
+ _UDWORD DDS:4; /* DDS */\r
+ _UDWORD SAD:1; /* SAD */\r
+ _UDWORD DAD:1; /* DAD */\r
+ _UDWORD TM:1; /* TM */\r
+ _UWORD :1; /* */\r
+ _UDWORD DEM:1; /* DEM */\r
+ _UDWORD TCM:1; /* TCM */\r
+ _UWORD :1; /* */\r
+ _UDWORD SBE:1; /* SBE */\r
+ _UDWORD RSEL:1; /* RSEL */\r
+ _UDWORD RSW:1; /* RSW */\r
+ _UDWORD REN:1; /* REN */\r
+ _UDWORD DMS:1; /* DMS */\r
+ } BIT; /* */\r
+ } CHCFG; /* */\r
+ union { /* CHITVL */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ITVL:16; /* ITVL */\r
+ _UWORD :16; /* */\r
+ } BIT; /* */\r
+ } CHITVL; /* */\r
+ union { /* CHEXT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :4; /* */\r
+ _UDWORD SCA:4; /* SCA */\r
+ _UWORD :4; /* */\r
+ _UDWORD DCA:4; /* DCA */\r
+ _UWORD :16; /* */\r
+ } CHEXT; /* */\r
+ } CHEXT; /* */\r
+ union { /* NXLA */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD NXLA:32; /* NXLA */\r
+ } BIT; /* */\r
+ } NXLA; /* */\r
+ union { /* CRLA */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CRLA:32; /* CRLA */\r
+ } BIT; /* */\r
+ } CRLA; /* */\r
+}; /* */\r
+\r
+struct st_dmac_07 { /* struct DMAC */\r
+ union { /* DCTRL */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD PR:1; /* PR */\r
+ _UDWORD LVINT:1; /* LVINT */\r
+ _UWORD :18; /* */\r
+ _UDWORD LDCA:4; /* LDCA */\r
+ _UWORD :4; /* */\r
+ _UDWORD LWCA:4; /* LWCA */\r
+ } BIT; /* */\r
+ } DCTRL; /* */\r
+ union { /* DSTAT_EN */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD EN0:1; /* EN0 */\r
+ _UDWORD EN1:1; /* EN1 */\r
+ _UDWORD EN2:1; /* EN2 */\r
+ _UDWORD EN3:1; /* EN3 */\r
+ _UDWORD EN4:1; /* EN4 */\r
+ _UDWORD EN5:1; /* EN5 */\r
+ _UDWORD EN6:1; /* EN6 */\r
+ _UDWORD EN7:1; /* EN7 */\r
+ _UWORD :24; /* */\r
+ } BIT; /* */\r
+ } DSTAT_EN; /* */\r
+ union { /* DSTAT_ER */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ER0:1; /* ER0 */\r
+ _UDWORD ER1:1; /* ER1 */\r
+ _UDWORD ER2:1; /* ER2 */\r
+ _UDWORD ER3:1; /* ER3 */\r
+ _UDWORD ER4:1; /* ER4 */\r
+ _UDWORD ER5:1; /* ER5 */\r
+ _UDWORD ER6:1; /* ER6 */\r
+ _UDWORD ER7:1; /* ER7 */\r
+ _UWORD :24; /* */\r
+ } BIT; /* */\r
+ } DSTAT_ER; /* */\r
+ union { /* DSTAT_END */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD END0:1; /* END0 */\r
+ _UDWORD END1:1; /* END1 */\r
+ _UDWORD END2:1; /* END2 */\r
+ _UDWORD END3:1; /* END3 */\r
+ _UDWORD END4:1; /* END4 */\r
+ _UDWORD END5:1; /* END5 */\r
+ _UDWORD END6:1; /* END6 */\r
+ _UDWORD END7:1; /* END7 */\r
+ _UWORD :24; /* */\r
+ } BIT; /* */\r
+ } DSTAT_END; /* */\r
+ union { /* DSTAT_TC */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TC0:1; /* TC0 */\r
+ _UDWORD TC1:1; /* TC1 */\r
+ _UDWORD TC2:1; /* TC2 */\r
+ _UDWORD TC3:1; /* TC3 */\r
+ _UDWORD TC4:1; /* TC4 */\r
+ _UDWORD TC5:1; /* TC5 */\r
+ _UDWORD TC6:1; /* TC6 */\r
+ _UDWORD TC7:1; /* TC7 */\r
+ _UWORD :24; /* */\r
+ } BIT; /* */\r
+ } DSTAT_TC; /* */\r
+ union { /* DSTAT_SUS */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SUS0:1; /* SUS0 */\r
+ _UDWORD SUS1:1; /* SUS1 */\r
+ _UDWORD SUS2:1; /* SUS2 */\r
+ _UDWORD SUS3:1; /* SUS3 */\r
+ _UDWORD SUS4:1; /* SUS4 */\r
+ _UDWORD SUS5:1; /* SUS5 */\r
+ _UDWORD SUS6:1; /* SUS6 */\r
+ _UDWORD SUS7:1; /* SUS7 */\r
+ _UWORD :24; /* */\r
+ } BIT; /* */\r
+ } DSTAT_SUS; /* */\r
+}; /* */\r
+\r
+struct st_dmac_815 { /* struct DMAC */\r
+ union { /* DCTRL */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD PR:1; /* PR */\r
+ _UDWORD LVINT:1; /* LVINT */\r
+ _UWORD :18; /* */\r
+ _UDWORD LDCA:4; /* LDCA */\r
+ _UWORD :4; /* */\r
+ _UDWORD LWCA:4; /* LWCA */\r
+ } BIT; /* */\r
+ } DCTRL; /* */\r
+ union { /* DSTAT_EN */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD EN8:1; /* EN8 */\r
+ _UDWORD EN9:1; /* EN9 */\r
+ _UDWORD EN10:1; /* EN10 */\r
+ _UDWORD EN11:1; /* EN11 */\r
+ _UDWORD EN12:1; /* EN12 */\r
+ _UDWORD EN13:1; /* EN13 */\r
+ _UDWORD EN14:1; /* EN14 */\r
+ _UDWORD EN15:1; /* EN15 */\r
+ _UWORD :24; /* */\r
+ } BIT; /* */\r
+ } DSTAT_EN; /* */\r
+ union { /* DSTAT_ER */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ER8:1; /* ER8 */\r
+ _UDWORD ER9:1; /* ER9 */\r
+ _UDWORD ER10:1; /* ER10 */\r
+ _UDWORD ER11:1; /* ER11 */\r
+ _UDWORD ER12:1; /* ER12 */\r
+ _UDWORD ER13:1; /* ER13 */\r
+ _UDWORD ER14:1; /* ER14 */\r
+ _UDWORD ER15:1; /* ER15 */\r
+ _UWORD :24; /* */\r
+ } BIT; /* */\r
+ } DSTAT_ER; /* */\r
+ union { /* DSTAT_END */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD END8:1; /* END8 */\r
+ _UDWORD END9:1; /* END9 */\r
+ _UDWORD END10:1; /* END10 */\r
+ _UDWORD END11:1; /* END11 */\r
+ _UDWORD END12:1; /* END12 */\r
+ _UDWORD END13:1; /* END13 */\r
+ _UDWORD END14:1; /* END14 */\r
+ _UDWORD END15:1; /* END15 */\r
+ _UWORD :24; /* */\r
+ } BIT; /* */\r
+ } DSTAT_END; /* */\r
+ union { /* DSTAT_TC */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TC8:1; /* TC8 */\r
+ _UDWORD TC9:1; /* TC9 */\r
+ _UDWORD TC10:1; /* TC10 */\r
+ _UDWORD TC11:1; /* TC11 */\r
+ _UDWORD TC12:1; /* TC12 */\r
+ _UDWORD TC13:1; /* TC13 */\r
+ _UDWORD TC14:1; /* TC14 */\r
+ _UDWORD TC15:1; /* TC15 */\r
+ _UWORD :24; /* */\r
+ } BIT; /* */\r
+ } DSTAT_TC; /* */\r
+ union { /* DSTAT_SUS */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SUS8:1; /* SUS8 */\r
+ _UDWORD SUS9:1; /* SUS9 */\r
+ _UDWORD SUS10:1; /* SUS10 */\r
+ _UDWORD SUS11:1; /* SUS11 */\r
+ _UDWORD SUS12:1; /* SUS12 */\r
+ _UDWORD SUS13:1; /* SUS13 */\r
+ _UDWORD SUS14:1; /* SUS14 */\r
+ _UDWORD SUS15:1; /* SUS15 */\r
+ _UWORD :24; /* */\r
+ } BIT; /* */\r
+ } DSTAT_SUS; /* */\r
+}; /* */\r
+\r
+struct st_dmac_01 { /* struct DMAC */\r
+ union { /* DMARS */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CH0_RID:2; /* CH0_RID */\r
+ _UDWORD CH0_MID:7; /* CH0_MID */\r
+ _UWORD :7; /* */\r
+ _UDWORD CH1_RID:2; /* CH1_RID */\r
+ _UDWORD CH1_MID:7; /* CH1_MID */\r
+ _UWORD :7; /* */\r
+ } BIT; /* */\r
+ } DMARS; /* */\r
+}; /* */\r
+\r
+struct st_dmac_23 { /* struct DMAC */\r
+ union { /* DMARS */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CH2_RID:2; /* CH2_RID */\r
+ _UDWORD CH2_MID:7; /* CH2_MID */\r
+ _UWORD :7; /* */\r
+ _UDWORD CH3_RID:2; /* CH3_RID */\r
+ _UDWORD CH3_MID:7; /* CH3_MID */\r
+ _UWORD :7; /* */\r
+ } BIT; /* */\r
+ } DMARS; /* */\r
+}; /* */\r
+\r
+struct st_dmac_45 { /* struct DMAC */\r
+ union { /* DMARS */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CH4_RID:2; /* CH4_RID */\r
+ _UDWORD CH4_MID:7; /* CH4_MID */\r
+ _UWORD :7; /* */\r
+ _UDWORD CH5_RID:2; /* CH5_RID */\r
+ _UDWORD CH5_MID:7; /* CH5_MID */\r
+ _UWORD :7; /* */\r
+ } BIT; /* */\r
+ } DMARS; /* */\r
+}; /* */\r
+\r
+struct st_dmac_67 { /* struct DMAC */\r
+ union { /* DMARS */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CH6_RID:2; /* CH6_RID */\r
+ _UDWORD CH6_MID:7; /* CH6_MID */\r
+ _UWORD :7; /* */\r
+ _UDWORD CH7_RID:2; /* CH7_RID */\r
+ _UDWORD CH7_MID:7; /* CH7_MID */\r
+ _UWORD :7; /* */\r
+ } BIT; /* */\r
+ } DMARS; /* */\r
+}; /* */\r
+\r
+struct st_dmac_89 { /* struct DMAC */\r
+ union { /* DMARS */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CH8_RID:2; /* CH8_RID */\r
+ _UDWORD CH8_MID:7; /* CH8_MID */\r
+ _UWORD :7; /* */\r
+ _UDWORD CH9_RID:2; /* CH9_RID */\r
+ _UDWORD CH9_MID:7; /* CH9_MID */\r
+ _UWORD :7; /* */\r
+ } BIT; /* */\r
+ } DMARS; /* */\r
+}; /* */\r
+\r
+struct st_dmac_1011 { /* struct DMAC */\r
+ union { /* DMARS */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CH10_RID:2; /* CH10_RID */\r
+ _UDWORD CH10_MID:7; /* CH10_MID */\r
+ _UWORD :7; /* */\r
+ _UDWORD CH11_RID:2; /* CH11_RID */\r
+ _UDWORD CH11_MID:7; /* CH11_MID */\r
+ _UWORD :7; /* */\r
+ } BIT; /* */\r
+ } DMARS; /* */\r
+}; /* */\r
+\r
+struct st_dmac_1213 { /* struct DMAC */\r
+ union { /* DMARS */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CH12_RID:2; /* CH12_RID */\r
+ _UDWORD CH12_MID:7; /* CH12_MID */\r
+ _UWORD :7; /* */\r
+ _UDWORD CH13_RID:2; /* CH13_RID */\r
+ _UDWORD CH13_MID:7; /* CH13_MID */\r
+ _UWORD :7; /* */\r
+ } BIT; /* */\r
+ } DMARS; /* */\r
+}; /* */\r
+\r
+struct st_dmac_1415 { /* struct DMAC */\r
+ union { /* DMARS */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CH14_RID:2; /* CH14_RID */\r
+ _UDWORD CH14_MID:7; /* CH14_MID */\r
+ _UWORD :7; /* */\r
+ _UDWORD CH15_RID:2; /* CH15_RID */\r
+ _UDWORD CH15_MID:7; /* CH15_MID */\r
+ _UWORD :7; /* */\r
+ } BIT; /* */\r
+ } DMARS; /* */\r
+}; /* */\r
+\r
+#define DMAC0 (*(volatile struct st_dmac_n *)0xE8200000) /* DMAC0 Address */\r
+#define DMAC1 (*(volatile struct st_dmac_n *)0xE8200040) /* DMAC1 Address */\r
+#define DMAC2 (*(volatile struct st_dmac_n *)0xE8200080) /* DMAC2 Address */\r
+#define DMAC3 (*(volatile struct st_dmac_n *)0xE82000C0) /* DMAC3 Address */\r
+#define DMAC4 (*(volatile struct st_dmac_n *)0xE8200100) /* DMAC4 Address */\r
+#define DMAC5 (*(volatile struct st_dmac_n *)0xE8200140) /* DMAC5 Address */\r
+#define DMAC6 (*(volatile struct st_dmac_n *)0xE8200180) /* DMAC6 Address */\r
+#define DMAC7 (*(volatile struct st_dmac_n *)0xE82001C0) /* DMAC7 Address */\r
+#define DMAC8 (*(volatile struct st_dmac_n *)0xE8200400) /* DMAC8 Address */\r
+#define DMAC9 (*(volatile struct st_dmac_n *)0xE8200440) /* DMAC9 Address */\r
+#define DMAC10 (*(volatile struct st_dmac_n *)0xE8200480) /* DMAC10 Address */\r
+#define DMAC11 (*(volatile struct st_dmac_n *)0xE82004C0) /* DMAC11 Address */\r
+#define DMAC12 (*(volatile struct st_dmac_n *)0xE8200500) /* DMAC12 Address */\r
+#define DMAC13 (*(volatile struct st_dmac_n *)0xE8200540) /* DMAC13 Address */\r
+#define DMAC14 (*(volatile struct st_dmac_n *)0xE8200580) /* DMAC14 Address */\r
+#define DMAC15 (*(volatile struct st_dmac_n *)0xE82005C0) /* DMAC15 Address */\r
+\r
+#define DMAC07 (*(volatile struct st_dmac_07 *)0xE8200300) /* DMAC0-7 Address */\r
+#define DMAC815 (*(volatile struct st_dmac_815 *)0xE8200700) /* DMAC8-15 Address */\r
+\r
+#define DMAC01 (*(volatile struct st_dmac_01 *)0xFCFE1000) /* DMAC0-1 Address */\r
+#define DMAC23 (*(volatile struct st_dmac_23 *)0xFCFE1004) /* DMAC2-3 Address */\r
+#define DMAC45 (*(volatile struct st_dmac_45 *)0xFCFE1008) /* DMAC4-5 Address */\r
+#define DMAC67 (*(volatile struct st_dmac_67 *)0xFCFE100C) /* DMAC6-7 Address */\r
+#define DMAC89 (*(volatile struct st_dmac_89 *)0xFCFE1010) /* DMAC8-9 Address */\r
+#define DMAC1011 (*(volatile struct st_dmac_1011 *)0xFCFE1014) /* DMAC10-11 Address */\r
+#define DMAC1213 (*(volatile struct st_dmac_1213 *)0xFCFE1018) /* DMAC12-13 Address */\r
+#define DMAC1415 (*(volatile struct st_dmac_1415 *)0xFCFE101C) /* DMAC14-15 Address */\r
+\r
+#endif /* __DMAC_IODEFINE_H__ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : intc_iodefine.h\r
+* Version : 0.01\r
+* Device(s) : Aragon\r
+* Tool-Chain : DS-5 Ver 5.13\r
+* ARM Complier \r
+* : \r
+* H/W Platform : Aragon CPU Board\r
+* Description : Aragon Sample Program vecotr.s\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+*******************************************************************************/\r
+#ifndef __INTC_IODEFINE_H__\r
+#define __INTC_IODEFINE_H__\r
+\r
+#include "typedefine.h"\r
+\r
+typedef union { /* ICDxxx0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SW0:1; /* SW0 */\r
+ _UDWORD SW1:1; /* SW1 */\r
+ _UDWORD SW2:1; /* SW2 */\r
+ _UDWORD SW3:1; /* SW3 */\r
+ _UDWORD SW4:1; /* SW4 */\r
+ _UDWORD SW5:1; /* SW5 */\r
+ _UDWORD SW6:1; /* SW6 */\r
+ _UDWORD SW7:1; /* SW7 */\r
+ _UDWORD SW8:1; /* SW8 */\r
+ _UDWORD SW9:1; /* SW9 */\r
+ _UDWORD SW10:1; /* SW10 */\r
+ _UDWORD SW11:1; /* SW11 */\r
+ _UDWORD SW12:1; /* SW12 */\r
+ _UDWORD SW13:1; /* SW13 */\r
+ _UDWORD SW14:1; /* SW14 */\r
+ _UDWORD SW15:1; /* SW15 */\r
+ _UDWORD PMUIRQ0:1; /* PMUIRQ0 */\r
+ _UDWORD COMMRX0:1; /* COMMRX0 */\r
+ _UDWORD COMMTX0:1; /* COMMTX0 */\r
+ _UDWORD CTIIRQ0:1; /* CTIIRQ0 */\r
+ _UDWORD :12; /* */\r
+ } BIT; /* */\r
+} ICDxxx0; /* */\r
+typedef union { /* ICDxxx1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IRQ0:1; /* IRQ0 */\r
+ _UDWORD IRQ1:1; /* IRQ1 */\r
+ _UDWORD IRQ2:1; /* IRQ2 */\r
+ _UDWORD IRQ3:1; /* IRQ3 */\r
+ _UDWORD IRQ4:1; /* IRQ4 */\r
+ _UDWORD IRQ5:1; /* IRQ5 */\r
+ _UDWORD IRQ6:1; /* IRQ6 */\r
+ _UDWORD IRQ7:1; /* IRQ7 */\r
+ _UDWORD PL310ERR:1; /* PL310ERR */\r
+ _UDWORD DMAINT0:1; /* DMAINT0 */\r
+ _UDWORD DMAINT1:1; /* DMAINT1 */\r
+ _UDWORD DMAINT2:1; /* DMAINT2 */\r
+ _UDWORD DMAINT3:1; /* DMAINT3 */\r
+ _UDWORD DMAINT4:1; /* DMAINT4 */\r
+ _UDWORD DMAINT5:1; /* DMAINT5 */\r
+ _UDWORD DMAINT6:1; /* DMAINT6 */\r
+ _UDWORD DMAINT7:1; /* DMAINT7 */\r
+ _UDWORD DMAINT8:1; /* DMAINT8 */\r
+ _UDWORD DMAINT9:1; /* DMAINT9 */\r
+ _UDWORD DMAINT10:1; /* DMAINT10 */\r
+ _UDWORD DMAINT11:1; /* DMAINT11 */\r
+ _UDWORD DMAINT12:1; /* DMAINT12 */\r
+ _UDWORD DMAINT13:1; /* DMAINT13 */\r
+ _UDWORD DMAINT14:1; /* DMAINT14 */\r
+ _UDWORD DMAINT15:1; /* DMAINT15 */\r
+ _UDWORD DMAERR:1; /* DMAERR */\r
+ _UDWORD :6; /* */\r
+ } BIT; /* */\r
+} ICDxxx1; /* */\r
+typedef union { /* ICDxxx2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :9; /* */\r
+ _UDWORD USBI0:1; /* USBI0 */\r
+ _UDWORD USBI1:1; /* USBI1 */\r
+ _UDWORD S0_VI_VSYNC0:1; /* S0_VI_VSYNC0 */\r
+ _UDWORD S0_LO_VSYNC0:1; /* S0_LO_VSYNC0 */\r
+ _UDWORD S0_VSYNCERR0:1; /* S0_VSYNCERR0 */\r
+ _UDWORD GR3_VLINE0:1; /* GR3_VLINE0 */\r
+ _UDWORD S0_VFIELD0:1; /* S0_VFIELD0 */\r
+ _UDWORD IV1_VBUFERR0:1; /* IV1_VBUFERR0 */\r
+ _UDWORD IV3_VBUFERR0:1; /* IV3_VBUFERR0 */\r
+ _UDWORD IV5_VBUFERR0:1; /* IV5_VBUFERR0 */\r
+ _UDWORD IV6_VBUFERR0:1; /* IV6_VBUFERR0 */\r
+ _UDWORD S0_WLINE0:1; /* S0_WLINE0 */\r
+ _UDWORD S1_VI_VSYNC0:1; /* S1_VI_VSYNC0 */\r
+ _UDWORD S1_LO_VSYNC0:1; /* S1_LO_VSYNC0 */\r
+ _UDWORD S1_VSYNCERR0:1; /* S1_VSYNCERR0 */\r
+ _UDWORD S1_VFIELD0:1; /* S1_VFIELD0 */\r
+ _UDWORD IV2_VBUFERR0:1; /* IV2_VBUFERR0 */\r
+ _UDWORD IV4_VBUFERR0:1; /* IV4_VBUFERR0 */\r
+ _UDWORD S1_WLINE0:1; /* S1_WLINE0 */\r
+ _UDWORD OIR_VI_VSYNC0:1; /* OIR_VI_VSYNC0 */\r
+ _UDWORD OIR_LO_VSYNC0:1; /* OIR_LO_VSYNC0 */\r
+ _UDWORD OIR_VSYNCERR0:1; /* OIR_VSYNCERR0 */\r
+ _UDWORD OIR_VFIELD0:1; /* OIR_VFIELD0 */\r
+ } BIT; /* */\r
+} ICDxxx2; /* */\r
+typedef union { /* ICDxxx3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IV7_VBUFERR0:1; /* IV7_VBUFERR0 */\r
+ _UDWORD IV8_VBUFERR0:1; /* IV8_VBUFERR0 */\r
+ _UDWORD OIR_WLINE0:1; /* OIR_WLINE0 */\r
+ _UDWORD S0_VI_VSYNC1:1; /* S0_VI_VSYNC1 */\r
+ _UDWORD S0_LO_VSYNC1:1; /* S0_LO_VSYNC1 */\r
+ _UDWORD S0_VSYNCERR1:1; /* S0_VSYNCERR1 */\r
+ _UDWORD GR3_VLINE1:1; /* GR3_VLINE1 */\r
+ _UDWORD S0_VFIELD1:1; /* S0_VFIELD1 */\r
+ _UDWORD IV1_VBUFERR1:1; /* IV1_VBUFERR1 */\r
+ _UDWORD IV3_VBUFERR1:1; /* IV3_VBUFERR1 */\r
+ _UDWORD IV5_VBUFERR1:1; /* IV5_VBUFERR1 */\r
+ _UDWORD IV6_VBUFERR1:1; /* IV6_VBUFERR1 */\r
+ _UDWORD S0_WLINE1:1; /* S0_WLINE1 */\r
+ _UDWORD S1_VI_VSYNC1:1; /* S1_VI_VSYNC1 */\r
+ _UDWORD S1_LO_VSYNC1:1; /* S1_LO_VSYNC1 */\r
+ _UDWORD S1_VSYNCERR1:1; /* S1_VSYNCERR1 */\r
+ _UDWORD S1_VFIELD1:1; /* S1_VFIELD1 */\r
+ _UDWORD IV2_VBUFERR1:1; /* IV2_VBUFERR1 */\r
+ _UDWORD IV4_VBUFERR1:1; /* IV4_VBUFERR1 */\r
+ _UDWORD S1_WLINE1:1; /* S1_WLINE1 */\r
+ _UDWORD OIR_VI_VSYNC1:1; /* OIR_VI_VSYNC1 */\r
+ _UDWORD OIR_LO_VSYNC1:1; /* OIR_LO_VSYNC1 */\r
+ _UDWORD OIR_VLINE1:1; /* OIR_VLINE1 */\r
+ _UDWORD OIR_VFIELD1:1; /* OIR_VFIELD1 */\r
+ _UDWORD IV7_VBUFERR1:1; /* IV7_VBUFERR1 */\r
+ _UDWORD IV8_VBUFERR1:1; /* IV8_VBUFERR1 */\r
+ _UDWORD OIR_WLINE1:1; /* OIR_WLINE1 */\r
+ _UDWORD IMRDI:1; /* IMRDI */\r
+ _UDWORD IMR2I0:1; /* IMR2I0 */\r
+ _UDWORD IMR2I1:1; /* IMR2I1 */\r
+ _UDWORD JEDI:1; /* JEDI */\r
+ _UDWORD JDTI:1; /* JDTI */\r
+ } BIT; /* */\r
+} ICDxxx3; /* */\r
+typedef union { /* ICDxxx4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CMP0:1; /* CMP0 */\r
+ _UDWORD CMP1:1; /* CMP1 */\r
+ _UDWORD INT0:1; /* INT0 */\r
+ _UDWORD INT1:1; /* INT1 */\r
+ _UDWORD INT2:1; /* INT2 */\r
+ _UDWORD INT3:1; /* INT3 */\r
+ _UDWORD OSTMI0:1; /* OSTMI0 */\r
+ _UDWORD OSTMI1:1; /* OSTMI1 */\r
+ _UDWORD CMI:1; /* CMI */\r
+ _UDWORD WTOUT:1; /* WTOUT */\r
+ _UDWORD ITI:1; /* ITI */\r
+ _UDWORD TGI0A:1; /* TGI0A */\r
+ _UDWORD TGI0B:1; /* TGI0B */\r
+ _UDWORD TGI0C:1; /* TGI0C */\r
+ _UDWORD TGI0D:1; /* TGI0D */\r
+ _UDWORD TGI0V:1; /* TGI0V */\r
+ _UDWORD TGI0E:1; /* TGI0E */\r
+ _UDWORD TGI0F:1; /* TGI0F */\r
+ _UDWORD TGI1A:1; /* TGI1A */\r
+ _UDWORD TGI1B:1; /* TGI1B */\r
+ _UDWORD TGI1V:1; /* TGI1V */\r
+ _UDWORD TGI1U:1; /* TGI1U */\r
+ _UDWORD TGI2A:1; /* TGI2A */\r
+ _UDWORD TGI2B:1; /* TGI2B */\r
+ _UDWORD TGI2V:1; /* TGI2V */\r
+ _UDWORD TGI2U:1; /* TGI2U */\r
+ _UDWORD TGI3A:1; /* TGI3A */\r
+ _UDWORD TGI3B:1; /* TGI3B */\r
+ _UDWORD TGI3C:1; /* TGI3C */\r
+ _UDWORD TGI3D:1; /* TGI3D */\r
+ _UDWORD TGI3V:1; /* TGI3V */\r
+ _UDWORD TGI4A:1; /* TGI4A */\r
+ } BIT; /* */\r
+} ICDxxx4; /* */\r
+typedef union { /* ICDxxx5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TGI4B:1; /* TGI4B */\r
+ _UDWORD TGI4C:1; /* TGI4C */\r
+ _UDWORD TGI4D:1; /* TGI4D */\r
+ _UDWORD TGI4V:1; /* TGI4V */\r
+ _UDWORD CMI1:1; /* CMI1 */\r
+ _UDWORD CMI2:1; /* CMI2 */\r
+ _UDWORD SGDEI0:1; /* SGDEI0 */\r
+ _UDWORD SGDEI1:1; /* SGDEI1 */\r
+ _UDWORD SGDEI2:1; /* SGDEI2 */\r
+ _UDWORD SGDEI3:1; /* SGDEI3 */\r
+ _UDWORD ADI:1; /* ADI */\r
+ _UDWORD ADWAR:1; /* ADWAR */\r
+ _UDWORD SSII0:1; /* SSII0 */\r
+ _UDWORD SSIRXI0:1; /* SSIRXI0 */\r
+ _UDWORD SSITXI0:1; /* SSITXI0 */\r
+ _UDWORD SSII1:1; /* SSII1 */\r
+ _UDWORD SSIRXI1:1; /* SSIRXI1 */\r
+ _UDWORD SSITXI1:1; /* SSITXI1 */\r
+ _UDWORD SSII2:1; /* SSII2 */\r
+ _UDWORD SSIRTI2:1; /* SSIRTI2 */\r
+ _UDWORD SSII3:1; /* SSII3 */\r
+ _UDWORD SSIRXI3:1; /* SSIRXI3 */\r
+ _UDWORD SSITXI3:1; /* SSITXI3 */\r
+ _UDWORD SSII4:1; /* SSII4 */\r
+ _UDWORD SSIRTI4:1; /* SSIRTI4 */\r
+ _UDWORD SSII5:1; /* SSII5 */\r
+ _UDWORD SSIRXI5:1; /* SSIRXI5 */\r
+ _UDWORD SSITXI5:1; /* SSITXI5 */\r
+ _UDWORD SPDIFI:1; /* SPDIFI */\r
+ _UDWORD TEI0:1; /* TEI0 */\r
+ _UDWORD RI0:1; /* RI0 */\r
+ _UDWORD TI0:1; /* TI0 */\r
+ } BIT; /* */\r
+} ICDxxx5; /* */\r
+typedef union { /* ICDxxx6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPI0:1; /* SPI0 */\r
+ _UDWORD STI0:1; /* STI0 */\r
+ _UDWORD NAKI0:1; /* NAKI0 */\r
+ _UDWORD ALI0:1; /* ALI0 */\r
+ _UDWORD TMOI0:1; /* TMOI0 */\r
+ _UDWORD TEI1:1; /* TEI1 */\r
+ _UDWORD RI1:1; /* RI1 */\r
+ _UDWORD TI1:1; /* TI1 */\r
+ _UDWORD SPI1:1; /* SPI1 */\r
+ _UDWORD STI1:1; /* STI1 */\r
+ _UDWORD NAKI1:1; /* NAKI1 */\r
+ _UDWORD ALI1:1; /* ALI1 */\r
+ _UDWORD TMOI1:1; /* TMOI1 */\r
+ _UDWORD TEI2:1; /* TEI2 */\r
+ _UDWORD RI2:1; /* RI2 */\r
+ _UDWORD TI2:1; /* TI2 */\r
+ _UDWORD SPI2:1; /* SPI2 */\r
+ _UDWORD STI2:1; /* STI2 */\r
+ _UDWORD NAKI2:1; /* NAKI2 */\r
+ _UDWORD ALI2:1; /* ALI2 */\r
+ _UDWORD TMOI2:1; /* TMOI2 */\r
+ _UDWORD TEI3:1; /* TEI3 */\r
+ _UDWORD RI3:1; /* RI3 */\r
+ _UDWORD TI3:1; /* TI3 */\r
+ _UDWORD SPI3:1; /* SPI3 */\r
+ _UDWORD STI3:1; /* STI3 */\r
+ _UDWORD NAKI3:1; /* NAKI3 */\r
+ _UDWORD ALI3:1; /* ALI3 */\r
+ _UDWORD TMOI3:1; /* TMOI3 */\r
+ _UDWORD BRI0:1; /* BRI0 */\r
+ _UDWORD ERI0:1; /* ERI0 */\r
+ _UDWORD RXI0:1; /* RXI0 */\r
+ } BIT; /* */\r
+} ICDxxx6; /* */\r
+typedef union { /* ICDxxx7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI0:1; /* TXI0 */\r
+ _UDWORD BRI1:1; /* BRI1 */\r
+ _UDWORD ERI1:1; /* ERI1 */\r
+ _UDWORD RXI1:1; /* RXI1 */\r
+ _UDWORD TXI1:1; /* TXI1 */\r
+ _UDWORD BRI2:1; /* BRI2 */\r
+ _UDWORD ERI2:1; /* ERI2 */\r
+ _UDWORD RXI2:1; /* RXI2 */\r
+ _UDWORD TXI2:1; /* TXI2 */\r
+ _UDWORD BRI3:1; /* BRI3 */\r
+ _UDWORD ERI3:1; /* ERI3 */\r
+ _UDWORD RXI3:1; /* RXI3 */\r
+ _UDWORD TXI3:1; /* TXI3 */\r
+ _UDWORD BRI4:1; /* BRI4 */\r
+ _UDWORD ERI4:1; /* ERI4 */\r
+ _UDWORD RXI4:1; /* RXI4 */\r
+ _UDWORD TXI4:1; /* TXI4 */\r
+ _UDWORD BRI5:1; /* BRI5 */\r
+ _UDWORD ERI5:1; /* ERI5 */\r
+ _UDWORD RXI5:1; /* RXI5 */\r
+ _UDWORD TXI5:1; /* TXI5 */\r
+ _UDWORD BRI6:1; /* BRI6 */\r
+ _UDWORD ERI6:1; /* ERI6 */\r
+ _UDWORD RXI6:1; /* RXI6 */\r
+ _UDWORD TXI6:1; /* TXI6 */\r
+ _UDWORD BRI7:1; /* BRI7 */\r
+ _UDWORD ERI7:1; /* ERI7 */\r
+ _UDWORD RXI7:1; /* RXI7 */\r
+ _UDWORD TXI7:1; /* TXI7 */\r
+ _UDWORD GERI:1; /* GERI */\r
+ _UDWORD RFI:1; /* RFI */\r
+ _UDWORD CFRXI0:1; /* CFRXI0 */\r
+ } BIT; /* */\r
+} ICDxxx7; /* */\r
+typedef union { /* ICDxxx8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CERI0:1; /* CERI0 */\r
+ _UDWORD CTXI0:1; /* CTXI0 */\r
+ _UDWORD CFRXI1:1; /* CFRXI1 */\r
+ _UDWORD CERI1:1; /* CERI1 */\r
+ _UDWORD CTXI1:1; /* CTXI1 */\r
+ _UDWORD CFRXI2:1; /* CFRXI2 */\r
+ _UDWORD CERI2:1; /* CERI2 */\r
+ _UDWORD CTXI2:1; /* CTXI2 */\r
+ _UDWORD CFRXI3:1; /* CFRXI3 */\r
+ _UDWORD CERI3:1; /* CERI3 */\r
+ _UDWORD CTXI3:1; /* CTXI3 */\r
+ _UDWORD CFRXI4:1; /* CFRXI4 */\r
+ _UDWORD CERI4:1; /* CERI4 */\r
+ _UDWORD CTXI4:1; /* CTXI4 */\r
+ _UDWORD SPEI0:1; /* SPEI0 */\r
+ _UDWORD SPRI0:1; /* SPRI0 */\r
+ _UDWORD SPTI0:1; /* SPTI0 */\r
+ _UDWORD SPEI1:1; /* SPEI1 */\r
+ _UDWORD SPRI1:1; /* SPRI1 */\r
+ _UDWORD SPTI1:1; /* SPTI1 */\r
+ _UDWORD SPEI2:1; /* SPEI2 */\r
+ _UDWORD SPRI2:1; /* SPRI2 */\r
+ _UDWORD SPTI2:1; /* SPTI2 */\r
+ _UDWORD SPEI3:1; /* SPEI3 */\r
+ _UDWORD SPRI3:1; /* SPRI3 */\r
+ _UDWORD SPTI3:1; /* SPTI3 */\r
+ _UDWORD SPEI4:1; /* SPEI4 */\r
+ _UDWORD SPRI4:1; /* SPRI4 */\r
+ _UDWORD SPTI4:1; /* SPTI4 */\r
+ _UDWORD IEBBTD:1; /* IEBBTD */\r
+ _UDWORD IEBBTERR:1; /* IEBBTERR */\r
+ _UDWORD IEBBTSTA:1; /* IEBBTSTA */\r
+ } BIT; /* */\r
+} ICDxxx8; /* */\r
+typedef union { /* ICDxxx9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IEBBTV:1; /* IEBBTV */\r
+ _UDWORD ISY:1; /* ISY */\r
+ _UDWORD IERR:1; /* IERR */\r
+ _UDWORD ITARG:1; /* ITARG */\r
+ _UDWORD ISEC:1; /* ISEC */\r
+ _UDWORD IBUF:1; /* IBUF */\r
+ _UDWORD IREADY:1; /* IREADY */\r
+ _UDWORD FLSTE:1; /* FLSTE */\r
+ _UDWORD FLTENDI:1; /* FLTENDI */\r
+ _UDWORD FLTREQ0I:1; /* FLTREQ0I */\r
+ _UDWORD FLTREQ1I:1; /* FLTREQ1I */\r
+ _UDWORD MMC0:1; /* MMC0 */\r
+ _UDWORD MMC1:1; /* MMC1 */\r
+ _UDWORD MMC2:1; /* MMC2 */\r
+ _UDWORD SDHI0_3:1; /* SDHI0_3 */\r
+ _UDWORD SDHI0_0:1; /* SDHI0_0 */\r
+ _UDWORD SDHI0_1:1; /* SDHI0_1 */\r
+ _UDWORD SDHI1_3:1; /* SDHI1_3 */\r
+ _UDWORD SDHI1_0:1; /* SDHI1_0 */\r
+ _UDWORD SDHI1_1:1; /* SDHI1_1 */\r
+ _UDWORD ARM:1; /* ARM */\r
+ _UDWORD PRD:1; /* PRD */\r
+ _UDWORD CUP:1; /* CUP */\r
+ _UDWORD SCUAI0:1; /* SCUAI0 */\r
+ _UDWORD SCUAI1:1; /* SCUAI1 */\r
+ _UDWORD SCUFDI0:1; /* SCUFDI0 */\r
+ _UDWORD SCUFDI1:1; /* SCUFDI1 */\r
+ _UDWORD SCUFDI2:1; /* SCUFDI2 */\r
+ _UDWORD SCUFDI3:1; /* SCUFDI3 */\r
+ _UDWORD SCUFUI0:1; /* SCUFUI0 */\r
+ _UDWORD SCUFUI1:1; /* SCUFUI1 */\r
+ _UDWORD SCUFUI2:1; /* SCUFUI2 */\r
+ } BIT; /* */\r
+} ICDxxx9; /* */\r
+typedef union { /* ICDxxx10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SCUFUI3:1; /* SCUFUI3 */\r
+ _UDWORD SCUDVI0:1; /* SCUDVI0 */\r
+ _UDWORD SCUDVI1:1; /* SCUDVI1 */\r
+ _UDWORD SCUDVI2:1; /* SCUDVI2 */\r
+ _UDWORD SCUDVI3:1; /* SCUDVI3 */\r
+ _UDWORD MLBCI:1; /* MLBCI */\r
+ _UDWORD MLBSI:1; /* MLBSI */\r
+ _UDWORD DRC0:1; /* DRC0 */\r
+ _UDWORD DRC1:1; /* DRC1 */\r
+ _UDWORD :2; /* */\r
+ _UDWORD LINI0_INT_T:1; /* LINI0_INT_T */\r
+ _UDWORD LINI0_INT_R:1; /* LINI0_INT_R */\r
+ _UDWORD LINI0_INT_S:1; /* LINI0_INT_S */\r
+ _UDWORD LINI0_INT_M:1; /* LINI0_INT_M */\r
+ _UDWORD LINI1_INT_T:1; /* LINI1_INT_T */\r
+ _UDWORD LINI1_INT_R:1; /* LINI1_INT_R */\r
+ _UDWORD LINI1_INT_S:1; /* LINI1_INT_S */\r
+ _UDWORD LINI1_INT_M:1; /* LINI1_INT_M */\r
+ _UDWORD :8; /* */\r
+ _UDWORD ERI0:1; /* ERI0 */\r
+ _UDWORD RXI0:1; /* RXI0 */\r
+ _UDWORD TXI0:1; /* TXI0 */\r
+ _UDWORD TEI0:1; /* TEI0 */\r
+ _UDWORD ERI1:1; /* ERI1 */\r
+ } BIT; /* */\r
+} ICDxxx10; /* */\r
+typedef union { /* ICDxxx11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD RXI1:1; /* RXI1 */\r
+ _UDWORD TXI1:1; /* TXI1 */\r
+ _UDWORD TEI1:1; /* TEI1 */\r
+ _UDWORD :4; /* */\r
+ _UDWORD ETHERI:1; /* ETHERI */\r
+ _UDWORD :4; /* */\r
+ _UDWORD CEUI:1; /* CEUI */\r
+ _UDWORD INT_CSIH0TIR:1; /* INT_CSIH0TIR */\r
+ _UDWORD INT_CSIH0TIRE:1; /* INT_CSIH0TIRE */\r
+ _UDWORD INT_CSIH1TIC:1; /* INT_CSIH1TIC */\r
+ _UDWORD INT_CSIH1TIJC:1; /* INT_CSIH1TIJC */\r
+ _UDWORD ECCE10:1; /* ECCE10 */\r
+ _UDWORD ECCE20:1; /* ECCE20 */\r
+ _UDWORD ECCOVF0:1; /* ECCOVF0 */\r
+ _UDWORD ECCE11:1; /* ECCE11 */\r
+ _UDWORD ECCE21:1; /* ECCE21 */\r
+ _UDWORD ECCOVF1:1; /* ECCOVF1 */\r
+ _UDWORD ECCE12:1; /* ECCE12 */\r
+ _UDWORD ECCE22:1; /* ECCE22 */\r
+ _UDWORD ECCOVF2:1; /* ECCOVF2 */\r
+ _UDWORD ECCE13:1; /* ECCE13 */\r
+ _UDWORD ECCE23:1; /* ECCE23 */\r
+ _UDWORD ECCOVF3:1; /* ECCOVF3 */\r
+ _UDWORD H2XMLB_ERRINT:1; /* H2XMLB_ERRINT */\r
+ _UDWORD H2XIC1_ERRINT:1; /* H2XIC1_ERRINT */\r
+ _UDWORD X2HPERI1_ERRINT:1; /* X2HPERI1_ERRINT */\r
+ } BIT; /* */\r
+} ICDxxx11; /* */\r
+typedef union { /* ICDxxx12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD X2HPERI2_ERRINT:1; /* X2HPERI2_ERRINT */\r
+ _UDWORD X2HPERI34_ERRINT:1; /* X2HPERI34_ERRINT */\r
+ _UDWORD X2HPERI5_ERRINT:1; /* X2HPERI5_ERRINT */\r
+ _UDWORD X2HPERI67_ERRINT:1; /* X2HPERI67_ERRINT */\r
+ _UDWORD X2HDBGR_ERRINT:1; /* X2HDBGR_ERRINT */\r
+ _UDWORD PRRI:1; /* PRRI */\r
+ _UDWORD IFEI0:1; /* IFEI0 */\r
+ _UDWORD OFFI0:1; /* OFFI0 */\r
+ _UDWORD PFVEI0:1; /* PFVEI0 */\r
+ _UDWORD IFEI1:1; /* IFEI1 */\r
+ _UDWORD OFFI1:1; /* OFFI1 */\r
+ _UDWORD PFVEI1:1; /* PFVEI1 */\r
+ _UDWORD :20; /* */\r
+ } BIT; /* */\r
+} ICDxxx12; /* */\r
+typedef union { /* ICDxxx13 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT0:1; /* TINT0 */\r
+ _UDWORD TINT1:1; /* TINT1 */\r
+ _UDWORD TINT2:1; /* TINT2 */\r
+ _UDWORD TINT3:1; /* TINT3 */\r
+ _UDWORD TINT4:1; /* TINT4 */\r
+ _UDWORD TINT5:1; /* TINT5 */\r
+ _UDWORD TINT6:1; /* TINT6 */\r
+ _UDWORD TINT7:1; /* TINT7 */\r
+ _UDWORD TINT8:1; /* TINT8 */\r
+ _UDWORD TINT9:1; /* TINT9 */\r
+ _UDWORD TINT10:1; /* TINT10 */\r
+ _UDWORD TINT11:1; /* TINT11 */\r
+ _UDWORD TINT12:1; /* TINT12 */\r
+ _UDWORD TINT13:1; /* TINT13 */\r
+ _UDWORD TINT14:1; /* TINT14 */\r
+ _UDWORD TINT15:1; /* TINT15 */\r
+ _UDWORD TINT16:1; /* TINT16 */\r
+ _UDWORD TINT17:1; /* TINT17 */\r
+ _UDWORD TINT18:1; /* TINT18 */\r
+ _UDWORD TINT19:1; /* TINT19 */\r
+ _UDWORD TINT20:1; /* TINT20 */\r
+ _UDWORD TINT21:1; /* TINT21 */\r
+ _UDWORD TINT22:1; /* TINT22 */\r
+ _UDWORD TINT23:1; /* TINT23 */\r
+ _UDWORD TINT24:1; /* TINT24 */\r
+ _UDWORD TINT25:1; /* TINT25 */\r
+ _UDWORD TINT26:1; /* TINT26 */\r
+ _UDWORD TINT27:1; /* TINT27 */\r
+ _UDWORD TINT28:1; /* TINT28 */\r
+ _UDWORD TINT29:1; /* TINT29 */\r
+ _UDWORD TINT30:1; /* TINT30 */\r
+ _UDWORD TINT31:1; /* TINT31 */\r
+ } BIT; /* */\r
+} ICDxxx13; /* */\r
+typedef union { /* ICDxxx14 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT32:1; /* TINT32 */\r
+ _UDWORD TINT33:1; /* TINT33 */\r
+ _UDWORD TINT34:1; /* TINT34 */\r
+ _UDWORD TINT35:1; /* TINT35 */\r
+ _UDWORD TINT36:1; /* TINT36 */\r
+ _UDWORD TINT37:1; /* TINT37 */\r
+ _UDWORD TINT38:1; /* TINT38 */\r
+ _UDWORD TINT39:1; /* TINT39 */\r
+ _UDWORD TINT40:1; /* TINT40 */\r
+ _UDWORD TINT41:1; /* TINT41 */\r
+ _UDWORD TINT42:1; /* TINT42 */\r
+ _UDWORD TINT43:1; /* TINT43 */\r
+ _UDWORD TINT44:1; /* TINT44 */\r
+ _UDWORD TINT45:1; /* TINT45 */\r
+ _UDWORD TINT46:1; /* TINT46 */\r
+ _UDWORD TINT47:1; /* TINT47 */\r
+ _UDWORD TINT48:1; /* TINT48 */\r
+ _UDWORD TINT49:1; /* TINT49 */\r
+ _UDWORD TINT50:1; /* TINT50 */\r
+ _UDWORD TINT51:1; /* TINT51 */\r
+ _UDWORD TINT52:1; /* TINT52 */\r
+ _UDWORD TINT53:1; /* TINT53 */\r
+ _UDWORD TINT54:1; /* TINT54 */\r
+ _UDWORD TINT55:1; /* TINT55 */\r
+ _UDWORD TINT56:1; /* TINT56 */\r
+ _UDWORD TINT57:1; /* TINT57 */\r
+ _UDWORD TINT58:1; /* TINT58 */\r
+ _UDWORD TINT59:1; /* TINT59 */\r
+ _UDWORD TINT60:1; /* TINT60 */\r
+ _UDWORD TINT61:1; /* TINT61 */\r
+ _UDWORD TINT62:1; /* TINT62 */\r
+ _UDWORD TINT63:1; /* TINT63 */\r
+ } BIT; /* */\r
+} ICDxxx14; /* */\r
+typedef union { /* ICDxxx15 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT64:1; /* TINT64 */\r
+ _UDWORD TINT65:1; /* TINT65 */\r
+ _UDWORD TINT66:1; /* TINT66 */\r
+ _UDWORD TINT67:1; /* TINT67 */\r
+ _UDWORD TINT68:1; /* TINT68 */\r
+ _UDWORD TINT69:1; /* TINT69 */\r
+ _UDWORD TINT70:1; /* TINT70 */\r
+ _UDWORD TINT71:1; /* TINT71 */\r
+ _UDWORD TINT72:1; /* TINT72 */\r
+ _UDWORD TINT73:1; /* TINT73 */\r
+ _UDWORD TINT74:1; /* TINT74 */\r
+ _UDWORD TINT75:1; /* TINT75 */\r
+ _UDWORD TINT76:1; /* TINT76 */\r
+ _UDWORD TINT77:1; /* TINT77 */\r
+ _UDWORD TINT78:1; /* TINT78 */\r
+ _UDWORD TINT79:1; /* TINT79 */\r
+ _UDWORD TINT80:1; /* TINT80 */\r
+ _UDWORD TINT81:1; /* TINT81 */\r
+ _UDWORD TINT82:1; /* TINT82 */\r
+ _UDWORD TINT83:1; /* TINT83 */\r
+ _UDWORD TINT84:1; /* TINT84 */\r
+ _UDWORD TINT85:1; /* TINT85 */\r
+ _UDWORD TINT86:1; /* TINT86 */\r
+ _UDWORD TINT87:1; /* TINT87 */\r
+ _UDWORD TINT88:1; /* TINT88 */\r
+ _UDWORD TINT89:1; /* TINT89 */\r
+ _UDWORD TINT90:1; /* TINT90 */\r
+ _UDWORD TINT91:1; /* TINT91 */\r
+ _UDWORD TINT92:1; /* TINT92 */\r
+ _UDWORD TINT93:1; /* TINT93 */\r
+ _UDWORD TINT94:1; /* TINT94 */\r
+ _UDWORD TINT95:1; /* TINT95 */\r
+ } BIT; /* */\r
+} ICDxxx15; /* */\r
+typedef union { /* ICDxxx16 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT96:1; /* TINT96 */\r
+ _UDWORD TINT97:1; /* TINT97 */\r
+ _UDWORD TINT98:1; /* TINT98 */\r
+ _UDWORD TINT99:1; /* TINT99 */\r
+ _UDWORD TINT100:1; /* TINT100 */\r
+ _UDWORD TINT101:1; /* TINT101 */\r
+ _UDWORD TINT102:1; /* TINT102 */\r
+ _UDWORD TINT103:1; /* TINT103 */\r
+ _UDWORD TINT104:1; /* TINT104 */\r
+ _UDWORD TINT105:1; /* TINT105 */\r
+ _UDWORD TINT106:1; /* TINT106 */\r
+ _UDWORD TINT107:1; /* TINT107 */\r
+ _UDWORD TINT108:1; /* TINT108 */\r
+ _UDWORD TINT109:1; /* TINT109 */\r
+ _UDWORD TINT110:1; /* TINT110 */\r
+ _UDWORD TINT111:1; /* TINT111 */\r
+ _UDWORD TINT112:1; /* TINT112 */\r
+ _UDWORD TINT113:1; /* TINT113 */\r
+ _UDWORD TINT114:1; /* TINT114 */\r
+ _UDWORD TINT115:1; /* TINT115 */\r
+ _UDWORD TINT116:1; /* TINT116 */\r
+ _UDWORD TINT117:1; /* TINT117 */\r
+ _UDWORD TINT118:1; /* TINT118 */\r
+ _UDWORD TINT119:1; /* TINT119 */\r
+ _UDWORD TINT120:1; /* TINT120 */\r
+ _UDWORD TINT121:1; /* TINT121 */\r
+ _UDWORD TINT122:1; /* TINT122 */\r
+ _UDWORD TINT123:1; /* TINT123 */\r
+ _UDWORD TINT124:1; /* TINT124 */\r
+ _UDWORD TINT125:1; /* TINT125 */\r
+ _UDWORD TINT126:1; /* TINT126 */\r
+ _UDWORD TINT127:1; /* TINT127 */\r
+ } BIT; /* */\r
+} ICDxxx16; /* */\r
+typedef union { /* ICDxxx17 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT128:1; /* TINT128 */\r
+ _UDWORD TINT129:1; /* TINT129 */\r
+ _UDWORD TINT130:1; /* TINT130 */\r
+ _UDWORD TINT131:1; /* TINT131 */\r
+ _UDWORD TINT132:1; /* TINT132 */\r
+ _UDWORD TINT133:1; /* TINT133 */\r
+ _UDWORD TINT134:1; /* TINT134 */\r
+ _UDWORD TINT135:1; /* TINT135 */\r
+ _UDWORD TINT136:1; /* TINT136 */\r
+ _UDWORD TINT137:1; /* TINT137 */\r
+ _UDWORD TINT138:1; /* TINT138 */\r
+ _UDWORD TINT139:1; /* TINT139 */\r
+ _UDWORD TINT140:1; /* TINT140 */\r
+ _UDWORD TINT141:1; /* TINT141 */\r
+ _UDWORD TINT142:1; /* TINT142 */\r
+ _UDWORD TINT143:1; /* TINT143 */\r
+ _UDWORD TINT144:1; /* TINT144 */\r
+ _UDWORD TINT145:1; /* TINT145 */\r
+ _UDWORD TINT146:1; /* TINT146 */\r
+ _UDWORD TINT147:1; /* TINT147 */\r
+ _UDWORD TINT148:1; /* TINT148 */\r
+ _UDWORD TINT149:1; /* TINT149 */\r
+ _UDWORD TINT150:1; /* TINT150 */\r
+ _UDWORD TINT151:1; /* TINT151 */\r
+ _UDWORD TINT152:1; /* TINT152 */\r
+ _UDWORD TINT153:1; /* TINT153 */\r
+ _UDWORD TINT154:1; /* TINT154 */\r
+ _UDWORD TINT155:1; /* TINT155 */\r
+ _UDWORD TINT156:1; /* TINT156 */\r
+ _UDWORD TINT157:1; /* TINT157 */\r
+ _UDWORD TINT158:1; /* TINT158 */\r
+ _UDWORD TINT159:1; /* TINT159 */\r
+ } BIT; /* */\r
+} ICDxxx17; /* */\r
+typedef union { /* ICDxxx18 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT160:1; /* TINT160 */\r
+ _UDWORD TINT161:1; /* TINT161 */\r
+ _UDWORD TINT162:1; /* TINT162 */\r
+ _UDWORD :29; /* */\r
+ } BIT; /* */\r
+} ICDxxx18; /* */\r
+\r
+\r
+struct st_intc { /* struct INTC */\r
+ union { /* ICDDCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD Enable:1; /* Enable */\r
+ _UDWORD :31; /* */\r
+ } BIT; /* */\r
+ } ICDDCR; /* */\r
+ union { /* ICDICTR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ITLinesNumber:5; /* ITLinesNumber */\r
+ _UDWORD CPUNumber:3; /* CPUNumber */\r
+ _UDWORD :2; /* */\r
+ _UDWORD SecurityExtn:1; /* SecurityExtn */\r
+ _UDWORD LSPI:5; /* LSPI */\r
+ _UDWORD :16; /* */\r
+ } BIT; /* */\r
+ } ICDICTR; /* */\r
+ union { /* ICDIIDR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD Implementer:12; /* Implementer */\r
+ _UDWORD Revision:4; /* Revision */\r
+ _UDWORD Variant:4; /* Variant */\r
+ _UDWORD :4; /* */\r
+ _UDWORD ProductID:8; /* ProductID */\r
+ } BIT; /* */\r
+ } ICDIIDR; /* */\r
+ _UBYTE wk0[116]; /* */\r
+ union { /* ICDISR */\r
+ _UDWORD LONG[19]; /* Long Access */\r
+ struct { /* ICDISRn */\r
+ ICDxxx0 ICDISR0; /* ICDISR0 */\r
+ ICDxxx1 ICDISR1; /* ICDISR1 */\r
+ ICDxxx2 ICDISR2; /* ICDISR2 */\r
+ ICDxxx3 ICDISR3; /* ICDISR3 */\r
+ ICDxxx4 ICDISR4; /* ICDISR4 */\r
+ ICDxxx5 ICDISR5; /* ICDISR5 */\r
+ ICDxxx6 ICDISR6; /* ICDISR6 */\r
+ ICDxxx7 ICDISR7; /* ICDISR7 */\r
+ ICDxxx8 ICDISR8; /* ICDISR8 */\r
+ ICDxxx9 ICDISR9; /* ICDISR9 */\r
+ ICDxxx10 ICDISR10; /* ICDISR10 */\r
+ ICDxxx11 ICDISR11; /* ICDISR11 */\r
+ ICDxxx12 ICDISR12; /* ICDISR12 */\r
+ ICDxxx13 ICDISR13; /* ICDISR13 */\r
+ ICDxxx14 ICDISR14; /* ICDISR14 */\r
+ ICDxxx15 ICDISR15; /* ICDISR15 */\r
+ ICDxxx16 ICDISR16; /* ICDISR16 */\r
+ ICDxxx17 ICDISR17; /* ICDISR17 */\r
+ ICDxxx18 ICDISR18; /* ICDISR18 */\r
+ } n; /* */\r
+ } ICDISR; /* */\r
+ _UBYTE wk1[52]; /* */\r
+ union { /* ICDISER */\r
+ _UDWORD LONG[19]; /* Long Access */\r
+ struct { /* ICDISERn */\r
+ ICDxxx0 ICDISER0; /* ICDISER0 */\r
+ ICDxxx1 ICDISER1; /* ICDISER1 */\r
+ ICDxxx2 ICDISER2; /* ICDISER2 */\r
+ ICDxxx3 ICDISER3; /* ICDISER3 */\r
+ ICDxxx4 ICDISER4; /* ICDISER4 */\r
+ ICDxxx5 ICDISER5; /* ICDISER5 */\r
+ ICDxxx6 ICDISER6; /* ICDISER6 */\r
+ ICDxxx7 ICDISER7; /* ICDISER7 */\r
+ ICDxxx8 ICDISER8; /* ICDISER8 */\r
+ ICDxxx9 ICDISER9; /* ICDISER9 */\r
+ ICDxxx10 ICDISER10; /* ICDISER10 */\r
+ ICDxxx11 ICDISER11; /* ICDISER11 */\r
+ ICDxxx12 ICDISER12; /* ICDISER12 */\r
+ ICDxxx13 ICDISER13; /* ICDISER13 */\r
+ ICDxxx14 ICDISER14; /* ICDISER14 */\r
+ ICDxxx15 ICDISER15; /* ICDISER15 */\r
+ ICDxxx16 ICDISER16; /* ICDISER16 */\r
+ ICDxxx17 ICDISER17; /* ICDISER17 */\r
+ ICDxxx18 ICDISER18; /* ICDISER18 */\r
+ } n; /* */\r
+ } ICDISER; /* */\r
+ _UBYTE wk2[52]; /* */\r
+ union { /* ICDICER */\r
+ _UDWORD LONG[19]; /* Long Access */\r
+ struct { /* ICDICERn */\r
+ ICDxxx0 ICDICER0; /* ICDICER0 */\r
+ ICDxxx1 ICDICER1; /* ICDICER1 */\r
+ ICDxxx2 ICDICER2; /* ICDICER2 */\r
+ ICDxxx3 ICDICER3; /* ICDICER3 */\r
+ ICDxxx4 ICDICER4; /* ICDICER4 */\r
+ ICDxxx5 ICDICER5; /* ICDICER5 */\r
+ ICDxxx6 ICDICER6; /* ICDICER6 */\r
+ ICDxxx7 ICDICER7; /* ICDICER7 */\r
+ ICDxxx8 ICDICER8; /* ICDICER8 */\r
+ ICDxxx9 ICDICER9; /* ICDICER9 */\r
+ ICDxxx10 ICDICER10; /* ICDICER10 */\r
+ ICDxxx11 ICDICER11; /* ICDICER11 */\r
+ ICDxxx12 ICDICER12; /* ICDICER12 */\r
+ ICDxxx13 ICDICER13; /* ICDICER13 */\r
+ ICDxxx14 ICDICER14; /* ICDICER14 */\r
+ ICDxxx15 ICDICER15; /* ICDICER15 */\r
+ ICDxxx16 ICDICER16; /* ICDICER16 */\r
+ ICDxxx17 ICDICER17; /* ICDICER17 */\r
+ ICDxxx18 ICDICER18; /* ICDICER18 */\r
+ } n; /* */\r
+ } ICDICER; /* */\r
+ _UBYTE wk3[52]; /* */\r
+ union { /* ICDISPR */\r
+ _UDWORD LONG[19]; /* Long Access */\r
+ struct { /* ICDISPRn */\r
+ ICDxxx0 ICDISPR0; /* ICDISPR0 */\r
+ ICDxxx1 ICDISPR1; /* ICDISPR1 */\r
+ ICDxxx2 ICDISPR2; /* ICDISPR2 */\r
+ ICDxxx3 ICDISPR3; /* ICDISPR3 */\r
+ ICDxxx4 ICDISPR4; /* ICDISPR4 */\r
+ ICDxxx5 ICDISPR5; /* ICDISPR5 */\r
+ ICDxxx6 ICDISPR6; /* ICDISPR6 */\r
+ ICDxxx7 ICDISPR7; /* ICDISPR7 */\r
+ ICDxxx8 ICDISPR8; /* ICDISPR8 */\r
+ ICDxxx9 ICDISPR9; /* ICDISPR9 */\r
+ ICDxxx10 ICDISPR10; /* ICDISPR10 */\r
+ ICDxxx11 ICDISPR11; /* ICDISPR11 */\r
+ ICDxxx12 ICDISPR12; /* ICDISPR12 */\r
+ ICDxxx13 ICDISPR13; /* ICDISPR13 */\r
+ ICDxxx14 ICDISPR14; /* ICDISPR14 */\r
+ ICDxxx15 ICDISPR15; /* ICDISPR15 */\r
+ ICDxxx16 ICDISPR16; /* ICDISPR16 */\r
+ ICDxxx17 ICDISPR17; /* ICDISPR17 */\r
+ ICDxxx18 ICDISPR18; /* ICDISPR18 */\r
+ } n; /* */\r
+ } ICDISPR; /* */\r
+ _UBYTE wk4[52]; /* */\r
+ union { /* ICDICPR */\r
+ _UDWORD LONG[19]; /* Long Access */\r
+ struct { /* ICDICPRn */\r
+ ICDxxx0 ICDICPR0; /* ICDICPR0 */\r
+ ICDxxx1 ICDICPR1; /* ICDICPR1 */\r
+ ICDxxx2 ICDICPR2; /* ICDICPR2 */\r
+ ICDxxx3 ICDICPR3; /* ICDICPR3 */\r
+ ICDxxx4 ICDICPR4; /* ICDICPR4 */\r
+ ICDxxx5 ICDICPR5; /* ICDICPR5 */\r
+ ICDxxx6 ICDICPR6; /* ICDICPR6 */\r
+ ICDxxx7 ICDICPR7; /* ICDICPR7 */\r
+ ICDxxx8 ICDICPR8; /* ICDICPR8 */\r
+ ICDxxx9 ICDICPR9; /* ICDICPR9 */\r
+ ICDxxx10 ICDICPR10; /* ICDICPR10 */\r
+ ICDxxx11 ICDICPR11; /* ICDICPR11 */\r
+ ICDxxx12 ICDICPR12; /* ICDICPR12 */\r
+ ICDxxx13 ICDICPR13; /* ICDICPR13 */\r
+ ICDxxx14 ICDICPR14; /* ICDICPR14 */\r
+ ICDxxx15 ICDICPR15; /* ICDICPR15 */\r
+ ICDxxx16 ICDICPR16; /* ICDICPR16 */\r
+ ICDxxx17 ICDICPR17; /* ICDICPR17 */\r
+ ICDxxx18 ICDICPR18; /* ICDICPR18 */\r
+ } n; /* */\r
+ } ICDICPR; /* */\r
+ _UBYTE wk5[52]; /* */\r
+ union { /* ICDABR */\r
+ _UDWORD LONG[19]; /* Long Access */\r
+ struct { /* ICDABRn */\r
+ ICDxxx0 ICDABR0; /* ICDABR0 */\r
+ ICDxxx1 ICDABR1; /* ICDABR1 */\r
+ ICDxxx2 ICDABR2; /* ICDABR2 */\r
+ ICDxxx3 ICDABR3; /* ICDABR3 */\r
+ ICDxxx4 ICDABR4; /* ICDABR4 */\r
+ ICDxxx5 ICDABR5; /* ICDABR5 */\r
+ ICDxxx6 ICDABR6; /* ICDABR6 */\r
+ ICDxxx7 ICDABR7; /* ICDABR7 */\r
+ ICDxxx8 ICDABR8; /* ICDABR8 */\r
+ ICDxxx9 ICDABR9; /* ICDABR9 */\r
+ ICDxxx10 ICDABR10; /* ICDABR10 */\r
+ ICDxxx11 ICDABR11; /* ICDABR11 */\r
+ ICDxxx12 ICDABR12; /* ICDABR12 */\r
+ ICDxxx13 ICDABR13; /* ICDABR13 */\r
+ ICDxxx14 ICDABR14; /* ICDABR14 */\r
+ ICDxxx15 ICDABR15; /* ICDABR15 */\r
+ ICDxxx16 ICDABR16; /* ICDABR16 */\r
+ ICDxxx17 ICDABR17; /* ICDABR17 */\r
+ ICDxxx18 ICDABR18; /* ICDABR18 */\r
+ } n; /* */\r
+ } ICDABR; /* */\r
+ _UBYTE wk6[180]; /* */\r
+ union { /* ICDIPR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SW0:8; /* SW0 */\r
+ _UDWORD SW1:8; /* SW1 */\r
+ _UDWORD SW2:8; /* SW2 */\r
+ _UDWORD SW3:8; /* SW3 */\r
+ } BIT; /* */\r
+ } ICDIPR0; /* */\r
+ union { /* ICDIPR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SW4:8; /* SW4 */\r
+ _UDWORD SW5:8; /* SW5 */\r
+ _UDWORD SW6:8; /* SW6 */\r
+ _UDWORD SW7:8; /* SW7 */\r
+ } BIT; /* */\r
+ } ICDIPR1; /* */\r
+ union { /* ICDIPR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SW8:8; /* SW8 */\r
+ _UDWORD SW9:8; /* SW9 */\r
+ _UDWORD SW10:8; /* SW10 */\r
+ _UDWORD SW11:8; /* SW11 */\r
+ } BIT; /* */\r
+ } ICDIPR2; /* */\r
+ union { /* ICDIPR3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SW12:8; /* SW12 */\r
+ _UDWORD SW13:8; /* SW13 */\r
+ _UDWORD SW14:8; /* SW14 */\r
+ _UDWORD SW15:8; /* SW15 */\r
+ } BIT; /* */\r
+ } ICDIPR3; /* */\r
+ union { /* ICDIPR4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD PMUIRQ0:8; /* PMUIRQ0 */\r
+ _UDWORD COMMRX0:8; /* COMMRX0 */\r
+ _UDWORD COMMTX0:8; /* COMMTX0 */\r
+ _UDWORD CTIIRQ0:8; /* CTIIRQ0 */\r
+ } BIT; /* */\r
+ } ICDIPR4; /* */\r
+ _UBYTE wk7[12]; /* */\r
+ union { /* ICDIPR8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IRQ0:8; /* IRQ0 */\r
+ _UDWORD IRQ1:8; /* IRQ1 */\r
+ _UDWORD IRQ2:8; /* IRQ2 */\r
+ _UDWORD IRQ3:8; /* IRQ3 */\r
+ } BIT; /* */\r
+ } ICDIPR8; /* */\r
+ union { /* ICDIPR9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IRQ4:8; /* IRQ4 */\r
+ _UDWORD IRQ5:8; /* IRQ5 */\r
+ _UDWORD IRQ6:8; /* IRQ6 */\r
+ _UDWORD IRQ7:8; /* IRQ7 */\r
+ } BIT; /* */\r
+ } ICDIPR9; /* */\r
+ union { /* ICDIPR10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD PL310ERR:8; /* PL310ERR */\r
+ _UDWORD DMAINT0:8; /* DMAINT0 */\r
+ _UDWORD DMAINT1:8; /* DMAINT1 */\r
+ _UDWORD DMAINT2:8; /* DMAINT2 */\r
+ } BIT; /* */\r
+ } ICDIPR10; /* */\r
+ union { /* ICDIPR11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DMAINT3:8; /* DMAINT3 */\r
+ _UDWORD DMAINT4:8; /* DMAINT4 */\r
+ _UDWORD DMAINT5:8; /* DMAINT5 */\r
+ _UDWORD DMAINT6:8; /* DMAINT6 */\r
+ } BIT; /* */\r
+ } ICDIPR11; /* */\r
+ union { /* ICDIPR12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DMAINT7:8; /* DMAINT7 */\r
+ _UDWORD DMAINT8:8; /* DMAINT8 */\r
+ _UDWORD DMAINT9:8; /* DMAINT9 */\r
+ _UDWORD DMAINT10:8; /* DMAINT10 */\r
+ } BIT; /* */\r
+ } ICDIPR12; /* */\r
+ union { /* ICDIPR13 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DMAINT11:8; /* DMAINT11 */\r
+ _UDWORD DMAINT12:8; /* DMAINT12 */\r
+ _UDWORD DMAINT13:8; /* DMAINT13 */\r
+ _UDWORD DMAINT14:8; /* DMAINT14 */\r
+ } BIT; /* */\r
+ } ICDIPR13; /* */\r
+ union { /* ICDIPR14 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DMAINT15:8; /* DMAINT15 */\r
+ _UDWORD DMAERR:8; /* DMAERR */\r
+ _UDWORD :16; /* */\r
+ } BIT; /* */\r
+ } ICDIPR14; /* */\r
+ _UBYTE wk8[12]; /* */\r
+ union { /* ICDIPR18 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :8; /* */\r
+ _UDWORD USBI0:8; /* USBI0 */\r
+ _UDWORD USBI1:8; /* USBI1 */\r
+ _UDWORD S0_VI_VSYNC0:8; /* S0_VI_VSYNC0 */\r
+ } BIT; /* */\r
+ } ICDIPR18; /* */\r
+ union { /* ICDIPR19 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD S0_LO_VSYNC0:8; /* S0_LO_VSYNC0 */\r
+ _UDWORD S0_VSYNCERR0:8; /* S0_VSYNCERR0 */\r
+ _UDWORD GR3_VLINE0:8; /* GR3_VLINE0 */\r
+ _UDWORD S0_VFIELD0:8; /* S0_VFIELD0 */\r
+ } BIT; /* */\r
+ } ICDIPR19; /* */\r
+ union { /* ICDIPR20 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IV1_VBUFERR0:8; /* IV1_VBUFERR0 */\r
+ _UDWORD IV3_VBUFERR0:8; /* IV3_VBUFERR0 */\r
+ _UDWORD IV5_VBUFERR0:8; /* IV5_VBUFERR0 */\r
+ _UDWORD IV6_VBUFERR0:8; /* IV6_VBUFERR0 */\r
+ } BIT; /* */\r
+ } ICDIPR20; /* */\r
+ union { /* ICDIPR21 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD S0_WLINE0:8; /* S0_WLINE0 */\r
+ _UDWORD S1_VI_VSYNC0:8; /* S1_VI_VSYNC0 */\r
+ _UDWORD S1_LO_VSYNC0:8; /* S1_LO_VSYNC0 */\r
+ _UDWORD S1_VSYNCERR0:8; /* S1_VSYNCERR0 */\r
+ } BIT; /* */\r
+ } ICDIPR21; /* */\r
+ union { /* ICDIPR22 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD S1_VFIELD0:8; /* S1_VFIELD0 */\r
+ _UDWORD IV2_VBUFERR0:8; /* IV2_VBUFERR0 */\r
+ _UDWORD IV4_VBUFERR0:8; /* IV4_VBUFERR0 */\r
+ _UDWORD S1_WLINE0:8; /* S1_WLINE0 */\r
+ } BIT; /* */\r
+ } ICDIPR22; /* */\r
+ union { /* ICDIPR23 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD OIR_VI_VSYNC0:8; /* OIR_VI_VSYNC0 */\r
+ _UDWORD OIR_LO_VSYNC0:8; /* OIR_LO_VSYNC0 */\r
+ _UDWORD OIR_VSYNCERR0:8; /* OIR_VSYNCERR0 */\r
+ _UDWORD OIR_VFIELD0:8; /* OIR_VFIELD0 */\r
+ } BIT; /* */\r
+ } ICDIPR23; /* */\r
+ union { /* ICDIPR24 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IV7_VBUFERR0:8; /* IV7_VBUFERR0 */\r
+ _UDWORD IV8_VBUFERR0:8; /* IV8_VBUFERR0 */\r
+ _UDWORD OIR_WLINE0:8; /* OIR_WLINE0 */\r
+ _UDWORD S0_VI_VSYNC1:8; /* S0_VI_VSYNC1 */\r
+ } BIT; /* */\r
+ } ICDIPR24; /* */\r
+ union { /* ICDIPR25 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD S0_LO_VSYNC1:8; /* S0_LO_VSYNC1 */\r
+ _UDWORD S0_VSYNCERR1:8; /* S0_VSYNCERR1 */\r
+ _UDWORD GR3_VLINE1:8; /* GR3_VLINE1 */\r
+ _UDWORD S0_VFIELD1:8; /* S0_VFIELD1 */\r
+ } BIT; /* */\r
+ } ICDIPR25; /* */\r
+ union { /* ICDIPR26 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IV1_VBUFERR1:8; /* IV1_VBUFERR1 */\r
+ _UDWORD IV3_VBUFERR1:8; /* IV3_VBUFERR1 */\r
+ _UDWORD IV5_VBUFERR1:8; /* IV5_VBUFERR1 */\r
+ _UDWORD IV6_VBUFERR1:8; /* IV6_VBUFERR1 */\r
+ } BIT; /* */\r
+ } ICDIPR26; /* */\r
+ union { /* ICDIPR27 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD S0_WLINE1:8; /* S0_WLINE1 */\r
+ _UDWORD S1_VI_VSYNC1:8; /* S1_VI_VSYNC1 */\r
+ _UDWORD S1_LO_VSYNC1:8; /* S1_LO_VSYNC1 */\r
+ _UDWORD S1_VSYNCERR1:8; /* S1_VSYNCERR1 */\r
+ } BIT; /* */\r
+ } ICDIPR27; /* */\r
+ union { /* ICDIPR28 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD S1_VFIELD1:8; /* S1_VFIELD1 */\r
+ _UDWORD IV2_VBUFERR1:8; /* IV2_VBUFERR1 */\r
+ _UDWORD IV4_VBUFERR1:8; /* IV4_VBUFERR1 */\r
+ _UDWORD S1_WLINE1:8; /* S1_WLINE1 */\r
+ } BIT; /* */\r
+ } ICDIPR28; /* */\r
+ union { /* ICDIPR29 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD OIR_VI_VSYNC1:8; /* OIR_VI_VSYNC1 */\r
+ _UDWORD OIR_LO_VSYNC1:8; /* OIR_LO_VSYNC1 */\r
+ _UDWORD OIR_VLINE1:8; /* OIR_VLINE1 */\r
+ _UDWORD OIR_VFIELD1:8; /* OIR_VFIELD1 */\r
+ } BIT; /* */\r
+ } ICDIPR29; /* */\r
+ union { /* ICDIPR30 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IV7_VBUFERR1:8; /* IV7_VBUFERR1 */\r
+ _UDWORD IV8_VBUFERR1:8; /* IV8_VBUFERR1 */\r
+ _UDWORD OIR_WLINE1:8; /* OIR_WLINE1 */\r
+ _UDWORD IMRDI:8; /* IMRDI */\r
+ } BIT; /* */\r
+ } ICDIPR30; /* */\r
+ union { /* ICDIPR31 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IMR2I0:8; /* IMR2I0 */\r
+ _UDWORD IMR2I1:8; /* IMR2I1 */\r
+ _UDWORD JEDI:8; /* JEDI */\r
+ _UDWORD JDTI:8; /* JDTI */\r
+ } BIT; /* */\r
+ } ICDIPR31; /* */\r
+ union { /* ICDIPR32 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CMP0:8; /* CMP0 */\r
+ _UDWORD CMP1:8; /* CMP1 */\r
+ _UDWORD INT0:8; /* INT0 */\r
+ _UDWORD INT1:8; /* INT1 */\r
+ } BIT; /* */\r
+ } ICDIPR32; /* */\r
+ union { /* ICDIPR33 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD INT2:8; /* INT2 */\r
+ _UDWORD INT3:8; /* INT3 */\r
+ _UDWORD OSTMI0:8; /* OSTMI0 */\r
+ _UDWORD OSTMI1:8; /* OSTMI1 */\r
+ } BIT; /* */\r
+ } ICDIPR33; /* */\r
+ union { /* ICDIPR34 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CMI:8; /* CMI */\r
+ _UDWORD WTOUT:8; /* WTOUT */\r
+ _UDWORD ITI:8; /* ITI */\r
+ _UDWORD TGI0A:8; /* TGI0A */\r
+ } BIT; /* */\r
+ } ICDIPR34; /* */\r
+ union { /* ICDIPR35 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TGI0B:8; /* TGI0B */\r
+ _UDWORD TGI0C:8; /* TGI0C */\r
+ _UDWORD TGI0D:8; /* TGI0D */\r
+ _UDWORD TGI0V:8; /* TGI0V */\r
+ } BIT; /* */\r
+ } ICDIPR35; /* */\r
+ union { /* ICDIPR36 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TGI0E:8; /* TGI0E */\r
+ _UDWORD TGI0F:8; /* TGI0F */\r
+ _UDWORD TGI1A:8; /* TGI1A */\r
+ _UDWORD TGI1B:8; /* TGI1B */\r
+ } BIT; /* */\r
+ } ICDIPR36; /* */\r
+ union { /* ICDIPR37 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TGI1V:8; /* TGI1V */\r
+ _UDWORD TGI1U:8; /* TGI1U */\r
+ _UDWORD TGI2A:8; /* TGI2A */\r
+ _UDWORD TGI2B:8; /* TGI2B */\r
+ } BIT; /* */\r
+ } ICDIPR37; /* */\r
+ union { /* ICDIPR38 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TGI2V:8; /* TGI2V */\r
+ _UDWORD TGI2U:8; /* TGI2U */\r
+ _UDWORD TGI3A:8; /* TGI3A */\r
+ _UDWORD TGI3B:8; /* TGI3B */\r
+ } BIT; /* */\r
+ } ICDIPR38; /* */\r
+ union { /* ICDIPR39 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TGI3C:8; /* TGI3C */\r
+ _UDWORD TGI3D:8; /* TGI3D */\r
+ _UDWORD TGI3V:8; /* TGI3V */\r
+ _UDWORD TGI4A:8; /* TGI4A */\r
+ } BIT; /* */\r
+ } ICDIPR39; /* */\r
+ union { /* ICDIPR40 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TGI4B:8; /* TGI4B */\r
+ _UDWORD TGI4C:8; /* TGI4C */\r
+ _UDWORD TGI4D:8; /* TGI4D */\r
+ _UDWORD TGI4V:8; /* TGI4V */\r
+ } BIT; /* */\r
+ } ICDIPR40; /* */\r
+ union { /* ICDIPR41 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CMI1:8; /* CMI1 */\r
+ _UDWORD CMI2:8; /* CMI2 */\r
+ _UDWORD SGDEI0:8; /* SGDEI0 */\r
+ _UDWORD SGDEI1:8; /* SGDEI1 */\r
+ } BIT; /* */\r
+ } ICDIPR41; /* */\r
+ union { /* ICDIPR42 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SGDEI2:8; /* SGDEI2 */\r
+ _UDWORD SGDEI3:8; /* SGDEI3 */\r
+ _UDWORD ADI:8; /* ADI */\r
+ _UDWORD ADWAR:8; /* ADWAR */\r
+ } BIT; /* */\r
+ } ICDIPR42; /* */\r
+ union { /* ICDIPR43 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SSII0:8; /* SSII0 */\r
+ _UDWORD SSIRXI0:8; /* SSIRXI0 */\r
+ _UDWORD SSITXI0:8; /* SSITXI0 */\r
+ _UDWORD SSII1:8; /* SSII1 */\r
+ } BIT; /* */\r
+ } ICDIPR43; /* */\r
+ union { /* ICDIPR44 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SSIRXI1:8; /* SSIRXI1 */\r
+ _UDWORD SSITXI1:8; /* SSITXI1 */\r
+ _UDWORD SSII2:8; /* SSII2 */\r
+ _UDWORD SSIRTI2:8; /* SSIRTI2 */\r
+ } BIT; /* */\r
+ } ICDIPR44; /* */\r
+ union { /* ICDIPR45 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SSII3:8; /* SSII3 */\r
+ _UDWORD SSIRXI3:8; /* SSIRXI3 */\r
+ _UDWORD SSITXI3:8; /* SSITXI3 */\r
+ _UDWORD SSII4:8; /* SSII4 */\r
+ } BIT; /* */\r
+ } ICDIPR45; /* */\r
+ union { /* ICDIPR46 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SSIRTI4:8; /* SSIRTI4 */\r
+ _UDWORD SSII5:8; /* SSII5 */\r
+ _UDWORD SSIRXI5:8; /* SSIRXI5 */\r
+ _UDWORD SSITXI5:8; /* SSITXI5 */\r
+ } BIT; /* */\r
+ } ICDIPR46; /* */\r
+ union { /* ICDIPR47 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPDIFI:8; /* SPDIFI */\r
+ _UDWORD TEI0:8; /* TEI0 */\r
+ _UDWORD RI0:8; /* RI0 */\r
+ _UDWORD TI0:8; /* TI0 */\r
+ } BIT; /* */\r
+ } ICDIPR47; /* */\r
+ union { /* ICDIPR48 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPI0:8; /* SPI0 */\r
+ _UDWORD STI0:8; /* STI0 */\r
+ _UDWORD NAKI0:8; /* NAKI0 */\r
+ _UDWORD ALI0:8; /* ALI0 */\r
+ } BIT; /* */\r
+ } ICDIPR48; /* */\r
+ union { /* ICDIPR49 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TMOI0:8; /* TMOI0 */\r
+ _UDWORD TEI1:8; /* TEI1 */\r
+ _UDWORD RI1:8; /* RI1 */\r
+ _UDWORD TI1:8; /* TI1 */\r
+ } BIT; /* */\r
+ } ICDIPR49; /* */\r
+ union { /* ICDIPR50 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPI1:8; /* SPI1 */\r
+ _UDWORD STI1:8; /* STI1 */\r
+ _UDWORD NAKI1:8; /* NAKI1 */\r
+ _UDWORD ALI1:8; /* ALI1 */\r
+ } BIT; /* */\r
+ } ICDIPR50; /* */\r
+ union { /* ICDIPR51 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TMOI1:8; /* TMOI1 */\r
+ _UDWORD TEI2:8; /* TEI2 */\r
+ _UDWORD RI2:8; /* RI2 */\r
+ _UDWORD TI2:8; /* TI2 */\r
+ } BIT; /* */\r
+ } ICDIPR51; /* */\r
+ union { /* ICDIPR52 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPI2:8; /* SPI2 */\r
+ _UDWORD STI2:8; /* STI2 */\r
+ _UDWORD NAKI2:8; /* NAKI2 */\r
+ _UDWORD ALI2:8; /* ALI2 */\r
+ } BIT; /* */\r
+ } ICDIPR52; /* */\r
+ union { /* ICDIPR53 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TMOI2:8; /* TMOI2 */\r
+ _UDWORD TEI3:8; /* TEI3 */\r
+ _UDWORD RI3:8; /* RI3 */\r
+ _UDWORD TI3:8; /* TI3 */\r
+ } BIT; /* */\r
+ } ICDIPR53; /* */\r
+ union { /* ICDIPR54 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPI3:8; /* SPI3 */\r
+ _UDWORD STI3:8; /* STI3 */\r
+ _UDWORD NAKI3:8; /* NAKI3 */\r
+ _UDWORD ALI3:8; /* ALI3 */\r
+ } BIT; /* */\r
+ } ICDIPR54; /* */\r
+ union { /* ICDIPR55 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TMOI3:8; /* TMOI3 */\r
+ _UDWORD BRI0:8; /* BRI0 */\r
+ _UDWORD ERI0:8; /* ERI0 */\r
+ _UDWORD RXI0:8; /* RXI0 */\r
+ } BIT; /* */\r
+ } ICDIPR55; /* */\r
+ union { /* ICDIPR56 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI0:8; /* TXI0 */\r
+ _UDWORD BRI1:8; /* BRI1 */\r
+ _UDWORD ERI1:8; /* ERI1 */\r
+ _UDWORD RXI1:8; /* RXI1 */\r
+ } BIT; /* */\r
+ } ICDIPR56; /* */\r
+ union { /* ICDIPR57 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI1:8; /* TXI1 */\r
+ _UDWORD BRI2:8; /* BRI2 */\r
+ _UDWORD ERI2:8; /* ERI2 */\r
+ _UDWORD RXI2:8; /* RXI2 */\r
+ } BIT; /* */\r
+ } ICDIPR57; /* */\r
+ union { /* ICDIPR58 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI2:8; /* TXI2 */\r
+ _UDWORD BRI3:8; /* BRI3 */\r
+ _UDWORD ERI3:8; /* ERI3 */\r
+ _UDWORD RXI3:8; /* RXI3 */\r
+ } BIT; /* */\r
+ } ICDIPR58; /* */\r
+ union { /* ICDIPR59 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI3:8; /* TXI3 */\r
+ _UDWORD BRI4:8; /* BRI4 */\r
+ _UDWORD ERI4:8; /* ERI4 */\r
+ _UDWORD RXI4:8; /* RXI4 */\r
+ } BIT; /* */\r
+ } ICDIPR59; /* */\r
+ union { /* ICDIPR60 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI4:8; /* TXI4 */\r
+ _UDWORD BRI5:8; /* BRI5 */\r
+ _UDWORD ERI5:8; /* ERI5 */\r
+ _UDWORD RXI5:8; /* RXI5 */\r
+ } BIT; /* */\r
+ } ICDIPR60; /* */\r
+ union { /* ICDIPR61 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI5:8; /* TXI5 */\r
+ _UDWORD BRI6:8; /* BRI6 */\r
+ _UDWORD ERI6:8; /* ERI6 */\r
+ _UDWORD RXI6:8; /* RXI6 */\r
+ } BIT; /* */\r
+ } ICDIPR61; /* */\r
+ union { /* ICDIPR62 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI6:8; /* TXI6 */\r
+ _UDWORD BRI7:8; /* BRI7 */\r
+ _UDWORD ERI7:8; /* ERI7 */\r
+ _UDWORD RXI7:8; /* RXI7 */\r
+ } BIT; /* */\r
+ } ICDIPR62; /* */\r
+ union { /* ICDIPR63 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI7:8; /* TXI7 */\r
+ _UDWORD GERI:8; /* GERI */\r
+ _UDWORD RFI:8; /* RFI */\r
+ _UDWORD CFRXI0:8; /* CFRXI0 */\r
+ } BIT; /* */\r
+ } ICDIPR63; /* */\r
+ union { /* ICDIPR64 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CERI0:8; /* CERI0 */\r
+ _UDWORD CTXI0:8; /* CTXI0 */\r
+ _UDWORD CFRXI1:8; /* CFRXI1 */\r
+ _UDWORD CERI1:8; /* CERI1 */\r
+ } BIT; /* */\r
+ } ICDIPR64; /* */\r
+ union { /* ICDIPR65 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CTXI1:8; /* CTXI1 */\r
+ _UDWORD CFRXI2:8; /* CFRXI2 */\r
+ _UDWORD CERI2:8; /* CERI2 */\r
+ _UDWORD CTXI2:8; /* CTXI2 */\r
+ } BIT; /* */\r
+ } ICDIPR65; /* */\r
+ union { /* ICDIPR66 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CFRXI3:8; /* CFRXI3 */\r
+ _UDWORD CERI3:8; /* CERI3 */\r
+ _UDWORD CTXI3:8; /* CTXI3 */\r
+ _UDWORD CFRXI4:8; /* CFRXI4 */\r
+ } BIT; /* */\r
+ } ICDIPR66; /* */\r
+ union { /* ICDIPR67 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CERI4:8; /* CERI4 */\r
+ _UDWORD CTXI4:8; /* CTXI4 */\r
+ _UDWORD SPEI0:8; /* SPEI0 */\r
+ _UDWORD SPRI0:8; /* SPRI0 */\r
+ } BIT; /* */\r
+ } ICDIPR67; /* */\r
+ union { /* ICDIPR68 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPTI0:8; /* SPTI0 */\r
+ _UDWORD SPEI1:8; /* SPEI1 */\r
+ _UDWORD SPRI1:8; /* SPRI1 */\r
+ _UDWORD SPTI1:8; /* SPTI1 */\r
+ } BIT; /* */\r
+ } ICDIPR68; /* */\r
+ union { /* ICDIPR69 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPEI2:8; /* SPEI2 */\r
+ _UDWORD SPRI2:8; /* SPRI2 */\r
+ _UDWORD SPTI2:8; /* SPTI2 */\r
+ _UDWORD SPEI3:8; /* SPEI3 */\r
+ } BIT; /* */\r
+ } ICDIPR69; /* */\r
+ union { /* ICDIPR70 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPRI3:8; /* SPRI3 */\r
+ _UDWORD SPTI3:8; /* SPTI3 */\r
+ _UDWORD SPEI4:8; /* SPEI4 */\r
+ _UDWORD SPRI4:8; /* SPRI4 */\r
+ } BIT; /* */\r
+ } ICDIPR70; /* */\r
+ union { /* ICDIPR71 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPTI4:8; /* SPTI4 */\r
+ _UDWORD IEBBTD:8; /* IEBBTD */\r
+ _UDWORD IEBBTERR:8; /* IEBBTERR */\r
+ _UDWORD IEBBTSTA:8; /* IEBBTSTA */\r
+ } BIT; /* */\r
+ } ICDIPR71; /* */\r
+ union { /* ICDIPR72 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IEBBTV:8; /* IEBBTV */\r
+ _UDWORD ISY:8; /* ISY */\r
+ _UDWORD IERR:8; /* IERR */\r
+ _UDWORD ITARG:8; /* ITARG */\r
+ } BIT; /* */\r
+ } ICDIPR72; /* */\r
+ union { /* ICDIPR73 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ISEC:8; /* ISEC */\r
+ _UDWORD IBUF:8; /* IBUF */\r
+ _UDWORD IREADY:8; /* IREADY */\r
+ _UDWORD FLSTE:8; /* FLSTE */\r
+ } BIT; /* */\r
+ } ICDIPR73; /* */\r
+ union { /* ICDIPR74 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FLTENDI:8; /* FLTENDI */\r
+ _UDWORD FLTREQ0I:8; /* FLTREQ0I */\r
+ _UDWORD FLTREQ1I:8; /* FLTREQ1I */\r
+ _UDWORD MMC0:8; /* MMC0 */\r
+ } BIT; /* */\r
+ } ICDIPR74; /* */\r
+ union { /* ICDIPR75 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD MMC1:8; /* MMC1 */\r
+ _UDWORD MMC2:8; /* MMC2 */\r
+ _UDWORD SDHI0_3:8; /* SDHI0_3 */\r
+ _UDWORD SDHI0_0:8; /* SDHI0_0 */\r
+ } BIT; /* */\r
+ } ICDIPR75; /* */\r
+ union { /* ICDIPR76 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SDHI0_1:8; /* SDHI0_1 */\r
+ _UDWORD SDHI1_3:8; /* SDHI1_3 */\r
+ _UDWORD SDHI1_0:8; /* SDHI1_0 */\r
+ _UDWORD SDHI1_1:8; /* SDHI1_1 */\r
+ } BIT; /* */\r
+ } ICDIPR76; /* */\r
+ union { /* ICDIPR77 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ARM:8; /* ARM */\r
+ _UDWORD PRD:8; /* PRD */\r
+ _UDWORD CUP:8; /* CUP */\r
+ _UDWORD SCUAI0:8; /* SCUAI0 */\r
+ } BIT; /* */\r
+ } ICDIPR77; /* */\r
+ union { /* ICDIPR78 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SCUAI1:8; /* SCUAI1 */\r
+ _UDWORD SCUFDI0:8; /* SCUFDI0 */\r
+ _UDWORD SCUFDI1:8; /* SCUFDI1 */\r
+ _UDWORD SCUFDI2:8; /* SCUFDI2 */\r
+ } BIT; /* */\r
+ } ICDIPR78; /* */\r
+ union { /* ICDIPR79 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SCUFDI3:8; /* SCUFDI3 */\r
+ _UDWORD SCUFUI0:8; /* SCUFUI0 */\r
+ _UDWORD SCUFUI1:8; /* SCUFUI1 */\r
+ _UDWORD SCUFUI2:8; /* SCUFUI2 */\r
+ } BIT; /* */\r
+ } ICDIPR79; /* */\r
+ union { /* ICDIPR80 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SCUFUI3:8; /* SCUFUI3 */\r
+ _UDWORD SCUDVI0:8; /* SCUDVI0 */\r
+ _UDWORD SCUDVI1:8; /* SCUDVI1 */\r
+ _UDWORD SCUDVI2:8; /* SCUDVI2 */\r
+ } BIT; /* */\r
+ } ICDIPR80; /* */\r
+ union { /* ICDIPR81 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SCUDVI3:8; /* SCUDVI3 */\r
+ _UDWORD MLBCI:8; /* MLBCI */\r
+ _UDWORD MLBSI:8; /* MLBSI */\r
+ _UDWORD DRC0:8; /* DRC0 */\r
+ } BIT; /* */\r
+ } ICDIPR81; /* */\r
+ union { /* ICDIPR82 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DRC1:8; /* DRC1 */\r
+ _UDWORD :16; /* */\r
+ _UDWORD LINI0_INT_T:8; /* LINI0_INT_T */\r
+ } BIT; /* */\r
+ } ICDIPR82; /* */\r
+ union { /* ICDIPR83 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD LINI0_INT_R:8; /* LINI0_INT_R */\r
+ _UDWORD LINI0_INT_S:8; /* LINI0_INT_S */\r
+ _UDWORD LINI0_INT_M:8; /* LINI0_INT_M */\r
+ _UDWORD LINI1_INT_T:8; /* LINI1_INT_T */\r
+ } BIT; /* */\r
+ } ICDIPR83; /* */\r
+ union { /* ICDIPR84 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD LINI1_INT_R:8; /* LINI1_INT_R */\r
+ _UDWORD LINI1_INT_S:8; /* LINI1_INT_S */\r
+ _UDWORD LINI1_INT_M:8; /* LINI1_INT_M */\r
+ _UDWORD :8; /* */\r
+ } BIT; /* */\r
+ } ICDIPR84; /* */\r
+ _UBYTE wk9[4]; /* */\r
+ union { /* ICDIPR86 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :24; /* */\r
+ _UDWORD ERI0:8; /* ERI0 */\r
+ } BIT; /* */\r
+ } ICDIPR86; /* */\r
+ union { /* ICDIPR87 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD RXI0:8; /* RXI0 */\r
+ _UDWORD TXI0:8; /* TXI0 */\r
+ _UDWORD TEI0:8; /* TEI0 */\r
+ _UDWORD ERI1:8; /* ERI1 */\r
+ } BIT; /* */\r
+ } ICDIPR87; /* */\r
+ union { /* ICDIPR88 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD RXI1:8; /* RXI1 */\r
+ _UDWORD TXI1:8; /* TXI1 */\r
+ _UDWORD TEI1:8; /* TEI1 */\r
+ _UDWORD :8; /* */\r
+ } BIT; /* */\r
+ } ICDIPR88; /* */\r
+ union { /* ICDIPR89 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :24; /* */\r
+ _UDWORD ETHERI:8; /* ETHERI */\r
+ } BIT; /* */\r
+ } ICDIPR89; /* */\r
+ _UBYTE wk10[4]; /* */\r
+ union { /* ICDIPR91 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CEUI:8; /* CEUI */\r
+ _UDWORD INT_CSIH0TIR:8; /* INT_CSIH0TIR */\r
+ _UDWORD INT_CSIH0TIRE:8; /* INT_CSIH0TIRE */\r
+ _UDWORD INT_CSIH1TIC:8; /* INT_CSIH1TIC */\r
+ } BIT; /* */\r
+ } ICDIPR91; /* */\r
+ union { /* ICDIPR92 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD INT_CSIH1TIJC:8; /* INT_CSIH1TIJC */\r
+ _UDWORD ECCE10:8; /* ECCE10 */\r
+ _UDWORD ECCE20:8; /* ECCE20 */\r
+ _UDWORD ECCOVF0:8; /* ECCOVF0 */\r
+ } BIT; /* */\r
+ } ICDIPR92; /* */\r
+ union { /* ICDIPR93 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ECCE11:8; /* ECCE11 */\r
+ _UDWORD ECCE21:8; /* ECCE21 */\r
+ _UDWORD ECCOVF1:8; /* ECCOVF1 */\r
+ _UDWORD ECCE12:8; /* ECCE12 */\r
+ } BIT; /* */\r
+ } ICDIPR93; /* */\r
+ union { /* ICDIPR94 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ECCE22:8; /* ECCE22 */\r
+ _UDWORD ECCOVF2:8; /* ECCOVF2 */\r
+ _UDWORD ECCE13:8; /* ECCE13 */\r
+ _UDWORD ECCE23:8; /* ECCE23 */\r
+ } BIT; /* */\r
+ } ICDIPR94; /* */\r
+ union { /* ICDIPR95 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ECCOVF3:8; /* ECCOVF3 */\r
+ _UDWORD H2XMLB_ERRINT:8; /* H2XMLB_ERRINT */\r
+ _UDWORD H2XIC1_ERRINT:8; /* H2XIC1_ERRINT */\r
+ _UDWORD X2HPERI1_ERRINT:8; /* X2HPERI1_ERRINT */\r
+ } BIT; /* */\r
+ } ICDIPR95; /* */\r
+ union { /* ICDIPR96 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD X2HPERI2_ERRINT:8; /* X2HPERI2_ERRINT */\r
+ _UDWORD X2HPERI34_ERRINT:8; /* X2HPERI34_ERRINT */\r
+ _UDWORD X2HPERI5_ERRINT:8; /* X2HPERI5_ERRINT */\r
+ _UDWORD X2HPERI67_ERRINT:8; /* X2HPERI67_ERRINT */\r
+ } BIT; /* */\r
+ } ICDIPR96; /* */\r
+ union { /* ICDIPR97 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD X2HDBGR_ERRINT:8; /* X2HDBGR_ERRINT */\r
+ _UDWORD PRRI:8; /* PRRI */\r
+ _UDWORD IFEI0:8; /* IFEI0 */\r
+ _UDWORD OFFI0:8; /* OFFI0 */\r
+ } BIT; /* */\r
+ } ICDIPR97; /* */\r
+ union { /* ICDIPR98 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD PFVEI0:8; /* PFVEI0 */\r
+ _UDWORD IFEI1:8; /* IFEI1 */\r
+ _UDWORD OFFI1:8; /* OFFI1 */\r
+ _UDWORD PFVEI1:8; /* PFVEI1 */\r
+ } BIT; /* */\r
+ } ICDIPR98; /* */\r
+ _UBYTE wk11[20]; /* */\r
+ union { /* ICDIPR104 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT0:8; /* TINT0 */\r
+ _UDWORD TINT1:8; /* TINT1 */\r
+ _UDWORD TINT2:8; /* TINT2 */\r
+ _UDWORD TINT3:8; /* TINT3 */\r
+ } BIT; /* */\r
+ } ICDIPR104; /* */\r
+ union { /* ICDIPR105 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT4:8; /* TINT4 */\r
+ _UDWORD TINT5:8; /* TINT5 */\r
+ _UDWORD TINT6:8; /* TINT6 */\r
+ _UDWORD TINT7:8; /* TINT7 */\r
+ } BIT; /* */\r
+ } ICDIPR105; /* */\r
+ union { /* ICDIPR106 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT8:8; /* TINT8 */\r
+ _UDWORD TINT9:8; /* TINT9 */\r
+ _UDWORD TINT10:8; /* TINT10 */\r
+ _UDWORD TINT11:8; /* TINT11 */\r
+ } BIT; /* */\r
+ } ICDIPR106; /* */\r
+ union { /* ICDIPR107 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT12:8; /* TINT12 */\r
+ _UDWORD TINT13:8; /* TINT13 */\r
+ _UDWORD TINT14:8; /* TINT14 */\r
+ _UDWORD TINT15:8; /* TINT15 */\r
+ } BIT; /* */\r
+ } ICDIPR107; /* */\r
+ union { /* ICDIPR108 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT16:8; /* TINT16 */\r
+ _UDWORD TINT17:8; /* TINT17 */\r
+ _UDWORD TINT18:8; /* TINT18 */\r
+ _UDWORD TINT19:8; /* TINT19 */\r
+ } BIT; /* */\r
+ } ICDIPR108; /* */\r
+ union { /* ICDIPR109 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT20:8; /* TINT20 */\r
+ _UDWORD TINT21:8; /* TINT21 */\r
+ _UDWORD TINT22:8; /* TINT22 */\r
+ _UDWORD TINT23:8; /* TINT23 */\r
+ } BIT; /* */\r
+ } ICDIPR109; /* */\r
+ union { /* ICDIPR110 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT24:8; /* TINT24 */\r
+ _UDWORD TINT25:8; /* TINT25 */\r
+ _UDWORD TINT26:8; /* TINT26 */\r
+ _UDWORD TINT27:8; /* TINT27 */\r
+ } BIT; /* */\r
+ } ICDIPR110; /* */\r
+ union { /* ICDIPR111 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT28:8; /* TINT28 */\r
+ _UDWORD TINT29:8; /* TINT29 */\r
+ _UDWORD TINT30:8; /* TINT30 */\r
+ _UDWORD TINT31:8; /* TINT31 */\r
+ } BIT; /* */\r
+ } ICDIPR111; /* */\r
+ union { /* ICDIPR112 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT32:8; /* TINT32 */\r
+ _UDWORD TINT33:8; /* TINT33 */\r
+ _UDWORD TINT34:8; /* TINT34 */\r
+ _UDWORD TINT35:8; /* TINT35 */\r
+ } BIT; /* */\r
+ } ICDIPR112; /* */\r
+ union { /* ICDIPR113 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT36:8; /* TINT36 */\r
+ _UDWORD TINT37:8; /* TINT37 */\r
+ _UDWORD TINT38:8; /* TINT38 */\r
+ _UDWORD TINT39:8; /* TINT39 */\r
+ } BIT; /* */\r
+ } ICDIPR113; /* */\r
+ union { /* ICDIPR114 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT40:8; /* TINT40 */\r
+ _UDWORD TINT41:8; /* TINT41 */\r
+ _UDWORD TINT42:8; /* TINT42 */\r
+ _UDWORD TINT43:8; /* TINT43 */\r
+ } BIT; /* */\r
+ } ICDIPR114; /* */\r
+ union { /* ICDIPR115 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT44:8; /* TINT44 */\r
+ _UDWORD TINT45:8; /* TINT45 */\r
+ _UDWORD TINT46:8; /* TINT46 */\r
+ _UDWORD TINT47:8; /* TINT47 */\r
+ } BIT; /* */\r
+ } ICDIPR115; /* */\r
+ union { /* ICDIPR116 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT48:8; /* TINT48 */\r
+ _UDWORD TINT49:8; /* TINT49 */\r
+ _UDWORD TINT50:8; /* TINT50 */\r
+ _UDWORD TINT51:8; /* TINT51 */\r
+ } BIT; /* */\r
+ } ICDIPR116; /* */\r
+ union { /* ICDIPR117 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT52:8; /* TINT52 */\r
+ _UDWORD TINT53:8; /* TINT53 */\r
+ _UDWORD TINT54:8; /* TINT54 */\r
+ _UDWORD TINT55:8; /* TINT55 */\r
+ } BIT; /* */\r
+ } ICDIPR117; /* */\r
+ union { /* ICDIPR118 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT56:8; /* TINT56 */\r
+ _UDWORD TINT57:8; /* TINT57 */\r
+ _UDWORD TINT58:8; /* TINT58 */\r
+ _UDWORD TINT59:8; /* TINT59 */\r
+ } BIT; /* */\r
+ } ICDIPR118; /* */\r
+ union { /* ICDIPR119 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT60:8; /* TINT60 */\r
+ _UDWORD TINT61:8; /* TINT61 */\r
+ _UDWORD TINT62:8; /* TINT62 */\r
+ _UDWORD TINT63:8; /* TINT63 */\r
+ } BIT; /* */\r
+ } ICDIPR119; /* */\r
+ union { /* ICDIPR120 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT64:8; /* TINT64 */\r
+ _UDWORD TINT65:8; /* TINT65 */\r
+ _UDWORD TINT66:8; /* TINT66 */\r
+ _UDWORD TINT67:8; /* TINT67 */\r
+ } BIT; /* */\r
+ } ICDIPR120; /* */\r
+ union { /* ICDIPR121 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT68:8; /* TINT68 */\r
+ _UDWORD TINT69:8; /* TINT69 */\r
+ _UDWORD TINT70:8; /* TINT70 */\r
+ _UDWORD TINT71:8; /* TINT71 */\r
+ } BIT; /* */\r
+ } ICDIPR121; /* */\r
+ union { /* ICDIPR122 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT72:8; /* TINT72 */\r
+ _UDWORD TINT73:8; /* TINT73 */\r
+ _UDWORD TINT74:8; /* TINT74 */\r
+ _UDWORD TINT75:8; /* TINT75 */\r
+ } BIT; /* */\r
+ } ICDIPR122; /* */\r
+ union { /* ICDIPR123 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT76:8; /* TINT76 */\r
+ _UDWORD TINT77:8; /* TINT77 */\r
+ _UDWORD TINT78:8; /* TINT78 */\r
+ _UDWORD TINT79:8; /* TINT79 */\r
+ } BIT; /* */\r
+ } ICDIPR123; /* */\r
+ union { /* ICDIPR124 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT80:8; /* TINT80 */\r
+ _UDWORD TINT81:8; /* TINT81 */\r
+ _UDWORD TINT82:8; /* TINT82 */\r
+ _UDWORD TINT83:8; /* TINT83 */\r
+ } BIT; /* */\r
+ } ICDIPR124; /* */\r
+ union { /* ICDIPR125 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT84:8; /* TINT84 */\r
+ _UDWORD TINT85:8; /* TINT85 */\r
+ _UDWORD TINT86:8; /* TINT86 */\r
+ _UDWORD TINT87:8; /* TINT87 */\r
+ } BIT; /* */\r
+ } ICDIPR125; /* */\r
+ union { /* ICDIPR126 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT88:8; /* TINT88 */\r
+ _UDWORD TINT89:8; /* TINT89 */\r
+ _UDWORD TINT90:8; /* TINT90 */\r
+ _UDWORD TINT91:8; /* TINT91 */\r
+ } BIT; /* */\r
+ } ICDIPR126; /* */\r
+ union { /* ICDIPR127 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT92:8; /* TINT92 */\r
+ _UDWORD TINT93:8; /* TINT93 */\r
+ _UDWORD TINT94:8; /* TINT94 */\r
+ _UDWORD TINT95:8; /* TINT95 */\r
+ } BIT; /* */\r
+ } ICDIPR127; /* */\r
+ union { /* ICDIPR128 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT96:8; /* TINT96 */\r
+ _UDWORD TINT97:8; /* TINT97 */\r
+ _UDWORD TINT98:8; /* TINT98 */\r
+ _UDWORD TINT99:8; /* TINT99 */\r
+ } BIT; /* */\r
+ } ICDIPR128; /* */\r
+ union { /* ICDIPR129 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT100:8; /* TINT100 */\r
+ _UDWORD TINT101:8; /* TINT101 */\r
+ _UDWORD TINT102:8; /* TINT102 */\r
+ _UDWORD TINT103:8; /* TINT103 */\r
+ } BIT; /* */\r
+ } ICDIPR129; /* */\r
+ union { /* ICDIPR130 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT104:8; /* TINT104 */\r
+ _UDWORD TINT105:8; /* TINT105 */\r
+ _UDWORD TINT106:8; /* TINT106 */\r
+ _UDWORD TINT107:8; /* TINT107 */\r
+ } BIT; /* */\r
+ } ICDIPR130; /* */\r
+ union { /* ICDIPR131 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT108:8; /* TINT108 */\r
+ _UDWORD TINT109:8; /* TINT109 */\r
+ _UDWORD TINT110:8; /* TINT110 */\r
+ _UDWORD TINT111:8; /* TINT111 */\r
+ } BIT; /* */\r
+ } ICDIPR131; /* */\r
+ union { /* ICDIPR132 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT112:8; /* TINT112 */\r
+ _UDWORD TINT113:8; /* TINT113 */\r
+ _UDWORD TINT114:8; /* TINT114 */\r
+ _UDWORD TINT115:8; /* TINT115 */\r
+ } BIT; /* */\r
+ } ICDIPR132; /* */\r
+ union { /* ICDIPR133 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT116:8; /* TINT116 */\r
+ _UDWORD TINT117:8; /* TINT117 */\r
+ _UDWORD TINT118:8; /* TINT118 */\r
+ _UDWORD TINT119:8; /* TINT119 */\r
+ } BIT; /* */\r
+ } ICDIPR133; /* */\r
+ union { /* ICDIPR134 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT120:8; /* TINT120 */\r
+ _UDWORD TINT121:8; /* TINT121 */\r
+ _UDWORD TINT122:8; /* TINT122 */\r
+ _UDWORD TINT123:8; /* TINT123 */\r
+ } BIT; /* */\r
+ } ICDIPR134; /* */\r
+ union { /* ICDIPR135 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT124:8; /* TINT124 */\r
+ _UDWORD TINT125:8; /* TINT125 */\r
+ _UDWORD TINT126:8; /* TINT126 */\r
+ _UDWORD TINT127:8; /* TINT127 */\r
+ } BIT; /* */\r
+ } ICDIPR135; /* */\r
+ union { /* ICDIPR136 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT128:8; /* TINT128 */\r
+ _UDWORD TINT129:8; /* TINT129 */\r
+ _UDWORD TINT130:8; /* TINT130 */\r
+ _UDWORD TINT131:8; /* TINT131 */\r
+ } BIT; /* */\r
+ } ICDIPR136; /* */\r
+ union { /* ICDIPR137 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT132:8; /* TINT132 */\r
+ _UDWORD TINT133:8; /* TINT133 */\r
+ _UDWORD TINT134:8; /* TINT134 */\r
+ _UDWORD TINT135:8; /* TINT135 */\r
+ } BIT; /* */\r
+ } ICDIPR137; /* */\r
+ union { /* ICDIPR138 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT136:8; /* TINT136 */\r
+ _UDWORD TINT137:8; /* TINT137 */\r
+ _UDWORD TINT138:8; /* TINT138 */\r
+ _UDWORD TINT139:8; /* TINT139 */\r
+ } BIT; /* */\r
+ } ICDIPR138; /* */\r
+ union { /* ICDIPR139 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT140:8; /* TINT140 */\r
+ _UDWORD TINT141:8; /* TINT141 */\r
+ _UDWORD TINT142:8; /* TINT142 */\r
+ _UDWORD TINT143:8; /* TINT143 */\r
+ } BIT; /* */\r
+ } ICDIPR139; /* */\r
+ union { /* ICDIPR140 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT144:8; /* TINT144 */\r
+ _UDWORD TINT145:8; /* TINT145 */\r
+ _UDWORD TINT146:8; /* TINT146 */\r
+ _UDWORD TINT147:8; /* TINT147 */\r
+ } BIT; /* */\r
+ } ICDIPR140; /* */\r
+ union { /* ICDIPR141 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT148:8; /* TINT148 */\r
+ _UDWORD TINT149:8; /* TINT149 */\r
+ _UDWORD TINT150:8; /* TINT150 */\r
+ _UDWORD TINT151:8; /* TINT151 */\r
+ } BIT; /* */\r
+ } ICDIPR141; /* */\r
+ union { /* ICDIPR142 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT152:8; /* TINT152 */\r
+ _UDWORD TINT153:8; /* TINT153 */\r
+ _UDWORD TINT154:8; /* TINT154 */\r
+ _UDWORD TINT155:8; /* TINT155 */\r
+ } BIT; /* */\r
+ } ICDIPR142; /* */\r
+ union { /* ICDIPR143 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT156:8; /* TINT156 */\r
+ _UDWORD TINT157:8; /* TINT157 */\r
+ _UDWORD TINT158:8; /* TINT158 */\r
+ _UDWORD TINT159:8; /* TINT159 */\r
+ } BIT; /* */\r
+ } ICDIPR143; /* */\r
+ union { /* ICDIPR144 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT160:8; /* TINT160 */\r
+ _UDWORD TINT161:8; /* TINT161 */\r
+ _UDWORD TINT162:8; /* TINT162 */\r
+ _UDWORD :8; /* */\r
+ } BIT; /* */\r
+ } ICDIPR144; /* */\r
+ _UBYTE wk12[444]; /* */\r
+ union { /* ICDIPTR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SW0:8; /* SW0 */\r
+ _UDWORD SW1:8; /* SW1 */\r
+ _UDWORD SW2:8; /* SW2 */\r
+ _UDWORD SW3:8; /* SW3 */\r
+ } BIT; /* */\r
+ } ICDIPTR0; /* */\r
+ union { /* ICDIPTR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SW4:8; /* SW4 */\r
+ _UDWORD SW5:8; /* SW5 */\r
+ _UDWORD SW6:8; /* SW6 */\r
+ _UDWORD SW7:8; /* SW7 */\r
+ } BIT; /* */\r
+ } ICDIPTR1; /* */\r
+ union { /* ICDIPTR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SW8:8; /* SW8 */\r
+ _UDWORD SW9:8; /* SW9 */\r
+ _UDWORD SW10:8; /* SW10 */\r
+ _UDWORD SW11:8; /* SW11 */\r
+ } BIT; /* */\r
+ } ICDIPTR2; /* */\r
+ union { /* ICDIPTR3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SW12:8; /* SW12 */\r
+ _UDWORD SW13:8; /* SW13 */\r
+ _UDWORD SW14:8; /* SW14 */\r
+ _UDWORD SW15:8; /* SW15 */\r
+ } BIT; /* */\r
+ } ICDIPTR3; /* */\r
+ union { /* ICDIPTR4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD PMUIRQ0:8; /* PMUIRQ0 */\r
+ _UDWORD COMMRX0:8; /* COMMRX0 */\r
+ _UDWORD COMMTX0:8; /* COMMTX0 */\r
+ _UDWORD CTIIRQ0:8; /* CTIIRQ0 */\r
+ } BIT; /* */\r
+ } ICDIPTR4; /* */\r
+ _UBYTE wk13[12]; /* */\r
+ union { /* ICDIPTR8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IRQ0:8; /* IRQ0 */\r
+ _UDWORD IRQ1:8; /* IRQ1 */\r
+ _UDWORD IRQ2:8; /* IRQ2 */\r
+ _UDWORD IRQ3:8; /* IRQ3 */\r
+ } BIT; /* */\r
+ } ICDIPTR8; /* */\r
+ union { /* ICDIPTR9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IRQ4:8; /* IRQ4 */\r
+ _UDWORD IRQ5:8; /* IRQ5 */\r
+ _UDWORD IRQ6:8; /* IRQ6 */\r
+ _UDWORD IRQ7:8; /* IRQ7 */\r
+ } BIT; /* */\r
+ } ICDIPTR9; /* */\r
+ union { /* ICDIPTR10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD PL310ERR:8; /* PL310ERR */\r
+ _UDWORD DMAINT0:8; /* DMAINT0 */\r
+ _UDWORD DMAINT1:8; /* DMAINT1 */\r
+ _UDWORD DMAINT2:8; /* DMAINT2 */\r
+ } BIT; /* */\r
+ } ICDIPTR10; /* */\r
+ union { /* ICDIPTR11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DMAINT3:8; /* DMAINT3 */\r
+ _UDWORD DMAINT4:8; /* DMAINT4 */\r
+ _UDWORD DMAINT5:8; /* DMAINT5 */\r
+ _UDWORD DMAINT6:8; /* DMAINT6 */\r
+ } BIT; /* */\r
+ } ICDIPTR11; /* */\r
+ union { /* ICDIPTR12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DMAINT7:8; /* DMAINT7 */\r
+ _UDWORD DMAINT8:8; /* DMAINT8 */\r
+ _UDWORD DMAINT9:8; /* DMAINT9 */\r
+ _UDWORD DMAINT10:8; /* DMAINT10 */\r
+ } BIT; /* */\r
+ } ICDIPTR12; /* */\r
+ union { /* ICDIPTR13 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DMAINT11:8; /* DMAINT11 */\r
+ _UDWORD DMAINT12:8; /* DMAINT12 */\r
+ _UDWORD DMAINT13:8; /* DMAINT13 */\r
+ _UDWORD DMAINT14:8; /* DMAINT14 */\r
+ } BIT; /* */\r
+ } ICDIPTR13; /* */\r
+ union { /* ICDIPTR14 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DMAINT15:8; /* DMAINT15 */\r
+ _UDWORD DMAERR:8; /* DMAERR */\r
+ _UDWORD :16; /* */\r
+ } BIT; /* */\r
+ } ICDIPTR14; /* */\r
+ _UBYTE wk14[12]; /* */\r
+ union { /* ICDIPTR18 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :8; /* */\r
+ _UDWORD USBI0:8; /* USBI0 */\r
+ _UDWORD USBI1:8; /* USBI1 */\r
+ _UDWORD S0_VI_VSYNC0:8; /* S0_VI_VSYNC0 */\r
+ } BIT; /* */\r
+ } ICDIPTR18; /* */\r
+ union { /* ICDIPTR19 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD S0_LO_VSYNC0:8; /* S0_LO_VSYNC0 */\r
+ _UDWORD S0_VSYNCERR0:8; /* S0_VSYNCERR0 */\r
+ _UDWORD GR3_VLINE0:8; /* GR3_VLINE0 */\r
+ _UDWORD S0_VFIELD0:8; /* S0_VFIELD0 */\r
+ } BIT; /* */\r
+ } ICDIPTR19; /* */\r
+ union { /* ICDIPTR20 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IV1_VBUFERR0:8; /* IV1_VBUFERR0 */\r
+ _UDWORD IV3_VBUFERR0:8; /* IV3_VBUFERR0 */\r
+ _UDWORD IV5_VBUFERR0:8; /* IV5_VBUFERR0 */\r
+ _UDWORD IV6_VBUFERR0:8; /* IV6_VBUFERR0 */\r
+ } BIT; /* */\r
+ } ICDIPTR20; /* */\r
+ union { /* ICDIPTR21 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD S0_WLINE0:8; /* S0_WLINE0 */\r
+ _UDWORD S1_VI_VSYNC0:8; /* S1_VI_VSYNC0 */\r
+ _UDWORD S1_LO_VSYNC0:8; /* S1_LO_VSYNC0 */\r
+ _UDWORD S1_VSYNCERR0:8; /* S1_VSYNCERR0 */\r
+ } BIT; /* */\r
+ } ICDIPTR21; /* */\r
+ union { /* ICDIPTR22 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD S1_VFIELD0:8; /* S1_VFIELD0 */\r
+ _UDWORD IV2_VBUFERR0:8; /* IV2_VBUFERR0 */\r
+ _UDWORD IV4_VBUFERR0:8; /* IV4_VBUFERR0 */\r
+ _UDWORD S1_WLINE0:8; /* S1_WLINE0 */\r
+ } BIT; /* */\r
+ } ICDIPTR22; /* */\r
+ union { /* ICDIPTR23 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD OIR_VI_VSYNC0:8; /* OIR_VI_VSYNC0 */\r
+ _UDWORD OIR_LO_VSYNC0:8; /* OIR_LO_VSYNC0 */\r
+ _UDWORD OIR_VSYNCERR0:8; /* OIR_VSYNCERR0 */\r
+ _UDWORD OIR_VFIELD0:8; /* OIR_VFIELD0 */\r
+ } BIT; /* */\r
+ } ICDIPTR23; /* */\r
+ union { /* ICDIPTR24 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IV7_VBUFERR0:8; /* IV7_VBUFERR0 */\r
+ _UDWORD IV8_VBUFERR0:8; /* IV8_VBUFERR0 */\r
+ _UDWORD OIR_WLINE0:8; /* OIR_WLINE0 */\r
+ _UDWORD S0_VI_VSYNC1:8; /* S0_VI_VSYNC1 */\r
+ } BIT; /* */\r
+ } ICDIPTR24; /* */\r
+ union { /* ICDIPTR25 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD S0_LO_VSYNC1:8; /* S0_LO_VSYNC1 */\r
+ _UDWORD S0_VSYNCERR1:8; /* S0_VSYNCERR1 */\r
+ _UDWORD GR3_VLINE1:8; /* GR3_VLINE1 */\r
+ _UDWORD S0_VFIELD1:8; /* S0_VFIELD1 */\r
+ } BIT; /* */\r
+ } ICDIPTR25; /* */\r
+ union { /* ICDIPTR26 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IV1_VBUFERR1:8; /* IV1_VBUFERR1 */\r
+ _UDWORD IV3_VBUFERR1:8; /* IV3_VBUFERR1 */\r
+ _UDWORD IV5_VBUFERR1:8; /* IV5_VBUFERR1 */\r
+ _UDWORD IV6_VBUFERR1:8; /* IV6_VBUFERR1 */\r
+ } BIT; /* */\r
+ } ICDIPTR26; /* */\r
+ union { /* ICDIPTR27 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD S0_WLINE1:8; /* S0_WLINE1 */\r
+ _UDWORD S1_VI_VSYNC1:8; /* S1_VI_VSYNC1 */\r
+ _UDWORD S1_LO_VSYNC1:8; /* S1_LO_VSYNC1 */\r
+ _UDWORD S1_VSYNCERR1:8; /* S1_VSYNCERR1 */\r
+ } BIT; /* */\r
+ } ICDIPTR27; /* */\r
+ union { /* ICDIPTR28 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD S1_VFIELD1:8; /* S1_VFIELD1 */\r
+ _UDWORD IV2_VBUFERR1:8; /* IV2_VBUFERR1 */\r
+ _UDWORD IV4_VBUFERR1:8; /* IV4_VBUFERR1 */\r
+ _UDWORD S1_WLINE1:8; /* S1_WLINE1 */\r
+ } BIT; /* */\r
+ } ICDIPTR28; /* */\r
+ union { /* ICDIPTR29 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD OIR_VI_VSYNC1:8; /* OIR_VI_VSYNC1 */\r
+ _UDWORD OIR_LO_VSYNC1:8; /* OIR_LO_VSYNC1 */\r
+ _UDWORD OIR_VLINE1:8; /* OIR_VLINE1 */\r
+ _UDWORD OIR_VFIELD1:8; /* OIR_VFIELD1 */\r
+ } BIT; /* */\r
+ } ICDIPTR29; /* */\r
+ union { /* ICDIPTR30 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IV7_VBUFERR1:8; /* IV7_VBUFERR1 */\r
+ _UDWORD IV8_VBUFERR1:8; /* IV8_VBUFERR1 */\r
+ _UDWORD OIR_WLINE1:8; /* OIR_WLINE1 */\r
+ _UDWORD IMRDI:8; /* IMRDI */\r
+ } BIT; /* */\r
+ } ICDIPTR30; /* */\r
+ union { /* ICDIPTR31 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IMR2I0:8; /* IMR2I0 */\r
+ _UDWORD IMR2I1:8; /* IMR2I1 */\r
+ _UDWORD JEDI:8; /* JEDI */\r
+ _UDWORD JDTI:8; /* JDTI */\r
+ } BIT; /* */\r
+ } ICDIPTR31; /* */\r
+ union { /* ICDIPTR32 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CMP0:8; /* CMP0 */\r
+ _UDWORD CMP1:8; /* CMP1 */\r
+ _UDWORD INT0:8; /* INT0 */\r
+ _UDWORD INT1:8; /* INT1 */\r
+ } BIT; /* */\r
+ } ICDIPTR32; /* */\r
+ union { /* ICDIPTR33 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD INT2:8; /* INT2 */\r
+ _UDWORD INT3:8; /* INT3 */\r
+ _UDWORD OSTMI0:8; /* OSTMI0 */\r
+ _UDWORD OSTMI1:8; /* OSTMI1 */\r
+ } BIT; /* */\r
+ } ICDIPTR33; /* */\r
+ union { /* ICDIPTR34 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CMI:8; /* CMI */\r
+ _UDWORD WTOUT:8; /* WTOUT */\r
+ _UDWORD ITI:8; /* ITI */\r
+ _UDWORD TGI0A:8; /* TGI0A */\r
+ } BIT; /* */\r
+ } ICDIPTR34; /* */\r
+ union { /* ICDIPTR35 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TGI0B:8; /* TGI0B */\r
+ _UDWORD TGI0C:8; /* TGI0C */\r
+ _UDWORD TGI0D:8; /* TGI0D */\r
+ _UDWORD TGI0V:8; /* TGI0V */\r
+ } BIT; /* */\r
+ } ICDIPTR35; /* */\r
+ union { /* ICDIPTR36 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TGI0E:8; /* TGI0E */\r
+ _UDWORD TGI0F:8; /* TGI0F */\r
+ _UDWORD TGI1A:8; /* TGI1A */\r
+ _UDWORD TGI1B:8; /* TGI1B */\r
+ } BIT; /* */\r
+ } ICDIPTR36; /* */\r
+ union { /* ICDIPTR37 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TGI1V:8; /* TGI1V */\r
+ _UDWORD TGI1U:8; /* TGI1U */\r
+ _UDWORD TGI2A:8; /* TGI2A */\r
+ _UDWORD TGI2B:8; /* TGI2B */\r
+ } BIT; /* */\r
+ } ICDIPTR37; /* */\r
+ union { /* ICDIPTR38 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TGI2V:8; /* TGI2V */\r
+ _UDWORD TGI2U:8; /* TGI2U */\r
+ _UDWORD TGI3A:8; /* TGI3A */\r
+ _UDWORD TGI3B:8; /* TGI3B */\r
+ } BIT; /* */\r
+ } ICDIPTR38; /* */\r
+ union { /* ICDIPTR39 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TGI3C:8; /* TGI3C */\r
+ _UDWORD TGI3D:8; /* TGI3D */\r
+ _UDWORD TGI3V:8; /* TGI3V */\r
+ _UDWORD TGI4A:8; /* TGI4A */\r
+ } BIT; /* */\r
+ } ICDIPTR39; /* */\r
+ union { /* ICDIPTR40 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TGI4B:8; /* TGI4B */\r
+ _UDWORD TGI4C:8; /* TGI4C */\r
+ _UDWORD TGI4D:8; /* TGI4D */\r
+ _UDWORD TGI4V:8; /* TGI4V */\r
+ } BIT; /* */\r
+ } ICDIPTR40; /* */\r
+ union { /* ICDIPTR41 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CMI1:8; /* CMI1 */\r
+ _UDWORD CMI2:8; /* CMI2 */\r
+ _UDWORD SGDEI0:8; /* SGDEI0 */\r
+ _UDWORD SGDEI1:8; /* SGDEI1 */\r
+ } BIT; /* */\r
+ } ICDIPTR41; /* */\r
+ union { /* ICDIPTR42 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SGDEI2:8; /* SGDEI2 */\r
+ _UDWORD SGDEI3:8; /* SGDEI3 */\r
+ _UDWORD ADI:8; /* ADI */\r
+ _UDWORD ADWAR:8; /* ADWAR */\r
+ } BIT; /* */\r
+ } ICDIPTR42; /* */\r
+ union { /* ICDIPTR43 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SSII0:8; /* SSII0 */\r
+ _UDWORD SSIRXI0:8; /* SSIRXI0 */\r
+ _UDWORD SSITXI0:8; /* SSITXI0 */\r
+ _UDWORD SSII1:8; /* SSII1 */\r
+ } BIT; /* */\r
+ } ICDIPTR43; /* */\r
+ union { /* ICDIPTR44 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SSIRXI1:8; /* SSIRXI1 */\r
+ _UDWORD SSITXI1:8; /* SSITXI1 */\r
+ _UDWORD SSII2:8; /* SSII2 */\r
+ _UDWORD SSIRTI2:8; /* SSIRTI2 */\r
+ } BIT; /* */\r
+ } ICDIPTR44; /* */\r
+ union { /* ICDIPTR45 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SSII3:8; /* SSII3 */\r
+ _UDWORD SSIRXI3:8; /* SSIRXI3 */\r
+ _UDWORD SSITXI3:8; /* SSITXI3 */\r
+ _UDWORD SSII4:8; /* SSII4 */\r
+ } BIT; /* */\r
+ } ICDIPTR45; /* */\r
+ union { /* ICDIPTR46 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SSIRTI4:8; /* SSIRTI4 */\r
+ _UDWORD SSII5:8; /* SSII5 */\r
+ _UDWORD SSIRXI5:8; /* SSIRXI5 */\r
+ _UDWORD SSITXI5:8; /* SSITXI5 */\r
+ } BIT; /* */\r
+ } ICDIPTR46; /* */\r
+ union { /* ICDIPTR47 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPDIFI:8; /* SPDIFI */\r
+ _UDWORD TEI0:8; /* TEI0 */\r
+ _UDWORD RI0:8; /* RI0 */\r
+ _UDWORD TI0:8; /* TI0 */\r
+ } BIT; /* */\r
+ } ICDIPTR47; /* */\r
+ union { /* ICDIPTR48 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPI0:8; /* SPI0 */\r
+ _UDWORD STI0:8; /* STI0 */\r
+ _UDWORD NAKI0:8; /* NAKI0 */\r
+ _UDWORD ALI0:8; /* ALI0 */\r
+ } BIT; /* */\r
+ } ICDIPTR48; /* */\r
+ union { /* ICDIPTR49 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TMOI0:8; /* TMOI0 */\r
+ _UDWORD TEI1:8; /* TEI1 */\r
+ _UDWORD RI1:8; /* RI1 */\r
+ _UDWORD TI1:8; /* TI1 */\r
+ } BIT; /* */\r
+ } ICDIPTR49; /* */\r
+ union { /* ICDIPTR50 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPI1:8; /* SPI1 */\r
+ _UDWORD STI1:8; /* STI1 */\r
+ _UDWORD NAKI1:8; /* NAKI1 */\r
+ _UDWORD ALI1:8; /* ALI1 */\r
+ } BIT; /* */\r
+ } ICDIPTR50; /* */\r
+ union { /* ICDIPTR51 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TMOI1:8; /* TMOI1 */\r
+ _UDWORD TEI2:8; /* TEI2 */\r
+ _UDWORD RI2:8; /* RI2 */\r
+ _UDWORD TI2:8; /* TI2 */\r
+ } BIT; /* */\r
+ } ICDIPTR51; /* */\r
+ union { /* ICDIPTR52 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPI2:8; /* SPI2 */\r
+ _UDWORD STI2:8; /* STI2 */\r
+ _UDWORD NAKI2:8; /* NAKI2 */\r
+ _UDWORD ALI2:8; /* ALI2 */\r
+ } BIT; /* */\r
+ } ICDIPTR52; /* */\r
+ union { /* ICDIPTR53 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TMOI2:8; /* TMOI2 */\r
+ _UDWORD TEI3:8; /* TEI3 */\r
+ _UDWORD RI3:8; /* RI3 */\r
+ _UDWORD TI3:8; /* TI3 */\r
+ } BIT; /* */\r
+ } ICDIPTR53; /* */\r
+ union { /* ICDIPTR54 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPI3:8; /* SPI3 */\r
+ _UDWORD STI3:8; /* STI3 */\r
+ _UDWORD NAKI3:8; /* NAKI3 */\r
+ _UDWORD ALI3:8; /* ALI3 */\r
+ } BIT; /* */\r
+ } ICDIPTR54; /* */\r
+ union { /* ICDIPTR55 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TMOI3:8; /* TMOI3 */\r
+ _UDWORD BRI0:8; /* BRI0 */\r
+ _UDWORD ERI0:8; /* ERI0 */\r
+ _UDWORD RXI0:8; /* RXI0 */\r
+ } BIT; /* */\r
+ } ICDIPTR55; /* */\r
+ union { /* ICDIPTR56 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI0:8; /* TXI0 */\r
+ _UDWORD BRI1:8; /* BRI1 */\r
+ _UDWORD ERI1:8; /* ERI1 */\r
+ _UDWORD RXI1:8; /* RXI1 */\r
+ } BIT; /* */\r
+ } ICDIPTR56; /* */\r
+ union { /* ICDIPTR57 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI1:8; /* TXI1 */\r
+ _UDWORD BRI2:8; /* BRI2 */\r
+ _UDWORD ERI2:8; /* ERI2 */\r
+ _UDWORD RXI2:8; /* RXI2 */\r
+ } BIT; /* */\r
+ } ICDIPTR57; /* */\r
+ union { /* ICDIPTR58 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI2:8; /* TXI2 */\r
+ _UDWORD BRI3:8; /* BRI3 */\r
+ _UDWORD ERI3:8; /* ERI3 */\r
+ _UDWORD RXI3:8; /* RXI3 */\r
+ } BIT; /* */\r
+ } ICDIPTR58; /* */\r
+ union { /* ICDIPTR59 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI3:8; /* TXI3 */\r
+ _UDWORD BRI4:8; /* BRI4 */\r
+ _UDWORD ERI4:8; /* ERI4 */\r
+ _UDWORD RXI4:8; /* RXI4 */\r
+ } BIT; /* */\r
+ } ICDIPTR59; /* */\r
+ union { /* ICDIPTR60 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI4:8; /* TXI4 */\r
+ _UDWORD BRI5:8; /* BRI5 */\r
+ _UDWORD ERI5:8; /* ERI5 */\r
+ _UDWORD RXI5:8; /* RXI5 */\r
+ } BIT; /* */\r
+ } ICDIPTR60; /* */\r
+ union { /* ICDIPTR61 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI5:8; /* TXI5 */\r
+ _UDWORD BRI6:8; /* BRI6 */\r
+ _UDWORD ERI6:8; /* ERI6 */\r
+ _UDWORD RXI6:8; /* RXI6 */\r
+ } BIT; /* */\r
+ } ICDIPTR61; /* */\r
+ union { /* ICDIPTR62 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI6:8; /* TXI6 */\r
+ _UDWORD BRI7:8; /* BRI7 */\r
+ _UDWORD ERI7:8; /* ERI7 */\r
+ _UDWORD RXI7:8; /* RXI7 */\r
+ } BIT; /* */\r
+ } ICDIPTR62; /* */\r
+ union { /* ICDIPTR63 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI7:8; /* TXI7 */\r
+ _UDWORD GERI:8; /* GERI */\r
+ _UDWORD RFI:8; /* RFI */\r
+ _UDWORD CFRXI0:8; /* CFRXI0 */\r
+ } BIT; /* */\r
+ } ICDIPTR63; /* */\r
+ union { /* ICDIPTR64 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CERI0:8; /* CERI0 */\r
+ _UDWORD CTXI0:8; /* CTXI0 */\r
+ _UDWORD CFRXI1:8; /* CFRXI1 */\r
+ _UDWORD CERI1:8; /* CERI1 */\r
+ } BIT; /* */\r
+ } ICDIPTR64; /* */\r
+ union { /* ICDIPTR65 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CTXI1:8; /* CTXI1 */\r
+ _UDWORD CFRXI2:8; /* CFRXI2 */\r
+ _UDWORD CERI2:8; /* CERI2 */\r
+ _UDWORD CTXI2:8; /* CTXI2 */\r
+ } BIT; /* */\r
+ } ICDIPTR65; /* */\r
+ union { /* ICDIPTR66 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CFRXI3:8; /* CFRXI3 */\r
+ _UDWORD CERI3:8; /* CERI3 */\r
+ _UDWORD CTXI3:8; /* CTXI3 */\r
+ _UDWORD CFRXI4:8; /* CFRXI4 */\r
+ } BIT; /* */\r
+ } ICDIPTR66; /* */\r
+ union { /* ICDIPTR67 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CERI4:8; /* CERI4 */\r
+ _UDWORD CTXI4:8; /* CTXI4 */\r
+ _UDWORD SPEI0:8; /* SPEI0 */\r
+ _UDWORD SPRI0:8; /* SPRI0 */\r
+ } BIT; /* */\r
+ } ICDIPTR67; /* */\r
+ union { /* ICDIPTR68 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPTI0:8; /* SPTI0 */\r
+ _UDWORD SPEI1:8; /* SPEI1 */\r
+ _UDWORD SPRI1:8; /* SPRI1 */\r
+ _UDWORD SPTI1:8; /* SPTI1 */\r
+ } BIT; /* */\r
+ } ICDIPTR68; /* */\r
+ union { /* ICDIPTR69 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPEI2:8; /* SPEI2 */\r
+ _UDWORD SPRI2:8; /* SPRI2 */\r
+ _UDWORD SPTI2:8; /* SPTI2 */\r
+ _UDWORD SPEI3:8; /* SPEI3 */\r
+ } BIT; /* */\r
+ } ICDIPTR69; /* */\r
+ union { /* ICDIPTR70 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPRI3:8; /* SPRI3 */\r
+ _UDWORD SPTI3:8; /* SPTI3 */\r
+ _UDWORD SPEI4:8; /* SPEI4 */\r
+ _UDWORD SPRI4:8; /* SPRI4 */\r
+ } BIT; /* */\r
+ } ICDIPTR70; /* */\r
+ union { /* ICDIPTR71 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPTI4:8; /* SPTI4 */\r
+ _UDWORD IEBBTD:8; /* IEBBTD */\r
+ _UDWORD IEBBTERR:8; /* IEBBTERR */\r
+ _UDWORD IEBBTSTA:8; /* IEBBTSTA */\r
+ } BIT; /* */\r
+ } ICDIPTR71; /* */\r
+ union { /* ICDIPTR72 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IEBBTV:8; /* IEBBTV */\r
+ _UDWORD ISY:8; /* ISY */\r
+ _UDWORD IERR:8; /* IERR */\r
+ _UDWORD ITARG:8; /* ITARG */\r
+ } BIT; /* */\r
+ } ICDIPTR72; /* */\r
+ union { /* ICDIPTR73 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ISEC:8; /* ISEC */\r
+ _UDWORD IBUF:8; /* IBUF */\r
+ _UDWORD IREADY:8; /* IREADY */\r
+ _UDWORD FLSTE:8; /* FLSTE */\r
+ } BIT; /* */\r
+ } ICDIPTR73; /* */\r
+ union { /* ICDIPTR74 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FLTENDI:8; /* FLTENDI */\r
+ _UDWORD FLTREQ0I:8; /* FLTREQ0I */\r
+ _UDWORD FLTREQ1I:8; /* FLTREQ1I */\r
+ _UDWORD MMC0:8; /* MMC0 */\r
+ } BIT; /* */\r
+ } ICDIPTR74; /* */\r
+ union { /* ICDIPTR75 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD MMC1:8; /* MMC1 */\r
+ _UDWORD MMC2:8; /* MMC2 */\r
+ _UDWORD SDHI0_3:8; /* SDHI0_3 */\r
+ _UDWORD SDHI0_0:8; /* SDHI0_0 */\r
+ } BIT; /* */\r
+ } ICDIPTR75; /* */\r
+ union { /* ICDIPTR76 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SDHI0_1:8; /* SDHI0_1 */\r
+ _UDWORD SDHI1_3:8; /* SDHI1_3 */\r
+ _UDWORD SDHI1_0:8; /* SDHI1_0 */\r
+ _UDWORD SDHI1_1:8; /* SDHI1_1 */\r
+ } BIT; /* */\r
+ } ICDIPTR76; /* */\r
+ union { /* ICDIPTR77 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ARM:8; /* ARM */\r
+ _UDWORD PRD:8; /* PRD */\r
+ _UDWORD CUP:8; /* CUP */\r
+ _UDWORD SCUAI0:8; /* SCUAI0 */\r
+ } BIT; /* */\r
+ } ICDIPTR77; /* */\r
+ union { /* ICDIPTR78 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SCUAI1:8; /* SCUAI1 */\r
+ _UDWORD SCUFDI0:8; /* SCUFDI0 */\r
+ _UDWORD SCUFDI1:8; /* SCUFDI1 */\r
+ _UDWORD SCUFDI2:8; /* SCUFDI2 */\r
+ } BIT; /* */\r
+ } ICDIPTR78; /* */\r
+ union { /* ICDIPTR79 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SCUFDI3:8; /* SCUFDI3 */\r
+ _UDWORD SCUFUI0:8; /* SCUFUI0 */\r
+ _UDWORD SCUFUI1:8; /* SCUFUI1 */\r
+ _UDWORD SCUFUI2:8; /* SCUFUI2 */\r
+ } BIT; /* */\r
+ } ICDIPTR79; /* */\r
+ union { /* ICDIPTR80 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SCUFUI3:8; /* SCUFUI3 */\r
+ _UDWORD SCUDVI0:8; /* SCUDVI0 */\r
+ _UDWORD SCUDVI1:8; /* SCUDVI1 */\r
+ _UDWORD SCUDVI2:8; /* SCUDVI2 */\r
+ } BIT; /* */\r
+ } ICDIPTR80; /* */\r
+ union { /* ICDIPTR81 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SCUDVI3:8; /* SCUDVI3 */\r
+ _UDWORD MLBCI:8; /* MLBCI */\r
+ _UDWORD MLBSI:8; /* MLBSI */\r
+ _UDWORD DRC0:8; /* DRC0 */\r
+ } BIT; /* */\r
+ } ICDIPTR81; /* */\r
+ union { /* ICDIPTR82 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DRC1:8; /* DRC1 */\r
+ _UDWORD :16; /* */\r
+ _UDWORD LINI0_INT_T:8; /* LINI0_INT_T */\r
+ } BIT; /* */\r
+ } ICDIPTR82; /* */\r
+ union { /* ICDIPTR83 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD LINI0_INT_R:8; /* LINI0_INT_R */\r
+ _UDWORD LINI0_INT_S:8; /* LINI0_INT_S */\r
+ _UDWORD LINI0_INT_M:8; /* LINI0_INT_M */\r
+ _UDWORD LINI1_INT_T:8; /* LINI1_INT_T */\r
+ } BIT; /* */\r
+ } ICDIPTR83; /* */\r
+ union { /* ICDIPTR84 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD LINI1_INT_R:8; /* LINI1_INT_R */\r
+ _UDWORD LINI1_INT_S:8; /* LINI1_INT_S */\r
+ _UDWORD LINI1_INT_M:8; /* LINI1_INT_M */\r
+ _UDWORD :8; /* */\r
+ } BIT; /* */\r
+ } ICDIPTR84; /* */\r
+ _UBYTE wk15[4]; /* */\r
+ union { /* ICDIPTR86 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :24; /* */\r
+ _UDWORD ERI0:8; /* ERI0 */\r
+ } BIT; /* */\r
+ } ICDIPTR86; /* */\r
+ union { /* ICDIPTR87 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD RXI0:8; /* RXI0 */\r
+ _UDWORD TXI0:8; /* TXI0 */\r
+ _UDWORD TEI0:8; /* TEI0 */\r
+ _UDWORD ERI1:8; /* ERI1 */\r
+ } BIT; /* */\r
+ } ICDIPTR87; /* */\r
+ union { /* ICDIPTR88 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD RXI1:8; /* RXI1 */\r
+ _UDWORD TXI1:8; /* TXI1 */\r
+ _UDWORD TEI1:8; /* TEI1 */\r
+ _UDWORD :8; /* */\r
+ } BIT; /* */\r
+ } ICDIPTR88; /* */\r
+ union { /* ICDIPTR89 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :24; /* */\r
+ _UDWORD ETHERI:8; /* ETHERI */\r
+ } BIT; /* */\r
+ } ICDIPTR89; /* */\r
+ _UBYTE wk16[4]; /* */\r
+ union { /* ICDIPTR91 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CEUI:8; /* CEUI */\r
+ _UDWORD INT_CSIH0TIR:8; /* INT_CSIH0TIR */\r
+ _UDWORD INT_CSIH0TIRE:8; /* INT_CSIH0TIRE */\r
+ _UDWORD INT_CSIH1TIC:8; /* INT_CSIH1TIC */\r
+ } BIT; /* */\r
+ } ICDIPTR91; /* */\r
+ union { /* ICDIPTR92 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD INT_CSIH1TIJC:8; /* INT_CSIH1TIJC */\r
+ _UDWORD ECCE10:8; /* ECCE10 */\r
+ _UDWORD ECCE20:8; /* ECCE20 */\r
+ _UDWORD ECCOVF0:8; /* ECCOVF0 */\r
+ } BIT; /* */\r
+ } ICDIPTR92; /* */\r
+ union { /* ICDIPTR93 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ECCE11:8; /* ECCE11 */\r
+ _UDWORD ECCE21:8; /* ECCE21 */\r
+ _UDWORD ECCOVF1:8; /* ECCOVF1 */\r
+ _UDWORD ECCE12:8; /* ECCE12 */\r
+ } BIT; /* */\r
+ } ICDIPTR93; /* */\r
+ union { /* ICDIPTR94 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ECCE22:8; /* ECCE22 */\r
+ _UDWORD ECCOVF2:8; /* ECCOVF2 */\r
+ _UDWORD ECCE13:8; /* ECCE13 */\r
+ _UDWORD ECCE23:8; /* ECCE23 */\r
+ } BIT; /* */\r
+ } ICDIPTR94; /* */\r
+ union { /* ICDIPTR95 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ECCOVF3:8; /* ECCOVF3 */\r
+ _UDWORD H2XMLB_ERRINT:8; /* H2XMLB_ERRINT */\r
+ _UDWORD H2XIC1_ERRINT:8; /* H2XIC1_ERRINT */\r
+ _UDWORD X2HPERI1_ERRINT:8; /* X2HPERI1_ERRINT */\r
+ } BIT; /* */\r
+ } ICDIPTR95; /* */\r
+ union { /* ICDIPTR96 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD X2HPERI2_ERRINT:8; /* X2HPERI2_ERRINT */\r
+ _UDWORD X2HPERI34_ERRINT:8; /* X2HPERI34_ERRINT */\r
+ _UDWORD X2HPERI5_ERRINT:8; /* X2HPERI5_ERRINT */\r
+ _UDWORD X2HPERI67_ERRINT:8; /* X2HPERI67_ERRINT */\r
+ } BIT; /* */\r
+ } ICDIPTR96; /* */\r
+ union { /* ICDIPTR97 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD X2HDBGR_ERRINT:8; /* X2HDBGR_ERRINT */\r
+ _UDWORD PRRI:8; /* PRRI */\r
+ _UDWORD IFEI0:8; /* IFEI0 */\r
+ _UDWORD OFFI0:8; /* OFFI0 */\r
+ } BIT; /* */\r
+ } ICDIPTR97; /* */\r
+ union { /* ICDIPTR98 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD PFVEI0:8; /* PFVEI0 */\r
+ _UDWORD IFEI1:8; /* IFEI1 */\r
+ _UDWORD OFFI1:8; /* OFFI1 */\r
+ _UDWORD PFVEI1:8; /* PFVEI1 */\r
+ } BIT; /* */\r
+ } ICDIPTR98; /* */\r
+ _UBYTE wk17[20]; /* */\r
+ union { /* ICDIPTR104 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT0:8; /* TINT0 */\r
+ _UDWORD TINT1:8; /* TINT1 */\r
+ _UDWORD TINT2:8; /* TINT2 */\r
+ _UDWORD TINT3:8; /* TINT3 */\r
+ } BIT; /* */\r
+ } ICDIPTR104; /* */\r
+ union { /* ICDIPTR105 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT4:8; /* TINT4 */\r
+ _UDWORD TINT5:8; /* TINT5 */\r
+ _UDWORD TINT6:8; /* TINT6 */\r
+ _UDWORD TINT7:8; /* TINT7 */\r
+ } BIT; /* */\r
+ } ICDIPTR105; /* */\r
+ union { /* ICDIPTR106 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT8:8; /* TINT8 */\r
+ _UDWORD TINT9:8; /* TINT9 */\r
+ _UDWORD TINT10:8; /* TINT10 */\r
+ _UDWORD TINT11:8; /* TINT11 */\r
+ } BIT; /* */\r
+ } ICDIPTR106; /* */\r
+ union { /* ICDIPTR107 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT12:8; /* TINT12 */\r
+ _UDWORD TINT13:8; /* TINT13 */\r
+ _UDWORD TINT14:8; /* TINT14 */\r
+ _UDWORD TINT15:8; /* TINT15 */\r
+ } BIT; /* */\r
+ } ICDIPTR107; /* */\r
+ union { /* ICDIPTR108 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT16:8; /* TINT16 */\r
+ _UDWORD TINT17:8; /* TINT17 */\r
+ _UDWORD TINT18:8; /* TINT18 */\r
+ _UDWORD TINT19:8; /* TINT19 */\r
+ } BIT; /* */\r
+ } ICDIPTR108; /* */\r
+ union { /* ICDIPTR109 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT20:8; /* TINT20 */\r
+ _UDWORD TINT21:8; /* TINT21 */\r
+ _UDWORD TINT22:8; /* TINT22 */\r
+ _UDWORD TINT23:8; /* TINT23 */\r
+ } BIT; /* */\r
+ } ICDIPTR109; /* */\r
+ union { /* ICDIPTR110 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT24:8; /* TINT24 */\r
+ _UDWORD TINT25:8; /* TINT25 */\r
+ _UDWORD TINT26:8; /* TINT26 */\r
+ _UDWORD TINT27:8; /* TINT27 */\r
+ } BIT; /* */\r
+ } ICDIPTR110; /* */\r
+ union { /* ICDIPTR111 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT28:8; /* TINT28 */\r
+ _UDWORD TINT29:8; /* TINT29 */\r
+ _UDWORD TINT30:8; /* TINT30 */\r
+ _UDWORD TINT31:8; /* TINT31 */\r
+ } BIT; /* */\r
+ } ICDIPTR111; /* */\r
+ union { /* ICDIPTR112 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT32:8; /* TINT32 */\r
+ _UDWORD TINT33:8; /* TINT33 */\r
+ _UDWORD TINT34:8; /* TINT34 */\r
+ _UDWORD TINT35:8; /* TINT35 */\r
+ } BIT; /* */\r
+ } ICDIPTR112; /* */\r
+ union { /* ICDIPTR113 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT36:8; /* TINT36 */\r
+ _UDWORD TINT37:8; /* TINT37 */\r
+ _UDWORD TINT38:8; /* TINT38 */\r
+ _UDWORD TINT39:8; /* TINT39 */\r
+ } BIT; /* */\r
+ } ICDIPTR113; /* */\r
+ union { /* ICDIPTR114 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT40:8; /* TINT40 */\r
+ _UDWORD TINT41:8; /* TINT41 */\r
+ _UDWORD TINT42:8; /* TINT42 */\r
+ _UDWORD TINT43:8; /* TINT43 */\r
+ } BIT; /* */\r
+ } ICDIPTR114; /* */\r
+ union { /* ICDIPTR115 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT44:8; /* TINT44 */\r
+ _UDWORD TINT45:8; /* TINT45 */\r
+ _UDWORD TINT46:8; /* TINT46 */\r
+ _UDWORD TINT47:8; /* TINT47 */\r
+ } BIT; /* */\r
+ } ICDIPTR115; /* */\r
+ union { /* ICDIPTR116 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT48:8; /* TINT48 */\r
+ _UDWORD TINT49:8; /* TINT49 */\r
+ _UDWORD TINT50:8; /* TINT50 */\r
+ _UDWORD TINT51:8; /* TINT51 */\r
+ } BIT; /* */\r
+ } ICDIPTR116; /* */\r
+ union { /* ICDIPTR117 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT52:8; /* TINT52 */\r
+ _UDWORD TINT53:8; /* TINT53 */\r
+ _UDWORD TINT54:8; /* TINT54 */\r
+ _UDWORD TINT55:8; /* TINT55 */\r
+ } BIT; /* */\r
+ } ICDIPTR117; /* */\r
+ union { /* ICDIPTR118 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT56:8; /* TINT56 */\r
+ _UDWORD TINT57:8; /* TINT57 */\r
+ _UDWORD TINT58:8; /* TINT58 */\r
+ _UDWORD TINT59:8; /* TINT59 */\r
+ } BIT; /* */\r
+ } ICDIPTR118; /* */\r
+ union { /* ICDIPTR119 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT60:8; /* TINT60 */\r
+ _UDWORD TINT61:8; /* TINT61 */\r
+ _UDWORD TINT62:8; /* TINT62 */\r
+ _UDWORD TINT63:8; /* TINT63 */\r
+ } BIT; /* */\r
+ } ICDIPTR119; /* */\r
+ union { /* ICDIPTR120 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT64:8; /* TINT64 */\r
+ _UDWORD TINT65:8; /* TINT65 */\r
+ _UDWORD TINT66:8; /* TINT66 */\r
+ _UDWORD TINT67:8; /* TINT67 */\r
+ } BIT; /* */\r
+ } ICDIPTR120; /* */\r
+ union { /* ICDIPTR121 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT68:8; /* TINT68 */\r
+ _UDWORD TINT69:8; /* TINT69 */\r
+ _UDWORD TINT70:8; /* TINT70 */\r
+ _UDWORD TINT71:8; /* TINT71 */\r
+ } BIT; /* */\r
+ } ICDIPTR121; /* */\r
+ union { /* ICDIPTR122 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT72:8; /* TINT72 */\r
+ _UDWORD TINT73:8; /* TINT73 */\r
+ _UDWORD TINT74:8; /* TINT74 */\r
+ _UDWORD TINT75:8; /* TINT75 */\r
+ } BIT; /* */\r
+ } ICDIPTR122; /* */\r
+ union { /* ICDIPTR123 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT76:8; /* TINT76 */\r
+ _UDWORD TINT77:8; /* TINT77 */\r
+ _UDWORD TINT78:8; /* TINT78 */\r
+ _UDWORD TINT79:8; /* TINT79 */\r
+ } BIT; /* */\r
+ } ICDIPTR123; /* */\r
+ union { /* ICDIPTR124 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT80:8; /* TINT80 */\r
+ _UDWORD TINT81:8; /* TINT81 */\r
+ _UDWORD TINT82:8; /* TINT82 */\r
+ _UDWORD TINT83:8; /* TINT83 */\r
+ } BIT; /* */\r
+ } ICDIPTR124; /* */\r
+ union { /* ICDIPTR125 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT84:8; /* TINT84 */\r
+ _UDWORD TINT85:8; /* TINT85 */\r
+ _UDWORD TINT86:8; /* TINT86 */\r
+ _UDWORD TINT87:8; /* TINT87 */\r
+ } BIT; /* */\r
+ } ICDIPTR125; /* */\r
+ union { /* ICDIPTR126 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT88:8; /* TINT88 */\r
+ _UDWORD TINT89:8; /* TINT89 */\r
+ _UDWORD TINT90:8; /* TINT90 */\r
+ _UDWORD TINT91:8; /* TINT91 */\r
+ } BIT; /* */\r
+ } ICDIPTR126; /* */\r
+ union { /* ICDIPTR127 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT92:8; /* TINT92 */\r
+ _UDWORD TINT93:8; /* TINT93 */\r
+ _UDWORD TINT94:8; /* TINT94 */\r
+ _UDWORD TINT95:8; /* TINT95 */\r
+ } BIT; /* */\r
+ } ICDIPTR127; /* */\r
+ union { /* ICDIPTR128 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT96:8; /* TINT96 */\r
+ _UDWORD TINT97:8; /* TINT97 */\r
+ _UDWORD TINT98:8; /* TINT98 */\r
+ _UDWORD TINT99:8; /* TINT99 */\r
+ } BIT; /* */\r
+ } ICDIPTR128; /* */\r
+ union { /* ICDIPTR129 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT100:8; /* TINT100 */\r
+ _UDWORD TINT101:8; /* TINT101 */\r
+ _UDWORD TINT102:8; /* TINT102 */\r
+ _UDWORD TINT103:8; /* TINT103 */\r
+ } BIT; /* */\r
+ } ICDIPTR129; /* */\r
+ union { /* ICDIPTR130 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT104:8; /* TINT104 */\r
+ _UDWORD TINT105:8; /* TINT105 */\r
+ _UDWORD TINT106:8; /* TINT106 */\r
+ _UDWORD TINT107:8; /* TINT107 */\r
+ } BIT; /* */\r
+ } ICDIPTR130; /* */\r
+ union { /* ICDIPTR131 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT108:8; /* TINT108 */\r
+ _UDWORD TINT109:8; /* TINT109 */\r
+ _UDWORD TINT110:8; /* TINT110 */\r
+ _UDWORD TINT111:8; /* TINT111 */\r
+ } BIT; /* */\r
+ } ICDIPTR131; /* */\r
+ union { /* ICDIPTR132 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT112:8; /* TINT112 */\r
+ _UDWORD TINT113:8; /* TINT113 */\r
+ _UDWORD TINT114:8; /* TINT114 */\r
+ _UDWORD TINT115:8; /* TINT115 */\r
+ } BIT; /* */\r
+ } ICDIPTR132; /* */\r
+ union { /* ICDIPTR133 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT116:8; /* TINT116 */\r
+ _UDWORD TINT117:8; /* TINT117 */\r
+ _UDWORD TINT118:8; /* TINT118 */\r
+ _UDWORD TINT119:8; /* TINT119 */\r
+ } BIT; /* */\r
+ } ICDIPTR133; /* */\r
+ union { /* ICDIPTR134 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT120:8; /* TINT120 */\r
+ _UDWORD TINT121:8; /* TINT121 */\r
+ _UDWORD TINT122:8; /* TINT122 */\r
+ _UDWORD TINT123:8; /* TINT123 */\r
+ } BIT; /* */\r
+ } ICDIPTR134; /* */\r
+ union { /* ICDIPTR135 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT124:8; /* TINT124 */\r
+ _UDWORD TINT125:8; /* TINT125 */\r
+ _UDWORD TINT126:8; /* TINT126 */\r
+ _UDWORD TINT127:8; /* TINT127 */\r
+ } BIT; /* */\r
+ } ICDIPTR135; /* */\r
+ union { /* ICDIPTR136 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT128:8; /* TINT128 */\r
+ _UDWORD TINT129:8; /* TINT129 */\r
+ _UDWORD TINT130:8; /* TINT130 */\r
+ _UDWORD TINT131:8; /* TINT131 */\r
+ } BIT; /* */\r
+ } ICDIPTR136; /* */\r
+ union { /* ICDIPTR137 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT132:8; /* TINT132 */\r
+ _UDWORD TINT133:8; /* TINT133 */\r
+ _UDWORD TINT134:8; /* TINT134 */\r
+ _UDWORD TINT135:8; /* TINT135 */\r
+ } BIT; /* */\r
+ } ICDIPTR137; /* */\r
+ union { /* ICDIPTR138 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT136:8; /* TINT136 */\r
+ _UDWORD TINT137:8; /* TINT137 */\r
+ _UDWORD TINT138:8; /* TINT138 */\r
+ _UDWORD TINT139:8; /* TINT139 */\r
+ } BIT; /* */\r
+ } ICDIPTR138; /* */\r
+ union { /* ICDIPTR139 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT140:8; /* TINT140 */\r
+ _UDWORD TINT141:8; /* TINT141 */\r
+ _UDWORD TINT142:8; /* TINT142 */\r
+ _UDWORD TINT143:8; /* TINT143 */\r
+ } BIT; /* */\r
+ } ICDIPTR139; /* */\r
+ union { /* ICDIPTR140 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT144:8; /* TINT144 */\r
+ _UDWORD TINT145:8; /* TINT145 */\r
+ _UDWORD TINT146:8; /* TINT146 */\r
+ _UDWORD TINT147:8; /* TINT147 */\r
+ } BIT; /* */\r
+ } ICDIPTR140; /* */\r
+ union { /* ICDIPTR141 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT148:8; /* TINT148 */\r
+ _UDWORD TINT149:8; /* TINT149 */\r
+ _UDWORD TINT150:8; /* TINT150 */\r
+ _UDWORD TINT151:8; /* TINT151 */\r
+ } BIT; /* */\r
+ } ICDIPTR141; /* */\r
+ union { /* ICDIPTR142 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT152:8; /* TINT152 */\r
+ _UDWORD TINT153:8; /* TINT153 */\r
+ _UDWORD TINT154:8; /* TINT154 */\r
+ _UDWORD TINT155:8; /* TINT155 */\r
+ } BIT; /* */\r
+ } ICDIPTR142; /* */\r
+ union { /* ICDIPTR143 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT156:8; /* TINT156 */\r
+ _UDWORD TINT157:8; /* TINT157 */\r
+ _UDWORD TINT158:8; /* TINT158 */\r
+ _UDWORD TINT159:8; /* TINT159 */\r
+ } BIT; /* */\r
+ } ICDIPTR143; /* */\r
+ union { /* ICDIPTR144 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT160:8; /* TINT160 */\r
+ _UDWORD TINT161:8; /* TINT161 */\r
+ _UDWORD TINT162:8; /* TINT162 */\r
+ _UDWORD :8; /* */\r
+ } BIT; /* */\r
+ } ICDIPTR144; /* */\r
+ _UBYTE wk18[444]; /* */\r
+ union { /* ICDICFR */\r
+ _UDWORD LONG[36]; /* Long Access */\r
+ struct { /* ICDICFRn */\r
+ union { /* ICDICFR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SW0_0:1; /* SW0[0] */\r
+ _UDWORD SW0_1:1; /* SW0[1] */\r
+ _UDWORD SW1_0:1; /* SW1[0] */\r
+ _UDWORD SW1_1:1; /* SW1[1] */\r
+ _UDWORD SW2_0:1; /* SW2[0] */\r
+ _UDWORD SW2_1:1; /* SW2[1] */\r
+ _UDWORD SW3_0:1; /* SW3[0] */\r
+ _UDWORD SW3_1:1; /* SW3[1] */\r
+ _UDWORD SW4_0:1; /* SW4[0] */\r
+ _UDWORD SW4_1:1; /* SW4[1] */\r
+ _UDWORD SW5_0:1; /* SW5[0] */\r
+ _UDWORD SW5_1:1; /* SW5[1] */\r
+ _UDWORD SW6_0:1; /* SW6[0] */\r
+ _UDWORD SW6_1:1; /* SW6[1] */\r
+ _UDWORD SW7_0:1; /* SW7[0] */\r
+ _UDWORD SW7_1:1; /* SW7[1] */\r
+ _UDWORD SW8_0:1; /* SW8[0] */\r
+ _UDWORD SW8_1:1; /* SW8[1] */\r
+ _UDWORD SW9_0:1; /* SW9[0] */\r
+ _UDWORD SW9_1:1; /* SW9[1] */\r
+ _UDWORD SW10_0:1; /* SW10[0] */\r
+ _UDWORD SW10_1:1; /* SW10[1] */\r
+ _UDWORD SW11_0:1; /* SW11[0] */\r
+ _UDWORD SW11_1:1; /* SW11[1] */\r
+ _UDWORD SW12_0:1; /* SW12[0] */\r
+ _UDWORD SW12_1:1; /* SW12[1] */\r
+ _UDWORD SW13_0:1; /* SW13[0] */\r
+ _UDWORD SW13_1:1; /* SW13[1] */\r
+ _UDWORD SW14_0:1; /* SW14[0] */\r
+ _UDWORD SW14_1:1; /* SW14[1] */\r
+ _UDWORD SW15_0:1; /* SW15[0] */\r
+ _UDWORD SW15_1:1; /* SW15[1] */\r
+ } BIT; /* */\r
+ } ICDICFR0; /* */\r
+ union { /* ICDICFR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD PMUIRQ0_0:1; /* PMUIRQ0[0] */\r
+ _UDWORD PMUIRQ0_1:1; /* PMUIRQ0[1] */\r
+ _UDWORD COMMRX0_0:1; /* COMMRX0[0] */\r
+ _UDWORD COMMRX0_1:1; /* COMMRX0[1] */\r
+ _UDWORD COMMTX0_0:1; /* COMMTX0[0] */\r
+ _UDWORD COMMTX0_1:1; /* COMMTX0[1] */\r
+ _UDWORD CTIIRQ0_0:1; /* CTIIRQ0[0] */\r
+ _UDWORD CTIIRQ0_1:1; /* CTIIRQ0[1] */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } ICDICFR1; /* */\r
+ union { /* ICDICFR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IRQ0_0:1; /* IRQ0[0] */\r
+ _UDWORD IRQ0_1:1; /* IRQ0[1] */\r
+ _UDWORD IRQ1_0:1; /* IRQ1[0] */\r
+ _UDWORD IRQ1_1:1; /* IRQ1[1] */\r
+ _UDWORD IRQ2_0:1; /* IRQ2[0] */\r
+ _UDWORD IRQ2_1:1; /* IRQ2[1] */\r
+ _UDWORD IRQ3_0:1; /* IRQ3[0] */\r
+ _UDWORD IRQ3_1:1; /* IRQ3[1] */\r
+ _UDWORD IRQ4_0:1; /* IRQ4[0] */\r
+ _UDWORD IRQ4_1:1; /* IRQ4[1] */\r
+ _UDWORD IRQ5_0:1; /* IRQ5[0] */\r
+ _UDWORD IRQ5_1:1; /* IRQ5[1] */\r
+ _UDWORD IRQ6_0:1; /* IRQ6[0] */\r
+ _UDWORD IRQ6_1:1; /* IRQ6[1] */\r
+ _UDWORD IRQ7_0:1; /* IRQ7[0] */\r
+ _UDWORD IRQ7_1:1; /* IRQ7[1] */\r
+ _UDWORD PL310ERR_0:1; /* PL310ERR[0] */\r
+ _UDWORD PL310ERR_1:1; /* PL310ERR[1] */\r
+ _UDWORD DMAINT0_0:1; /* DMAINT0[0] */\r
+ _UDWORD DMAINT0_1:1; /* DMAINT0[1] */\r
+ _UDWORD DMAINT1_0:1; /* DMAINT1[0] */\r
+ _UDWORD DMAINT1_1:1; /* DMAINT1[1] */\r
+ _UDWORD DMAINT2_0:1; /* DMAINT2[0] */\r
+ _UDWORD DMAINT2_1:1; /* DMAINT2[1] */\r
+ _UDWORD DMAINT3_0:1; /* DMAINT3[0] */\r
+ _UDWORD DMAINT3_1:1; /* DMAINT3[1] */\r
+ _UDWORD DMAINT4_0:1; /* DMAINT4[0] */\r
+ _UDWORD DMAINT4_1:1; /* DMAINT4[1] */\r
+ _UDWORD DMAINT5_0:1; /* DMAINT5[0] */\r
+ _UDWORD DMAINT5_1:1; /* DMAINT5[1] */\r
+ _UDWORD DMAINT6_0:1; /* DMAINT6[0] */\r
+ _UDWORD DMAINT6_1:1; /* DMAINT6[1] */\r
+ } BIT; /* */\r
+ } ICDICFR2; /* */\r
+ union { /* ICDICFR3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DMAINT7_0:1; /* DMAINT7[0] */\r
+ _UDWORD DMAINT7_1:1; /* DMAINT7[1] */\r
+ _UDWORD DMAINT8_0:1; /* DMAINT8[0] */\r
+ _UDWORD DMAINT8_1:1; /* DMAINT8[1] */\r
+ _UDWORD DMAINT9_0:1; /* DMAINT9[0] */\r
+ _UDWORD DMAINT9_1:1; /* DMAINT9[1] */\r
+ _UDWORD DMAINT10_0:1; /* DMAINT10[0] */\r
+ _UDWORD DMAINT10_1:1; /* DMAINT10[1] */\r
+ _UDWORD DMAINT11_0:1; /* DMAINT11[0] */\r
+ _UDWORD DMAINT11_1:1; /* DMAINT11[1] */\r
+ _UDWORD DMAINT12_0:1; /* DMAINT12[0] */\r
+ _UDWORD DMAINT12_1:1; /* DMAINT12[1] */\r
+ _UDWORD DMAINT13_0:1; /* DMAINT13[0] */\r
+ _UDWORD DMAINT13_1:1; /* DMAINT13[1] */\r
+ _UDWORD DMAINT14_0:1; /* DMAINT14[0] */\r
+ _UDWORD DMAINT14_1:1; /* DMAINT14[1] */\r
+ _UDWORD DMAINT15_0:1; /* DMAINT15[0] */\r
+ _UDWORD DMAINT15_1:1; /* DMAINT15[1] */\r
+ _UDWORD DMAERR_0:1; /* DMAERR[0] */\r
+ _UDWORD DMAERR_1:1; /* DMAERR[1] */\r
+ _UDWORD :12; /* */\r
+ } BIT; /* */\r
+ } ICDICFR3; /* */\r
+ union { /* ICDICFR4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :18; /* */\r
+ _UDWORD USBI0_0:1; /* USBI0[0] */\r
+ _UDWORD USBI0_1:1; /* USBI0[1] */\r
+ _UDWORD USBI1_0:1; /* USBI1[0] */\r
+ _UDWORD USBI1_1:1; /* USBI1[1] */\r
+ _UDWORD S0_VI_VSYNC0_0:1;/* S0_VI_VSYNC0[0] */\r
+ _UDWORD S0_VI_VSYNC0_1:1;/* S0_VI_VSYNC0[1] */\r
+ _UDWORD S0_LO_VSYNC0_0:1;/* S0_LO_VSYNC0[0] */\r
+ _UDWORD S0_LO_VSYNC0_1:1;/* S0_LO_VSYNC0[1] */\r
+ _UDWORD S0_VSYNCERR0_0:1;/* S0_VSYNCERR0[0] */\r
+ _UDWORD S0_VSYNCERR0_1:1;/* S0_VSYNCERR0[1] */\r
+ _UDWORD GR3_VLINE0_0:1;/* GR3_VLINE0[0] */\r
+ _UDWORD GR3_VLINE0_1:1;/* GR3_VLINE0[1] */\r
+ _UDWORD S0_VFIELD0_0:1;/* S0_VFIELD0[0] */\r
+ _UDWORD S0_VFIELD0_1:1;/* S0_VFIELD0[1] */\r
+ } BIT; /* */\r
+ } ICDICFR4; /* */\r
+ union { /* ICDICFR5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IV1_VBUFERR0_0:1;/* IV1_VBUFERR0[0] */\r
+ _UDWORD IV1_VBUFERR0_1:1;/* IV1_VBUFERR0[1] */\r
+ _UDWORD IV3_VBUFERR0_0:1;/* IV3_VBUFERR0[0] */\r
+ _UDWORD IV3_VBUFERR0_1:1;/* IV3_VBUFERR0[1] */\r
+ _UDWORD IV5_VBUFERR0_0:1;/* IV5_VBUFERR0[0] */\r
+ _UDWORD IV5_VBUFERR0_1:1;/* IV5_VBUFERR0[1] */\r
+ _UDWORD IV6_VBUFERR0_0:1;/* IV6_VBUFERR0[0] */\r
+ _UDWORD IV6_VBUFERR0_1:1;/* IV6_VBUFERR0[1] */\r
+ _UDWORD S0_WLINE0_0:1;/* S0_WLINE0[0] */\r
+ _UDWORD S0_WLINE0_1:1;/* S0_WLINE0[1] */\r
+ _UDWORD S1_VI_VSYNC0_0:1;/* S1_VI_VSYNC0[0] */\r
+ _UDWORD S1_VI_VSYNC0_1:1;/* S1_VI_VSYNC0[1] */\r
+ _UDWORD S1_LO_VSYNC0_0:1;/* S1_LO_VSYNC0[0] */\r
+ _UDWORD S1_LO_VSYNC0_1:1;/* S1_LO_VSYNC0[1] */\r
+ _UDWORD S1_VSYNCERR0_0:1;/* S1_VSYNCERR0[0] */\r
+ _UDWORD S1_VSYNCERR0_1:1;/* S1_VSYNCERR0[1] */\r
+ _UDWORD S1_VFIELD0_0:1;/* S1_VFIELD0[0] */\r
+ _UDWORD S1_VFIELD0_1:1;/* S1_VFIELD0[1] */\r
+ _UDWORD IV2_VBUFERR0_0:1;/* IV2_VBUFERR0[0] */\r
+ _UDWORD IV2_VBUFERR0_1:1;/* IV2_VBUFERR0[1] */\r
+ _UDWORD IV4_VBUFERR0_0:1;/* IV4_VBUFERR0[0] */\r
+ _UDWORD IV4_VBUFERR0_1:1;/* IV4_VBUFERR0[1] */\r
+ _UDWORD S1_WLINE0_0:1;/* S1_WLINE0[0] */\r
+ _UDWORD S1_WLINE0_1:1;/* S1_WLINE0[1] */\r
+ _UDWORD OIR_VI_VSYNC0_0:1;/* OIR_VI_VSYNC0[0] */\r
+ _UDWORD OIR_VI_VSYNC0_1:1;/* OIR_VI_VSYNC0[1] */\r
+ _UDWORD OIR_LO_VSYNC0_0:1;/* OIR_LO_VSYNC0[0] */\r
+ _UDWORD OIR_LO_VSYNC0_1:1;/* OIR_LO_VSYNC0[1] */\r
+ _UDWORD OIR_VSYNCERR0_0:1;/* OIR_VSYNCERR0[0] */\r
+ _UDWORD OIR_VSYNCERR0_1:1;/* OIR_VSYNCERR0[1] */\r
+ _UDWORD OIR_VFIELD0_0:1;/* OIR_VFIELD0[0] */\r
+ _UDWORD OIR_VFIELD0_1:1;/* OIR_VFIELD0[1] */\r
+ } BIT; /* */\r
+ } ICDICFR5; /* */\r
+ union { /* ICDICFR6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IV7_VBUFERR0_0:1;/* IV7_VBUFERR0[0] */\r
+ _UDWORD IV7_VBUFERR0_1:1;/* IV7_VBUFERR0[1] */\r
+ _UDWORD IV8_VBUFERR0_0:1;/* IV8_VBUFERR0[0] */\r
+ _UDWORD IV8_VBUFERR0_1:1;/* IV8_VBUFERR0[1] */\r
+ _UDWORD OIR_WLINE0_0:1;/* OIR_WLINE0[0] */\r
+ _UDWORD OIR_WLINE0_1:1;/* OIR_WLINE0[1] */\r
+ _UDWORD S0_VI_VSYNC1_0:1;/* S0_VI_VSYNC1[0] */\r
+ _UDWORD S0_VI_VSYNC1_1:1;/* S0_VI_VSYNC1[1] */\r
+ _UDWORD S0_LO_VSYNC1_0:1;/* S0_LO_VSYNC1[0] */\r
+ _UDWORD S0_LO_VSYNC1_1:1;/* S0_LO_VSYNC1[1] */\r
+ _UDWORD S0_VSYNCERR1_0:1;/* S0_VSYNCERR1[0] */\r
+ _UDWORD S0_VSYNCERR1_1:1;/* S0_VSYNCERR1[1] */\r
+ _UDWORD GR3_VLINE1_0:1;/* GR3_VLINE1[0] */\r
+ _UDWORD GR3_VLINE1_1:1;/* GR3_VLINE1[1] */\r
+ _UDWORD S0_VFIELD1_0:1;/* S0_VFIELD1[0] */\r
+ _UDWORD S0_VFIELD1_1:1;/* S0_VFIELD1[1] */\r
+ _UDWORD IV1_VBUFERR1_0:1;/* IV1_VBUFERR1[0] */\r
+ _UDWORD IV1_VBUFERR1_1:1;/* IV1_VBUFERR1[1] */\r
+ _UDWORD IV3_VBUFERR1_0:1;/* IV3_VBUFERR1[0] */\r
+ _UDWORD IV3_VBUFERR1_1:1;/* IV3_VBUFERR1[1] */\r
+ _UDWORD IV5_VBUFERR1_0:1;/* IV5_VBUFERR1[0] */\r
+ _UDWORD IV5_VBUFERR1_1:1;/* IV5_VBUFERR1[1] */\r
+ _UDWORD IV6_VBUFERR1_0:1;/* IV6_VBUFERR1[0] */\r
+ _UDWORD IV6_VBUFERR1_1:1;/* IV6_VBUFERR1[1] */\r
+ _UDWORD S0_WLINE1_0:1;/* S0_WLINE1[0] */\r
+ _UDWORD S0_WLINE1_1:1;/* S0_WLINE1[1] */\r
+ _UDWORD S1_VI_VSYNC1_0:1;/* S1_VI_VSYNC1[0] */\r
+ _UDWORD S1_VI_VSYNC1_1:1;/* S1_VI_VSYNC1[1] */\r
+ _UDWORD S1_LO_VSYNC1_0:1;/* S1_LO_VSYNC1[0] */\r
+ _UDWORD S1_LO_VSYNC1_1:1;/* S1_LO_VSYNC1[1] */\r
+ _UDWORD S1_VSYNCERR1_0:1;/* S1_VSYNCERR1[0] */\r
+ _UDWORD S1_VSYNCERR1_1:1;/* S1_VSYNCERR1[1] */\r
+ } BIT; /* */\r
+ } ICDICFR6; /* */\r
+ union { /* ICDICFR7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD S1_VFIELD1_0:1;/* S1_VFIELD1[0] */\r
+ _UDWORD S1_VFIELD1_1:1;/* S1_VFIELD1[1] */\r
+ _UDWORD IV2_VBUFERR1_0:1;/* IV2_VBUFERR1[0] */\r
+ _UDWORD IV2_VBUFERR1_1:1;/* IV2_VBUFERR1[1] */\r
+ _UDWORD IV4_VBUFERR1_0:1;/* IV4_VBUFERR1[0] */\r
+ _UDWORD IV4_VBUFERR1_1:1;/* IV4_VBUFERR1[1] */\r
+ _UDWORD S1_WLINE1_0:1;/* S1_WLINE1[0] */\r
+ _UDWORD S1_WLINE1_1:1;/* S1_WLINE1[1] */\r
+ _UDWORD OIR_VI_VSYNC1_0:1;/* OIR_VI_VSYNC1[0] */\r
+ _UDWORD OIR_VI_VSYNC1_1:1;/* OIR_VI_VSYNC1[1] */\r
+ _UDWORD OIR_LO_VSYNC1_0:1;/* OIR_LO_VSYNC1[0] */\r
+ _UDWORD OIR_LO_VSYNC1_1:1;/* OIR_LO_VSYNC1[1] */\r
+ _UDWORD OIR_VLINE1_0:1;/* OIR_VLINE1[0] */\r
+ _UDWORD OIR_VLINE1_1:1;/* OIR_VLINE1[1] */\r
+ _UDWORD OIR_VFIELD1_0:1;/* OIR_VFIELD1[0] */\r
+ _UDWORD OIR_VFIELD1_1:1;/* OIR_VFIELD1[1] */\r
+ _UDWORD IV7_VBUFERR1_0:1;/* IV7_VBUFERR1[0] */\r
+ _UDWORD IV7_VBUFERR1_1:1;/* IV7_VBUFERR1[1] */\r
+ _UDWORD IV8_VBUFERR1_0:1;/* IV8_VBUFERR1[0] */\r
+ _UDWORD IV8_VBUFERR1_1:1;/* IV8_VBUFERR1[1] */\r
+ _UDWORD OIR_WLINE1_0:1;/* OIR_WLINE1[0] */\r
+ _UDWORD OIR_WLINE1_1:1;/* OIR_WLINE1[1] */\r
+ _UDWORD IMRDI_0:1; /* IMRDI[0] */\r
+ _UDWORD IMRDI_1:1; /* IMRDI[1] */\r
+ _UDWORD IMR2I0_0:1; /* IMR2I0[0] */\r
+ _UDWORD IMR2I0_1:1; /* IMR2I0[1] */\r
+ _UDWORD IMR2I1_0:1; /* IMR2I1[0] */\r
+ _UDWORD IMR2I1_1:1; /* IMR2I1[1] */\r
+ _UDWORD JEDI_0:1; /* JEDI[0] */\r
+ _UDWORD JEDI_1:1; /* JEDI[1] */\r
+ _UDWORD JDTI_0:1; /* JDTI[0] */\r
+ _UDWORD JDTI_1:1; /* JDTI[1] */\r
+ } BIT; /* */\r
+ } ICDICFR7; /* */\r
+ union { /* ICDICFR8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CMP0_0:1; /* CMP0[0] */\r
+ _UDWORD CMP0_1:1; /* CMP0[1] */\r
+ _UDWORD CMP1_0:1; /* CMP1[0] */\r
+ _UDWORD CMP1_1:1; /* CMP1[1] */\r
+ _UDWORD INT0_0:1; /* INT0[0] */\r
+ _UDWORD INT0_1:1; /* INT0[1] */\r
+ _UDWORD INT1_0:1; /* INT1[0] */\r
+ _UDWORD INT1_1:1; /* INT1[1] */\r
+ _UDWORD INT2_0:1; /* INT2[0] */\r
+ _UDWORD INT2_1:1; /* INT2[1] */\r
+ _UDWORD INT3_0:1; /* INT3[0] */\r
+ _UDWORD INT3_1:1; /* INT3[1] */\r
+ _UDWORD OSTMI0_0:1; /* OSTMI0[0] */\r
+ _UDWORD OSTMI0_1:1; /* OSTMI0[1] */\r
+ _UDWORD OSTMI1_0:1; /* OSTMI1[0] */\r
+ _UDWORD OSTMI1_1:1; /* OSTMI1[1] */\r
+ _UDWORD CMI_0:1; /* CMI[0] */\r
+ _UDWORD CMI_1:1; /* CMI[1] */\r
+ _UDWORD WTOUT_0:1; /* WTOUT[0] */\r
+ _UDWORD WTOUT_1:1; /* WTOUT[1] */\r
+ _UDWORD ITI_0:1; /* ITI[0] */\r
+ _UDWORD ITI_1:1; /* ITI[1] */\r
+ _UDWORD TGI0A_0:1; /* TGI0A[0] */\r
+ _UDWORD TGI0A_1:1; /* TGI0A[1] */\r
+ _UDWORD TGI0B_0:1; /* TGI0B[0] */\r
+ _UDWORD TGI0B_1:1; /* TGI0B[1] */\r
+ _UDWORD TGI0C_0:1; /* TGI0C[0] */\r
+ _UDWORD TGI0C_1:1; /* TGI0C[1] */\r
+ _UDWORD TGI0D_0:1; /* TGI0D[0] */\r
+ _UDWORD TGI0D_1:1; /* TGI0D[1] */\r
+ _UDWORD TGI0V_0:1; /* TGI0V[0] */\r
+ _UDWORD TGI0V_1:1; /* TGI0V[1] */\r
+ } BIT; /* */\r
+ } ICDICFR8; /* */\r
+ union { /* ICDICFR9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TGI0E_0:1; /* TGI0E[0] */\r
+ _UDWORD TGI0E_1:1; /* TGI0E[1] */\r
+ _UDWORD TGI0F_0:1; /* TGI0F[0] */\r
+ _UDWORD TGI0F_1:1; /* TGI0F[1] */\r
+ _UDWORD TGI1A_0:1; /* TGI1A[0] */\r
+ _UDWORD TGI1A_1:1; /* TGI1A[1] */\r
+ _UDWORD TGI1B_0:1; /* TGI1B[0] */\r
+ _UDWORD TGI1B_1:1; /* TGI1B[1] */\r
+ _UDWORD TGI1V_0:1; /* TGI1V[0] */\r
+ _UDWORD TGI1V_1:1; /* TGI1V[1] */\r
+ _UDWORD TGI1U_0:1; /* TGI1U[0] */\r
+ _UDWORD TGI1U_1:1; /* TGI1U[1] */\r
+ _UDWORD TGI2A_0:1; /* TGI2A[0] */\r
+ _UDWORD TGI2A_1:1; /* TGI2A[1] */\r
+ _UDWORD TGI2B_0:1; /* TGI2B[0] */\r
+ _UDWORD TGI2B_1:1; /* TGI2B[1] */\r
+ _UDWORD TGI2V_0:1; /* TGI2V[0] */\r
+ _UDWORD TGI2V_1:1; /* TGI2V[1] */\r
+ _UDWORD TGI2U_0:1; /* TGI2U[0] */\r
+ _UDWORD TGI2U_1:1; /* TGI2U[1] */\r
+ _UDWORD TGI3A_0:1; /* TGI3A[0] */\r
+ _UDWORD TGI3A_1:1; /* TGI3A[1] */\r
+ _UDWORD TGI3B_0:1; /* TGI3B[0] */\r
+ _UDWORD TGI3B_1:1; /* TGI3B[1] */\r
+ _UDWORD TGI3C_0:1; /* TGI3C[0] */\r
+ _UDWORD TGI3C_1:1; /* TGI3C[1] */\r
+ _UDWORD TGI3D_0:1; /* TGI3D[0] */\r
+ _UDWORD TGI3D_1:1; /* TGI3D[1] */\r
+ _UDWORD TGI3V_0:1; /* TGI3V[0] */\r
+ _UDWORD TGI3V_1:1; /* TGI3V[1] */\r
+ _UDWORD TGI4A_0:1; /* TGI4A[0] */\r
+ _UDWORD TGI4A_1:1; /* TGI4A[1] */\r
+ } BIT; /* */\r
+ } ICDICFR9; /* */\r
+ union { /* ICDICFR10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TGI4B_0:1; /* TGI4B[0] */\r
+ _UDWORD TGI4B_1:1; /* TGI4B[1] */\r
+ _UDWORD TGI4C_0:1; /* TGI4C[0] */\r
+ _UDWORD TGI4C_1:1; /* TGI4C[1] */\r
+ _UDWORD TGI4D_0:1; /* TGI4D[0] */\r
+ _UDWORD TGI4D_1:1; /* TGI4D[1] */\r
+ _UDWORD TGI4V_0:1; /* TGI4V[0] */\r
+ _UDWORD TGI4V_1:1; /* TGI4V[1] */\r
+ _UDWORD CMI1_0:1; /* CMI1[0] */\r
+ _UDWORD CMI1_1:1; /* CMI1[1] */\r
+ _UDWORD CMI2_0:1; /* CMI2[0] */\r
+ _UDWORD CMI2_1:1; /* CMI2[1] */\r
+ _UDWORD SGDEI0_0:1; /* SGDEI0[0] */\r
+ _UDWORD SGDEI0_1:1; /* SGDEI0[1] */\r
+ _UDWORD SGDEI1_0:1; /* SGDEI1[0] */\r
+ _UDWORD SGDEI1_1:1; /* SGDEI1[1] */\r
+ _UDWORD SGDEI2_0:1; /* SGDEI2[0] */\r
+ _UDWORD SGDEI2_1:1; /* SGDEI2[1] */\r
+ _UDWORD SGDEI3_0:1; /* SGDEI3[0] */\r
+ _UDWORD SGDEI3_1:1; /* SGDEI3[1] */\r
+ _UDWORD ADI_0:1; /* ADI[0] */\r
+ _UDWORD ADI_1:1; /* ADI[1] */\r
+ _UDWORD ADWAR_0:1; /* ADWAR[0] */\r
+ _UDWORD ADWAR_1:1; /* ADWAR[1] */\r
+ _UDWORD SSII0_0:1; /* SSII0[0] */\r
+ _UDWORD SSII0_1:1; /* SSII0[1] */\r
+ _UDWORD SSIRXI0_0:1; /* SSIRXI0[0] */\r
+ _UDWORD SSIRXI0_1:1; /* SSIRXI0[1] */\r
+ _UDWORD SSITXI0_0:1; /* SSITXI0[0] */\r
+ _UDWORD SSITXI0_1:1; /* SSITXI0[1] */\r
+ _UDWORD SSII1_0:1; /* SSII1[0] */\r
+ _UDWORD SSII1_1:1; /* SSII1[1] */\r
+ } BIT; /* */\r
+ } ICDICFR10; /* */\r
+ union { /* ICDICFR11 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SSIRXI1_0:1; /* SSIRXI1[0] */\r
+ _UDWORD SSIRXI1_1:1; /* SSIRXI1[1] */\r
+ _UDWORD SSITXI1_0:1; /* SSITXI1[0] */\r
+ _UDWORD SSITXI1_1:1; /* SSITXI1[1] */\r
+ _UDWORD SSII2_0:1; /* SSII2[0] */\r
+ _UDWORD SSII2_1:1; /* SSII2[1] */\r
+ _UDWORD SSIRTI2_0:1; /* SSIRTI2[0] */\r
+ _UDWORD SSIRTI2_1:1; /* SSIRTI2[1] */\r
+ _UDWORD SSII3_0:1; /* SSII3[0] */\r
+ _UDWORD SSII3_1:1; /* SSII3[1] */\r
+ _UDWORD SSIRXI3_0:1; /* SSIRXI3[0] */\r
+ _UDWORD SSIRXI3_1:1; /* SSIRXI3[1] */\r
+ _UDWORD SSITXI3_0:1; /* SSITXI3[0] */\r
+ _UDWORD SSITXI3_1:1; /* SSITXI3[1] */\r
+ _UDWORD SSII4_0:1; /* SSII4[0] */\r
+ _UDWORD SSII4_1:1; /* SSII4[1] */\r
+ _UDWORD SSIRTI4_0:1; /* SSIRTI4[0] */\r
+ _UDWORD SSIRTI4_1:1; /* SSIRTI4[1] */\r
+ _UDWORD SSII5_0:1; /* SSII5[0] */\r
+ _UDWORD SSII5_1:1; /* SSII5[1] */\r
+ _UDWORD SSIRXI5_0:1; /* SSIRXI5[0] */\r
+ _UDWORD SSIRXI5_1:1; /* SSIRXI5[1] */\r
+ _UDWORD SSITXI5_0:1; /* SSITXI5[0] */\r
+ _UDWORD SSITXI5_1:1; /* SSITXI5[1] */\r
+ _UDWORD SPDIFI_0:1; /* SPDIFI[0] */\r
+ _UDWORD SPDIFI_1:1; /* SPDIFI[1] */\r
+ _UDWORD TEI0_0:1; /* TEI0[0] */\r
+ _UDWORD TEI0_1:1; /* TEI0[1] */\r
+ _UDWORD RI0_0:1; /* RI0[0] */\r
+ _UDWORD RI0_1:1; /* RI0[1] */\r
+ _UDWORD TI0_0:1; /* TI0[0] */\r
+ _UDWORD TI0_1:1; /* TI0[1] */\r
+ } BIT; /* */\r
+ } ICDICFR11; /* */\r
+ union { /* ICDICFR12 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPI0_0:1; /* SPI0[0] */\r
+ _UDWORD SPI0_1:1; /* SPI0[1] */\r
+ _UDWORD STI0_0:1; /* STI0[0] */\r
+ _UDWORD STI0_1:1; /* STI0[1] */\r
+ _UDWORD NAKI0_0:1; /* NAKI0[0] */\r
+ _UDWORD NAKI0_1:1; /* NAKI0[1] */\r
+ _UDWORD ALI0_0:1; /* ALI0[0] */\r
+ _UDWORD ALI0_1:1; /* ALI0[1] */\r
+ _UDWORD TMOI0_0:1; /* TMOI0[0] */\r
+ _UDWORD TMOI0_1:1; /* TMOI0[1] */\r
+ _UDWORD TEI1_0:1; /* TEI1[0] */\r
+ _UDWORD TEI1_1:1; /* TEI1[1] */\r
+ _UDWORD RI1_0:1; /* RI1[0] */\r
+ _UDWORD RI1_1:1; /* RI1[1] */\r
+ _UDWORD TI1_0:1; /* TI1[0] */\r
+ _UDWORD TI1_1:1; /* TI1[1] */\r
+ _UDWORD SPI1_0:1; /* SPI1[0] */\r
+ _UDWORD SPI1_1:1; /* SPI1[1] */\r
+ _UDWORD STI1_0:1; /* STI1[0] */\r
+ _UDWORD STI1_1:1; /* STI1[1] */\r
+ _UDWORD NAKI1_0:1; /* NAKI1[0] */\r
+ _UDWORD NAKI1_1:1; /* NAKI1[1] */\r
+ _UDWORD ALI1_0:1; /* ALI1[0] */\r
+ _UDWORD ALI1_1:1; /* ALI1[1] */\r
+ _UDWORD TMOI1_0:1; /* TMOI1[0] */\r
+ _UDWORD TMOI1_1:1; /* TMOI1[1] */\r
+ _UDWORD TEI2_0:1; /* TEI2[0] */\r
+ _UDWORD TEI2_1:1; /* TEI2[1] */\r
+ _UDWORD RI2_0:1; /* RI2[0] */\r
+ _UDWORD RI2_1:1; /* RI2[1] */\r
+ _UDWORD TI2_0:1; /* TI2[0] */\r
+ _UDWORD TI2_1:1; /* TI2[1] */\r
+ } BIT; /* */\r
+ } ICDICFR12; /* */\r
+ union { /* ICDICFR13 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPI2_0:1; /* SPI2[0] */\r
+ _UDWORD SPI2_1:1; /* SPI2[1] */\r
+ _UDWORD STI2_0:1; /* STI2[0] */\r
+ _UDWORD STI2_1:1; /* STI2[1] */\r
+ _UDWORD NAKI2_0:1; /* NAKI2[0] */\r
+ _UDWORD NAKI2_1:1; /* NAKI2[1] */\r
+ _UDWORD ALI2_0:1; /* ALI2[0] */\r
+ _UDWORD ALI2_1:1; /* ALI2[1] */\r
+ _UDWORD TMOI2_0:1; /* TMOI2[0] */\r
+ _UDWORD TMOI2_1:1; /* TMOI2[1] */\r
+ _UDWORD TEI3_0:1; /* TEI3[0] */\r
+ _UDWORD TEI3_1:1; /* TEI3[1] */\r
+ _UDWORD RI3_0:1; /* RI3[0] */\r
+ _UDWORD RI3_1:1; /* RI3[1] */\r
+ _UDWORD TI3_0:1; /* TI3[0] */\r
+ _UDWORD TI3_1:1; /* TI3[1] */\r
+ _UDWORD SPI3_0:1; /* SPI3[0] */\r
+ _UDWORD SPI3_1:1; /* SPI3[1] */\r
+ _UDWORD STI3_0:1; /* STI3[0] */\r
+ _UDWORD STI3_1:1; /* STI3[1] */\r
+ _UDWORD NAKI3_0:1; /* NAKI3[0] */\r
+ _UDWORD NAKI3_1:1; /* NAKI3[1] */\r
+ _UDWORD ALI3_0:1; /* ALI3[0] */\r
+ _UDWORD ALI3_1:1; /* ALI3[1] */\r
+ _UDWORD TMOI3_0:1; /* TMOI3[0] */\r
+ _UDWORD TMOI3_1:1; /* TMOI3[1] */\r
+ _UDWORD BRI0_0:1; /* BRI0[0] */\r
+ _UDWORD BRI0_1:1; /* BRI0[1] */\r
+ _UDWORD ERI0_0:1; /* ERI0[0] */\r
+ _UDWORD ERI0_1:1; /* ERI0[1] */\r
+ _UDWORD RXI0_0:1; /* RXI0[0] */\r
+ _UDWORD RXI0_1:1; /* RXI0[1] */\r
+ } BIT; /* */\r
+ } ICDICFR13; /* */\r
+ union { /* ICDICFR14 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI0_0:1; /* TXI0[0] */\r
+ _UDWORD TXI0_1:1; /* TXI0[1] */\r
+ _UDWORD BRI1_0:1; /* BRI1[0] */\r
+ _UDWORD BRI1_1:1; /* BRI1[1] */\r
+ _UDWORD ERI1_0:1; /* ERI1[0] */\r
+ _UDWORD ERI1_1:1; /* ERI1[1] */\r
+ _UDWORD RXI1_0:1; /* RXI1[0] */\r
+ _UDWORD RXI1_1:1; /* RXI1[1] */\r
+ _UDWORD TXI1_0:1; /* TXI1[0] */\r
+ _UDWORD TXI1_1:1; /* TXI1[1] */\r
+ _UDWORD BRI2_0:1; /* BRI2[0] */\r
+ _UDWORD BRI2_1:1; /* BRI2[1] */\r
+ _UDWORD ERI2_0:1; /* ERI2[0] */\r
+ _UDWORD ERI2_1:1; /* ERI2[1] */\r
+ _UDWORD RXI2_0:1; /* RXI2[0] */\r
+ _UDWORD RXI2_1:1; /* RXI2[1] */\r
+ _UDWORD TXI2_0:1; /* TXI2[0] */\r
+ _UDWORD TXI2_1:1; /* TXI2[1] */\r
+ _UDWORD BRI3_0:1; /* BRI3[0] */\r
+ _UDWORD BRI3_1:1; /* BRI3[1] */\r
+ _UDWORD ERI3_0:1; /* ERI3[0] */\r
+ _UDWORD ERI3_1:1; /* ERI3[1] */\r
+ _UDWORD RXI3_0:1; /* RXI3[0] */\r
+ _UDWORD RXI3_1:1; /* RXI3[1] */\r
+ _UDWORD TXI3_0:1; /* TXI3[0] */\r
+ _UDWORD TXI3_1:1; /* TXI3[1] */\r
+ _UDWORD BRI4_0:1; /* BRI4[0] */\r
+ _UDWORD BRI4_1:1; /* BRI4[1] */\r
+ _UDWORD ERI4_0:1; /* ERI4[0] */\r
+ _UDWORD ERI4_1:1; /* ERI4[1] */\r
+ _UDWORD RXI4_0:1; /* RXI4[0] */\r
+ _UDWORD RXI4_1:1; /* RXI4[1] */\r
+ } BIT; /* */\r
+ } ICDICFR14; /* */\r
+ union { /* ICDICFR15 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TXI4_0:1; /* TXI4[0] */\r
+ _UDWORD TXI4_1:1; /* TXI4[1] */\r
+ _UDWORD BRI5_0:1; /* BRI5[0] */\r
+ _UDWORD BRI5_1:1; /* BRI5[1] */\r
+ _UDWORD ERI5_0:1; /* ERI5[0] */\r
+ _UDWORD ERI5_1:1; /* ERI5[1] */\r
+ _UDWORD RXI5_0:1; /* RXI5[0] */\r
+ _UDWORD RXI5_1:1; /* RXI5[1] */\r
+ _UDWORD TXI5_0:1; /* TXI5[0] */\r
+ _UDWORD TXI5_1:1; /* TXI5[1] */\r
+ _UDWORD BRI6_0:1; /* BRI6[0] */\r
+ _UDWORD BRI6_1:1; /* BRI6[1] */\r
+ _UDWORD ERI6_0:1; /* ERI6[0] */\r
+ _UDWORD ERI6_1:1; /* ERI6[1] */\r
+ _UDWORD RXI6_0:1; /* RXI6[0] */\r
+ _UDWORD RXI6_1:1; /* RXI6[1] */\r
+ _UDWORD TXI6_0:1; /* TXI6[0] */\r
+ _UDWORD TXI6_1:1; /* TXI6[1] */\r
+ _UDWORD BRI7_0:1; /* BRI7[0] */\r
+ _UDWORD BRI7_1:1; /* BRI7[1] */\r
+ _UDWORD ERI7_0:1; /* ERI7[0] */\r
+ _UDWORD ERI7_1:1; /* ERI7[1] */\r
+ _UDWORD RXI7_0:1; /* RXI7[0] */\r
+ _UDWORD RXI7_1:1; /* RXI7[1] */\r
+ _UDWORD TXI7_0:1; /* TXI7[0] */\r
+ _UDWORD TXI7_1:1; /* TXI7[1] */\r
+ _UDWORD GERI_0:1; /* GERI[0] */\r
+ _UDWORD GERI_1:1; /* GERI[1] */\r
+ _UDWORD RFI_0:1; /* RFI[0] */\r
+ _UDWORD RFI_1:1; /* RFI[1] */\r
+ _UDWORD CFRXI0_0:1; /* CFRXI0[0] */\r
+ _UDWORD CFRXI0_1:1; /* CFRXI0[1] */\r
+ } BIT; /* */\r
+ } ICDICFR15; /* */\r
+ union { /* ICDICFR16 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CERI0_0:1; /* CERI0[0] */\r
+ _UDWORD CERI0_1:1; /* CERI0[1] */\r
+ _UDWORD CTXI0_0:1; /* CTXI0[0] */\r
+ _UDWORD CTXI0_1:1; /* CTXI0[1] */\r
+ _UDWORD CFRXI1_0:1; /* CFRXI1[0] */\r
+ _UDWORD CFRXI1_1:1; /* CFRXI1[1] */\r
+ _UDWORD CERI1_0:1; /* CERI1[0] */\r
+ _UDWORD CERI1_1:1; /* CERI1[1] */\r
+ _UDWORD CTXI1_0:1; /* CTXI1[0] */\r
+ _UDWORD CTXI1_1:1; /* CTXI1[1] */\r
+ _UDWORD CFRXI2_0:1; /* CFRXI2[0] */\r
+ _UDWORD CFRXI2_1:1; /* CFRXI2[1] */\r
+ _UDWORD CERI2_0:1; /* CERI2[0] */\r
+ _UDWORD CERI2_1:1; /* CERI2[1] */\r
+ _UDWORD CTXI2_0:1; /* CTXI2[0] */\r
+ _UDWORD CTXI2_1:1; /* CTXI2[1] */\r
+ _UDWORD CFRXI3_0:1; /* CFRXI3[0] */\r
+ _UDWORD CFRXI3_1:1; /* CFRXI3[1] */\r
+ _UDWORD CERI3_0:1; /* CERI3[0] */\r
+ _UDWORD CERI3_1:1; /* CERI3[1] */\r
+ _UDWORD CTXI3_0:1; /* CTXI3[0] */\r
+ _UDWORD CTXI3_1:1; /* CTXI3[1] */\r
+ _UDWORD CFRXI4_0:1; /* CFRXI4[0] */\r
+ _UDWORD CFRXI4_1:1; /* CFRXI4[1] */\r
+ _UDWORD CERI4_0:1; /* CERI4[0] */\r
+ _UDWORD CERI4_1:1; /* CERI4[1] */\r
+ _UDWORD CTXI4_0:1; /* CTXI4[0] */\r
+ _UDWORD CTXI4_1:1; /* CTXI4[1] */\r
+ _UDWORD SPEI0_0:1; /* SPEI0[0] */\r
+ _UDWORD SPEI0_1:1; /* SPEI0[1] */\r
+ _UDWORD SPRI0_0:1; /* SPRI0[0] */\r
+ _UDWORD SPRI0_1:1; /* SPRI0[1] */\r
+ } BIT; /* */\r
+ } ICDICFR16; /* */\r
+ union { /* ICDICFR17 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPTI0_0:1; /* SPTI0[0] */\r
+ _UDWORD SPTI0_1:1; /* SPTI0[1] */\r
+ _UDWORD SPEI1_0:1; /* SPEI1[0] */\r
+ _UDWORD SPEI1_1:1; /* SPEI1[1] */\r
+ _UDWORD SPRI1_0:1; /* SPRI1[0] */\r
+ _UDWORD SPRI1_1:1; /* SPRI1[1] */\r
+ _UDWORD SPTI1_0:1; /* SPTI1[0] */\r
+ _UDWORD SPTI1_1:1; /* SPTI1[1] */\r
+ _UDWORD SPEI2_0:1; /* SPEI2[0] */\r
+ _UDWORD SPEI2_1:1; /* SPEI2[1] */\r
+ _UDWORD SPRI2_0:1; /* SPRI2[0] */\r
+ _UDWORD SPRI2_1:1; /* SPRI2[1] */\r
+ _UDWORD SPTI2_0:1; /* SPTI2[0] */\r
+ _UDWORD SPTI2_1:1; /* SPTI2[1] */\r
+ _UDWORD SPEI3_0:1; /* SPEI3[0] */\r
+ _UDWORD SPEI3_1:1; /* SPEI3[1] */\r
+ _UDWORD SPRI3_0:1; /* SPRI3[0] */\r
+ _UDWORD SPRI3_1:1; /* SPRI3[1] */\r
+ _UDWORD SPTI3_0:1; /* SPTI3[0] */\r
+ _UDWORD SPTI3_1:1; /* SPTI3[1] */\r
+ _UDWORD SPEI4_0:1; /* SPEI4[0] */\r
+ _UDWORD SPEI4_1:1; /* SPEI4[1] */\r
+ _UDWORD SPRI4_0:1; /* SPRI4[0] */\r
+ _UDWORD SPRI4_1:1; /* SPRI4[1] */\r
+ _UDWORD SPTI4_0:1; /* SPTI4[0] */\r
+ _UDWORD SPTI4_1:1; /* SPTI4[1] */\r
+ _UDWORD IEBBTD_0:1; /* IEBBTD[0] */\r
+ _UDWORD IEBBTD_1:1; /* IEBBTD[1] */\r
+ _UDWORD IEBBTERR_0:1; /* IEBBTERR[0] */\r
+ _UDWORD IEBBTERR_1:1; /* IEBBTERR[1] */\r
+ _UDWORD IEBBTSTA_0:1; /* IEBBTSTA[0] */\r
+ _UDWORD IEBBTSTA_1:1; /* IEBBTSTA[1] */\r
+ } BIT; /* */\r
+ } ICDICFR17; /* */\r
+ union { /* ICDICFR18 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IEBBTV_0:1; /* IEBBTV[0] */\r
+ _UDWORD IEBBTV_1:1; /* IEBBTV[1] */\r
+ _UDWORD ISY_0:1; /* ISY[0] */\r
+ _UDWORD ISY_1:1; /* ISY[1] */\r
+ _UDWORD IERR_0:1; /* IERR[0] */\r
+ _UDWORD IERR_1:1; /* IERR[1] */\r
+ _UDWORD ITARG_0:1; /* ITARG[0] */\r
+ _UDWORD ITARG_1:1; /* ITARG[1] */\r
+ _UDWORD ISEC_0:1; /* ISEC[0] */\r
+ _UDWORD ISEC_1:1; /* ISEC[1] */\r
+ _UDWORD IBUF_0:1; /* IBUF[0] */\r
+ _UDWORD IBUF_1:1; /* IBUF[1] */\r
+ _UDWORD IREADY_0:1; /* IREADY[0] */\r
+ _UDWORD IREADY_1:1; /* IREADY[1] */\r
+ _UDWORD FLSTE_0:1; /* FLSTE[0] */\r
+ _UDWORD FLSTE_1:1; /* FLSTE[1] */\r
+ _UDWORD FLTENDI_0:1; /* FLTENDI[0] */\r
+ _UDWORD FLTENDI_1:1; /* FLTENDI[1] */\r
+ _UDWORD FLTREQ0I_0:1; /* FLTREQ0I[0] */\r
+ _UDWORD FLTREQ0I_1:1; /* FLTREQ0I[1] */\r
+ _UDWORD FLTREQ1I_0:1; /* FLTREQ1I[0] */\r
+ _UDWORD FLTREQ1I_1:1; /* FLTREQ1I[1] */\r
+ _UDWORD MMC0_0:1; /* MMC0[0] */\r
+ _UDWORD MMC0_1:1; /* MMC0[1] */\r
+ _UDWORD MMC1_0:1; /* MMC1[0] */\r
+ _UDWORD MMC1_1:1; /* MMC1[1] */\r
+ _UDWORD MMC2_0:1; /* MMC2[0] */\r
+ _UDWORD MMC2_1:1; /* MMC2[1] */\r
+ _UDWORD SDHI0_3_0:1; /* SDHI0_3[0] */\r
+ _UDWORD SDHI0_3_1:1; /* SDHI0_3[1] */\r
+ _UDWORD SDHI0_0_0:1; /* SDHI0_0[0] */\r
+ _UDWORD SDHI0_0_1:1; /* SDHI0_0[1] */\r
+ } BIT; /* */\r
+ } ICDICFR18; /* */\r
+ union { /* ICDICFR19 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SDHI0_1_0:1; /* SDHI0_1[0] */\r
+ _UDWORD SDHI0_1_1:1; /* SDHI0_1[1] */\r
+ _UDWORD SDHI1_3_0:1; /* SDHI1_3[0] */\r
+ _UDWORD SDHI1_3_1:1; /* SDHI1_3[1] */\r
+ _UDWORD SDHI1_0_0:1; /* SDHI1_0[0] */\r
+ _UDWORD SDHI1_0_1:1; /* SDHI1_0[1] */\r
+ _UDWORD SDHI1_1_0:1; /* SDHI1_1[0] */\r
+ _UDWORD SDHI1_1_1:1; /* SDHI1_1[1] */\r
+ _UDWORD ARM_0:1; /* ARM[0] */\r
+ _UDWORD ARM_1:1; /* ARM[1] */\r
+ _UDWORD PRD_0:1; /* PRD[0] */\r
+ _UDWORD PRD_1:1; /* PRD[1] */\r
+ _UDWORD CUP_0:1; /* CUP[0] */\r
+ _UDWORD CUP_1:1; /* CUP[1] */\r
+ _UDWORD SCUAI0_0:1; /* SCUAI0[0] */\r
+ _UDWORD SCUAI0_1:1; /* SCUAI0[1] */\r
+ _UDWORD SCUAI1_0:1; /* SCUAI1[0] */\r
+ _UDWORD SCUAI1_1:1; /* SCUAI1[1] */\r
+ _UDWORD SCUFDI0_0:1; /* SCUFDI0[0] */\r
+ _UDWORD SCUFDI0_1:1; /* SCUFDI0[1] */\r
+ _UDWORD SCUFDI1_0:1; /* SCUFDI1[0] */\r
+ _UDWORD SCUFDI1_1:1; /* SCUFDI1[1] */\r
+ _UDWORD SCUFDI2_0:1; /* SCUFDI2[0] */\r
+ _UDWORD SCUFDI2_1:1; /* SCUFDI2[1] */\r
+ _UDWORD SCUFDI3_0:1; /* SCUFDI3[0] */\r
+ _UDWORD SCUFDI3_1:1; /* SCUFDI3[1] */\r
+ _UDWORD SCUFUI0_0:1; /* SCUFUI0[0] */\r
+ _UDWORD SCUFUI0_1:1; /* SCUFUI0[1] */\r
+ _UDWORD SCUFUI1_0:1; /* SCUFUI1[0] */\r
+ _UDWORD SCUFUI1_1:1; /* SCUFUI1[1] */\r
+ _UDWORD SCUFUI2_0:1; /* SCUFUI2[0] */\r
+ _UDWORD SCUFUI2_1:1; /* SCUFUI2[1] */\r
+ } BIT; /* */\r
+ } ICDICFR19; /* */\r
+ union { /* ICDICFR20 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SCUFUI3_0:1; /* SCUFUI3[0] */\r
+ _UDWORD SCUFUI3_1:1; /* SCUFUI3[1] */\r
+ _UDWORD SCUDVI0_0:1; /* SCUDVI0[0] */\r
+ _UDWORD SCUDVI0_1:1; /* SCUDVI0[1] */\r
+ _UDWORD SCUDVI1_0:1; /* SCUDVI1[0] */\r
+ _UDWORD SCUDVI1_1:1; /* SCUDVI1[1] */\r
+ _UDWORD SCUDVI2_0:1; /* SCUDVI2[0] */\r
+ _UDWORD SCUDVI2_1:1; /* SCUDVI2[1] */\r
+ _UDWORD SCUDVI3_0:1; /* SCUDVI3[0] */\r
+ _UDWORD SCUDVI3_1:1; /* SCUDVI3[1] */\r
+ _UDWORD MLBCI_0:1; /* MLBCI[0] */\r
+ _UDWORD MLBCI_1:1; /* MLBCI[1] */\r
+ _UDWORD MLBSI_0:1; /* MLBSI[0] */\r
+ _UDWORD MLBSI_1:1; /* MLBSI[1] */\r
+ _UDWORD DRC0_0:1; /* DRC0[0] */\r
+ _UDWORD DRC0_1:1; /* DRC0[1] */\r
+ _UDWORD DRC1_0:1; /* DRC1[0] */\r
+ _UDWORD DRC1_1:1; /* DRC1[1] */\r
+ _UDWORD :4; /* */\r
+ _UDWORD LINI0_INT_T_0:1;/* LINI0_INT_T[0] */\r
+ _UDWORD LINI0_INT_T_1:1;/* LINI0_INT_T[1] */\r
+ _UDWORD LINI0_INT_R_0:1;/* LINI0_INT_R[0] */\r
+ _UDWORD LINI0_INT_R_1:1;/* LINI0_INT_R[1] */\r
+ _UDWORD LINI0_INT_S_0:1;/* LINI0_INT_S[0] */\r
+ _UDWORD LINI0_INT_S_1:1;/* LINI0_INT_S[1] */\r
+ _UDWORD LINI0_INT_M_0:1;/* LINI0_INT_M[0] */\r
+ _UDWORD LINI0_INT_M_1:1;/* LINI0_INT_M[1] */\r
+ _UDWORD LINI1_INT_T_0:1;/* LINI1_INT_T[0] */\r
+ _UDWORD LINI1_INT_T_1:1;/* LINI1_INT_T[1] */\r
+ } BIT; /* */\r
+ } ICDICFR20; /* */\r
+ union { /* ICDICFR21 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD LINI1_INT_R_0:1;/* LINI1_INT_R[0] */\r
+ _UDWORD LINI1_INT_R_1:1;/* LINI1_INT_R[1] */\r
+ _UDWORD LINI1_INT_S_0:1;/* LINI1_INT_S[0] */\r
+ _UDWORD LINI1_INT_S_1:1;/* LINI1_INT_S[1] */\r
+ _UDWORD LINI1_INT_M_0:1;/* LINI1_INT_M[0] */\r
+ _UDWORD LINI1_INT_M_1:1;/* LINI1_INT_M[1] */\r
+ _UDWORD :16; /* */\r
+ _UDWORD ERI0_0:1; /* ERI0[0] */\r
+ _UDWORD ERI0_1:1; /* ERI0[1] */\r
+ _UDWORD RXI0_0:1; /* RXI0[0] */\r
+ _UDWORD RXI0_1:1; /* RXI0[1] */\r
+ _UDWORD TXI0_0:1; /* TXI0[0] */\r
+ _UDWORD TXI0_1:1; /* TXI0[1] */\r
+ _UDWORD TEI0_0:1; /* TEI0[0] */\r
+ _UDWORD TEI0_1:1; /* TEI0[1] */\r
+ _UDWORD ERI1_0:1; /* ERI1[0] */\r
+ _UDWORD ERI1_1:1; /* ERI1[1] */\r
+ } BIT; /* */\r
+ } ICDICFR21; /* */\r
+ union { /* ICDICFR22 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD RXI1_0:1; /* RXI1[0] */\r
+ _UDWORD RXI1_1:1; /* RXI1[1] */\r
+ _UDWORD TXI1_0:1; /* TXI1[0] */\r
+ _UDWORD TXI1_1:1; /* TXI1[1] */\r
+ _UDWORD TEI1_0:1; /* TEI1[0] */\r
+ _UDWORD TEI1_1:1; /* TEI1[1] */\r
+ _UDWORD :8; /* */\r
+ _UDWORD ETHERI_0:1; /* ETHERI[0] */\r
+ _UDWORD ETHERI_1:1; /* ETHERI[1] */\r
+ _UDWORD :8; /* */\r
+ _UDWORD CEUI_0:1; /* CEUI[0] */\r
+ _UDWORD CEUI_1:1; /* CEUI[1] */\r
+ _UDWORD INT_CSIH0TIR_0:1;/* INT_CSIH0TIR[0] */\r
+ _UDWORD INT_CSIH0TIR_1:1;/* INT_CSIH0TIR[1] */\r
+ _UDWORD INT_CSIH0TIRE_0:1;/* INT_CSIH0TIRE[0] */\r
+ _UDWORD INT_CSIH0TIRE_1:1;/* INT_CSIH0TIRE[1] */\r
+ _UDWORD INT_CSIH1TIC_0:1;/* INT_CSIH1TIC[0] */\r
+ _UDWORD INT_CSIH1TIC_1:1;/* INT_CSIH1TIC[1] */\r
+ } BIT; /* */\r
+ } ICDICFR22; /* */\r
+ union { /* ICDICFR23 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD INT_CSIH1TIJC_0:1;/* INT_CSIH1TIJC[0] */\r
+ _UDWORD INT_CSIH1TIJC_1:1;/* INT_CSIH1TIJC[1] */\r
+ _UDWORD ECCE10_0:1; /* ECCE10[0] */\r
+ _UDWORD ECCE10_1:1; /* ECCE10[1] */\r
+ _UDWORD ECCE20_0:1; /* ECCE20[0] */\r
+ _UDWORD ECCE20_1:1; /* ECCE20[1] */\r
+ _UDWORD ECCOVF0_0:1; /* ECCOVF0[0] */\r
+ _UDWORD ECCOVF0_1:1; /* ECCOVF0[1] */\r
+ _UDWORD ECCE11_0:1; /* ECCE11[0] */\r
+ _UDWORD ECCE11_1:1; /* ECCE11[1] */\r
+ _UDWORD ECCE21_0:1; /* ECCE21[0] */\r
+ _UDWORD ECCE21_1:1; /* ECCE21[1] */\r
+ _UDWORD ECCOVF1_0:1; /* ECCOVF1[0] */\r
+ _UDWORD ECCOVF1_1:1; /* ECCOVF1[1] */\r
+ _UDWORD ECCE12_0:1; /* ECCE12[0] */\r
+ _UDWORD ECCE12_1:1; /* ECCE12[1] */\r
+ _UDWORD ECCE22_0:1; /* ECCE22[0] */\r
+ _UDWORD ECCE22_1:1; /* ECCE22[1] */\r
+ _UDWORD ECCOVF2_0:1; /* ECCOVF2[0] */\r
+ _UDWORD ECCOVF2_1:1; /* ECCOVF2[1] */\r
+ _UDWORD ECCE13_0:1; /* ECCE13[0] */\r
+ _UDWORD ECCE13_1:1; /* ECCE13[1] */\r
+ _UDWORD ECCE23_0:1; /* ECCE23[0] */\r
+ _UDWORD ECCE23_1:1; /* ECCE23[1] */\r
+ _UDWORD ECCOVF3_0:1; /* ECCOVF3[0] */\r
+ _UDWORD ECCOVF3_1:1; /* ECCOVF3[1] */\r
+ _UDWORD H2XMLB_ERRINT_0:1;/* H2XMLB_ERRINT[0] */\r
+ _UDWORD H2XMLB_ERRINT_1:1;/* H2XMLB_ERRINT[1] */\r
+ _UDWORD H2XIC1_ERRINT_0:1;/* H2XIC1_ERRINT[0] */\r
+ _UDWORD H2XIC1_ERRINT_1:1;/* H2XIC1_ERRINT[1] */\r
+ _UDWORD X2HPERI1_ERRINT_0:1;/* X2HPERI1_ERRINT[0] */\r
+ _UDWORD X2HPERI1_ERRINT_1:1;/* X2HPERI1_ERRINT[1] */\r
+ } BIT; /* */\r
+ } ICDICFR23; /* */\r
+ union { /* ICDICFR24 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD X2HPERI2_ERRINT_0:1;/* X2HPERI2_ERRINT[0] */\r
+ _UDWORD X2HPERI2_ERRINT_1:1;/* X2HPERI2_ERRINT[1] */\r
+ _UDWORD X2HPERI34_ERRINT_0:1;/* X2HPERI34_ERRINT[0] */\r
+ _UDWORD X2HPERI34_ERRINT_1:1;/* X2HPERI34_ERRINT[1] */\r
+ _UDWORD X2HPERI5_ERRINT_0:1;/* X2HPERI5_ERRINT[0] */\r
+ _UDWORD X2HPERI5_ERRINT_1:1;/* X2HPERI5_ERRINT[1] */\r
+ _UDWORD X2HPERI67_ERRINT_0:1;/* X2HPERI67_ERRINT[0] */\r
+ _UDWORD X2HPERI67_ERRINT_1:1;/* X2HPERI67_ERRINT[1] */\r
+ _UDWORD X2HDBGR_ERRINT_0:1;/* X2HDBGR_ERRINT[0] */\r
+ _UDWORD X2HDBGR_ERRINT_1:1;/* X2HDBGR_ERRINT[1] */\r
+ _UDWORD PRRI_0:1; /* PRRI[0] */\r
+ _UDWORD PRRI_1:1; /* PRRI[1] */\r
+ _UDWORD IFEI0_0:1; /* IFEI0[0] */\r
+ _UDWORD IFEI0_1:1; /* IFEI0[1] */\r
+ _UDWORD OFFI0_0:1; /* OFFI0[0] */\r
+ _UDWORD OFFI0_1:1; /* OFFI0[1] */\r
+ _UDWORD PFVEI0_0:1; /* PFVEI0[0] */\r
+ _UDWORD PFVEI0_1:1; /* PFVEI0[1] */\r
+ _UDWORD IFEI1_0:1; /* IFEI1[0] */\r
+ _UDWORD IFEI1_1:1; /* IFEI1[1] */\r
+ _UDWORD OFFI1_0:1; /* OFFI1[0] */\r
+ _UDWORD OFFI1_1:1; /* OFFI1[1] */\r
+ _UDWORD PFVEI1_0:1; /* PFVEI1[0] */\r
+ _UDWORD PFVEI1_1:1; /* PFVEI1[1] */\r
+ _UDWORD :8; /* */\r
+ } BIT; /* */\r
+ } ICDICFR24; /* */\r
+ union { /* ICDICFR25 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD dummy:32; /* */\r
+ } BIT; /* */\r
+ } ICDICFR25; /* */\r
+ union { /* ICDICFR26 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT0_0:1; /* TINT0[0] */\r
+ _UDWORD TINT0_1:1; /* TINT0[1] */\r
+ _UDWORD TINT1_0:1; /* TINT1[0] */\r
+ _UDWORD TINT1_1:1; /* TINT1[1] */\r
+ _UDWORD TINT2_0:1; /* TINT2[0] */\r
+ _UDWORD TINT2_1:1; /* TINT2[1] */\r
+ _UDWORD TINT3_0:1; /* TINT3[0] */\r
+ _UDWORD TINT3_1:1; /* TINT3[1] */\r
+ _UDWORD TINT4_0:1; /* TINT4[0] */\r
+ _UDWORD TINT4_1:1; /* TINT4[1] */\r
+ _UDWORD TINT5_0:1; /* TINT5[0] */\r
+ _UDWORD TINT5_1:1; /* TINT5[1] */\r
+ _UDWORD TINT6_0:1; /* TINT6[0] */\r
+ _UDWORD TINT6_1:1; /* TINT6[1] */\r
+ _UDWORD TINT7_0:1; /* TINT7[0] */\r
+ _UDWORD TINT7_1:1; /* TINT7[1] */\r
+ _UDWORD TINT8_0:1; /* TINT8[0] */\r
+ _UDWORD TINT8_1:1; /* TINT8[1] */\r
+ _UDWORD TINT9_0:1; /* TINT9[0] */\r
+ _UDWORD TINT9_1:1; /* TINT9[1] */\r
+ _UDWORD TINT10_0:1; /* TINT10[0] */\r
+ _UDWORD TINT10_1:1; /* TINT10[1] */\r
+ _UDWORD TINT11_0:1; /* TINT11[0] */\r
+ _UDWORD TINT11_1:1; /* TINT11[1] */\r
+ _UDWORD TINT12_0:1; /* TINT12[0] */\r
+ _UDWORD TINT12_1:1; /* TINT12[1] */\r
+ _UDWORD TINT13_0:1; /* TINT13[0] */\r
+ _UDWORD TINT13_1:1; /* TINT13[1] */\r
+ _UDWORD TINT14_0:1; /* TINT14[0] */\r
+ _UDWORD TINT14_1:1; /* TINT14[1] */\r
+ _UDWORD TINT15_0:1; /* TINT15[0] */\r
+ _UDWORD TINT15_1:1; /* TINT15[1] */\r
+ } BIT; /* */\r
+ } ICDICFR26; /* */\r
+ union { /* ICDICFR27 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT16_0:1; /* TINT16[0] */\r
+ _UDWORD TINT16_1:1; /* TINT16[1] */\r
+ _UDWORD TINT17_0:1; /* TINT17[0] */\r
+ _UDWORD TINT17_1:1; /* TINT17[1] */\r
+ _UDWORD TINT18_0:1; /* TINT18[0] */\r
+ _UDWORD TINT18_1:1; /* TINT18[1] */\r
+ _UDWORD TINT19_0:1; /* TINT19[0] */\r
+ _UDWORD TINT19_1:1; /* TINT19[1] */\r
+ _UDWORD TINT20_0:1; /* TINT20[0] */\r
+ _UDWORD TINT20_1:1; /* TINT20[1] */\r
+ _UDWORD TINT21_0:1; /* TINT21[0] */\r
+ _UDWORD TINT21_1:1; /* TINT21[1] */\r
+ _UDWORD TINT22_0:1; /* TINT22[0] */\r
+ _UDWORD TINT22_1:1; /* TINT22[1] */\r
+ _UDWORD TINT23_0:1; /* TINT23[0] */\r
+ _UDWORD TINT23_1:1; /* TINT23[1] */\r
+ _UDWORD TINT24_0:1; /* TINT24[0] */\r
+ _UDWORD TINT24_1:1; /* TINT24[1] */\r
+ _UDWORD TINT25_0:1; /* TINT25[0] */\r
+ _UDWORD TINT25_1:1; /* TINT25[1] */\r
+ _UDWORD TINT26_0:1; /* TINT26[0] */\r
+ _UDWORD TINT26_1:1; /* TINT26[1] */\r
+ _UDWORD TINT27_0:1; /* TINT27[0] */\r
+ _UDWORD TINT27_1:1; /* TINT27[1] */\r
+ _UDWORD TINT28_0:1; /* TINT28[0] */\r
+ _UDWORD TINT28_1:1; /* TINT28[1] */\r
+ _UDWORD TINT29_0:1; /* TINT29[0] */\r
+ _UDWORD TINT29_1:1; /* TINT29[1] */\r
+ _UDWORD TINT30_0:1; /* TINT30[0] */\r
+ _UDWORD TINT30_1:1; /* TINT30[1] */\r
+ _UDWORD TINT31_0:1; /* TINT31[0] */\r
+ _UDWORD TINT31_1:1; /* TINT31[1] */\r
+ } BIT; /* */\r
+ } ICDICFR27; /* */\r
+ union { /* ICDICFR28 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT32_0:1; /* TINT32[0] */\r
+ _UDWORD TINT32_1:1; /* TINT32[1] */\r
+ _UDWORD TINT33_0:1; /* TINT33[0] */\r
+ _UDWORD TINT33_1:1; /* TINT33[1] */\r
+ _UDWORD TINT34_0:1; /* TINT34[0] */\r
+ _UDWORD TINT34_1:1; /* TINT34[1] */\r
+ _UDWORD TINT35_0:1; /* TINT35[0] */\r
+ _UDWORD TINT35_1:1; /* TINT35[1] */\r
+ _UDWORD TINT36_0:1; /* TINT36[0] */\r
+ _UDWORD TINT36_1:1; /* TINT36[1] */\r
+ _UDWORD TINT37_0:1; /* TINT37[0] */\r
+ _UDWORD TINT37_1:1; /* TINT37[1] */\r
+ _UDWORD TINT38_0:1; /* TINT38[0] */\r
+ _UDWORD TINT38_1:1; /* TINT38[1] */\r
+ _UDWORD TINT39_0:1; /* TINT39[0] */\r
+ _UDWORD TINT39_1:1; /* TINT39[1] */\r
+ _UDWORD TINT40_0:1; /* TINT40[0] */\r
+ _UDWORD TINT40_1:1; /* TINT40[1] */\r
+ _UDWORD TINT41_0:1; /* TINT41[0] */\r
+ _UDWORD TINT41_1:1; /* TINT41[1] */\r
+ _UDWORD TINT42_0:1; /* TINT42[0] */\r
+ _UDWORD TINT42_1:1; /* TINT42[1] */\r
+ _UDWORD TINT43_0:1; /* TINT43[0] */\r
+ _UDWORD TINT43_1:1; /* TINT43[1] */\r
+ _UDWORD TINT44_0:1; /* TINT44[0] */\r
+ _UDWORD TINT44_1:1; /* TINT44[1] */\r
+ _UDWORD TINT45_0:1; /* TINT45[0] */\r
+ _UDWORD TINT45_1:1; /* TINT45[1] */\r
+ _UDWORD TINT46_0:1; /* TINT46[0] */\r
+ _UDWORD TINT46_1:1; /* TINT46[1] */\r
+ _UDWORD TINT47_0:1; /* TINT47[0] */\r
+ _UDWORD TINT47_1:1; /* TINT47[1] */\r
+ } BIT; /* */\r
+ } ICDICFR28; /* */\r
+ union { /* ICDICFR29 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT48_0:1; /* TINT48[0] */\r
+ _UDWORD TINT48_1:1; /* TINT48[1] */\r
+ _UDWORD TINT49_0:1; /* TINT49[0] */\r
+ _UDWORD TINT49_1:1; /* TINT49[1] */\r
+ _UDWORD TINT50_0:1; /* TINT50[0] */\r
+ _UDWORD TINT50_1:1; /* TINT50[1] */\r
+ _UDWORD TINT51_0:1; /* TINT51[0] */\r
+ _UDWORD TINT51_1:1; /* TINT51[1] */\r
+ _UDWORD TINT52_0:1; /* TINT52[0] */\r
+ _UDWORD TINT52_1:1; /* TINT52[1] */\r
+ _UDWORD TINT53_0:1; /* TINT53[0] */\r
+ _UDWORD TINT53_1:1; /* TINT53[1] */\r
+ _UDWORD TINT54_0:1; /* TINT54[0] */\r
+ _UDWORD TINT54_1:1; /* TINT54[1] */\r
+ _UDWORD TINT55_0:1; /* TINT55[0] */\r
+ _UDWORD TINT55_1:1; /* TINT55[1] */\r
+ _UDWORD TINT56_0:1; /* TINT56[0] */\r
+ _UDWORD TINT56_1:1; /* TINT56[1] */\r
+ _UDWORD TINT57_0:1; /* TINT57[0] */\r
+ _UDWORD TINT57_1:1; /* TINT57[1] */\r
+ _UDWORD TINT58_0:1; /* TINT58[0] */\r
+ _UDWORD TINT58_1:1; /* TINT58[1] */\r
+ _UDWORD TINT59_0:1; /* TINT59[0] */\r
+ _UDWORD TINT59_1:1; /* TINT59[1] */\r
+ _UDWORD TINT60_0:1; /* TINT60[0] */\r
+ _UDWORD TINT60_1:1; /* TINT60[1] */\r
+ _UDWORD TINT61_0:1; /* TINT61[0] */\r
+ _UDWORD TINT61_1:1; /* TINT61[1] */\r
+ _UDWORD TINT62_0:1; /* TINT62[0] */\r
+ _UDWORD TINT62_1:1; /* TINT62[1] */\r
+ _UDWORD TINT63_0:1; /* TINT63[0] */\r
+ _UDWORD TINT63_1:1; /* TINT63[1] */\r
+ } BIT; /* */\r
+ } ICDICFR29; /* */\r
+ union { /* ICDICFR30 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT64_0:1; /* TINT64[0] */\r
+ _UDWORD TINT64_1:1; /* TINT64[1] */\r
+ _UDWORD TINT65_0:1; /* TINT65[0] */\r
+ _UDWORD TINT65_1:1; /* TINT65[1] */\r
+ _UDWORD TINT66_0:1; /* TINT66[0] */\r
+ _UDWORD TINT66_1:1; /* TINT66[1] */\r
+ _UDWORD TINT67_0:1; /* TINT67[0] */\r
+ _UDWORD TINT67_1:1; /* TINT67[1] */\r
+ _UDWORD TINT68_0:1; /* TINT68[0] */\r
+ _UDWORD TINT68_1:1; /* TINT68[1] */\r
+ _UDWORD TINT69_0:1; /* TINT69[0] */\r
+ _UDWORD TINT69_1:1; /* TINT69[1] */\r
+ _UDWORD TINT70_0:1; /* TINT70[0] */\r
+ _UDWORD TINT70_1:1; /* TINT70[1] */\r
+ _UDWORD TINT71_0:1; /* TINT71[0] */\r
+ _UDWORD TINT71_1:1; /* TINT71[1] */\r
+ _UDWORD TINT72_0:1; /* TINT72[0] */\r
+ _UDWORD TINT72_1:1; /* TINT72[1] */\r
+ _UDWORD TINT73_0:1; /* TINT73[0] */\r
+ _UDWORD TINT73_1:1; /* TINT73[1] */\r
+ _UDWORD :12; /* */\r
+ } BIT; /* */\r
+ } ICDICFR30; /* */\r
+ union { /* ICDICFR31 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT80_0:1; /* TINT80[0] */\r
+ _UDWORD TINT80_1:1; /* TINT80[1] */\r
+ _UDWORD TINT81_0:1; /* TINT81[0] */\r
+ _UDWORD TINT81_1:1; /* TINT81[1] */\r
+ _UDWORD TINT82_0:1; /* TINT82[0] */\r
+ _UDWORD TINT82_1:1; /* TINT82[1] */\r
+ _UDWORD TINT83_0:1; /* TINT83[0] */\r
+ _UDWORD TINT83_1:1; /* TINT83[1] */\r
+ _UDWORD TINT84_0:1; /* TINT84[0] */\r
+ _UDWORD TINT84_1:1; /* TINT84[1] */\r
+ _UDWORD TINT85_0:1; /* TINT85[0] */\r
+ _UDWORD TINT85_1:1; /* TINT85[1] */\r
+ _UDWORD TINT86_0:1; /* TINT86[0] */\r
+ _UDWORD TINT86_1:1; /* TINT86[1] */\r
+ _UDWORD TINT87_0:1; /* TINT87[0] */\r
+ _UDWORD TINT87_1:1; /* TINT87[1] */\r
+ _UDWORD TINT88_0:1; /* TINT88[0] */\r
+ _UDWORD TINT88_1:1; /* TINT88[1] */\r
+ _UDWORD TINT89_0:1; /* TINT89[0] */\r
+ _UDWORD TINT89_1:1; /* TINT89[1] */\r
+ _UDWORD TINT90_0:1; /* TINT90[0] */\r
+ _UDWORD TINT90_1:1; /* TINT90[1] */\r
+ _UDWORD TINT91_0:1; /* TINT91[0] */\r
+ _UDWORD TINT91_1:1; /* TINT91[1] */\r
+ _UDWORD TINT92_0:1; /* TINT92[0] */\r
+ _UDWORD TINT92_1:1; /* TINT92[1] */\r
+ _UDWORD TINT93_0:1; /* TINT93[0] */\r
+ _UDWORD TINT93_1:1; /* TINT93[1] */\r
+ _UDWORD TINT94_0:1; /* TINT94[0] */\r
+ _UDWORD TINT94_1:1; /* TINT94[1] */\r
+ _UDWORD TINT95_0:1; /* TINT95[0] */\r
+ _UDWORD TINT95_1:1; /* TINT95[1] */\r
+ } BIT; /* */\r
+ } ICDICFR31; /* */\r
+ union { /* ICDICFR32 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT96_0:1; /* TINT96[0] */\r
+ _UDWORD TINT96_1:1; /* TINT96[1] */\r
+ _UDWORD TINT97_0:1; /* TINT97[0] */\r
+ _UDWORD TINT97_1:1; /* TINT97[1] */\r
+ _UDWORD TINT98_0:1; /* TINT98[0] */\r
+ _UDWORD TINT98_1:1; /* TINT98[1] */\r
+ _UDWORD TINT99_0:1; /* TINT99[0] */\r
+ _UDWORD TINT99_1:1; /* TINT99[1] */\r
+ _UDWORD TINT100_0:1; /* TINT100[0] */\r
+ _UDWORD TINT100_1:1; /* TINT100[1] */\r
+ _UDWORD TINT101_0:1; /* TINT101[0] */\r
+ _UDWORD TINT101_1:1; /* TINT101[1] */\r
+ _UDWORD TINT102_0:1; /* TINT102[0] */\r
+ _UDWORD TINT102_1:1; /* TINT102[1] */\r
+ _UDWORD TINT103_0:1; /* TINT103[0] */\r
+ _UDWORD TINT103_1:1; /* TINT103[1] */\r
+ _UDWORD TINT104_0:1; /* TINT104[0] */\r
+ _UDWORD TINT104_1:1; /* TINT104[1] */\r
+ _UDWORD TINT105_0:1; /* TINT105[0] */\r
+ _UDWORD TINT105_1:1; /* TINT105[1] */\r
+ _UDWORD TINT106_0:1; /* TINT106[0] */\r
+ _UDWORD TINT106_1:1; /* TINT106[1] */\r
+ _UDWORD TINT107_0:1; /* TINT107[0] */\r
+ _UDWORD TINT107_1:1; /* TINT107[1] */\r
+ _UDWORD TINT108_0:1; /* TINT108[0] */\r
+ _UDWORD TINT108_1:1; /* TINT108[1] */\r
+ _UDWORD TINT109_0:1; /* TINT109[0] */\r
+ _UDWORD TINT109_1:1; /* TINT109[1] */\r
+ _UDWORD TINT110_0:1; /* TINT110[0] */\r
+ _UDWORD TINT110_1:1; /* TINT110[1] */\r
+ _UDWORD TINT111_0:1; /* TINT111[0] */\r
+ _UDWORD TINT111_1:1; /* TINT111[1] */\r
+ } BIT; /* */\r
+ } ICDICFR32; /* */\r
+ union { /* ICDICFR33 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT112_0:1; /* TINT112[0] */\r
+ _UDWORD TINT112_1:1; /* TINT112[1] */\r
+ _UDWORD TINT113_0:1; /* TINT113[0] */\r
+ _UDWORD TINT113_1:1; /* TINT113[1] */\r
+ _UDWORD TINT114_0:1; /* TINT114[0] */\r
+ _UDWORD TINT114_1:1; /* TINT114[1] */\r
+ _UDWORD TINT115_0:1; /* TINT115[0] */\r
+ _UDWORD TINT115_1:1; /* TINT115[1] */\r
+ _UDWORD TINT116_0:1; /* TINT116[0] */\r
+ _UDWORD TINT116_1:1; /* TINT116[1] */\r
+ _UDWORD TINT117_0:1; /* TINT117[0] */\r
+ _UDWORD TINT117_1:1; /* TINT117[1] */\r
+ _UDWORD TINT118_0:1; /* TINT118[0] */\r
+ _UDWORD TINT118_1:1; /* TINT118[1] */\r
+ _UDWORD TINT119_0:1; /* TINT119[0] */\r
+ _UDWORD TINT119_1:1; /* TINT119[1] */\r
+ _UDWORD TINT120_0:1; /* TINT120[0] */\r
+ _UDWORD TINT120_1:1; /* TINT120[1] */\r
+ _UDWORD TINT121_0:1; /* TINT121[0] */\r
+ _UDWORD TINT121_1:1; /* TINT121[1] */\r
+ _UDWORD TINT122_0:1; /* TINT122[0] */\r
+ _UDWORD TINT122_1:1; /* TINT122[1] */\r
+ _UDWORD TINT123_0:1; /* TINT123[0] */\r
+ _UDWORD TINT123_1:1; /* TINT123[1] */\r
+ _UDWORD TINT124_0:1; /* TINT124[0] */\r
+ _UDWORD TINT124_1:1; /* TINT124[1] */\r
+ _UDWORD TINT125_0:1; /* TINT125[0] */\r
+ _UDWORD TINT125_1:1; /* TINT125[1] */\r
+ _UDWORD TINT126_0:1; /* TINT126[0] */\r
+ _UDWORD TINT126_1:1; /* TINT126[1] */\r
+ _UDWORD TINT127_0:1; /* TINT127[0] */\r
+ _UDWORD TINT127_1:1; /* TINT127[1] */\r
+ } BIT; /* */\r
+ } ICDICFR33; /* */\r
+ union { /* ICDICFR34 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT128_0:1; /* TINT128[0] */\r
+ _UDWORD TINT128_1:1; /* TINT128[1] */\r
+ _UDWORD TINT129_0:1; /* TINT129[0] */\r
+ _UDWORD TINT129_1:1; /* TINT129[1] */\r
+ _UDWORD TINT130_0:1; /* TINT130[0] */\r
+ _UDWORD TINT130_1:1; /* TINT130[1] */\r
+ _UDWORD TINT131_0:1; /* TINT131[0] */\r
+ _UDWORD TINT131_1:1; /* TINT131[1] */\r
+ _UDWORD TINT132_0:1; /* TINT132[0] */\r
+ _UDWORD TINT132_1:1; /* TINT132[1] */\r
+ _UDWORD TINT133_0:1; /* TINT133[0] */\r
+ _UDWORD TINT133_1:1; /* TINT133[1] */\r
+ _UDWORD TINT134_0:1; /* TINT134[0] */\r
+ _UDWORD TINT134_1:1; /* TINT134[1] */\r
+ _UDWORD TINT135_0:1; /* TINT135[0] */\r
+ _UDWORD TINT135_1:1; /* TINT135[1] */\r
+ _UDWORD TINT136_0:1; /* TINT136[0] */\r
+ _UDWORD TINT136_1:1; /* TINT136[1] */\r
+ _UDWORD TINT137_0:1; /* TINT137[0] */\r
+ _UDWORD TINT137_1:1; /* TINT137[1] */\r
+ _UDWORD TINT138_0:1; /* TINT138[0] */\r
+ _UDWORD TINT138_1:1; /* TINT138[1] */\r
+ _UDWORD TINT139_0:1; /* TINT139[0] */\r
+ _UDWORD TINT139_1:1; /* TINT139[1] */\r
+ _UDWORD TINT140_0:1; /* TINT140[0] */\r
+ _UDWORD TINT140_1:1; /* TINT140[1] */\r
+ _UDWORD TINT141_0:1; /* TINT141[0] */\r
+ _UDWORD TINT141_1:1; /* TINT141[1] */\r
+ _UDWORD TINT142_0:1; /* TINT142[0] */\r
+ _UDWORD TINT142_1:1; /* TINT142[1] */\r
+ _UDWORD TINT143_0:1; /* TINT143[0] */\r
+ _UDWORD TINT143_1:1; /* TINT143[1] */\r
+ } BIT; /* */\r
+ } ICDICFR34; /* */\r
+ union { /* ICDICFR35 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT144_0:1; /* TINT144[0] */\r
+ _UDWORD TINT144_1:1; /* TINT144[1] */\r
+ _UDWORD TINT145_0:1; /* TINT145[0] */\r
+ _UDWORD TINT145_1:1; /* TINT145[1] */\r
+ _UDWORD TINT146_0:1; /* TINT146[0] */\r
+ _UDWORD TINT146_1:1; /* TINT146[1] */\r
+ _UDWORD TINT147_0:1; /* TINT147[0] */\r
+ _UDWORD TINT147_1:1; /* TINT147[1] */\r
+ _UDWORD TINT148_0:1; /* TINT148[0] */\r
+ _UDWORD TINT148_1:1; /* TINT148[1] */\r
+ _UDWORD TINT149_0:1; /* TINT149[0] */\r
+ _UDWORD TINT149_1:1; /* TINT149[1] */\r
+ _UDWORD TINT150_0:1; /* TINT150[0] */\r
+ _UDWORD TINT150_1:1; /* TINT150[1] */\r
+ _UDWORD TINT151_0:1; /* TINT151[0] */\r
+ _UDWORD TINT151_1:1; /* TINT151[1] */\r
+ _UDWORD TINT152_0:1; /* TINT152[0] */\r
+ _UDWORD TINT152_1:1; /* TINT152[1] */\r
+ _UDWORD TINT153_0:1; /* TINT153[0] */\r
+ _UDWORD TINT153_1:1; /* TINT153[1] */\r
+ _UDWORD TINT154_0:1; /* TINT154[0] */\r
+ _UDWORD TINT154_1:1; /* TINT154[1] */\r
+ _UDWORD TINT155_0:1; /* TINT155[0] */\r
+ _UDWORD TINT155_1:1; /* TINT155[1] */\r
+ _UDWORD TINT156_0:1; /* TINT156[0] */\r
+ _UDWORD TINT156_1:1; /* TINT156[1] */\r
+ _UDWORD TINT157_0:1; /* TINT157[0] */\r
+ _UDWORD TINT157_1:1; /* TINT157[1] */\r
+ _UDWORD TINT158_0:1; /* TINT158[0] */\r
+ _UDWORD TINT158_1:1; /* TINT158[1] */\r
+ _UDWORD TINT159_0:1; /* TINT159[0] */\r
+ _UDWORD TINT159_1:1; /* TINT159[1] */\r
+ } BIT; /* */\r
+ } ICDICFR35; /* */\r
+ union { /* ICDICFR36 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TINT160_0:1; /* TINT160[0] */\r
+ _UDWORD TINT160_1:1; /* TINT160[1] */\r
+ _UDWORD TINT161_0:1; /* TINT161[0] */\r
+ _UDWORD TINT161_1:1; /* TINT161[1] */\r
+ _UDWORD TINT162_0:1; /* TINT162[0] */\r
+ _UDWORD TINT162_1:1; /* TINT162[1] */\r
+ _UDWORD :26; /* */\r
+ } BIT; /* */\r
+ } ICDICFR36; /* */\r
+ } n; /* */\r
+ } ICDICFR; /* */\r
+ _UBYTE wk19[108]; /* */\r
+ union { /* ppi_status */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :11; /* */\r
+ _UDWORD ppi_status0:1; /* ppi_status[0] */\r
+ _UDWORD ppi_status1:1; /* ppi_status[1] */\r
+ _UDWORD ppi_status2:1; /* ppi_status[2] */\r
+ _UDWORD ppi_status3:1; /* ppi_status[3] */\r
+ _UDWORD ppi_status4:1; /* ppi_status[4] */\r
+ _UDWORD :16; /* */\r
+ } BIT; /* */\r
+ } ppi_status; /* */\r
+ union { /* spi_status */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD spi_status0:1; /* spi_status[0] */\r
+ _UDWORD spi_status1:1; /* spi_status[1] */\r
+ _UDWORD spi_status2:1; /* spi_status[2] */\r
+ _UDWORD spi_status3:1; /* spi_status[3] */\r
+ _UDWORD spi_status4:1; /* spi_status[4] */\r
+ _UDWORD spi_status5:1; /* spi_status[5] */\r
+ _UDWORD spi_status6:1; /* spi_status[6] */\r
+ _UDWORD spi_status7:1; /* spi_status[7] */\r
+ _UDWORD spi_status8:1; /* spi_status[8] */\r
+ _UDWORD spi_status9:1; /* spi_status[9] */\r
+ _UDWORD spi_status10:1; /* spi_status[10] */\r
+ _UDWORD spi_status11:1; /* spi_status[11] */\r
+ _UDWORD spi_status12:1; /* spi_status[12] */\r
+ _UDWORD spi_status13:1; /* spi_status[13] */\r
+ _UDWORD spi_status14:1; /* spi_status[14] */\r
+ _UDWORD spi_status15:1; /* spi_status[15] */\r
+ _UDWORD spi_status16:1; /* spi_status[16] */\r
+ _UDWORD spi_status17:1; /* spi_status[17] */\r
+ _UDWORD spi_status18:1; /* spi_status[18] */\r
+ _UDWORD spi_status19:1; /* spi_status[19] */\r
+ _UDWORD spi_status20:1; /* spi_status[20] */\r
+ _UDWORD spi_status21:1; /* spi_status[21] */\r
+ _UDWORD spi_status22:1; /* spi_status[22] */\r
+ _UDWORD spi_status23:1; /* spi_status[23] */\r
+ _UDWORD spi_status24:1; /* spi_status[24] */\r
+ _UDWORD spi_status25:1; /* spi_status[25] */\r
+ _UDWORD spi_status26:1; /* spi_status[26] */\r
+ _UDWORD spi_status27:1; /* spi_status[27] */\r
+ _UDWORD spi_status28:1; /* spi_status[28] */\r
+ _UDWORD spi_status29:1; /* spi_status[29] */\r
+ _UDWORD spi_status30:1; /* spi_status[30] */\r
+ _UDWORD spi_status31:1; /* spi_status[31] */\r
+ } BIT; /* */\r
+ } spi_status[17]; /* */\r
+ _UBYTE wk20[440]; /* */\r
+ union { /* ICDSGIR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SGIINTID:4; /* SGIINTID */\r
+ _UDWORD :11; /* */\r
+ _UDWORD SATT:1; /* SATT */\r
+ _UDWORD CPUTargetList:8; /* CPUTargetList */\r
+ _UDWORD TargetListFilter:2; /* TargetListFilter */\r
+ _UDWORD :6; /* */\r
+ } BIT; /* */\r
+ } ICDSGIR; /* */\r
+ _UBYTE wk21[252]; /* */\r
+ union { /* ICCICR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD EnableS:1; /* EnableS */\r
+ _UDWORD EnableNS:1; /* EnableNS */\r
+ _UDWORD AckCtl:1; /* AckCtl */\r
+ _UDWORD FIQEn:1; /* FIQEn */\r
+ _UDWORD SBPR:1; /* SBPR */\r
+ _UDWORD :27; /* */\r
+ } BIT; /* */\r
+ } ICCICR; /* */\r
+ union { /* ICCPMR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD Priority:8; /* Priority */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } ICCPMR; /* */\r
+ union { /* ICCBPR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD Binarypoint:3; /* Binarypoint */\r
+ _UDWORD :29; /* */\r
+ } BIT; /* */\r
+ } ICCBPR; /* */\r
+ union { /* ICCIAR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ACKINTID:10; /* ACKINTID */\r
+ _UDWORD CPUID:3; /* CPUID */\r
+ _UDWORD :19; /* */\r
+ } BIT; /* */\r
+ } ICCIAR; /* */\r
+ union { /* ICCEOIR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD EOIINTID:10; /* EOIINTID */\r
+ _UDWORD CPUID:3; /* CPUID */\r
+ _UDWORD :19; /* */\r
+ } BIT; /* */\r
+ } ICCEOIR; /* */\r
+ union { /* ICCRPR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD Priority:8; /* Priority */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } ICCRPR; /* */\r
+ union { /* ICCHPIR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD PENDINTID:10; /* PENDINTID */\r
+ _UDWORD CPUID:3; /* CPUID */\r
+ _UDWORD :19; /* */\r
+ } BIT; /* */\r
+ } ICCHPIR; /* */\r
+ union { /* ICCABPR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD Binarypoint:3; /* Binarypoint */\r
+ _UDWORD :29; /* */\r
+ } BIT; /* */\r
+ } ICCABPR; /* */\r
+ _UBYTE wk22[220]; /* */\r
+ _UDWORD ICCIDR; /* ICCIDR */\r
+}; /* */\r
+struct st_intc_2 { /* struct INTC2 */\r
+ union { /* ICR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :1; /* */\r
+ _UWORD NMIF:1; /* NMIF */\r
+ _UWORD :6; /* */\r
+ _UWORD NMIE:1; /* NMIE */\r
+ _UWORD :6; /* */\r
+ _UWORD NMIL:1; /* NMIL */\r
+ } BIT; /* */\r
+ } ICR0; /* */\r
+ union { /* ICR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD IRQ00S:1; /* IRQ00S */\r
+ _UWORD IRQ01S:1; /* IRQ01S */\r
+ _UWORD IRQ10S:1; /* IRQ10S */\r
+ _UWORD IRQ11S:1; /* IRQ11S */\r
+ _UWORD IRQ20S:1; /* IRQ20S */\r
+ _UWORD IRQ21S:1; /* IRQ21S */\r
+ _UWORD IRQ30S:1; /* IRQ30S */\r
+ _UWORD IRQ31S:1; /* IRQ31S */\r
+ _UWORD IRQ40S:1; /* IRQ40S */\r
+ _UWORD IRQ41S:1; /* IRQ41S */\r
+ _UWORD IRQ50S:1; /* IRQ50S */\r
+ _UWORD IRQ51S:1; /* IRQ51S */\r
+ _UWORD IRQ60S:1; /* IRQ60S */\r
+ _UWORD IRQ61S:1; /* IRQ61S */\r
+ _UWORD IRQ70S:1; /* IRQ70S */\r
+ _UWORD IRQ71S:1; /* IRQ71S */\r
+ } BIT; /* */\r
+ } ICR1; /* */\r
+ _UBYTE wk0[2]; /* */\r
+ union { /* IRQRR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD IRQ0F:1; /* IRQ0F */\r
+ _UWORD IRQ1F:1; /* IRQ1F */\r
+ _UWORD IRQ2F:1; /* IRQ2F */\r
+ _UWORD IRQ3F:1; /* IRQ3F */\r
+ _UWORD IRQ4F:1; /* IRQ4F */\r
+ _UWORD IRQ5F:1; /* IRQ5F */\r
+ _UWORD IRQ6F:1; /* IRQ6F */\r
+ _UWORD IRQ7F:1; /* IRQ7F */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } IRQRR; /* */\r
+ _UBYTE wk1[16]; /* */\r
+ union { /* MXIR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD MXI:1; /* MXI */\r
+ _UWORD :15; /* */\r
+ } BIT; /* */\r
+ } MXIR0; /* */\r
+ union { /* MXIR1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD MXI:1; /* MXI */\r
+ _UWORD :15; /* */\r
+ } BIT; /* */\r
+ } MXIR1; /* */\r
+}; /* */\r
+\r
+#ifndef ARM_SIM\r
+#define INTC (*(volatile struct st_intc *) 0xE8201000) /* INTC Address */\r
+#define INTC2 (*(volatile struct st_intc_2 *)0xFCFEF800) /* INTC2 Address */\r
+#else /* ARM_SIM */\r
+#define INTC (*(volatile struct st_intc *) 0x45201000) /* INTC Address */\r
+#define INTC2 (*(volatile struct st_intc_2 *)0x49FEF800) /* INTC2 Address */\r
+#endif /* ARM_SIM */\r
+\r
+#endif /* __INTC_IODEFINE_H__ */\r
+\r
+/* End of File */\r
--- /dev/null
+/******************************************************************************\r
+* DISCLAIMER\r
+*\r
+* This software is supplied by Renesas Electronics Corporation and is only \r
+* intended for use with Renesas products. No other uses are authorized.\r
+*\r
+* This software is owned by Renesas Electronics Corporation and is protected under \r
+* all applicable laws, including copyright laws.\r
+*\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES \r
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, \r
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A \r
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY \r
+* DISCLAIMED.\r
+*\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES \r
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS\r
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+*\r
+* Renesas reserves the right, without notice, to make changes to this \r
+* software and to discontinue the availability of this software.\r
+* By using this software, you agree to the additional terms and \r
+* conditions found by accessing the following link: \r
+* http://www.renesas.com/disclaimer\r
+********************************************************************************\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+**************************** Technical reference data **************************\r
+* System Name : \r
+* File Name : mtu2_iodefine.h\r
+* Abstract : \r
+* Version : 1.00.00\r
+* Device : ARM\r
+* Tool-Chain : \r
+* OS : None\r
+* H/W Platform: \r
+* Description : \r
+********************************************************************************\r
+* History : Jan.11,2013 Ver.1.00.00\r
+*******************************************************************************/\r
+#ifndef __MTU2_IODEFINE_H__\r
+#define __MTU2_IODEFINE_H__\r
+\r
+#include "typedefine.h"\r
+\r
+struct st_mtu2{ /* struct MTU2 */\r
+ union { /* TCR_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TPSC:3; /* TPSC */\r
+ _UBYTE CKEG:2; /* CKEG */\r
+ _UBYTE CCLR:2; /* CCLR */\r
+ _UBYTE :1;\r
+ } BIT; /* */\r
+ } TCR_2; /* */\r
+ union { /* TMDR_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MD:4; /* MD */\r
+ _UBYTE :4; /* */\r
+ } BIT; /* */\r
+ } TMDR_2; /* */\r
+ union { /* TIOR_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOA:4; /* IOA */\r
+ _UBYTE IOB:4; /* IOB */\r
+ } BIT; /* */\r
+ } TIOR_2; /* */\r
+ _UBYTE wk0[1]; /* */\r
+ union { /* TIER_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TGIEA:1; /* TGIEA */\r
+ _UBYTE TGIEB:1; /* TGIEB */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TCIEV:1; /* TCIEV */\r
+ _UBYTE TCIEU:1; /* TCIEU */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TTGE:1; /* TTGE */\r
+ } BIT; /* */\r
+ } TIER_2; /* */\r
+ union { /* TSR_2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TGFA:1; /* TGFA */\r
+ _UBYTE TGFB:1; /* TGFB */\r
+ _UBYTE :1; /* */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TCFV:1; /* TCFV */\r
+ _UBYTE TCFU:1; /* TCFU */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TCFD:1; /* TCFD */\r
+ } BIT; /* */\r
+ } TSR_2; /* */\r
+ union { /* TCNT_2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCNT_2; /* */\r
+ union { /* TGRA_2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRA_2; /* */\r
+ union { /* TGRB_2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRB_2; /* */\r
+ _UBYTE wk1[500]; /* */\r
+ union { /* TCR_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TPSC:3; /* TPSC */\r
+ _UBYTE CKEG:2; /* CKEG */\r
+ _UBYTE CCLR:3; /* CCLR */\r
+ } BIT; /* */\r
+ } TCR_3; /* */\r
+ union { /* TCR_4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TPSC:3; /* TPSC */\r
+ _UBYTE CKEG:2; /* CKEG */\r
+ _UBYTE CCLR:3; /* CCLR */\r
+ } BIT; /* */\r
+ } TCR_4; /* */\r
+ union { /* TMDR_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MD:4; /* MD */\r
+ _UBYTE BFA:1; /* BFA */\r
+ _UBYTE BFB:1; /* BFB */\r
+ _UBYTE :2; /* */\r
+ } BIT; /* */\r
+ } TMDR_3; /* */\r
+ union { /* TMDR_4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MD:4; /* MD */\r
+ _UBYTE BFA:1; /* BFA */\r
+ _UBYTE BFB:1; /* BFB */\r
+ _UBYTE :2; /* */\r
+ } BIT; /* */\r
+ } TMDR_4; /* */\r
+ union { /* TIORH_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOA:4; /* IOA */\r
+ _UBYTE IOB:4; /* IOB */\r
+ } BIT; /* */\r
+ } TIORH_3; /* */\r
+ union { /* TIORL_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOC:4; /* IOC */\r
+ _UBYTE IOD:4; /* IOD */\r
+ } BIT; /* */\r
+ } TIORL_3; /* */\r
+ union { /* TIORH_4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOA:4; /* IOA */\r
+ _UBYTE IOB:4; /* IOB */\r
+ } BIT; /* */\r
+ } TIORH_4; /* */\r
+ union { /* TIORL_4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOC:4; /* IOC */\r
+ _UBYTE IOD:4; /* IOD */\r
+ } BIT; /* */\r
+ } TIORL_4; /* */\r
+ union { /* TIER_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TGIEA:1; /* TGIEA */\r
+ _UBYTE TGIEB:1; /* TGIEB */\r
+ _UBYTE TGIEC:1; /* TGIEC */\r
+ _UBYTE TGIED:1; /* TGIED */\r
+ _UBYTE TCIEV:1; /* TCIEV */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TTGE:1; /* TTGE */\r
+ } BIT; /* */\r
+ } TIER_3; /* */\r
+ union { /* TIER_4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TGIEA:1; /* TGIEA */\r
+ _UBYTE TGIEB:1; /* TGIEB */\r
+ _UBYTE TGIEC:1; /* TGIEC */\r
+ _UBYTE TGIED:1; /* TGIED */\r
+ _UBYTE TCIEV:1; /* TCIEV */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TTGE2:1; /* TTGE2 */\r
+ _UBYTE TTGE:1; /* TTGE */\r
+ } BIT; /* */\r
+ } TIER_4; /* */\r
+ union { /* TOER */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE OE3B:1; /* OE3B */\r
+ _UBYTE OE4A:1; /* OE4A */\r
+ _UBYTE OE4B:1; /* OE4B */\r
+ _UBYTE OE3D:1; /* OE3D */\r
+ _UBYTE OE4C:1; /* OE4C */\r
+ _UBYTE OE4D:1; /* OE4D */\r
+ _UBYTE :2; /* */\r
+ } BIT; /* */\r
+ } TOER; /* */\r
+ _UBYTE wk2[2]; /* */\r
+ union { /* TGCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE UF:1; /* UF */\r
+ _UBYTE VF:1; /* VF */\r
+ _UBYTE WF:1; /* WF */\r
+ _UBYTE FB:1; /* FB */\r
+ _UBYTE P:1; /* P */\r
+ _UBYTE N:1; /* N */\r
+ _UBYTE BDC:1; /* BDC */\r
+ _UBYTE :1; /* */\r
+ } BIT; /* */\r
+ } TGCR; /* */\r
+ union { /* TOCR1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE OLSP:1; /* OLSP */\r
+ _UBYTE OLSN:1; /* OLSN */\r
+ _UBYTE TOCS:1; /* TOCS */\r
+ _UBYTE TOCL:1; /* TOCL */\r
+ _UBYTE :2; /* */\r
+ _UBYTE PSYE:1; /* PSYE */\r
+ _UBYTE :1; /* */\r
+ } BIT; /* */\r
+ } TOCR1; /* */\r
+ union { /* TOCR2 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE OLS1P:1; /* OLS1P */\r
+ _UBYTE OLS1N:1; /* OLS1N */\r
+ _UBYTE OLS2P:1; /* OLS2P */\r
+ _UBYTE OLS2N:1; /* OLS2N */\r
+ _UBYTE OLS3P:1; /* OLS3P */\r
+ _UBYTE OLS3N:1; /* OLS3N */\r
+ _UBYTE BF:2; /* BF */\r
+ } BIT; /* */\r
+ } TOCR2; /* */\r
+ union { /* TCNT_3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCNT_3; /* */\r
+ union { /* TCNT_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCNT_4; /* */\r
+ union { /* TCDR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCDR; /* */\r
+ union { /* TDDR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TDDR; /* */\r
+ union { /* TGRA_3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRA_3; /* */\r
+ union { /* TGRB_3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRB_3; /* */\r
+ union { /* TGRA_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRA_4; /* */\r
+ union { /* TGRB_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRB_4; /* */\r
+ union { /* TCNTS */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCNTS; /* */\r
+ union { /* TCBR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCBR; /* */\r
+ union { /* TGRC_3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRC_3; /* */\r
+ union { /* TGRD_3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRD_3; /* */\r
+ union { /* TGRC_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRC_4; /* */\r
+ union { /* TGRD_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRD_4; /* */\r
+ union { /* TSR_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TGFA:1; /* TGFA */\r
+ _UBYTE TGFB:1; /* TGFB */\r
+ _UBYTE TGFC:1; /* TGFC */\r
+ _UBYTE TGFD:1; /* TGFD */\r
+ _UBYTE TCFV:1; /* TCFV */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TCFD:1; /* TCFD */\r
+ } BIT; /* */\r
+ } TSR_3; /* */\r
+ union { /* TSR_4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TGFA:1; /* TGFA */\r
+ _UBYTE TGFB:1; /* TGFB */\r
+ _UBYTE TGFC:1; /* TGFC */\r
+ _UBYTE TGFD:1; /* TGFD */\r
+ _UBYTE TCFV:1; /* TCFV */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TCFD:1; /* TCFD */\r
+ } BIT; /* */\r
+ } TSR_4; /* */\r
+ _UBYTE wk3[2]; /* */\r
+ union { /* TITCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE _4VCOR:3; /* _4VCOR */\r
+ _UBYTE T4VEN:1; /* T4VEN */\r
+ _UBYTE _3ACOR:3; /* _3ACOR */\r
+ _UBYTE T3AEN:1; /* T3AEN */\r
+ } BIT; /* */\r
+ } TITCR; /* */\r
+ union { /* TITCNT */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE _4VCNT:3; /* _4VCNT */\r
+ _UBYTE :1; /* */\r
+ _UBYTE _3ACNT:3; /* _3ACNT */\r
+ _UBYTE :1; /* */\r
+ } BIT; /* */\r
+ } TITCNT; /* */\r
+ union { /* TBTER */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE BTE:2; /* BTE */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } TBTER; /* */\r
+ _UBYTE wk4[1]; /* */\r
+ union { /* TDER */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TDER:1; /* TDER */\r
+ _UBYTE :7; /* */\r
+ } BIT; /* */\r
+ } TDER; /* */\r
+ _UBYTE wk5[1]; /* */\r
+ union { /* TOLBR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE OLS1P:1; /* OLS1P */\r
+ _UBYTE OLS1N:1; /* OLS1N */\r
+ _UBYTE OLS2P:1; /* OLS2P */\r
+ _UBYTE OLS2N:1; /* OLS2N */\r
+ _UBYTE OLS3P:1; /* OLS3P */\r
+ _UBYTE OLS3N:1; /* OLS3N */\r
+ _UBYTE :2; /* */\r
+ } BIT; /* */\r
+ } TOLBR; /* */\r
+ _UBYTE wk6[1]; /* */\r
+ union { /* TBTM_3 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TTSA:1; /* TTSA */\r
+ _UBYTE TTSB:1; /* TTSB */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } TBTM_3; /* */\r
+ union { /* TBTM_4 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TTSA:1; /* TTSA */\r
+ _UBYTE TTSB:1; /* TTSB */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } TBTM_4; /* */\r
+ _UBYTE wk7[6]; /* */\r
+ union { /* TADCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD ITB4VE:1; /* ITB4VE */\r
+ _UWORD ITB3AE:1; /* ITB3AE */\r
+ _UWORD ITA4VE:1; /* ITA4VE */\r
+ _UWORD ITA3AE:1; /* ITA3AE */\r
+ _UWORD DT4BE:1; /* DT4BE */\r
+ _UWORD UT4BE:1; /* UT4BE */\r
+ _UWORD DT4AE:1; /* DT4AE */\r
+ _UWORD UT4AE:1; /* UT4AE */\r
+ _UWORD :6; /* */\r
+ _UWORD BF:2; /* BF */\r
+ } BIT; /* */\r
+ } TADCR; /* */\r
+ _UBYTE wk8[2]; /* */\r
+ union { /* TADCORA_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TADCORA_4; /* */\r
+ union { /* TADCORB_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TADCORB_4; /* */\r
+ union { /* TADCOBRA_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TADCOBRA_4; /* */\r
+ union { /* TADCOBRB_4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TADCOBRB_4; /* */\r
+ _UBYTE wk9[20]; /* */\r
+ union { /* TWCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE WRE:1; /* WRE */\r
+ _UBYTE :6; /* */\r
+ _UBYTE CCE:1; /* CCE */\r
+ } BIT; /* */\r
+ } TWCR; /* */\r
+ _UBYTE wk10[31]; /* */\r
+ union { /* TSTR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE CST0:1; /* CST0 */\r
+ _UBYTE CST1:1; /* CST1 */\r
+ _UBYTE CST2:1; /* CST2 */\r
+ _UBYTE :3; /* */\r
+ _UBYTE CST3:1; /* CST3 */\r
+ _UBYTE CST4:1; /* CST4 */\r
+ } BIT; /* */\r
+ } TSTR; /* */\r
+ union { /* TSYR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE SYNC0:1; /* SYNC0 */\r
+ _UBYTE SYNC1:1; /* SYNC1 */\r
+ _UBYTE SYNC2:1; /* SYNC2 */\r
+ _UBYTE :3; /* */\r
+ _UBYTE SYNC3:1; /* SYNC3 */\r
+ _UBYTE SYNC4:1; /* SYNC4 */\r
+ } BIT; /* */\r
+ } TSYR; /* */\r
+ _UBYTE wk11[2]; /* */\r
+ union { /* TRWER */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE RWE:1; /* RWE */\r
+ _UBYTE :7; /* */\r
+ } BIT; /* */\r
+ } TRWER; /* */\r
+ _UBYTE wk12[123]; /* */\r
+ union { /* TCR_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TPSC:3; /* TPSC */\r
+ _UBYTE CKEG:2; /* CKEG */\r
+ _UBYTE CCLR:3; /* CCLR */\r
+ } BIT; /* */\r
+ } TCR_0; /* */\r
+ union { /* TMDR_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MD:4; /* MD */\r
+ _UBYTE BFA:1; /* BFA */\r
+ _UBYTE BFB:1; /* BFB */\r
+ _UBYTE BFE:1; /* BFE */\r
+ _UBYTE :1; /* */\r
+ } BIT; /* */\r
+ } TMDR_0; /* */\r
+ union { /* TIORH_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOA:4; /* IOA */\r
+ _UBYTE IOB:4; /* IOB */\r
+ } BIT; /* */\r
+ } TIORH_0; /* */\r
+ union { /* TIORL_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOC:4; /* IOC */\r
+ _UBYTE IOD:4; /* IOD */\r
+ } BIT; /* */\r
+ } TIORL_0; /* */\r
+ union { /* TIER_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TGIEA:1; /* TGIEA */\r
+ _UBYTE TGIEB:1; /* TGIEB */\r
+ _UBYTE TGIEC:1; /* TGIEC */\r
+ _UBYTE TGIED:1; /* TGIED */\r
+ _UBYTE TCIEV:1; /* TCIEV */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TTGE:1; /* TTGE */\r
+ } BIT; /* */\r
+ } TIER_0; /* */\r
+ union { /* TSR_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TGFA:1; /* TGFA */\r
+ _UBYTE TGFB:1; /* TGFB */\r
+ _UBYTE TGFC:1; /* TGFC */\r
+ _UBYTE TGFD:1; /* TGFD */\r
+ _UBYTE TCFV:1; /* TCFV */\r
+ _UBYTE :3; /* */\r
+ } BIT; /* */\r
+ } TSR_0; /* */\r
+ union { /* TCNT_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCNT_0; /* */\r
+ union { /* TGRA_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRA_0; /* */\r
+ union { /* TGRB_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRB_0; /* */\r
+ union { /* TGRC_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRC_0; /* */\r
+ union { /* TGRD_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRD_0; /* */\r
+ _UBYTE wk13[16]; /* */\r
+ union { /* TGRE_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRE_0; /* */\r
+ union { /* TGRF_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRF_0; /* */\r
+ union { /* TIER2_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TGIEE:1; /* TGIEE */\r
+ _UBYTE TGIEF:1; /* TGIEF */\r
+ _UBYTE :5; /* */\r
+ _UBYTE TTGE2:1; /* TTGE2 */\r
+ } BIT; /* */\r
+ } TIER2_0; /* */\r
+ union { /* TSR2_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TGFE:1; /* TGFE */\r
+ _UBYTE TGFF:1; /* TGFF */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } TSR2_0; /* */\r
+ union { /* TBTM_0 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TTSA:1; /* TTSA */\r
+ _UBYTE TTSB:1; /* TTSB */\r
+ _UBYTE TTSE:1; /* TTSE */\r
+ _UBYTE :5; /* */\r
+ } BIT; /* */\r
+ } TBTM_0; /* */\r
+ _UBYTE wk14[89]; /* */\r
+ union { /* TCR_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TPSC:3; /* TPSC */\r
+ _UBYTE CKEG:2; /* CKEG */\r
+ _UBYTE CCLR:2; /* CCLR */\r
+ _UBYTE :1;\r
+ } BIT; /* */\r
+ } TCR_1; /* */\r
+ union { /* TMDR_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE MD:4; /* MD */\r
+ _UBYTE :4; /* */\r
+ } BIT; /* */\r
+ } TMDR_1; /* */\r
+ union { /* TIOR_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE IOA:4; /* IOA */\r
+ _UBYTE IOB:4; /* IOB */\r
+ } BIT; /* */\r
+ } TIOR_1; /* */\r
+ _UBYTE wk15[1]; /* */\r
+ union { /* TIER_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TGIEA:1; /* TGIEA */\r
+ _UBYTE TGIEB:1; /* TGIEB */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TCIEV:1; /* TCIEV */\r
+ _UBYTE TCIEU:1; /* TCIEU */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TTGE:1; /* TTGE */\r
+ } BIT; /* */\r
+ } TIER_1; /* */\r
+ union { /* TSR_1 */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE TGFA:1; /* TGFA */\r
+ _UBYTE TGFB:1; /* TGFB */\r
+ _UBYTE :2; /* */\r
+ _UBYTE TCFV:1; /* TCFV */\r
+ _UBYTE TCFU:1; /* TCFU */\r
+ _UBYTE :1; /* */\r
+ _UBYTE TCFD:1; /* TCFD */\r
+ } BIT; /* */\r
+ } TSR_1; /* */\r
+ union { /* TCNT_1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TCNT_1; /* */\r
+ union { /* TGRA_1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRA_1; /* */\r
+ union { /* TGRB_1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD D:16; /* D */\r
+ } BIT; /* */\r
+ } TGRB_1; /* */\r
+ _UBYTE wk16[4]; /* */\r
+ union { /* TICCR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE I1AE:1; /* I1AE */\r
+ _UBYTE I1BE:1; /* I1BE */\r
+ _UBYTE I2AE:1; /* I2AE */\r
+ _UBYTE I2BE:1; /* I2BE */\r
+ _UBYTE :4; /* */\r
+ } BIT; /* */\r
+ } TICCR; /* */\r
+}; /* */\r
+\r
+\r
+#define MTU2 (*(volatile struct st_mtu2 *)0xFCFF0000) /* MTU2 Address */\r
+\r
+#endif /* __MTU2_IODEFINE_H__ */\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : ostm_iodefine.h\r
+* Version : 0.01\r
+* Device(s) : Aragon\r
+* Tool-Chain : DS-5 Ver 5.8\r
+* ARM Complier \r
+* : \r
+* H/W Platform : Aragon CPU Board\r
+* Description : Aragon Sample Program vecotr.s\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 27.07.2012 0.01 \8eQ\8dl\8e\91\97¿\81Fsec11_OSTM_120601.pdf\r
+*******************************************************************************/\r
+#ifndef __OSTM_IODEFINE_H__\r
+#define __OSTM_IODEFINE_H__\r
+\r
+#include "typedefine.h"\r
+\r
+struct st_ostm_n { /* struct OSTM */\r
+ _UDWORD OSTMnCMP; /* OSTMnCMP */\r
+ _UDWORD OSTMnCNT; /* OSTMnCNT */\r
+ _UBYTE wk0[8]; /* */\r
+ union { /* OSTMnTE */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE OSTMnTE:1; /* OSTMnTE */\r
+ _UBYTE :7; /* */\r
+ } BIT; /* */\r
+ } OSTMnTE; /* */\r
+ _UBYTE wk1[3]; /* */\r
+ union { /* OSTMnTS */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE OSTMnTS:1; /* OSTMnTS */\r
+ _UBYTE :7; /* */\r
+ } BIT; /* */\r
+ } OSTMnTS; /* */\r
+ _UBYTE wk2[3]; /* */\r
+ union { /* OSTMnTT */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE OSTMnTT:1; /* OSTMnTT */\r
+ _UBYTE :7; /* */\r
+ } BIT; /* */\r
+ } OSTMnTT; /* */\r
+ _UBYTE wk3[7]; /* */\r
+ union { /* OSTMnCTL */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE OSTMnMD0:1; /* OSTMnMD0 */\r
+ _UBYTE OSTMnMD1:1; /* OSTMnMD1 */\r
+ _UBYTE :6; /* */\r
+ } BIT; /* */\r
+ } OSTMnCTL; /* */\r
+}; /* */\r
+\r
+#define OSTM0 (*(volatile struct st_ostm_n *)0xFCFEC000) /* OSTM0 Address */\r
+#define OSTM1 (*(volatile struct st_ostm_n *)0xFCFEC400) /* OSTM1 Address */\r
+\r
+\r
+#endif /* __OSTM_IODEFINE_H__ */\r
+\r
+/* End of File */\r
--- /dev/null
+/******************************************************************************\r
+* DISCLAIMER\r
+*\r
+* This software is supplied by Renesas Electronics Corporation and is only \r
+* intended for use with Renesas products. No other uses are authorized.\r
+*\r
+* This software is owned by Renesas Electronics Corporation and is protected under \r
+* all applicable laws, including copyright laws.\r
+*\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES \r
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, \r
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A \r
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY \r
+* DISCLAIMED.\r
+*\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES \r
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS\r
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+*\r
+* Renesas reserves the right, without notice, to make changes to this \r
+* software and to discontinue the availability of this software.\r
+* By using this software, you agree to the additional terms and \r
+* conditions found by accessing the following link: \r
+* http://www.renesas.com/disclaimer\r
+********************************************************************************\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+**************************** Technical reference data **************************\r
+* System Name : \r
+* File Name : pfc_iodefine.h\r
+* Abstract : \r
+* Version : 1.00.00\r
+* Device : ARM\r
+* Tool-Chain : \r
+* OS : None\r
+* H/W Platform: \r
+* Description : \r
+********************************************************************************\r
+* History : Mar.06,2012 Ver.1.00.00\r
+*******************************************************************************/\r
+#ifndef __PFC_IODEFINE_H__\r
+#define __PFC_IODEFINE_H__\r
+\r
+#include "typedefine.h"\r
+\r
+struct st_pfc_n { /* struct PFC */\r
+ union { /* Pn */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD Pn0:1; /* */\r
+ _UWORD Pn1:1; /* */\r
+ _UWORD Pn2:1; /* */\r
+ _UWORD Pn3:1; /* */\r
+ _UWORD Pn4:1; /* */\r
+ _UWORD Pn5:1; /* */\r
+ _UWORD Pn6:1; /* */\r
+ _UWORD Pn7:1; /* */\r
+ _UWORD Pn8:1; /* */\r
+ _UWORD Pn9:1; /* */\r
+ _UWORD Pn10:1; /* */\r
+ _UWORD Pn11:1; /* */\r
+ _UWORD Pn12:1; /* */\r
+ _UWORD Pn13:1; /* */\r
+ _UWORD Pn14:1; /* */\r
+ _UWORD Pn15:1; /* */\r
+ } BIT; /* */\r
+ } Pn; /* */\r
+ _UBYTE wk0[0x100-2]; /* */\r
+ union { /* PSRn */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* WORD Access */\r
+ _UDWORD ENABLE:16; /* */\r
+ _UDWORD SET:16; /* */\r
+ } SET;\r
+ struct { /* Bit Access */\r
+ _UDWORD PSRn0:1; /* */\r
+ _UDWORD PSRn1:1; /* */\r
+ _UDWORD PSRn2:1; /* */\r
+ _UDWORD PSRn3:1; /* */\r
+ _UDWORD PSRn4:1; /* */\r
+ _UDWORD PSRn5:1; /* */\r
+ _UDWORD PSRn6:1; /* */\r
+ _UDWORD PSRn7:1; /* */\r
+ _UDWORD PSRn8:1; /* */\r
+ _UDWORD PSRn9:1; /* */\r
+ _UDWORD PSRn10:1; /* */\r
+ _UDWORD PSRn11:1; /* */\r
+ _UDWORD PSRn12:1; /* */\r
+ _UDWORD PSRn13:1; /* */\r
+ _UDWORD PSRn14:1; /* */\r
+ _UDWORD PSRn15:1; /* */\r
+ _UDWORD PSRn16:1; /* */\r
+ _UDWORD PSRn17:1; /* */\r
+ _UDWORD PSRn18:1; /* */\r
+ _UDWORD PSRn19:1; /* */\r
+ _UDWORD PSRn20:1; /* */\r
+ _UDWORD PSRn21:1; /* */\r
+ _UDWORD PSRn22:1; /* */\r
+ _UDWORD PSRn23:1; /* */\r
+ _UDWORD PSRn24:1; /* */\r
+ _UDWORD PSRn25:1; /* */\r
+ _UDWORD PSRn26:1; /* */\r
+ _UDWORD PSRn27:1; /* */\r
+ _UDWORD PSRn28:1; /* */\r
+ _UDWORD PSRn29:1; /* */\r
+ _UDWORD PSRn30:1; /* */\r
+ _UDWORD PSRn31:1; /* */\r
+ } BIT; /* */\r
+ } PSRn; /* */\r
+ _UBYTE wk1[0x100-4]; /* */\r
+ union { /* PPRn */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PPRn0:1; /* */\r
+ _UWORD PPRn1:1; /* */\r
+ _UWORD PPRn2:1; /* */\r
+ _UWORD PPRn3:1; /* */\r
+ _UWORD PPRn4:1; /* */\r
+ _UWORD PPRn5:1; /* */\r
+ _UWORD PPRn6:1; /* */\r
+ _UWORD PPRn7:1; /* */\r
+ _UWORD PPRn8:1; /* */\r
+ _UWORD PPRn9:1; /* */\r
+ _UWORD PPRn10:1; /* */\r
+ _UWORD PPRn11:1; /* */\r
+ _UWORD PPRn12:1; /* */\r
+ _UWORD PPRn13:1; /* */\r
+ _UWORD PPRn14:1; /* */\r
+ _UWORD PPRn15:1; /* */\r
+ } BIT; /* */\r
+ } PPRn; /* */\r
+ _UBYTE wk2[0x100-2]; /* */\r
+ union { /* PMn */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PMn0:1; /* */\r
+ _UWORD PMn1:1; /* */\r
+ _UWORD PMn2:1; /* */\r
+ _UWORD PMn3:1; /* */\r
+ _UWORD PMn4:1; /* */\r
+ _UWORD PMn5:1; /* */\r
+ _UWORD PMn6:1; /* */\r
+ _UWORD PMn7:1; /* */\r
+ _UWORD PMn8:1; /* */\r
+ _UWORD PMn9:1; /* */\r
+ _UWORD PMn10:1; /* */\r
+ _UWORD PMn11:1; /* */\r
+ _UWORD PMn12:1; /* */\r
+ _UWORD PMn13:1; /* */\r
+ _UWORD PMn14:1; /* */\r
+ _UWORD PMn15:1; /* */\r
+ } BIT; /* */\r
+ } PMn; /* */\r
+ _UBYTE wk3[0x100-2]; /* */\r
+ union { /* PMCn */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PMCn0:1; /* */\r
+ _UWORD PMCn1:1; /* */\r
+ _UWORD PMCn2:1; /* */\r
+ _UWORD PMCn3:1; /* */\r
+ _UWORD PMCn4:1; /* */\r
+ _UWORD PMCn5:1; /* */\r
+ _UWORD PMCn6:1; /* */\r
+ _UWORD PMCn7:1; /* */\r
+ _UWORD PMCn8:1; /* */\r
+ _UWORD PMCn9:1; /* */\r
+ _UWORD PMCn10:1; /* */\r
+ _UWORD PMCn11:1; /* */\r
+ _UWORD PMCn12:1; /* */\r
+ _UWORD PMCn13:1; /* */\r
+ _UWORD PMCn14:1; /* */\r
+ _UWORD PMCn15:1; /* */\r
+ } BIT; /* */\r
+ } PMCn; /* */\r
+ _UBYTE wk4[0x100-2]; /* */\r
+ union { /* PFCn */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PFCn0:1; /* */\r
+ _UWORD PFCn1:1; /* */\r
+ _UWORD PFCn2:1; /* */\r
+ _UWORD PFCn3:1; /* */\r
+ _UWORD PFCn4:1; /* */\r
+ _UWORD PFCn5:1; /* */\r
+ _UWORD PFCn6:1; /* */\r
+ _UWORD PFCn7:1; /* */\r
+ _UWORD PFCn8:1; /* */\r
+ _UWORD PFCn9:1; /* */\r
+ _UWORD PFCn10:1; /* */\r
+ _UWORD PFCn11:1; /* */\r
+ _UWORD PFCn12:1; /* */\r
+ _UWORD PFCn13:1; /* */\r
+ _UWORD PFCn14:1; /* */\r
+ _UWORD PFCn15:1; /* */\r
+ } BIT; /* */\r
+ } PFCn; /* */\r
+ _UBYTE wk5[0x100-2]; /* */\r
+ union { /* PFCEn */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PFCEn0:1; /* */\r
+ _UWORD PFCEn1:1; /* */\r
+ _UWORD PFCEn2:1; /* */\r
+ _UWORD PFCEn3:1; /* */\r
+ _UWORD PFCEn4:1; /* */\r
+ _UWORD PFCEn5:1; /* */\r
+ _UWORD PFCEn6:1; /* */\r
+ _UWORD PFCEn7:1; /* */\r
+ _UWORD PFCEn8:1; /* */\r
+ _UWORD PFCEn9:1; /* */\r
+ _UWORD PFCEn10:1; /* */\r
+ _UWORD PFCEn11:1; /* */\r
+ _UWORD PFCEn12:1; /* */\r
+ _UWORD PFCEn13:1; /* */\r
+ _UWORD PFCEn14:1; /* */\r
+ _UWORD PFCEn15:1; /* */\r
+ } BIT; /* */\r
+ } PFCEn; /* */\r
+ _UBYTE wk6[0x100-2]; /* */\r
+ union { /* PNOTn */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PNOTn0:1; /* */\r
+ _UWORD PNOTn1:1; /* */\r
+ _UWORD PNOTn2:1; /* */\r
+ _UWORD PNOTn3:1; /* */\r
+ _UWORD PNOTn4:1; /* */\r
+ _UWORD PNOTn5:1; /* */\r
+ _UWORD PNOTn6:1; /* */\r
+ _UWORD PNOTn7:1; /* */\r
+ _UWORD PNOTn8:1; /* */\r
+ _UWORD PNOTn9:1; /* */\r
+ _UWORD PNOTn10:1; /* */\r
+ _UWORD PNOTn11:1; /* */\r
+ _UWORD PNOTn12:1; /* */\r
+ _UWORD PNOTn13:1; /* */\r
+ _UWORD PNOTn14:1; /* */\r
+ _UWORD PNOTn15:1; /* */\r
+ } BIT; /* */\r
+ } PNOTn; /* */\r
+ _UBYTE wk7[0x100-2]; /* */\r
+ union { /* PMSRn */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* WORD Access */\r
+ _UDWORD ENABLE:16; /* */\r
+ _UDWORD SET:16; /* */\r
+ } SET;\r
+ struct { /* Bit Access */\r
+ _UDWORD PMSRn0:1; /* */\r
+ _UDWORD PMSRn1:1; /* */\r
+ _UDWORD PMSRn2:1; /* */\r
+ _UDWORD PMSRn3:1; /* */\r
+ _UDWORD PMSRn4:1; /* */\r
+ _UDWORD PMSRn5:1; /* */\r
+ _UDWORD PMSRn6:1; /* */\r
+ _UDWORD PMSRn7:1; /* */\r
+ _UDWORD PMSRn8:1; /* */\r
+ _UDWORD PMSRn9:1; /* */\r
+ _UDWORD PMSRn10:1; /* */\r
+ _UDWORD PMSRn11:1; /* */\r
+ _UDWORD PMSRn12:1; /* */\r
+ _UDWORD PMSRn13:1; /* */\r
+ _UDWORD PMSRn14:1; /* */\r
+ _UDWORD PMSRn15:1; /* */\r
+ _UDWORD PMSRn16:1; /* */\r
+ _UDWORD PMSRn17:1; /* */\r
+ _UDWORD PMSRn18:1; /* */\r
+ _UDWORD PMSRn19:1; /* */\r
+ _UDWORD PMSRn20:1; /* */\r
+ _UDWORD PMSRn21:1; /* */\r
+ _UDWORD PMSRn22:1; /* */\r
+ _UDWORD PMSRn23:1; /* */\r
+ _UDWORD PMSRn24:1; /* */\r
+ _UDWORD PMSRn25:1; /* */\r
+ _UDWORD PMSRn26:1; /* */\r
+ _UDWORD PMSRn27:1; /* */\r
+ _UDWORD PMSRn28:1; /* */\r
+ _UDWORD PMSRn29:1; /* */\r
+ _UDWORD PMSRn30:1; /* */\r
+ _UDWORD PMSRn31:1; /* */\r
+ } BIT; /* */\r
+ } PMSRn; /* */\r
+ _UBYTE wk8[0x100-4]; /* */\r
+ union { /* PMCSRn */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* WORD Access */\r
+ _UDWORD ENABLE:16; /* */\r
+ _UDWORD SET:16; /* */\r
+ } SET;\r
+ struct { /* Bit Access */\r
+ _UDWORD PMCSRn0:1; /* */\r
+ _UDWORD PMCSRn1:1; /* */\r
+ _UDWORD PMCSRn2:1; /* */\r
+ _UDWORD PMCSRn3:1; /* */\r
+ _UDWORD PMCSRn4:1; /* */\r
+ _UDWORD PMCSRn5:1; /* */\r
+ _UDWORD PMCSRn6:1; /* */\r
+ _UDWORD PMCSRn7:1; /* */\r
+ _UDWORD PMCSRn8:1; /* */\r
+ _UDWORD PMCSRn9:1; /* */\r
+ _UDWORD PMCSRn10:1; /* */\r
+ _UDWORD PMCSRn11:1; /* */\r
+ _UDWORD PMCSRn12:1; /* */\r
+ _UDWORD PMCSRn13:1; /* */\r
+ _UDWORD PMCSRn14:1; /* */\r
+ _UDWORD PMCSRn15:1; /* */\r
+ _UDWORD PMCSRn16:1; /* */\r
+ _UDWORD PMCSRn17:1; /* */\r
+ _UDWORD PMCSRn18:1; /* */\r
+ _UDWORD PMCSRn19:1; /* */\r
+ _UDWORD PMCSRn20:1; /* */\r
+ _UDWORD PMCSRn21:1; /* */\r
+ _UDWORD PMCSRn22:1; /* */\r
+ _UDWORD PMCSRn23:1; /* */\r
+ _UDWORD PMCSRn24:1; /* */\r
+ _UDWORD PMCSRn25:1; /* */\r
+ _UDWORD PMCSRn26:1; /* */\r
+ _UDWORD PMCSRn27:1; /* */\r
+ _UDWORD PMCSRn28:1; /* */\r
+ _UDWORD PMCSRn29:1; /* */\r
+ _UDWORD PMCSRn30:1; /* */\r
+ _UDWORD PMCSRn31:1; /* */\r
+ } BIT; /* */\r
+ } PMCSRn; /* */\r
+ _UBYTE wk9[0x100-4]; /* */\r
+ union { /* PFACEn */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PFCAEn0:1; /* */\r
+ _UWORD PFCAEn1:1; /* */\r
+ _UWORD PFCAEn2:1; /* */\r
+ _UWORD PFCAEn3:1; /* */\r
+ _UWORD PFCAEn4:1; /* */\r
+ _UWORD PFCAEn5:1; /* */\r
+ _UWORD PFCAEn6:1; /* */\r
+ _UWORD PFCAEn7:1; /* */\r
+ _UWORD PFCAEn8:1; /* */\r
+ _UWORD PFCAEn9:1; /* */\r
+ _UWORD PFCAEn10:1; /* */\r
+ _UWORD PFCAEn11:1; /* */\r
+ _UWORD PFCAEn12:1; /* */\r
+ _UWORD PFCAEn13:1; /* */\r
+ _UWORD PFCAEn14:1; /* */\r
+ _UWORD PFCAEn15:1; /* */\r
+ } BIT; /* */\r
+ } PFCAEn; /* */\r
+ _UBYTE wk10[0x4000-0xa00-2]; /* */\r
+ union { /* PIBCn */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PIBCn0:1; /* */\r
+ _UWORD PIBCn1:1; /* */\r
+ _UWORD PIBCn2:1; /* */\r
+ _UWORD PIBCn3:1; /* */\r
+ _UWORD PIBCn4:1; /* */\r
+ _UWORD PIBCn5:1; /* */\r
+ _UWORD PIBCn6:1; /* */\r
+ _UWORD PIBCn7:1; /* */\r
+ _UWORD PIBCn8:1; /* */\r
+ _UWORD PIBCn9:1; /* */\r
+ _UWORD PIBCn10:1; /* */\r
+ _UWORD PIBCn11:1; /* */\r
+ _UWORD PIBCn12:1; /* */\r
+ _UWORD PIBCn13:1; /* */\r
+ _UWORD PIBCn14:1; /* */\r
+ _UWORD PIBCn15:1; /* */\r
+ } BIT; /* */\r
+ } PIBCn; /* */\r
+ _UBYTE wk11[0x100-2]; /* */\r
+ union { /* PBDCn */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PBDCn0:1; /* */\r
+ _UWORD PBDCn1:1; /* */\r
+ _UWORD PBDCn2:1; /* */\r
+ _UWORD PBDCn3:1; /* */\r
+ _UWORD PBDCn4:1; /* */\r
+ _UWORD PBDCn5:1; /* */\r
+ _UWORD PBDCn6:1; /* */\r
+ _UWORD PBDCn7:1; /* */\r
+ _UWORD PBDCn8:1; /* */\r
+ _UWORD PBDCn9:1; /* */\r
+ _UWORD PBDCn10:1; /* */\r
+ _UWORD PBDCn11:1; /* */\r
+ _UWORD PBDCn12:1; /* */\r
+ _UWORD PBDCn13:1; /* */\r
+ _UWORD PBDCn14:1; /* */\r
+ _UWORD PBDCn15:1; /* */\r
+ } BIT; /* */\r
+ } PBDCn; /* */\r
+ _UBYTE wk12[0x100-2]; /* */\r
+ union { /* PIPCn */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PIPCn0:1; /* */\r
+ _UWORD PIPCn1:1; /* */\r
+ _UWORD PIPCn2:1; /* */\r
+ _UWORD PIPCn3:1; /* */\r
+ _UWORD PIPCn4:1; /* */\r
+ _UWORD PIPCn5:1; /* */\r
+ _UWORD PIPCn6:1; /* */\r
+ _UWORD PIPCn7:1; /* */\r
+ _UWORD PIPCn8:1; /* */\r
+ _UWORD PIPCn9:1; /* */\r
+ _UWORD PIPCn10:1; /* */\r
+ _UWORD PIPCn11:1; /* */\r
+ _UWORD PIPCn12:1; /* */\r
+ _UWORD PIPCn13:1; /* */\r
+ _UWORD PIPCn14:1; /* */\r
+ _UWORD PIPCn15:1; /* */\r
+ } BIT; /* */\r
+ } PIPCn; /* */\r
+ _UBYTE wk13[0x100-2]; /* */\r
+}; /* */\r
+\r
+#define PORTn_BASE 0xFCFE3000\r
+\r
+#define PORT0 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 0))) /* PORT 0 Address */\r
+#define PORT1 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 1))) /* PORT 1 Address */\r
+#define PORT2 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 2))) /* PORT 2 Address */\r
+#define PORT3 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 3))) /* PORT 3 Address */\r
+#define PORT4 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 4))) /* PORT 4 Address */\r
+#define PORT5 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 5))) /* PORT 5 Address */\r
+#define PORT6 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 6))) /* PORT 6 Address */\r
+#define PORT7 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 7))) /* PORT 7 Address */\r
+#define PORT8 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 8))) /* PORT 8 Address */\r
+#define PORT9 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 9))) /* PORT 9 Address */\r
+#define PORT10 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 10))) /* PORT 10 Address */\r
+#define PORT11 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 11))) /* PORT 11 Address */\r
+\r
+\r
+#endif /* __PFC_IODEFINE_H__ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : prr_iodefine.h\r
+* Version : 0.01\r
+* Device(s) : Aragon\r
+* Tool-Chain : DS-5 Ver 5.8\r
+* ARM Complier \r
+* : \r
+* H/W Platform : Aragon CPU Board\r
+* Description : Aragon Sample Program vecotr.s\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 27.07.2012 0.01 \8eQ\8dl\8e\91\97¿\81FAragon_PRR120614.xls !!!BSID\82Ì\93à\97e\82ª\8ed\97l\8f\91\82É\82È\82¢!!!\r
+*******************************************************************************/\r
+#ifndef __PRR_IODEFINE_H__\r
+#define __PRR_IODEFINE_H__\r
+\r
+#include "typedefine.h"\r
+\r
+struct st_prr { /* struct PRR */\r
+ union { /* MDR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD BTMD:3; /* BTMD */\r
+ _UDWORD :1; /* */\r
+ _UDWORD BTTEST:1; /* BTTEST */\r
+ _UDWORD :1; /* */\r
+ _UDWORD SEC:1; /* SEC */\r
+ _UDWORD SELFEWP:1; /* SELFEWP */\r
+ _UDWORD RAMBOOT:1; /* RAMBOOT */\r
+ _UDWORD :23; /* */\r
+ } BIT; /* */\r
+ } MDR; /* */\r
+ union { /* BSID */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD dummy:32; /* */ /* !!!\83r\83b\83g\8c\88\92è\8e\9f\91æ\81A\92è\8b`\82·\82é!!! */\r
+ } BIT; /* */\r
+ } BSID; /* */\r
+ union { /* ECCRR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ECCEN:1; /* ECCEN */\r
+ _UDWORD :31; /* */\r
+ } BIT; /* */\r
+ } ECCRR; /* */\r
+ _UBYTE wk0[276]; /* */\r
+ union { /* SEMRn */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SEMF:1; /* SEMF */\r
+ _UDWORD :31; /* */\r
+ } BIT; /* */\r
+ } SEMRn[32]; /* */\r
+ _UBYTE wk1[96]; /* */\r
+ union { /* RMPR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD AXI64:1; /* AXI64 */\r
+ _UDWORD AXI128:1; /* AXI128 */\r
+ _UDWORD :30; /* */\r
+ } BIT; /* */\r
+ } RMPR; /* */\r
+ union { /* AXIBUSCTL0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ETHAWCACHE:4; /* ETHAWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD ETHARCACHE:4; /* ETHARCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD JCUAWCACHE:4; /* JCUAWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD JCUARCACHE:4; /* JCUARCACHE */\r
+ _UDWORD :4; /* */\r
+ } BIT; /* */\r
+ } AXIBUSCTL0; /* */\r
+ union { /* AXIBUSCTL1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD IMR21AWCACHE:4; /* IMR21AWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD IMR21ARCACHE:4; /* IMR21ARCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD IMR20AWCACHE:4; /* IMR20AWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD IMR20ARCACHE:4; /* IMR20ARCACHE */\r
+ _UDWORD :4; /* */\r
+ } BIT; /* */\r
+ } AXIBUSCTL1; /* */\r
+ union { /* AXIBUSCTL2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD CEUAWCACHE:4; /* CEUAWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD CEUARCACHE:4; /* CEUARCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD IMRDAWCACHE:4; /* IMRDAWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD IMRDARCACHE:4; /* IMRDARCACHE */\r
+ _UDWORD :4; /* */\r
+ } BIT; /* */\r
+ } AXIBUSCTL2; /* */\r
+ union { /* AXIBUSCTL3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD RGP641AWCACHE:4; /* RGP641AWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD RGP641ARCACHE:4; /* RGP641ARCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD RGP640AWCACHE:4; /* RGP640AWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD RGP640ARCACHE:4; /* RGP640ARCACHE */\r
+ _UDWORD :4; /* */\r
+ } BIT; /* */\r
+ } AXIBUSCTL3; /* */\r
+ union { /* AXIBUSCTL4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD RGP1280AWCACHE:4; /* RGP1280AWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD RGP1280ARCACHE:4; /* RGP1280ARCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD RGP642AWCACHE:4; /* RGP642AWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD RGP642ARCACHE:4; /* RGP642ARCACHE */\r
+ _UDWORD :4; /* */\r
+ } BIT; /* */\r
+ } AXIBUSCTL4; /* */\r
+ union { /* AXIBUSCTL5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD MLB_AxCACHE:2; /* MLB_AxCACHE */\r
+ _UDWORD :14; /* */\r
+ _UDWORD RGP1281AWCACHE:4; /* RGP1281AWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD RGP1281ARCACHE:4; /* RGP1281ARCACHE */\r
+ _UDWORD :4; /* */\r
+ } BIT; /* */\r
+ } AXIBUSCTL5; /* */\r
+ union { /* AXIBUSCTL6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :8; /* */\r
+ _UDWORD VDC502ARCACHE:4; /* VDC502ARCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD VDC501AWCACHE:4; /* VDC501AWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD VDC501ARCACHE:4; /* VDC501ARCACHE */\r
+ _UDWORD :4; /* */\r
+ } BIT; /* */\r
+ } AXIBUSCTL6; /* */\r
+ union { /* AXIBUSCTL7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :8; /* */\r
+ _UDWORD VDC504ARCACHE:4; /* VDC504ARCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD VDC503AWCACHE:4; /* VDC503AWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD VDC503ARCACHE:4; /* VDC503ARCACHE */\r
+ _UDWORD :4; /* */\r
+ } BIT; /* */\r
+ } AXIBUSCTL7; /* */\r
+ union { /* AXIBUSCTL8 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD VDC511AWCACHE:4; /* VDC511AWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD VDC511ARCACHE:4; /* VDC511ARCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD VDC505AWCACHE:4; /* VDC505AWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD VDC505ARCACHE:4; /* VDC505ARCACHE */\r
+ _UDWORD :4; /* */\r
+ } BIT; /* */\r
+ } AXIBUSCTL8; /* */\r
+ union { /* AXIBUSCTL9 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD VDC513AWCACHE:4; /* VDC513AWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD VDC513ARCACHE:4; /* VDC513ARCACHE */\r
+ _UDWORD :12; /* */\r
+ _UDWORD VDC512ARCACHE:4; /* VDC512ARCACHE */\r
+ _UDWORD :4; /* */\r
+ } BIT; /* */\r
+ } AXIBUSCTL9; /* */\r
+ union { /* AXIBUSCTL10 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD VDC515AWCACHE:4; /* VDC515AWCACHE */\r
+ _UDWORD :4; /* */\r
+ _UDWORD VDC515ARCACHE:4; /* VDC515ARCACHE */\r
+ _UDWORD :12; /* */\r
+ _UDWORD VDC514ARCACHE:4; /* VDC514ARCACHE */\r
+ _UDWORD :4; /* */\r
+ } BIT; /* */\r
+ } AXIBUSCTL10; /* */\r
+ union { /* AXIRERRCTL0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :8; /* */\r
+ _UDWORD CEURERREN:1; /* CEURERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD IMRDRERREN:1; /* IMRDRERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD IMR21RERREN:1; /* IMR21RERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD IMR20RERREN:1; /* IMR20RERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD ETHRERREN:1; /* ETHRERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD JCURERREN:1; /* JCURERREN */\r
+ _UDWORD :3; /* */\r
+ } BIT; /* */\r
+ } AXIRERRCTL0; /* */\r
+ union { /* AXIRERRCTL1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :12; /* */\r
+ _UDWORD RGP1281RERREN:1; /* RGP1281RERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD RGP1280RERREN:1; /* RGP1280RERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD RGP642RERREN:1; /* RGP642RERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD RGP641RERREN:1; /* RGP641RERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD RGP640RERREN:1; /* RGP640RERREN */\r
+ _UDWORD :3; /* */\r
+ } BIT; /* */\r
+ } AXIRERRCTL1; /* */\r
+ union { /* AXIRERRCTL2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :12; /* */\r
+ _UDWORD VDC505RERREN:1; /* VDC505RERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD VDC504RERREN:1; /* VDC504RERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD VDC503RERREN:1; /* VDC503RERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD VDC502RERREN:1; /* VDC502RERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD VDC501RERREN:1; /* VDC501RERREN */\r
+ _UDWORD :3; /* */\r
+ } BIT; /* */\r
+ } AXIRERRCTL2; /* */\r
+ union { /* AXIRERRCTL3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :12; /* */\r
+ _UDWORD VDC515RERREN:1; /* VDC515RERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD VDC514RERREN:1; /* VDC514RERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD VDC513RERREN:1; /* VDC513RERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD VDC512RERREN:1; /* VDC512RERREN */\r
+ _UDWORD :3; /* */\r
+ _UDWORD VDC511RERREN:1; /* VDC511RERREN */\r
+ _UDWORD :3; /* */\r
+ } BIT; /* */\r
+ } AXIRERRCTL3; /* */\r
+ union { /* AXIRERRST0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :8; /* */\r
+ _UDWORD CEUBRESP:2; /* CEUBRESP */\r
+ _UDWORD CEURRESP:2; /* CEURRESP */\r
+ _UDWORD IMRDBRESP:2; /* IMRDBRESP */\r
+ _UDWORD IMRDRRESP:2; /* IMRDRRESP */\r
+ _UDWORD IMR21BRESP:2; /* IMR21BRESP */\r
+ _UDWORD IMR21RRESP:2; /* IMR21RRESP */\r
+ _UDWORD IMR20BRESP:2; /* IMR20BRESP */\r
+ _UDWORD IMR20RRESP:2; /* IMR20RRESP */\r
+ _UDWORD ETHBRESP:2; /* ETHBRESP */\r
+ _UDWORD ETHRRESP:2; /* ETHRRESP */\r
+ _UDWORD JCUBRESP:2; /* JCUBRESP */\r
+ _UDWORD JCURRESP:2; /* JCURRESP */\r
+ } BIT; /* */\r
+ } AXIRERRST0; /* */\r
+ union { /* AXIRERRST1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :12; /* */\r
+ _UDWORD RGP1281BRESP:2; /* RGP1281BRESP */\r
+ _UDWORD RGP1281RRESP:2; /* RGP1281RRESP */\r
+ _UDWORD RGP1280BRESP:2; /* RGP1280BRESP */\r
+ _UDWORD RGP1280RRESP:2; /* RGP1280RRESP */\r
+ _UDWORD RGP642BRESP:2; /* RGP642BRESP */\r
+ _UDWORD RGP642RRESP:2; /* RGP642RRESP */\r
+ _UDWORD RGP641BRESP:2; /* RGP641BRESP */\r
+ _UDWORD RGP641RRESP:2; /* RGP641RRESP */\r
+ _UDWORD RGP640BRESP:2; /* RGP640BRESP */\r
+ _UDWORD RGP640RRESP:2; /* RGP640RRESP */\r
+ } BIT; /* */\r
+ } AXIRERRST1; /* */\r
+ union { /* AXIRERRST2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :12; /* */\r
+ _UDWORD VDC505BRESP:2; /* VDC505BRESP */\r
+ _UDWORD VDC505RRESP:2; /* VDC505RRESP */\r
+ _UDWORD VDC504BRESP:2; /* VDC504BRESP */\r
+ _UDWORD VDC504RRESP:2; /* VDC504RRESP */\r
+ _UDWORD VDC503BRESP:2; /* VDC503BRESP */\r
+ _UDWORD VDC503RRESP:2; /* VDC503RRESP */\r
+ _UDWORD VDC502BRESP:2; /* VDC502BRESP */\r
+ _UDWORD VDC502RRESP:2; /* VDC502RRESP */\r
+ _UDWORD VDC501BRESP:2; /* VDC501BRESP */\r
+ _UDWORD VDC501RRESP:2; /* VDC501RRESP */\r
+ } BIT; /* */\r
+ } AXIRERRST2; /* */\r
+ union { /* AXIRERRST3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :12; /* */\r
+ _UDWORD VDC515BRESP:2; /* VDC515BRESP */\r
+ _UDWORD VDC515RRESP:2; /* VDC515RRESP */\r
+ _UDWORD VDC514BRESP:2; /* VDC514BRESP */\r
+ _UDWORD VDC514RRESP:2; /* VDC514RRESP */\r
+ _UDWORD VDC513BRESP:2; /* VDC513BRESP */\r
+ _UDWORD VDC513RRESP:2; /* VDC513RRESP */\r
+ _UDWORD VDC512BRESP:2; /* VDC512BRESP */\r
+ _UDWORD VDC512RRESP:2; /* VDC512RRESP */\r
+ _UDWORD VDC511BRESP:2; /* VDC511BRESP */\r
+ _UDWORD VDC511RRESP:2; /* VDC511RRESP */\r
+ } BIT; /* */\r
+ } AXIRERRST3; /* */\r
+ union { /* AXIRERRCLR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :8; /* */\r
+ _UDWORD CEUBRESPCLR:1; /* CEUBRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD CEURRESPCLR:1; /* CEURRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD IMRDBRESPCLR:1; /* IMRDBRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD IMRDRRESPCLR:1; /* IMRDRRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD IMR21BRESPCLR:1; /* IMR21BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD IMR21RRESPCLR:1; /* IMR21RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD IMR20BRESPCLR:1; /* IMR20BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD IMR20RRESPCLR:1; /* IMR20RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD ETHBRESPCLR:1; /* ETHBRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD ETHRRESPCLR:1; /* ETHRRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD JCUBRESPCLR:1; /* JCUBRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD JCURRESPCLR:1; /* JCURRESPCLR */\r
+ _UDWORD :1; /* */\r
+ } BIT; /* */\r
+ } AXIRERRCLR0; /* */\r
+ union { /* AXIRERRCLR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :12; /* */\r
+ _UDWORD RGP1281BRESPCLR:1; /* RGP1281BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD RGP1281RRESPCLR:1; /* RGP1281RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD RGP1280BRESPCLR:1; /* RGP1280BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD RGP1280RRESPCLR:1; /* RGP1280RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD RGP642BRESPCLR:1; /* RGP642BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD RGP642RRESPCLR:1; /* RGP642RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD RGP641BRESPCLR:1; /* RGP641BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD RGP641RRESPCLR:1; /* RGP641RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD RGP640BRESPCLR:1; /* RGP640BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD RGP640RRESPCLR:1; /* RGP640RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ } BIT; /* */\r
+ } AXIRERRCLR1; /* */\r
+ union { /* AXIRERRCLR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :12; /* */\r
+ _UDWORD VDC505BRESPCLR:1; /* VDC505BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC505RRESPCLR:1; /* VDC505RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC504BRESPCLR:1; /* VDC504BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC504RRESPCLR:1; /* VDC504RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC503BRESPCLR:1; /* VDC503BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC503RRESPCLR:1; /* VDC503RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC502BRESPCLR:1; /* VDC502BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC502RRESPCLR:1; /* VDC502RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC501BRESPCLR:1; /* VDC501BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC501RRESPCLR:1; /* VDC501RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ } BIT; /* */\r
+ } AXIRERRCLR2; /* */\r
+ union { /* AXIRERRCLR3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :12; /* */\r
+ _UDWORD VDC515BRESPCLR:1; /* VDC515BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC515RRESPCLR:1; /* VDC515RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC514BRESPCLR:1; /* VDC514BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC514RRESPCLR:1; /* VDC514RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC513BRESPCLR:1; /* VDC513BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC513RRESPCLR:1; /* VDC513RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC512BRESPCLR:1; /* VDC512BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC512RRESPCLR:1; /* VDC512RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC511BRESPCLR:1; /* VDC511BRESPCLR */\r
+ _UDWORD :1; /* */\r
+ _UDWORD VDC511RRESPCLR:1; /* VDC511RRESPCLR */\r
+ _UDWORD :1; /* */\r
+ } BIT; /* */\r
+ } AXIRERRCLR3; /* */\r
+}; /* */\r
+\r
+#define PRR (*(volatile struct st_prr *)0xFCFE1800) /* PRR Address */\r
+\r
+\r
+#endif /* __PRR_IODEFINE_H__ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : riic_iodefine.h\r
+* Version : 0.01\r
+* Device(s) : Aragon\r
+* Tool-Chain : DS-5 Ver 5.8\r
+* ARM Complier \r
+* : \r
+* H/W Platform : Aragon CPU Board\r
+* Description : Aragon Sample Program vecotr.s\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 27.07.2012 0.01 \8eQ\8dl\8e\91\97¿\81FRZ_A1H_05J_121010_11.pdf\r
+*******************************************************************************/\r
+#ifndef __RIIC_IODEFINE_H__\r
+#define __RIIC_IODEFINE_H__\r
+\r
+#include "typedefine.h"\r
+\r
+typedef union { /* RIICnICSARy */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SVA0:1; /* SVA0 */\r
+ _UDWORD SVA:9; /* SVA */\r
+ _UDWORD :5; /* */\r
+ _UDWORD FSy:1; /* FSy */\r
+ _UDWORD :16; /* */\r
+ } BIT; /* */\r
+} RIICnICSARy; /* */\r
+\r
+struct st_riic_n { /* struct RIIC */\r
+ union { /* RIICnICCR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SDAI:1; /* SDAI */\r
+ _UDWORD SCLI:1; /* SCLI */\r
+ _UDWORD SDAO:1; /* SDAO */\r
+ _UDWORD SCLO:1; /* SCLO */\r
+ _UDWORD SOWP:1; /* SOWP */\r
+ _UDWORD CLO:1; /* CLO */\r
+ _UDWORD IICRST:1; /* IICRST */\r
+ _UDWORD ICE:1; /* ICE */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } RIICnICCR1; /* */\r
+ union { /* RIICnICCR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :1; /* */\r
+ _UDWORD ST:1; /* ST */\r
+ _UDWORD RS:1; /* RS */\r
+ _UDWORD SP:1; /* SP */\r
+ _UDWORD :1; /* */\r
+ _UDWORD TRS:1; /* TRS */\r
+ _UDWORD MST:1; /* MST */\r
+ _UDWORD BBSY:1; /* BBSY */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } RIICnICCR2; /* */\r
+ union { /* RIICnICMR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD BC:3; /* BC */\r
+ _UDWORD BCWP:1; /* BCWP */\r
+ _UDWORD CKS:3; /* CKS */\r
+ _UDWORD MTWP:1; /* MTWP */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } RIICnICMR1; /* */\r
+ union { /* RIICnICMR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TMOS:1; /* TMOS */\r
+ _UDWORD TMOL:1; /* TMOL */\r
+ _UDWORD TMOH:1; /* TMOH */\r
+ _UDWORD :1; /* */\r
+ _UDWORD SDDL:3; /* SDDL */\r
+ _UDWORD DLCS:1; /* DLCS */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } RIICnICMR2; /* */\r
+ union { /* RIICnICMR3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD NF:2; /* NF */\r
+ _UDWORD ACKBR:1; /* ACKBR */\r
+ _UDWORD ACKBT:1; /* ACKBT */\r
+ _UDWORD ACKWP:1; /* ACKWP */\r
+ _UDWORD RDRFS:1; /* RDRFS */\r
+ _UDWORD WAIT:1; /* WAIT */\r
+ _UDWORD SMBS:1; /* SMBS */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } RIICnICMR3; /* */\r
+ union { /* RIICnICFER */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TMOE:1; /* TMOE */\r
+ _UDWORD MALE:1; /* MALE */\r
+ _UDWORD NALE:1; /* NALE */\r
+ _UDWORD SALE:1; /* SALE */\r
+ _UDWORD NACKE:1; /* NACKE */\r
+ _UDWORD NFE:1; /* NFE */\r
+ _UDWORD SCLE:1; /* SCLE */\r
+ _UDWORD FMPE:1; /* FMPE */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } RIICnICFER; /* */\r
+ union { /* RIICnICSER */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SAR0E:1; /* SAR0E */\r
+ _UDWORD SAR1E:1; /* SAR1E */\r
+ _UDWORD SAR2E:1; /* SAR2E */\r
+ _UDWORD GCAE:1; /* GCAE */\r
+ _UDWORD :1; /* */\r
+ _UDWORD DIDE:1; /* DIDE */\r
+ _UDWORD :1; /* */\r
+ _UDWORD HOAE:1; /* HOAE */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } RIICnICSER; /* */\r
+ union { /* RIICnICIER */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TMOIE:1; /* TMOIE */\r
+ _UDWORD ALIE:1; /* ALIE */\r
+ _UDWORD STIE:1; /* STIE */\r
+ _UDWORD SPIE:1; /* SPIE */\r
+ _UDWORD NAKIE:1; /* NAKIE */\r
+ _UDWORD RIE:1; /* RIE */\r
+ _UDWORD TEIE:1; /* TEIE */\r
+ _UDWORD TIE:1; /* TIE */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } RIICnICIER; /* */\r
+ union { /* RIICnICSR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD AAS0:1; /* AAS0 */\r
+ _UDWORD AAS1:1; /* AAS1 */\r
+ _UDWORD AAS2:1; /* AAS2 */\r
+ _UDWORD GCA:1; /* GCA */\r
+ _UDWORD :1; /* */\r
+ _UDWORD DID:1; /* DID */\r
+ _UDWORD :1; /* */\r
+ _UDWORD HOA:1; /* HOA */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } RIICnICSR1; /* */\r
+ union { /* RIICnICSR2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TMOF:1; /* TMOF */\r
+ _UDWORD AL:1; /* AL */\r
+ _UDWORD START:1; /* START */\r
+ _UDWORD STOP:1; /* STOP */\r
+ _UDWORD NACKF:1; /* NACKF */\r
+ _UDWORD RDRF:1; /* RDRF */\r
+ _UDWORD TEND:1; /* TEND */\r
+ _UDWORD TDRE:1; /* TDRE */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } RIICnICSR2; /* */\r
+ RIICnICSARy RIICnICSAR0; /* RIICnICSAR0 */\r
+ RIICnICSARy RIICnICSAR1; /* RIICnICSAR1 */\r
+ RIICnICSARy RIICnICSAR2; /* RIICnICSAR2 */\r
+ union { /* RIICnICBRL */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD BRL:5; /* BRL */\r
+ _UDWORD :27; /* */\r
+ } BIT; /* */\r
+ } RIICnICBRL; /* */\r
+ union { /* RIICnICBRH */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD BRH:5; /* BRH */\r
+ _UDWORD :27; /* */\r
+ } BIT; /* */\r
+ } RIICnICBRH; /* */\r
+ union { /* RIICnICDRT */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ICDRS:8; /* ICDRS */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } RIICnICDRT; /* */\r
+ union { /* RIICnICDRR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ICDRR:8; /* ICDRR */\r
+ _UDWORD :24; /* */\r
+ } BIT; /* */\r
+ } RIICnICDRR; /* */\r
+}; /* */\r
+\r
+#define RIIC_0 (*(volatile struct st_riic_n *)0xFCFEE000) /* RIIC_0 Address */\r
+#define RIIC_1 (*(volatile struct st_riic_n *)0xFCFEE400) /* RIIC_1 Address */\r
+#define RIIC_2 (*(volatile struct st_riic_n *)0xFCFEE800) /* RIIC_2 Address */\r
+#define RIIC_3 (*(volatile struct st_riic_n *)0xFCFEEC00) /* RIIC_3 Address */\r
+\r
+\r
+#endif /* __RIIC_IODEFINE_H__ */\r
+\r
+/* End of File */\r
--- /dev/null
+/******************************************************************************\r
+* DISCLAIMER\r
+*\r
+* This software is supplied by Renesas Electronics Corporation and is only \r
+* intended for use with Renesas products. No other uses are authorized.\r
+*\r
+* This software is owned by Renesas Electronics Corporation and is protected under \r
+* all applicable laws, including copyright laws.\r
+*\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES \r
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, \r
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A \r
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY \r
+* DISCLAIMED.\r
+*\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES \r
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS\r
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+*\r
+* Renesas reserves the right, without notice, to make changes to this \r
+* software and to discontinue the availability of this software.\r
+* By using this software, you agree to the additional terms and \r
+* conditions found by accessing the following link: \r
+* http://www.renesas.com/disclaimer\r
+********************************************************************************\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+**************************** Technical reference data **************************\r
+* System Name : \r
+* File Name : scif_iodefine.h\r
+* Abstract : \r
+* Version : 1.00.00\r
+* Device : ARM\r
+* Tool-Chain : \r
+* OS : None\r
+* H/W Platform: \r
+* Description : \r
+********************************************************************************\r
+* History : Mar.06,2012 Ver.1.00.00\r
+*******************************************************************************/\r
+#ifndef __SCIF_IODEFINE_H__\r
+#define __SCIF_IODEFINE_H__\r
+\r
+#include "typedefine.h"\r
+\r
+struct st_scif_n { /* struct SCIF */\r
+ union { /* SCSMR_0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD CKS:2; /* CKS */\r
+ _UWORD :1; /* */\r
+ _UWORD STOP:1; /* STOP */\r
+ _UWORD OE:1; /* O/E */\r
+ _UWORD PE:1; /* PE */\r
+ _UWORD CHR:1; /* CHR */\r
+ _UWORD CA:1; /* C/A */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } SCSMR; /* */\r
+ _UBYTE wk0[2]; /* */\r
+ union { /* SCBRR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE D:8; /* D */\r
+ } BIT; /* */\r
+ } SCBRR; /* */\r
+ _UBYTE wk1[3]; /* */\r
+ union { /* SCSCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD CKE:2; /* CKE */\r
+ _UWORD :1; /* */\r
+ _UWORD REIE:1; /* REIE */\r
+ _UWORD RE:1; /* RE */\r
+ _UWORD TE:1; /* TE */\r
+ _UWORD RIE:1; /* RIE */\r
+ _UWORD TIE:1; /* TIE */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } SCSCR; /* */\r
+ _UBYTE wk2[2]; /* */\r
+ union { /* SCFTDR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE D:8; /* D */\r
+ } BIT; /* */\r
+ } SCFTDR; /* */\r
+ _UBYTE wk3[3]; /* */\r
+ union { /* SCFSR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD DR:1; /* DR */\r
+ _UWORD RDF:1; /* RDF */\r
+ _UWORD PER:1; /* PER */\r
+ _UWORD FER:1; /* FER */\r
+ _UWORD BRK:1; /* BRK */\r
+ _UWORD TDFE:1; /* TDFE */\r
+ _UWORD TEND:1; /* TEND */\r
+ _UWORD ER:1; /* ER */\r
+ _UWORD FERN:4; /* FERN */\r
+ _UWORD PERN:4; /* PERN */\r
+ } BIT; /* */\r
+ } SCFSR; /* */\r
+ _UBYTE wk4[2]; /* */\r
+ union { /* SCFRDR */\r
+ _UBYTE BYTE; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UBYTE D:8; /* D */\r
+ } BIT; /* */\r
+ } SCFRDR; /* */\r
+ _UBYTE wk5[3]; /* */\r
+ union { /* SCFCR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD LOOP:1; /* LOOP */\r
+ _UWORD RFRST:1; /* RFRST */\r
+ _UWORD TFRST:1; /* TFRST */\r
+ _UWORD MCE:1; /* MCE */\r
+ _UWORD TTRG:2; /* TTRG */\r
+ _UWORD RTRG:2; /* RTRG */\r
+ _UWORD RSTRG:3; /* RSTRG */\r
+ _UWORD :5; /* */\r
+ } BIT; /* */\r
+ } SCFCR; /* */\r
+ _UBYTE wk6[2]; /* */\r
+ union { /* SCFDR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD R:5; /* R */\r
+ _UWORD :3; /* */\r
+ _UWORD T:5; /* T */\r
+ _UWORD :3; /* */\r
+ } BIT; /* */\r
+ } SCFDR; /* */\r
+ _UBYTE wk7[2]; /* */\r
+ union { /* SCSPTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD SPB2DT:1; /* SPB2DT */\r
+ _UWORD SPB2IO:1; /* SPB2IO */\r
+ _UWORD SCKDT:1; /* SCKDT */\r
+ _UWORD SCKIO:1; /* SCKIO */\r
+ _UWORD CTSDT:1; /* CTSDT */\r
+ _UWORD CTSIO:1; /* CTSIO */\r
+ _UWORD RTSDT:1; /* RTSDT */\r
+ _UWORD RTSIO:1; /* RTSIO */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } SCSPTR; /* */\r
+ _UBYTE wk8[2]; /* */\r
+ union { /* SCLSR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD ORER:1; /* ORER */\r
+ _UWORD :15; /* */\r
+ } BIT; /* */\r
+ } SCLSR; /* */\r
+ _UBYTE wk9[2]; /* */\r
+ union { /* SCEMR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD ABCS:1; /* ABCS */\r
+ _UWORD :6; /* */\r
+ _UWORD BGDM:1; /* BGDM */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } SCEMR; /* */\r
+}; /* */\r
+\r
+#define SCIF0 (*(volatile struct st_scif_n *)0xE8007000) /* SCIF0 Address */\r
+#define SCIF1 (*(volatile struct st_scif_n *)0xE8007800) /* SCIF1 Address */\r
+#define SCIF2 (*(volatile struct st_scif_n *)0xE8008000) /* SCIF2 Address */\r
+#define SCIF3 (*(volatile struct st_scif_n *)0xE8008800) /* SCIF3 Address */\r
+#define SCIF4 (*(volatile struct st_scif_n *)0xE8009000) /* SCIF4 Address */\r
+#define SCIF5 (*(volatile struct st_scif_n *)0xE8009800) /* SCIF5 Address */\r
+#define SCIF6 (*(volatile struct st_scif_n *)0xE800A000) /* SCIF6 Address */\r
+#define SCIF7 (*(volatile struct st_scif_n *)0xE800A800) /* SCIF7 Address */\r
+\r
+\r
+#endif /* __SCIF_IODEFINE_H__ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : spibsc_iodefine.h \r
+* Version : 0.01\r
+* Device(s) : \r
+* Tool-Chain : DS-5 Ver 5.8\r
+* ARM Complier \r
+* : \r
+* H/W Platform : CPU Board\r
+* Description : \r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* History : 05.11.2012 0.01 Version Description\r
+*******************************************************************************/\r
+#ifndef __SPIBSC_IODEFINE_H__\r
+#define __SPIBSC_IODEFINE_H__\r
+\r
+#include "typedefine.h"\r
+\r
+\r
+/****************************************************************/\r
+/* SPIBSC */\r
+/****************************************************************/\r
+struct st_spibsc_n { /* struct SPIBSC*/\r
+ union { /* CMNCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD BSZ:2; /* BSZ */\r
+ _UDWORD :1; /* */\r
+ _UDWORD CPOL:1; /* CPOL */\r
+ _UDWORD SSLP:1; /* SSLP */\r
+ _UDWORD CPHAR:1; /* CPHAR */\r
+ _UDWORD CPHAT:1; /* CPHAT */\r
+ _UDWORD :1; /* */\r
+ _UDWORD IO0FV:2; /* IO0FV */\r
+ _UDWORD :2; /* */\r
+ _UDWORD IO2FV:2; /* IO2FV */\r
+ _UDWORD IO3FV:2; /* IO3FV */\r
+ _UDWORD MOIIO0:2; /* MOIIO0 */\r
+ _UDWORD MOIIO1:2; /* MOIIO1 */\r
+ _UDWORD MOIIO2:2; /* MOIIO2 */\r
+ _UDWORD MOIIO3:2; /* MOIIO3 */\r
+ _UDWORD :7; /* */\r
+ _UDWORD MD:1; /* MD */\r
+ } BIT; /* */\r
+ } CMNCR; /* */\r
+ union { /* SSLDR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SCKDL:3; /* SCKDL */\r
+ _UDWORD :5; /* */\r
+ _UDWORD SLNDL:3; /* SLNDL */\r
+ _UDWORD :5; /* */\r
+ _UDWORD SPNDL:3; /* SPNDL */\r
+ _UDWORD :13; /* */\r
+ } BIT; /* */\r
+ } SSLDR; /* */\r
+ union { /* SPBCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD BRDV:2; /* BRDV */\r
+ _UDWORD :6; /* */\r
+ _UDWORD SPBR:8; /* SPBR */\r
+ _UDWORD :16; /* */\r
+ } BIT; /* */\r
+ } SPBCR; /* */\r
+ union { /* DRCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SSLE:1; /* SSLE */\r
+ _UDWORD :7; /* */\r
+ _UDWORD RBE:1; /* RBE */\r
+ _UDWORD RCF:1; /* RCF */\r
+ _UDWORD :6; /* */\r
+ _UDWORD RBURST:4; /* RBURST */\r
+ _UDWORD :4; /* */\r
+ _UDWORD SSLN:1; /* SSLN */\r
+ _UDWORD :7; /* */\r
+ } BIT; /* */\r
+ } DRCR; /* */\r
+ union { /* DRCMR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD OCMD:8; /* OCMD */\r
+ _UDWORD :8; /* */\r
+ _UDWORD CMD:8; /* CMD */\r
+ _UDWORD :8; /* */\r
+ } BIT; /* */\r
+ } DRCMR; /* */\r
+ union { /* DREAR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD EAC:3; /* EAC */\r
+ _UDWORD :13; /* */\r
+ _UDWORD EAV:8; /* EAV */\r
+ _UDWORD :8; /* */\r
+ } BIT; /* */\r
+ } DREAR; /* */\r
+ union { /* DROPR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD OPD0:8; /* OPD0 */\r
+ _UDWORD OPD1:8; /* OPD1 */\r
+ _UDWORD OPD2:8; /* OPD2 */\r
+ _UDWORD OPD3:8; /* OPD3 */\r
+ } BIT; /* */\r
+ } DROPR; /* */\r
+ union { /* DRENR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD :4; /* */\r
+ _UDWORD OPDE:4; /* OPDE */\r
+ _UDWORD ADE:4; /* ADE */\r
+ _UDWORD OCDE:1; /* OCDE */\r
+ _UDWORD :1; /* */\r
+ _UDWORD CDE:1; /* CDE */\r
+ _UDWORD DME:1; /* DME */\r
+ _UDWORD DRDB:2; /* DRDB */\r
+ _UDWORD :2; /* */\r
+ _UDWORD OPDB:2; /* OPDB */\r
+ _UDWORD :2; /* */\r
+ _UDWORD ADB:2; /* ADB */\r
+ _UDWORD :2; /* */\r
+ _UDWORD OCDB:2; /* OCDB */\r
+ _UDWORD CDB:2; /* CDB */\r
+ } BIT; /* */\r
+ } DRENR; /* */\r
+ union { /* SMCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPIE:1; /* SPIE */\r
+ _UDWORD SPIWE:1; /* SPIWE */\r
+ _UDWORD SPIRE:1; /* SPIRE */\r
+ _UDWORD :5; /* */\r
+ _UDWORD SSLKP:1; /* SSLKP */\r
+ _UDWORD :23; /* */\r
+ } BIT; /* */\r
+ } SMCR; /* */\r
+ union { /* SMCMR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD OCMD:8; /* OCMD */\r
+ _UDWORD :8; /* */\r
+ _UDWORD CMD:8; /* CMD */\r
+ _UDWORD :8; /* */\r
+ } BIT; /* */\r
+ } SMCMR; /* */\r
+ union { /* SMADR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD ADR:32; /* ADR */\r
+ } BIT; /* */\r
+ } SMADR; /* */\r
+ union { /* SMOPR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD OPD0:8; /* OPD0 */\r
+ _UDWORD OPD1:8; /* OPD1 */\r
+ _UDWORD OPD2:8; /* OPD2 */\r
+ _UDWORD OPD3:8; /* OPD3 */\r
+ } BIT; /* */\r
+ } SMOPR; /* */\r
+ union { /* SMENR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPIDE:4; /* SPIDE */\r
+ _UDWORD OPDE:4; /* OPDE */\r
+ _UDWORD ADE:4; /* ADE */\r
+ _UDWORD OCDE:1; /* OCDE */\r
+ _UDWORD :1; /* */\r
+ _UDWORD CDE:1; /* CDE */\r
+ _UDWORD DME:1; /* DME */\r
+ _UDWORD SPIDB:2; /* SPIDB */\r
+ _UDWORD :2; /* */\r
+ _UDWORD OPDB:2; /* OPDB */\r
+ _UDWORD :2; /* */\r
+ _UDWORD ADB:2; /* ADB */\r
+ _UDWORD :2; /* */\r
+ _UDWORD OCDB:2; /* OCDB */\r
+ _UDWORD CDB:2; /* CDB */\r
+ } BIT; /* */\r
+ } SMENR; /* */\r
+ _UBYTE wk0[4]; /* */\r
+ union { /* SMRDR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD L; /* Low */\r
+ _UWORD H; /* High */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE LL; /* Low, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE HH; /* High, High */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD RDATA0:32; /* RDATA0 */\r
+ } BIT; /* */\r
+ } SMRDR0; /* */\r
+ union { /* SMRDR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD L; /* Low */\r
+ _UWORD H; /* High */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE LL; /* Low, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE HH; /* High, High */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD RDATA1:32; /* RDATA1 */\r
+ } BIT; /* */\r
+ } SMRDR1; /* */\r
+ union { /* SMWDR0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD L; /* Low */\r
+ _UWORD H; /* High */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE LL; /* Low, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE HH; /* High, High */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD WDATA0:32; /* WDATA0 */\r
+ } BIT; /* */\r
+ } SMWDR0; /* */\r
+ union { /* SMWDR1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Word Access */\r
+ _UWORD L; /* Low */\r
+ _UWORD H; /* High */\r
+ } WORD; /* */\r
+ struct { /* Byte Access */\r
+ _UBYTE LL; /* Low, Low */\r
+ _UBYTE LH; /* Low, High */\r
+ _UBYTE HL; /* High, Low */\r
+ _UBYTE HH; /* High, High */\r
+ } BYTE; /* */\r
+ struct { /* Bit Access */\r
+ _UDWORD WDATA1:32; /* WDATA1 */\r
+ } BIT; /* */\r
+ } SMWDR1; /* */\r
+ union { /* CMNSR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD TEND:1; /* TEND */\r
+ _UDWORD SSLF:1; /* SSLF */\r
+ _UDWORD :30; /* */\r
+ } BIT; /* */\r
+ } CMNSR; /* */\r
+ _UBYTE wk1[12]; /* */\r
+ union { /* DRDMCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DMCYC:3; /* */\r
+ _UDWORD :13; /* */\r
+ _UDWORD DMDB:2; /* */\r
+ _UDWORD :14; /* */\r
+ } BIT; /* */\r
+ } DRDMCR; /* */\r
+ union { /* DRDRENR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DRDRE:1; /* */\r
+ _UDWORD :3; /* */\r
+ _UDWORD OPDRE:1; /* */\r
+ _UDWORD :3; /* */\r
+ _UDWORD ADDRE:1; /* */\r
+ _UDWORD :23; /* */\r
+ } BIT; /* */\r
+ } DRDRENR; /* */\r
+\r
+ union { /* SMDMCR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD DMCYC:3; /* */\r
+ _UDWORD :13; /* */\r
+ _UDWORD DMDB:2; /* */\r
+ _UDWORD :14; /* */\r
+ } BIT; /* */\r
+ } SMDMCR; /* */\r
+ union { /* SMDRENR */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD SPIDRE:1; /* */\r
+ _UDWORD :3; /* */\r
+ _UDWORD OPDRE:1; /* */\r
+ _UDWORD :3; /* */\r
+ _UDWORD ADDRE:1; /* */\r
+ _UDWORD :23; /* */\r
+ } BIT; /* */\r
+ } SMDRENR; /* */\r
+}; /* */\r
+\r
+#define SPIBSC0 (*(volatile struct st_spibsc_n *)0x3FEFA000)\r
+#define SPIBSC1 (*(volatile struct st_spibsc_n *)0x3FEFB000)\r
+\r
+\r
+#endif /* __SPIBSC_IODEFINE_H__ */\r
--- /dev/null
+/******************************************************************************\r
+* DISCLAIMER\r
+*\r
+* This software is supplied by Renesas Electronics Corporation and is only \r
+* intended for use with Renesas products. No other uses are authorized.\r
+*\r
+* This software is owned by Renesas Electronics Corporation and is protected under \r
+* all applicable laws, including copyright laws.\r
+*\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES \r
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, \r
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A \r
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY \r
+* DISCLAIMED.\r
+*\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES \r
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS\r
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+*\r
+* Renesas reserves the right, without notice, to make changes to this \r
+* software and to discontinue the availability of this software.\r
+* By using this software, you agree to the additional terms and \r
+* conditions found by accessing the following link: \r
+* http://www.renesas.com/disclaimer\r
+********************************************************************************\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+**************************** Technical reference data **************************\r
+* System Name : \r
+* File Name : usb_iodefine.h\r
+* Abstract : \r
+* Version : 1.00.00\r
+* Device : ARM\r
+* Tool-Chain : \r
+* OS : None\r
+* H/W Platform: \r
+* Description : \r
+********************************************************************************\r
+* History : Mar.06,2012 Ver.1.00.00\r
+*******************************************************************************/\r
+#ifndef __USB_IODEFINE_H__\r
+#define __USB_IODEFINE_H__\r
+\r
+#include "typedefine.h"\r
+\r
+struct st_usb_n { /* struct USB */\r
+ union { /* SYSCFG */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD USBE:1; /* USBE */\r
+ _UWORD UPLLE:1; /* UPLLE */\r
+ _UWORD UCKSEL:1; /* UCKSEL */\r
+ _UWORD :1; /* */\r
+ _UWORD DPRPU:1; /* DPRPU */\r
+ _UWORD DRPD:1; /* DRPD */\r
+ _UWORD DCFM:1; /* DCFM */\r
+ _UWORD HSE:1; /* HSE */\r
+ _UWORD :8; /* */\r
+ } BIT; /* */\r
+ } SYSCFG; /* */\r
+ union { /* BUSWAIT */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BWAIT:6; /* BWAIT */\r
+ _UWORD :10; /* */\r
+ } BIT; /* */\r
+ } BUSWAIT; /* */\r
+ union { /* SYSSTS0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD LNST:2; /* LNST */\r
+ _UWORD :14; /* */\r
+ } BIT; /* */\r
+ } SYSSTS0; /* */\r
+ _UBYTE wk0[2]; /* */\r
+ union { /* DVSTCTR0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD RHST:3; /* RHST */\r
+ _UWORD :1; /* */\r
+ _UWORD UACT:1; /* UACT */\r
+ _UWORD RESUME:1; /* RESUME */\r
+ _UWORD USBRST:1; /* USBRST */\r
+ _UWORD RWUPE:1; /* RWUPE */\r
+ _UWORD WKUP:1; /* WKUP */\r
+ _UWORD :7; /* */\r
+ } BIT; /* */\r
+ } DVSTCTR0; /* */\r
+ _UBYTE wk1[2]; /* */\r
+ union { /* UTEST */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD UTST:4; /* UTST */\r
+ _UWORD :12; /* */\r
+ } BIT; /* */\r
+ } UTEST; /* */\r
+ _UBYTE wk2[2]; /* */\r
+ union { /* D0FBCFG */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :4; /* */\r
+ _UWORD TENDE:1; /* TENDE */\r
+ _UWORD :7; /* */\r
+ _UWORD DFACC:2; /* DFACC */\r
+ _UWORD :2; /* */\r
+ } BIT; /* */\r
+ } D0FBCFG; /* */\r
+ union { /* D1FBCFG */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :4; /* */\r
+ _UWORD TENDE:1; /* TENDE */\r
+ _UWORD :7; /* */\r
+ _UWORD DFACC:2; /* DFACC */\r
+ _UWORD :2; /* */\r
+ } BIT; /* */\r
+ } D1FBCFG; /* */\r
+ union { /* CFIFO */\r
+ _UDWORD LONG; /* Long Access */\r
+ _UWORD WORD[2]; /* Word Access */\r
+ _UBYTE BYTE[4]; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } CFIFO; /* */\r
+ union { /* D0FIFO */\r
+ _UDWORD LONG; /* Long Access */\r
+ _UWORD WORD[2]; /* Word Access */\r
+ _UBYTE BYTE[4]; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D0FIFO; /* */\r
+ union { /* D1FIFO */\r
+ _UDWORD LONG; /* Long Access */\r
+ _UWORD WORD[2]; /* Word Access */\r
+ _UBYTE BYTE[4]; /* Byte Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D1FIFO; /* */\r
+ union { /* CFIFOSEL */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD CURPIPE:4; /* CURPIPE */\r
+ _UWORD :1; /* */\r
+ _UWORD ISEL:1; /* ISEL */\r
+ _UWORD :2; /* */\r
+ _UWORD BIGEND:1; /* BIGEND */\r
+ _UWORD :1; /* */\r
+ _UWORD MBW:2; /* MBW */\r
+ _UWORD :2; /* */\r
+ _UWORD REW:1; /* REW */\r
+ _UWORD RCNT:1; /* RCNT */\r
+ } BIT; /* */\r
+ } CFIFOSEL; /* */\r
+ union { /* CFIFOCTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD DTLN:12; /* DTLN */\r
+ _UWORD :1; /* */\r
+ _UWORD FRDY:1; /* FRDY */\r
+ _UWORD BCLR:1; /* BCLR */\r
+ _UWORD BVAL:1; /* BVAL */\r
+ } BIT; /* */\r
+ } CFIFOCTR; /* */\r
+ _UBYTE wk3[4]; /* */\r
+ union { /* D0FIFOSEL */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD CURPIPE:4; /* CURPIPE */\r
+ _UWORD :4; /* */\r
+ _UWORD BIGEND:1; /* BIGEND */\r
+ _UWORD :1; /* */\r
+ _UWORD MBW:2; /* MBW */\r
+ _UWORD DREQE:1; /* DREQE */\r
+ _UWORD DCLRM:1; /* DCLRM */\r
+ _UWORD REW:1; /* REW */\r
+ _UWORD RCNT:1; /* RCNT */\r
+ } BIT; /* */\r
+ } D0FIFOSEL; /* */\r
+ union { /* D0FIFOCTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD DTLN:12; /* DTLN */\r
+ _UWORD :1; /* */\r
+ _UWORD FRDY:1; /* FRDY */\r
+ _UWORD BCLR:1; /* BCLR */\r
+ _UWORD BVAL:1; /* BVAL */\r
+ } BIT; /* */\r
+ } D0FIFOCTR; /* */\r
+ union { /* D1FIFOSEL */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD CURPIPE:4; /* CURPIPE */\r
+ _UWORD :4; /* */\r
+ _UWORD BIGEND:1; /* BIGEND */\r
+ _UWORD :1; /* */\r
+ _UWORD MBW:2; /* MBW */\r
+ _UWORD DREQE:1; /* DREQE */\r
+ _UWORD DCLRM:1; /* DCLRM */\r
+ _UWORD REW:1; /* REW */\r
+ _UWORD RCNT:1; /* RCNT */\r
+ } BIT; /* */\r
+ } D1FIFOSEL; /* */\r
+ union { /* D1FIFOCTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD DTLN:12; /* DTLN */\r
+ _UWORD :1; /* */\r
+ _UWORD FRDY:1; /* FRDY */\r
+ _UWORD BCLR:1; /* BCLR */\r
+ _UWORD BVAL:1; /* BVAL */\r
+ } BIT; /* */\r
+ } D1FIFOCTR; /* */\r
+ union { /* INTENB0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD BRDYE:1; /* BRDYE */\r
+ _UWORD NRDYE:1; /* NRDYE */\r
+ _UWORD BEMPE:1; /* BEMPE */\r
+ _UWORD CTRE:1; /* CTRE */\r
+ _UWORD DVSE:1; /* DVSE */\r
+ _UWORD SOFE:1; /* SOFE */\r
+ _UWORD RSME:1; /* RSME */\r
+ _UWORD VBSE:1; /* VBSE */\r
+ } BIT; /* */\r
+ } INTENB0; /* */\r
+ union { /* INTENB1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :4; /* */\r
+ _UWORD SACKE:1; /* SACKE */\r
+ _UWORD SIGNE:1; /* SIGNE */\r
+ _UWORD EOFERRE:1; /* EOFERRE */\r
+ _UWORD :4; /* */\r
+ _UWORD ATTCHE:1; /* ATTCHE */\r
+ _UWORD DTCHE:1; /* DTCHE */\r
+ _UWORD :1; /* */\r
+ _UWORD BCHGE:1; /* BCHGE */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } INTENB1; /* */\r
+ _UBYTE wk4[2]; /* */\r
+ union { /* BRDYENB */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PIPE0BRDYE:1; /* PIPE0BRDYE */\r
+ _UWORD PIPE1BRDYE:1; /* PIPE1BRDYE */\r
+ _UWORD PIPE2BRDYE:1; /* PIPE2BRDYE */\r
+ _UWORD PIPE3BRDYE:1; /* PIPE3BRDYE */\r
+ _UWORD PIPE4BRDYE:1; /* PIPE4BRDYE */\r
+ _UWORD PIPE5BRDYE:1; /* PIPE5BRDYE */\r
+ _UWORD PIPE6BRDYE:1; /* PIPE6BRDYE */\r
+ _UWORD PIPE7BRDYE:1; /* PIPE7BRDYE */\r
+ _UWORD PIPE8BRDYE:1; /* PIPE8BRDYE */\r
+ _UWORD PIPE9BRDYE:1; /* PIPE9BRDYE */\r
+ _UWORD PIPEABRDYE:1; /* PIPEABRDYE */\r
+ _UWORD PIPEBBRDYE:1; /* PIPEBBRDYE */\r
+ _UWORD PIPECBRDYE:1; /* PIPECBRDYE */\r
+ _UWORD PIPEDBRDYE:1; /* PIPEDBRDYE */\r
+ _UWORD PIPEEBRDYE:1; /* PIPEEBRDYE */\r
+ _UWORD PIPEFBRDYE:1; /* PIPEFBRDYE */\r
+ } BIT; /* */\r
+ } BRDYENB; /* */\r
+ union { /* NRDYENB */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PIPE0NRDYE:1; /* PIPE0NRDYE */\r
+ _UWORD PIPE1NRDYE:1; /* PIPE1NRDYE */\r
+ _UWORD PIPE2NRDYE:1; /* PIPE2NRDYE */\r
+ _UWORD PIPE3NRDYE:1; /* PIPE3NRDYE */\r
+ _UWORD PIPE4NRDYE:1; /* PIPE4NRDYE */\r
+ _UWORD PIPE5NRDYE:1; /* PIPE5NRDYE */\r
+ _UWORD PIPE6NRDYE:1; /* PIPE6NRDYE */\r
+ _UWORD PIPE7NRDYE:1; /* PIPE7NRDYE */\r
+ _UWORD PIPE8NRDYE:1; /* PIPE8NRDYE */\r
+ _UWORD PIPE9NRDYE:1; /* PIPE9NRDYE */\r
+ _UWORD PIPEANRDYE:1; /* PIPEANRDYE */\r
+ _UWORD PIPEBNRDYE:1; /* PIPEBNRDYE */\r
+ _UWORD PIPECNRDYE:1; /* PIPECNRDYE */\r
+ _UWORD PIPEDNRDYE:1; /* PIPEDNRDYE */\r
+ _UWORD PIPEENRDYE:1; /* PIPEENRDYE */\r
+ _UWORD PIPEFNRDYE:1; /* PIPEFNRDYE */\r
+ } BIT; /* */\r
+ } NRDYENB; /* */\r
+ union { /* BEMPENB */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PIPE0BEMPE:1; /* PIPE0BEMPE */\r
+ _UWORD PIPE1BEMPE:1; /* PIPE1BEMPE */\r
+ _UWORD PIPE2BEMPE:1; /* PIPE2BEMPE */\r
+ _UWORD PIPE3BEMPE:1; /* PIPE3BEMPE */\r
+ _UWORD PIPE4BEMPE:1; /* PIPE4BEMPE */\r
+ _UWORD PIPE5BEMPE:1; /* PIPE5BEMPE */\r
+ _UWORD PIPE6BEMPE:1; /* PIPE6BEMPE */\r
+ _UWORD PIPE7BEMPE:1; /* PIPE7BEMPE */\r
+ _UWORD PIPE8BEMPE:1; /* PIPE8BEMPE */\r
+ _UWORD PIPE9BEMPE:1; /* PIPE9BEMPE */\r
+ _UWORD PIPEABEMPE:1; /* PIPEABEMPE */\r
+ _UWORD PIPEBBEMPE:1; /* PIPEBBEMPE */\r
+ _UWORD PIPECBEMPE:1; /* PIPECBEMPE */\r
+ _UWORD PIPEDBEMPE:1; /* PIPEDBEMPE */\r
+ _UWORD PIPEEBEMPE:1; /* PIPEEBEMPE */\r
+ _UWORD PIPEFBEMPE:1; /* PIPEFBEMPE */\r
+ } BIT; /* */\r
+ } BEMPENB; /* */\r
+ union { /* SOFCFG */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD BRDYM:1; /* BRDYM */\r
+ _UWORD :1; /* */\r
+ _UWORD TRNENSEL:1; /* TRNENSEL */\r
+ _UWORD :7; /* */\r
+ } BIT; /* */\r
+ } SOFCFG; /* */\r
+ _UBYTE wk5[2]; /* */\r
+ union { /* INTSTS0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD CTSQ:3; /* CTSQ */\r
+ _UWORD VALID:1; /* VALID */\r
+ _UWORD DVSQ:3; /* DVSQ */\r
+ _UWORD VBSTS:1; /* VBSTS */\r
+ _UWORD BRDY:1; /* BRDY */\r
+ _UWORD NRDY:1; /* NRDY */\r
+ _UWORD BEMP:1; /* BEMP */\r
+ _UWORD CTRT:1; /* CTRT */\r
+ _UWORD DVST:1; /* DVST */\r
+ _UWORD SOFR:1; /* SOFR */\r
+ _UWORD RESM:1; /* RESM */\r
+ _UWORD VBINT:1; /* VBINT */\r
+ } BIT; /* */\r
+ } INTSTS0; /* */\r
+ union { /* INTSTS1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :4; /* */\r
+ _UWORD SACK:1; /* SACK */\r
+ _UWORD SIGN:1; /* SIGN */\r
+ _UWORD EOFERR:1; /* EOFERR */\r
+ _UWORD :4; /* */\r
+ _UWORD ATTCH:1; /* ATTCH */\r
+ _UWORD DTCH:1; /* DTCH */\r
+ _UWORD :1; /* */\r
+ _UWORD BCHG:1; /* BCHG */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } INTSTS1; /* */\r
+ _UBYTE wk6[2]; /* */\r
+ union { /* BRDYSTS */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PIPE0BRDY:1; /* PIPE0BRDY */\r
+ _UWORD PIPE1BRDY:1; /* PIPE1BRDY */\r
+ _UWORD PIPE2BRDY:1; /* PIPE2BRDY */\r
+ _UWORD PIPE3BRDY:1; /* PIPE3BRDY */\r
+ _UWORD PIPE4BRDY:1; /* PIPE4BRDY */\r
+ _UWORD PIPE5BRDY:1; /* PIPE5BRDY */\r
+ _UWORD PIPE6BRDY:1; /* PIPE6BRDY */\r
+ _UWORD PIPE7BRDY:1; /* PIPE7BRDY */\r
+ _UWORD PIPE8BRDY:1; /* PIPE8BRDY */\r
+ _UWORD PIPE9BRDY:1; /* PIPE9BRDY */\r
+ _UWORD PIPEABRDY:1; /* PIPEABRDY */\r
+ _UWORD PIPEBBRDY:1; /* PIPEBBRDY */\r
+ _UWORD PIPECBRDY:1; /* PIPECBRDY */\r
+ _UWORD PIPEDBRDY:1; /* PIPEDBRDY */\r
+ _UWORD PIPEEBRDY:1; /* PIPEEBRDY */\r
+ _UWORD PIPEFBRDY:1; /* PIPEFBRDY */\r
+ } BIT; /* */\r
+ } BRDYSTS; /* */\r
+ union { /* NRDYSTS */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PIPE0NRDY:1; /* PIPE0NRDY */\r
+ _UWORD PIPE1NRDY:1; /* PIPE1NRDY */\r
+ _UWORD PIPE2NRDY:1; /* PIPE2NRDY */\r
+ _UWORD PIPE3NRDY:1; /* PIPE3NRDY */\r
+ _UWORD PIPE4NRDY:1; /* PIPE4NRDY */\r
+ _UWORD PIPE5NRDY:1; /* PIPE5NRDY */\r
+ _UWORD PIPE6NRDY:1; /* PIPE6NRDY */\r
+ _UWORD PIPE7NRDY:1; /* PIPE7NRDY */\r
+ _UWORD PIPE8NRDY:1; /* PIPE8NRDY */\r
+ _UWORD PIPE9NRDY:1; /* PIPE9NRDY */\r
+ _UWORD PIPEANRDY:1; /* PIPEANRDY */\r
+ _UWORD PIPEBNRDY:1; /* PIPEBNRDY */\r
+ _UWORD PIPECNRDY:1; /* PIPECNRDY */\r
+ _UWORD PIPEDNRDY:1; /* PIPEDNRDY */\r
+ _UWORD PIPEENRDY:1; /* PIPEENRDY */\r
+ _UWORD PIPEFNRDY:1; /* PIPEFNRDY */\r
+ } BIT; /* */\r
+ } NRDYSTS; /* */\r
+ union { /* BEMPSTS */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PIPE0BEMP:1; /* PIPE0BEMP */\r
+ _UWORD PIPE1BEMP:1; /* PIPE1BEMP */\r
+ _UWORD PIPE2BEMP:1; /* PIPE2BEMP */\r
+ _UWORD PIPE3BEMP:1; /* PIPE3BEMP */\r
+ _UWORD PIPE4BEMP:1; /* PIPE4BEMP */\r
+ _UWORD PIPE5BEMP:1; /* PIPE5BEMP */\r
+ _UWORD PIPE6BEMP:1; /* PIPE6BEMP */\r
+ _UWORD PIPE7BEMP:1; /* PIPE7BEMP */\r
+ _UWORD PIPE8BEMP:1; /* PIPE8BEMP */\r
+ _UWORD PIPE9BEMP:1; /* PIPE9BEMP */\r
+ _UWORD PIPEABEMP:1; /* PIPEABEMP */\r
+ _UWORD PIPEBBEMP:1; /* PIPEBBEMP */\r
+ _UWORD PIPECBEMP:1; /* PIPECBEMP */\r
+ _UWORD PIPEDBEMP:1; /* PIPEDBEMP */\r
+ _UWORD PIPEEBEMP:1; /* PIPEEBEMP */\r
+ _UWORD PIPEFBEMP:1; /* PIPEFBEMP */\r
+ } BIT; /* */\r
+ } BEMPSTS; /* */\r
+ union { /* FRMNUM */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD FRNM:11; /* FRNM */\r
+ _UWORD :3; /* */\r
+ _UWORD CRCE:1; /* CRCE */\r
+ _UWORD OVRN:1; /* OVRN */\r
+ } BIT; /* */\r
+ } FRMNUM; /* */\r
+ union { /* UFRMNUM */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD UFRNM:3; /* UFRNM */\r
+ _UWORD :13; /* */\r
+ } BIT; /* */\r
+ } UFRMNUM; /* */\r
+ union { /* USBADDR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD USBADDR:7; /* USBADDR */\r
+ _UWORD :9; /* */\r
+ } BIT; /* */\r
+ } USBADDR; /* */\r
+ _UBYTE wk7[2]; /* */\r
+ union { /* USBREQ */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BMREQUESTTYPE:8; /* BMREQUESTTYPE */\r
+ _UWORD BREQUEST:8; /* BREQUEST */\r
+ } BIT; /* */\r
+ } USBREQ; /* */\r
+ _UWORD USBVAL; /* USBVAL */\r
+ _UWORD USBINDX; /* USBINDX */\r
+ _UWORD USBLENG; /* USBLENG */\r
+ union { /* DCPCFG */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :4; /* */\r
+ _UWORD DIR:1; /* DIR */\r
+ _UWORD :11; /* */\r
+ } BIT; /* */\r
+ } DCPCFG; /* */\r
+ union { /* DCPMAXP */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD MXPS:7; /* MXPS */\r
+ _UWORD :5; /* */\r
+ _UWORD DEVSEL:4; /* DEVSEL */\r
+ } BIT; /* */\r
+ } DCPMAXP; /* */\r
+ union { /* DCPCTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD CCPL:1; /* CCPL */\r
+ _UWORD :1; /* */\r
+ _UWORD PINGE:1; /* PINGE */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD :2; /* */\r
+ _UWORD SUREQCLR:1; /* SUREQCLR */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD SUREQ:1; /* SUREQ */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } DCPCTR; /* */\r
+ _UBYTE wk8[2]; /* */\r
+ union { /* PIPESEL */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PIPESEL:4; /* PIPESEL */\r
+ _UWORD :12; /* */\r
+ } BIT; /* */\r
+ } PIPESEL; /* */\r
+ _UBYTE wk9[2]; /* */\r
+ union { /* PIPECFG */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD EPNUM:4; /* EPNUM */\r
+ _UWORD DIR:1; /* DIR */\r
+ _UWORD :2; /* */\r
+ _UWORD SHTNAK:1; /* SHTNAK */\r
+ _UWORD CNTMD:1; /* CNTMD */\r
+ _UWORD DBLB:1; /* DBLB */\r
+ _UWORD BFRE:1; /* BFRE */\r
+ _UWORD :3; /* */\r
+ _UWORD TYPE:2; /* TYPE */\r
+ } BIT; /* */\r
+ } PIPECFG; /* */\r
+ union { /* PIPEBUF */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD BUFNMB:8; /* BUFNMB */\r
+ _UWORD :2; /* */\r
+ _UWORD BUFSIZE:5; /* BUFSIZE */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } PIPEBUF; /* */\r
+ union { /* PIPEMAXP */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD MXPS:11; /* MXPS */\r
+ _UWORD :1; /* */\r
+ _UWORD DEVSEL:4; /* DEVSEL */\r
+ } BIT; /* */\r
+ } PIPEMAXP; /* */\r
+ union { /* PIPEPERI */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD IITV:3; /* IITV */\r
+ _UWORD :9; /* */\r
+ _UWORD IFIS:1; /* IFIS */\r
+ _UWORD :3; /* */\r
+ } BIT; /* */\r
+ } PIPEPERI; /* */\r
+ union { /* PIPE1CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD :3; /* */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD :1; /* */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } PIPE1CTR; /* */\r
+ union { /* PIPE2CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD :3; /* */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD :1; /* */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } PIPE2CTR; /* */\r
+ union { /* PIPE3CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD :3; /* */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD :1; /* */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } PIPE3CTR; /* */\r
+ union { /* PIPE4CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD :3; /* */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD :1; /* */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } PIPE4CTR; /* */\r
+ union { /* PIPE5CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD :3; /* */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD :1; /* */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } PIPE5CTR; /* */\r
+ union { /* PIPE6CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD :3; /* */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD :2; /* */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD :1; /* */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } PIPE6CTR; /* */\r
+ union { /* PIPE7CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD :3; /* */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD :2; /* */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD :1; /* */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } PIPE7CTR; /* */\r
+ union { /* PIPE8CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD :3; /* */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD :2; /* */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD :1; /* */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } PIPE8CTR; /* */\r
+ union { /* PIPE9CTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD :3; /* */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD :1; /* */\r
+ _UWORD CSSTS:1; /* CSSTS */\r
+ _UWORD CSCLR:1; /* CSCLR */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } PIPE9CTR; /* */\r
+ union { /* PIPEACTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD :3; /* */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD :3; /* */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } PIPEACTR; /* */\r
+ union { /* PIPEBCTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD :3; /* */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD :3; /* */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } PIPEBCTR; /* */\r
+ union { /* PIPECCTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD :3; /* */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD :3; /* */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } PIPECCTR; /* */\r
+ union { /* PIPEDCTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD :3; /* */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD :3; /* */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } PIPEDCTR; /* */\r
+ union { /* PIPEECTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD :3; /* */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD :3; /* */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } PIPEECTR; /* */\r
+ union { /* PIPEFCTR */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD PID:2; /* PID */\r
+ _UWORD :3; /* */\r
+ _UWORD PBUSY:1; /* PBUSY */\r
+ _UWORD SQMON:1; /* SQMON */\r
+ _UWORD SQSET:1; /* SQSET */\r
+ _UWORD SQCLR:1; /* SQCLR */\r
+ _UWORD ACLRM:1; /* ACLRM */\r
+ _UWORD ATREPM:1; /* ATREPM */\r
+ _UWORD :3; /* */\r
+ _UWORD INBUFM:1; /* INBUFM */\r
+ _UWORD BSTS:1; /* BSTS */\r
+ } BIT; /* */\r
+ } PIPEFCTR; /* */\r
+ _UBYTE wk10[2]; /* */\r
+ union { /* PIPE1TRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } PIPE1TRE; /* */\r
+ _UWORD PIPE1TRN; /* PIPE1TRN */\r
+ union { /* PIPE2TRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } PIPE2TRE; /* */\r
+ _UWORD PIPE2TRN; /* PIPE2TRN */\r
+ union { /* PIPE3TRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } PIPE3TRE; /* */\r
+ _UWORD PIPE3TRN; /* PIPE3TRN */\r
+ union { /* PIPE4TRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } PIPE4TRE; /* */\r
+ _UWORD PIPE4TRN; /* PIPE4TRN */\r
+ union { /* PIPE5TRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } PIPE5TRE; /* */\r
+ _UWORD PIPE5TRN; /* PIPE5TRN */\r
+ union { /* PIPEBTRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } PIPEBTRE; /* */\r
+ _UWORD PIPEBTRN; /* PIPEBTRN */\r
+ union { /* PIPECTRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } PIPECTRE; /* */\r
+ _UWORD PIPECTRN; /* PIPECTRN */\r
+ union { /* PIPEDTRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } PIPEDTRE; /* */\r
+ _UWORD PIPEDTRN; /* PIPEDTRN */\r
+ union { /* PIPEETRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } PIPEETRE; /* */\r
+ _UWORD PIPEETRN; /* PIPEETRN */\r
+ union { /* PIPEFTRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } PIPEFTRE; /* */\r
+ _UWORD PIPEFTRN; /* PIPEFTRN */\r
+ union { /* PIPE9TRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } PIPE9TRE; /* */\r
+ _UWORD PIPE9TRN; /* PIPE9TRN */\r
+ union { /* PIPEATRE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :8; /* */\r
+ _UWORD TRCLR:1; /* TRCLR */\r
+ _UWORD TRENB:1; /* TRENB */\r
+ _UWORD :6; /* */\r
+ } BIT; /* */\r
+ } PIPEATRE; /* */\r
+ _UWORD PIPEATRN; /* PIPEATRN */\r
+ _UBYTE wk11[16]; /* */\r
+ union { /* DEVADD0 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } DEVADD0; /* */\r
+ union { /* DEVADD1 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } DEVADD1; /* */\r
+ union { /* DEVADD2 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } DEVADD2; /* */\r
+ union { /* DEVADD3 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } DEVADD3; /* */\r
+ union { /* DEVADD4 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } DEVADD4; /* */\r
+ union { /* DEVADD5 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } DEVADD5; /* */\r
+ union { /* DEVADD6 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } DEVADD6; /* */\r
+ union { /* DEVADD7 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } DEVADD7; /* */\r
+ union { /* DEVADD8 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } DEVADD8; /* */\r
+ union { /* DEVADD9 */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } DEVADD9; /* */\r
+ union { /* DEVADDA */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :6; /* */\r
+ _UWORD USBSPD:2; /* USBSPD */\r
+ _UWORD HUBPORT:3; /* HUBPORT */\r
+ _UWORD UPPHUB:4; /* UPPHUB */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } DEVADDA; /* */\r
+ _UBYTE wk12[28]; /* */\r
+ union { /* SUSPMODE */\r
+ _UWORD WORD; /* Word Access */\r
+ struct { /* Bit Access */\r
+ _UWORD :14; /* */\r
+ _UWORD SUSPM:1; /* SUSPM */\r
+ _UWORD :1; /* */\r
+ } BIT; /* */\r
+ } SUSPMODE; /* */\r
+ _UBYTE wk13[92]; /* */\r
+ union { /* D0FIFOB0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D0FIFOB0; /* */\r
+ union { /* D0FIFOB1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D0FIFOB1; /* */\r
+ union { /* D0FIFOB2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D0FIFOB2; /* */\r
+ union { /* D0FIFOB3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D0FIFOB3; /* */\r
+ union { /* D0FIFOB4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D0FIFOB4; /* */\r
+ union { /* D0FIFOB5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D0FIFOB5; /* */\r
+ union { /* D0FIFOB6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D0FIFOB6; /* */\r
+ union { /* D0FIFOB7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D0FIFOB7; /* */\r
+ union { /* D1FIFOB0 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D1FIFOB0; /* */\r
+ union { /* D1FIFOB1 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D1FIFOB1; /* */\r
+ union { /* D1FIFOB2 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D1FIFOB2; /* */\r
+ union { /* D1FIFOB3 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D1FIFOB3; /* */\r
+ union { /* D1FIFOB4 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D1FIFOB4; /* */\r
+ union { /* D1FIFOB5 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D1FIFOB5; /* */\r
+ union { /* D1FIFOB6 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D1FIFOB6; /* */\r
+ union { /* D1FIFOB7 */\r
+ _UDWORD LONG; /* Long Access */\r
+ struct { /* Bit Access */\r
+ _UDWORD FIFOPORT:32; /* FIFOPORT */\r
+ } BIT; /* */\r
+ } D1FIFOB7; /* */\r
+}; /* */\r
+\r
+#define USB0 (*(volatile struct st_usb_n *)0xE8010000) /* USB0 Address */\r
+#define USB1 (*(volatile struct st_usb_n *)0xE8207000) /* USB1 Address */\r
+\r
+\r
+#endif /* __USB_IODEFINE_H__ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/******************************************************************************\r
+* File Name : main.h\r
+* $Rev: $\r
+* $Date:: $\r
+* Description : Aragon Sample Program - Main\r
+******************************************************************************/\r
+#ifndef _MAIN_H_\r
+#define _MAIN_H_\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+int_t main(void);\r
+void Sample_OSTM0_Interrupt(void);\r
+\r
+#endif /* _MAIN_H_ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/******************************************************************************\r
+* File Name : port_init.h\r
+* $Rev: 17531 $\r
+* $Date:: 2013-04-10 12:58:44 +0100#$\r
+* Description : Aragon Sample Program - SCIF UART sample program\r
+******************************************************************************/\r
+#ifndef _PORT_INIT_H_\r
+#define _PORT_INIT_H_\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+void PORT_Init(void);\r
+\r
+\r
+#endif /* _PORT_INIT_H_ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : r_typedefs.h\r
+* $Rev: 17531 $\r
+* $Date:: 2013-04-10 12:58:44 +0100#$\r
+* Description : basic type definition\r
+******************************************************************************/\r
+#ifndef R_TYPEDEFS_H\r
+#define R_TYPEDEFS_H\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include <stddef.h>\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+#if !defined(__bool_true_false_are_defined) && !defined(__cplusplus)\r
+#define false 0\r
+#define true 1\r
+#endif\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+typedef char char_t;\r
+typedef unsigned int bool_t;\r
+typedef int int_t;\r
+typedef signed char int8_t;\r
+typedef signed short int16_t;\r
+typedef signed long int32_t;\r
+typedef signed long long int64_t;\r
+typedef unsigned char uint8_t;\r
+typedef unsigned short uint16_t;\r
+typedef unsigned long uint32_t;\r
+typedef unsigned long long uint64_t;\r
+typedef float float32_t;\r
+typedef double float64_t;\r
+typedef long double float128_t;\r
+\r
+#endif /* R_TYPEDEFS_H */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/******************************************************************************\r
+* File Name : resetprg.h\r
+* $Rev: 17531 $\r
+* $Date:: 2013-04-10 12:58:44 +0100#$\r
+* Description : Aragon Sample Program - Program after reset\r
+******************************************************************************/\r
+#ifndef _RESETPRG_H_\r
+#define _RESETPRG_H_\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+void io_init_cache(void);\r
+int32_t io_cache_writeback(void);\r
+\r
+#endif /* _RESETPRG_H_ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/******************************************************************************\r
+* File Name : sample_main.h\r
+* $Rev: $\r
+* $Date:: $\r
+* Description : Aragon Sample Program - RIIC sample program\r
+******************************************************************************/\r
+#ifndef _SAMPLE_MAIN_H_\r
+#define _SAMPLE_MAIN_H_\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+void Sample_Main(void);\r
+\r
+\r
+#endif /* _SAMPLE_MAIN_H_ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/******************************************************************************\r
+* File Name : sio_char.h\r
+* $Rev: 17531 $\r
+* $Date:: 2013-04-10 12:58:44 +0100#$\r
+* Description : Aragon Sample Program - Terminal I/O\r
+******************************************************************************/\r
+#ifndef _SIO_CHAR_H_\r
+#define _SIO_CHAR_H_\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+int32_t SioWrite(int32_t file_no, const char_t * buffer, uint32_t writing_b);\r
+int32_t SioRead(int32_t file_no, char_t * buffer, uint32_t reading_b);\r
+\r
+void IoInitScif2(void);\r
+char_t IoGetchar(void);\r
+void IoPutchar(char_t buffer);\r
+\r
+#endif /* _SIO_CHAR_H_ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/******************************************************************************\r
+* File Name : stb_init.h\r
+* $Rev: 17531 $\r
+* $Date:: 2013-04-10 12:58:44 +0100#$\r
+* Description : Aragon Sample Program - SCIF UART sample program\r
+******************************************************************************/\r
+#ifndef _STB_INIT_H_\r
+#define _STB_INIT_H_\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+void STB_Init(void);\r
+\r
+\r
+#endif /* _STB_INIT_H_ */\r
+\r
+/* End of File */\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : typedefine.h\r
+* Version : 1.00\r
+* Description : Defines exact width integer types.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 24.05.2012 1.00 First Release\r
+*******************************************************************************/\r
+#ifndef _TYPE_DEFINE_H_\r
+#define _TYPE_DEFINE_H_\r
+\r
+/*******************************************************************************\r
+Typedef definitions\r
+*******************************************************************************/\r
+typedef signed char _SBYTE;\r
+typedef unsigned char _UBYTE;\r
+typedef signed short _SWORD;\r
+typedef unsigned short _UWORD;\r
+typedef signed int _SINT;\r
+typedef unsigned int _UINT;\r
+typedef signed long _SDWORD;\r
+typedef unsigned long _UDWORD;\r
+typedef signed long long _SQWORD;\r
+typedef unsigned long long _UQWORD;\r
+\r
+#endif /* _TYPE_DEFINE_H_ */\r
+\r
+/* End of File */\r
--- /dev/null
+;/*******************************************************************************\r
+;* DISCLAIMER\r
+;* This software is supplied by Renesas Electronics Corporation and is only\r
+;* intended for use with Renesas products. No other uses are authorized. This\r
+;* software is owned by Renesas Electronics Corporation and is protected under\r
+;* all applicable laws, including copyright laws.\r
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+;* Renesas reserves the right, without notice, to make changes to this software\r
+;* and to discontinue the availability of this software. By using this software,\r
+;* you agree to the additional terms and conditions found by accessing the\r
+;* following link:\r
+;* http://www.renesas.com/disclaimer\r
+;*\r
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* File Name : vector_mirrortable.s\r
+;* Version : 0.01\r
+;* Device(s) : Aragon\r
+;* Tool-Chain : DS-5 Ver 5.13\r
+;* ARM Complier \r
+;* : \r
+;* H/W Platform : Aragon CPU Board\r
+;* Description : Aragon Sample Program - Vector mirrortable\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* History : DD.MM.YYYY Version Description\r
+;* : 23.05.2012 0.01\r
+;*******************************************************************************/\r
+\r
+;==================================================================\r
+; Entry point for the Reset handler\r
+;==================================================================\r
+ PRESERVE8\r
+ AREA VECTOR_MIRROR_TABLE, CODE, READONLY\r
+\r
+; EXPORT vector_table\r
+\r
+ IMPORT reset_handler\r
+ IMPORT undefined_handler\r
+ IMPORT prefetch_handler\r
+ IMPORT abort_handler\r
+ IMPORT reserved_handler\r
+ IMPORT FreeRTOS_IRQ_Handler\r
+ IMPORT fiq_handler\r
+ IMPORT FreeRTOS_SWI_Handler\r
+\r
+; ENTRY\r
+\r
+; EXPORT Start\r
+\r
+;Start\r
+\r
+vector_table2\r
+ LDR pc, =reset_handler ; 0x0000_0000\r
+ LDR pc, =undefined_handler ; 0x0000_0004\r
+ LDR pc, =FreeRTOS_SWI_Handler ; 0x0000_0008\r
+ LDR pc, =prefetch_handler ; 0x0000_000c\r
+ LDR pc, =abort_handler ; 0x0000_0010\r
+ LDR pc, =reserved_handler ; 0x0000_0014\r
+ LDR pc, =FreeRTOS_IRQ_Handler ; 0x0000_0018\r
+ LDR pc, =fiq_handler ; 0x0000_001c\r
+\r
+Literals\r
+ LTORG\r
+\r
+ END\r
--- /dev/null
+;/*******************************************************************************\r
+;* DISCLAIMER\r
+;* This software is supplied by Renesas Electronics Corporation and is only\r
+;* intended for use with Renesas products. No other uses are authorized. This\r
+;* software is owned by Renesas Electronics Corporation and is protected under\r
+;* all applicable laws, including copyright laws.\r
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+;* Renesas reserves the right, without notice, to make changes to this software\r
+;* and to discontinue the availability of this software. By using this software,\r
+;* you agree to the additional terms and conditions found by accessing the\r
+;* following link:\r
+;* http://www.renesas.com/disclaimer\r
+;*\r
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* File Name : vector_table.s\r
+;* Version : 0.01\r
+;* Device(s) : Aragon - RZ/A1H\r
+;* Tool-Chain : DS-5 Ver 5.13\r
+;* ARM Complier \r
+;* : \r
+;* H/W Platform : Aragon CPU Board\r
+;* Description : Aragon Sample Program - Vector table\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* History : DD.MM.YYYY Version Description\r
+;* : 23.05.2012 0.01\r
+;*******************************************************************************/\r
+\r
+;==================================================================\r
+; Entry point for the Reset handler\r
+;==================================================================\r
+ PRESERVE8\r
+ AREA VECTOR_TABLE, CODE, READONLY\r
+\r
+ EXPORT vector_table\r
+\r
+ IMPORT reset_handler\r
+ IMPORT undefined_handler\r
+ IMPORT FreeRTOS_SWI_Handler\r
+ IMPORT prefetch_handler\r
+ IMPORT abort_handler\r
+ IMPORT reserved_handler\r
+ IMPORT FreeRTOS_IRQ_Handler\r
+ IMPORT fiq_handler\r
+\r
+ ENTRY\r
+\r
+ EXPORT Start\r
+\r
+Start\r
+\r
+vector_table\r
+ LDR pc, =reset_handler ; 0x0000_0000\r
+ LDR pc, =undefined_handler ; 0x0000_0004\r
+ LDR pc, =FreeRTOS_SWI_Handler ; 0x0000_0008\r
+ LDR pc, =prefetch_handler ; 0x0000_000c\r
+ LDR pc, =abort_handler ; 0x0000_0010\r
+ LDR pc, =reserved_handler ; 0x0000_0014\r
+ LDR pc, =FreeRTOS_IRQ_Handler ; 0x0000_0018\r
+ LDR pc, =fiq_handler ; 0x0000_001c\r
+\r
+Literals\r
+ LTORG\r
+\r
+ END\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project,\r
+ * and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
+ * select between the two. The simply blinky demo is implemented and described\r
+ * in main_blinky.c. The more comprehensive test and demo application is\r
+ * implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and FreeRTOS hook functions.\r
+ *\r
+ * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON\r
+ * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO\r
+ * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo includes. */\r
+#include "partest.h"\r
+#include "TimerDemo.h"\r
+\r
+/* Renesas includes. */\r
+#include "r_typedefs.h"\r
+#include "sio_char.h"\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive test and demo application. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Configure the hardware as necessary to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1\r
+ extern void main_blinky( void );\r
+#else\r
+ extern void main_full( void );\r
+#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */\r
+\r
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
+within this file. */\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+/*\r
+ * Creates and verifies different files on the volume, demonstrating the use of\r
+ * various different API functions.\r
+ */\r
+extern void vCreateAndVerifySampleFiles( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Configure the hardware ready to run the demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+ of this file. */\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1\r
+ {\r
+ main_blinky();\r
+ }\r
+ #else\r
+ {\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Initialise the pins used by the LEDs (the obscure [now for historical\r
+ reasons] name ParTest stands for Parallel Port test). */\r
+ vParTestInitialise();\r
+\r
+ /* Call the Renesas driver that initialises the serial port. P1=66.67MHz\r
+ CKS=0 SCBRR=17 Bit rate error=0.46% => Baud rate=115200bps. */\r
+ IoInitScif2();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* Called if a call to pvPortMalloc() fails because there is insufficient\r
+ free memory available in the FreeRTOS heap. pvPortMalloc() is called\r
+ internally by FreeRTOS API functions that create tasks, queues, software\r
+ timers, and semaphores. The size of the FreeRTOS heap is set by the\r
+ configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+volatile size_t xFreeHeapSpace;\r
+\r
+ /* This is just a trivial example of an idle hook. It is called on each\r
+ cycle of the idle task. It must *NOT* attempt to block. In this case the\r
+ idle task just queries the amount of FreeRTOS heap that remains. See the\r
+ memory management section on the http://www.FreeRTOS.org web site for memory\r
+ management options. If there is a lot of heap memory free then the\r
+ configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up\r
+ RAM. */\r
+ xFreeHeapSpace = xPortGetFreeHeapSize();\r
+\r
+ /* Remove compiler warning about xFreeHeapSpace being set but never used. */\r
+ ( void ) xFreeHeapSpace;\r
+\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1\r
+ {\r
+ /* If the file system is only going to be accessed from one task then\r
+ F_FS_THREAD_AWARE can be set to 0 and the set of example files is\r
+ created before the RTOS scheduler is started. If the file system is\r
+ going to be access from more than one task then F_FS_THREAD_AWARE must\r
+ be set to 1 and the set of sample files are created from the idle task\r
+ hook function. */\r
+ #if F_FS_THREAD_AWARE == 1\r
+ {\r
+ static portBASE_TYPE xCreatedSampleFiles = pdFALSE;\r
+\r
+ /* Initialise the drive and file system, then create a few example\r
+ files. The output from this function just goes to the stdout window,\r
+ allowing the output to be viewed when the UDP command console is not\r
+ connected. */\r
+ if( xCreatedSampleFiles == pdFALSE )\r
+ {\r
+ vCreateAndVerifySampleFiles();\r
+ xCreatedSampleFiles = pdTRUE;\r
+ }\r
+ }\r
+ #endif\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vAssertCalled( const char * pcFile, unsigned long ulLine )\r
+{\r
+volatile unsigned long ul = 0;\r
+\r
+ ( void ) pcFile;\r
+ ( void ) ulLine;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Set ul to a non-zero value using the debugger to step out of this\r
+ function. */\r
+ while( ul == 0 )\r
+ {\r
+ portNOP();\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0\r
+ {\r
+ /* The full demo includes a software timer demo/test that requires\r
+ prodding periodically from the tick interrupt. */\r
+ vTimerPeriodicISRTests();\r
+ }\r
+ #endif\r
+}\r
+\r
+\r
+\r
--- /dev/null
+;/*******************************************************************************\r
+;* DISCLAIMER\r
+;* This software is supplied by Renesas Electronics Corporation and is only\r
+;* intended for use with Renesas products. No other uses are authorized. This\r
+;* software is owned by Renesas Electronics Corporation and is protected under\r
+;* all applicable laws, including copyright laws.\r
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+;* Renesas reserves the right, without notice, to make changes to this software\r
+;* and to discontinue the availability of this software. By using this software,\r
+;* you agree to the additional terms and conditions found by accessing the\r
+;* following link:\r
+;* http://www.renesas.com/disclaimer\r
+;*\r
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* File Name : scatter.scat\r
+;* Version : 0.01\r
+;* Device(s) : Aragon\r
+;* Tool-Chain : DS-5 Ver 5.8\r
+;* ARM Complier \r
+;* : \r
+;* H/W Platform : Aragon CPU Board\r
+;* Description : Aragon Sample Program scatter file\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* History : DD.MM.YYYY Version Description\r
+;* : 23.05.2012 0.01\r
+;*******************************************************************************/\r
+\r
+LOAD_MODULE3 0x20020000 0x209FFFFF ;; Internal RAM Area (0x20020000-0x2003FFFF)\r
+{\r
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+ ;; use as RAM Area ;;\r
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+ VECTOR_MIRROR_TABLE 0x20020000 ;; Internal RAM Area (0x20020000-0x200200FF)\r
+ { * (VECTOR_MIRROR_TABLE) } ;; Vector table\r
+
+ CODE +0 FIXED\r
+ { * (+RO-CODE) }\r
+\r
+ CONST +0 FIXED\r
+ { * (+RO-DATA) }\r
+\r
+ DATA +0\r
+ { * (+RW) }\r
+\r
+ BSS +0\r
+ { * (+ZI) }\r
+\r
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+ ;; use as RAM Area(2) ;;\r
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+ ARM_LIB_HEAP 0x20080000 EMPTY 0x00008000 ; Application heap\r
+ { }\r
+\r
+ ARM_LIB_STACK 0x20090000 EMPTY -0x00008000 ; Application stack\r
+ { }\r
+\r
+ IRQ_STACK 0x20092000 EMPTY -0x00002000 ; IRQ mode stack\r
+ { }\r
+\r
+ FIQ_STACK 0x20094000 EMPTY -0x00002000 ; FRQ mode stack\r
+ { }\r
+\r
+ SVC_STACK 0x20096000 EMPTY -0x00002000 ; SVC mode stack\r
+ { }\r
+\r
+ ABT_STACK 0x20098000 EMPTY -0x00002000 ; ABT mode stack\r
+ { }\r
+\r
+ TTB (0x20098000 AND 0xFFFFC000) EMPTY 0x00008000 ; Level-1 Translation Table for MMU\r
+ { }\r
+}\r
--- /dev/null
+stop\r
+pause 500\r
+reset\r
+stop\r
+#reset\r
+\r
+info memory\r
+memory S:0x00000000 S:0x07ffffff ro\r
+memory S:0x3fffff80 S:0x3fffffff nocache noverify\r
+memory S:0xfcfe0000 S:0xfcfeffff nocache noverify\r
+\r
+# USB Register accessed by only 16bit\r
+memory S:0xe8010000 S:0xe801010f 16\r
+memory S:0xe8207000 S:0xe820710f 16\r
+info memory\r
+\r
+######################################\r
+# Release L2 cache standby ##\r
+######################################\r
+mem set 0x3fffff80 32 0x00000001\r
+\r
+# ;*Writing to On-Chip Data-Retention RAM is enabled.\r
+# ;SYSCR3.RRAMWE3=RRAMWE2=RRAMWE1=RRAMWE0=1\r
+mem set 0xfcfe0408 32 0xf\r
+\r
+######################################\r
+# CS0 Port Setting ##\r
+# CS1 Port Setting ##\r
+######################################\r
+# P9_1(A25), P9_0(A24),\r
+mem set 0xfcfe3424 16 0x0003 # PMC9\r
+mem set 0xfcfe3A24 16 0x0000 # PFCAE9\r
+mem set 0xfcfe3624 16 0x0000 # PFCE9\r
+mem set 0xfcfe3524 16 0x0000 # PFC9\r
+mem set 0xfcfe7224 16 0x0003 # PIPC9\r
+# P8_15(A23), P8_14(A22), P8_13(A21),\r
+mem set 0xfcfe3420 16 0xffff # PMC8\r
+mem set 0xfcfe3A20 16 0x0000 # PFCAE8\r
+mem set 0xfcfe3620 16 0x0000 # PFCE8\r
+mem set 0xfcfe3520 16 0x0000 # PFC8\r
+mem set 0xfcfe7220 16 0xffff # PIPC8\r
+# P7_6(WE0#), P7_8(RD#), P7_0(CS0#),\r
+mem set 0xfcfe341c 16 0xff41 # PMC7\r
+mem set 0xfcfe3A1c 16 0x0000 # PFCAE7\r
+mem set 0xfcfe361c 16 0x0000 # PFCE7\r
+mem set 0xfcfe351c 16 0x0000 # PFC7\r
+mem set 0xfcfe721c 16 0xff41 # PIPC7\r
+# P3_7(CS1#),\r
+mem set 0xfcfe340c 16 0x0080 # PMC3\r
+mem set 0xfcfe3A0c 16 0x0080 # PFCAE3\r
+mem set 0xfcfe360c 16 0x0080 # PFCE3\r
+mem set 0xfcfe350c 16 0x0000 # PFC3\r
+mem set 0xfcfe720c 16 0x0080 # PIPC3\r
+\r
projects / freertos / commitdiff