Update RSIC-V port layer after testing saving and receiving of chip specific registers.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2617 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h
index 2448d8a7833a932296bb27f61d7cb69dd094a5cd..5121abab1bc8cc68819767961b160f17ecfe8ed5 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h
@@ -75,7 +75,7 @@
 \r
 /* Save additional registers found on the Pulpino. */\r
 .macro portasmSAVE_ADDITIONAL_REGISTERS\r
-       addi sp, sp, -portasmADDITIONAL_CONTEXT_SIZE /* Make room for the additional registers. */\r
+       addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */\r
        csrr t0, lpstart0                                                        /* Load additional registers into accessable temporary registers. */\r
        csrr t1, lpend0\r
        csrr t2, lpcount0\r
@@ -104,7 +104,7 @@
        csrw lpstart1, t3\r
        csrw lpend1, t4\r
        csrw lpcount1, t5\r
-       addi sp, sp, -portasmADDITIONAL_CONTEXT_SIZE /* Remove space added for additional registers. */\r
+       addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */\r
        .endm\r
 \r
 #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */\r

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
index 12cc49b4d06526d5379c951406b5c90657ea8c94..5d9e5f30743c505ad464d4fbf895c4f21d01a18c 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
@@ -363,22 +363,13 @@ xPortStartFirstTask:
  * x6\r
  * x5\r
  * portTASK_RETURN_ADDRESS\r
+ * [chip specific registers go here]\r
  * pxCode\r
  */\r
 .align 8\r
 .func\r
 pxPortInitialiseStack:\r
 \r
-       addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */\r
-\r
-chip_specific_stack_frame:                             /* First add any chip specific registers to the stack frame being created. */\r
-       beq t0, x0, standard_stack_frame        /* No more chip specific registers to save. */\r
-       addi a0, a0, -portWORD_SIZE                     /* Make space for chip specific register. */\r
-       sw x0, 0(a0)                                            /* Give the chip specific register an initial value of zero. */\r
-       addi t0, t0, -1                                         /* Decrement the count of chip specific registers remaining. */\r
-       j chip_specific_stack_frame                     /* Until no more chip specific registers. */\r
-\r
-standard_stack_frame:                                  /* Now create the stack frame for the standard registers. */\r
        csrr t0, mstatus                                        /* Obtain current mstatus value. */\r
        addi t1, x0, 0x188                                      /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */\r
        slli t1, t1, 4\r
@@ -390,6 +381,14 @@ standard_stack_frame:                                      /* Now create the stack frame for the standard registe
        sw a2, 0(a0)                                            /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */\r
        addi a0, a0, -(6 * portWORD_SIZE)       /* Space for registers x5-x9. */\r
        sw x0, 0(a0)                                            /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */\r
+       addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */\r
+chip_specific_stack_frame:                             /* First add any chip specific registers to the stack frame being created. */\r
+       beq t0, x0, 1f                                          /* No more chip specific registers to save. */\r
+       addi a0, a0, -portWORD_SIZE                     /* Make space for chip specific register. */\r
+       sw x0, 0(a0)                                            /* Give the chip specific register an initial value of zero. */\r
+       addi t0, t0, -1                                         /* Decrement the count of chip specific registers remaining. */\r
+       j chip_specific_stack_frame                     /* Until no more chip specific registers. */\r
+1:\r
        addi a0, a0, -portWORD_SIZE\r
        sw a1, 0(a0)                                            /* mret value (pxCode parameter) onto the stack. */\r
        ret\r