noinst_LIBRARIES = libflash.a
libflash_a_SOURCES = flash.c lpc2000.c cfi.c non_cfi.c at91sam7.c str7x.c str9x.c nand.c lpc3180_nand_controller.c \
stellaris.c str9xpec.c stm32x.c tms470.c ecos.c \
- s3c24xx_nand.c s3c2410_nand.c s3c2412_nand.c s3c2440_nand.c s3c2443_nand.c lpc288x.c
+ s3c24xx_nand.c s3c2410_nand.c s3c2412_nand.c s3c2440_nand.c s3c2443_nand.c lpc288x.c ocl.c
noinst_HEADERS = flash.h lpc2000.h cfi.h non_cfi.h at91sam7.h str7x.h str9x.h nand.h lpc3180_nand_controller.h \
stellaris.h str9xpec.h stm32x.h tms470.h s3c24xx_nand.h s3c24xx_regs_nand.h lpc288x.h
extern flash_driver_t tms470_flash;
extern flash_driver_t ecosflash_flash;
extern flash_driver_t lpc288x_flash;
+extern flash_driver_t ocl_flash;
flash_driver_t *flash_drivers[] =
{
&tms470_flash,
&ecosflash_flash,
&lpc288x_flash,
+ &ocl_flash,
NULL,
};
--- /dev/null
+/***************************************************************************\r
+ * Copyright (C) 2007 by Pavel Chromy *\r
+ * chromy@asix.cz *\r
+ * *\r
+ * This program is free software; you can redistribute it and/or modify *\r
+ * it under the terms of the GNU General Public License as published by *\r
+ * the Free Software Foundation; either version 2 of the License, or *\r
+ * (at your option) any later version. *\r
+ * *\r
+ * This program is distributed in the hope that it will be useful, *\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
+ * GNU General Public License for more details. *\r
+ * *\r
+ * You should have received a copy of the GNU General Public License *\r
+ * along with this program; if not, write to the *\r
+ * Free Software Foundation, Inc., *\r
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
+ ***************************************************************************/\r
+#ifdef HAVE_CONFIG_H\r
+#include "config.h"\r
+#endif\r
+\r
+#include "replacements.h"\r
+\r
+#include "ocl.h"\r
+\r
+#include "flash.h"\r
+#include "target.h"\r
+#include "log.h"\r
+#include "binarybuffer.h"\r
+#include "types.h"\r
+#include "embeddedice.h"\r
+#include "arm7_9_common.h"\r
+\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include <unistd.h>\r
+\r
+int ocl_register_commands(struct command_context_s *cmd_ctx);\r
+int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);\r
+int ocl_erase(struct flash_bank_s *bank, int first, int last);\r
+int ocl_protect(struct flash_bank_s *bank, int set, int first, int last);\r
+int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);\r
+int ocl_probe(struct flash_bank_s *bank);\r
+int ocl_erase_check(struct flash_bank_s *bank);\r
+int ocl_protect_check(struct flash_bank_s *bank);\r
+int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size);\r
+int ocl_auto_probe(struct flash_bank_s *bank);\r
+\r
+flash_driver_t ocl_flash =\r
+{\r
+ .name = "ocl",\r
+ .register_commands = ocl_register_commands,\r
+ .flash_bank_command = ocl_flash_bank_command,\r
+ .erase = ocl_erase,\r
+ .protect = ocl_protect,\r
+ .write = ocl_write,\r
+ .probe = ocl_probe,\r
+ .erase_check = ocl_erase_check,\r
+ .protect_check = ocl_protect_check,\r
+ .info = ocl_info,\r
+ .auto_probe = ocl_auto_probe\r
+};\r
+\r
+\r
+typedef struct ocl_priv_s\r
+{\r
+ arm_jtag_t *jtag_info;\r
+ int buflen;\r
+ int bufalign;\r
+} ocl_priv_t;\r
+\r
+\r
+int ocl_register_commands(struct command_context_s *cmd_ctx)\r
+{\r
+ return ERROR_OK;\r
+}\r
+\r
+\r
+int ocl_erase_check(struct flash_bank_s *bank)\r
+{\r
+ return ERROR_OK;\r
+}\r
+\r
+\r
+int ocl_protect_check(struct flash_bank_s *bank)\r
+{\r
+ return ERROR_OK;\r
+}\r
+\r
+\r
+/* flash_bank ocl 0 0 0 0 <target#> */\r
+int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)\r
+{\r
+ int retval;\r
+ armv4_5_common_t *armv4_5;\r
+ arm7_9_common_t *arm7_9;\r
+ ocl_priv_t *ocl;\r
+\r
+ if (argc < 6)\r
+ {\r
+ LOG_WARNING("incomplete flash_bank ocl configuration");\r
+ return ERROR_FLASH_BANK_INVALID;\r
+ }\r
+\r
+ if ((retval = arm7_9_get_arch_pointers(bank->target, &armv4_5, &arm7_9)) != ERROR_OK)\r
+ return retval;\r
+\r
+ ocl = bank->driver_priv = malloc(sizeof(ocl_priv_t));\r
+ ocl->jtag_info = &arm7_9->jtag_info;\r
+ ocl->buflen = 0;\r
+ ocl->bufalign = 1;\r
+\r
+ return ERROR_OK;\r
+}\r
+\r
+\r
+int ocl_erase(struct flash_bank_s *bank, int first, int last)\r
+{\r
+ ocl_priv_t *ocl = bank->driver_priv;\r
+ int retval;\r
+ u32 dcc_buffer[3];\r
+\r
+ /* check preconditions */\r
+ if (bank->num_sectors == 0)\r
+ return ERROR_FLASH_BANK_NOT_PROBED;\r
+ \r
+ if (bank->target->state != TARGET_RUNNING)\r
+ {\r
+ LOG_ERROR("target has to be running to communicate with the loader");\r
+ return ERROR_TARGET_NOT_RUNNING;\r
+ }\r
+ \r
+ if ((first == 0) && (last == bank->num_sectors - 1))\r
+ {\r
+ dcc_buffer[0] = OCL_ERASE_ALL;\r
+ if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))\r
+ return retval;\r
+ }\r
+ else\r
+ {\r
+ dcc_buffer[0] = OCL_ERASE_BLOCK;\r
+ dcc_buffer[1] = first;\r
+ dcc_buffer[2] = last;\r
+ if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 3) != ERROR_OK))\r
+ return retval;\r
+ }\r
+\r
+ /* wait for response, fixed timeout of 1 s */\r
+ if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK))\r
+ {\r
+ if (retval == ERROR_TARGET_TIMEOUT)\r
+ LOG_ERROR("loader not responding");\r
+ return retval;\r
+ }\r
+\r
+ /* receive response */\r
+ if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer+1, 1) != ERROR_OK))\r
+ return retval;\r
+\r
+ if (dcc_buffer[1] != OCL_CMD_DONE)\r
+ {\r
+ if (dcc_buffer[0] == OCL_ERASE_ALL)\r
+ LOG_ERROR("loader response to OCL_ERASE_ALL 0x%08lX", dcc_buffer[1]);\r
+ else\r
+ LOG_ERROR("loader response to OCL_ERASE_BLOCK 0x%08lX", dcc_buffer[1]);\r
+ return ERROR_FLASH_OPERATION_FAILED;\r
+ }\r
+\r
+ return ERROR_OK;\r
+}\r
+\r
+\r
+int ocl_protect(struct flash_bank_s *bank, int set, int first, int last)\r
+{\r
+ return ERROR_OK;\r
+}\r
+\r
+\r
+int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)\r
+{\r
+ ocl_priv_t *ocl = bank->driver_priv;\r
+ int retval;\r
+ u32 *dcc_buffer;\r
+ u32 *dcc_bufptr;\r
+ int byteofs;\r
+ int runlen;\r
+ u32 chksum;\r
+ \r
+ int i;\r
+\r
+ /* check preconditions */\r
+ if (ocl->buflen == 0 || ocl->bufalign==0)\r
+ return ERROR_FLASH_BANK_NOT_PROBED;\r
+\r
+ if (bank->target->state != TARGET_RUNNING)\r
+ {\r
+ LOG_ERROR("target has to be running to communicate with the loader");\r
+ return ERROR_TARGET_NOT_RUNNING;\r
+ }\r
+\r
+ /* allocate buffer for max. ocl buffer + overhead */\r
+ dcc_buffer = malloc(sizeof(u32)*(ocl->buflen/4+3));\r
+\r
+ while (count)\r
+ {\r
+ if (count + (offset % ocl->bufalign) > ocl->buflen)\r
+ runlen = ocl->buflen - (offset % ocl->bufalign);\r
+ else\r
+ runlen = count;\r
+\r
+ dcc_buffer[0] = OCL_FLASH_BLOCK | runlen;\r
+ dcc_buffer[1] = offset;\r
+ dcc_bufptr = &dcc_buffer[2];\r
+\r
+ *dcc_bufptr = 0xffffffff;\r
+ byteofs = (offset % ocl->bufalign) % 4;\r
+ chksum = OCL_CHKS_INIT;\r
+\r
+ /* copy data to DCC buffer in proper byte order and properly aligned */\r
+ for (i=0; i<runlen; i++)\r
+ {\r
+ switch (byteofs++)\r
+ {\r
+ case 0:\r
+ *dcc_bufptr &= *(buffer++) | 0xffffff00;\r
+ break;\r
+ case 1:\r
+ *dcc_bufptr &= ((*(buffer++))<<8) | 0xffff00ff;\r
+ break;\r
+ case 2:\r
+ *dcc_bufptr &= ((*(buffer++))<<16) | 0xff00ffff;\r
+ break;\r
+ case 3:\r
+ *dcc_bufptr &= ((*(buffer++))<<24) | 0x00ffffff;\r
+ chksum ^= *(dcc_bufptr++);\r
+ *dcc_bufptr = 0xffffffff;\r
+ byteofs = 0;\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* add the remaining word to checksum */\r
+ if (byteofs)\r
+ chksum ^= *(dcc_bufptr++);\r
+\r
+ *(dcc_bufptr++) = chksum;\r
+ \r
+ /* send the data */\r
+ if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, dcc_bufptr-dcc_buffer)) != ERROR_OK)\r
+ {\r
+ free(dcc_buffer);\r
+ return retval;\r
+ }\r
+\r
+ /* wait for response, fixed timeout of 1 s */\r
+ if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK))\r
+ {\r
+ if (retval == ERROR_TARGET_TIMEOUT)\r
+ LOG_ERROR("loader not responding");\r
+ free(dcc_buffer);\r
+ return retval;\r
+ }\r
+\r
+ /* receive response */\r
+ if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))\r
+ {\r
+ free(dcc_buffer);\r
+ return retval;\r
+ }\r
+\r
+ if (dcc_buffer[0] != OCL_CMD_DONE)\r
+ {\r
+ LOG_ERROR("loader response to OCL_FLASH_BLOCK 0x%08lX", dcc_buffer[0]);\r
+ free(dcc_buffer);\r
+ return ERROR_FLASH_OPERATION_FAILED;\r
+ }\r
+\r
+ count -= runlen;\r
+ offset += runlen;\r
+ }\r
+\r
+ free(dcc_buffer);\r
+ return ERROR_OK;\r
+}\r
+\r
+\r
+int ocl_probe(struct flash_bank_s *bank)\r
+{\r
+ ocl_priv_t *ocl = bank->driver_priv;\r
+ int retval;\r
+ u32 dcc_buffer[1];\r
+ int sectsize;\r
+ int i;\r
+\r
+ /* purge pending data in DCC */\r
+ embeddedice_receive(ocl->jtag_info, dcc_buffer, 1);\r
+\r
+ dcc_buffer[0] = OCL_PROBE;\r
+ if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))\r
+ return retval;\r
+\r
+ /* wait for response, fixed timeout of 1 s */\r
+ if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK))\r
+ {\r
+ if (retval == ERROR_TARGET_TIMEOUT)\r
+ LOG_ERROR("loader not responding");\r
+ return retval;\r
+ }\r
+\r
+ /* receive response */\r
+ if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))\r
+ return retval;\r
+ \r
+ if (dcc_buffer[0] != OCL_CMD_DONE)\r
+ {\r
+ LOG_ERROR("loader response to OCL_PROBE 0x%08lX", dcc_buffer[0]);\r
+ return ERROR_FLASH_OPERATION_FAILED;\r
+ }\r
+\r
+ /* receive and fill in parameters, detection of loader is important, receive it one by one */\r
+ if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)\r
+ || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))\r
+ return retval;\r
+ bank->base = dcc_buffer[0];\r
+\r
+ if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)\r
+ || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))\r
+ return retval;\r
+ bank->size = dcc_buffer[0];\r
+\r
+ if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)\r
+ || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))\r
+ return retval;\r
+ bank->num_sectors = dcc_buffer[0];\r
+\r
+ if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)\r
+ || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))\r
+ return retval;\r
+ ocl->buflen = dcc_buffer[0] & 0xffff;\r
+ ocl->bufalign = dcc_buffer[0] >> 16;\r
+\r
+ bank->sectors = realloc(bank->sectors, sizeof(flash_sector_t)*bank->num_sectors);\r
+ if (bank->num_sectors == 0)\r
+ {\r
+ LOG_ERROR("number of sectors shall be non zero value");\r
+ return ERROR_FLASH_BANK_INVALID;\r
+ }\r
+ if (bank->size % bank->num_sectors) {\r
+ LOG_ERROR("bank size not divisible by number of sectors");\r
+ return ERROR_FLASH_BANK_INVALID;\r
+ }\r
+ sectsize = bank->size / bank->num_sectors;\r
+ for (i=0; i<bank->num_sectors; i++)\r
+ {\r
+ bank->sectors[i].offset = i * sectsize;\r
+ bank->sectors[i].size = sectsize;\r
+ bank->sectors[i].is_erased = -1;\r
+ bank->sectors[i].is_protected = -1;\r
+ }\r
+\r
+ if (ocl->bufalign == 0)\r
+ ocl->bufalign = 1;\r
+\r
+ if (ocl->buflen == 0)\r
+ {\r
+ LOG_ERROR("buflen shall be non zero value");\r
+ return ERROR_FLASH_BANK_INVALID;\r
+ }\r
+\r
+ if ((ocl->bufalign > ocl->buflen) || (ocl->buflen % ocl->bufalign))\r
+ {\r
+ LOG_ERROR("buflen is not multiple of bufalign");\r
+ return ERROR_FLASH_BANK_INVALID;\r
+ }\r
+\r
+ if (ocl->buflen % 4)\r
+ {\r
+ LOG_ERROR("buflen shall be divisible by 4");\r
+ return ERROR_FLASH_BANK_INVALID;\r
+ }\r
+\r
+ return ERROR_OK;\r
+}\r
+\r
+\r
+int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size)\r
+{\r
+ return ERROR_OK;\r
+}\r
+\r
+\r
+int ocl_auto_probe(struct flash_bank_s *bank)\r
+{\r
+ ocl_priv_t *ocl = bank->driver_priv;\r
+\r
+ if (ocl->buflen == 0 || ocl->bufalign==0)\r
+ return ERROR_FLASH_BANK_NOT_PROBED;\r
+\r
+ return ERROR_OK;\r
+}\r
--- /dev/null
+/***************************************************************************\r
+ * Copyright (C) 2007 by Pavel Chromy *\r
+ * chromy@asix.cz *\r
+ * *\r
+ * This program is free software; you can redistribute it and/or modify *\r
+ * it under the terms of the GNU General Public License as published by *\r
+ * the Free Software Foundation; either version 2 of the License, or *\r
+ * (at your option) any later version. *\r
+ * *\r
+ * This program is distributed in the hope that it will be useful, *\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
+ * GNU General Public License for more details. *\r
+ * *\r
+ * You should have received a copy of the GNU General Public License *\r
+ * along with this program; if not, write to the *\r
+ * Free Software Foundation, Inc., *\r
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
+ ***************************************************************************/\r
+#ifndef OCL_H\r
+#define OCL_H\r
+\r
+/* command/response mask */\r
+#define OCL_CMD_MASK 0xFFFF0000L\r
+\r
+/* commads */\r
+#define OCL_FLASH_BLOCK 0x0CFB0000L\r
+#define OCL_ERASE_BLOCK 0x0CEB0000L\r
+#define OCL_ERASE_ALL 0x0CEA0000L\r
+#define OCL_PROBE 0x0CBE0000L\r
+\r
+/* responses */\r
+#define OCL_CMD_DONE 0x0ACD0000L\r
+#define OCL_CMD_ERR 0x0ACE0000L\r
+#define OCL_CHKS_FAIL 0x0ACF0000L\r
+#define OCL_BUFF_OVER 0x0AB00000L\r
+\r
+#define OCL_CHKS_INIT 0xC100CD0CL\r
+\r
+#endif /* OCL_H */\r
--- /dev/null
+soft_reset_halt\r
+load_image at91sam7x_ocl.bin 0x200000\r
+resume 0x200000\r
+flash probe 0\r
--- /dev/null
+/****************************************************************************\r
+* Copyright (c) 2006 by Michael Fischer. All rights reserved.\r
+*\r
+* Redistribution and use in source and binary forms, with or without \r
+* modification, are permitted provided that the following conditions \r
+* are met:\r
+* \r
+* 1. Redistributions of source code must retain the above copyright \r
+* notice, this list of conditions and the following disclaimer.\r
+* 2. Redistributions in binary form must reproduce the above copyright\r
+* notice, this list of conditions and the following disclaimer in the \r
+* documentation and/or other materials provided with the distribution.\r
+* 3. Neither the name of the author nor the names of its contributors may \r
+* be used to endorse or promote products derived from this software \r
+* without specific prior written permission.\r
+*\r
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS \r
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL \r
+* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, \r
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, \r
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS \r
+* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED \r
+* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, \r
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF \r
+* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF \r
+* SUCH DAMAGE.\r
+*\r
+****************************************************************************\r
+*\r
+* History:\r
+*\r
+* 30.03.06 mifi First Version\r
+****************************************************************************/\r
+\r
+\r
+ENTRY(ResetHandler)\r
+SEARCH_DIR(.)\r
+\r
+/*\r
+ * Define stack size here\r
+ */\r
+FIQ_STACK_SIZE = 0x0100;\r
+IRQ_STACK_SIZE = 0x0100;\r
+ABT_STACK_SIZE = 0x0100;\r
+UND_STACK_SIZE = 0x0100;\r
+SVC_STACK_SIZE = 0x0100;\r
+\r
+\r
+MEMORY\r
+{\r
+ ram : org = 0x00200000, len = 64k\r
+}\r
+\r
+/*\r
+ * Do not change the next code\r
+ */\r
+SECTIONS\r
+{\r
+ .text :\r
+ {\r
+ *(.vectors);\r
+ . = ALIGN(4);\r
+ *(.init);\r
+ . = ALIGN(4);\r
+ *(.text);\r
+ . = ALIGN(4);\r
+ *(.rodata);\r
+ . = ALIGN(4);\r
+ *(.rodata*);\r
+ . = ALIGN(4);\r
+ *(.glue_7t);\r
+ . = ALIGN(4);\r
+ *(.glue_7);\r
+ . = ALIGN(4);\r
+ etext = .;\r
+ } > ram\r
+\r
+ .data :\r
+ {\r
+ PROVIDE (__data_start = .);\r
+ *(.data)\r
+ . = ALIGN(4);\r
+ edata = .;\r
+ _edata = .;\r
+ PROVIDE (__data_end = .);\r
+ } > ram\r
+\r
+ .bss :\r
+ {\r
+ PROVIDE (__bss_start = .);\r
+ *(.bss)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ PROVIDE (__bss_end = .);\r
+ \r
+ . = ALIGN(256);\r
+ \r
+ PROVIDE (__stack_start = .);\r
+ \r
+ PROVIDE (__stack_fiq_start = .);\r
+ . += FIQ_STACK_SIZE;\r
+ . = ALIGN(4);\r
+ PROVIDE (__stack_fiq_end = .);\r
+\r
+ PROVIDE (__stack_irq_start = .);\r
+ . += IRQ_STACK_SIZE;\r
+ . = ALIGN(4);\r
+ PROVIDE (__stack_irq_end = .);\r
+\r
+ PROVIDE (__stack_abt_start = .);\r
+ . += ABT_STACK_SIZE;\r
+ . = ALIGN(4);\r
+ PROVIDE (__stack_abt_end = .);\r
+\r
+ PROVIDE (__stack_und_start = .);\r
+ . += UND_STACK_SIZE;\r
+ . = ALIGN(4);\r
+ PROVIDE (__stack_und_end = .);\r
+\r
+ PROVIDE (__stack_svc_start = .);\r
+ . += SVC_STACK_SIZE;\r
+ . = ALIGN(4);\r
+ PROVIDE (__stack_svc_end = .);\r
+ PROVIDE (__stack_end = .);\r
+ PROVIDE (__heap_start = .); \r
+ } > ram\r
+ \r
+}\r
+/*** EOF ***/\r
+\r
--- /dev/null
+/****************************************************************************\r
+* Copyright (c) 2006 by Michael Fischer. All rights reserved.\r
+*\r
+* Redistribution and use in source and binary forms, with or without \r
+* modification, are permitted provided that the following conditions \r
+* are met:\r
+* \r
+* 1. Redistributions of source code must retain the above copyright \r
+* notice, this list of conditions and the following disclaimer.\r
+* 2. Redistributions in binary form must reproduce the above copyright\r
+* notice, this list of conditions and the following disclaimer in the \r
+* documentation and/or other materials provided with the distribution.\r
+* 3. Neither the name of the author nor the names of its contributors may \r
+* be used to endorse or promote products derived from this software \r
+* without specific prior written permission.\r
+*\r
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS \r
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL \r
+* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, \r
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, \r
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS \r
+* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED \r
+* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, \r
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF \r
+* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF \r
+* SUCH DAMAGE.\r
+*\r
+****************************************************************************\r
+*\r
+* History:\r
+*\r
+* 18.12.06 mifi First Version\r
+* The hardware initialization is based on the startup file\r
+* crtat91sam7x256_rom.S from NutOS 4.2.1. \r
+* Therefore partial copyright by egnite Software GmbH.\r
+****************************************************************************/\r
+\r
+/*\r
+ * Some defines for the program status registers\r
+ */\r
+ ARM_MODE_USER = 0x10 /* Normal User Mode */ \r
+ ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */\r
+ ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */\r
+ ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */\r
+ ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */\r
+ ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */\r
+ ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */\r
+ ARM_MODE_MASK = 0x1F\r
+ \r
+ I_BIT = 0x80 /* disable IRQ when I bit is set */\r
+ F_BIT = 0x40 /* disable IRQ when I bit is set */\r
+ \r
+/*\r
+ * Register Base Address\r
+ */\r
+ AIC_BASE = 0xFFFFF000\r
+ AIC_EOICR_OFF = 0x130\r
+ AIC_IDCR_OFF = 0x124\r
+\r
+ RSTC_MR = 0xFFFFFD08\r
+ RSTC_KEY = 0xA5000000\r
+ RSTC_URSTEN = 0x00000001\r
+\r
+ WDT_BASE = 0xFFFFFD40\r
+ WDT_MR_OFF = 0x00000004\r
+ WDT_WDDIS = 0x00008000\r
+\r
+ MC_BASE = 0xFFFFFF00\r
+ MC_FMR_OFF = 0x00000060\r
+ MC_FWS_1FWS = 0x00480100\r
+ \r
+ .section .vectors,"ax"\r
+ .code 32\r
+ \r
+/****************************************************************************/\r
+/* Vector table and reset entry */\r
+/****************************************************************************/\r
+_vectors:\r
+ ldr pc, ResetAddr /* Reset */\r
+ ldr pc, UndefAddr /* Undefined instruction */\r
+ ldr pc, SWIAddr /* Software interrupt */\r
+ ldr pc, PAbortAddr /* Prefetch abort */\r
+ ldr pc, DAbortAddr /* Data abort */\r
+ ldr pc, ReservedAddr /* Reserved */\r
+ ldr pc, IRQAddr /* IRQ interrupt */\r
+ ldr pc, FIQAddr /* FIQ interrupt */\r
+\r
+\r
+ResetAddr: .word ResetHandler\r
+UndefAddr: .word UndefHandler\r
+SWIAddr: .word SWIHandler\r
+PAbortAddr: .word PAbortHandler\r
+DAbortAddr: .word DAbortHandler\r
+ReservedAddr: .word 0\r
+IRQAddr: .word IRQHandler\r
+FIQAddr: .word FIQHandler\r
+\r
+ .ltorg\r
+\r
+ .section .init, "ax"\r
+ .code 32\r
+ \r
+ .global ResetHandler\r
+ .global ExitFunction\r
+ .extern main\r
+/****************************************************************************/\r
+/* Reset handler */\r
+/****************************************************************************/\r
+ResetHandler:\r
+ /*\r
+ * The watchdog is enabled after processor reset. Disable it.\r
+ */\r
+ ldr r1, =WDT_BASE\r
+ ldr r0, =WDT_WDDIS\r
+ str r0, [r1, #WDT_MR_OFF]\r
+\r
+ \r
+ /*\r
+ * Enable user reset: assertion length programmed to 1ms\r
+ */\r
+ ldr r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8))\r
+ ldr r1, =RSTC_MR\r
+ str r0, [r1, #0]\r
+\r
+ \r
+ /*\r
+ * Use 2 cycles for flash access.\r
+ */\r
+ ldr r1, =MC_BASE\r
+ ldr r0, =MC_FWS_1FWS\r
+ str r0, [r1, #MC_FMR_OFF]\r
+\r
+\r
+ /*\r
+ * Disable all interrupts. Useful for debugging w/o target reset.\r
+ */\r
+ ldr r1, =AIC_BASE\r
+ mvn r0, #0\r
+ str r0, [r1, #AIC_EOICR_OFF]\r
+ str r0, [r1, #AIC_IDCR_OFF]\r
+\r
+ \r
+ /*\r
+ * Setup a stack for each mode\r
+ */ \r
+ msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */ \r
+ ldr sp, =__stack_und_end\r
+ \r
+ msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */\r
+ ldr sp, =__stack_abt_end\r
+ \r
+ msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */ \r
+ ldr sp, =__stack_fiq_end\r
+ \r
+ msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */ \r
+ ldr sp, =__stack_irq_end\r
+ \r
+ msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */\r
+ ldr sp, =__stack_svc_end\r
+\r
+\r
+ /*\r
+ * Clear .bss section\r
+ */\r
+ ldr r1, =__bss_start\r
+ ldr r2, =__bss_end\r
+ ldr r3, =0\r
+bss_clear_loop:\r
+ cmp r1, r2\r
+ strne r3, [r1], #+4\r
+ bne bss_clear_loop\r
+ \r
+ \r
+ /*\r
+ * Jump to main\r
+ */\r
+ mrs r0, cpsr\r
+ bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */\r
+ msr cpsr, r0\r
+ \r
+ mov r0, #0 /* No arguments */\r
+ mov r1, #0 /* No arguments */\r
+ ldr r2, =main\r
+ mov lr, pc\r
+ bx r2 /* And jump... */\r
+ \r
+ExitFunction:\r
+ nop\r
+ nop\r
+ nop\r
+ b ExitFunction \r
+ \r
+\r
+/****************************************************************************/\r
+/* Default interrupt handler */\r
+/****************************************************************************/\r
+\r
+UndefHandler:\r
+ b UndefHandler\r
+ \r
+SWIHandler:\r
+ b SWIHandler\r
+\r
+PAbortHandler:\r
+ b PAbortHandler\r
+\r
+DAbortHandler:\r
+ b DAbortHandler\r
+ \r
+IRQHandler:\r
+ b IRQHandler\r
+ \r
+FIQHandler:\r
+ b FIQHandler\r
+ \r
+ .weak ExitFunction\r
+ .weak UndefHandler, PAbortHandler, DAbortHandler\r
+ .weak IRQHandler, FIQHandler\r
+\r
+ .ltorg\r
+/*** EOF ***/ \r
+ \r
+\rIndex: src/flash/ocl/at91sam7x/dcc.c\r
--- /dev/null
+/***************************************************************************\r
+ * Copyright (C) 2007 by Pavel Chromy *\r
+ * chromy@asix.cz *\r
+ * *\r
+ * This program is free software; you can redistribute it and/or modify *\r
+ * it under the terms of the GNU General Public License as published by *\r
+ * the Free Software Foundation; either version 2 of the License, or *\r
+ * (at your option) any later version. *\r
+ * *\r
+ * This program is distributed in the hope that it will be useful, *\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
+ * GNU General Public License for more details. *\r
+ * *\r
+ * You should have received a copy of the GNU General Public License *\r
+ * along with this program; if not, write to the *\r
+ * Free Software Foundation, Inc., *\r
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
+ ***************************************************************************/\r
+#include "dcc.h"\r
+\r
+\r
+/* debug channel read (debugger->MCU) */\r
+uint32 dcc_rd(void)\r
+{\r
+ volatile uint32 dcc_reg;\r
+\r
+ do {\r
+ asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) : );\r
+ } while ((dcc_reg&1)==0);\r
+\r
+ asm volatile ("mrc p14, 0, %0, C1, C0" : "=r" (dcc_reg) : );\r
+ return dcc_reg;\r
+}\r
+\r
+\r
+/* debug channel write (MCU->debugger) */\r
+int dcc_wr(uint32 data)\r
+{\r
+ volatile uint32 dcc_reg;\r
+\r
+ do {\r
+ asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) : );\r
+ /* operation controled by master, cancel operation\r
+ upon reception of data for immediate response */\r
+ if (dcc_reg&1) return -1;\r
+ } while (dcc_reg&2);\r
+\r
+ asm volatile ("mcr p14, 0, %0, C1, C0" : : "r" (data));\r
+ return 0;\r
+}\r
--- /dev/null
+/***************************************************************************\r
+ * Copyright (C) 2007 by Pavel Chromy *\r
+ * chromy@asix.cz *\r
+ * *\r
+ * This program is free software; you can redistribute it and/or modify *\r
+ * it under the terms of the GNU General Public License as published by *\r
+ * the Free Software Foundation; either version 2 of the License, or *\r
+ * (at your option) any later version. *\r
+ * *\r
+ * This program is distributed in the hope that it will be useful, *\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
+ * GNU General Public License for more details. *\r
+ * *\r
+ * You should have received a copy of the GNU General Public License *\r
+ * along with this program; if not, write to the *\r
+ * Free Software Foundation, Inc., *\r
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
+ ***************************************************************************/\r
+#ifndef dccH\r
+#define dccH\r
+\r
+#include "platform.h"\r
+\r
+/* debug channel read (debugger->MCU) */\r
+extern uint32 dcc_rd(void);\r
+\r
+/* debug channel write (MCU->debugger) */\r
+extern int dcc_wr(uint32 data);\r
+\r
+#endif\r
--- /dev/null
+/***************************************************************************\r
+ * Copyright (C) 2007 by Pavel Chromy *\r
+ * chromy@asix.cz *\r
+ * *\r
+ * This program is free software; you can redistribute it and/or modify *\r
+ * it under the terms of the GNU General Public License as published by *\r
+ * the Free Software Foundation; either version 2 of the License, or *\r
+ * (at your option) any later version. *\r
+ * *\r
+ * This program is distributed in the hope that it will be useful, *\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
+ * GNU General Public License for more details. *\r
+ * *\r
+ * You should have received a copy of the GNU General Public License *\r
+ * along with this program; if not, write to the *\r
+ * Free Software Foundation, Inc., *\r
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
+ ***************************************************************************/\r
+#include "platform.h"\r
+\r
+#include "ocl.h"\r
+#include "dcc.h"\r
+#include "samflash.h"\r
+\r
+\r
+#define BUFSIZE 1024 /* words, i.e. 4 KiB */\r
+uint32 buffer[1024];\r
+\r
+void cmd_flash(uint32 cmd)\r
+{\r
+ unsigned int len;\r
+ uint32 adr;\r
+ uint32 chksum;\r
+ unsigned int bi; /* buffer index */\r
+ unsigned int bi_start; /* receive start mark */\r
+ unsigned int bi_end; /* receive end mark */\r
+ unsigned int ofs;\r
+ int pagenum;\r
+ int result;\r
+\r
+ adr=dcc_rd();\r
+ len=cmd&0xffff;\r
+ ofs=adr%flash_page_size;\r
+ bi_start=ofs/4;\r
+ bi_end=(ofs+len+3)/4;\r
+\r
+ if (bi_end>BUFSIZE) {\r
+ dcc_wr(OCL_BUFF_OVER);\r
+ return;\r
+ }\r
+\r
+ chksum=OCL_CHKS_INIT;\r
+ for (bi=0; bi<bi_end; bi++) chksum^=buffer[bi]=dcc_rd();\r
+\r
+ if (dcc_rd()!=chksum) {\r
+ dcc_wr(OCL_CHKS_FAIL);\r
+ return;\r
+ }\r
+\r
+ /* fill in unused positions with unprogrammed values */\r
+ for (bi=0; bi<bi_start; bi++) buffer[bi]=0xffffffff;\r
+ for (bi=bi_end; bi%flash_page_size; bi++) buffer[bi]=0xffffffff;\r
+\r
+ result=0;\r
+ pagenum=adr/flash_page_size;\r
+ for (bi=0; bi<bi_end; bi+=flash_page_size/4) {\r
+ result=flash_page_program(buffer+bi, pagenum++);\r
+ if (result) break;\r
+ }\r
+\r
+ /* verify written data */\r
+ if (!result) result=flash_verify(adr, len, ((uint8 *)buffer)+ofs);\r
+\r
+ dcc_wr(OCL_CMD_DONE|result);\r
+}\r
+\r
+\r
+int main (void)\r
+{\r
+ uint32 cmd;\r
+\r
+ for (;;) {\r
+ cmd=dcc_rd();\r
+ switch (cmd&OCL_CMD_MASK) {\r
+ case OCL_PROBE:\r
+ dcc_wr(OCL_CMD_DONE|flash_init());\r
+ dcc_wr(0x100000); /* base */\r
+ dcc_wr(flash_page_count*flash_page_size); /* size */\r
+ dcc_wr(1); /* num_sectors */\r
+ dcc_wr(4096 | ((unsigned long) flash_page_size<<16)); /* buflen and bufalign */\r
+ break;\r
+ case OCL_ERASE_ALL:\r
+ dcc_wr(OCL_CMD_DONE|flash_erase_all());\r
+ break;\r
+ case OCL_FLASH_BLOCK:\r
+ cmd_flash(cmd);\r
+ break;\r
+ default:\r
+ /* unknown command */\r
+ dcc_wr(OCL_CMD_ERR);\r
+ break;\r
+ }\r
+ }\r
+\r
+ return(0); /* we shall never get here, just to supress compiler warning */\r
+}\r
--- /dev/null
+##############################################################################################\r
+# Start of default section\r
+#\r
+\r
+TRGT = arm-elf-\r
+CC = $(TRGT)gcc\r
+CP = $(TRGT)objcopy\r
+AS = $(TRGT)gcc -x assembler-with-cpp\r
+HEX = $(CP) -O ihex\r
+BIN = $(CP) -O binary\r
+OBJDUMP = $(TRGT)objdump\r
+\r
+MCU = arm7tdmi\r
+\r
+# List all default C defines here, like -D_DEBUG=1\r
+DDEFS = \r
+\r
+# List all default ASM defines here, like -D_DEBUG=1\r
+DADEFS = \r
+\r
+# List all default directories to look for include files here\r
+DINCDIR = \r
+\r
+# List the default directory to look for the libraries here\r
+DLIBDIR =\r
+\r
+# List all default libraries here\r
+DLIBS = \r
+\r
+#\r
+# End of default section\r
+##############################################################################################\r
+\r
+##############################################################################################\r
+# Start of user section\r
+#\r
+\r
+# Define project name here\r
+PROJECT = at91sam7x_ocl\r
+\r
+# Define linker script file here\r
+LDSCRIPT= at91sam7x_ram.ld\r
+\r
+# List all user C define here, like -D_DEBUG=1\r
+UDEFS = \r
+\r
+# Define ASM defines here\r
+UADEFS = \r
+\r
+# List C source files here\r
+SRC = main.c dcc.c samflash.c\r
+\r
+# List ASM source files here\r
+ASRC = crt.s\r
+\r
+# List all user directories here\r
+UINCDIR =\r
+\r
+# List the user directory to look for the libraries here\r
+ULIBDIR =\r
+\r
+# List all user libraries here\r
+ULIBS = \r
+\r
+# Define optimisation level here\r
+OPT = -O2\r
+\r
+#\r
+# End of user defines\r
+##############################################################################################\r
+\r
+\r
+INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR))\r
+LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))\r
+DEFS = $(DDEFS) $(UDEFS)\r
+ADEFS = $(DADEFS) $(UADEFS)\r
+OBJS = $(ASRC:.s=.o) $(SRC:.c=.o)\r
+LIBS = $(DLIBS) $(ULIBS)\r
+MCFLAGS = -mcpu=$(MCU)\r
+\r
+ASFLAGS = $(MCFLAGS) -g -gdwarf-2 -Wa,-amhls=$(<:.s=.lst) $(ADEFS)\r
+CPFLAGS = $(MCFLAGS) $(OPT) -gdwarf-2 -mthumb-interwork -fomit-frame-pointer -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS)\r
+LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR)\r
+\r
+# Generate dependency information\r
+#CPFLAGS += -MD -MP -MF .dep/$(@F).d\r
+\r
+#\r
+# makefile rules\r
+#\r
+\r
+all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).lst\r
+\r
+%o : %c\r
+ $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@\r
+\r
+%o : %s\r
+ $(AS) -c $(ASFLAGS) $< -o $@\r
+\r
+%elf: $(OBJS)\r
+ $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@\r
+\r
+%hex: %elf\r
+ $(HEX) $< $@\r
+\r
+%bin: %elf\r
+ $(BIN) $< $@\r
+\r
+%.lst: %.elf\r
+ $(OBJDUMP) -h -S $< > $@\r
+\r
+clean:\r
+ -rm -f $(OBJS)\r
+ -rm -f $(PROJECT).elf\r
+ -rm -f $(PROJECT).map\r
+ -rm -f $(PROJECT).hex\r
+ -rm -f $(PROJECT).bin\r
+ -rm -f $(PROJECT).lst\r
+ -rm -f $(SRC:.c=.c.bak)\r
+ -rm -f $(SRC:.c=.lst)\r
+ -rm -f $(ASRC:.s=.s.bak)\r
+ -rm -f $(ASRC:.s=.lst)\r
+ -rm -fR .dep\r
+\r
+# \r
+# Include the dependency files, should be the last of the makefile\r
+#\r
+#-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)\r
+\r
+# *** EOF ***
\ No newline at end of file
--- /dev/null
+/***************************************************************************\r
+ * Copyright (C) 2007 by Pavel Chromy *\r
+ * chromy@asix.cz *\r
+ * *\r
+ * This program is free software; you can redistribute it and/or modify *\r
+ * it under the terms of the GNU General Public License as published by *\r
+ * the Free Software Foundation; either version 2 of the License, or *\r
+ * (at your option) any later version. *\r
+ * *\r
+ * This program is distributed in the hope that it will be useful, *\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
+ * GNU General Public License for more details. *\r
+ * *\r
+ * You should have received a copy of the GNU General Public License *\r
+ * along with this program; if not, write to the *\r
+ * Free Software Foundation, Inc., *\r
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
+ ***************************************************************************/\r
+#ifndef OCL_H\r
+#define OCL_H\r
+\r
+/* command/response mask */\r
+#define OCL_CMD_MASK 0xFFFF0000L\r
+\r
+/* commads */\r
+#define OCL_FLASH_BLOCK 0x0CFB0000L\r
+#define OCL_ERASE_BLOCK 0x0CEB0000L\r
+#define OCL_ERASE_ALL 0x0CEA0000L\r
+#define OCL_PROBE 0x0CBE0000L\r
+\r
+/* responses */\r
+#define OCL_CMD_DONE 0x0ACD0000L\r
+#define OCL_CMD_ERR 0x0ACE0000L\r
+#define OCL_CHKS_FAIL 0x0ACF0000L\r
+#define OCL_BUFF_OVER 0x0AB00000L\r
+\r
+#define OCL_CHKS_INIT 0xC100CD0CL\r
+\r
+#endif /* OCL_H */\r
--- /dev/null
+/***************************************************************************\r
+ * Copyright (C) 2007 by Pavel Chromy *\r
+ * chromy@asix.cz *\r
+ * *\r
+ * This program is free software; you can redistribute it and/or modify *\r
+ * it under the terms of the GNU General Public License as published by *\r
+ * the Free Software Foundation; either version 2 of the License, or *\r
+ * (at your option) any later version. *\r
+ * *\r
+ * This program is distributed in the hope that it will be useful, *\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
+ * GNU General Public License for more details. *\r
+ * *\r
+ * You should have received a copy of the GNU General Public License *\r
+ * along with this program; if not, write to the *\r
+ * Free Software Foundation, Inc., *\r
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
+ ***************************************************************************/\r
+#ifndef platformH\r
+#define platformH\r
+\r
+#include "samregs.h"\r
+\r
+\r
+#define outb(_reg, _val) (*((volatile unsigned char *)(_reg)) = (_val))\r
+#define outw(_reg, _val) (*((volatile unsigned short *)(_reg)) = (_val))\r
+#define outr(_reg, _val) (*((volatile unsigned int *)(_reg)) = (_val))\r
+\r
+#define inb(_reg) (*((volatile unsigned char *)(_reg)))\r
+#define inw(_reg) (*((volatile unsigned short *)(_reg)))\r
+#define inr(_reg) (*((volatile unsigned int *)(_reg)))\r
+\r
+#define _BV(bit) (1 << (bit))\r
+\r
+\r
+typedef signed char int8;\r
+typedef unsigned char uint8;\r
+\r
+typedef signed short int16;\r
+typedef unsigned short uint16;\r
+\r
+typedef signed int int32;\r
+typedef unsigned int uint32;\r
+\r
+#endif\r
--- /dev/null
+/***************************************************************************\r
+ * Copyright (C) 2007 by Pavel Chromy *\r
+ * chromy@asix.cz *\r
+ * *\r
+ * This program is free software; you can redistribute it and/or modify *\r
+ * it under the terms of the GNU General Public License as published by *\r
+ * the Free Software Foundation; either version 2 of the License, or *\r
+ * (at your option) any later version. *\r
+ * *\r
+ * This program is distributed in the hope that it will be useful, *\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
+ * GNU General Public License for more details. *\r
+ * *\r
+ * You should have received a copy of the GNU General Public License *\r
+ * along with this program; if not, write to the *\r
+ * Free Software Foundation, Inc., *\r
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
+ ***************************************************************************/\r
+#include "samflash.h"\r
+\r
+\r
+unsigned int flash_page_count=1024;\r
+unsigned int flash_page_size=256;\r
+\r
+/* pages per lock bit */\r
+unsigned int flash_lock_pages=1024/16;\r
+\r
+\r
+/* detect chip and set loader parameters */\r
+int flash_init(void)\r
+{\r
+ unsigned int nvpsiz;\r
+\r
+ nvpsiz=(inr(DBGU_CIDR)>>8)&0xf;\r
+\r
+ switch (nvpsiz) {\r
+ case 3:\r
+ /* AT91SAM7x32 */\r
+ flash_page_count=256;\r
+ flash_page_size=128;\r
+ flash_lock_pages=256/8;\r
+ break;\r
+ case 5:\r
+ /* AT91SAM7x64 */\r
+ flash_page_count=512;\r
+ flash_page_size=128;\r
+ flash_lock_pages=512/16;\r
+ break;\r
+ case 7:\r
+ /* AT91SAM7x128*/\r
+ flash_page_count=512;\r
+ flash_page_size=256;\r
+ flash_lock_pages=512/8;\r
+ break;\r
+ case 9:\r
+ /* AT91SAM7x256 */\r
+ flash_page_count=1024;\r
+ flash_page_size=256;\r
+ flash_lock_pages=1024/16;\r
+ break;\r
+ case 10:\r
+ /* AT91SAM7x512 */\r
+ flash_page_count=2048;\r
+ flash_page_size=256;\r
+ flash_lock_pages=2048/32;\r
+ break;\r
+ default:\r
+ return FLASH_STAT_INITE;\r
+ }\r
+ return FLASH_STAT_OK;\r
+}\r
+\r
+\r
+/* program single flash page */\r
+int flash_page_program(uint32 *data, int page_num)\r
+{\r
+ int i;\r
+ int efc_ofs;\r
+\r
+ uint32 *flash_ptr;\r
+ uint32 *data_ptr;\r
+\r
+ /* select proper controller */\r
+ if (page_num>=1024) efc_ofs=0x10;\r
+ else efc_ofs=0;\r
+\r
+ /* wait until FLASH is ready, just for sure */\r
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);\r
+\r
+ /* calculate page address, only lower 8 bits are used to address the latch,\r
+ but the upper part of address is needed for writing to proper EFC */\r
+ flash_ptr=(uint32 *)(FLASH_AREA_ADDR+(page_num*flash_page_size));\r
+ data_ptr=data;\r
+\r
+ /* copy data to latch */\r
+ for (i=flash_page_size/4; i; i--) {\r
+ /* we do not use memcpy to be sure that only 32 bit access is used */\r
+ *(flash_ptr++)=*(data_ptr++);\r
+ }\r
+\r
+ /* page number and page write command to FCR */\r
+ outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | MC_KEY | MC_FCMD_WP);\r
+\r
+ /* wait until it's done */\r
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);\r
+\r
+ /* check for errors */\r
+ if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;\r
+ if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;\r
+\r
+#if 0\r
+ /* verify written data */\r
+ flash_ptr=(uint32 *)(FLASH_AREA_ADDR+(page_num*flash_page_size));\r
+ data_ptr=data;\r
+\r
+ for (i=flash_page_size/4; i; i--) {\r
+ if (*(flash_ptr++)!=*(data_ptr++)) return FLASH_STAT_VERIFE;\r
+ }\r
+#endif\r
+\r
+ return FLASH_STAT_OK;\r
+}\r
+\r
+\r
+int flash_erase_plane(int efc_ofs)\r
+{\r
+ unsigned int lockbits;\r
+ int page_num;\r
+\r
+ page_num=0;\r
+ lockbits=inr(MC_FSR+efc_ofs)>>16;\r
+ while (lockbits) {\r
+ if (lockbits&1) {\r
+\r
+ /* wait until FLASH is ready, just for sure */\r
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);\r
+\r
+ outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | 0x5a000004);\r
+\r
+ /* wait until it's done */\r
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);\r
+\r
+ /* check for errors */\r
+ if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;\r
+ if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;\r
+\r
+ }\r
+ if ((page_num+=flash_lock_pages)>flash_page_count) break;\r
+ lockbits>>=1;\r
+ }\r
+\r
+ /* wait until FLASH is ready, just for sure */\r
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);\r
+\r
+ /* erase all command to FCR */\r
+ outr(MC_FCR+efc_ofs, 0x5a000008);\r
+\r
+ /* wait until it's done */\r
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);\r
+\r
+ /* check for errors */\r
+ if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;\r
+ if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;\r
+\r
+ /* set no erase before programming */\r
+ outr(MC_FMR+efc_ofs, inr(MC_FMR+efc_ofs)|0x80);\r
+\r
+ return FLASH_STAT_OK;\r
+}\r
+\r
+\r
+/* erase whole chip */\r
+int flash_erase_all(void)\r
+{\r
+ int result;\r
+ \r
+ if ((result=flash_erase_plane(0))!=FLASH_STAT_OK) return result;\r
+\r
+ /* the second flash controller, if any */\r
+ if (flash_page_count>1024) result=flash_erase_plane(0x10);\r
+\r
+ return result;\r
+}\r
+\r
+\r
+int flash_verify(uint32 adr, unsigned int len, uint8 *src)\r
+{\r
+ unsigned char *flash_ptr;\r
+\r
+ flash_ptr=(uint8 *)FLASH_AREA_ADDR+adr;\r
+ for ( ;len; len--) {\r
+ if (*(flash_ptr++)!=*(src++)) return FLASH_STAT_VERIFE;\r
+ }\r
+ return FLASH_STAT_OK;\r
+}\r
--- /dev/null
+/***************************************************************************\r
+ * Copyright (C) 2007 by Pavel Chromy *\r
+ * chromy@asix.cz *\r
+ * *\r
+ * This program is free software; you can redistribute it and/or modify *\r
+ * it under the terms of the GNU General Public License as published by *\r
+ * the Free Software Foundation; either version 2 of the License, or *\r
+ * (at your option) any later version. *\r
+ * *\r
+ * This program is distributed in the hope that it will be useful, *\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
+ * GNU General Public License for more details. *\r
+ * *\r
+ * You should have received a copy of the GNU General Public License *\r
+ * along with this program; if not, write to the *\r
+ * Free Software Foundation, Inc., *\r
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
+ ***************************************************************************/\r
+#ifndef samflashH\r
+#define samflashH\r
+\r
+#include "platform.h"\r
+\r
+#define FLASH_AREA_ADDR 0x100000\r
+\r
+#define FLASH_STAT_OK 0\r
+#define FLASH_STAT_PROGE 1\r
+#define FLASH_STAT_LOCKE 2\r
+#define FLASH_STAT_VERIFE 3\r
+#define FLASH_STAT_INITE 4\r
+\r
+extern unsigned int flash_page_count;\r
+extern unsigned int flash_page_size; /* words */\r
+\r
+/* detect chip and set loader parameters */\r
+extern int flash_init(void);\r
+\r
+/* program single flash page */\r
+extern int flash_page_program(uint32 *data, int page_num);\r
+\r
+/* erase whole chip */\r
+extern int flash_erase_all(void);\r
+\r
+/* verify written data */\r
+extern int flash_verify(uint32 adr, unsigned int len, uint8 *src);\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the copyright holders nor the names of\r
+ * contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS\r
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE\r
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\r
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\r
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF\r
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * For additional information see http://www.ethernut.de/\r
+ */\r
+\r
+\r
+#ifndef samregsH\r
+#define samregsH\r
+\r
+\r
+/*\r
+ * Register definitions below copied from NutOS\r
+ */\r
+\r
+#define DBGU_BASE 0xFFFFF200 /*!< \brief DBGU base address. */\r
+\r
+#define DBGU_CIDR_OFF 0x00000040 /*!< \brief DBGU chip ID register offset. */\r
+#define DBGU_CIDR (DBGU_BASE + DBGU_CIDR_OFF) /*!< \brief DBGU chip ID register. */\r
+\r
+\r
+#define MC_BASE 0xFFFFFF00 /*!< \brief Memory controller base. */\r
+\r
+#define MC_FMR_OFF 0x00000060 /*!< \brief MC flash mode register offset. */\r
+#define MC_FMR (MC_BASE + MC_FMR_OFF) /*!< \brief MC flash mode register address. */\r
+#define MC_FRDY 0x00000001 /*!< \brief Flash ready. */\r
+#define MC_LOCKE 0x00000004 /*!< \brief Lock error. */\r
+#define MC_PROGE 0x00000008 /*!< \brief Programming error. */\r
+#define MC_NEBP 0x00000080 /*!< \brief No erase before programming. */\r
+#define MC_FWS_MASK 0x00000300 /*!< \brief Flash wait state mask. */\r
+#define MC_FWS_1R2W 0x00000000 /*!< \brief 1 cycle for read, 2 for write operations. */\r
+#define MC_FWS_2R3W 0x00000100 /*!< \brief 2 cycles for read, 3 for write operations. */\r
+#define MC_FWS_3R4W 0x00000200 /*!< \brief 3 cycles for read, 4 for write operations. */\r
+#define MC_FWS_4R4W 0x00000300 /*!< \brief 4 cycles for read and write operations. */\r
+#define MC_FMCN_MASK 0x00FF0000 /*!< \brief Flash microsecond cycle number mask. */\r
+\r
+#define MC_FCR_OFF 0x00000064 /*!< \brief MC flash command register offset. */\r
+#define MC_FCR (MC_BASE + MC_FCR_OFF) /*!< \brief MC flash command register address. */\r
+#define MC_FCMD_MASK 0x0000000F /*!< \brief Flash command mask. */\r
+#define MC_FCMD_NOP 0x00000000 /*!< \brief No command. */\r
+#define MC_FCMD_WP 0x00000001 /*!< \brief Write page. */\r
+#define MC_FCMD_SLB 0x00000002 /*!< \brief Set lock bit. */\r
+#define MC_FCMD_WPL 0x00000003 /*!< \brief Write page and lock. */\r
+#define MC_FCMD_CLB 0x00000004 /*!< \brief Clear lock bit. */\r
+#define MC_FCMD_EA 0x00000008 /*!< \brief Erase all. */\r
+#define MC_FCMD_SGPB 0x0000000B /*!< \brief Set general purpose NVM bit. */\r
+#define MC_FCMD_CGPB 0x0000000D /*!< \brief Clear general purpose NVM bit. */\r
+#define MC_FCMD_SSB 0x0000000F /*!< \brief Set security bit. */\r
+#define MC_PAGEN_MASK 0x0003FF00 /*!< \brief Page number mask. */\r
+#define MC_KEY 0x5A000000 /*!< \brief Writing protect key. */\r
+\r
+#define MC_FSR_OFF 0x00000068 /*!< \brief MC flash status register offset. */\r
+#define MC_FSR (MC_BASE + MC_FSR_OFF) /*!< \brief MC flash status register address. */\r
+#define MC_SECURITY 0x00000010 /*!< \brief Security bit status. */\r
+\r
+\r
+#endif\r
#define ERROR_TARGET_DATA_ABORT (-307)
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE (-308)
#define ERROR_TARGET_TRANSLATION_FAULT (-309)
+#define ERROR_TARGET_NOT_RUNNING (-310)
#endif /* TARGET_H */
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