Small tidy up of the new MicroBlaze port layer.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1458 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/FreeRTOS_Source/portable/GCC/MicroBlaze/port.c b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/FreeRTOS_Source/portable/GCC/MicroBlaze/port.c
index 05710e90b626756ded853cb15247b198dcd8f5ad..38d271c55d1998e1015ccfd5795d02c8d2b5085f 100644 (file)
--- a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/FreeRTOS_Source/portable/GCC/MicroBlaze/port.c
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/FreeRTOS_Source/portable/GCC/MicroBlaze/port.c
@@ -68,16 +68,16 @@
 #include <xintc_i.h>\r
 #include <xtmrctr.h>\r
 #include <xil_exception.h>\r
-\r
-/* Tasks are started with interrupts disabled as they will have their interrupts\r
-enabled as the task starts (when its context is restored for the first time). */\r
-#define portINITIAL_MSR_STATE          ( ( portSTACK_TYPE ) 0x00 )\r
+#include <mb_interface.h>\r
 \r
 /* Tasks are started with a critical section nesting of 0 - however prior\r
 to the scheduler being commenced we don't want the critical nesting level\r
 to reach zero, so it is initialised to a high value. */\r
 #define portINITIAL_NESTING_VALUE      ( 0xff )\r
 \r
+/* The bit within the MSR register that enabled/disables interrupts. */\r
+#define portMSR_IE                                     ( 0x02U )\r
+\r
 /*-----------------------------------------------------------*/\r
 \r
 /*\r
@@ -119,19 +119,6 @@ extern void *_SDA2_BASE_, *_SDA_BASE_;
 const unsigned long ulR2 = ( unsigned long ) &_SDA2_BASE_;\r
 const unsigned long ulR13 = ( unsigned long ) &_SDA_BASE_;\r
 \r
-#if 0\r
-//_RB_\r
-       #ifdef XPAR_MICROBLAZE_USE_ICACHE\r
-               microblaze_invalidate_icache();\r
-               microblaze_enable_icache();\r
-       #endif\r
-\r
-       #ifdef XPAR_MICROBLAZE_USE_DCACHE\r
-               microblaze_invalidate_dcache();\r
-               microblaze_enable_dcache();\r
-       #endif\r
-#endif\r
-\r
        /* Place a few bytes of known values on the bottom of the stack. \r
        This is essential for the Microblaze port and these lines must\r
        not be omitted.  The parameter value will overwrite the \r
@@ -219,8 +206,10 @@ const unsigned long ulR13 = ( unsigned long ) &_SDA_BASE_;
        *pxTopOfStack = ( portSTACK_TYPE ) 0x1e;        /* R30 - must be saved across function calls. Callee-save. */\r
        pxTopOfStack--;\r
 \r
-       /* The MSR is stacked between R30 and R31. */\r
-       *pxTopOfStack = portINITIAL_MSR_STATE;\r
+       /* The MSR is stacked between R30 and R31.  This should have interrupts\r
+       disabled.  Each task will enable interrupts automatically when it enters\r
+       the running state for the first time. */\r
+       *pxTopOfStack = mfmsr() & ~portMSR_IE;\r
        pxTopOfStack--;\r
 \r
        *pxTopOfStack = ( portSTACK_TYPE ) 0x1f;        /* R31 - must be saved across function calls. Callee-save. */\r