Add low level Ethernet driver files to the RX RDK project.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1080 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/webserver/phy.c b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/webserver/phy.c
new file mode 100644 (file)
index 0000000..f11e4cd
--- /dev/null
+++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/webserver/phy.c
@@ -0,0 +1,467 @@
+/******************************************************************************\r
+* DISCLAIMER\r
+\r
+* This software is supplied by Renesas Technology Corp. and is only \r
+* intended for use with Renesas products. No other uses are authorized.\r
+\r
+* This software is owned by Renesas Technology Corp. and is protected under \r
+* all applicable laws, including copyright laws.\r
+\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES\r
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, \r
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A \r
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY \r
+* DISCLAIMED.\r
+\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
+* TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES \r
+* FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS \r
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+\r
+* Renesas reserves the right, without notice, to make changes to this \r
+* software and to discontinue the availability of this software.  \r
+* By using this software, you agree to the additional terms and \r
+* conditions found by accessing the following link:\r
+* http://www.renesas.com/disclaimer\r
+******************************************************************************\r
+* Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved.\r
+*******************************************************************************        \r
+* File Name    : phy.c\r
+* Version      : 1.01\r
+* Description  : Ethernet PHY device driver\r
+******************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+*         : 15.02.2010 1.00    First Release\r
+*         : 06.04.2010 1.01    RX62N changes\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Includes   <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "iodefine.h"\r
+#include "r_ether.h"\r
+#include "phy.h"\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+uint16_t  _phy_read( uint16_t reg_addr );\r
+void  _phy_write( uint16_t reg_addr, uint16_t data );\r
+void  _phy_preamble( void );\r
+void  _phy_reg_set( uint16_t reg_addr, int32_t option );\r
+void  _phy_reg_read( uint16_t *data );\r
+void  _phy_reg_write( uint16_t data );\r
+void  _phy_ta_z0( void );\r
+void  _phy_ta_10( void );\r
+void  _phy_mii_write_1( void );\r
+void  _phy_mii_write_0( void );\r
+\r
+/**\r
+ * External functions\r
+ */\r
+\r
+/******************************************************************************\r
+* Function Name: phy_init\r
+* Description  : Resets Ethernet PHY device\r
+* Arguments    : none\r
+* Return Value : none\r
+******************************************************************************/\r
+int16_t  phy_init( void )\r
+{\r
+  uint16_t reg;\r
+  uint32_t count;\r
+\r
+  /* Reset PHY */\r
+  _phy_write(BASIC_MODE_CONTROL_REG, 0x8000);\r
+\r
+  count = 0;\r
+\r
+  do\r
+  {\r
+         vTaskDelay( 2 / portTICK_RATE_MS );\r
+      reg = _phy_read(BASIC_MODE_CONTROL_REG);\r
+         count++;\r
+  } while (reg & 0x8000 && count < PHY_RESET_WAIT);\r
+\r
+  if( count < PHY_RESET_WAIT )\r
+  {      \r
+       return R_PHY_OK;\r
+  }\r
+  \r
+  return R_PHY_ERROR;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: phy_set_100full\r
+* Description  : Set Ethernet PHY device to 100 Mbps full duplex\r
+* Arguments    : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void phy_set_100full( void )\r
+{\r
+       _phy_write(BASIC_MODE_CONTROL_REG, 0x2100);\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: phy_set_10half\r
+* Description  : Sets Ethernet PHY device to 10 Mbps half duplexR\r
+* Arguments    : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void phy_set_10half( void )\r
+{\r
+       _phy_write(BASIC_MODE_CONTROL_REG, 0x0000);\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: phy_set_autonegotiate\r
+* Description  : Starts autonegotiate and reports the other side's \r
+*              : physical capability\r
+* Arguments    : none\r
+* Return Value : bit 8 - Full duplex 100 mbps\r
+*              : bit 7 - Half duplex 100 mbps\r
+*              : bit 6 - Full duplex 10 mbps\r
+*              : bit 5 - Half duplex 10 mbps\r
+*              : bit 4:0 - Always set to 00001 (IEEE 802.3)\r
+*              : -1 if error\r
+******************************************************************************/\r
+int16_t phy_set_autonegotiate( void )\r
+{\r
+  uint16_t reg;\r
+  uint32_t count;\r
+\r
+  _phy_write(AN_ADVERTISEMENT_REG, 0x01E1);\r
+  _phy_write(BASIC_MODE_CONTROL_REG, 0x1200);\r
+  \r
+  count = 0;\r
+\r
+  do\r
+  {\r
+      reg = _phy_read(BASIC_MODE_STATUS_REG);\r
+      count++;\r
+         vTaskDelay( 100 / portTICK_RATE_MS );\r
+  } while (!(reg & 0x0020) && (count < PHY_AUTO_NEGOTIATON_WAIT));\r
+\r
+  if (count >= PHY_AUTO_NEGOTIATON_WAIT)\r
+  {\r
+      return R_PHY_ERROR;\r
+  }\r
+  else\r
+  {\r
+         /* National DP83640 fix */\r
+         _phy_write(0x13, 0x0006);\r
+         reg = _phy_read(0x14);\r
+         _phy_write(0x14, (reg&0x7FFF)); \r
+      _phy_write(0x13, 0x0000);\r
+         \r
+      /* Get the link partner response */\r
+         reg = (int16_t)_phy_read(AN_LINK_PARTNER_ABILITY_REG);\r
+         \r
+         if (reg & ( 1 << 8 ) )\r
+         {\r
+                 return PHY_LINK_100F;\r
+         }\r
+         if (reg & ( 1 << 7 ) )\r
+         {\r
+                 return PHY_LINK_100H;\r
+         }\r
+         if (reg & ( 1 << 6 ) )\r
+         {\r
+                 return PHY_LINK_10F;\r
+         }\r
+         if (reg & 1 << 5 )\r
+         {\r
+                 return PHY_LINK_10H;\r
+         }       \r
+\r
+         return (-1);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+ * Internal functions\r
+ */\r
+\r
+/******************************************************************************\r
+* Function Name: _phy_read\r
+* Description  : Reads a PHY register\r
+* Arguments    : reg_addr - address of the PHY register\r
+* Return Value : read value\r
+******************************************************************************/\r
+uint16_t _phy_read( uint16_t reg_addr )\r
+{\r
+  uint16_t data;\r
+\r
+  _phy_preamble();\r
+  _phy_reg_set( reg_addr, PHY_READ );\r
+  _phy_ta_z0();\r
+  _phy_reg_read( &data );\r
+  _phy_ta_z0();\r
+\r
+  return( data );\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: _phy_write\r
+* Description  : Writes to a PHY register\r
+* Arguments    : reg_addr - address of the PHY register\r
+*              : data - value\r
+* Return Value : none\r
+******************************************************************************/\r
+void  _phy_write( uint16_t reg_addr, uint16_t data )\r
+{\r
+  _phy_preamble();\r
+  _phy_reg_set( reg_addr, PHY_WRITE );\r
+  _phy_ta_10();\r
+  _phy_reg_write( data );\r
+  _phy_ta_z0();\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: _phy_preamble\r
+* Description  : As preliminary preparation for access to the PHY module register,\r
+*                "1" is output via the MII management interface.                  \r
+* Arguments    : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void  _phy_preamble( void )\r
+{\r
+  int16_t i;\r
+\r
+  i = 32;\r
+  while( i > 0 )\r
+  {\r
+    _phy_mii_write_1();\r
+    i--;\r
+  }\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: _phy_reg_set\r
+* Description  : Sets a PHY device to read or write mode\r
+* Arguments    : reg_addr - address of the PHY register\r
+*              : option - mode\r
+* Return Value : none\r
+******************************************************************************/\r
+void  _phy_reg_set( uint16_t reg_addr, int32_t option )\r
+{\r
+  int32_t    i;\r
+  uint16_t data;\r
+\r
+  data = 0;\r
+  data = (PHY_ST << 14);        /* ST code    */\r
+\r
+  if( option == PHY_READ )\r
+  {\r
+    data |= (PHY_READ << 12);  /* OP code(RD)  */\r
+  }\r
+  else\r
+  {\r
+    data |= (PHY_WRITE << 12);  /* OP code(WT)  */\r
+  }\r
+\r
+  data |= (PHY_ADDR << 7);    /* PHY Address  */\r
+  data |= (reg_addr << 2);    /* Reg Address  */\r
+\r
+  i = 14;\r
+  while( i > 0 )\r
+  {\r
+    if( (data & 0x8000) == 0 )\r
+    {\r
+      _phy_mii_write_0();\r
+    }\r
+    else\r
+    {\r
+      _phy_mii_write_1();\r
+    }\r
+    data <<= 1;\r
+    i--;\r
+  }\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: _phy_reg_read\r
+* Description  : Reads PHY register through MII interface\r
+* Arguments    : data - pointer to store the data read\r
+* Return Value : none\r
+******************************************************************************/\r
+void  _phy_reg_read( uint16_t *data )\r
+{\r
+  int32_t      i, j;\r
+  uint16_t   reg_data;\r
+\r
+  reg_data = 0;\r
+  i = 16;\r
+  while( i > 0 )\r
+  {\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000000;\r
+    }\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000001;\r
+    }\r
+    \r
+       reg_data <<= 1;\r
+    reg_data |= (uint16_t)((ETHERC.PIR.LONG & 0x00000008) >> 3);  /* MDI read  */\r
+\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000001;\r
+    }\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000000;\r
+    }\r
+    i--;\r
+  }\r
+  *data = reg_data;\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: _phy_reg_write\r
+* Description  : Writes to PHY register through MII interface\r
+* Arguments    : data - value to write\r
+* Return Value : none\r
+******************************************************************************/\r
+void  _phy_reg_write( uint16_t data )\r
+{\r
+  int32_t  i;\r
+\r
+  i = 16;\r
+  while( i > 0 )\r
+  {\r
+    if( (data & 0x8000) == 0 )\r
+    {\r
+      _phy_mii_write_0();\r
+    }\r
+    else\r
+    {\r
+      _phy_mii_write_1();\r
+    }\r
+    i--;\r
+    data <<= 1;\r
+  }\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: _phy_ta_z0\r
+* Description  : Performs bus release so that PHY can drive data\r
+*              : for read operation \r
+* Arguments    : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void  _phy_ta_z0( void )\r
+{\r
+    int32_t j;\r
+\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000000;\r
+    }\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000001;\r
+    }\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000001;\r
+    }\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000000;\r
+    }\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: _phy_ta_10\r
+* Description  : Switches data bus so MII interface can drive data\r
+*              : for write operation \r
+* Arguments    : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void _phy_ta_10(void)\r
+{\r
+    _phy_mii_write_1();\r
+    _phy_mii_write_0();\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: _phy_mii_write_1\r
+* Description  : Outputs 1 to the MII interface \r
+* Arguments    : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void  _phy_mii_write_1( void )\r
+{\r
+    int32_t j;\r
+\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000006;\r
+    }\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000007;\r
+    }\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000007;\r
+    }\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000006;\r
+    }\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: _phy_mii_write_0\r
+* Description  : Outputs 0 to the MII interface \r
+* Arguments    : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void  _phy_mii_write_0( void )\r
+{\r
+    int32_t j;\r
+\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000002;\r
+    }\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000003;\r
+    }\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000003;\r
+    }\r
+    for(j = MDC_WAIT; j > 0; j--)\r
+       {\r
+        ETHERC.PIR.LONG = 0x00000002;\r
+    }\r
+}\r
+\r
+\r

diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/webserver/phy.h b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/webserver/phy.h
new file mode 100644 (file)
index 0000000..2736b69
--- /dev/null
+++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/webserver/phy.h
@@ -0,0 +1,84 @@
+/******************************************************************************\r
+* DISCLAIMER\r
+* Please refer to http://www.renesas.com/disclaimer\r
+******************************************************************************\r
+  Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved.\r
+*******************************************************************************\r
+* File Name    : phy.h\r
+* Version      : 1.02\r
+* Description  : Ethernet PHY device driver\r
+******************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+*         : 15.02.2010 1.00    First Release\r
+*         : 17.03.2010 1.01    Modification of macro definitions for access timing\r
+*         : 06.04.2010 1.02    RX62N changes\r
+******************************************************************************/\r
+\r
+#ifndef        PHY_H\r
+#define        PHY_H\r
+\r
+/******************************************************************************\r
+Includes   <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include <stdint.h>\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+/* Standard PHY Registers */\r
+#define        BASIC_MODE_CONTROL_REG          0       \r
+#define        BASIC_MODE_STATUS_REG           1       \r
+#define        PHY_IDENTIFIER1_REG                 2       \r
+#define        PHY_IDENTIFIER2_REG                 3       \r
+#define        AN_ADVERTISEMENT_REG            4       \r
+#define        AN_LINK_PARTNER_ABILITY_REG     5       \r
+#define        AN_EXPANSION_REG                    6\r
+\r
+/* Media Independent Interface */\r
+#define  PHY_ST    1\r
+#define  PHY_READ  2\r
+#define  PHY_WRITE 1\r
+#define  PHY_ADDR  0x01\r
+\r
+#define  MDC_WAIT  2\r
+\r
+/* PHY return definitions */\r
+#define R_PHY_OK     0\r
+#define R_PHY_ERROR -1\r
+\r
+/* Auto-Negotiation Link Partner Status */\r
+#define PHY_AN_LINK_PARTNER_100BASE    0x0180\r
+#define PHY_AN_LINK_PARTNER_FULL       0x0140\r
+#define PHY_AN_COMPLETE                                ( 1 << 5 )\r
+\r
+/*\r
+ *     Wait counter definitions of PHY-LSI initialization\r
+ *     ICLK = 96MHz\r
+*/\r
+#define PHY_RESET_WAIT                         0x00000020L\r
+#define PHY_AUTO_NEGOTIATON_WAIT       75L\r
+\r
+#define PHY_AN_ENABLE                          0x1200\r
+#define PHY_AN_10_100_F_H                      0xde1\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+/**\r
+ * External prototypes\r
+ **/\r
+int16_t        phy_init( void );\r
+void   phy_set_100full( void );\r
+void   phy_set_10half( void );\r
+int16_t        phy_set_autonegotiate( void );\r
+\r
+#endif /* PHY_H */\r
+\r

diff --git a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/webserver/r_ether.h b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/webserver/r_ether.h
new file mode 100644 (file)
index 0000000..ca8e76e
--- /dev/null
+++ b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/webserver/r_ether.h
@@ -0,0 +1,158 @@
+/******************************************************************************\r
+* DISCLAIMER\r
+* Please refer to http://www.renesas.com/disclaimer\r
+******************************************************************************\r
+  Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved.\r
+*******************************************************************************\r
+* File Name    : r_ether.h\r
+* Version      : 1.02\r
+* Description  : Ethernet module device driver\r
+******************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+*         : 15.02.2010 1.00    First Release\r
+*         : 03.03.2010 1.01    Buffer size is aligned on the 32-byte boundary.\r
+*         : 04.06.2010 1.02    RX62N changes\r
+******************************************************************************/\r
+\r
+#ifndef        R_ETHER_H\r
+#define        R_ETHER_H\r
+\r
+/******************************************************************************\r
+Includes   <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include <stdint.h>\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+struct Descriptor\r
+{\r
+       __evenaccess uint32_t   status;\r
+#if __LIT                               \r
+/* Little endian */\r
+       __evenaccess uint16_t   size;\r
+       __evenaccess uint16_t   bufsize;\r
+#else                                   \r
+/* Big endian */\r
+       __evenaccess uint16_t   bufsize;\r
+       __evenaccess uint16_t   size;\r
+\r
+#endif\r
+       int8_t                                  *buf_p;\r
+       struct Descriptor               *next;\r
+};\r
+\r
+typedef struct Descriptor ethfifo;\r
+\r
+typedef enum _NETLNK\r
+{\r
+    PHY_NO_LINK = 0,\r
+    PHY_LINK_10H,\r
+    PHY_LINK_10F,\r
+    PHY_LINK_100H,\r
+    PHY_LINK_100F\r
+    \r
+} NETLNK;\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+#define        BUFSIZE   256                   /* Must be 32-bit aligned */\r
+#define ENTRY     8                     /* Number of RX and TX buffers */\r
+\r
+#define  ACT      0x80000000\r
+#define  DL       0x40000000\r
+#define  FP1      0x20000000\r
+#define  FP0      0x10000000\r
+#define  FE       0x08000000\r
+\r
+#define  RFOVER   0x00000200\r
+#define  RAD      0x00000100\r
+#define  RMAF     0x00000080\r
+#define  RRF      0x00000010\r
+#define  RTLF     0x00000008\r
+#define  RTSF     0x00000004\r
+#define  PRE      0x00000002\r
+#define  CERF     0x00000001\r
+\r
+#define  TAD      0x00000100\r
+#define  CND      0x00000008\r
+#define  DLC      0x00000004\r
+#define  CD       0x00000002\r
+#define  TRO      0x00000001\r
+\r
+/** \r
+ * Renesas Ethernet API return defines\r
+ **/\r
+#define R_ETHER_OK          0\r
+#define R_ETHER_ERROR       -1\r
+\r
+/*     Ether Interface definitions     */\r
+#define ETH_RMII_MODE  0\r
+#define ETH_MII_MODE   1\r
+/*     Select Ether Interface Mode     */\r
+#define ETH_MODE_SEL   ETH_MII_MODE\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+/** \r
+ * Renesas Ethernet API prototypes\r
+ **/\r
+int32_t R_Ether_Open(uint32_t ch, uint8_t mac_addr[]);\r
+int32_t R_Ether_Close(uint32_t ch);\r
+int32_t R_Ether_Write(uint32_t ch, void *buf, uint32_t len);\r
+int32_t R_Ether_Read(uint32_t ch, void *buf);\r
+\r
+\r
+/****************************************************/\r
+/* Ethernet statistic collection data */\r
+struct enet_stats\r
+{\r
+  uint32_t  rx_packets;      /* total packets received    */\r
+  uint32_t  tx_packets;      /* total packets transmitted  */\r
+  uint32_t  rx_errors;       /* bad packets received      */\r
+  uint32_t  tx_errors;       /* packet transmit problems    */\r
+  uint32_t  rx_dropped;      /* no space in buffers      */\r
+  uint32_t  tx_dropped;      /* no space available      */\r
+  uint32_t  multicast;       /* multicast packets received  */\r
+  uint32_t  collisions;\r
+\r
+  /* detailed rx_errors: */\r
+  uint32_t  rx_length_errors;\r
+  uint32_t  rx_over_errors;    /* receiver ring buffer overflow  */\r
+  uint32_t  rx_crc_errors;     /* recved pkt with crc error  */\r
+  uint32_t  rx_frame_errors;   /* recv'd frame alignment error  */\r
+  uint32_t  rx_fifo_errors;    /* recv'r fifo overrun      */\r
+  uint32_t  rx_missed_errors;  /* receiver missed packet    */\r
+\r
+  /* detailed tx_errors */\r
+  uint32_t  tx_aborted_errors;\r
+  uint32_t  tx_carrier_errors;\r
+  uint32_t  tx_fifo_errors;\r
+  uint32_t  tx_heartbeat_errors;\r
+  uint32_t  tx_window_errors;\r
+};\r
+\r
+struct ei_device\r
+{\r
+  const int8_t      *name;\r
+  uint8_t           open;\r
+  uint8_t           Tx_act;\r
+  uint8_t           Rx_act;\r
+  uint8_t           txing;        /* Transmit Active */\r
+  uint8_t           irqlock;      /* EDMAC's interrupt disabled when '1'. */\r
+  uint8_t           dmaing;       /* EDMAC Active */\r
+  ethfifo           *rxcurrent;   /* current receive discripter */\r
+  ethfifo           *txcurrent;   /* current transmit discripter */\r
+  uint8_t           save_irq;     /* Original dev->irq value. */\r
+  struct enet_stats stat;\r
+  uint8_t           mac_addr[6];\r
+};\r
+\r
+#endif /* R_ETHER_H */\r
+\r