--- /dev/null
+// ----------------------------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ----------------------------------------------------------------------------\r
+// Copyright (c) 2006, Atmel Corporation\r
+// \r
+// All rights reserved.\r
+// \r
+// Redistribution and use in source and binary forms, with or without\r
+// modification, are permitted provided that the following conditions are met:\r
+// \r
+// - Redistributions of source code must retain the above copyright notice,\r
+// this list of conditions and the disclaimer below.\r
+// \r
+// - Redistributions in binary form must reproduce the above copyright notice,\r
+// this list of conditions and the disclaimer below in the documentation and/or\r
+// other materials provided with the distribution. \r
+// \r
+// Atmel's name may not be used to endorse or promote products derived from\r
+// this software without specific prior written permission. \r
+// \r
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+// ----------------------------------------------------------------------------\r
+// File Name : AT91SAM9XE128.h\r
+// Object : AT91SAM9XE128 definitions\r
+// Generated : AT91 SW Application Group 02/13/2008 (18:26:05)\r
+// \r
+// CVS Reference : /AT91SAM9XE128.pl/1.3/Wed Jan 30 13:58:28 2008//\r
+// CVS Reference : /SYS_SAM9260.pl/1.2/Wed Feb 13 13:29:23 2008//\r
+// CVS Reference : /HMATRIX1_SAM9260.pl/1.7/Mon Apr 23 10:39:45 2007//\r
+// CVS Reference : /CCR_SAM9260.pl/1.2/Mon Apr 16 10:47:39 2007//\r
+// CVS Reference : /PMC_SAM9262.pl/1.4/Mon Mar 7 18:03:13 2005//\r
+// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//\r
+// CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004//\r
+// CVS Reference : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//\r
+// CVS Reference : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//\r
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//\r
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//\r
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//\r
+// CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004//\r
+// CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 6 14:16:58 2004//\r
+// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//\r
+// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//\r
+// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//\r
+// CVS Reference : /EFC2_IGS036.pl/1.2/Fri Nov 10 10:47:53 2006//\r
+// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//\r
+// CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 3 13:20:23 2005//\r
+// CVS Reference : /TWI_6061B.pl/1.2/Fri Aug 4 08:53:02 2006//\r
+// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//\r
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//\r
+// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//\r
+// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//\r
+// CVS Reference : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006//\r
+// CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//\r
+// CVS Reference : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005//\r
+// CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 9 17:16:57 2005//\r
+// CVS Reference : /ISI_xxxxx.pl/1.3/Thu Mar 3 11:11:48 2005//\r
+// ----------------------------------------------------------------------------\r
+\r
+#ifndef AT91SAM9XE128_H\r
+#define AT91SAM9XE128_H\r
+\r
+#ifndef __ASSEMBLY__\r
+typedef volatile unsigned int AT91_REG;// Hardware register definition\r
+#define AT91_CAST(a) (a)\r
+#else\r
+#define AT91_CAST(a)\r
+#endif\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR System Peripherals\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SYS {\r
+ AT91_REG Reserved0[2560]; // \r
+ AT91_REG ECC_CR; // ECC reset register\r
+ AT91_REG ECC_MR; // ECC Page size register\r
+ AT91_REG ECC_SR; // ECC Status register\r
+ AT91_REG ECC_PR; // ECC Parity register\r
+ AT91_REG ECC_NPR; // ECC Parity N register\r
+ AT91_REG Reserved1[58]; // \r
+ AT91_REG ECC_VR; // ECC Version register\r
+ AT91_REG Reserved2[64]; // \r
+ AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register\r
+ AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register\r
+ AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register\r
+ AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register\r
+ AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register\r
+ AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register\r
+ AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register\r
+ AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register\r
+ AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register\r
+ AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register\r
+ AT91_REG Reserved3[118]; // \r
+ AT91_REG SMC_SETUP0; // Setup Register for CS 0\r
+ AT91_REG SMC_PULSE0; // Pulse Register for CS 0\r
+ AT91_REG SMC_CYCLE0; // Cycle Register for CS 0\r
+ AT91_REG SMC_CTRL0; // Control Register for CS 0\r
+ AT91_REG SMC_SETUP1; // Setup Register for CS 1\r
+ AT91_REG SMC_PULSE1; // Pulse Register for CS 1\r
+ AT91_REG SMC_CYCLE1; // Cycle Register for CS 1\r
+ AT91_REG SMC_CTRL1; // Control Register for CS 1\r
+ AT91_REG SMC_SETUP2; // Setup Register for CS 2\r
+ AT91_REG SMC_PULSE2; // Pulse Register for CS 2\r
+ AT91_REG SMC_CYCLE2; // Cycle Register for CS 2\r
+ AT91_REG SMC_CTRL2; // Control Register for CS 2\r
+ AT91_REG SMC_SETUP3; // Setup Register for CS 3\r
+ AT91_REG SMC_PULSE3; // Pulse Register for CS 3\r
+ AT91_REG SMC_CYCLE3; // Cycle Register for CS 3\r
+ AT91_REG SMC_CTRL3; // Control Register for CS 3\r
+ AT91_REG SMC_SETUP4; // Setup Register for CS 4\r
+ AT91_REG SMC_PULSE4; // Pulse Register for CS 4\r
+ AT91_REG SMC_CYCLE4; // Cycle Register for CS 4\r
+ AT91_REG SMC_CTRL4; // Control Register for CS 4\r
+ AT91_REG SMC_SETUP5; // Setup Register for CS 5\r
+ AT91_REG SMC_PULSE5; // Pulse Register for CS 5\r
+ AT91_REG SMC_CYCLE5; // Cycle Register for CS 5\r
+ AT91_REG SMC_CTRL5; // Control Register for CS 5\r
+ AT91_REG SMC_SETUP6; // Setup Register for CS 6\r
+ AT91_REG SMC_PULSE6; // Pulse Register for CS 6\r
+ AT91_REG SMC_CYCLE6; // Cycle Register for CS 6\r
+ AT91_REG SMC_CTRL6; // Control Register for CS 6\r
+ AT91_REG SMC_SETUP7; // Setup Register for CS 7\r
+ AT91_REG SMC_PULSE7; // Pulse Register for CS 7\r
+ AT91_REG SMC_CYCLE7; // Cycle Register for CS 7\r
+ AT91_REG SMC_CTRL7; // Control Register for CS 7\r
+ AT91_REG Reserved4[96]; // \r
+ AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k) \r
+ AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom) \r
+ AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs) \r
+ AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi)\r
+ AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge) \r
+ AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox) \r
+ AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k) \r
+ AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog) \r
+ AT91_REG Reserved5[8]; // \r
+ AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k) \r
+ AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom) \r
+ AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs) \r
+ AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi)\r
+ AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge) \r
+ AT91_REG Reserved6[11]; // \r
+ AT91_REG MATRIX_PRAS0; // PRAS0 (ram0) \r
+ AT91_REG MATRIX_PRBS0; // PRBS0 (ram0) \r
+ AT91_REG MATRIX_PRAS1; // PRAS1 (ram1) \r
+ AT91_REG MATRIX_PRBS1; // PRBS1 (ram1) \r
+ AT91_REG MATRIX_PRAS2; // PRAS2 (ram2) \r
+ AT91_REG MATRIX_PRBS2; // PRBS2 (ram2) \r
+ AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs\r
+ AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs\r
+ AT91_REG MATRIX_PRAS4; // PRAS4 : ebi\r
+ AT91_REG MATRIX_PRBS4; // PRBS4 : ebi\r
+ AT91_REG Reserved7[22]; // \r
+ AT91_REG MATRIX_MRCR; // Master Remp Control Register \r
+ AT91_REG Reserved8[6]; // \r
+ AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register\r
+ AT91_REG Reserved9[3]; // \r
+ AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register\r
+ AT91_REG Reserved10[51]; // \r
+ AT91_REG CCFG_MATRIXVERSION; // Version Register\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved11[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved12[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+ AT91_REG Reserved13[45]; // \r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved14[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved15[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+ AT91_REG Reserved16[54]; // \r
+ AT91_REG PIOA_PER; // PIO Enable Register\r
+ AT91_REG PIOA_PDR; // PIO Disable Register\r
+ AT91_REG PIOA_PSR; // PIO Status Register\r
+ AT91_REG Reserved17[1]; // \r
+ AT91_REG PIOA_OER; // Output Enable Register\r
+ AT91_REG PIOA_ODR; // Output Disable Registerr\r
+ AT91_REG PIOA_OSR; // Output Status Register\r
+ AT91_REG Reserved18[1]; // \r
+ AT91_REG PIOA_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOA_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved19[1]; // \r
+ AT91_REG PIOA_SODR; // Set Output Data Register\r
+ AT91_REG PIOA_CODR; // Clear Output Data Register\r
+ AT91_REG PIOA_ODSR; // Output Data Status Register\r
+ AT91_REG PIOA_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOA_IER; // Interrupt Enable Register\r
+ AT91_REG PIOA_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOA_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOA_ISR; // Interrupt Status Register\r
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved20[1]; // \r
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved21[1]; // \r
+ AT91_REG PIOA_ASR; // Select A Register\r
+ AT91_REG PIOA_BSR; // Select B Register\r
+ AT91_REG PIOA_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved22[9]; // \r
+ AT91_REG PIOA_OWER; // Output Write Enable Register\r
+ AT91_REG PIOA_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOA_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved23[213]; // \r
+ AT91_REG PIOB_PER; // PIO Enable Register\r
+ AT91_REG PIOB_PDR; // PIO Disable Register\r
+ AT91_REG PIOB_PSR; // PIO Status Register\r
+ AT91_REG Reserved24[1]; // \r
+ AT91_REG PIOB_OER; // Output Enable Register\r
+ AT91_REG PIOB_ODR; // Output Disable Registerr\r
+ AT91_REG PIOB_OSR; // Output Status Register\r
+ AT91_REG Reserved25[1]; // \r
+ AT91_REG PIOB_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOB_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved26[1]; // \r
+ AT91_REG PIOB_SODR; // Set Output Data Register\r
+ AT91_REG PIOB_CODR; // Clear Output Data Register\r
+ AT91_REG PIOB_ODSR; // Output Data Status Register\r
+ AT91_REG PIOB_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOB_IER; // Interrupt Enable Register\r
+ AT91_REG PIOB_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOB_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOB_ISR; // Interrupt Status Register\r
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved27[1]; // \r
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved28[1]; // \r
+ AT91_REG PIOB_ASR; // Select A Register\r
+ AT91_REG PIOB_BSR; // Select B Register\r
+ AT91_REG PIOB_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved29[9]; // \r
+ AT91_REG PIOB_OWER; // Output Write Enable Register\r
+ AT91_REG PIOB_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOB_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved30[85]; // \r
+ AT91_REG PIOC_PER; // PIO Enable Register\r
+ AT91_REG PIOC_PDR; // PIO Disable Register\r
+ AT91_REG PIOC_PSR; // PIO Status Register\r
+ AT91_REG Reserved31[1]; // \r
+ AT91_REG PIOC_OER; // Output Enable Register\r
+ AT91_REG PIOC_ODR; // Output Disable Registerr\r
+ AT91_REG PIOC_OSR; // Output Status Register\r
+ AT91_REG Reserved32[1]; // \r
+ AT91_REG PIOC_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOC_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOC_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved33[1]; // \r
+ AT91_REG PIOC_SODR; // Set Output Data Register\r
+ AT91_REG PIOC_CODR; // Clear Output Data Register\r
+ AT91_REG PIOC_ODSR; // Output Data Status Register\r
+ AT91_REG PIOC_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOC_IER; // Interrupt Enable Register\r
+ AT91_REG PIOC_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOC_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOC_ISR; // Interrupt Status Register\r
+ AT91_REG PIOC_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOC_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOC_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved34[1]; // \r
+ AT91_REG PIOC_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOC_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOC_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved35[1]; // \r
+ AT91_REG PIOC_ASR; // Select A Register\r
+ AT91_REG PIOC_BSR; // Select B Register\r
+ AT91_REG PIOC_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved36[9]; // \r
+ AT91_REG PIOC_OWER; // Output Write Enable Register\r
+ AT91_REG PIOC_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOC_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved37[85]; // \r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved38[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved39[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG PMC_PLLAR; // PLL A Register\r
+ AT91_REG PMC_PLLBR; // PLL B Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved40[3]; // \r
+ AT91_REG PMC_PCKR[8]; // Programmable Clock Register\r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved41[36]; // \r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+ AT91_REG Reserved42[1]; // \r
+ AT91_REG SHDWC_SHCR; // Shut Down Control Register\r
+ AT91_REG SHDWC_SHMR; // Shut Down Mode Register\r
+ AT91_REG SHDWC_SHSR; // Shut Down Status Register\r
+ AT91_REG Reserved43[1]; // \r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+ AT91_REG Reserved44[1]; // \r
+ AT91_REG SYS_GPBR[4]; // General Purpose Register\r
+} AT91S_SYS, *AT91PS_SYS;\r
+#else\r
+#define SYS_GPBR (AT91_CAST(AT91_REG *) 0x00003D50) // (SYS_GPBR) General Purpose Register\r
+\r
+#endif\r
+// -------- GPBR : (SYS Offset: 0x3d50) GPBR General Purpose Register -------- \r
+#define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR External Bus Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_EBI {\r
+ AT91_REG EBI_DUMMY; // Dummy register - Do not use\r
+} AT91S_EBI, *AT91PS_EBI;\r
+#else\r
+#define EBI_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI_DUMMY) Dummy register - Do not use\r
+\r
+#endif\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Error Correction Code controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_ECC {\r
+ AT91_REG ECC_CR; // ECC reset register\r
+ AT91_REG ECC_MR; // ECC Page size register\r
+ AT91_REG ECC_SR; // ECC Status register\r
+ AT91_REG ECC_PR; // ECC Parity register\r
+ AT91_REG ECC_NPR; // ECC Parity N register\r
+ AT91_REG Reserved0[58]; // \r
+ AT91_REG ECC_VR; // ECC Version register\r
+} AT91S_ECC, *AT91PS_ECC;\r
+#else\r
+#define ECC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ECC_CR) ECC reset register\r
+#define ECC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ECC_MR) ECC Page size register\r
+#define ECC_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ECC_SR) ECC Status register\r
+#define ECC_PR (AT91_CAST(AT91_REG *) 0x0000000C) // (ECC_PR) ECC Parity register\r
+#define ECC_NPR (AT91_CAST(AT91_REG *) 0x00000010) // (ECC_NPR) ECC Parity N register\r
+#define ECC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (ECC_VR) ECC Version register\r
+\r
+#endif\r
+// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register -------- \r
+#define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity\r
+// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register -------- \r
+#define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size\r
+// -------- ECC_SR : (ECC Offset: 0x8) ECC status register -------- \r
+#define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error\r
+#define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error\r
+#define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR\r
+// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register -------- \r
+#define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error\r
+#define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit\r
+// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register -------- \r
+#define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N \r
+// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register -------- \r
+#define AT91C_ECC_VR (0xF << 0) // (ECC) ECC version register\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR SDRAM Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SDRAMC {\r
+ AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register\r
+ AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register\r
+ AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register\r
+ AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register\r
+ AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register\r
+ AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register\r
+ AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register\r
+ AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register\r
+ AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register\r
+ AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register\r
+} AT91S_SDRAMC, *AT91PS_SDRAMC;\r
+#else\r
+#define SDRAMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register\r
+#define SDRAMC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register\r
+#define SDRAMC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register\r
+#define SDRAMC_HSR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register\r
+#define SDRAMC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register\r
+#define SDRAMC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register\r
+#define SDRAMC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register\r
+#define SDRAMC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register\r
+#define SDRAMC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register\r
+#define SDRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register\r
+\r
+#endif\r
+// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register -------- \r
+#define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode\r
+#define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode\r
+#define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access\r
+#define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access\r
+#define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access\r
+#define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh\r
+#define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register\r
+#define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode\r
+// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register -------- \r
+#define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter\r
+// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register -------- \r
+#define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits\r
+#define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits\r
+#define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits\r
+#define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits\r
+#define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits\r
+#define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits\r
+#define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits\r
+#define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits\r
+#define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits\r
+#define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks\r
+#define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks\r
+#define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks\r
+#define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency\r
+#define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles\r
+#define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles\r
+#define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width\r
+#define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus\r
+#define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus\r
+#define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles\r
+#define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15\r
+#define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles\r
+#define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15\r
+#define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles\r
+#define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15\r
+#define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles\r
+#define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15\r
+#define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles\r
+#define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15\r
+#define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles\r
+#define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15\r
+// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register -------- \r
+#define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit\r
+#define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle\r
+#define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle\r
+// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register -------- \r
+#define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations\r
+#define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features\r
+#define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH\r
+#define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN\r
+#define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN\r
+#define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)\r
+#define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)\r
+#define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)\r
+#define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled\r
+#define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately\r
+#define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer\r
+#define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer\r
+// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- \r
+#define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status\r
+// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- \r
+// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- \r
+// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- \r
+// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register -------- \r
+#define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type\r
+#define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode\r
+#define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Static Memory Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SMC {\r
+ AT91_REG SMC_SETUP0; // Setup Register for CS 0\r
+ AT91_REG SMC_PULSE0; // Pulse Register for CS 0\r
+ AT91_REG SMC_CYCLE0; // Cycle Register for CS 0\r
+ AT91_REG SMC_CTRL0; // Control Register for CS 0\r
+ AT91_REG SMC_SETUP1; // Setup Register for CS 1\r
+ AT91_REG SMC_PULSE1; // Pulse Register for CS 1\r
+ AT91_REG SMC_CYCLE1; // Cycle Register for CS 1\r
+ AT91_REG SMC_CTRL1; // Control Register for CS 1\r
+ AT91_REG SMC_SETUP2; // Setup Register for CS 2\r
+ AT91_REG SMC_PULSE2; // Pulse Register for CS 2\r
+ AT91_REG SMC_CYCLE2; // Cycle Register for CS 2\r
+ AT91_REG SMC_CTRL2; // Control Register for CS 2\r
+ AT91_REG SMC_SETUP3; // Setup Register for CS 3\r
+ AT91_REG SMC_PULSE3; // Pulse Register for CS 3\r
+ AT91_REG SMC_CYCLE3; // Cycle Register for CS 3\r
+ AT91_REG SMC_CTRL3; // Control Register for CS 3\r
+ AT91_REG SMC_SETUP4; // Setup Register for CS 4\r
+ AT91_REG SMC_PULSE4; // Pulse Register for CS 4\r
+ AT91_REG SMC_CYCLE4; // Cycle Register for CS 4\r
+ AT91_REG SMC_CTRL4; // Control Register for CS 4\r
+ AT91_REG SMC_SETUP5; // Setup Register for CS 5\r
+ AT91_REG SMC_PULSE5; // Pulse Register for CS 5\r
+ AT91_REG SMC_CYCLE5; // Cycle Register for CS 5\r
+ AT91_REG SMC_CTRL5; // Control Register for CS 5\r
+ AT91_REG SMC_SETUP6; // Setup Register for CS 6\r
+ AT91_REG SMC_PULSE6; // Pulse Register for CS 6\r
+ AT91_REG SMC_CYCLE6; // Cycle Register for CS 6\r
+ AT91_REG SMC_CTRL6; // Control Register for CS 6\r
+ AT91_REG SMC_SETUP7; // Setup Register for CS 7\r
+ AT91_REG SMC_PULSE7; // Pulse Register for CS 7\r
+ AT91_REG SMC_CYCLE7; // Cycle Register for CS 7\r
+ AT91_REG SMC_CTRL7; // Control Register for CS 7\r
+} AT91S_SMC, *AT91PS_SMC;\r
+#else\r
+#define SETUP0 (AT91_CAST(AT91_REG *) 0x00000000) // (SETUP0) Setup Register for CS 0\r
+#define PULSE0 (AT91_CAST(AT91_REG *) 0x00000004) // (PULSE0) Pulse Register for CS 0\r
+#define CYCLE0 (AT91_CAST(AT91_REG *) 0x00000008) // (CYCLE0) Cycle Register for CS 0\r
+#define CTRL0 (AT91_CAST(AT91_REG *) 0x0000000C) // (CTRL0) Control Register for CS 0\r
+#define SETUP1 (AT91_CAST(AT91_REG *) 0x00000010) // (SETUP1) Setup Register for CS 1\r
+#define PULSE1 (AT91_CAST(AT91_REG *) 0x00000014) // (PULSE1) Pulse Register for CS 1\r
+#define CYCLE1 (AT91_CAST(AT91_REG *) 0x00000018) // (CYCLE1) Cycle Register for CS 1\r
+#define CTRL1 (AT91_CAST(AT91_REG *) 0x0000001C) // (CTRL1) Control Register for CS 1\r
+#define SETUP2 (AT91_CAST(AT91_REG *) 0x00000020) // (SETUP2) Setup Register for CS 2\r
+#define PULSE2 (AT91_CAST(AT91_REG *) 0x00000024) // (PULSE2) Pulse Register for CS 2\r
+#define CYCLE2 (AT91_CAST(AT91_REG *) 0x00000028) // (CYCLE2) Cycle Register for CS 2\r
+#define CTRL2 (AT91_CAST(AT91_REG *) 0x0000002C) // (CTRL2) Control Register for CS 2\r
+#define SETUP3 (AT91_CAST(AT91_REG *) 0x00000030) // (SETUP3) Setup Register for CS 3\r
+#define PULSE3 (AT91_CAST(AT91_REG *) 0x00000034) // (PULSE3) Pulse Register for CS 3\r
+#define CYCLE3 (AT91_CAST(AT91_REG *) 0x00000038) // (CYCLE3) Cycle Register for CS 3\r
+#define CTRL3 (AT91_CAST(AT91_REG *) 0x0000003C) // (CTRL3) Control Register for CS 3\r
+#define SETUP4 (AT91_CAST(AT91_REG *) 0x00000040) // (SETUP4) Setup Register for CS 4\r
+#define PULSE4 (AT91_CAST(AT91_REG *) 0x00000044) // (PULSE4) Pulse Register for CS 4\r
+#define CYCLE4 (AT91_CAST(AT91_REG *) 0x00000048) // (CYCLE4) Cycle Register for CS 4\r
+#define CTRL4 (AT91_CAST(AT91_REG *) 0x0000004C) // (CTRL4) Control Register for CS 4\r
+#define SETUP5 (AT91_CAST(AT91_REG *) 0x00000050) // (SETUP5) Setup Register for CS 5\r
+#define PULSE5 (AT91_CAST(AT91_REG *) 0x00000054) // (PULSE5) Pulse Register for CS 5\r
+#define CYCLE5 (AT91_CAST(AT91_REG *) 0x00000058) // (CYCLE5) Cycle Register for CS 5\r
+#define CTRL5 (AT91_CAST(AT91_REG *) 0x0000005C) // (CTRL5) Control Register for CS 5\r
+#define SETUP6 (AT91_CAST(AT91_REG *) 0x00000060) // (SETUP6) Setup Register for CS 6\r
+#define PULSE6 (AT91_CAST(AT91_REG *) 0x00000064) // (PULSE6) Pulse Register for CS 6\r
+#define CYCLE6 (AT91_CAST(AT91_REG *) 0x00000068) // (CYCLE6) Cycle Register for CS 6\r
+#define CTRL6 (AT91_CAST(AT91_REG *) 0x0000006C) // (CTRL6) Control Register for CS 6\r
+#define SETUP7 (AT91_CAST(AT91_REG *) 0x00000070) // (SETUP7) Setup Register for CS 7\r
+#define PULSE7 (AT91_CAST(AT91_REG *) 0x00000074) // (PULSE7) Pulse Register for CS 7\r
+#define CYCLE7 (AT91_CAST(AT91_REG *) 0x00000078) // (CYCLE7) Cycle Register for CS 7\r
+#define CTRL7 (AT91_CAST(AT91_REG *) 0x0000007C) // (CTRL7) Control Register for CS 7\r
+\r
+#endif\r
+// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x -------- \r
+#define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length\r
+#define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access\r
+#define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length\r
+#define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access\r
+// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x -------- \r
+#define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length\r
+#define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access\r
+#define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length\r
+#define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access\r
+// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x -------- \r
+#define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length\r
+#define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length\r
+// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x -------- \r
+#define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode\r
+#define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode\r
+#define AT91C_SMC_NWAITM (0x3 << 4) // (SMC) NWAIT Mode\r
+#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 4) // (SMC) External NWAIT disabled.\r
+#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 4) // (SMC) External NWAIT enabled in frozen mode.\r
+#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 4) // (SMC) External NWAIT enabled in ready mode.\r
+#define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type\r
+#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.\r
+#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.\r
+#define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width\r
+#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits.\r
+#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits.\r
+#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.\r
+#define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time.\r
+#define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled.\r
+#define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled.\r
+#define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size\r
+#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes.\r
+#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes.\r
+#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes.\r
+#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.\r
+// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR AHB Matrix Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_MATRIX {\r
+ AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k) \r
+ AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom) \r
+ AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs) \r
+ AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi)\r
+ AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge) \r
+ AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox) \r
+ AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k) \r
+ AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog) \r
+ AT91_REG Reserved0[8]; // \r
+ AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k) \r
+ AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom) \r
+ AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs) \r
+ AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi)\r
+ AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge) \r
+ AT91_REG Reserved1[11]; // \r
+ AT91_REG MATRIX_PRAS0; // PRAS0 (ram0) \r
+ AT91_REG MATRIX_PRBS0; // PRBS0 (ram0) \r
+ AT91_REG MATRIX_PRAS1; // PRAS1 (ram1) \r
+ AT91_REG MATRIX_PRBS1; // PRBS1 (ram1) \r
+ AT91_REG MATRIX_PRAS2; // PRAS2 (ram2) \r
+ AT91_REG MATRIX_PRBS2; // PRBS2 (ram2) \r
+ AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs\r
+ AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs\r
+ AT91_REG MATRIX_PRAS4; // PRAS4 : ebi\r
+ AT91_REG MATRIX_PRBS4; // PRBS4 : ebi\r
+ AT91_REG Reserved2[22]; // \r
+ AT91_REG MATRIX_MRCR; // Master Remp Control Register \r
+ AT91_REG Reserved3[6]; // \r
+ AT91_REG MATRIX_EBI; // Slave 3 (ebi) Special Function Register\r
+ AT91_REG Reserved4[3]; // \r
+ AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register\r
+ AT91_REG Reserved5[51]; // \r
+ AT91_REG MATRIX_VERSION; // Version Register\r
+} AT91S_MATRIX, *AT91PS_MATRIX;\r
+#else\r
+#define MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG0) Master Configuration Register 0 (ram96k) \r
+#define MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_MCFG1) Master Configuration Register 1 (rom) \r
+#define MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_MCFG2) Master Configuration Register 2 (hperiphs) \r
+#define MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_MCFG3) Master Configuration Register 3 (ebi)\r
+#define MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_MCFG4) Master Configuration Register 4 (bridge) \r
+#define MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_MCFG5) Master Configuration Register 5 (mailbox) \r
+#define MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x00000018) // (MATRIX_MCFG6) Master Configuration Register 6 (ram16k) \r
+#define MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x0000001C) // (MATRIX_MCFG7) Master Configuration Register 7 (teak_prog) \r
+#define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG0) Slave Configuration Register 0 (ram96k) \r
+#define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_SCFG1) Slave Configuration Register 1 (rom) \r
+#define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x00000048) // (MATRIX_SCFG2) Slave Configuration Register 2 (hperiphs) \r
+#define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x0000004C) // (MATRIX_SCFG3) Slave Configuration Register 3 (ebi)\r
+#define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000050) // (MATRIX_SCFG4) Slave Configuration Register 4 (bridge) \r
+#define MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0x00000080) // (MATRIX_PRAS0) PRAS0 (ram0) \r
+#define MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0x00000084) // (MATRIX_PRBS0) PRBS0 (ram0) \r
+#define MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0x00000088) // (MATRIX_PRAS1) PRAS1 (ram1) \r
+#define MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0x0000008C) // (MATRIX_PRBS1) PRBS1 (ram1) \r
+#define MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0x00000090) // (MATRIX_PRAS2) PRAS2 (ram2) \r
+#define MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0x00000094) // (MATRIX_PRBS2) PRBS2 (ram2) \r
+#define MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0x00000098) // (MATRIX_PRAS3) PRAS3 : usb_dev_hs\r
+#define MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0x0000009C) // (MATRIX_PRBS3) PRBS3 : usb_dev_hs\r
+#define MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0x000000A0) // (MATRIX_PRAS4) PRAS4 : ebi\r
+#define MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0x000000A4) // (MATRIX_PRBS4) PRBS4 : ebi\r
+#define MATRIX_MRCR (AT91_CAST(AT91_REG *) 0x00000100) // (MATRIX_MRCR) Master Remp Control Register \r
+#define MATRIX_EBI (AT91_CAST(AT91_REG *) 0x0000011C) // (MATRIX_EBI) Slave 3 (ebi) Special Function Register\r
+#define MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0x0000012C) // (MATRIX_TEAKCFG) Slave 7 (teak_prog) Special Function Register\r
+#define MATRIX_VERSION (AT91_CAST(AT91_REG *) 0x000001FC) // (MATRIX_VERSION) Version Register\r
+\r
+#endif\r
+// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- \r
+#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst\r
+#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type\r
+#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.\r
+#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.\r
+#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master\r
+// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master\r
+// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master\r
+// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR3_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master\r
+// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master\r
+// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register -------- \r
+#define AT91C_MATRIX_M0PR (0x3 << 0) // (MATRIX) ARM926EJ-S Instruction priority\r
+#define AT91C_MATRIX_M1PR (0x3 << 4) // (MATRIX) ARM926EJ-S Data priority\r
+#define AT91C_MATRIX_M2PR (0x3 << 8) // (MATRIX) PDC priority\r
+#define AT91C_MATRIX_M3PR (0x3 << 12) // (MATRIX) LCDC priority\r
+#define AT91C_MATRIX_M4PR (0x3 << 16) // (MATRIX) 2DGC priority\r
+#define AT91C_MATRIX_M5PR (0x3 << 20) // (MATRIX) ISI priority\r
+#define AT91C_MATRIX_M6PR (0x3 << 24) // (MATRIX) DMA priority\r
+#define AT91C_MATRIX_M7PR (0x3 << 28) // (MATRIX) EMAC priority\r
+// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register -------- \r
+#define AT91C_MATRIX_M8PR (0x3 << 0) // (MATRIX) USB priority\r
+// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register -------- \r
+// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register -------- \r
+// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register -------- \r
+// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register -------- \r
+// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register -------- \r
+// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register -------- \r
+// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register -------- \r
+// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register -------- \r
+// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register -------- \r
+#define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master\r
+#define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command for ARM926EJ-S Data Master\r
+// -------- MATRIX_EBI : (MATRIX Offset: 0x11c) EBI (Slave 3) Special Function Register -------- \r
+#define AT91C_MATRIX_CS1A (0x1 << 1) // (MATRIX) Chip Select 1 Assignment\r
+#define AT91C_MATRIX_CS1A_SMC (0x0 << 1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller.\r
+#define AT91C_MATRIX_CS1A_SDRAMC (0x1 << 1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller.\r
+#define AT91C_MATRIX_CS3A (0x1 << 3) // (MATRIX) Chip Select 3 Assignment\r
+#define AT91C_MATRIX_CS3A_SMC (0x0 << 3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.\r
+#define AT91C_MATRIX_CS3A_SM (0x1 << 3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.\r
+#define AT91C_MATRIX_CS4A (0x1 << 4) // (MATRIX) Chip Select 4 Assignment\r
+#define AT91C_MATRIX_CS4A_SMC (0x0 << 4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.\r
+#define AT91C_MATRIX_CS4A_CF (0x1 << 4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.\r
+#define AT91C_MATRIX_CS5A (0x1 << 5) // (MATRIX) Chip Select 5 Assignment\r
+#define AT91C_MATRIX_CS5A_SMC (0x0 << 5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC\r
+#define AT91C_MATRIX_CS5A_CF (0x1 << 5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.\r
+#define AT91C_MATRIX_DBPUC (0x1 << 8) // (MATRIX) Data Bus Pull-up Configuration\r
+// -------- MATRIX_TEAKCFG : (MATRIX Offset: 0x12c) Slave 7 Special Function Register -------- \r
+#define AT91C_TEAK_PROGRAM_ACCESS (0x1 << 0) // (MATRIX) TEAK program memory access from AHB\r
+#define AT91C_TEAK_PROGRAM_ACCESS_DISABLED (0x0) // (MATRIX) TEAK program access disabled\r
+#define AT91C_TEAK_PROGRAM_ACCESS_ENABLED (0x1) // (MATRIX) TEAK program access enabled\r
+#define AT91C_TEAK_BOOT (0x1 << 1) // (MATRIX) TEAK program start from boot routine\r
+#define AT91C_TEAK_BOOT_DISABLED (0x0 << 1) // (MATRIX) TEAK program starts from boot routine disabled\r
+#define AT91C_TEAK_BOOT_ENABLED (0x1 << 1) // (MATRIX) TEAK program starts from boot routine enabled\r
+#define AT91C_TEAK_NRESET (0x1 << 2) // (MATRIX) active low TEAK reset\r
+#define AT91C_TEAK_NRESET_ENABLED (0x0 << 2) // (MATRIX) active low TEAK reset enabled\r
+#define AT91C_TEAK_NRESET_DISABLED (0x1 << 2) // (MATRIX) active low TEAK reset disabled\r
+#define AT91C_TEAK_LVECTORP (0x3FFFF << 14) // (MATRIX) boot routine start address\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Chip Configuration Registers\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_CCFG {\r
+ AT91_REG Reserved0[3]; // \r
+ AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register\r
+ AT91_REG Reserved1[55]; // \r
+ AT91_REG CCFG_MATRIXVERSION; // Version Register\r
+} AT91S_CCFG, *AT91PS_CCFG;\r
+#else\r
+#define CCFG_EBICSA (AT91_CAST(AT91_REG *) 0x0000000C) // (CCFG_EBICSA) EBI Chip Select Assignement Register\r
+#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0x000000EC) // (CCFG_MATRIXVERSION) Version Register\r
+\r
+#endif\r
+// -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register -------- \r
+#define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment\r
+#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.\r
+#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller.\r
+#define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment\r
+#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.\r
+#define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.\r
+#define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment\r
+#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.\r
+#define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.\r
+#define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment\r
+#define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC\r
+#define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.\r
+#define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration\r
+#define AT91C_EBI_SUPPLY (0x1 << 16) // (CCFG) EBI supply selection\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PDC {\r
+ AT91_REG PDC_RPR; // Receive Pointer Register\r
+ AT91_REG PDC_RCR; // Receive Counter Register\r
+ AT91_REG PDC_TPR; // Transmit Pointer Register\r
+ AT91_REG PDC_TCR; // Transmit Counter Register\r
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG PDC_RNCR; // Receive Next Counter Register\r
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register\r
+} AT91S_PDC, *AT91PS_PDC;\r
+#else\r
+#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register\r
+#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register\r
+#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register\r
+#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register\r
+#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register\r
+#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register\r
+#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register\r
+#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register\r
+#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register\r
+#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register\r
+\r
+#endif\r
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable\r
+#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable\r
+#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable\r
+#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable\r
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Debug Unit\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_DBGU {\r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved0[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved1[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+} AT91S_DBGU, *AT91PS_DBGU;\r
+#else\r
+#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register\r
+#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register\r
+#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register\r
+#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register\r
+#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register\r
+#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register\r
+#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register\r
+#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register\r
+#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register\r
+#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register\r
+#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register\r
+#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register\r
+\r
+#endif\r
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver\r
+#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter\r
+#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable\r
+#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable\r
+#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable\r
+#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable\r
+#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits\r
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type\r
+#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity\r
+#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity\r
+#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)\r
+#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)\r
+#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity\r
+#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode\r
+#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode\r
+#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt\r
+#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt\r
+#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt\r
+#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt\r
+#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt\r
+#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt\r
+#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt\r
+#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt\r
+#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt\r
+#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt\r
+#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt\r
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_AIC {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+} AT91S_AIC, *AT91PS_AIC;\r
+#else\r
+#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register\r
+#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register\r
+#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register\r
+#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register\r
+#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register\r
+#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register\r
+#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register\r
+#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register\r
+#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register\r
+#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register\r
+#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register\r
+#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register\r
+#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register\r
+#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register\r
+#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)\r
+#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register\r
+#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register\r
+#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register\r
+\r
+#endif\r
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level\r
+#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level\r
+#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level\r
+#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type\r
+#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive\r
+#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered\r
+#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered\r
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status\r
+#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status\r
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode\r
+#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PIO {\r
+ AT91_REG PIO_PER; // PIO Enable Register\r
+ AT91_REG PIO_PDR; // PIO Disable Register\r
+ AT91_REG PIO_PSR; // PIO Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PIO_OER; // Output Enable Register\r
+ AT91_REG PIO_ODR; // Output Disable Registerr\r
+ AT91_REG PIO_OSR; // Output Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PIO_IFER; // Input Filter Enable Register\r
+ AT91_REG PIO_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIO_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PIO_SODR; // Set Output Data Register\r
+ AT91_REG PIO_CODR; // Clear Output Data Register\r
+ AT91_REG PIO_ODSR; // Output Data Status Register\r
+ AT91_REG PIO_PDSR; // Pin Data Status Register\r
+ AT91_REG PIO_IER; // Interrupt Enable Register\r
+ AT91_REG PIO_IDR; // Interrupt Disable Register\r
+ AT91_REG PIO_IMR; // Interrupt Mask Register\r
+ AT91_REG PIO_ISR; // Interrupt Status Register\r
+ AT91_REG PIO_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIO_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved3[1]; // \r
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIO_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIO_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved4[1]; // \r
+ AT91_REG PIO_ASR; // Select A Register\r
+ AT91_REG PIO_BSR; // Select B Register\r
+ AT91_REG PIO_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved5[9]; // \r
+ AT91_REG PIO_OWER; // Output Write Enable Register\r
+ AT91_REG PIO_OWDR; // Output Write Disable Register\r
+ AT91_REG PIO_OWSR; // Output Write Status Register\r
+} AT91S_PIO, *AT91PS_PIO;\r
+#else\r
+#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register\r
+#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register\r
+#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register\r
+#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register\r
+#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr\r
+#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register\r
+#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register\r
+#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register\r
+#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register\r
+#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register\r
+#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register\r
+#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register\r
+#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register\r
+#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register\r
+#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register\r
+#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register\r
+#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register\r
+#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register\r
+#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register\r
+#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register\r
+#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register\r
+#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register\r
+#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register\r
+#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register\r
+#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register\r
+#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register\r
+#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register\r
+#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register\r
+#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register\r
+\r
+#endif\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Embedded Flash Controller 2.0\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_EFC {\r
+ AT91_REG EFC_FMR; // EFC Flash Mode Register\r
+ AT91_REG EFC_FCR; // EFC Flash Command Register\r
+ AT91_REG EFC_FSR; // EFC Flash Status Register\r
+ AT91_REG EFC_FRR; // EFC Flash Result Register\r
+ AT91_REG EFC_FVR; // EFC Flash Version Register\r
+} AT91S_EFC, *AT91PS_EFC;\r
+#else\r
+#define EFC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (EFC_FMR) EFC Flash Mode Register\r
+#define EFC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (EFC_FCR) EFC Flash Command Register\r
+#define EFC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (EFC_FSR) EFC Flash Status Register\r
+#define EFC_FRR (AT91_CAST(AT91_REG *) 0x0000000C) // (EFC_FRR) EFC Flash Result Register\r
+#define EFC_FVR (AT91_CAST(AT91_REG *) 0x00000010) // (EFC_FVR) EFC Flash Version Register\r
+\r
+#endif\r
+// -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register -------- \r
+#define AT91C_EFC_FRDY (0x1 << 0) // (EFC) Ready Interrupt Enable\r
+#define AT91C_EFC_FWS (0xF << 8) // (EFC) Flash Wait State.\r
+#define AT91C_EFC_FWS_0WS (0x0 << 8) // (EFC) 0 Wait State\r
+#define AT91C_EFC_FWS_1WS (0x1 << 8) // (EFC) 1 Wait State\r
+#define AT91C_EFC_FWS_2WS (0x2 << 8) // (EFC) 2 Wait States\r
+#define AT91C_EFC_FWS_3WS (0x3 << 8) // (EFC) 3 Wait States\r
+// -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register -------- \r
+#define AT91C_EFC_FCMD (0xFF << 0) // (EFC) Flash Command\r
+#define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor\r
+#define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page\r
+#define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock\r
+#define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page\r
+#define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock\r
+#define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All\r
+#define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase Plane\r
+#define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase Pages\r
+#define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit\r
+#define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit\r
+#define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit\r
+#define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit\r
+#define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit\r
+#define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit\r
+#define AT91C_EFC_FARG (0xFFFF << 8) // (EFC) Flash Command Argument\r
+#define AT91C_EFC_FKEY (0xFF << 24) // (EFC) Flash Writing Protection Key\r
+// -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register -------- \r
+#define AT91C_EFC_FRDY_S (0x1 << 0) // (EFC) Flash Ready Status\r
+#define AT91C_EFC_FCMDE (0x1 << 1) // (EFC) Flash Command Error Status\r
+#define AT91C_EFC_LOCKE (0x1 << 2) // (EFC) Flash Lock Error Status\r
+// -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register -------- \r
+#define AT91C_EFC_FVALUE (0x0 << 0) // (EFC) Flash Result Value\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_CKGR {\r
+ AT91_REG CKGR_MOR; // Main Oscillator Register\r
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register\r
+ AT91_REG CKGR_PLLAR; // PLL A Register\r
+ AT91_REG CKGR_PLLBR; // PLL B Register\r
+} AT91S_CKGR, *AT91PS_CKGR;\r
+#else\r
+#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register\r
+#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register\r
+#define CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x00000008) // (CKGR_PLLAR) PLL A Register\r
+#define CKGR_PLLBR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLBR) PLL B Register\r
+\r
+#endif\r
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable\r
+#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass\r
+#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time\r
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency\r
+#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready\r
+// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- \r
+#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected\r
+#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0\r
+#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed\r
+#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter\r
+#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range\r
+#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet\r
+#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet\r
+#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet\r
+#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet\r
+#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier\r
+#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR) \r
+// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- \r
+#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected\r
+#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0\r
+#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed\r
+#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter\r
+#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range\r
+#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet\r
+#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet\r
+#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet\r
+#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet\r
+#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier\r
+#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks\r
+#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output\r
+#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2\r
+#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Power Management Controler\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PMC {\r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG PMC_PLLAR; // PLL A Register\r
+ AT91_REG PMC_PLLBR; // PLL B Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved2[3]; // \r
+ AT91_REG PMC_PCKR[8]; // Programmable Clock Register\r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+} AT91S_PMC, *AT91PS_PMC;\r
+#else\r
+#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register\r
+#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register\r
+#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register\r
+#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register\r
+#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register\r
+#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register\r
+#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register\r
+#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register\r
+#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register\r
+#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register\r
+#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register\r
+#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register\r
+\r
+#endif\r
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock\r
+#define AT91C_PMC_OTG (0x1 << 5) // (PMC) USB OTG Clock\r
+#define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock\r
+#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock\r
+#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output\r
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- \r
+// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection\r
+#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected\r
+#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected\r
+#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected\r
+#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected\r
+#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler\r
+#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock\r
+#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2\r
+#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4\r
+#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8\r
+#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16\r
+#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32\r
+#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64\r
+#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division\r
+#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same\r
+#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock\r
+#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is four times faster than the master clock\r
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_RSTC {\r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+} AT91S_RSTC, *AT91PS_RSTC;\r
+#else\r
+#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register\r
+#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register\r
+#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register\r
+\r
+#endif\r
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset\r
+#define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset\r
+#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset\r
+#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset\r
+#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password\r
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status\r
+#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type\r
+#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.\r
+#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.\r
+#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.\r
+#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level\r
+#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable\r
+#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Shut Down Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SHDWC {\r
+ AT91_REG SHDWC_SHCR; // Shut Down Control Register\r
+ AT91_REG SHDWC_SHMR; // Shut Down Mode Register\r
+ AT91_REG SHDWC_SHSR; // Shut Down Status Register\r
+} AT91S_SHDWC, *AT91PS_SHDWC;\r
+#else\r
+#define SHDWC_SHCR (AT91_CAST(AT91_REG *) 0x00000000) // (SHDWC_SHCR) Shut Down Control Register\r
+#define SHDWC_SHMR (AT91_CAST(AT91_REG *) 0x00000004) // (SHDWC_SHMR) Shut Down Mode Register\r
+#define SHDWC_SHSR (AT91_CAST(AT91_REG *) 0x00000008) // (SHDWC_SHSR) Shut Down Status Register\r
+\r
+#endif\r
+// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- \r
+#define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset\r
+#define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password\r
+// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- \r
+#define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection\r
+#define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input.\r
+#define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level.\r
+#define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level.\r
+#define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change.\r
+#define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0\r
+#define AT91C_SHDWC_WKMODE1 (0x3 << 8) // (SHDWC) Wake Up 1 Mode Selection\r
+#define AT91C_SHDWC_WKMODE1_NONE (0x0 << 8) // (SHDWC) None. No detection is performed on the wake up input.\r
+#define AT91C_SHDWC_WKMODE1_HIGH (0x1 << 8) // (SHDWC) High Level.\r
+#define AT91C_SHDWC_WKMODE1_LOW (0x2 << 8) // (SHDWC) Low Level.\r
+#define AT91C_SHDWC_WKMODE1_ANYLEVEL (0x3 << 8) // (SHDWC) Any level change.\r
+#define AT91C_SHDWC_CPTWK1 (0xF << 12) // (SHDWC) Counter On Wake Up 1\r
+#define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable\r
+#define AT91C_SHDWC_RTCWKEN (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable\r
+// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- \r
+#define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status\r
+#define AT91C_SHDWC_WAKEUP1 (0x1 << 1) // (SHDWC) Wake Up 1 Status\r
+#define AT91C_SHDWC_FWKUP (0x1 << 2) // (SHDWC) Force Wake Up Status\r
+#define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up\r
+#define AT91C_SHDWC_RTCWK (0x1 << 17) // (SHDWC) Real Time Clock wake Up\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_RTTC {\r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+} AT91S_RTTC, *AT91PS_RTTC;\r
+#else\r
+#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register\r
+#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register\r
+#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register\r
+#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register\r
+\r
+#endif\r
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
+#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
+#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
+#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart\r
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value\r
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value\r
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status\r
+#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PITC {\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+} AT91S_PITC, *AT91PS_PITC;\r
+#else\r
+#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register\r
+#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register\r
+#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register\r
+#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register\r
+\r
+#endif\r
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value\r
+#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
+#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable\r
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status\r
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value\r
+#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter\r
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_WDTC {\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+} AT91S_WDTC, *AT91PS_WDTC;\r
+#else\r
+#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register\r
+#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register\r
+#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register\r
+\r
+#endif\r
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart\r
+#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password\r
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
+#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable\r
+#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable\r
+#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value\r
+#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt\r
+#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt\r
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow\r
+#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_TC {\r
+ AT91_REG TC_CCR; // Channel Control Register\r
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TC_CV; // Counter Value\r
+ AT91_REG TC_RA; // Register A\r
+ AT91_REG TC_RB; // Register B\r
+ AT91_REG TC_RC; // Register C\r
+ AT91_REG TC_SR; // Status Register\r
+ AT91_REG TC_IER; // Interrupt Enable Register\r
+ AT91_REG TC_IDR; // Interrupt Disable Register\r
+ AT91_REG TC_IMR; // Interrupt Mask Register\r
+} AT91S_TC, *AT91PS_TC;\r
+#else\r
+#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register\r
+#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value\r
+#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A\r
+#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B\r
+#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C\r
+#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register\r
+#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register\r
+#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register\r
+#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register\r
+\r
+#endif\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection\r
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
+#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0\r
+#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1\r
+#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2\r
+#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert\r
+#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection\r
+#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal\r
+#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock\r
+#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading\r
+#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading\r
+#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection\r
+#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection\r
+#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection\r
+#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
+#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection\r
+#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE (0x1 << 15) // (TC) \r
+#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none\r
+#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set\r
+#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear\r
+#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection\r
+#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None\r
+#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none\r
+#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set\r
+#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear\r
+#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection\r
+#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None\r
+#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none\r
+#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set\r
+#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear\r
+#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none\r
+#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set\r
+#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear\r
+#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none\r
+#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set\r
+#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear\r
+#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none\r
+#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set\r
+#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear\r
+#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none\r
+#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set\r
+#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear\r
+#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none\r
+#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set\r
+#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear\r
+#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading\r
+#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger\r
+#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_TCB {\r
+ AT91S_TC TCB_TC0; // TC Channel 0\r
+ AT91_REG Reserved0[4]; // \r
+ AT91S_TC TCB_TC1; // TC Channel 1\r
+ AT91_REG Reserved1[4]; // \r
+ AT91S_TC TCB_TC2; // TC Channel 2\r
+ AT91_REG Reserved2[4]; // \r
+ AT91_REG TCB_BCR; // TC Block Control Register\r
+ AT91_REG TCB_BMR; // TC Block Mode Register\r
+} AT91S_TCB, *AT91PS_TCB;\r
+#else\r
+#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register\r
+#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register\r
+\r
+#endif\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection\r
+#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection\r
+#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection\r
+#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Multimedia Card Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_MCI {\r
+ AT91_REG MCI_CR; // MCI Control Register\r
+ AT91_REG MCI_MR; // MCI Mode Register\r
+ AT91_REG MCI_DTOR; // MCI Data Timeout Register\r
+ AT91_REG MCI_SDCR; // MCI SD Card Register\r
+ AT91_REG MCI_ARGR; // MCI Argument Register\r
+ AT91_REG MCI_CMDR; // MCI Command Register\r
+ AT91_REG MCI_BLKR; // MCI Block Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG MCI_RSPR[4]; // MCI Response Register\r
+ AT91_REG MCI_RDR; // MCI Receive Data Register\r
+ AT91_REG MCI_TDR; // MCI Transmit Data Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG MCI_SR; // MCI Status Register\r
+ AT91_REG MCI_IER; // MCI Interrupt Enable Register\r
+ AT91_REG MCI_IDR; // MCI Interrupt Disable Register\r
+ AT91_REG MCI_IMR; // MCI Interrupt Mask Register\r
+ AT91_REG Reserved2[43]; // \r
+ AT91_REG MCI_VR; // MCI Version Register\r
+ AT91_REG MCI_RPR; // Receive Pointer Register\r
+ AT91_REG MCI_RCR; // Receive Counter Register\r
+ AT91_REG MCI_TPR; // Transmit Pointer Register\r
+ AT91_REG MCI_TCR; // Transmit Counter Register\r
+ AT91_REG MCI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG MCI_RNCR; // Receive Next Counter Register\r
+ AT91_REG MCI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG MCI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG MCI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG MCI_PTSR; // PDC Transfer Status Register\r
+} AT91S_MCI, *AT91PS_MCI;\r
+#else\r
+#define MCI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (MCI_CR) MCI Control Register\r
+#define MCI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (MCI_MR) MCI Mode Register\r
+#define MCI_DTOR (AT91_CAST(AT91_REG *) 0x00000008) // (MCI_DTOR) MCI Data Timeout Register\r
+#define MCI_SDCR (AT91_CAST(AT91_REG *) 0x0000000C) // (MCI_SDCR) MCI SD Card Register\r
+#define MCI_ARGR (AT91_CAST(AT91_REG *) 0x00000010) // (MCI_ARGR) MCI Argument Register\r
+#define MCI_CMDR (AT91_CAST(AT91_REG *) 0x00000014) // (MCI_CMDR) MCI Command Register\r
+#define MCI_BLKR (AT91_CAST(AT91_REG *) 0x00000018) // (MCI_BLKR) MCI Block Register\r
+#define MCI_RSPR (AT91_CAST(AT91_REG *) 0x00000020) // (MCI_RSPR) MCI Response Register\r
+#define MCI_RDR (AT91_CAST(AT91_REG *) 0x00000030) // (MCI_RDR) MCI Receive Data Register\r
+#define MCI_TDR (AT91_CAST(AT91_REG *) 0x00000034) // (MCI_TDR) MCI Transmit Data Register\r
+#define MCI_SR (AT91_CAST(AT91_REG *) 0x00000040) // (MCI_SR) MCI Status Register\r
+#define MCI_IER (AT91_CAST(AT91_REG *) 0x00000044) // (MCI_IER) MCI Interrupt Enable Register\r
+#define MCI_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (MCI_IDR) MCI Interrupt Disable Register\r
+#define MCI_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register\r
+#define MCI_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (MCI_VR) MCI Version Register\r
+\r
+#endif\r
+// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- \r
+#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable\r
+#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable\r
+#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable\r
+#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable\r
+#define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset\r
+// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- \r
+#define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider\r
+#define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider\r
+#define AT91C_MCI_RDPROOF (0x1 << 11) // (MCI) Read Proof Enable\r
+#define AT91C_MCI_WRPROOF (0x1 << 12) // (MCI) Write Proof Enable\r
+#define AT91C_MCI_PDCFBYTE (0x1 << 13) // (MCI) PDC Force Byte Transfer\r
+#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value\r
+#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode\r
+#define AT91C_MCI_BLKLEN (0xFFFF << 16) // (MCI) Data Block Length\r
+// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- \r
+#define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number\r
+#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier\r
+#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1\r
+#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16\r
+#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128\r
+#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256\r
+#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024\r
+#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096\r
+#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536\r
+#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576\r
+// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- \r
+#define AT91C_MCI_SCDSEL (0x3 << 0) // (MCI) SD Card Selector\r
+#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SDCard/SDIO Bus Width\r
+// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- \r
+#define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number\r
+#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type\r
+#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response\r
+#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response\r
+#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response\r
+#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD\r
+#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD\r
+#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD\r
+#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD\r
+#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command\r
+#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response\r
+#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command\r
+#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond\r
+#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD\r
+#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer\r
+#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer\r
+#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer\r
+#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction\r
+#define AT91C_MCI_TRTYP (0x7 << 19) // (MCI) Transfer Type\r
+#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type\r
+#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type\r
+#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) MMC Stream transfer type\r
+#define AT91C_MCI_TRTYP_SDIO_BYTE (0x4 << 19) // (MCI) SDIO Byte transfer type\r
+#define AT91C_MCI_TRTYP_SDIO_BLOCK (0x5 << 19) // (MCI) SDIO Block transfer type\r
+#define AT91C_MCI_IOSPCMD (0x3 << 24) // (MCI) SDIO Special Command\r
+#define AT91C_MCI_IOSPCMD_NONE (0x0 << 24) // (MCI) NOT a special command\r
+#define AT91C_MCI_IOSPCMD_SUSPEND (0x1 << 24) // (MCI) SDIO Suspend Command\r
+#define AT91C_MCI_IOSPCMD_RESUME (0x2 << 24) // (MCI) SDIO Resume Command\r
+// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register -------- \r
+#define AT91C_MCI_BCNT (0xFFFF << 0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count\r
+// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- \r
+#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag\r
+#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag\r
+#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag\r
+#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag\r
+#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag\r
+#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag\r
+#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag\r
+#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag\r
+#define AT91C_MCI_SDIOIRQA (0x1 << 8) // (MCI) SDIO Interrupt for Slot A\r
+#define AT91C_MCI_SDIOIRQB (0x1 << 9) // (MCI) SDIO Interrupt for Slot B\r
+#define AT91C_MCI_SDIOIRQC (0x1 << 10) // (MCI) SDIO Interrupt for Slot C\r
+#define AT91C_MCI_SDIOIRQD (0x1 << 11) // (MCI) SDIO Interrupt for Slot D\r
+#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag\r
+#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag\r
+#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag\r
+#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag\r
+#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag\r
+#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag\r
+#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag\r
+#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag\r
+#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag\r
+#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag\r
+#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag\r
+// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- \r
+// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- \r
+// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_TWI {\r
+ AT91_REG TWI_CR; // Control Register\r
+ AT91_REG TWI_MMR; // Master Mode Register\r
+ AT91_REG TWI_SMR; // Slave Mode Register\r
+ AT91_REG TWI_IADR; // Internal Address Register\r
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register\r
+ AT91_REG Reserved0[3]; // \r
+ AT91_REG TWI_SR; // Status Register\r
+ AT91_REG TWI_IER; // Interrupt Enable Register\r
+ AT91_REG TWI_IDR; // Interrupt Disable Register\r
+ AT91_REG TWI_IMR; // Interrupt Mask Register\r
+ AT91_REG TWI_RHR; // Receive Holding Register\r
+ AT91_REG TWI_THR; // Transmit Holding Register\r
+ AT91_REG Reserved1[50]; // \r
+ AT91_REG TWI_RPR; // Receive Pointer Register\r
+ AT91_REG TWI_RCR; // Receive Counter Register\r
+ AT91_REG TWI_TPR; // Transmit Pointer Register\r
+ AT91_REG TWI_TCR; // Transmit Counter Register\r
+ AT91_REG TWI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG TWI_RNCR; // Receive Next Counter Register\r
+ AT91_REG TWI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG TWI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG TWI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG TWI_PTSR; // PDC Transfer Status Register\r
+} AT91S_TWI, *AT91PS_TWI;\r
+#else\r
+#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register\r
+#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register\r
+#define TWI_SMR (AT91_CAST(AT91_REG *) 0x00000008) // (TWI_SMR) Slave Mode Register\r
+#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register\r
+#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register\r
+#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register\r
+#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register\r
+#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register\r
+#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register\r
+#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register\r
+#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register\r
+\r
+#endif\r
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition\r
+#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition\r
+#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled\r
+#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled\r
+#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave mode Enabled\r
+#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave mode Disabled\r
+#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset\r
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size\r
+#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address\r
+#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address\r
+#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address\r
+#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address\r
+#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction\r
+#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address\r
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- \r
+#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Address\r
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider\r
+#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider\r
+#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider\r
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+#define AT91C_TWI_TXCOMP_SLAVE (0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_TXCOMP_MASTER (0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY\r
+#define AT91C_TWI_TXRDY_MASTER (0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_TXRDY_SLAVE (0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave READ (used only in Slave mode)\r
+#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave ACCess (used only in Slave mode)\r
+#define AT91C_TWI_GACC (0x1 << 5) // (TWI) General Call ACcess (used only in Slave mode)\r
+#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error (used only in Master and Multi-master mode)\r
+#define AT91C_TWI_NACK_SLAVE (0x1 << 8) // (TWI) Not Acknowledged\r
+#define AT91C_TWI_NACK_MASTER (0x1 << 8) // (TWI) Not Acknowledged\r
+#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 << 9) // (TWI) Arbitration Lost (used only in Multimaster mode)\r
+#define AT91C_TWI_SCLWS (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)\r
+#define AT91C_TWI_EOSACC (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)\r
+#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) End of Receiver Transfer\r
+#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) End of Receiver Transfer\r
+#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) RXBUFF Interrupt\r
+#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) TXBUFE Interrupt\r
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Usart\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_USART {\r
+ AT91_REG US_CR; // Control Register\r
+ AT91_REG US_MR; // Mode Register\r
+ AT91_REG US_IER; // Interrupt Enable Register\r
+ AT91_REG US_IDR; // Interrupt Disable Register\r
+ AT91_REG US_IMR; // Interrupt Mask Register\r
+ AT91_REG US_CSR; // Channel Status Register\r
+ AT91_REG US_RHR; // Receiver Holding Register\r
+ AT91_REG US_THR; // Transmitter Holding Register\r
+ AT91_REG US_BRGR; // Baud Rate Generator Register\r
+ AT91_REG US_RTOR; // Receiver Time-out Register\r
+ AT91_REG US_TTGR; // Transmitter Time-guard Register\r
+ AT91_REG Reserved0[5]; // \r
+ AT91_REG US_FIDI; // FI_DI_Ratio Register\r
+ AT91_REG US_NER; // Nb Errors Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG US_IF; // IRDA_FILTER Register\r
+ AT91_REG Reserved2[44]; // \r
+ AT91_REG US_RPR; // Receive Pointer Register\r
+ AT91_REG US_RCR; // Receive Counter Register\r
+ AT91_REG US_TPR; // Transmit Pointer Register\r
+ AT91_REG US_TCR; // Transmit Counter Register\r
+ AT91_REG US_RNPR; // Receive Next Pointer Register\r
+ AT91_REG US_RNCR; // Receive Next Counter Register\r
+ AT91_REG US_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG US_TNCR; // Transmit Next Counter Register\r
+ AT91_REG US_PTCR; // PDC Transfer Control Register\r
+ AT91_REG US_PTSR; // PDC Transfer Status Register\r
+} AT91S_USART, *AT91PS_USART;\r
+#else\r
+#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register\r
+#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register\r
+#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register\r
+#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register\r
+#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register\r
+#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register\r
+#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register\r
+#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register\r
+#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register\r
+#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register\r
+#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register\r
+#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register\r
+#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register\r
+#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register\r
+\r
+#endif\r
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break\r
+#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address\r
+#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations\r
+#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge\r
+#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out\r
+#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable\r
+#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable\r
+#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable\r
+#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable\r
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode\r
+#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal\r
+#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485\r
+#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking\r
+#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem\r
+#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0\r
+#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1\r
+#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA\r
+#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking\r
+#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock\r
+#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1\r
+#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)\r
+#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits\r
+#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits\r
+#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits\r
+#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits\r
+#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit\r
+#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order\r
+#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select\r
+#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode\r
+#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge\r
+#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK\r
+#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions\r
+#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter\r
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break\r
+#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out\r
+#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached\r
+#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge\r
+#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
+#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
+#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag\r
+#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag\r
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input\r
+#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input\r
+#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input\r
+#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SSC {\r
+ AT91_REG SSC_CR; // Control Register\r
+ AT91_REG SSC_CMR; // Clock Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister\r
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register\r
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register\r
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register\r
+ AT91_REG SSC_RHR; // Receive Holding Register\r
+ AT91_REG SSC_THR; // Transmit Holding Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register\r
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register\r
+ AT91_REG Reserved2[2]; // \r
+ AT91_REG SSC_SR; // Status Register\r
+ AT91_REG SSC_IER; // Interrupt Enable Register\r
+ AT91_REG SSC_IDR; // Interrupt Disable Register\r
+ AT91_REG SSC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved3[44]; // \r
+ AT91_REG SSC_RPR; // Receive Pointer Register\r
+ AT91_REG SSC_RCR; // Receive Counter Register\r
+ AT91_REG SSC_TPR; // Transmit Pointer Register\r
+ AT91_REG SSC_TCR; // Transmit Counter Register\r
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SSC_RNCR; // Receive Next Counter Register\r
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register\r
+} AT91S_SSC, *AT91PS_SSC;\r
+#else\r
+#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register\r
+#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register\r
+#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister\r
+#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register\r
+#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register\r
+#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register\r
+#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register\r
+#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register\r
+#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register\r
+#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register\r
+#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register\r
+#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register\r
+#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register\r
+#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register\r
+\r
+#endif\r
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable\r
+#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable\r
+#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable\r
+#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable\r
+#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset\r
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection\r
+#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock\r
+#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal\r
+#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin\r
+#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
+#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion\r
+#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection\r
+#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start\r
+#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input\r
+#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input\r
+#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input\r
+#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input\r
+#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input\r
+#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input\r
+#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0\r
+#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
+#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length\r
+#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode\r
+#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First\r
+#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame\r
+#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
+#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
+#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection\r
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value\r
+#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable\r
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready\r
+#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty\r
+#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission\r
+#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty\r
+#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready\r
+#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun\r
+#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception\r
+#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full\r
+#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync\r
+#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync\r
+#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable\r
+#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable\r
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SPI {\r
+ AT91_REG SPI_CR; // Control Register\r
+ AT91_REG SPI_MR; // Mode Register\r
+ AT91_REG SPI_RDR; // Receive Data Register\r
+ AT91_REG SPI_TDR; // Transmit Data Register\r
+ AT91_REG SPI_SR; // Status Register\r
+ AT91_REG SPI_IER; // Interrupt Enable Register\r
+ AT91_REG SPI_IDR; // Interrupt Disable Register\r
+ AT91_REG SPI_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved0[4]; // \r
+ AT91_REG SPI_CSR[4]; // Chip Select Register\r
+ AT91_REG Reserved1[48]; // \r
+ AT91_REG SPI_RPR; // Receive Pointer Register\r
+ AT91_REG SPI_RCR; // Receive Counter Register\r
+ AT91_REG SPI_TPR; // Transmit Pointer Register\r
+ AT91_REG SPI_TCR; // Transmit Counter Register\r
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SPI_RNCR; // Receive Next Counter Register\r
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register\r
+} AT91S_SPI, *AT91PS_SPI;\r
+#else\r
+#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register\r
+#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register\r
+#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register\r
+#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register\r
+#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register\r
+#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register\r
+#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register\r
+#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register\r
+#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register\r
+\r
+#endif\r
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable\r
+#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable\r
+#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset\r
+#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer\r
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode\r
+#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select\r
+#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select\r
+#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select\r
+#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode\r
+#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection\r
+#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection\r
+#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection\r
+#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select\r
+#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects\r
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data\r
+#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data\r
+#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full\r
+#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty\r
+#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error\r
+#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status\r
+#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt\r
+#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt\r
+#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt\r
+#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt\r
+#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status\r
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity\r
+#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase\r
+#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer\r
+#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer\r
+#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer\r
+#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer\r
+#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer\r
+#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer\r
+#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer\r
+#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer\r
+#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer\r
+#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer\r
+#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer\r
+#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK\r
+#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_ADC {\r
+ AT91_REG ADC_CR; // ADC Control Register\r
+ AT91_REG ADC_MR; // ADC Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG ADC_CHER; // ADC Channel Enable Register\r
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register\r
+ AT91_REG ADC_CHSR; // ADC Channel Status Register\r
+ AT91_REG ADC_SR; // ADC Status Register\r
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register\r
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register\r
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register\r
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register\r
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0\r
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1\r
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2\r
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3\r
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4\r
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5\r
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6\r
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7\r
+ AT91_REG Reserved1[44]; // \r
+ AT91_REG ADC_RPR; // Receive Pointer Register\r
+ AT91_REG ADC_RCR; // Receive Counter Register\r
+ AT91_REG ADC_TPR; // Transmit Pointer Register\r
+ AT91_REG ADC_TCR; // Transmit Counter Register\r
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG ADC_RNCR; // Receive Next Counter Register\r
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register\r
+} AT91S_ADC, *AT91PS_ADC;\r
+#else\r
+#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register\r
+#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register\r
+#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register\r
+#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register\r
+#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register\r
+#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register\r
+#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register\r
+#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register\r
+#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register\r
+#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register\r
+#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0\r
+#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1\r
+#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2\r
+#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3\r
+#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4\r
+#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5\r
+#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6\r
+#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7\r
+\r
+#endif\r
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset\r
+#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion\r
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable\r
+#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection\r
+#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0\r
+#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1\r
+#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2\r
+#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3\r
+#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4\r
+#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5\r
+#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger\r
+#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.\r
+#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution\r
+#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution\r
+#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode\r
+#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection\r
+#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time\r
+#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time\r
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0\r
+#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1\r
+#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2\r
+#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3\r
+#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4\r
+#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5\r
+#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6\r
+#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7\r
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion\r
+#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error\r
+#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready\r
+#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun\r
+#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer\r
+#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt\r
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted\r
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data\r
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_EMAC {\r
+ AT91_REG EMAC_NCR; // Network Control Register\r
+ AT91_REG EMAC_NCFGR; // Network Configuration Register\r
+ AT91_REG EMAC_NSR; // Network Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG EMAC_TSR; // Transmit Status Register\r
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer\r
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer\r
+ AT91_REG EMAC_RSR; // Receive Status Register\r
+ AT91_REG EMAC_ISR; // Interrupt Status Register\r
+ AT91_REG EMAC_IER; // Interrupt Enable Register\r
+ AT91_REG EMAC_IDR; // Interrupt Disable Register\r
+ AT91_REG EMAC_IMR; // Interrupt Mask Register\r
+ AT91_REG EMAC_MAN; // PHY Maintenance Register\r
+ AT91_REG EMAC_PTR; // Pause Time Register\r
+ AT91_REG EMAC_PFR; // Pause Frames received Register\r
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register\r
+ AT91_REG EMAC_SCF; // Single Collision Frame Register\r
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register\r
+ AT91_REG EMAC_FRO; // Frames Received OK Register\r
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register\r
+ AT91_REG EMAC_ALE; // Alignment Error Register\r
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register\r
+ AT91_REG EMAC_LCOL; // Late Collision Register\r
+ AT91_REG EMAC_ECOL; // Excessive Collision Register\r
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register\r
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register\r
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register\r
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register\r
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register\r
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register\r
+ AT91_REG EMAC_RJA; // Receive Jabbers Register\r
+ AT91_REG EMAC_USF; // Undersize Frames Register\r
+ AT91_REG EMAC_STE; // SQE Test Error Register\r
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register\r
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register\r
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]\r
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]\r
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes\r
+ AT91_REG EMAC_TID; // Type ID Checking Register\r
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register\r
+ AT91_REG EMAC_USRIO; // USER Input/Output Register\r
+ AT91_REG EMAC_WOL; // Wake On LAN Register\r
+ AT91_REG Reserved1[13]; // \r
+ AT91_REG EMAC_REV; // Revision Register\r
+} AT91S_EMAC, *AT91PS_EMAC;\r
+#else\r
+#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register\r
+#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register\r
+#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register\r
+#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register\r
+#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer\r
+#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer\r
+#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register\r
+#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register\r
+#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register\r
+#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register\r
+#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register\r
+#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register\r
+#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register\r
+#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register\r
+#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register\r
+#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register\r
+#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register\r
+#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register\r
+#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register\r
+#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register\r
+#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register\r
+#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register\r
+#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register\r
+#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register\r
+#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register\r
+#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register\r
+#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register\r
+#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register\r
+#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register\r
+#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register\r
+#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register\r
+#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register\r
+#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register\r
+#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register\r
+#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]\r
+#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32]\r
+#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes\r
+#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes\r
+#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes\r
+#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes\r
+#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes\r
+#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes\r
+#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes\r
+#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes\r
+#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register\r
+#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register\r
+#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register\r
+#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register\r
+#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register\r
+\r
+#endif\r
+// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- \r
+#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.\r
+#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. \r
+#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. \r
+#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. \r
+#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. \r
+#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. \r
+#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. \r
+#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. \r
+#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. \r
+#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. \r
+#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. \r
+#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame \r
+#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame\r
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- \r
+#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. \r
+#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. \r
+#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. \r
+#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. \r
+#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. \r
+#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable\r
+#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. \r
+#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. \r
+#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. \r
+#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) \r
+#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8\r
+#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16\r
+#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32\r
+#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64\r
+#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) \r
+#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) \r
+#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable\r
+#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS\r
+#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) \r
+#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS\r
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- \r
+#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) \r
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- \r
+#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go\r
+#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame\r
+#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) \r
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \r
+#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) \r
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \r
+#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) \r
+#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) \r
+#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) \r
+#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) \r
+#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) \r
+#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) \r
+#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) \r
+#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) \r
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \r
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \r
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \r
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \r
+#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) \r
+#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) \r
+#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) \r
+#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) \r
+#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) \r
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- \r
+#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII\r
+#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable\r
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- \r
+#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address\r
+#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable\r
+#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable\r
+#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable\r
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- \r
+#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Device Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_UDP {\r
+ AT91_REG UDP_NUM; // Frame Number Register\r
+ AT91_REG UDP_GLBSTATE; // Global State Register\r
+ AT91_REG UDP_FADDR; // Function Address Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG UDP_IER; // Interrupt Enable Register\r
+ AT91_REG UDP_IDR; // Interrupt Disable Register\r
+ AT91_REG UDP_IMR; // Interrupt Mask Register\r
+ AT91_REG UDP_ISR; // Interrupt Status Register\r
+ AT91_REG UDP_ICR; // Interrupt Clear Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register\r
+ AT91_REG Reserved3[2]; // \r
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register\r
+ AT91_REG Reserved4[3]; // \r
+ AT91_REG UDP_TXVC; // Transceiver Control Register\r
+} AT91S_UDP, *AT91PS_UDP;\r
+#else\r
+#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register\r
+#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register\r
+#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register\r
+#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register\r
+#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register\r
+#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register\r
+#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register\r
+#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register\r
+#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register\r
+#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register\r
+#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register\r
+#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register\r
+\r
+#endif\r
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
+#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error\r
+#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK\r
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable\r
+#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured\r
+#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume\r
+#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host\r
+#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable\r
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value\r
+#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable\r
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt\r
+#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt\r
+#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt\r
+#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt\r
+#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt\r
+#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt\r
+#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt\r
+#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt\r
+#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt\r
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\r
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0\r
+#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1\r
+#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2\r
+#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3\r
+#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4\r
+#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5\r
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR\r
+#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0\r
+#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)\r
+#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)\r
+#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)\r
+#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready\r
+#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction\r
+#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type\r
+#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control\r
+#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT\r
+#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT\r
+#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT\r
+#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN\r
+#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN\r
+#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN\r
+#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle\r
+#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable\r
+#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\r
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- \r
+#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) \r
+#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Host Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_UHP {\r
+ AT91_REG UHP_HcRevision; // Revision\r
+ AT91_REG UHP_HcControl; // Operating modes for the Host Controller\r
+ AT91_REG UHP_HcCommandStatus; // Command & status Register\r
+ AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register\r
+ AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register\r
+ AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register\r
+ AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area\r
+ AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor\r
+ AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list\r
+ AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register\r
+ AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list\r
+ AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list\r
+ AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor\r
+ AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs\r
+ AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame\r
+ AT91_REG UHP_HcFmNumber; // Frame number\r
+ AT91_REG UHP_HcPeriodicStart; // Periodic Start\r
+ AT91_REG UHP_HcLSThreshold; // LS Threshold\r
+ AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A\r
+ AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B\r
+ AT91_REG UHP_HcRhStatus; // Root Hub Status register\r
+ AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register\r
+} AT91S_UHP, *AT91PS_UHP;\r
+#else\r
+#define HcRevision (AT91_CAST(AT91_REG *) 0x00000000) // (HcRevision) Revision\r
+#define HcControl (AT91_CAST(AT91_REG *) 0x00000004) // (HcControl) Operating modes for the Host Controller\r
+#define HcCommandStatus (AT91_CAST(AT91_REG *) 0x00000008) // (HcCommandStatus) Command & status Register\r
+#define HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0000000C) // (HcInterruptStatus) Interrupt Status Register\r
+#define HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00000010) // (HcInterruptEnable) Interrupt Enable Register\r
+#define HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00000014) // (HcInterruptDisable) Interrupt Disable Register\r
+#define HcHCCA (AT91_CAST(AT91_REG *) 0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area\r
+#define HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor\r
+#define HcControlHeadED (AT91_CAST(AT91_REG *) 0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list\r
+#define HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register\r
+#define HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list\r
+#define HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list\r
+#define HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor\r
+#define HcFmInterval (AT91_CAST(AT91_REG *) 0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs\r
+#define HcFmRemaining (AT91_CAST(AT91_REG *) 0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame\r
+#define HcFmNumber (AT91_CAST(AT91_REG *) 0x0000003C) // (HcFmNumber) Frame number\r
+#define HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00000040) // (HcPeriodicStart) Periodic Start\r
+#define HcLSThreshold (AT91_CAST(AT91_REG *) 0x00000044) // (HcLSThreshold) LS Threshold\r
+#define HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00000048) // (HcRhDescriptorA) Root Hub characteristics A\r
+#define HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B\r
+#define HcRhStatus (AT91_CAST(AT91_REG *) 0x00000050) // (HcRhStatus) Root Hub Status register\r
+#define HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00000054) // (HcRhPortStatus) Root Hub Port Status Register\r
+\r
+#endif\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Image Sensor Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_ISI {\r
+ AT91_REG ISI_CR1; // Control Register 1\r
+ AT91_REG ISI_CR2; // Control Register 2\r
+ AT91_REG ISI_SR; // Status Register\r
+ AT91_REG ISI_IER; // Interrupt Enable Register\r
+ AT91_REG ISI_IDR; // Interrupt Disable Register\r
+ AT91_REG ISI_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG ISI_PSIZE; // Preview Size Register\r
+ AT91_REG ISI_PDECF; // Preview Decimation Factor Register\r
+ AT91_REG ISI_PFBD; // Preview Frame Buffer Address Register\r
+ AT91_REG ISI_CDBA; // Codec Dma Address Register\r
+ AT91_REG ISI_Y2RSET0; // Color Space Conversion Register\r
+ AT91_REG ISI_Y2RSET1; // Color Space Conversion Register\r
+ AT91_REG ISI_R2YSET0; // Color Space Conversion Register\r
+ AT91_REG ISI_R2YSET1; // Color Space Conversion Register\r
+ AT91_REG ISI_R2YSET2; // Color Space Conversion Register\r
+} AT91S_ISI, *AT91PS_ISI;\r
+#else\r
+#define ISI_CR1 (AT91_CAST(AT91_REG *) 0x00000000) // (ISI_CR1) Control Register 1\r
+#define ISI_CR2 (AT91_CAST(AT91_REG *) 0x00000004) // (ISI_CR2) Control Register 2\r
+#define ISI_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ISI_SR) Status Register\r
+#define ISI_IER (AT91_CAST(AT91_REG *) 0x0000000C) // (ISI_IER) Interrupt Enable Register\r
+#define ISI_IDR (AT91_CAST(AT91_REG *) 0x00000010) // (ISI_IDR) Interrupt Disable Register\r
+#define ISI_IMR (AT91_CAST(AT91_REG *) 0x00000014) // (ISI_IMR) Interrupt Mask Register\r
+#define ISI_PSIZE (AT91_CAST(AT91_REG *) 0x00000020) // (ISI_PSIZE) Preview Size Register\r
+#define ISI_PDECF (AT91_CAST(AT91_REG *) 0x00000024) // (ISI_PDECF) Preview Decimation Factor Register\r
+#define ISI_PFBD (AT91_CAST(AT91_REG *) 0x00000028) // (ISI_PFBD) Preview Frame Buffer Address Register\r
+#define ISI_CDBA (AT91_CAST(AT91_REG *) 0x0000002C) // (ISI_CDBA) Codec Dma Address Register\r
+#define ISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0x00000030) // (ISI_Y2RSET0) Color Space Conversion Register\r
+#define ISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0x00000034) // (ISI_Y2RSET1) Color Space Conversion Register\r
+#define ISI_R2YSET0 (AT91_CAST(AT91_REG *) 0x00000038) // (ISI_R2YSET0) Color Space Conversion Register\r
+#define ISI_R2YSET1 (AT91_CAST(AT91_REG *) 0x0000003C) // (ISI_R2YSET1) Color Space Conversion Register\r
+#define ISI_R2YSET2 (AT91_CAST(AT91_REG *) 0x00000040) // (ISI_R2YSET2) Color Space Conversion Register\r
+\r
+#endif\r
+// -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 -------- \r
+#define AT91C_ISI_RST (0x1 << 0) // (ISI) Image sensor interface reset\r
+#define AT91C_ISI_DISABLE (0x1 << 1) // (ISI) image sensor disable.\r
+#define AT91C_ISI_HSYNC_POL (0x1 << 2) // (ISI) Horizontal synchronisation polarity\r
+#define AT91C_ISI_PIXCLK_POL (0x1 << 4) // (ISI) Pixel Clock Polarity\r
+#define AT91C_ISI_EMB_SYNC (0x1 << 6) // (ISI) Embedded synchronisation\r
+#define AT91C_ISI_CRC_SYNC (0x1 << 7) // (ISI) CRC correction\r
+#define AT91C_ISI_FULL (0x1 << 12) // (ISI) Full mode is allowed\r
+#define AT91C_ISI_THMASK (0x3 << 13) // (ISI) DMA Burst Mask\r
+#define AT91C_ISI_THMASK_4_8_16_BURST (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed\r
+#define AT91C_ISI_THMASK_8_16_BURST (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed\r
+#define AT91C_ISI_THMASK_16_BURST (0x2 << 13) // (ISI) Only 16 AHB burst are allowed\r
+#define AT91C_ISI_CODEC_ON (0x1 << 15) // (ISI) Enable the codec path\r
+#define AT91C_ISI_SLD (0xFF << 16) // (ISI) Start of Line Delay\r
+#define AT91C_ISI_SFD (0xFF << 24) // (ISI) Start of frame Delay\r
+// -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 -------- \r
+#define AT91C_ISI_IM_VSIZE (0x7FF << 0) // (ISI) Vertical size of the Image sensor [0..2047]\r
+#define AT91C_ISI_GS_MODE (0x1 << 11) // (ISI) Grayscale Memory Mode\r
+#define AT91C_ISI_RGB_MODE (0x3 << 12) // (ISI) RGB mode\r
+#define AT91C_ISI_RGB_MODE_RGB_888 (0x0 << 12) // (ISI) RGB 8:8:8 24 bits\r
+#define AT91C_ISI_RGB_MODE_RGB_565 (0x1 << 12) // (ISI) RGB 5:6:5 16 bits\r
+#define AT91C_ISI_RGB_MODE_RGB_555 (0x2 << 12) // (ISI) RGB 5:5:5 16 bits\r
+#define AT91C_ISI_GRAYSCALE (0x1 << 13) // (ISI) Grayscale Mode\r
+#define AT91C_ISI_RGB_SWAP (0x1 << 14) // (ISI) RGB Swap\r
+#define AT91C_ISI_COL_SPACE (0x1 << 15) // (ISI) Color space for the image data\r
+#define AT91C_ISI_IM_HSIZE (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047]\r
+#define AT91C_ISI_RGB_MODE_YCC_DEF (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1)\r
+#define AT91C_ISI_RGB_MODE_YCC_MOD1 (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1)\r
+#define AT91C_ISI_RGB_MODE_YCC_MOD2 (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i)\r
+#define AT91C_ISI_RGB_MODE_YCC_MOD3 (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i)\r
+#define AT91C_ISI_RGB_CFG (0x3 << 30) // (ISI) RGB configuration\r
+#define AT91C_ISI_RGB_CFG_RGB_DEF (0x0 << 30) // (ISI) R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B\r
+#define AT91C_ISI_RGB_CFG_RGB_MOD1 (0x1 << 30) // (ISI) B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R\r
+#define AT91C_ISI_RGB_CFG_RGB_MOD2 (0x2 << 30) // (ISI) G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB)\r
+#define AT91C_ISI_RGB_CFG_RGB_MOD3 (0x3 << 30) // (ISI) G(LSB)/B R/G(MSB) G(LSB)/B R/G(MSB)\r
+// -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register -------- \r
+#define AT91C_ISI_SOF (0x1 << 0) // (ISI) Start of Frame\r
+#define AT91C_ISI_DIS (0x1 << 1) // (ISI) Image Sensor Interface disable\r
+#define AT91C_ISI_SOFTRST (0x1 << 2) // (ISI) Software Reset\r
+#define AT91C_ISI_CRC_ERR (0x1 << 4) // (ISI) CRC synchronisation error\r
+#define AT91C_ISI_FO_C_OVF (0x1 << 5) // (ISI) Fifo Codec Overflow \r
+#define AT91C_ISI_FO_P_OVF (0x1 << 6) // (ISI) Fifo Preview Overflow \r
+#define AT91C_ISI_FO_P_EMP (0x1 << 7) // (ISI) Fifo Preview Empty\r
+#define AT91C_ISI_FO_C_EMP (0x1 << 8) // (ISI) Fifo Codec Empty\r
+#define AT91C_ISI_FR_OVR (0x1 << 9) // (ISI) Frame rate overun\r
+// -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register -------- \r
+// -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register -------- \r
+// -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register -------- \r
+// -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register -------- \r
+#define AT91C_ISI_PREV_VSIZE (0x3FF << 0) // (ISI) Vertical size for the preview path\r
+#define AT91C_ISI_PREV_HSIZE (0x3FF << 16) // (ISI) Horizontal size for the preview path\r
+// -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register -------- \r
+#define AT91C_ISI_Y2R_C0 (0xFF << 0) // (ISI) Color Space Conversion Matrix Coefficient C0\r
+#define AT91C_ISI_Y2R_C1 (0xFF << 8) // (ISI) Color Space Conversion Matrix Coefficient C1\r
+#define AT91C_ISI_Y2R_C2 (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2\r
+#define AT91C_ISI_Y2R_C3 (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3\r
+// -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register -------- \r
+#define AT91C_ISI_Y2R_C4 (0x1FF << 0) // (ISI) Color Space Conversion Matrix Coefficient C4\r
+#define AT91C_ISI_Y2R_YOFF (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset\r
+#define AT91C_ISI_Y2R_CROFF (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset\r
+#define AT91C_ISI_Y2R_CBFF (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset\r
+// -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register -------- \r
+#define AT91C_ISI_R2Y_C0 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0\r
+#define AT91C_ISI_R2Y_C1 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1\r
+#define AT91C_ISI_R2Y_C2 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2\r
+#define AT91C_ISI_R2Y_ROFF (0x1 << 4) // (ISI) Color Space Conversion Red component offset\r
+// -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register -------- \r
+#define AT91C_ISI_R2Y_C3 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3\r
+#define AT91C_ISI_R2Y_C4 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4\r
+#define AT91C_ISI_R2Y_C5 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5\r
+#define AT91C_ISI_R2Y_GOFF (0x1 << 4) // (ISI) Color Space Conversion Green component offset\r
+// -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register -------- \r
+#define AT91C_ISI_R2Y_C6 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6\r
+#define AT91C_ISI_R2Y_C7 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7\r
+#define AT91C_ISI_R2Y_C8 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8\r
+#define AT91C_ISI_R2Y_BOFF (0x1 << 4) // (ISI) Color Space Conversion Blue component offset\r
+\r
+// *****************************************************************************\r
+// REGISTER ADDRESS DEFINITION FOR AT91SAM9XE128\r
+// *****************************************************************************\r
+// ========== Register definition for SYS peripheral ========== \r
+#define AT91C_SYS_GPBR (AT91_CAST(AT91_REG *) 0xFFFFFFFF) // (SYS) General Purpose Register\r
+// ========== Register definition for EBI peripheral ========== \r
+#define AT91C_EBI_DUMMY (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (EBI) Dummy register - Do not use\r
+// ========== Register definition for HECC peripheral ========== \r
+#define AT91C_HECC_VR (AT91_CAST(AT91_REG *) 0xFFFFE8FC) // (HECC) ECC Version register\r
+#define AT91C_HECC_NPR (AT91_CAST(AT91_REG *) 0xFFFFE810) // (HECC) ECC Parity N register\r
+#define AT91C_HECC_SR (AT91_CAST(AT91_REG *) 0xFFFFE808) // (HECC) ECC Status register\r
+#define AT91C_HECC_PR (AT91_CAST(AT91_REG *) 0xFFFFE80C) // (HECC) ECC Parity register\r
+#define AT91C_HECC_MR (AT91_CAST(AT91_REG *) 0xFFFFE804) // (HECC) ECC Page size register\r
+#define AT91C_HECC_CR (AT91_CAST(AT91_REG *) 0xFFFFE800) // (HECC) ECC reset register\r
+// ========== Register definition for SDRAMC peripheral ========== \r
+#define AT91C_SDRAMC_MR (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register\r
+#define AT91C_SDRAMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register\r
+#define AT91C_SDRAMC_LPR (AT91_CAST(AT91_REG *) 0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register\r
+#define AT91C_SDRAMC_ISR (AT91_CAST(AT91_REG *) 0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register\r
+#define AT91C_SDRAMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register\r
+#define AT91C_SDRAMC_CR (AT91_CAST(AT91_REG *) 0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register\r
+#define AT91C_SDRAMC_TR (AT91_CAST(AT91_REG *) 0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register\r
+#define AT91C_SDRAMC_MDR (AT91_CAST(AT91_REG *) 0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register\r
+#define AT91C_SDRAMC_HSR (AT91_CAST(AT91_REG *) 0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register\r
+#define AT91C_SDRAMC_IER (AT91_CAST(AT91_REG *) 0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register\r
+// ========== Register definition for SMC peripheral ========== \r
+#define AT91C_SMC_CTRL1 (AT91_CAST(AT91_REG *) 0xFFFFEC1C) // (SMC) Control Register for CS 1\r
+#define AT91C_SMC_PULSE7 (AT91_CAST(AT91_REG *) 0xFFFFEC74) // (SMC) Pulse Register for CS 7\r
+#define AT91C_SMC_PULSE6 (AT91_CAST(AT91_REG *) 0xFFFFEC64) // (SMC) Pulse Register for CS 6\r
+#define AT91C_SMC_SETUP4 (AT91_CAST(AT91_REG *) 0xFFFFEC40) // (SMC) Setup Register for CS 4\r
+#define AT91C_SMC_PULSE3 (AT91_CAST(AT91_REG *) 0xFFFFEC34) // (SMC) Pulse Register for CS 3\r
+#define AT91C_SMC_CYCLE5 (AT91_CAST(AT91_REG *) 0xFFFFEC58) // (SMC) Cycle Register for CS 5\r
+#define AT91C_SMC_CYCLE2 (AT91_CAST(AT91_REG *) 0xFFFFEC28) // (SMC) Cycle Register for CS 2\r
+#define AT91C_SMC_CTRL2 (AT91_CAST(AT91_REG *) 0xFFFFEC2C) // (SMC) Control Register for CS 2\r
+#define AT91C_SMC_CTRL0 (AT91_CAST(AT91_REG *) 0xFFFFEC0C) // (SMC) Control Register for CS 0\r
+#define AT91C_SMC_PULSE5 (AT91_CAST(AT91_REG *) 0xFFFFEC54) // (SMC) Pulse Register for CS 5\r
+#define AT91C_SMC_PULSE1 (AT91_CAST(AT91_REG *) 0xFFFFEC14) // (SMC) Pulse Register for CS 1\r
+#define AT91C_SMC_PULSE0 (AT91_CAST(AT91_REG *) 0xFFFFEC04) // (SMC) Pulse Register for CS 0\r
+#define AT91C_SMC_CYCLE7 (AT91_CAST(AT91_REG *) 0xFFFFEC78) // (SMC) Cycle Register for CS 7\r
+#define AT91C_SMC_CTRL4 (AT91_CAST(AT91_REG *) 0xFFFFEC4C) // (SMC) Control Register for CS 4\r
+#define AT91C_SMC_CTRL3 (AT91_CAST(AT91_REG *) 0xFFFFEC3C) // (SMC) Control Register for CS 3\r
+#define AT91C_SMC_SETUP7 (AT91_CAST(AT91_REG *) 0xFFFFEC70) // (SMC) Setup Register for CS 7\r
+#define AT91C_SMC_CTRL7 (AT91_CAST(AT91_REG *) 0xFFFFEC7C) // (SMC) Control Register for CS 7\r
+#define AT91C_SMC_SETUP1 (AT91_CAST(AT91_REG *) 0xFFFFEC10) // (SMC) Setup Register for CS 1\r
+#define AT91C_SMC_CYCLE0 (AT91_CAST(AT91_REG *) 0xFFFFEC08) // (SMC) Cycle Register for CS 0\r
+#define AT91C_SMC_CTRL5 (AT91_CAST(AT91_REG *) 0xFFFFEC5C) // (SMC) Control Register for CS 5\r
+#define AT91C_SMC_CYCLE1 (AT91_CAST(AT91_REG *) 0xFFFFEC18) // (SMC) Cycle Register for CS 1\r
+#define AT91C_SMC_CTRL6 (AT91_CAST(AT91_REG *) 0xFFFFEC6C) // (SMC) Control Register for CS 6\r
+#define AT91C_SMC_SETUP0 (AT91_CAST(AT91_REG *) 0xFFFFEC00) // (SMC) Setup Register for CS 0\r
+#define AT91C_SMC_PULSE4 (AT91_CAST(AT91_REG *) 0xFFFFEC44) // (SMC) Pulse Register for CS 4\r
+#define AT91C_SMC_SETUP5 (AT91_CAST(AT91_REG *) 0xFFFFEC50) // (SMC) Setup Register for CS 5\r
+#define AT91C_SMC_SETUP2 (AT91_CAST(AT91_REG *) 0xFFFFEC20) // (SMC) Setup Register for CS 2\r
+#define AT91C_SMC_CYCLE3 (AT91_CAST(AT91_REG *) 0xFFFFEC38) // (SMC) Cycle Register for CS 3\r
+#define AT91C_SMC_CYCLE6 (AT91_CAST(AT91_REG *) 0xFFFFEC68) // (SMC) Cycle Register for CS 6\r
+#define AT91C_SMC_SETUP6 (AT91_CAST(AT91_REG *) 0xFFFFEC60) // (SMC) Setup Register for CS 6\r
+#define AT91C_SMC_CYCLE4 (AT91_CAST(AT91_REG *) 0xFFFFEC48) // (SMC) Cycle Register for CS 4\r
+#define AT91C_SMC_PULSE2 (AT91_CAST(AT91_REG *) 0xFFFFEC24) // (SMC) Pulse Register for CS 2\r
+#define AT91C_SMC_SETUP3 (AT91_CAST(AT91_REG *) 0xFFFFEC30) // (SMC) Setup Register for CS 3\r
+// ========== Register definition for MATRIX peripheral ========== \r
+#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE00) // (MATRIX) Master Configuration Register 0 (ram96k) \r
+#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0xFFFFEE1C) // (MATRIX) Master Configuration Register 7 (teak_prog) \r
+#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE44) // (MATRIX) Slave Configuration Register 1 (rom) \r
+#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE10) // (MATRIX) Master Configuration Register 4 (bridge) \r
+#define AT91C_MATRIX_VERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (MATRIX) Version Register\r
+#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE08) // (MATRIX) Master Configuration Register 2 (hperiphs) \r
+#define AT91C_MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA4) // (MATRIX) PRBS4 : ebi\r
+#define AT91C_MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0xFFFFEE84) // (MATRIX) PRBS0 (ram0) \r
+#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE4C) // (MATRIX) Slave Configuration Register 3 (ebi)\r
+#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0xFFFFEE18) // (MATRIX) Master Configuration Register 6 (ram16k) \r
+#define AT91C_MATRIX_EBI (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (MATRIX) Slave 3 (ebi) Special Function Register\r
+#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE40) // (MATRIX) Slave Configuration Register 0 (ram96k) \r
+#define AT91C_MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0xFFFFEE9C) // (MATRIX) PRBS3 : usb_dev_hs\r
+#define AT91C_MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0xFFFFEE98) // (MATRIX) PRAS3 : usb_dev_hs\r
+#define AT91C_MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0xFFFFEE80) // (MATRIX) PRAS0 (ram0) \r
+#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE0C) // (MATRIX) Master Configuration Register 3 (ebi)\r
+#define AT91C_MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0xFFFFEE88) // (MATRIX) PRAS1 (ram1) \r
+#define AT91C_MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0xFFFFEE90) // (MATRIX) PRAS2 (ram2) \r
+#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE48) // (MATRIX) Slave Configuration Register 2 (hperiphs) \r
+#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0xFFFFEE14) // (MATRIX) Master Configuration Register 5 (mailbox) \r
+#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE04) // (MATRIX) Master Configuration Register 1 (rom) \r
+#define AT91C_MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA0) // (MATRIX) PRAS4 : ebi\r
+#define AT91C_MATRIX_MRCR (AT91_CAST(AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register \r
+#define AT91C_MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0xFFFFEE94) // (MATRIX) PRBS2 (ram2) \r
+#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE50) // (MATRIX) Slave Configuration Register 4 (bridge) \r
+#define AT91C_MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0xFFFFEF2C) // (MATRIX) Slave 7 (teak_prog) Special Function Register\r
+#define AT91C_MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0xFFFFEE8C) // (MATRIX) PRBS1 (ram1) \r
+// ========== Register definition for CCFG peripheral ========== \r
+#define AT91C_CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (CCFG) Version Register\r
+#define AT91C_CCFG_EBICSA (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register\r
+// ========== Register definition for PDC_DBGU peripheral ========== \r
+#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\r
+#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\r
+#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\r
+#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\r
+#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\r
+#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register\r
+#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\r
+#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\r
+#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\r
+#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\r
+// ========== Register definition for DBGU peripheral ========== \r
+#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register\r
+#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register\r
+#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register\r
+#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register\r
+#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register\r
+#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register\r
+#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register\r
+#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register\r
+#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register\r
+#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register\r
+#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register\r
+#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register\r
+// ========== Register definition for AIC peripheral ========== \r
+#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register\r
+#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register\r
+#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register\r
+#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)\r
+#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register\r
+#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register\r
+#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register\r
+#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register\r
+#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register\r
+#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register\r
+#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register\r
+#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register\r
+#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register\r
+#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register\r
+#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register\r
+#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register\r
+#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register\r
+#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register\r
+// ========== Register definition for PIOA peripheral ========== \r
+#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr\r
+#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register\r
+#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register\r
+#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register\r
+#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register\r
+#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register\r
+#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register\r
+#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register\r
+#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register\r
+#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register\r
+#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register\r
+#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register\r
+#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register\r
+#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register\r
+#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register\r
+#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register\r
+#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register\r
+#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register\r
+#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register\r
+#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register\r
+#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register\r
+#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register\r
+#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register\r
+#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register\r
+#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register\r
+#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register\r
+#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register\r
+#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register\r
+#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register\r
+// ========== Register definition for PIOB peripheral ========== \r
+#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register\r
+#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register\r
+#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register\r
+#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register\r
+#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register\r
+#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register\r
+#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register\r
+#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register\r
+#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register\r
+#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register\r
+#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register\r
+#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register\r
+#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register\r
+#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register\r
+#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register\r
+#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register\r
+#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr\r
+#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register\r
+#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register\r
+#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register\r
+#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register\r
+#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register\r
+#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register\r
+#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register\r
+#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register\r
+#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register\r
+#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register\r
+#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register\r
+#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register\r
+// ========== Register definition for PIOC peripheral ========== \r
+#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register\r
+#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register\r
+#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register\r
+#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register\r
+#define AT91C_PIOC_PSR (AT91_CAST(AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register\r
+#define AT91C_PIOC_PDR (AT91_CAST(AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register\r
+#define AT91C_PIOC_ODR (AT91_CAST(AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr\r
+#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF868) // (PIOC) Pull-up Status Register\r
+#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register\r
+#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register\r
+#define AT91C_PIOC_OER (AT91_CAST(AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register\r
+#define AT91C_PIOC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register\r
+#define AT91C_PIOC_ASR (AT91_CAST(AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register\r
+#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register\r
+#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register\r
+#define AT91C_PIOC_PER (AT91_CAST(AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register\r
+#define AT91C_PIOC_IDR (AT91_CAST(AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register\r
+#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register\r
+#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register\r
+#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register\r
+#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register\r
+#define AT91C_PIOC_BSR (AT91_CAST(AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register\r
+#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register\r
+#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register\r
+#define AT91C_PIOC_IER (AT91_CAST(AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register\r
+#define AT91C_PIOC_OSR (AT91_CAST(AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register\r
+#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register\r
+#define AT91C_PIOC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register\r
+#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register\r
+// ========== Register definition for EFC peripheral ========== \r
+#define AT91C_EFC_FVR (AT91_CAST(AT91_REG *) 0xFFFFFA10) // (EFC) EFC Flash Version Register\r
+#define AT91C_EFC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFA04) // (EFC) EFC Flash Command Register\r
+#define AT91C_EFC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFA00) // (EFC) EFC Flash Mode Register\r
+#define AT91C_EFC_FRR (AT91_CAST(AT91_REG *) 0xFFFFFA0C) // (EFC) EFC Flash Result Register\r
+#define AT91C_EFC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFA08) // (EFC) EFC Flash Status Register\r
+// ========== Register definition for CKGR peripheral ========== \r
+#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register\r
+#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register\r
+#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register\r
+#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register\r
+// ========== Register definition for PMC peripheral ========== \r
+#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\r
+#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register\r
+#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register\r
+#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register\r
+#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\r
+#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register\r
+#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register\r
+#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register\r
+#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register\r
+#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register\r
+#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register\r
+#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register\r
+#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register\r
+#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register\r
+#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register\r
+#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register\r
+// ========== Register definition for RSTC peripheral ========== \r
+#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register\r
+#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register\r
+#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register\r
+// ========== Register definition for SHDWC peripheral ========== \r
+#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register\r
+#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register\r
+#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register\r
+// ========== Register definition for RTTC peripheral ========== \r
+#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register\r
+#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register\r
+#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register\r
+#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register\r
+// ========== Register definition for PITC peripheral ========== \r
+#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register\r
+#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register\r
+#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register\r
+#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register\r
+// ========== Register definition for WDTC peripheral ========== \r
+#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register\r
+#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register\r
+#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register\r
+#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C\r
+#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B\r
+#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register\r
+#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A\r
+#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value\r
+#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B\r
+#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register\r
+#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register\r
+#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A\r
+#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C\r
+#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register\r
+#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value\r
+#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A\r
+#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B\r
+#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register\r
+#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C\r
+#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register\r
+// ========== Register definition for TC3 peripheral ========== \r
+#define AT91C_TC3_IER (AT91_CAST(AT91_REG *) 0xFFFDC024) // (TC3) Interrupt Enable Register\r
+#define AT91C_TC3_RB (AT91_CAST(AT91_REG *) 0xFFFDC018) // (TC3) Register B\r
+#define AT91C_TC3_CMR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC3_RC (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (TC3) Register C\r
+#define AT91C_TC3_CCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (TC3) Channel Control Register\r
+#define AT91C_TC3_SR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (TC3) Status Register\r
+#define AT91C_TC3_CV (AT91_CAST(AT91_REG *) 0xFFFDC010) // (TC3) Counter Value\r
+#define AT91C_TC3_RA (AT91_CAST(AT91_REG *) 0xFFFDC014) // (TC3) Register A\r
+#define AT91C_TC3_IDR (AT91_CAST(AT91_REG *) 0xFFFDC028) // (TC3) Interrupt Disable Register\r
+#define AT91C_TC3_IMR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (TC3) Interrupt Mask Register\r
+// ========== Register definition for TC4 peripheral ========== \r
+#define AT91C_TC4_CMR (AT91_CAST(AT91_REG *) 0xFFFDC044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC4_RC (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (TC4) Register C\r
+#define AT91C_TC4_SR (AT91_CAST(AT91_REG *) 0xFFFDC060) // (TC4) Status Register\r
+#define AT91C_TC4_RB (AT91_CAST(AT91_REG *) 0xFFFDC058) // (TC4) Register B\r
+#define AT91C_TC4_IER (AT91_CAST(AT91_REG *) 0xFFFDC064) // (TC4) Interrupt Enable Register\r
+#define AT91C_TC4_CV (AT91_CAST(AT91_REG *) 0xFFFDC050) // (TC4) Counter Value\r
+#define AT91C_TC4_RA (AT91_CAST(AT91_REG *) 0xFFFDC054) // (TC4) Register A\r
+#define AT91C_TC4_IDR (AT91_CAST(AT91_REG *) 0xFFFDC068) // (TC4) Interrupt Disable Register\r
+#define AT91C_TC4_IMR (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (TC4) Interrupt Mask Register\r
+#define AT91C_TC4_CCR (AT91_CAST(AT91_REG *) 0xFFFDC040) // (TC4) Channel Control Register\r
+// ========== Register definition for TC5 peripheral ========== \r
+#define AT91C_TC5_RB (AT91_CAST(AT91_REG *) 0xFFFDC098) // (TC5) Register B\r
+#define AT91C_TC5_RA (AT91_CAST(AT91_REG *) 0xFFFDC094) // (TC5) Register A\r
+#define AT91C_TC5_CV (AT91_CAST(AT91_REG *) 0xFFFDC090) // (TC5) Counter Value\r
+#define AT91C_TC5_CCR (AT91_CAST(AT91_REG *) 0xFFFDC080) // (TC5) Channel Control Register\r
+#define AT91C_TC5_SR (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (TC5) Status Register\r
+#define AT91C_TC5_IER (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (TC5) Interrupt Enable Register\r
+#define AT91C_TC5_IDR (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (TC5) Interrupt Disable Register\r
+#define AT91C_TC5_RC (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (TC5) Register C\r
+#define AT91C_TC5_IMR (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (TC5) Interrupt Mask Register\r
+#define AT91C_TC5_CMR (AT91_CAST(AT91_REG *) 0xFFFDC084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode)\r
+// ========== Register definition for TCB0 peripheral ========== \r
+#define AT91C_TCB0_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register\r
+#define AT91C_TCB0_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register\r
+// ========== Register definition for TCB1 peripheral ========== \r
+#define AT91C_TCB1_BCR (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (TCB1) TC Block Control Register\r
+#define AT91C_TCB1_BMR (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (TCB1) TC Block Mode Register\r
+// ========== Register definition for PDC_MCI peripheral ========== \r
+#define AT91C_MCI_RNCR (AT91_CAST(AT91_REG *) 0xFFFA8114) // (PDC_MCI) Receive Next Counter Register\r
+#define AT91C_MCI_TCR (AT91_CAST(AT91_REG *) 0xFFFA810C) // (PDC_MCI) Transmit Counter Register\r
+#define AT91C_MCI_RCR (AT91_CAST(AT91_REG *) 0xFFFA8104) // (PDC_MCI) Receive Counter Register\r
+#define AT91C_MCI_TNPR (AT91_CAST(AT91_REG *) 0xFFFA8118) // (PDC_MCI) Transmit Next Pointer Register\r
+#define AT91C_MCI_RNPR (AT91_CAST(AT91_REG *) 0xFFFA8110) // (PDC_MCI) Receive Next Pointer Register\r
+#define AT91C_MCI_RPR (AT91_CAST(AT91_REG *) 0xFFFA8100) // (PDC_MCI) Receive Pointer Register\r
+#define AT91C_MCI_TNCR (AT91_CAST(AT91_REG *) 0xFFFA811C) // (PDC_MCI) Transmit Next Counter Register\r
+#define AT91C_MCI_TPR (AT91_CAST(AT91_REG *) 0xFFFA8108) // (PDC_MCI) Transmit Pointer Register\r
+#define AT91C_MCI_PTSR (AT91_CAST(AT91_REG *) 0xFFFA8124) // (PDC_MCI) PDC Transfer Status Register\r
+#define AT91C_MCI_PTCR (AT91_CAST(AT91_REG *) 0xFFFA8120) // (PDC_MCI) PDC Transfer Control Register\r
+// ========== Register definition for MCI peripheral ========== \r
+#define AT91C_MCI_RDR (AT91_CAST(AT91_REG *) 0xFFFA8030) // (MCI) MCI Receive Data Register\r
+#define AT91C_MCI_CMDR (AT91_CAST(AT91_REG *) 0xFFFA8014) // (MCI) MCI Command Register\r
+#define AT91C_MCI_VR (AT91_CAST(AT91_REG *) 0xFFFA80FC) // (MCI) MCI Version Register\r
+#define AT91C_MCI_IDR (AT91_CAST(AT91_REG *) 0xFFFA8048) // (MCI) MCI Interrupt Disable Register\r
+#define AT91C_MCI_DTOR (AT91_CAST(AT91_REG *) 0xFFFA8008) // (MCI) MCI Data Timeout Register\r
+#define AT91C_MCI_TDR (AT91_CAST(AT91_REG *) 0xFFFA8034) // (MCI) MCI Transmit Data Register\r
+#define AT91C_MCI_IER (AT91_CAST(AT91_REG *) 0xFFFA8044) // (MCI) MCI Interrupt Enable Register\r
+#define AT91C_MCI_BLKR (AT91_CAST(AT91_REG *) 0xFFFA8018) // (MCI) MCI Block Register\r
+#define AT91C_MCI_MR (AT91_CAST(AT91_REG *) 0xFFFA8004) // (MCI) MCI Mode Register\r
+#define AT91C_MCI_IMR (AT91_CAST(AT91_REG *) 0xFFFA804C) // (MCI) MCI Interrupt Mask Register\r
+#define AT91C_MCI_CR (AT91_CAST(AT91_REG *) 0xFFFA8000) // (MCI) MCI Control Register\r
+#define AT91C_MCI_ARGR (AT91_CAST(AT91_REG *) 0xFFFA8010) // (MCI) MCI Argument Register\r
+#define AT91C_MCI_SDCR (AT91_CAST(AT91_REG *) 0xFFFA800C) // (MCI) MCI SD Card Register\r
+#define AT91C_MCI_SR (AT91_CAST(AT91_REG *) 0xFFFA8040) // (MCI) MCI Status Register\r
+#define AT91C_MCI_RSPR (AT91_CAST(AT91_REG *) 0xFFFA8020) // (MCI) MCI Response Register\r
+// ========== Register definition for PDC_TWI0 peripheral ========== \r
+#define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFAC124) // (PDC_TWI0) PDC Transfer Status Register\r
+#define AT91C_TWI0_RPR (AT91_CAST(AT91_REG *) 0xFFFAC100) // (PDC_TWI0) Receive Pointer Register\r
+#define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFAC114) // (PDC_TWI0) Receive Next Counter Register\r
+#define AT91C_TWI0_RCR (AT91_CAST(AT91_REG *) 0xFFFAC104) // (PDC_TWI0) Receive Counter Register\r
+#define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFAC120) // (PDC_TWI0) PDC Transfer Control Register\r
+#define AT91C_TWI0_TPR (AT91_CAST(AT91_REG *) 0xFFFAC108) // (PDC_TWI0) Transmit Pointer Register\r
+#define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFAC110) // (PDC_TWI0) Receive Next Pointer Register\r
+#define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFAC118) // (PDC_TWI0) Transmit Next Pointer Register\r
+#define AT91C_TWI0_TCR (AT91_CAST(AT91_REG *) 0xFFFAC10C) // (PDC_TWI0) Transmit Counter Register\r
+#define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFAC11C) // (PDC_TWI0) Transmit Next Counter Register\r
+// ========== Register definition for TWI0 peripheral ========== \r
+#define AT91C_TWI0_THR (AT91_CAST(AT91_REG *) 0xFFFAC034) // (TWI0) Transmit Holding Register\r
+#define AT91C_TWI0_IDR (AT91_CAST(AT91_REG *) 0xFFFAC028) // (TWI0) Interrupt Disable Register\r
+#define AT91C_TWI0_SMR (AT91_CAST(AT91_REG *) 0xFFFAC008) // (TWI0) Slave Mode Register\r
+#define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *) 0xFFFAC010) // (TWI0) Clock Waveform Generator Register\r
+#define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *) 0xFFFAC00C) // (TWI0) Internal Address Register\r
+#define AT91C_TWI0_RHR (AT91_CAST(AT91_REG *) 0xFFFAC030) // (TWI0) Receive Holding Register\r
+#define AT91C_TWI0_IER (AT91_CAST(AT91_REG *) 0xFFFAC024) // (TWI0) Interrupt Enable Register\r
+#define AT91C_TWI0_MMR (AT91_CAST(AT91_REG *) 0xFFFAC004) // (TWI0) Master Mode Register\r
+#define AT91C_TWI0_SR (AT91_CAST(AT91_REG *) 0xFFFAC020) // (TWI0) Status Register\r
+#define AT91C_TWI0_IMR (AT91_CAST(AT91_REG *) 0xFFFAC02C) // (TWI0) Interrupt Mask Register\r
+#define AT91C_TWI0_CR (AT91_CAST(AT91_REG *) 0xFFFAC000) // (TWI0) Control Register\r
+// ========== Register definition for PDC_TWI1 peripheral ========== \r
+#define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_TWI1) PDC Transfer Status Register\r
+#define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_TWI1) PDC Transfer Control Register\r
+#define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_TWI1) Transmit Next Pointer Register\r
+#define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_TWI1) Transmit Next Counter Register\r
+#define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_TWI1) Receive Next Pointer Register\r
+#define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_TWI1) Receive Next Counter Register\r
+#define AT91C_TWI1_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_TWI1) Receive Pointer Register\r
+#define AT91C_TWI1_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_TWI1) Transmit Counter Register\r
+#define AT91C_TWI1_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_TWI1) Transmit Pointer Register\r
+#define AT91C_TWI1_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_TWI1) Receive Counter Register\r
+// ========== Register definition for TWI1 peripheral ========== \r
+#define AT91C_TWI1_RHR (AT91_CAST(AT91_REG *) 0xFFFD8030) // (TWI1) Receive Holding Register\r
+#define AT91C_TWI1_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (TWI1) Interrupt Enable Register\r
+#define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *) 0xFFFD8010) // (TWI1) Clock Waveform Generator Register\r
+#define AT91C_TWI1_MMR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (TWI1) Master Mode Register\r
+#define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *) 0xFFFD800C) // (TWI1) Internal Address Register\r
+#define AT91C_TWI1_THR (AT91_CAST(AT91_REG *) 0xFFFD8034) // (TWI1) Transmit Holding Register\r
+#define AT91C_TWI1_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (TWI1) Interrupt Mask Register\r
+#define AT91C_TWI1_SR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (TWI1) Status Register\r
+#define AT91C_TWI1_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (TWI1) Interrupt Disable Register\r
+#define AT91C_TWI1_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (TWI1) Control Register\r
+#define AT91C_TWI1_SMR (AT91_CAST(AT91_REG *) 0xFFFD8008) // (TWI1) Slave Mode Register\r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFB010C) // (PDC_US0) Transmit Counter Register\r
+#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFB0120) // (PDC_US0) PDC Transfer Control Register\r
+#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFB0114) // (PDC_US0) Receive Next Counter Register\r
+#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFB0124) // (PDC_US0) PDC Transfer Status Register\r
+#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFB011C) // (PDC_US0) Transmit Next Counter Register\r
+#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFB0110) // (PDC_US0) Receive Next Pointer Register\r
+#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFB0104) // (PDC_US0) Receive Counter Register\r
+#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFB0108) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register\r
+#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFB0100) // (PDC_US0) Receive Pointer Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFB0044) // (US0) Nb Errors Register\r
+#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFB0008) // (US0) Interrupt Enable Register\r
+#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFB0000) // (US0) Control Register\r
+#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (US0) Transmitter Holding Register\r
+#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (US0) Channel Status Register\r
+#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFB0024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFB0028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFB000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFB0004) // (US0) Mode Register\r
+#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFB004C) // (US0) IRDA_FILTER Register\r
+#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFB0040) // (US0) FI_DI_Ratio Register\r
+#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFB0010) // (US0) Interrupt Mask Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFB4120) // (PDC_US1) PDC Transfer Control Register\r
+#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFB4104) // (PDC_US1) Receive Counter Register\r
+#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFB4100) // (PDC_US1) Receive Pointer Register\r
+#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFB4124) // (PDC_US1) PDC Transfer Status Register\r
+#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFB4108) // (PDC_US1) Transmit Pointer Register\r
+#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFB410C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFB4110) // (PDC_US1) Receive Next Pointer Register\r
+#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFB411C) // (PDC_US1) Transmit Next Counter Register\r
+#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFB4114) // (PDC_US1) Receive Next Counter Register\r
+#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFB401C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFB4028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFB4020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFB400C) // (US1) Interrupt Disable Register\r
+#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFB4004) // (US1) Mode Register\r
+#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFB4024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFB4000) // (US1) Control Register\r
+#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFB4010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFB4040) // (US1) FI_DI_Ratio Register\r
+#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFB4018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFB4008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFB4014) // (US1) Channel Status Register\r
+#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFB404C) // (US1) IRDA_FILTER Register\r
+#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFB4044) // (US1) Nb Errors Register\r
+// ========== Register definition for PDC_US2 peripheral ========== \r
+#define AT91C_US2_TNCR (AT91_CAST(AT91_REG *) 0xFFFB811C) // (PDC_US2) Transmit Next Counter Register\r
+#define AT91C_US2_RNCR (AT91_CAST(AT91_REG *) 0xFFFB8114) // (PDC_US2) Receive Next Counter Register\r
+#define AT91C_US2_TNPR (AT91_CAST(AT91_REG *) 0xFFFB8118) // (PDC_US2) Transmit Next Pointer Register\r
+#define AT91C_US2_PTCR (AT91_CAST(AT91_REG *) 0xFFFB8120) // (PDC_US2) PDC Transfer Control Register\r
+#define AT91C_US2_TCR (AT91_CAST(AT91_REG *) 0xFFFB810C) // (PDC_US2) Transmit Counter Register\r
+#define AT91C_US2_RPR (AT91_CAST(AT91_REG *) 0xFFFB8100) // (PDC_US2) Receive Pointer Register\r
+#define AT91C_US2_TPR (AT91_CAST(AT91_REG *) 0xFFFB8108) // (PDC_US2) Transmit Pointer Register\r
+#define AT91C_US2_RCR (AT91_CAST(AT91_REG *) 0xFFFB8104) // (PDC_US2) Receive Counter Register\r
+#define AT91C_US2_PTSR (AT91_CAST(AT91_REG *) 0xFFFB8124) // (PDC_US2) PDC Transfer Status Register\r
+#define AT91C_US2_RNPR (AT91_CAST(AT91_REG *) 0xFFFB8110) // (PDC_US2) Receive Next Pointer Register\r
+// ========== Register definition for US2 peripheral ========== \r
+#define AT91C_US2_RTOR (AT91_CAST(AT91_REG *) 0xFFFB8024) // (US2) Receiver Time-out Register\r
+#define AT91C_US2_CSR (AT91_CAST(AT91_REG *) 0xFFFB8014) // (US2) Channel Status Register\r
+#define AT91C_US2_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (US2) Control Register\r
+#define AT91C_US2_BRGR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (US2) Baud Rate Generator Register\r
+#define AT91C_US2_NER (AT91_CAST(AT91_REG *) 0xFFFB8044) // (US2) Nb Errors Register\r
+#define AT91C_US2_FIDI (AT91_CAST(AT91_REG *) 0xFFFB8040) // (US2) FI_DI_Ratio Register\r
+#define AT91C_US2_TTGR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (US2) Transmitter Time-guard Register\r
+#define AT91C_US2_RHR (AT91_CAST(AT91_REG *) 0xFFFB8018) // (US2) Receiver Holding Register\r
+#define AT91C_US2_IDR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (US2) Interrupt Disable Register\r
+#define AT91C_US2_THR (AT91_CAST(AT91_REG *) 0xFFFB801C) // (US2) Transmitter Holding Register\r
+#define AT91C_US2_MR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (US2) Mode Register\r
+#define AT91C_US2_IMR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (US2) Interrupt Mask Register\r
+#define AT91C_US2_IF (AT91_CAST(AT91_REG *) 0xFFFB804C) // (US2) IRDA_FILTER Register\r
+#define AT91C_US2_IER (AT91_CAST(AT91_REG *) 0xFFFB8008) // (US2) Interrupt Enable Register\r
+// ========== Register definition for PDC_US3 peripheral ========== \r
+#define AT91C_US3_RNPR (AT91_CAST(AT91_REG *) 0xFFFD0110) // (PDC_US3) Receive Next Pointer Register\r
+#define AT91C_US3_RNCR (AT91_CAST(AT91_REG *) 0xFFFD0114) // (PDC_US3) Receive Next Counter Register\r
+#define AT91C_US3_PTSR (AT91_CAST(AT91_REG *) 0xFFFD0124) // (PDC_US3) PDC Transfer Status Register\r
+#define AT91C_US3_PTCR (AT91_CAST(AT91_REG *) 0xFFFD0120) // (PDC_US3) PDC Transfer Control Register\r
+#define AT91C_US3_TCR (AT91_CAST(AT91_REG *) 0xFFFD010C) // (PDC_US3) Transmit Counter Register\r
+#define AT91C_US3_TNPR (AT91_CAST(AT91_REG *) 0xFFFD0118) // (PDC_US3) Transmit Next Pointer Register\r
+#define AT91C_US3_RCR (AT91_CAST(AT91_REG *) 0xFFFD0104) // (PDC_US3) Receive Counter Register\r
+#define AT91C_US3_TPR (AT91_CAST(AT91_REG *) 0xFFFD0108) // (PDC_US3) Transmit Pointer Register\r
+#define AT91C_US3_TNCR (AT91_CAST(AT91_REG *) 0xFFFD011C) // (PDC_US3) Transmit Next Counter Register\r
+#define AT91C_US3_RPR (AT91_CAST(AT91_REG *) 0xFFFD0100) // (PDC_US3) Receive Pointer Register\r
+// ========== Register definition for US3 peripheral ========== \r
+#define AT91C_US3_NER (AT91_CAST(AT91_REG *) 0xFFFD0044) // (US3) Nb Errors Register\r
+#define AT91C_US3_RTOR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (US3) Receiver Time-out Register\r
+#define AT91C_US3_IDR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (US3) Interrupt Disable Register\r
+#define AT91C_US3_MR (AT91_CAST(AT91_REG *) 0xFFFD0004) // (US3) Mode Register\r
+#define AT91C_US3_FIDI (AT91_CAST(AT91_REG *) 0xFFFD0040) // (US3) FI_DI_Ratio Register\r
+#define AT91C_US3_BRGR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (US3) Baud Rate Generator Register\r
+#define AT91C_US3_THR (AT91_CAST(AT91_REG *) 0xFFFD001C) // (US3) Transmitter Holding Register\r
+#define AT91C_US3_CR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (US3) Control Register\r
+#define AT91C_US3_IF (AT91_CAST(AT91_REG *) 0xFFFD004C) // (US3) IRDA_FILTER Register\r
+#define AT91C_US3_IER (AT91_CAST(AT91_REG *) 0xFFFD0008) // (US3) Interrupt Enable Register\r
+#define AT91C_US3_TTGR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (US3) Transmitter Time-guard Register\r
+#define AT91C_US3_RHR (AT91_CAST(AT91_REG *) 0xFFFD0018) // (US3) Receiver Holding Register\r
+#define AT91C_US3_IMR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (US3) Interrupt Mask Register\r
+#define AT91C_US3_CSR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (US3) Channel Status Register\r
+// ========== Register definition for PDC_US4 peripheral ========== \r
+#define AT91C_US4_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_US4) Transmit Next Counter Register\r
+#define AT91C_US4_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_US4) Receive Pointer Register\r
+#define AT91C_US4_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_US4) Receive Next Counter Register\r
+#define AT91C_US4_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_US4) Transmit Pointer Register\r
+#define AT91C_US4_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_US4) PDC Transfer Control Register\r
+#define AT91C_US4_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_US4) Transmit Counter Register\r
+#define AT91C_US4_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_US4) Receive Counter Register\r
+#define AT91C_US4_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_US4) Receive Next Pointer Register\r
+#define AT91C_US4_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_US4) Transmit Next Pointer Register\r
+#define AT91C_US4_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_US4) PDC Transfer Status Register\r
+// ========== Register definition for US4 peripheral ========== \r
+#define AT91C_US4_BRGR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (US4) Baud Rate Generator Register\r
+#define AT91C_US4_THR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (US4) Transmitter Holding Register\r
+#define AT91C_US4_RTOR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (US4) Receiver Time-out Register\r
+#define AT91C_US4_IMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (US4) Interrupt Mask Register\r
+#define AT91C_US4_NER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (US4) Nb Errors Register\r
+#define AT91C_US4_TTGR (AT91_CAST(AT91_REG *) 0xFFFD4028) // (US4) Transmitter Time-guard Register\r
+#define AT91C_US4_FIDI (AT91_CAST(AT91_REG *) 0xFFFD4040) // (US4) FI_DI_Ratio Register\r
+#define AT91C_US4_MR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (US4) Mode Register\r
+#define AT91C_US4_IER (AT91_CAST(AT91_REG *) 0xFFFD4008) // (US4) Interrupt Enable Register\r
+#define AT91C_US4_RHR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (US4) Receiver Holding Register\r
+#define AT91C_US4_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (US4) Control Register\r
+#define AT91C_US4_IF (AT91_CAST(AT91_REG *) 0xFFFD404C) // (US4) IRDA_FILTER Register\r
+#define AT91C_US4_IDR (AT91_CAST(AT91_REG *) 0xFFFD400C) // (US4) Interrupt Disable Register\r
+#define AT91C_US4_CSR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (US4) Channel Status Register\r
+// ========== Register definition for PDC_SSC0 peripheral ========== \r
+#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 0xFFFBC118) // (PDC_SSC0) Transmit Next Pointer Register\r
+#define AT91C_SSC0_TCR (AT91_CAST(AT91_REG *) 0xFFFBC10C) // (PDC_SSC0) Transmit Counter Register\r
+#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 0xFFFBC114) // (PDC_SSC0) Receive Next Counter Register\r
+#define AT91C_SSC0_RPR (AT91_CAST(AT91_REG *) 0xFFFBC100) // (PDC_SSC0) Receive Pointer Register\r
+#define AT91C_SSC0_TPR (AT91_CAST(AT91_REG *) 0xFFFBC108) // (PDC_SSC0) Transmit Pointer Register\r
+#define AT91C_SSC0_RCR (AT91_CAST(AT91_REG *) 0xFFFBC104) // (PDC_SSC0) Receive Counter Register\r
+#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 0xFFFBC110) // (PDC_SSC0) Receive Next Pointer Register\r
+#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 0xFFFBC120) // (PDC_SSC0) PDC Transfer Control Register\r
+#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 0xFFFBC11C) // (PDC_SSC0) Transmit Next Counter Register\r
+#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 0xFFFBC124) // (PDC_SSC0) PDC Transfer Status Register\r
+// ========== Register definition for SSC0 peripheral ========== \r
+#define AT91C_SSC0_IMR (AT91_CAST(AT91_REG *) 0xFFFBC04C) // (SSC0) Interrupt Mask Register\r
+#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 0xFFFBC014) // (SSC0) Receive Frame Mode Register\r
+#define AT91C_SSC0_CR (AT91_CAST(AT91_REG *) 0xFFFBC000) // (SSC0) Control Register\r
+#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 0xFFFBC01C) // (SSC0) Transmit Frame Mode Register\r
+#define AT91C_SSC0_CMR (AT91_CAST(AT91_REG *) 0xFFFBC004) // (SSC0) Clock Mode Register\r
+#define AT91C_SSC0_IER (AT91_CAST(AT91_REG *) 0xFFFBC044) // (SSC0) Interrupt Enable Register\r
+#define AT91C_SSC0_RHR (AT91_CAST(AT91_REG *) 0xFFFBC020) // (SSC0) Receive Holding Register\r
+#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 0xFFFBC010) // (SSC0) Receive Clock ModeRegister\r
+#define AT91C_SSC0_SR (AT91_CAST(AT91_REG *) 0xFFFBC040) // (SSC0) Status Register\r
+#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 0xFFFBC030) // (SSC0) Receive Sync Holding Register\r
+#define AT91C_SSC0_THR (AT91_CAST(AT91_REG *) 0xFFFBC024) // (SSC0) Transmit Holding Register\r
+#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 0xFFFBC018) // (SSC0) Transmit Clock Mode Register\r
+#define AT91C_SSC0_IDR (AT91_CAST(AT91_REG *) 0xFFFBC048) // (SSC0) Interrupt Disable Register\r
+#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 0xFFFBC034) // (SSC0) Transmit Sync Holding Register\r
+// ========== Register definition for PDC_SPI0 peripheral ========== \r
+#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC8120) // (PDC_SPI0) PDC Transfer Control Register\r
+#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFC810C) // (PDC_SPI0) Transmit Counter Register\r
+#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFC8100) // (PDC_SPI0) Receive Pointer Register\r
+#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFC8108) // (PDC_SPI0) Transmit Pointer Register\r
+#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC8124) // (PDC_SPI0) PDC Transfer Status Register\r
+#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC8114) // (PDC_SPI0) Receive Next Counter Register\r
+#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC8118) // (PDC_SPI0) Transmit Next Pointer Register\r
+#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFC8104) // (PDC_SPI0) Receive Counter Register\r
+#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC8110) // (PDC_SPI0) Receive Next Pointer Register\r
+#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC811C) // (PDC_SPI0) Transmit Next Counter Register\r
+// ========== Register definition for SPI0 peripheral ========== \r
+#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFC8018) // (SPI0) Interrupt Disable Register\r
+#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFC800C) // (SPI0) Transmit Data Register\r
+#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFC8010) // (SPI0) Status Register\r
+#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFC8000) // (SPI0) Control Register\r
+#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFC8030) // (SPI0) Chip Select Register\r
+#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFC8008) // (SPI0) Receive Data Register\r
+#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFC8004) // (SPI0) Mode Register\r
+#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFC8014) // (SPI0) Interrupt Enable Register\r
+#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFC801C) // (SPI0) Interrupt Mask Register\r
+// ========== Register definition for PDC_SPI1 peripheral ========== \r
+#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFCC120) // (PDC_SPI1) PDC Transfer Control Register\r
+#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFCC110) // (PDC_SPI1) Receive Next Pointer Register\r
+#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFCC104) // (PDC_SPI1) Receive Counter Register\r
+#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFCC108) // (PDC_SPI1) Transmit Pointer Register\r
+#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFCC124) // (PDC_SPI1) PDC Transfer Status Register\r
+#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFCC11C) // (PDC_SPI1) Transmit Next Counter Register\r
+#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFCC100) // (PDC_SPI1) Receive Pointer Register\r
+#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFCC10C) // (PDC_SPI1) Transmit Counter Register\r
+#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFCC114) // (PDC_SPI1) Receive Next Counter Register\r
+#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFCC118) // (PDC_SPI1) Transmit Next Pointer Register\r
+// ========== Register definition for SPI1 peripheral ========== \r
+#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFCC014) // (SPI1) Interrupt Enable Register\r
+#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFCC008) // (SPI1) Receive Data Register\r
+#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFCC010) // (SPI1) Status Register\r
+#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (SPI1) Interrupt Mask Register\r
+#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (SPI1) Transmit Data Register\r
+#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (SPI1) Interrupt Disable Register\r
+#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFCC030) // (SPI1) Chip Select Register\r
+#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (SPI1) Control Register\r
+#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFCC004) // (SPI1) Mode Register\r
+// ========== Register definition for PDC_ADC peripheral ========== \r
+#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_ADC) PDC Transfer Control Register\r
+#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_ADC) Transmit Pointer Register\r
+#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_ADC) Transmit Counter Register\r
+#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_ADC) Receive Counter Register\r
+#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_ADC) PDC Transfer Status Register\r
+#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_ADC) Receive Next Pointer Register\r
+#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_ADC) Receive Pointer Register\r
+#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_ADC) Transmit Next Counter Register\r
+#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_ADC) Receive Next Counter Register\r
+#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_ADC) Transmit Next Pointer Register\r
+// ========== Register definition for ADC peripheral ========== \r
+#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFE0014) // (ADC) ADC Channel Disable Register\r
+#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFE003C) // (ADC) ADC Channel Data Register 3\r
+#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (ADC) ADC Control Register\r
+#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFE002C) // (ADC) ADC Interrupt Mask Register\r
+#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFE0038) // (ADC) ADC Channel Data Register 2\r
+#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (ADC) ADC Status Register\r
+#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFE0024) // (ADC) ADC Interrupt Enable Register\r
+#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFE004C) // (ADC) ADC Channel Data Register 7\r
+#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFE0030) // (ADC) ADC Channel Data Register 0\r
+#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFE0044) // (ADC) ADC Channel Data Register 5\r
+#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFE0040) // (ADC) ADC Channel Data Register 4\r
+#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFE0010) // (ADC) ADC Channel Enable Register\r
+#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (ADC) ADC Channel Status Register\r
+#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (ADC) ADC Mode Register\r
+#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFE0048) // (ADC) ADC Channel Data Register 6\r
+#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFE0020) // (ADC) ADC Last Converted Data Register\r
+#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFE0034) // (ADC) ADC Channel Data Register 1\r
+#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFE0028) // (ADC) ADC Interrupt Disable Register\r
+// ========== Register definition for EMACB peripheral ========== \r
+#define AT91C_EMACB_USRIO (AT91_CAST(AT91_REG *) 0xFFFC40C0) // (EMACB) USER Input/Output Register\r
+#define AT91C_EMACB_RSE (AT91_CAST(AT91_REG *) 0xFFFC4074) // (EMACB) Receive Symbol Errors Register\r
+#define AT91C_EMACB_SCF (AT91_CAST(AT91_REG *) 0xFFFC4044) // (EMACB) Single Collision Frame Register\r
+#define AT91C_EMACB_STE (AT91_CAST(AT91_REG *) 0xFFFC4084) // (EMACB) SQE Test Error Register\r
+#define AT91C_EMACB_SA1H (AT91_CAST(AT91_REG *) 0xFFFC409C) // (EMACB) Specific Address 1 Top, Last 2 bytes\r
+#define AT91C_EMACB_ROV (AT91_CAST(AT91_REG *) 0xFFFC4070) // (EMACB) Receive Overrun Errors Register\r
+#define AT91C_EMACB_TBQP (AT91_CAST(AT91_REG *) 0xFFFC401C) // (EMACB) Transmit Buffer Queue Pointer\r
+#define AT91C_EMACB_IMR (AT91_CAST(AT91_REG *) 0xFFFC4030) // (EMACB) Interrupt Mask Register\r
+#define AT91C_EMACB_IER (AT91_CAST(AT91_REG *) 0xFFFC4028) // (EMACB) Interrupt Enable Register\r
+#define AT91C_EMACB_REV (AT91_CAST(AT91_REG *) 0xFFFC40FC) // (EMACB) Revision Register\r
+#define AT91C_EMACB_SA3L (AT91_CAST(AT91_REG *) 0xFFFC40A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes\r
+#define AT91C_EMACB_ELE (AT91_CAST(AT91_REG *) 0xFFFC4078) // (EMACB) Excessive Length Errors Register\r
+#define AT91C_EMACB_HRT (AT91_CAST(AT91_REG *) 0xFFFC4094) // (EMACB) Hash Address Top[63:32]\r
+#define AT91C_EMACB_SA2L (AT91_CAST(AT91_REG *) 0xFFFC40A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes\r
+#define AT91C_EMACB_RRE (AT91_CAST(AT91_REG *) 0xFFFC406C) // (EMACB) Receive Ressource Error Register\r
+#define AT91C_EMACB_FRO (AT91_CAST(AT91_REG *) 0xFFFC404C) // (EMACB) Frames Received OK Register\r
+#define AT91C_EMACB_TPQ (AT91_CAST(AT91_REG *) 0xFFFC40BC) // (EMACB) Transmit Pause Quantum Register\r
+#define AT91C_EMACB_ISR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (EMACB) Interrupt Status Register\r
+#define AT91C_EMACB_TSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (EMACB) Transmit Status Register\r
+#define AT91C_EMACB_RLE (AT91_CAST(AT91_REG *) 0xFFFC4088) // (EMACB) Receive Length Field Mismatch Register\r
+#define AT91C_EMACB_USF (AT91_CAST(AT91_REG *) 0xFFFC4080) // (EMACB) Undersize Frames Register\r
+#define AT91C_EMACB_WOL (AT91_CAST(AT91_REG *) 0xFFFC40C4) // (EMACB) Wake On LAN Register\r
+#define AT91C_EMACB_TPF (AT91_CAST(AT91_REG *) 0xFFFC408C) // (EMACB) Transmitted Pause Frames Register\r
+#define AT91C_EMACB_PTR (AT91_CAST(AT91_REG *) 0xFFFC4038) // (EMACB) Pause Time Register\r
+#define AT91C_EMACB_TUND (AT91_CAST(AT91_REG *) 0xFFFC4064) // (EMACB) Transmit Underrun Error Register\r
+#define AT91C_EMACB_MAN (AT91_CAST(AT91_REG *) 0xFFFC4034) // (EMACB) PHY Maintenance Register\r
+#define AT91C_EMACB_RJA (AT91_CAST(AT91_REG *) 0xFFFC407C) // (EMACB) Receive Jabbers Register\r
+#define AT91C_EMACB_SA4L (AT91_CAST(AT91_REG *) 0xFFFC40B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes\r
+#define AT91C_EMACB_CSE (AT91_CAST(AT91_REG *) 0xFFFC4068) // (EMACB) Carrier Sense Error Register\r
+#define AT91C_EMACB_HRB (AT91_CAST(AT91_REG *) 0xFFFC4090) // (EMACB) Hash Address Bottom[31:0]\r
+#define AT91C_EMACB_ALE (AT91_CAST(AT91_REG *) 0xFFFC4054) // (EMACB) Alignment Error Register\r
+#define AT91C_EMACB_SA1L (AT91_CAST(AT91_REG *) 0xFFFC4098) // (EMACB) Specific Address 1 Bottom, First 4 bytes\r
+#define AT91C_EMACB_NCR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (EMACB) Network Control Register\r
+#define AT91C_EMACB_FTO (AT91_CAST(AT91_REG *) 0xFFFC4040) // (EMACB) Frames Transmitted OK Register\r
+#define AT91C_EMACB_ECOL (AT91_CAST(AT91_REG *) 0xFFFC4060) // (EMACB) Excessive Collision Register\r
+#define AT91C_EMACB_DTF (AT91_CAST(AT91_REG *) 0xFFFC4058) // (EMACB) Deferred Transmission Frame Register\r
+#define AT91C_EMACB_SA4H (AT91_CAST(AT91_REG *) 0xFFFC40B4) // (EMACB) Specific Address 4 Top, Last 2 bytes\r
+#define AT91C_EMACB_FCSE (AT91_CAST(AT91_REG *) 0xFFFC4050) // (EMACB) Frame Check Sequence Error Register\r
+#define AT91C_EMACB_TID (AT91_CAST(AT91_REG *) 0xFFFC40B8) // (EMACB) Type ID Checking Register\r
+#define AT91C_EMACB_PFR (AT91_CAST(AT91_REG *) 0xFFFC403C) // (EMACB) Pause Frames received Register\r
+#define AT91C_EMACB_IDR (AT91_CAST(AT91_REG *) 0xFFFC402C) // (EMACB) Interrupt Disable Register\r
+#define AT91C_EMACB_SA3H (AT91_CAST(AT91_REG *) 0xFFFC40AC) // (EMACB) Specific Address 3 Top, Last 2 bytes\r
+#define AT91C_EMACB_NSR (AT91_CAST(AT91_REG *) 0xFFFC4008) // (EMACB) Network Status Register\r
+#define AT91C_EMACB_MCF (AT91_CAST(AT91_REG *) 0xFFFC4048) // (EMACB) Multiple Collision Frame Register\r
+#define AT91C_EMACB_RBQP (AT91_CAST(AT91_REG *) 0xFFFC4018) // (EMACB) Receive Buffer Queue Pointer\r
+#define AT91C_EMACB_RSR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (EMACB) Receive Status Register\r
+#define AT91C_EMACB_SA2H (AT91_CAST(AT91_REG *) 0xFFFC40A4) // (EMACB) Specific Address 2 Top, Last 2 bytes\r
+#define AT91C_EMACB_NCFGR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (EMACB) Network Configuration Register\r
+#define AT91C_EMACB_LCOL (AT91_CAST(AT91_REG *) 0xFFFC405C) // (EMACB) Late Collision Register\r
+// ========== Register definition for UDP peripheral ========== \r
+#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFA4004) // (UDP) Global State Register\r
+#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFA4050) // (UDP) Endpoint FIFO Data Register\r
+#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFA4028) // (UDP) Reset Endpoint Register\r
+#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFA4008) // (UDP) Function Address Register\r
+#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFA4000) // (UDP) Frame Number Register\r
+#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFA4014) // (UDP) Interrupt Disable Register\r
+#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFA4018) // (UDP) Interrupt Mask Register\r
+#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFA4030) // (UDP) Endpoint Control and Status Register\r
+#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFA4010) // (UDP) Interrupt Enable Register\r
+#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFA4020) // (UDP) Interrupt Clear Register\r
+#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFA4074) // (UDP) Transceiver Control Register\r
+#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFA401C) // (UDP) Interrupt Status Register\r
+// ========== Register definition for UHP peripheral ========== \r
+#define AT91C_UHP_HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0050000C) // (UHP) Interrupt Status Register\r
+#define AT91C_UHP_HcCommandStatus (AT91_CAST(AT91_REG *) 0x00500008) // (UHP) Command & status Register\r
+#define AT91C_UHP_HcRhStatus (AT91_CAST(AT91_REG *) 0x00500050) // (UHP) Root Hub Status register\r
+#define AT91C_UHP_HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00500014) // (UHP) Interrupt Disable Register\r
+#define AT91C_UHP_HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00500040) // (UHP) Periodic Start\r
+#define AT91C_UHP_HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00500024) // (UHP) Endpoint Control and Status Register\r
+#define AT91C_UHP_HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0050001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor\r
+#define AT91C_UHP_HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00500028) // (UHP) First endpoint register of the Bulk list\r
+#define AT91C_UHP_HcRevision (AT91_CAST(AT91_REG *) 0x00500000) // (UHP) Revision\r
+#define AT91C_UHP_HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0050002C) // (UHP) Current endpoint of the Bulk list\r
+#define AT91C_UHP_HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0050004C) // (UHP) Root Hub characteristics B\r
+#define AT91C_UHP_HcControlHeadED (AT91_CAST(AT91_REG *) 0x00500020) // (UHP) First Endpoint Descriptor of the Control list\r
+#define AT91C_UHP_HcFmRemaining (AT91_CAST(AT91_REG *) 0x00500038) // (UHP) Bit time remaining in the current Frame\r
+#define AT91C_UHP_HcHCCA (AT91_CAST(AT91_REG *) 0x00500018) // (UHP) Pointer to the Host Controller Communication Area\r
+#define AT91C_UHP_HcLSThreshold (AT91_CAST(AT91_REG *) 0x00500044) // (UHP) LS Threshold\r
+#define AT91C_UHP_HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00500054) // (UHP) Root Hub Port Status Register\r
+#define AT91C_UHP_HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00500010) // (UHP) Interrupt Enable Register\r
+#define AT91C_UHP_HcFmNumber (AT91_CAST(AT91_REG *) 0x0050003C) // (UHP) Frame number\r
+#define AT91C_UHP_HcFmInterval (AT91_CAST(AT91_REG *) 0x00500034) // (UHP) Bit time between 2 consecutive SOFs\r
+#define AT91C_UHP_HcControl (AT91_CAST(AT91_REG *) 0x00500004) // (UHP) Operating modes for the Host Controller\r
+#define AT91C_UHP_HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00500030) // (UHP) Last completed transfer descriptor\r
+#define AT91C_UHP_HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00500048) // (UHP) Root Hub characteristics A\r
+// ========== Register definition for HECC peripheral ========== \r
+// ========== Register definition for HISI peripheral ========== \r
+#define AT91C_HISI_PSIZE (AT91_CAST(AT91_REG *) 0xFFFC0020) // (HISI) Preview Size Register\r
+#define AT91C_HISI_CR1 (AT91_CAST(AT91_REG *) 0xFFFC0000) // (HISI) Control Register 1\r
+#define AT91C_HISI_R2YSET1 (AT91_CAST(AT91_REG *) 0xFFFC003C) // (HISI) Color Space Conversion Register\r
+#define AT91C_HISI_CDBA (AT91_CAST(AT91_REG *) 0xFFFC002C) // (HISI) Codec Dma Address Register\r
+#define AT91C_HISI_IDR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (HISI) Interrupt Disable Register\r
+#define AT91C_HISI_R2YSET2 (AT91_CAST(AT91_REG *) 0xFFFC0040) // (HISI) Color Space Conversion Register\r
+#define AT91C_HISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0xFFFC0034) // (HISI) Color Space Conversion Register\r
+#define AT91C_HISI_PFBD (AT91_CAST(AT91_REG *) 0xFFFC0028) // (HISI) Preview Frame Buffer Address Register\r
+#define AT91C_HISI_CR2 (AT91_CAST(AT91_REG *) 0xFFFC0004) // (HISI) Control Register 2\r
+#define AT91C_HISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0xFFFC0030) // (HISI) Color Space Conversion Register\r
+#define AT91C_HISI_PDECF (AT91_CAST(AT91_REG *) 0xFFFC0024) // (HISI) Preview Decimation Factor Register\r
+#define AT91C_HISI_IMR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (HISI) Interrupt Mask Register\r
+#define AT91C_HISI_IER (AT91_CAST(AT91_REG *) 0xFFFC000C) // (HISI) Interrupt Enable Register\r
+#define AT91C_HISI_R2YSET0 (AT91_CAST(AT91_REG *) 0xFFFC0038) // (HISI) Color Space Conversion Register\r
+#define AT91C_HISI_SR (AT91_CAST(AT91_REG *) 0xFFFC0008) // (HISI) Status Register\r
+\r
+// *****************************************************************************\r
+// PIO DEFINITIONS FOR AT91SAM9XE128\r
+// *****************************************************************************\r
+#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0\r
+#define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) // SPI 0 Master In Slave\r
+#define AT91C_PA0_MCDB0 (AT91C_PIO_PA0) // Multimedia Card B Data 0\r
+#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1\r
+#define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) // SPI 0 Master Out Slave\r
+#define AT91C_PA1_MCCDB (AT91C_PIO_PA1) // Multimedia Card B Command\r
+#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10\r
+#define AT91C_PA10_MCDA2 (AT91C_PIO_PA10) // Multimedia Card A Data 2\r
+#define AT91C_PA10_ETX2_0 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 2\r
+#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11\r
+#define AT91C_PA11_MCDA3 (AT91C_PIO_PA11) // Multimedia Card A Data 3\r
+#define AT91C_PA11_ETX3_0 (AT91C_PIO_PA11) // Ethernet MAC Transmit Data 3\r
+#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12\r
+#define AT91C_PA12_ETX0 (AT91C_PIO_PA12) // Ethernet MAC Transmit Data 0\r
+#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13\r
+#define AT91C_PA13_ETX1 (AT91C_PIO_PA13) // Ethernet MAC Transmit Data 1\r
+#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14\r
+#define AT91C_PA14_ERX0 (AT91C_PIO_PA14) // Ethernet MAC Receive Data 0\r
+#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15\r
+#define AT91C_PA15_ERX1 (AT91C_PIO_PA15) // Ethernet MAC Receive Data 1\r
+#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16\r
+#define AT91C_PA16_ETXEN (AT91C_PIO_PA16) // Ethernet MAC Transmit Enable\r
+#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17\r
+#define AT91C_PA17_ERXDV (AT91C_PIO_PA17) // Ethernet MAC Receive Data Valid\r
+#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18\r
+#define AT91C_PA18_ERXER (AT91C_PIO_PA18) // Ethernet MAC Receive Error\r
+#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19\r
+#define AT91C_PA19_ETXCK (AT91C_PIO_PA19) // Ethernet MAC Transmit Clock/Reference Clock\r
+#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2\r
+#define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) // SPI 0 Serial Clock\r
+#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20\r
+#define AT91C_PA20_EMDC (AT91C_PIO_PA20) // Ethernet MAC Management Data Clock\r
+#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21\r
+#define AT91C_PA21_EMDIO (AT91C_PIO_PA21) // Ethernet MAC Management Data Input/Output\r
+#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22\r
+#define AT91C_PA22_ADTRG (AT91C_PIO_PA22) // ADC Trigger\r
+#define AT91C_PA22_ETXER (AT91C_PIO_PA22) // Ethernet MAC Transmikt Coding Error\r
+#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23\r
+#define AT91C_PA23_TWD0 (AT91C_PIO_PA23) // TWI Two-wire Serial Data 0\r
+#define AT91C_PA23_ETX2_1 (AT91C_PIO_PA23) // Ethernet MAC Transmit Data 2\r
+#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24\r
+#define AT91C_PA24_TWCK0 (AT91C_PIO_PA24) // TWI Two-wire Serial Clock 0\r
+#define AT91C_PA24_ETX3_1 (AT91C_PIO_PA24) // Ethernet MAC Transmit Data 3\r
+#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25\r
+#define AT91C_PA25_TCLK0 (AT91C_PIO_PA25) // Timer Counter 0 external clock input\r
+#define AT91C_PA25_ERX2 (AT91C_PIO_PA25) // Ethernet MAC Receive Data 2\r
+#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26\r
+#define AT91C_PA26_TIOA0 (AT91C_PIO_PA26) // Timer Counter 0 Multipurpose Timer I/O Pin A\r
+#define AT91C_PA26_ERX3 (AT91C_PIO_PA26) // Ethernet MAC Receive Data 3\r
+#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27\r
+#define AT91C_PA27_TIOA1 (AT91C_PIO_PA27) // Timer Counter 1 Multipurpose Timer I/O Pin A\r
+#define AT91C_PA27_ERXCK (AT91C_PIO_PA27) // Ethernet MAC Receive Clock\r
+#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28\r
+#define AT91C_PA28_TIOA2 (AT91C_PIO_PA28) // Timer Counter 2 Multipurpose Timer I/O Pin A\r
+#define AT91C_PA28_ECRS (AT91C_PIO_PA28) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\r
+#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29\r
+#define AT91C_PA29_SCK1 (AT91C_PIO_PA29) // USART 1 Serial Clock\r
+#define AT91C_PA29_ECOL (AT91C_PIO_PA29) // Ethernet MAC Collision Detected\r
+#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3\r
+#define AT91C_PA3_SPI0_NPCS0 (AT91C_PIO_PA3) // SPI 0 Peripheral Chip Select 0\r
+#define AT91C_PA3_MCDB3 (AT91C_PIO_PA3) // Multimedia Card B Data 3\r
+#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30\r
+#define AT91C_PA30_SCK2 (AT91C_PIO_PA30) // USART 2 Serial Clock\r
+#define AT91C_PA30_RXD4 (AT91C_PIO_PA30) // USART 4 Receive Data\r
+#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31\r
+#define AT91C_PA31_SCK0 (AT91C_PIO_PA31) // USART 0 Serial Clock\r
+#define AT91C_PA31_TXD4 (AT91C_PIO_PA31) // USART 4 Transmit Data\r
+#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4\r
+#define AT91C_PA4_RTS2 (AT91C_PIO_PA4) // USART 2 Ready To Send\r
+#define AT91C_PA4_MCDB2 (AT91C_PIO_PA4) // Multimedia Card B Data 2\r
+#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5\r
+#define AT91C_PA5_CTS2 (AT91C_PIO_PA5) // USART 2 Clear To Send\r
+#define AT91C_PA5_MCDB1 (AT91C_PIO_PA5) // Multimedia Card B Data 1\r
+#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6\r
+#define AT91C_PA6_MCDA0 (AT91C_PIO_PA6) // Multimedia Card A Data 0\r
+#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7\r
+#define AT91C_PA7_MCCDA (AT91C_PIO_PA7) // Multimedia Card A Command\r
+#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8\r
+#define AT91C_PA8_MCCK (AT91C_PIO_PA8) // Multimedia Card Clock\r
+#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9\r
+#define AT91C_PA9_MCDA1 (AT91C_PIO_PA9) // Multimedia Card A Data 1\r
+#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0\r
+#define AT91C_PB0_SPI1_MISO (AT91C_PIO_PB0) // SPI 1 Master In Slave\r
+#define AT91C_PB0_TIOA3 (AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin A\r
+#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1\r
+#define AT91C_PB1_SPI1_MOSI (AT91C_PIO_PB1) // SPI 1 Master Out Slave\r
+#define AT91C_PB1_TIOB3 (AT91C_PIO_PB1) // Timer Counter 3 Multipurpose Timer I/O Pin B\r
+#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10\r
+#define AT91C_PB10_TXD3 (AT91C_PIO_PB10) // USART 3 Transmit Data\r
+#define AT91C_PB10_ISI_D8 (AT91C_PIO_PB10) // Image Sensor Data 8\r
+#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11\r
+#define AT91C_PB11_RXD3 (AT91C_PIO_PB11) // USART 3 Receive Data\r
+#define AT91C_PB11_ISI_D9 (AT91C_PIO_PB11) // Image Sensor Data 9\r
+#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12\r
+#define AT91C_PB12_TWD1 (AT91C_PIO_PB12) // TWI Two-wire Serial Data 1\r
+#define AT91C_PB12_ISI_D10 (AT91C_PIO_PB12) // Image Sensor Data 10\r
+#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13\r
+#define AT91C_PB13_TWCK1 (AT91C_PIO_PB13) // TWI Two-wire Serial Clock 1\r
+#define AT91C_PB13_ISI_D11 (AT91C_PIO_PB13) // Image Sensor Data 11\r
+#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14\r
+#define AT91C_PB14_DRXD (AT91C_PIO_PB14) // DBGU Debug Receive Data\r
+#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15\r
+#define AT91C_PB15_DTXD (AT91C_PIO_PB15) // DBGU Debug Transmit Data\r
+#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16\r
+#define AT91C_PB16_TK0 (AT91C_PIO_PB16) // SSC0 Transmit Clock\r
+#define AT91C_PB16_TCLK3 (AT91C_PIO_PB16) // Timer Counter 3 external clock input\r
+#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17\r
+#define AT91C_PB17_TF0 (AT91C_PIO_PB17) // SSC0 Transmit Frame Sync\r
+#define AT91C_PB17_TCLK4 (AT91C_PIO_PB17) // Timer Counter 4 external clock input\r
+#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18\r
+#define AT91C_PB18_TD0 (AT91C_PIO_PB18) // SSC0 Transmit data\r
+#define AT91C_PB18_TIOB4 (AT91C_PIO_PB18) // Timer Counter 4 Multipurpose Timer I/O Pin B\r
+#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19\r
+#define AT91C_PB19_RD0 (AT91C_PIO_PB19) // SSC0 Receive Data\r
+#define AT91C_PB19_TIOB5 (AT91C_PIO_PB19) // Timer Counter 5 Multipurpose Timer I/O Pin B\r
+#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2\r
+#define AT91C_PB2_SPI1_SPCK (AT91C_PIO_PB2) // SPI 1 Serial Clock\r
+#define AT91C_PB2_TIOA4 (AT91C_PIO_PB2) // Timer Counter 4 Multipurpose Timer I/O Pin A\r
+#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20\r
+#define AT91C_PB20_RK0 (AT91C_PIO_PB20) // SSC0 Receive Clock\r
+#define AT91C_PB20_ISI_D0 (AT91C_PIO_PB20) // Image Sensor Data 0\r
+#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21\r
+#define AT91C_PB21_RF0 (AT91C_PIO_PB21) // SSC0 Receive Frame Sync\r
+#define AT91C_PB21_ISI_D1 (AT91C_PIO_PB21) // Image Sensor Data 1\r
+#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22\r
+#define AT91C_PB22_DSR0 (AT91C_PIO_PB22) // USART 0 Data Set ready\r
+#define AT91C_PB22_ISI_D2 (AT91C_PIO_PB22) // Image Sensor Data 2\r
+#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23\r
+#define AT91C_PB23_DCD0 (AT91C_PIO_PB23) // USART 0 Data Carrier Detect\r
+#define AT91C_PB23_ISI_D3 (AT91C_PIO_PB23) // Image Sensor Data 3\r
+#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24\r
+#define AT91C_PB24_DTR0 (AT91C_PIO_PB24) // USART 0 Data Terminal ready\r
+#define AT91C_PB24_ISI_D4 (AT91C_PIO_PB24) // Image Sensor Data 4\r
+#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25\r
+#define AT91C_PB25_RI0 (AT91C_PIO_PB25) // USART 0 Ring Indicator\r
+#define AT91C_PB25_ISI_D5 (AT91C_PIO_PB25) // Image Sensor Data 5\r
+#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26\r
+#define AT91C_PB26_RTS0 (AT91C_PIO_PB26) // USART 0 Ready To Send\r
+#define AT91C_PB26_ISI_D6 (AT91C_PIO_PB26) // Image Sensor Data 6\r
+#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27\r
+#define AT91C_PB27_CTS0 (AT91C_PIO_PB27) // USART 0 Clear To Send\r
+#define AT91C_PB27_ISI_D7 (AT91C_PIO_PB27) // Image Sensor Data 7\r
+#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28\r
+#define AT91C_PB28_RTS1 (AT91C_PIO_PB28) // USART 1 Ready To Send\r
+#define AT91C_PB28_ISI_PCK (AT91C_PIO_PB28) // Image Sensor Data Clock\r
+#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29\r
+#define AT91C_PB29_CTS1 (AT91C_PIO_PB29) // USART 1 Clear To Send\r
+#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) // Image Sensor Vertical Synchro\r
+#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3\r
+#define AT91C_PB3_SPI1_NPCS0 (AT91C_PIO_PB3) // SPI 1 Peripheral Chip Select 0\r
+#define AT91C_PB3_TIOA5 (AT91C_PIO_PB3) // Timer Counter 5 Multipurpose Timer I/O Pin A\r
+#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30\r
+#define AT91C_PB30_PCK0_0 (AT91C_PIO_PB30) // PMC Programmable Clock Output 0\r
+#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) // Image Sensor Horizontal Synchro\r
+#define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31\r
+#define AT91C_PB31_PCK1_0 (AT91C_PIO_PB31) // PMC Programmable Clock Output 1\r
+#define AT91C_PB31_ISI_MCK (AT91C_PIO_PB31) // Image Sensor Reference Clock\r
+#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4\r
+#define AT91C_PB4_TXD0 (AT91C_PIO_PB4) // USART 0 Transmit Data\r
+#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5\r
+#define AT91C_PB5_RXD0 (AT91C_PIO_PB5) // USART 0 Receive Data\r
+#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6\r
+#define AT91C_PB6_TXD1 (AT91C_PIO_PB6) // USART 1 Transmit Data\r
+#define AT91C_PB6_TCLK1 (AT91C_PIO_PB6) // Timer Counter 1 external clock input\r
+#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7\r
+#define AT91C_PB7_RXD1 (AT91C_PIO_PB7) // USART 1 Receive Data\r
+#define AT91C_PB7_TCLK2 (AT91C_PIO_PB7) // Timer Counter 2 external clock input\r
+#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8\r
+#define AT91C_PB8_TXD2 (AT91C_PIO_PB8) // USART 2 Transmit Data\r
+#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9\r
+#define AT91C_PB9_RXD2 (AT91C_PIO_PB9) // USART 2 Receive Data\r
+#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0\r
+#define AT91C_PC0_AD0 (AT91C_PIO_PC0) // ADC Analog Input 0\r
+#define AT91C_PC0_SCK3 (AT91C_PIO_PC0) // USART 3 Serial Clock\r
+#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1\r
+#define AT91C_PC1_AD1 (AT91C_PIO_PC1) // ADC Analog Input 1\r
+#define AT91C_PC1_PCK0 (AT91C_PIO_PC1) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10\r
+#define AT91C_PC10_A25_CFRNW (AT91C_PIO_PC10) // Address Bus[25]\r
+#define AT91C_PC10_CTS3 (AT91C_PIO_PC10) // USART 3 Clear To Send\r
+#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11\r
+#define AT91C_PC11_NCS2 (AT91C_PIO_PC11) // Chip Select Line 2\r
+#define AT91C_PC11_SPI0_NPCS1 (AT91C_PIO_PC11) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12\r
+#define AT91C_PC12_IRQ0 (AT91C_PIO_PC12) // External Interrupt 0\r
+#define AT91C_PC12_NCS7 (AT91C_PIO_PC12) // Chip Select Line 7\r
+#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13\r
+#define AT91C_PC13_FIQ (AT91C_PIO_PC13) // AIC Fast Interrupt Input\r
+#define AT91C_PC13_NCS6 (AT91C_PIO_PC13) // Chip Select Line 6\r
+#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14\r
+#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) // Chip Select Line 3\r
+#define AT91C_PC14_IRQ2 (AT91C_PIO_PC14) // External Interrupt 2\r
+#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15\r
+#define AT91C_PC15_NWAIT (AT91C_PIO_PC15) // External Wait Signal\r
+#define AT91C_PC15_IRQ1 (AT91C_PIO_PC15) // External Interrupt 1\r
+#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16\r
+#define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus[16]\r
+#define AT91C_PC16_SPI0_NPCS2 (AT91C_PIO_PC16) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17\r
+#define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus[17]\r
+#define AT91C_PC17_SPI0_NPCS3 (AT91C_PIO_PC17) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18\r
+#define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus[18]\r
+#define AT91C_PC18_SPI1_NPCS1_1 (AT91C_PIO_PC18) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19\r
+#define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus[19]\r
+#define AT91C_PC19_SPI1_NPCS2_1 (AT91C_PIO_PC19) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2\r
+#define AT91C_PC2_AD2 (AT91C_PIO_PC2) // ADC Analog Input 2\r
+#define AT91C_PC2_PCK1 (AT91C_PIO_PC2) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20\r
+#define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus[20]\r
+#define AT91C_PC20_SPI1_NPCS3_1 (AT91C_PIO_PC20) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21\r
+#define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus[21]\r
+#define AT91C_PC21_EF100 (AT91C_PIO_PC21) // Ethernet MAC Force 100 Mbits/sec\r
+#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22\r
+#define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus[22]\r
+#define AT91C_PC22_TCLK5 (AT91C_PIO_PC22) // Timer Counter 5 external clock input\r
+#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23\r
+#define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus[23]\r
+#define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24\r
+#define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus[24]\r
+#define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25\r
+#define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus[25]\r
+#define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26\r
+#define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus[26]\r
+#define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27\r
+#define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus[27]\r
+#define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28\r
+#define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus[28]\r
+#define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29\r
+#define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus[29]\r
+#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3\r
+#define AT91C_PC3_AD3 (AT91C_PIO_PC3) // ADC Analog Input 3\r
+#define AT91C_PC3_SPI1_NPCS3_0 (AT91C_PIO_PC3) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30\r
+#define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus[30]\r
+#define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31\r
+#define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus[31]\r
+#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4\r
+#define AT91C_PC4_A23 (AT91C_PIO_PC4) // Address Bus[23]\r
+#define AT91C_PC4_SPI1_NPCS2_0 (AT91C_PIO_PC4) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5\r
+#define AT91C_PC5_A24 (AT91C_PIO_PC5) // Address Bus[24]\r
+#define AT91C_PC5_SPI1_NPCS1_0 (AT91C_PIO_PC5) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6\r
+#define AT91C_PC6_TIOB2 (AT91C_PIO_PC6) // Timer Counter 2 Multipurpose Timer I/O Pin B\r
+#define AT91C_PC6_CFCE1 (AT91C_PIO_PC6) // Compact Flash Enable 1\r
+#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7\r
+#define AT91C_PC7_TIOB1 (AT91C_PIO_PC7) // Timer Counter 1 Multipurpose Timer I/O Pin B\r
+#define AT91C_PC7_CFCE2 (AT91C_PIO_PC7) // Compact Flash Enable 2\r
+#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8\r
+#define AT91C_PC8_NCS4_CFCS0 (AT91C_PIO_PC8) // Chip Select Line 4\r
+#define AT91C_PC8_RTS3 (AT91C_PIO_PC8) // USART 3 Ready To Send\r
+#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9\r
+#define AT91C_PC9_NCS5_CFCS1 (AT91C_PIO_PC9) // Chip Select Line 5\r
+#define AT91C_PC9_TIOB0 (AT91C_PIO_PC9) // Timer Counter 0 Multipurpose Timer I/O Pin B\r
+\r
+// *****************************************************************************\r
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM9XE128\r
+// *****************************************************************************\r
+#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)\r
+#define AT91C_ID_SYS ( 1) // System Controller\r
+#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A\r
+#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B\r
+#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C\r
+#define AT91C_ID_ADC ( 5) // ADC\r
+#define AT91C_ID_US0 ( 6) // USART 0\r
+#define AT91C_ID_US1 ( 7) // USART 1\r
+#define AT91C_ID_US2 ( 8) // USART 2\r
+#define AT91C_ID_MCI ( 9) // Multimedia Card Interface 0\r
+#define AT91C_ID_UDP (10) // USB Device Port\r
+#define AT91C_ID_TWI0 (11) // Two-Wire Interface 0\r
+#define AT91C_ID_SPI0 (12) // Serial Peripheral Interface 0\r
+#define AT91C_ID_SPI1 (13) // Serial Peripheral Interface 1\r
+#define AT91C_ID_SSC0 (14) // Serial Synchronous Controller 0\r
+#define AT91C_ID_TC0 (17) // Timer Counter 0\r
+#define AT91C_ID_TC1 (18) // Timer Counter 1\r
+#define AT91C_ID_TC2 (19) // Timer Counter 2\r
+#define AT91C_ID_UHP (20) // USB Host Port\r
+#define AT91C_ID_EMAC (21) // Ethernet Mac\r
+#define AT91C_ID_HISI (22) // Image Sensor Interface\r
+#define AT91C_ID_US3 (23) // USART 3\r
+#define AT91C_ID_US4 (24) // USART 4\r
+#define AT91C_ID_TWI1 (25) // Two-Wire Interface 1\r
+#define AT91C_ID_TC3 (26) // Timer Counter 3\r
+#define AT91C_ID_TC4 (27) // Timer Counter 4\r
+#define AT91C_ID_TC5 (28) // Timer Counter 5\r
+#define AT91C_ID_IRQ0 (29) // Advanced Interrupt Controller (IRQ0)\r
+#define AT91C_ID_IRQ1 (30) // Advanced Interrupt Controller (IRQ1)\r
+#define AT91C_ID_IRQ2 (31) // Advanced Interrupt Controller (IRQ2)\r
+#define AT91C_ALL_INT (0xFFFE7FFF) // ALL VALID INTERRUPTS\r
+\r
+// *****************************************************************************\r
+// BASE ADDRESS DEFINITIONS FOR AT91SAM9XE128\r
+// *****************************************************************************\r
+#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFFD00) // (SYS) Base Address\r
+#define AT91C_BASE_EBI (AT91_CAST(AT91PS_EBI) 0xFFFFEA00) // (EBI) Base Address\r
+#define AT91C_BASE_HECC (AT91_CAST(AT91PS_ECC) 0xFFFFE800) // (HECC) Base Address\r
+#define AT91C_BASE_SDRAMC (AT91_CAST(AT91PS_SDRAMC) 0xFFFFEA00) // (SDRAMC) Base Address\r
+#define AT91C_BASE_SMC (AT91_CAST(AT91PS_SMC) 0xFFFFEC00) // (SMC) Base Address\r
+#define AT91C_BASE_MATRIX (AT91_CAST(AT91PS_MATRIX) 0xFFFFEE00) // (MATRIX) Base Address\r
+#define AT91C_BASE_CCFG (AT91_CAST(AT91PS_CCFG) 0xFFFFEF10) // (CCFG) Base Address\r
+#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address\r
+#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address\r
+#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address\r
+#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address\r
+#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address\r
+#define AT91C_BASE_PIOC (AT91_CAST(AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address\r
+#define AT91C_BASE_EFC (AT91_CAST(AT91PS_EFC) 0xFFFFFA00) // (EFC) Base Address\r
+#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address\r
+#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address\r
+#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address\r
+#define AT91C_BASE_SHDWC (AT91_CAST(AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address\r
+#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address\r
+#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address\r
+#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address\r
+#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address\r
+#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address\r
+#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address\r
+#define AT91C_BASE_TC3 (AT91_CAST(AT91PS_TC) 0xFFFDC000) // (TC3) Base Address\r
+#define AT91C_BASE_TC4 (AT91_CAST(AT91PS_TC) 0xFFFDC040) // (TC4) Base Address\r
+#define AT91C_BASE_TC5 (AT91_CAST(AT91PS_TC) 0xFFFDC080) // (TC5) Base Address\r
+#define AT91C_BASE_TCB0 (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address\r
+#define AT91C_BASE_TCB1 (AT91_CAST(AT91PS_TCB) 0xFFFDC000) // (TCB1) Base Address\r
+#define AT91C_BASE_PDC_MCI (AT91_CAST(AT91PS_PDC) 0xFFFA8100) // (PDC_MCI) Base Address\r
+#define AT91C_BASE_MCI (AT91_CAST(AT91PS_MCI) 0xFFFA8000) // (MCI) Base Address\r
+#define AT91C_BASE_PDC_TWI0 (AT91_CAST(AT91PS_PDC) 0xFFFAC100) // (PDC_TWI0) Base Address\r
+#define AT91C_BASE_TWI0 (AT91_CAST(AT91PS_TWI) 0xFFFAC000) // (TWI0) Base Address\r
+#define AT91C_BASE_PDC_TWI1 (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_TWI1) Base Address\r
+#define AT91C_BASE_TWI1 (AT91_CAST(AT91PS_TWI) 0xFFFD8000) // (TWI1) Base Address\r
+#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFB0100) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFB0000) // (US0) Base Address\r
+#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFB4100) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFB4000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US2 (AT91_CAST(AT91PS_PDC) 0xFFFB8100) // (PDC_US2) Base Address\r
+#define AT91C_BASE_US2 (AT91_CAST(AT91PS_USART) 0xFFFB8000) // (US2) Base Address\r
+#define AT91C_BASE_PDC_US3 (AT91_CAST(AT91PS_PDC) 0xFFFD0100) // (PDC_US3) Base Address\r
+#define AT91C_BASE_US3 (AT91_CAST(AT91PS_USART) 0xFFFD0000) // (US3) Base Address\r
+#define AT91C_BASE_PDC_US4 (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_US4) Base Address\r
+#define AT91C_BASE_US4 (AT91_CAST(AT91PS_USART) 0xFFFD4000) // (US4) Base Address\r
+#define AT91C_BASE_PDC_SSC0 (AT91_CAST(AT91PS_PDC) 0xFFFBC100) // (PDC_SSC0) Base Address\r
+#define AT91C_BASE_SSC0 (AT91_CAST(AT91PS_SSC) 0xFFFBC000) // (SSC0) Base Address\r
+#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFC8100) // (PDC_SPI0) Base Address\r
+#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFC8000) // (SPI0) Base Address\r
+#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFCC100) // (PDC_SPI1) Base Address\r
+#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFCC000) // (SPI1) Base Address\r
+#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_ADC) Base Address\r
+#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFE0000) // (ADC) Base Address\r
+#define AT91C_BASE_EMACB (AT91_CAST(AT91PS_EMAC) 0xFFFC4000) // (EMACB) Base Address\r
+#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFA4000) // (UDP) Base Address\r
+#define AT91C_BASE_UHP (AT91_CAST(AT91PS_UHP) 0x00500000) // (UHP) Base Address\r
+#define AT91C_BASE_HISI (AT91_CAST(AT91PS_ISI) 0xFFFC0000) // (HISI) Base Address\r
+\r
+// *****************************************************************************\r
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM9XE128\r
+// *****************************************************************************\r
+// IROM\r
+#define AT91C_IROM (0x00100000) // Internal ROM base address\r
+#define AT91C_IROM_SIZE (0x00008000) // Internal ROM size in byte (32 Kbytes)\r
+// ISRAM\r
+#define AT91C_ISRAM (0x00300000) // Maximum IRAM Area : 16Kbyte base address\r
+#define AT91C_ISRAM_SIZE (0x00004000) // Maximum IRAM Area : 16Kbyte size in byte (16 Kbytes)\r
+// ISRAM_MIN\r
+#define AT91C_ISRAM_MIN (0x00300000) // Minimun IRAM Area : 16Kbyte base address\r
+#define AT91C_ISRAM_MIN_SIZE (0x00004000) // Minimun IRAM Area : 16Kbyte size in byte (16 Kbytes)\r
+// IFLASH\r
+#define AT91C_IFLASH (0x00200000) // Maximum IFLASH Area : 128Kbyte base address\r
+#define AT91C_IFLASH_SIZE (0x00020000) // Maximum IFLASH Area : 128Kbyte size in byte (128 Kbytes)\r
+#define AT91C_IFLASH_PAGE_SIZE (512) // Maximum IFLASH Area : 128Kbyte Page Size: 512 bytes\r
+#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Maximum IFLASH Area : 128Kbyte Lock Region Size: 16 Kbytes\r
+#define AT91C_IFLASH_NB_OF_PAGES (256) // Maximum IFLASH Area : 128Kbyte Number of Pages: 256 bytes\r
+#define AT91C_IFLASH_NB_OF_LOCK_BITS (8) // Maximum IFLASH Area : 128Kbyte Number of Lock Bits: 8 bytes\r
+// EBI_CS0\r
+#define AT91C_EBI_CS0 (0x10000000) // EBI Chip Select 0 base address\r
+#define AT91C_EBI_CS0_SIZE (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)\r
+// EBI_CS1\r
+#define AT91C_EBI_CS1 (0x20000000) // EBI Chip Select 1 base address\r
+#define AT91C_EBI_CS1_SIZE (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)\r
+// EBI_SDRAM\r
+#define AT91C_EBI_SDRAM (0x20000000) // SDRAM on EBI Chip Select 1 base address\r
+#define AT91C_EBI_SDRAM_SIZE (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes)\r
+// EBI_SDRAM_16BIT\r
+#define AT91C_EBI_SDRAM_16BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address\r
+#define AT91C_EBI_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes)\r
+// EBI_SDRAM_32BIT\r
+#define AT91C_EBI_SDRAM_32BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address\r
+#define AT91C_EBI_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes)\r
+// EBI_CS2\r
+#define AT91C_EBI_CS2 (0x30000000) // EBI Chip Select 2 base address\r
+#define AT91C_EBI_CS2_SIZE (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)\r
+// EBI_CS3\r
+#define AT91C_EBI_CS3 (0x40000000) // EBI Chip Select 3 base address\r
+#define AT91C_EBI_CS3_SIZE (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)\r
+// EBI_SM\r
+#define AT91C_EBI_SM (0x40000000) // SmartMedia on Chip Select 3 base address\r
+#define AT91C_EBI_SM_SIZE (0x10000000) // SmartMedia on Chip Select 3 size in byte (262144 Kbytes)\r
+// EBI_CS4\r
+#define AT91C_EBI_CS4 (0x50000000) // EBI Chip Select 4 base address\r
+#define AT91C_EBI_CS4_SIZE (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)\r
+// EBI_CF0\r
+#define AT91C_EBI_CF0 (0x50000000) // CompactFlash 0 on Chip Select 4 base address\r
+#define AT91C_EBI_CF0_SIZE (0x10000000) // CompactFlash 0 on Chip Select 4 size in byte (262144 Kbytes)\r
+// EBI_CS5\r
+#define AT91C_EBI_CS5 (0x60000000) // EBI Chip Select 5 base address\r
+#define AT91C_EBI_CS5_SIZE (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)\r
+// EBI_CF1\r
+#define AT91C_EBI_CF1 (0x60000000) // CompactFlash 1 on Chip Select 5 base address\r
+#define AT91C_EBI_CF1_SIZE (0x10000000) // CompactFlash 1 on Chip Select 5 size in byte (262144 Kbytes)\r
+// EBI_CS6\r
+#define AT91C_EBI_CS6 (0x70000000) // EBI Chip Select 6 base address\r
+#define AT91C_EBI_CS6_SIZE (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes)\r
+// EBI_CS7\r
+#define AT91C_EBI_CS7 (0x80000000) // EBI Chip Select 7 base address\r
+#define AT91C_EBI_CS7_SIZE (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes)\r
+\r
+#endif\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x200000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x21FFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x300000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x303FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_startup__ = 0x100;\r
+define symbol __ICFEDIT_size_vectors__ = 0x100;\r
+define symbol __ICFEDIT_size_cstack__ = 0x1000;\r
+define symbol __ICFEDIT_size_svcstack__ = 0x60;\r
+define symbol __ICFEDIT_size_irqstack__ = 0x60;\r
+define symbol __ICFEDIT_size_heap__ = 0x0;\r
+/*-Exports-*/\r
+export symbol __ICFEDIT_region_ROM_start__;\r
+export symbol __ICFEDIT_region_ROM_end__;\r
+export symbol __ICFEDIT_region_RAM_start__;\r
+export symbol __ICFEDIT_region_RAM_end__;\r
+export symbol __ICFEDIT_size_startup__;\r
+export symbol __ICFEDIT_size_vectors__;\r
+export symbol __ICFEDIT_size_cstack__;\r
+export symbol __ICFEDIT_size_svcstack__;\r
+export symbol __ICFEDIT_size_irqstack__;\r
+export symbol __ICFEDIT_size_heap__;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region STA_region = mem:[from __ICFEDIT_region_ROM_start__ size __ICFEDIT_size_startup__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_ROM_end__];\r
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };\r
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+initialize by copy { section .vectors };\r
+do not initialize { section .noinit };\r
+\r
+place in STA_region { section .cstartup };\r
+place in ROM_region { readonly };\r
+place in VEC_region { section .vectors };\r
+place in RAM_region { readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };\r
+\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_SDRAM_end__ = 0x21FFFFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x300000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x303FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_startup__ = 0x100;\r
+define symbol __ICFEDIT_size_vectors__ = 0x100;\r
+define symbol __ICFEDIT_size_cstack__ = 0x1000;\r
+define symbol __ICFEDIT_size_svcstack__ = 0x60;\r
+define symbol __ICFEDIT_size_irqstack__ = 0x60;\r
+define symbol __ICFEDIT_size_heap__ = 0x0;\r
+/*-Exports-*/\r
+export symbol __ICFEDIT_region_SDRAM_start__;\r
+export symbol __ICFEDIT_region_SDRAM_end__;\r
+export symbol __ICFEDIT_region_RAM_start__;\r
+export symbol __ICFEDIT_region_RAM_end__;\r
+export symbol __ICFEDIT_size_startup__;\r
+export symbol __ICFEDIT_size_vectors__;\r
+export symbol __ICFEDIT_size_cstack__;\r
+export symbol __ICFEDIT_size_svcstack__;\r
+export symbol __ICFEDIT_size_irqstack__;\r
+export symbol __ICFEDIT_size_heap__;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region STA_region = mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__];\r
+define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__];\r
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };\r
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { section .vectors };\r
+do not initialize { section .noinit };\r
+\r
+place in STA_region { section .cstartup };\r
+place in VEC_region { section .vectors };\r
+place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };\r
+\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x300000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x303FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_vectors__ = 0x100;\r
+define symbol __ICFEDIT_size_cstack__ = 0x800;\r
+define symbol __ICFEDIT_size_svcstack__ = 0x60;\r
+define symbol __ICFEDIT_size_irqstack__ = 0x60;\r
+define symbol __ICFEDIT_size_heap__ = 0x0;\r
+/*-Exports-*/\r
+export symbol __ICFEDIT_region_RAM_start__;\r
+export symbol __ICFEDIT_region_RAM_end__;\r
+export symbol __ICFEDIT_size_vectors__;\r
+export symbol __ICFEDIT_size_cstack__;\r
+export symbol __ICFEDIT_size_svcstack__;\r
+export symbol __ICFEDIT_size_irqstack__;\r
+export symbol __ICFEDIT_size_heap__;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };\r
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+do not initialize { section .noinit };\r
+\r
+place in VEC_region { section .vectors };\r
+place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };\r
+\r
--- /dev/null
+// ----------------------------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ----------------------------------------------------------------------------\r
+// Copyright (c) 2006, Atmel Corporation\r
+// \r
+// All rights reserved.\r
+// \r
+// Redistribution and use in source and binary forms, with or without\r
+// modification, are permitted provided that the following conditions are met:\r
+// \r
+// - Redistributions of source code must retain the above copyright notice,\r
+// this list of conditions and the disclaimer below.\r
+// \r
+// - Redistributions in binary form must reproduce the above copyright notice,\r
+// this list of conditions and the disclaimer below in the documentation and/or\r
+// other materials provided with the distribution. \r
+// \r
+// Atmel's name may not be used to endorse or promote products derived from\r
+// this software without specific prior written permission. \r
+// \r
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+// ----------------------------------------------------------------------------\r
+// File Name : AT91SAM9XE256.h\r
+// Object : AT91SAM9XE256 definitions\r
+// Generated : AT91 SW Application Group 02/13/2008 (18:26:11)\r
+// \r
+// CVS Reference : /AT91SAM9XE256.pl/1.3/Wed Jan 30 13:59:12 2008//\r
+// CVS Reference : /SYS_SAM9260.pl/1.2/Wed Feb 13 13:29:23 2008//\r
+// CVS Reference : /HMATRIX1_SAM9260.pl/1.7/Mon Apr 23 10:39:45 2007//\r
+// CVS Reference : /CCR_SAM9260.pl/1.2/Mon Apr 16 10:47:39 2007//\r
+// CVS Reference : /PMC_SAM9262.pl/1.4/Mon Mar 7 18:03:13 2005//\r
+// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//\r
+// CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004//\r
+// CVS Reference : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//\r
+// CVS Reference : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//\r
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//\r
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//\r
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//\r
+// CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004//\r
+// CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 6 14:16:58 2004//\r
+// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//\r
+// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//\r
+// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//\r
+// CVS Reference : /EFC2_IGS036.pl/1.2/Fri Nov 10 10:47:53 2006//\r
+// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//\r
+// CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 3 13:20:23 2005//\r
+// CVS Reference : /TWI_6061B.pl/1.2/Fri Aug 4 08:53:02 2006//\r
+// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//\r
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//\r
+// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//\r
+// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//\r
+// CVS Reference : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006//\r
+// CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//\r
+// CVS Reference : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005//\r
+// CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 9 17:16:57 2005//\r
+// CVS Reference : /ISI_xxxxx.pl/1.3/Thu Mar 3 11:11:48 2005//\r
+// ----------------------------------------------------------------------------\r
+\r
+#ifndef AT91SAM9XE256_H\r
+#define AT91SAM9XE256_H\r
+\r
+#ifndef __ASSEMBLY__\r
+typedef volatile unsigned int AT91_REG;// Hardware register definition\r
+#define AT91_CAST(a) (a)\r
+#else\r
+#define AT91_CAST(a)\r
+#endif\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR System Peripherals\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SYS {\r
+ AT91_REG Reserved0[2560]; // \r
+ AT91_REG ECC_CR; // ECC reset register\r
+ AT91_REG ECC_MR; // ECC Page size register\r
+ AT91_REG ECC_SR; // ECC Status register\r
+ AT91_REG ECC_PR; // ECC Parity register\r
+ AT91_REG ECC_NPR; // ECC Parity N register\r
+ AT91_REG Reserved1[58]; // \r
+ AT91_REG ECC_VR; // ECC Version register\r
+ AT91_REG Reserved2[64]; // \r
+ AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register\r
+ AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register\r
+ AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register\r
+ AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register\r
+ AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register\r
+ AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register\r
+ AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register\r
+ AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register\r
+ AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register\r
+ AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register\r
+ AT91_REG Reserved3[118]; // \r
+ AT91_REG SMC_SETUP0; // Setup Register for CS 0\r
+ AT91_REG SMC_PULSE0; // Pulse Register for CS 0\r
+ AT91_REG SMC_CYCLE0; // Cycle Register for CS 0\r
+ AT91_REG SMC_CTRL0; // Control Register for CS 0\r
+ AT91_REG SMC_SETUP1; // Setup Register for CS 1\r
+ AT91_REG SMC_PULSE1; // Pulse Register for CS 1\r
+ AT91_REG SMC_CYCLE1; // Cycle Register for CS 1\r
+ AT91_REG SMC_CTRL1; // Control Register for CS 1\r
+ AT91_REG SMC_SETUP2; // Setup Register for CS 2\r
+ AT91_REG SMC_PULSE2; // Pulse Register for CS 2\r
+ AT91_REG SMC_CYCLE2; // Cycle Register for CS 2\r
+ AT91_REG SMC_CTRL2; // Control Register for CS 2\r
+ AT91_REG SMC_SETUP3; // Setup Register for CS 3\r
+ AT91_REG SMC_PULSE3; // Pulse Register for CS 3\r
+ AT91_REG SMC_CYCLE3; // Cycle Register for CS 3\r
+ AT91_REG SMC_CTRL3; // Control Register for CS 3\r
+ AT91_REG SMC_SETUP4; // Setup Register for CS 4\r
+ AT91_REG SMC_PULSE4; // Pulse Register for CS 4\r
+ AT91_REG SMC_CYCLE4; // Cycle Register for CS 4\r
+ AT91_REG SMC_CTRL4; // Control Register for CS 4\r
+ AT91_REG SMC_SETUP5; // Setup Register for CS 5\r
+ AT91_REG SMC_PULSE5; // Pulse Register for CS 5\r
+ AT91_REG SMC_CYCLE5; // Cycle Register for CS 5\r
+ AT91_REG SMC_CTRL5; // Control Register for CS 5\r
+ AT91_REG SMC_SETUP6; // Setup Register for CS 6\r
+ AT91_REG SMC_PULSE6; // Pulse Register for CS 6\r
+ AT91_REG SMC_CYCLE6; // Cycle Register for CS 6\r
+ AT91_REG SMC_CTRL6; // Control Register for CS 6\r
+ AT91_REG SMC_SETUP7; // Setup Register for CS 7\r
+ AT91_REG SMC_PULSE7; // Pulse Register for CS 7\r
+ AT91_REG SMC_CYCLE7; // Cycle Register for CS 7\r
+ AT91_REG SMC_CTRL7; // Control Register for CS 7\r
+ AT91_REG Reserved4[96]; // \r
+ AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k) \r
+ AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom) \r
+ AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs) \r
+ AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi)\r
+ AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge) \r
+ AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox) \r
+ AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k) \r
+ AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog) \r
+ AT91_REG Reserved5[8]; // \r
+ AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k) \r
+ AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom) \r
+ AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs) \r
+ AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi)\r
+ AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge) \r
+ AT91_REG Reserved6[11]; // \r
+ AT91_REG MATRIX_PRAS0; // PRAS0 (ram0) \r
+ AT91_REG MATRIX_PRBS0; // PRBS0 (ram0) \r
+ AT91_REG MATRIX_PRAS1; // PRAS1 (ram1) \r
+ AT91_REG MATRIX_PRBS1; // PRBS1 (ram1) \r
+ AT91_REG MATRIX_PRAS2; // PRAS2 (ram2) \r
+ AT91_REG MATRIX_PRBS2; // PRBS2 (ram2) \r
+ AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs\r
+ AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs\r
+ AT91_REG MATRIX_PRAS4; // PRAS4 : ebi\r
+ AT91_REG MATRIX_PRBS4; // PRBS4 : ebi\r
+ AT91_REG Reserved7[22]; // \r
+ AT91_REG MATRIX_MRCR; // Master Remp Control Register \r
+ AT91_REG Reserved8[6]; // \r
+ AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register\r
+ AT91_REG Reserved9[3]; // \r
+ AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register\r
+ AT91_REG Reserved10[51]; // \r
+ AT91_REG CCFG_MATRIXVERSION; // Version Register\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved11[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved12[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+ AT91_REG Reserved13[45]; // \r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved14[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved15[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+ AT91_REG Reserved16[54]; // \r
+ AT91_REG PIOA_PER; // PIO Enable Register\r
+ AT91_REG PIOA_PDR; // PIO Disable Register\r
+ AT91_REG PIOA_PSR; // PIO Status Register\r
+ AT91_REG Reserved17[1]; // \r
+ AT91_REG PIOA_OER; // Output Enable Register\r
+ AT91_REG PIOA_ODR; // Output Disable Registerr\r
+ AT91_REG PIOA_OSR; // Output Status Register\r
+ AT91_REG Reserved18[1]; // \r
+ AT91_REG PIOA_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOA_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved19[1]; // \r
+ AT91_REG PIOA_SODR; // Set Output Data Register\r
+ AT91_REG PIOA_CODR; // Clear Output Data Register\r
+ AT91_REG PIOA_ODSR; // Output Data Status Register\r
+ AT91_REG PIOA_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOA_IER; // Interrupt Enable Register\r
+ AT91_REG PIOA_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOA_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOA_ISR; // Interrupt Status Register\r
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved20[1]; // \r
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved21[1]; // \r
+ AT91_REG PIOA_ASR; // Select A Register\r
+ AT91_REG PIOA_BSR; // Select B Register\r
+ AT91_REG PIOA_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved22[9]; // \r
+ AT91_REG PIOA_OWER; // Output Write Enable Register\r
+ AT91_REG PIOA_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOA_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved23[213]; // \r
+ AT91_REG PIOB_PER; // PIO Enable Register\r
+ AT91_REG PIOB_PDR; // PIO Disable Register\r
+ AT91_REG PIOB_PSR; // PIO Status Register\r
+ AT91_REG Reserved24[1]; // \r
+ AT91_REG PIOB_OER; // Output Enable Register\r
+ AT91_REG PIOB_ODR; // Output Disable Registerr\r
+ AT91_REG PIOB_OSR; // Output Status Register\r
+ AT91_REG Reserved25[1]; // \r
+ AT91_REG PIOB_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOB_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved26[1]; // \r
+ AT91_REG PIOB_SODR; // Set Output Data Register\r
+ AT91_REG PIOB_CODR; // Clear Output Data Register\r
+ AT91_REG PIOB_ODSR; // Output Data Status Register\r
+ AT91_REG PIOB_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOB_IER; // Interrupt Enable Register\r
+ AT91_REG PIOB_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOB_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOB_ISR; // Interrupt Status Register\r
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved27[1]; // \r
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved28[1]; // \r
+ AT91_REG PIOB_ASR; // Select A Register\r
+ AT91_REG PIOB_BSR; // Select B Register\r
+ AT91_REG PIOB_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved29[9]; // \r
+ AT91_REG PIOB_OWER; // Output Write Enable Register\r
+ AT91_REG PIOB_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOB_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved30[85]; // \r
+ AT91_REG PIOC_PER; // PIO Enable Register\r
+ AT91_REG PIOC_PDR; // PIO Disable Register\r
+ AT91_REG PIOC_PSR; // PIO Status Register\r
+ AT91_REG Reserved31[1]; // \r
+ AT91_REG PIOC_OER; // Output Enable Register\r
+ AT91_REG PIOC_ODR; // Output Disable Registerr\r
+ AT91_REG PIOC_OSR; // Output Status Register\r
+ AT91_REG Reserved32[1]; // \r
+ AT91_REG PIOC_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOC_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOC_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved33[1]; // \r
+ AT91_REG PIOC_SODR; // Set Output Data Register\r
+ AT91_REG PIOC_CODR; // Clear Output Data Register\r
+ AT91_REG PIOC_ODSR; // Output Data Status Register\r
+ AT91_REG PIOC_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOC_IER; // Interrupt Enable Register\r
+ AT91_REG PIOC_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOC_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOC_ISR; // Interrupt Status Register\r
+ AT91_REG PIOC_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOC_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOC_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved34[1]; // \r
+ AT91_REG PIOC_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOC_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOC_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved35[1]; // \r
+ AT91_REG PIOC_ASR; // Select A Register\r
+ AT91_REG PIOC_BSR; // Select B Register\r
+ AT91_REG PIOC_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved36[9]; // \r
+ AT91_REG PIOC_OWER; // Output Write Enable Register\r
+ AT91_REG PIOC_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOC_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved37[85]; // \r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved38[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved39[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG PMC_PLLAR; // PLL A Register\r
+ AT91_REG PMC_PLLBR; // PLL B Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved40[3]; // \r
+ AT91_REG PMC_PCKR[8]; // Programmable Clock Register\r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved41[36]; // \r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+ AT91_REG Reserved42[1]; // \r
+ AT91_REG SHDWC_SHCR; // Shut Down Control Register\r
+ AT91_REG SHDWC_SHMR; // Shut Down Mode Register\r
+ AT91_REG SHDWC_SHSR; // Shut Down Status Register\r
+ AT91_REG Reserved43[1]; // \r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+ AT91_REG Reserved44[1]; // \r
+ AT91_REG SYS_GPBR[4]; // General Purpose Register\r
+} AT91S_SYS, *AT91PS_SYS;\r
+#else\r
+#define SYS_GPBR (AT91_CAST(AT91_REG *) 0x00003D50) // (SYS_GPBR) General Purpose Register\r
+\r
+#endif\r
+// -------- GPBR : (SYS Offset: 0x3d50) GPBR General Purpose Register -------- \r
+#define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR External Bus Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_EBI {\r
+ AT91_REG EBI_DUMMY; // Dummy register - Do not use\r
+} AT91S_EBI, *AT91PS_EBI;\r
+#else\r
+#define EBI_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI_DUMMY) Dummy register - Do not use\r
+\r
+#endif\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Error Correction Code controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_ECC {\r
+ AT91_REG ECC_CR; // ECC reset register\r
+ AT91_REG ECC_MR; // ECC Page size register\r
+ AT91_REG ECC_SR; // ECC Status register\r
+ AT91_REG ECC_PR; // ECC Parity register\r
+ AT91_REG ECC_NPR; // ECC Parity N register\r
+ AT91_REG Reserved0[58]; // \r
+ AT91_REG ECC_VR; // ECC Version register\r
+} AT91S_ECC, *AT91PS_ECC;\r
+#else\r
+#define ECC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ECC_CR) ECC reset register\r
+#define ECC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ECC_MR) ECC Page size register\r
+#define ECC_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ECC_SR) ECC Status register\r
+#define ECC_PR (AT91_CAST(AT91_REG *) 0x0000000C) // (ECC_PR) ECC Parity register\r
+#define ECC_NPR (AT91_CAST(AT91_REG *) 0x00000010) // (ECC_NPR) ECC Parity N register\r
+#define ECC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (ECC_VR) ECC Version register\r
+\r
+#endif\r
+// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register -------- \r
+#define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity\r
+// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register -------- \r
+#define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size\r
+// -------- ECC_SR : (ECC Offset: 0x8) ECC status register -------- \r
+#define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error\r
+#define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error\r
+#define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR\r
+// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register -------- \r
+#define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error\r
+#define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit\r
+// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register -------- \r
+#define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N \r
+// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register -------- \r
+#define AT91C_ECC_VR (0xF << 0) // (ECC) ECC version register\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR SDRAM Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SDRAMC {\r
+ AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register\r
+ AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register\r
+ AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register\r
+ AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register\r
+ AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register\r
+ AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register\r
+ AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register\r
+ AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register\r
+ AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register\r
+ AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register\r
+} AT91S_SDRAMC, *AT91PS_SDRAMC;\r
+#else\r
+#define SDRAMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register\r
+#define SDRAMC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register\r
+#define SDRAMC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register\r
+#define SDRAMC_HSR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register\r
+#define SDRAMC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register\r
+#define SDRAMC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register\r
+#define SDRAMC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register\r
+#define SDRAMC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register\r
+#define SDRAMC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register\r
+#define SDRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register\r
+\r
+#endif\r
+// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register -------- \r
+#define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode\r
+#define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode\r
+#define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access\r
+#define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access\r
+#define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access\r
+#define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh\r
+#define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register\r
+#define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode\r
+// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register -------- \r
+#define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter\r
+// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register -------- \r
+#define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits\r
+#define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits\r
+#define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits\r
+#define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits\r
+#define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits\r
+#define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits\r
+#define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits\r
+#define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits\r
+#define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits\r
+#define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks\r
+#define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks\r
+#define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks\r
+#define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency\r
+#define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles\r
+#define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles\r
+#define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width\r
+#define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus\r
+#define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus\r
+#define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles\r
+#define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15\r
+#define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles\r
+#define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15\r
+#define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles\r
+#define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15\r
+#define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles\r
+#define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15\r
+#define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles\r
+#define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15\r
+#define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles\r
+#define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15\r
+// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register -------- \r
+#define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit\r
+#define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle\r
+#define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle\r
+// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register -------- \r
+#define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations\r
+#define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features\r
+#define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH\r
+#define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN\r
+#define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN\r
+#define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)\r
+#define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)\r
+#define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)\r
+#define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled\r
+#define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately\r
+#define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer\r
+#define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer\r
+// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- \r
+#define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status\r
+// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- \r
+// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- \r
+// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- \r
+// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register -------- \r
+#define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type\r
+#define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode\r
+#define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Static Memory Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SMC {\r
+ AT91_REG SMC_SETUP0; // Setup Register for CS 0\r
+ AT91_REG SMC_PULSE0; // Pulse Register for CS 0\r
+ AT91_REG SMC_CYCLE0; // Cycle Register for CS 0\r
+ AT91_REG SMC_CTRL0; // Control Register for CS 0\r
+ AT91_REG SMC_SETUP1; // Setup Register for CS 1\r
+ AT91_REG SMC_PULSE1; // Pulse Register for CS 1\r
+ AT91_REG SMC_CYCLE1; // Cycle Register for CS 1\r
+ AT91_REG SMC_CTRL1; // Control Register for CS 1\r
+ AT91_REG SMC_SETUP2; // Setup Register for CS 2\r
+ AT91_REG SMC_PULSE2; // Pulse Register for CS 2\r
+ AT91_REG SMC_CYCLE2; // Cycle Register for CS 2\r
+ AT91_REG SMC_CTRL2; // Control Register for CS 2\r
+ AT91_REG SMC_SETUP3; // Setup Register for CS 3\r
+ AT91_REG SMC_PULSE3; // Pulse Register for CS 3\r
+ AT91_REG SMC_CYCLE3; // Cycle Register for CS 3\r
+ AT91_REG SMC_CTRL3; // Control Register for CS 3\r
+ AT91_REG SMC_SETUP4; // Setup Register for CS 4\r
+ AT91_REG SMC_PULSE4; // Pulse Register for CS 4\r
+ AT91_REG SMC_CYCLE4; // Cycle Register for CS 4\r
+ AT91_REG SMC_CTRL4; // Control Register for CS 4\r
+ AT91_REG SMC_SETUP5; // Setup Register for CS 5\r
+ AT91_REG SMC_PULSE5; // Pulse Register for CS 5\r
+ AT91_REG SMC_CYCLE5; // Cycle Register for CS 5\r
+ AT91_REG SMC_CTRL5; // Control Register for CS 5\r
+ AT91_REG SMC_SETUP6; // Setup Register for CS 6\r
+ AT91_REG SMC_PULSE6; // Pulse Register for CS 6\r
+ AT91_REG SMC_CYCLE6; // Cycle Register for CS 6\r
+ AT91_REG SMC_CTRL6; // Control Register for CS 6\r
+ AT91_REG SMC_SETUP7; // Setup Register for CS 7\r
+ AT91_REG SMC_PULSE7; // Pulse Register for CS 7\r
+ AT91_REG SMC_CYCLE7; // Cycle Register for CS 7\r
+ AT91_REG SMC_CTRL7; // Control Register for CS 7\r
+} AT91S_SMC, *AT91PS_SMC;\r
+#else\r
+#define SETUP0 (AT91_CAST(AT91_REG *) 0x00000000) // (SETUP0) Setup Register for CS 0\r
+#define PULSE0 (AT91_CAST(AT91_REG *) 0x00000004) // (PULSE0) Pulse Register for CS 0\r
+#define CYCLE0 (AT91_CAST(AT91_REG *) 0x00000008) // (CYCLE0) Cycle Register for CS 0\r
+#define CTRL0 (AT91_CAST(AT91_REG *) 0x0000000C) // (CTRL0) Control Register for CS 0\r
+#define SETUP1 (AT91_CAST(AT91_REG *) 0x00000010) // (SETUP1) Setup Register for CS 1\r
+#define PULSE1 (AT91_CAST(AT91_REG *) 0x00000014) // (PULSE1) Pulse Register for CS 1\r
+#define CYCLE1 (AT91_CAST(AT91_REG *) 0x00000018) // (CYCLE1) Cycle Register for CS 1\r
+#define CTRL1 (AT91_CAST(AT91_REG *) 0x0000001C) // (CTRL1) Control Register for CS 1\r
+#define SETUP2 (AT91_CAST(AT91_REG *) 0x00000020) // (SETUP2) Setup Register for CS 2\r
+#define PULSE2 (AT91_CAST(AT91_REG *) 0x00000024) // (PULSE2) Pulse Register for CS 2\r
+#define CYCLE2 (AT91_CAST(AT91_REG *) 0x00000028) // (CYCLE2) Cycle Register for CS 2\r
+#define CTRL2 (AT91_CAST(AT91_REG *) 0x0000002C) // (CTRL2) Control Register for CS 2\r
+#define SETUP3 (AT91_CAST(AT91_REG *) 0x00000030) // (SETUP3) Setup Register for CS 3\r
+#define PULSE3 (AT91_CAST(AT91_REG *) 0x00000034) // (PULSE3) Pulse Register for CS 3\r
+#define CYCLE3 (AT91_CAST(AT91_REG *) 0x00000038) // (CYCLE3) Cycle Register for CS 3\r
+#define CTRL3 (AT91_CAST(AT91_REG *) 0x0000003C) // (CTRL3) Control Register for CS 3\r
+#define SETUP4 (AT91_CAST(AT91_REG *) 0x00000040) // (SETUP4) Setup Register for CS 4\r
+#define PULSE4 (AT91_CAST(AT91_REG *) 0x00000044) // (PULSE4) Pulse Register for CS 4\r
+#define CYCLE4 (AT91_CAST(AT91_REG *) 0x00000048) // (CYCLE4) Cycle Register for CS 4\r
+#define CTRL4 (AT91_CAST(AT91_REG *) 0x0000004C) // (CTRL4) Control Register for CS 4\r
+#define SETUP5 (AT91_CAST(AT91_REG *) 0x00000050) // (SETUP5) Setup Register for CS 5\r
+#define PULSE5 (AT91_CAST(AT91_REG *) 0x00000054) // (PULSE5) Pulse Register for CS 5\r
+#define CYCLE5 (AT91_CAST(AT91_REG *) 0x00000058) // (CYCLE5) Cycle Register for CS 5\r
+#define CTRL5 (AT91_CAST(AT91_REG *) 0x0000005C) // (CTRL5) Control Register for CS 5\r
+#define SETUP6 (AT91_CAST(AT91_REG *) 0x00000060) // (SETUP6) Setup Register for CS 6\r
+#define PULSE6 (AT91_CAST(AT91_REG *) 0x00000064) // (PULSE6) Pulse Register for CS 6\r
+#define CYCLE6 (AT91_CAST(AT91_REG *) 0x00000068) // (CYCLE6) Cycle Register for CS 6\r
+#define CTRL6 (AT91_CAST(AT91_REG *) 0x0000006C) // (CTRL6) Control Register for CS 6\r
+#define SETUP7 (AT91_CAST(AT91_REG *) 0x00000070) // (SETUP7) Setup Register for CS 7\r
+#define PULSE7 (AT91_CAST(AT91_REG *) 0x00000074) // (PULSE7) Pulse Register for CS 7\r
+#define CYCLE7 (AT91_CAST(AT91_REG *) 0x00000078) // (CYCLE7) Cycle Register for CS 7\r
+#define CTRL7 (AT91_CAST(AT91_REG *) 0x0000007C) // (CTRL7) Control Register for CS 7\r
+\r
+#endif\r
+// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x -------- \r
+#define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length\r
+#define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access\r
+#define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length\r
+#define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access\r
+// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x -------- \r
+#define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length\r
+#define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access\r
+#define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length\r
+#define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access\r
+// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x -------- \r
+#define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length\r
+#define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length\r
+// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x -------- \r
+#define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode\r
+#define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode\r
+#define AT91C_SMC_NWAITM (0x3 << 4) // (SMC) NWAIT Mode\r
+#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 4) // (SMC) External NWAIT disabled.\r
+#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 4) // (SMC) External NWAIT enabled in frozen mode.\r
+#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 4) // (SMC) External NWAIT enabled in ready mode.\r
+#define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type\r
+#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.\r
+#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.\r
+#define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width\r
+#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits.\r
+#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits.\r
+#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.\r
+#define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time.\r
+#define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled.\r
+#define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled.\r
+#define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size\r
+#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes.\r
+#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes.\r
+#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes.\r
+#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.\r
+// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR AHB Matrix Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_MATRIX {\r
+ AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k) \r
+ AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom) \r
+ AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs) \r
+ AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi)\r
+ AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge) \r
+ AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox) \r
+ AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k) \r
+ AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog) \r
+ AT91_REG Reserved0[8]; // \r
+ AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k) \r
+ AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom) \r
+ AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs) \r
+ AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi)\r
+ AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge) \r
+ AT91_REG Reserved1[11]; // \r
+ AT91_REG MATRIX_PRAS0; // PRAS0 (ram0) \r
+ AT91_REG MATRIX_PRBS0; // PRBS0 (ram0) \r
+ AT91_REG MATRIX_PRAS1; // PRAS1 (ram1) \r
+ AT91_REG MATRIX_PRBS1; // PRBS1 (ram1) \r
+ AT91_REG MATRIX_PRAS2; // PRAS2 (ram2) \r
+ AT91_REG MATRIX_PRBS2; // PRBS2 (ram2) \r
+ AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs\r
+ AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs\r
+ AT91_REG MATRIX_PRAS4; // PRAS4 : ebi\r
+ AT91_REG MATRIX_PRBS4; // PRBS4 : ebi\r
+ AT91_REG Reserved2[22]; // \r
+ AT91_REG MATRIX_MRCR; // Master Remp Control Register \r
+ AT91_REG Reserved3[6]; // \r
+ AT91_REG MATRIX_EBI; // Slave 3 (ebi) Special Function Register\r
+ AT91_REG Reserved4[3]; // \r
+ AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register\r
+ AT91_REG Reserved5[51]; // \r
+ AT91_REG MATRIX_VERSION; // Version Register\r
+} AT91S_MATRIX, *AT91PS_MATRIX;\r
+#else\r
+#define MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG0) Master Configuration Register 0 (ram96k) \r
+#define MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_MCFG1) Master Configuration Register 1 (rom) \r
+#define MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_MCFG2) Master Configuration Register 2 (hperiphs) \r
+#define MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_MCFG3) Master Configuration Register 3 (ebi)\r
+#define MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_MCFG4) Master Configuration Register 4 (bridge) \r
+#define MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_MCFG5) Master Configuration Register 5 (mailbox) \r
+#define MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x00000018) // (MATRIX_MCFG6) Master Configuration Register 6 (ram16k) \r
+#define MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x0000001C) // (MATRIX_MCFG7) Master Configuration Register 7 (teak_prog) \r
+#define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG0) Slave Configuration Register 0 (ram96k) \r
+#define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_SCFG1) Slave Configuration Register 1 (rom) \r
+#define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x00000048) // (MATRIX_SCFG2) Slave Configuration Register 2 (hperiphs) \r
+#define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x0000004C) // (MATRIX_SCFG3) Slave Configuration Register 3 (ebi)\r
+#define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000050) // (MATRIX_SCFG4) Slave Configuration Register 4 (bridge) \r
+#define MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0x00000080) // (MATRIX_PRAS0) PRAS0 (ram0) \r
+#define MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0x00000084) // (MATRIX_PRBS0) PRBS0 (ram0) \r
+#define MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0x00000088) // (MATRIX_PRAS1) PRAS1 (ram1) \r
+#define MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0x0000008C) // (MATRIX_PRBS1) PRBS1 (ram1) \r
+#define MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0x00000090) // (MATRIX_PRAS2) PRAS2 (ram2) \r
+#define MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0x00000094) // (MATRIX_PRBS2) PRBS2 (ram2) \r
+#define MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0x00000098) // (MATRIX_PRAS3) PRAS3 : usb_dev_hs\r
+#define MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0x0000009C) // (MATRIX_PRBS3) PRBS3 : usb_dev_hs\r
+#define MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0x000000A0) // (MATRIX_PRAS4) PRAS4 : ebi\r
+#define MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0x000000A4) // (MATRIX_PRBS4) PRBS4 : ebi\r
+#define MATRIX_MRCR (AT91_CAST(AT91_REG *) 0x00000100) // (MATRIX_MRCR) Master Remp Control Register \r
+#define MATRIX_EBI (AT91_CAST(AT91_REG *) 0x0000011C) // (MATRIX_EBI) Slave 3 (ebi) Special Function Register\r
+#define MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0x0000012C) // (MATRIX_TEAKCFG) Slave 7 (teak_prog) Special Function Register\r
+#define MATRIX_VERSION (AT91_CAST(AT91_REG *) 0x000001FC) // (MATRIX_VERSION) Version Register\r
+\r
+#endif\r
+// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- \r
+#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst\r
+#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type\r
+#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.\r
+#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.\r
+#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master\r
+// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master\r
+// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master\r
+// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR3_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master\r
+// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master\r
+// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register -------- \r
+#define AT91C_MATRIX_M0PR (0x3 << 0) // (MATRIX) ARM926EJ-S Instruction priority\r
+#define AT91C_MATRIX_M1PR (0x3 << 4) // (MATRIX) ARM926EJ-S Data priority\r
+#define AT91C_MATRIX_M2PR (0x3 << 8) // (MATRIX) PDC priority\r
+#define AT91C_MATRIX_M3PR (0x3 << 12) // (MATRIX) LCDC priority\r
+#define AT91C_MATRIX_M4PR (0x3 << 16) // (MATRIX) 2DGC priority\r
+#define AT91C_MATRIX_M5PR (0x3 << 20) // (MATRIX) ISI priority\r
+#define AT91C_MATRIX_M6PR (0x3 << 24) // (MATRIX) DMA priority\r
+#define AT91C_MATRIX_M7PR (0x3 << 28) // (MATRIX) EMAC priority\r
+// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register -------- \r
+#define AT91C_MATRIX_M8PR (0x3 << 0) // (MATRIX) USB priority\r
+// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register -------- \r
+// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register -------- \r
+// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register -------- \r
+// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register -------- \r
+// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register -------- \r
+// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register -------- \r
+// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register -------- \r
+// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register -------- \r
+// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register -------- \r
+#define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master\r
+#define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command for ARM926EJ-S Data Master\r
+// -------- MATRIX_EBI : (MATRIX Offset: 0x11c) EBI (Slave 3) Special Function Register -------- \r
+#define AT91C_MATRIX_CS1A (0x1 << 1) // (MATRIX) Chip Select 1 Assignment\r
+#define AT91C_MATRIX_CS1A_SMC (0x0 << 1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller.\r
+#define AT91C_MATRIX_CS1A_SDRAMC (0x1 << 1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller.\r
+#define AT91C_MATRIX_CS3A (0x1 << 3) // (MATRIX) Chip Select 3 Assignment\r
+#define AT91C_MATRIX_CS3A_SMC (0x0 << 3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.\r
+#define AT91C_MATRIX_CS3A_SM (0x1 << 3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.\r
+#define AT91C_MATRIX_CS4A (0x1 << 4) // (MATRIX) Chip Select 4 Assignment\r
+#define AT91C_MATRIX_CS4A_SMC (0x0 << 4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.\r
+#define AT91C_MATRIX_CS4A_CF (0x1 << 4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.\r
+#define AT91C_MATRIX_CS5A (0x1 << 5) // (MATRIX) Chip Select 5 Assignment\r
+#define AT91C_MATRIX_CS5A_SMC (0x0 << 5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC\r
+#define AT91C_MATRIX_CS5A_CF (0x1 << 5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.\r
+#define AT91C_MATRIX_DBPUC (0x1 << 8) // (MATRIX) Data Bus Pull-up Configuration\r
+// -------- MATRIX_TEAKCFG : (MATRIX Offset: 0x12c) Slave 7 Special Function Register -------- \r
+#define AT91C_TEAK_PROGRAM_ACCESS (0x1 << 0) // (MATRIX) TEAK program memory access from AHB\r
+#define AT91C_TEAK_PROGRAM_ACCESS_DISABLED (0x0) // (MATRIX) TEAK program access disabled\r
+#define AT91C_TEAK_PROGRAM_ACCESS_ENABLED (0x1) // (MATRIX) TEAK program access enabled\r
+#define AT91C_TEAK_BOOT (0x1 << 1) // (MATRIX) TEAK program start from boot routine\r
+#define AT91C_TEAK_BOOT_DISABLED (0x0 << 1) // (MATRIX) TEAK program starts from boot routine disabled\r
+#define AT91C_TEAK_BOOT_ENABLED (0x1 << 1) // (MATRIX) TEAK program starts from boot routine enabled\r
+#define AT91C_TEAK_NRESET (0x1 << 2) // (MATRIX) active low TEAK reset\r
+#define AT91C_TEAK_NRESET_ENABLED (0x0 << 2) // (MATRIX) active low TEAK reset enabled\r
+#define AT91C_TEAK_NRESET_DISABLED (0x1 << 2) // (MATRIX) active low TEAK reset disabled\r
+#define AT91C_TEAK_LVECTORP (0x3FFFF << 14) // (MATRIX) boot routine start address\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Chip Configuration Registers\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_CCFG {\r
+ AT91_REG Reserved0[3]; // \r
+ AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register\r
+ AT91_REG Reserved1[55]; // \r
+ AT91_REG CCFG_MATRIXVERSION; // Version Register\r
+} AT91S_CCFG, *AT91PS_CCFG;\r
+#else\r
+#define CCFG_EBICSA (AT91_CAST(AT91_REG *) 0x0000000C) // (CCFG_EBICSA) EBI Chip Select Assignement Register\r
+#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0x000000EC) // (CCFG_MATRIXVERSION) Version Register\r
+\r
+#endif\r
+// -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register -------- \r
+#define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment\r
+#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.\r
+#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller.\r
+#define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment\r
+#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.\r
+#define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.\r
+#define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment\r
+#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.\r
+#define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.\r
+#define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment\r
+#define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC\r
+#define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.\r
+#define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration\r
+#define AT91C_EBI_SUPPLY (0x1 << 16) // (CCFG) EBI supply selection\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PDC {\r
+ AT91_REG PDC_RPR; // Receive Pointer Register\r
+ AT91_REG PDC_RCR; // Receive Counter Register\r
+ AT91_REG PDC_TPR; // Transmit Pointer Register\r
+ AT91_REG PDC_TCR; // Transmit Counter Register\r
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG PDC_RNCR; // Receive Next Counter Register\r
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register\r
+} AT91S_PDC, *AT91PS_PDC;\r
+#else\r
+#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register\r
+#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register\r
+#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register\r
+#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register\r
+#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register\r
+#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register\r
+#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register\r
+#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register\r
+#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register\r
+#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register\r
+\r
+#endif\r
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable\r
+#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable\r
+#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable\r
+#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable\r
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Debug Unit\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_DBGU {\r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved0[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved1[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+} AT91S_DBGU, *AT91PS_DBGU;\r
+#else\r
+#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register\r
+#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register\r
+#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register\r
+#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register\r
+#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register\r
+#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register\r
+#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register\r
+#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register\r
+#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register\r
+#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register\r
+#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register\r
+#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register\r
+\r
+#endif\r
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver\r
+#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter\r
+#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable\r
+#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable\r
+#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable\r
+#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable\r
+#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits\r
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type\r
+#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity\r
+#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity\r
+#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)\r
+#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)\r
+#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity\r
+#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode\r
+#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode\r
+#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt\r
+#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt\r
+#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt\r
+#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt\r
+#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt\r
+#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt\r
+#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt\r
+#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt\r
+#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt\r
+#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt\r
+#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt\r
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_AIC {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+} AT91S_AIC, *AT91PS_AIC;\r
+#else\r
+#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register\r
+#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register\r
+#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register\r
+#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register\r
+#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register\r
+#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register\r
+#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register\r
+#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register\r
+#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register\r
+#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register\r
+#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register\r
+#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register\r
+#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register\r
+#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register\r
+#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)\r
+#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register\r
+#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register\r
+#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register\r
+\r
+#endif\r
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level\r
+#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level\r
+#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level\r
+#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type\r
+#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive\r
+#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered\r
+#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered\r
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status\r
+#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status\r
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode\r
+#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PIO {\r
+ AT91_REG PIO_PER; // PIO Enable Register\r
+ AT91_REG PIO_PDR; // PIO Disable Register\r
+ AT91_REG PIO_PSR; // PIO Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PIO_OER; // Output Enable Register\r
+ AT91_REG PIO_ODR; // Output Disable Registerr\r
+ AT91_REG PIO_OSR; // Output Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PIO_IFER; // Input Filter Enable Register\r
+ AT91_REG PIO_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIO_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PIO_SODR; // Set Output Data Register\r
+ AT91_REG PIO_CODR; // Clear Output Data Register\r
+ AT91_REG PIO_ODSR; // Output Data Status Register\r
+ AT91_REG PIO_PDSR; // Pin Data Status Register\r
+ AT91_REG PIO_IER; // Interrupt Enable Register\r
+ AT91_REG PIO_IDR; // Interrupt Disable Register\r
+ AT91_REG PIO_IMR; // Interrupt Mask Register\r
+ AT91_REG PIO_ISR; // Interrupt Status Register\r
+ AT91_REG PIO_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIO_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved3[1]; // \r
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIO_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIO_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved4[1]; // \r
+ AT91_REG PIO_ASR; // Select A Register\r
+ AT91_REG PIO_BSR; // Select B Register\r
+ AT91_REG PIO_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved5[9]; // \r
+ AT91_REG PIO_OWER; // Output Write Enable Register\r
+ AT91_REG PIO_OWDR; // Output Write Disable Register\r
+ AT91_REG PIO_OWSR; // Output Write Status Register\r
+} AT91S_PIO, *AT91PS_PIO;\r
+#else\r
+#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register\r
+#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register\r
+#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register\r
+#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register\r
+#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr\r
+#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register\r
+#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register\r
+#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register\r
+#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register\r
+#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register\r
+#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register\r
+#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register\r
+#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register\r
+#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register\r
+#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register\r
+#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register\r
+#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register\r
+#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register\r
+#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register\r
+#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register\r
+#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register\r
+#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register\r
+#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register\r
+#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register\r
+#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register\r
+#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register\r
+#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register\r
+#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register\r
+#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register\r
+\r
+#endif\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Embedded Flash Controller 2.0\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_EFC {\r
+ AT91_REG EFC_FMR; // EFC Flash Mode Register\r
+ AT91_REG EFC_FCR; // EFC Flash Command Register\r
+ AT91_REG EFC_FSR; // EFC Flash Status Register\r
+ AT91_REG EFC_FRR; // EFC Flash Result Register\r
+ AT91_REG EFC_FVR; // EFC Flash Version Register\r
+} AT91S_EFC, *AT91PS_EFC;\r
+#else\r
+#define EFC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (EFC_FMR) EFC Flash Mode Register\r
+#define EFC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (EFC_FCR) EFC Flash Command Register\r
+#define EFC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (EFC_FSR) EFC Flash Status Register\r
+#define EFC_FRR (AT91_CAST(AT91_REG *) 0x0000000C) // (EFC_FRR) EFC Flash Result Register\r
+#define EFC_FVR (AT91_CAST(AT91_REG *) 0x00000010) // (EFC_FVR) EFC Flash Version Register\r
+\r
+#endif\r
+// -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register -------- \r
+#define AT91C_EFC_FRDY (0x1 << 0) // (EFC) Ready Interrupt Enable\r
+#define AT91C_EFC_FWS (0xF << 8) // (EFC) Flash Wait State.\r
+#define AT91C_EFC_FWS_0WS (0x0 << 8) // (EFC) 0 Wait State\r
+#define AT91C_EFC_FWS_1WS (0x1 << 8) // (EFC) 1 Wait State\r
+#define AT91C_EFC_FWS_2WS (0x2 << 8) // (EFC) 2 Wait States\r
+#define AT91C_EFC_FWS_3WS (0x3 << 8) // (EFC) 3 Wait States\r
+// -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register -------- \r
+#define AT91C_EFC_FCMD (0xFF << 0) // (EFC) Flash Command\r
+#define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor\r
+#define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page\r
+#define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock\r
+#define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page\r
+#define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock\r
+#define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All\r
+#define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase Plane\r
+#define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase Pages\r
+#define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit\r
+#define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit\r
+#define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit\r
+#define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit\r
+#define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit\r
+#define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit\r
+#define AT91C_EFC_FARG (0xFFFF << 8) // (EFC) Flash Command Argument\r
+#define AT91C_EFC_FKEY (0xFF << 24) // (EFC) Flash Writing Protection Key\r
+// -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register -------- \r
+#define AT91C_EFC_FRDY_S (0x1 << 0) // (EFC) Flash Ready Status\r
+#define AT91C_EFC_FCMDE (0x1 << 1) // (EFC) Flash Command Error Status\r
+#define AT91C_EFC_LOCKE (0x1 << 2) // (EFC) Flash Lock Error Status\r
+// -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register -------- \r
+#define AT91C_EFC_FVALUE (0x0 << 0) // (EFC) Flash Result Value\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_CKGR {\r
+ AT91_REG CKGR_MOR; // Main Oscillator Register\r
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register\r
+ AT91_REG CKGR_PLLAR; // PLL A Register\r
+ AT91_REG CKGR_PLLBR; // PLL B Register\r
+} AT91S_CKGR, *AT91PS_CKGR;\r
+#else\r
+#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register\r
+#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register\r
+#define CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x00000008) // (CKGR_PLLAR) PLL A Register\r
+#define CKGR_PLLBR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLBR) PLL B Register\r
+\r
+#endif\r
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable\r
+#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass\r
+#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time\r
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency\r
+#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready\r
+// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- \r
+#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected\r
+#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0\r
+#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed\r
+#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter\r
+#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range\r
+#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet\r
+#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet\r
+#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet\r
+#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet\r
+#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier\r
+#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR) \r
+// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- \r
+#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected\r
+#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0\r
+#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed\r
+#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter\r
+#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range\r
+#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet\r
+#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet\r
+#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet\r
+#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet\r
+#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier\r
+#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks\r
+#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output\r
+#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2\r
+#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Power Management Controler\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PMC {\r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG PMC_PLLAR; // PLL A Register\r
+ AT91_REG PMC_PLLBR; // PLL B Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved2[3]; // \r
+ AT91_REG PMC_PCKR[8]; // Programmable Clock Register\r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+} AT91S_PMC, *AT91PS_PMC;\r
+#else\r
+#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register\r
+#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register\r
+#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register\r
+#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register\r
+#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register\r
+#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register\r
+#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register\r
+#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register\r
+#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register\r
+#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register\r
+#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register\r
+#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register\r
+\r
+#endif\r
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock\r
+#define AT91C_PMC_OTG (0x1 << 5) // (PMC) USB OTG Clock\r
+#define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock\r
+#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock\r
+#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output\r
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- \r
+// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection\r
+#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected\r
+#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected\r
+#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected\r
+#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected\r
+#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler\r
+#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock\r
+#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2\r
+#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4\r
+#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8\r
+#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16\r
+#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32\r
+#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64\r
+#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division\r
+#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same\r
+#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock\r
+#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is four times faster than the master clock\r
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_RSTC {\r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+} AT91S_RSTC, *AT91PS_RSTC;\r
+#else\r
+#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register\r
+#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register\r
+#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register\r
+\r
+#endif\r
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset\r
+#define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset\r
+#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset\r
+#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset\r
+#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password\r
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status\r
+#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type\r
+#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.\r
+#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.\r
+#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.\r
+#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level\r
+#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable\r
+#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Shut Down Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SHDWC {\r
+ AT91_REG SHDWC_SHCR; // Shut Down Control Register\r
+ AT91_REG SHDWC_SHMR; // Shut Down Mode Register\r
+ AT91_REG SHDWC_SHSR; // Shut Down Status Register\r
+} AT91S_SHDWC, *AT91PS_SHDWC;\r
+#else\r
+#define SHDWC_SHCR (AT91_CAST(AT91_REG *) 0x00000000) // (SHDWC_SHCR) Shut Down Control Register\r
+#define SHDWC_SHMR (AT91_CAST(AT91_REG *) 0x00000004) // (SHDWC_SHMR) Shut Down Mode Register\r
+#define SHDWC_SHSR (AT91_CAST(AT91_REG *) 0x00000008) // (SHDWC_SHSR) Shut Down Status Register\r
+\r
+#endif\r
+// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- \r
+#define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset\r
+#define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password\r
+// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- \r
+#define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection\r
+#define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input.\r
+#define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level.\r
+#define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level.\r
+#define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change.\r
+#define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0\r
+#define AT91C_SHDWC_WKMODE1 (0x3 << 8) // (SHDWC) Wake Up 1 Mode Selection\r
+#define AT91C_SHDWC_WKMODE1_NONE (0x0 << 8) // (SHDWC) None. No detection is performed on the wake up input.\r
+#define AT91C_SHDWC_WKMODE1_HIGH (0x1 << 8) // (SHDWC) High Level.\r
+#define AT91C_SHDWC_WKMODE1_LOW (0x2 << 8) // (SHDWC) Low Level.\r
+#define AT91C_SHDWC_WKMODE1_ANYLEVEL (0x3 << 8) // (SHDWC) Any level change.\r
+#define AT91C_SHDWC_CPTWK1 (0xF << 12) // (SHDWC) Counter On Wake Up 1\r
+#define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable\r
+#define AT91C_SHDWC_RTCWKEN (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable\r
+// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- \r
+#define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status\r
+#define AT91C_SHDWC_WAKEUP1 (0x1 << 1) // (SHDWC) Wake Up 1 Status\r
+#define AT91C_SHDWC_FWKUP (0x1 << 2) // (SHDWC) Force Wake Up Status\r
+#define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up\r
+#define AT91C_SHDWC_RTCWK (0x1 << 17) // (SHDWC) Real Time Clock wake Up\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_RTTC {\r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+} AT91S_RTTC, *AT91PS_RTTC;\r
+#else\r
+#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register\r
+#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register\r
+#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register\r
+#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register\r
+\r
+#endif\r
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
+#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
+#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
+#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart\r
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value\r
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value\r
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status\r
+#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PITC {\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+} AT91S_PITC, *AT91PS_PITC;\r
+#else\r
+#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register\r
+#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register\r
+#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register\r
+#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register\r
+\r
+#endif\r
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value\r
+#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
+#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable\r
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status\r
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value\r
+#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter\r
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_WDTC {\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+} AT91S_WDTC, *AT91PS_WDTC;\r
+#else\r
+#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register\r
+#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register\r
+#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register\r
+\r
+#endif\r
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart\r
+#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password\r
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
+#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable\r
+#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable\r
+#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value\r
+#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt\r
+#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt\r
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow\r
+#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_TC {\r
+ AT91_REG TC_CCR; // Channel Control Register\r
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TC_CV; // Counter Value\r
+ AT91_REG TC_RA; // Register A\r
+ AT91_REG TC_RB; // Register B\r
+ AT91_REG TC_RC; // Register C\r
+ AT91_REG TC_SR; // Status Register\r
+ AT91_REG TC_IER; // Interrupt Enable Register\r
+ AT91_REG TC_IDR; // Interrupt Disable Register\r
+ AT91_REG TC_IMR; // Interrupt Mask Register\r
+} AT91S_TC, *AT91PS_TC;\r
+#else\r
+#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register\r
+#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value\r
+#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A\r
+#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B\r
+#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C\r
+#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register\r
+#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register\r
+#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register\r
+#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register\r
+\r
+#endif\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection\r
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
+#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0\r
+#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1\r
+#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2\r
+#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert\r
+#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection\r
+#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal\r
+#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock\r
+#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading\r
+#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading\r
+#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection\r
+#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection\r
+#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection\r
+#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
+#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection\r
+#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE (0x1 << 15) // (TC) \r
+#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none\r
+#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set\r
+#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear\r
+#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection\r
+#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None\r
+#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none\r
+#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set\r
+#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear\r
+#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection\r
+#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None\r
+#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none\r
+#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set\r
+#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear\r
+#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none\r
+#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set\r
+#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear\r
+#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none\r
+#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set\r
+#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear\r
+#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none\r
+#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set\r
+#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear\r
+#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none\r
+#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set\r
+#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear\r
+#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none\r
+#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set\r
+#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear\r
+#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading\r
+#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger\r
+#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_TCB {\r
+ AT91S_TC TCB_TC0; // TC Channel 0\r
+ AT91_REG Reserved0[4]; // \r
+ AT91S_TC TCB_TC1; // TC Channel 1\r
+ AT91_REG Reserved1[4]; // \r
+ AT91S_TC TCB_TC2; // TC Channel 2\r
+ AT91_REG Reserved2[4]; // \r
+ AT91_REG TCB_BCR; // TC Block Control Register\r
+ AT91_REG TCB_BMR; // TC Block Mode Register\r
+} AT91S_TCB, *AT91PS_TCB;\r
+#else\r
+#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register\r
+#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register\r
+\r
+#endif\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection\r
+#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection\r
+#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection\r
+#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Multimedia Card Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_MCI {\r
+ AT91_REG MCI_CR; // MCI Control Register\r
+ AT91_REG MCI_MR; // MCI Mode Register\r
+ AT91_REG MCI_DTOR; // MCI Data Timeout Register\r
+ AT91_REG MCI_SDCR; // MCI SD Card Register\r
+ AT91_REG MCI_ARGR; // MCI Argument Register\r
+ AT91_REG MCI_CMDR; // MCI Command Register\r
+ AT91_REG MCI_BLKR; // MCI Block Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG MCI_RSPR[4]; // MCI Response Register\r
+ AT91_REG MCI_RDR; // MCI Receive Data Register\r
+ AT91_REG MCI_TDR; // MCI Transmit Data Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG MCI_SR; // MCI Status Register\r
+ AT91_REG MCI_IER; // MCI Interrupt Enable Register\r
+ AT91_REG MCI_IDR; // MCI Interrupt Disable Register\r
+ AT91_REG MCI_IMR; // MCI Interrupt Mask Register\r
+ AT91_REG Reserved2[43]; // \r
+ AT91_REG MCI_VR; // MCI Version Register\r
+ AT91_REG MCI_RPR; // Receive Pointer Register\r
+ AT91_REG MCI_RCR; // Receive Counter Register\r
+ AT91_REG MCI_TPR; // Transmit Pointer Register\r
+ AT91_REG MCI_TCR; // Transmit Counter Register\r
+ AT91_REG MCI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG MCI_RNCR; // Receive Next Counter Register\r
+ AT91_REG MCI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG MCI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG MCI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG MCI_PTSR; // PDC Transfer Status Register\r
+} AT91S_MCI, *AT91PS_MCI;\r
+#else\r
+#define MCI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (MCI_CR) MCI Control Register\r
+#define MCI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (MCI_MR) MCI Mode Register\r
+#define MCI_DTOR (AT91_CAST(AT91_REG *) 0x00000008) // (MCI_DTOR) MCI Data Timeout Register\r
+#define MCI_SDCR (AT91_CAST(AT91_REG *) 0x0000000C) // (MCI_SDCR) MCI SD Card Register\r
+#define MCI_ARGR (AT91_CAST(AT91_REG *) 0x00000010) // (MCI_ARGR) MCI Argument Register\r
+#define MCI_CMDR (AT91_CAST(AT91_REG *) 0x00000014) // (MCI_CMDR) MCI Command Register\r
+#define MCI_BLKR (AT91_CAST(AT91_REG *) 0x00000018) // (MCI_BLKR) MCI Block Register\r
+#define MCI_RSPR (AT91_CAST(AT91_REG *) 0x00000020) // (MCI_RSPR) MCI Response Register\r
+#define MCI_RDR (AT91_CAST(AT91_REG *) 0x00000030) // (MCI_RDR) MCI Receive Data Register\r
+#define MCI_TDR (AT91_CAST(AT91_REG *) 0x00000034) // (MCI_TDR) MCI Transmit Data Register\r
+#define MCI_SR (AT91_CAST(AT91_REG *) 0x00000040) // (MCI_SR) MCI Status Register\r
+#define MCI_IER (AT91_CAST(AT91_REG *) 0x00000044) // (MCI_IER) MCI Interrupt Enable Register\r
+#define MCI_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (MCI_IDR) MCI Interrupt Disable Register\r
+#define MCI_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register\r
+#define MCI_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (MCI_VR) MCI Version Register\r
+\r
+#endif\r
+// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- \r
+#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable\r
+#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable\r
+#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable\r
+#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable\r
+#define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset\r
+// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- \r
+#define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider\r
+#define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider\r
+#define AT91C_MCI_RDPROOF (0x1 << 11) // (MCI) Read Proof Enable\r
+#define AT91C_MCI_WRPROOF (0x1 << 12) // (MCI) Write Proof Enable\r
+#define AT91C_MCI_PDCFBYTE (0x1 << 13) // (MCI) PDC Force Byte Transfer\r
+#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value\r
+#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode\r
+#define AT91C_MCI_BLKLEN (0xFFFF << 16) // (MCI) Data Block Length\r
+// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- \r
+#define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number\r
+#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier\r
+#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1\r
+#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16\r
+#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128\r
+#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256\r
+#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024\r
+#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096\r
+#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536\r
+#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576\r
+// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- \r
+#define AT91C_MCI_SCDSEL (0x3 << 0) // (MCI) SD Card Selector\r
+#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SDCard/SDIO Bus Width\r
+// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- \r
+#define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number\r
+#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type\r
+#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response\r
+#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response\r
+#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response\r
+#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD\r
+#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD\r
+#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD\r
+#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD\r
+#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command\r
+#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response\r
+#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command\r
+#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond\r
+#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD\r
+#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer\r
+#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer\r
+#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer\r
+#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction\r
+#define AT91C_MCI_TRTYP (0x7 << 19) // (MCI) Transfer Type\r
+#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type\r
+#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type\r
+#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) MMC Stream transfer type\r
+#define AT91C_MCI_TRTYP_SDIO_BYTE (0x4 << 19) // (MCI) SDIO Byte transfer type\r
+#define AT91C_MCI_TRTYP_SDIO_BLOCK (0x5 << 19) // (MCI) SDIO Block transfer type\r
+#define AT91C_MCI_IOSPCMD (0x3 << 24) // (MCI) SDIO Special Command\r
+#define AT91C_MCI_IOSPCMD_NONE (0x0 << 24) // (MCI) NOT a special command\r
+#define AT91C_MCI_IOSPCMD_SUSPEND (0x1 << 24) // (MCI) SDIO Suspend Command\r
+#define AT91C_MCI_IOSPCMD_RESUME (0x2 << 24) // (MCI) SDIO Resume Command\r
+// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register -------- \r
+#define AT91C_MCI_BCNT (0xFFFF << 0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count\r
+// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- \r
+#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag\r
+#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag\r
+#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag\r
+#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag\r
+#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag\r
+#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag\r
+#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag\r
+#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag\r
+#define AT91C_MCI_SDIOIRQA (0x1 << 8) // (MCI) SDIO Interrupt for Slot A\r
+#define AT91C_MCI_SDIOIRQB (0x1 << 9) // (MCI) SDIO Interrupt for Slot B\r
+#define AT91C_MCI_SDIOIRQC (0x1 << 10) // (MCI) SDIO Interrupt for Slot C\r
+#define AT91C_MCI_SDIOIRQD (0x1 << 11) // (MCI) SDIO Interrupt for Slot D\r
+#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag\r
+#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag\r
+#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag\r
+#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag\r
+#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag\r
+#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag\r
+#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag\r
+#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag\r
+#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag\r
+#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag\r
+#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag\r
+// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- \r
+// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- \r
+// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_TWI {\r
+ AT91_REG TWI_CR; // Control Register\r
+ AT91_REG TWI_MMR; // Master Mode Register\r
+ AT91_REG TWI_SMR; // Slave Mode Register\r
+ AT91_REG TWI_IADR; // Internal Address Register\r
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register\r
+ AT91_REG Reserved0[3]; // \r
+ AT91_REG TWI_SR; // Status Register\r
+ AT91_REG TWI_IER; // Interrupt Enable Register\r
+ AT91_REG TWI_IDR; // Interrupt Disable Register\r
+ AT91_REG TWI_IMR; // Interrupt Mask Register\r
+ AT91_REG TWI_RHR; // Receive Holding Register\r
+ AT91_REG TWI_THR; // Transmit Holding Register\r
+ AT91_REG Reserved1[50]; // \r
+ AT91_REG TWI_RPR; // Receive Pointer Register\r
+ AT91_REG TWI_RCR; // Receive Counter Register\r
+ AT91_REG TWI_TPR; // Transmit Pointer Register\r
+ AT91_REG TWI_TCR; // Transmit Counter Register\r
+ AT91_REG TWI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG TWI_RNCR; // Receive Next Counter Register\r
+ AT91_REG TWI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG TWI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG TWI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG TWI_PTSR; // PDC Transfer Status Register\r
+} AT91S_TWI, *AT91PS_TWI;\r
+#else\r
+#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register\r
+#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register\r
+#define TWI_SMR (AT91_CAST(AT91_REG *) 0x00000008) // (TWI_SMR) Slave Mode Register\r
+#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register\r
+#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register\r
+#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register\r
+#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register\r
+#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register\r
+#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register\r
+#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register\r
+#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register\r
+\r
+#endif\r
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition\r
+#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition\r
+#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled\r
+#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled\r
+#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave mode Enabled\r
+#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave mode Disabled\r
+#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset\r
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size\r
+#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address\r
+#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address\r
+#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address\r
+#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address\r
+#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction\r
+#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address\r
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- \r
+#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Address\r
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider\r
+#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider\r
+#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider\r
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+#define AT91C_TWI_TXCOMP_SLAVE (0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_TXCOMP_MASTER (0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY\r
+#define AT91C_TWI_TXRDY_MASTER (0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_TXRDY_SLAVE (0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave READ (used only in Slave mode)\r
+#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave ACCess (used only in Slave mode)\r
+#define AT91C_TWI_GACC (0x1 << 5) // (TWI) General Call ACcess (used only in Slave mode)\r
+#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error (used only in Master and Multi-master mode)\r
+#define AT91C_TWI_NACK_SLAVE (0x1 << 8) // (TWI) Not Acknowledged\r
+#define AT91C_TWI_NACK_MASTER (0x1 << 8) // (TWI) Not Acknowledged\r
+#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 << 9) // (TWI) Arbitration Lost (used only in Multimaster mode)\r
+#define AT91C_TWI_SCLWS (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)\r
+#define AT91C_TWI_EOSACC (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)\r
+#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) End of Receiver Transfer\r
+#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) End of Receiver Transfer\r
+#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) RXBUFF Interrupt\r
+#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) TXBUFE Interrupt\r
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Usart\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_USART {\r
+ AT91_REG US_CR; // Control Register\r
+ AT91_REG US_MR; // Mode Register\r
+ AT91_REG US_IER; // Interrupt Enable Register\r
+ AT91_REG US_IDR; // Interrupt Disable Register\r
+ AT91_REG US_IMR; // Interrupt Mask Register\r
+ AT91_REG US_CSR; // Channel Status Register\r
+ AT91_REG US_RHR; // Receiver Holding Register\r
+ AT91_REG US_THR; // Transmitter Holding Register\r
+ AT91_REG US_BRGR; // Baud Rate Generator Register\r
+ AT91_REG US_RTOR; // Receiver Time-out Register\r
+ AT91_REG US_TTGR; // Transmitter Time-guard Register\r
+ AT91_REG Reserved0[5]; // \r
+ AT91_REG US_FIDI; // FI_DI_Ratio Register\r
+ AT91_REG US_NER; // Nb Errors Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG US_IF; // IRDA_FILTER Register\r
+ AT91_REG Reserved2[44]; // \r
+ AT91_REG US_RPR; // Receive Pointer Register\r
+ AT91_REG US_RCR; // Receive Counter Register\r
+ AT91_REG US_TPR; // Transmit Pointer Register\r
+ AT91_REG US_TCR; // Transmit Counter Register\r
+ AT91_REG US_RNPR; // Receive Next Pointer Register\r
+ AT91_REG US_RNCR; // Receive Next Counter Register\r
+ AT91_REG US_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG US_TNCR; // Transmit Next Counter Register\r
+ AT91_REG US_PTCR; // PDC Transfer Control Register\r
+ AT91_REG US_PTSR; // PDC Transfer Status Register\r
+} AT91S_USART, *AT91PS_USART;\r
+#else\r
+#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register\r
+#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register\r
+#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register\r
+#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register\r
+#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register\r
+#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register\r
+#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register\r
+#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register\r
+#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register\r
+#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register\r
+#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register\r
+#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register\r
+#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register\r
+#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register\r
+\r
+#endif\r
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break\r
+#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address\r
+#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations\r
+#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge\r
+#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out\r
+#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable\r
+#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable\r
+#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable\r
+#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable\r
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode\r
+#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal\r
+#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485\r
+#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking\r
+#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem\r
+#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0\r
+#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1\r
+#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA\r
+#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking\r
+#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock\r
+#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1\r
+#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)\r
+#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits\r
+#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits\r
+#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits\r
+#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits\r
+#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit\r
+#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order\r
+#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select\r
+#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode\r
+#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge\r
+#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK\r
+#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions\r
+#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter\r
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break\r
+#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out\r
+#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached\r
+#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge\r
+#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
+#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
+#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag\r
+#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag\r
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input\r
+#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input\r
+#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input\r
+#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SSC {\r
+ AT91_REG SSC_CR; // Control Register\r
+ AT91_REG SSC_CMR; // Clock Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister\r
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register\r
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register\r
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register\r
+ AT91_REG SSC_RHR; // Receive Holding Register\r
+ AT91_REG SSC_THR; // Transmit Holding Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register\r
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register\r
+ AT91_REG Reserved2[2]; // \r
+ AT91_REG SSC_SR; // Status Register\r
+ AT91_REG SSC_IER; // Interrupt Enable Register\r
+ AT91_REG SSC_IDR; // Interrupt Disable Register\r
+ AT91_REG SSC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved3[44]; // \r
+ AT91_REG SSC_RPR; // Receive Pointer Register\r
+ AT91_REG SSC_RCR; // Receive Counter Register\r
+ AT91_REG SSC_TPR; // Transmit Pointer Register\r
+ AT91_REG SSC_TCR; // Transmit Counter Register\r
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SSC_RNCR; // Receive Next Counter Register\r
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register\r
+} AT91S_SSC, *AT91PS_SSC;\r
+#else\r
+#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register\r
+#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register\r
+#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister\r
+#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register\r
+#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register\r
+#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register\r
+#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register\r
+#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register\r
+#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register\r
+#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register\r
+#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register\r
+#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register\r
+#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register\r
+#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register\r
+\r
+#endif\r
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable\r
+#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable\r
+#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable\r
+#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable\r
+#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset\r
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection\r
+#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock\r
+#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal\r
+#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin\r
+#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
+#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion\r
+#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection\r
+#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start\r
+#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input\r
+#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input\r
+#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input\r
+#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input\r
+#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input\r
+#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input\r
+#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0\r
+#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
+#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length\r
+#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode\r
+#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First\r
+#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame\r
+#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
+#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
+#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection\r
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value\r
+#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable\r
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready\r
+#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty\r
+#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission\r
+#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty\r
+#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready\r
+#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun\r
+#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception\r
+#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full\r
+#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync\r
+#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync\r
+#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable\r
+#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable\r
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SPI {\r
+ AT91_REG SPI_CR; // Control Register\r
+ AT91_REG SPI_MR; // Mode Register\r
+ AT91_REG SPI_RDR; // Receive Data Register\r
+ AT91_REG SPI_TDR; // Transmit Data Register\r
+ AT91_REG SPI_SR; // Status Register\r
+ AT91_REG SPI_IER; // Interrupt Enable Register\r
+ AT91_REG SPI_IDR; // Interrupt Disable Register\r
+ AT91_REG SPI_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved0[4]; // \r
+ AT91_REG SPI_CSR[4]; // Chip Select Register\r
+ AT91_REG Reserved1[48]; // \r
+ AT91_REG SPI_RPR; // Receive Pointer Register\r
+ AT91_REG SPI_RCR; // Receive Counter Register\r
+ AT91_REG SPI_TPR; // Transmit Pointer Register\r
+ AT91_REG SPI_TCR; // Transmit Counter Register\r
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SPI_RNCR; // Receive Next Counter Register\r
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register\r
+} AT91S_SPI, *AT91PS_SPI;\r
+#else\r
+#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register\r
+#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register\r
+#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register\r
+#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register\r
+#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register\r
+#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register\r
+#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register\r
+#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register\r
+#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register\r
+\r
+#endif\r
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable\r
+#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable\r
+#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset\r
+#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer\r
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode\r
+#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select\r
+#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select\r
+#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select\r
+#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode\r
+#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection\r
+#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection\r
+#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection\r
+#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select\r
+#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects\r
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data\r
+#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data\r
+#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full\r
+#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty\r
+#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error\r
+#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status\r
+#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt\r
+#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt\r
+#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt\r
+#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt\r
+#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status\r
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity\r
+#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase\r
+#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer\r
+#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer\r
+#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer\r
+#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer\r
+#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer\r
+#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer\r
+#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer\r
+#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer\r
+#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer\r
+#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer\r
+#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer\r
+#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK\r
+#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_ADC {\r
+ AT91_REG ADC_CR; // ADC Control Register\r
+ AT91_REG ADC_MR; // ADC Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG ADC_CHER; // ADC Channel Enable Register\r
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register\r
+ AT91_REG ADC_CHSR; // ADC Channel Status Register\r
+ AT91_REG ADC_SR; // ADC Status Register\r
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register\r
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register\r
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register\r
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register\r
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0\r
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1\r
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2\r
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3\r
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4\r
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5\r
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6\r
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7\r
+ AT91_REG Reserved1[44]; // \r
+ AT91_REG ADC_RPR; // Receive Pointer Register\r
+ AT91_REG ADC_RCR; // Receive Counter Register\r
+ AT91_REG ADC_TPR; // Transmit Pointer Register\r
+ AT91_REG ADC_TCR; // Transmit Counter Register\r
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG ADC_RNCR; // Receive Next Counter Register\r
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register\r
+} AT91S_ADC, *AT91PS_ADC;\r
+#else\r
+#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register\r
+#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register\r
+#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register\r
+#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register\r
+#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register\r
+#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register\r
+#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register\r
+#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register\r
+#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register\r
+#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register\r
+#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0\r
+#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1\r
+#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2\r
+#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3\r
+#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4\r
+#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5\r
+#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6\r
+#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7\r
+\r
+#endif\r
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset\r
+#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion\r
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable\r
+#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection\r
+#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0\r
+#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1\r
+#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2\r
+#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3\r
+#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4\r
+#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5\r
+#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger\r
+#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.\r
+#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution\r
+#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution\r
+#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode\r
+#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection\r
+#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time\r
+#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time\r
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0\r
+#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1\r
+#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2\r
+#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3\r
+#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4\r
+#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5\r
+#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6\r
+#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7\r
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion\r
+#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error\r
+#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready\r
+#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun\r
+#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer\r
+#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt\r
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted\r
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data\r
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_EMAC {\r
+ AT91_REG EMAC_NCR; // Network Control Register\r
+ AT91_REG EMAC_NCFGR; // Network Configuration Register\r
+ AT91_REG EMAC_NSR; // Network Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG EMAC_TSR; // Transmit Status Register\r
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer\r
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer\r
+ AT91_REG EMAC_RSR; // Receive Status Register\r
+ AT91_REG EMAC_ISR; // Interrupt Status Register\r
+ AT91_REG EMAC_IER; // Interrupt Enable Register\r
+ AT91_REG EMAC_IDR; // Interrupt Disable Register\r
+ AT91_REG EMAC_IMR; // Interrupt Mask Register\r
+ AT91_REG EMAC_MAN; // PHY Maintenance Register\r
+ AT91_REG EMAC_PTR; // Pause Time Register\r
+ AT91_REG EMAC_PFR; // Pause Frames received Register\r
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register\r
+ AT91_REG EMAC_SCF; // Single Collision Frame Register\r
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register\r
+ AT91_REG EMAC_FRO; // Frames Received OK Register\r
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register\r
+ AT91_REG EMAC_ALE; // Alignment Error Register\r
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register\r
+ AT91_REG EMAC_LCOL; // Late Collision Register\r
+ AT91_REG EMAC_ECOL; // Excessive Collision Register\r
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register\r
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register\r
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register\r
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register\r
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register\r
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register\r
+ AT91_REG EMAC_RJA; // Receive Jabbers Register\r
+ AT91_REG EMAC_USF; // Undersize Frames Register\r
+ AT91_REG EMAC_STE; // SQE Test Error Register\r
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register\r
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register\r
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]\r
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]\r
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes\r
+ AT91_REG EMAC_TID; // Type ID Checking Register\r
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register\r
+ AT91_REG EMAC_USRIO; // USER Input/Output Register\r
+ AT91_REG EMAC_WOL; // Wake On LAN Register\r
+ AT91_REG Reserved1[13]; // \r
+ AT91_REG EMAC_REV; // Revision Register\r
+} AT91S_EMAC, *AT91PS_EMAC;\r
+#else\r
+#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register\r
+#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register\r
+#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register\r
+#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register\r
+#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer\r
+#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer\r
+#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register\r
+#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register\r
+#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register\r
+#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register\r
+#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register\r
+#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register\r
+#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register\r
+#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register\r
+#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register\r
+#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register\r
+#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register\r
+#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register\r
+#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register\r
+#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register\r
+#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register\r
+#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register\r
+#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register\r
+#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register\r
+#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register\r
+#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register\r
+#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register\r
+#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register\r
+#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register\r
+#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register\r
+#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register\r
+#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register\r
+#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register\r
+#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register\r
+#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]\r
+#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32]\r
+#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes\r
+#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes\r
+#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes\r
+#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes\r
+#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes\r
+#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes\r
+#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes\r
+#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes\r
+#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register\r
+#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register\r
+#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register\r
+#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register\r
+#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register\r
+\r
+#endif\r
+// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- \r
+#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.\r
+#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. \r
+#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. \r
+#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. \r
+#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. \r
+#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. \r
+#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. \r
+#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. \r
+#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. \r
+#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. \r
+#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. \r
+#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame \r
+#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame\r
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- \r
+#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. \r
+#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. \r
+#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. \r
+#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. \r
+#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. \r
+#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable\r
+#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. \r
+#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. \r
+#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. \r
+#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) \r
+#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8\r
+#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16\r
+#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32\r
+#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64\r
+#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) \r
+#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) \r
+#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable\r
+#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS\r
+#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) \r
+#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS\r
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- \r
+#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) \r
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- \r
+#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go\r
+#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame\r
+#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) \r
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \r
+#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) \r
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \r
+#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) \r
+#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) \r
+#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) \r
+#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) \r
+#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) \r
+#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) \r
+#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) \r
+#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) \r
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \r
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \r
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \r
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \r
+#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) \r
+#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) \r
+#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) \r
+#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) \r
+#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) \r
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- \r
+#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII\r
+#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable\r
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- \r
+#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address\r
+#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable\r
+#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable\r
+#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable\r
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- \r
+#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Device Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_UDP {\r
+ AT91_REG UDP_NUM; // Frame Number Register\r
+ AT91_REG UDP_GLBSTATE; // Global State Register\r
+ AT91_REG UDP_FADDR; // Function Address Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG UDP_IER; // Interrupt Enable Register\r
+ AT91_REG UDP_IDR; // Interrupt Disable Register\r
+ AT91_REG UDP_IMR; // Interrupt Mask Register\r
+ AT91_REG UDP_ISR; // Interrupt Status Register\r
+ AT91_REG UDP_ICR; // Interrupt Clear Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register\r
+ AT91_REG Reserved3[2]; // \r
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register\r
+ AT91_REG Reserved4[3]; // \r
+ AT91_REG UDP_TXVC; // Transceiver Control Register\r
+} AT91S_UDP, *AT91PS_UDP;\r
+#else\r
+#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register\r
+#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register\r
+#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register\r
+#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register\r
+#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register\r
+#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register\r
+#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register\r
+#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register\r
+#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register\r
+#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register\r
+#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register\r
+#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register\r
+\r
+#endif\r
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
+#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error\r
+#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK\r
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable\r
+#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured\r
+#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume\r
+#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host\r
+#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable\r
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value\r
+#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable\r
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt\r
+#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt\r
+#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt\r
+#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt\r
+#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt\r
+#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt\r
+#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt\r
+#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt\r
+#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt\r
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\r
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0\r
+#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1\r
+#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2\r
+#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3\r
+#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4\r
+#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5\r
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR\r
+#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0\r
+#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)\r
+#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)\r
+#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)\r
+#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready\r
+#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction\r
+#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type\r
+#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control\r
+#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT\r
+#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT\r
+#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT\r
+#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN\r
+#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN\r
+#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN\r
+#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle\r
+#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable\r
+#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\r
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- \r
+#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) \r
+#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Host Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_UHP {\r
+ AT91_REG UHP_HcRevision; // Revision\r
+ AT91_REG UHP_HcControl; // Operating modes for the Host Controller\r
+ AT91_REG UHP_HcCommandStatus; // Command & status Register\r
+ AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register\r
+ AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register\r
+ AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register\r
+ AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area\r
+ AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor\r
+ AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list\r
+ AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register\r
+ AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list\r
+ AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list\r
+ AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor\r
+ AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs\r
+ AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame\r
+ AT91_REG UHP_HcFmNumber; // Frame number\r
+ AT91_REG UHP_HcPeriodicStart; // Periodic Start\r
+ AT91_REG UHP_HcLSThreshold; // LS Threshold\r
+ AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A\r
+ AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B\r
+ AT91_REG UHP_HcRhStatus; // Root Hub Status register\r
+ AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register\r
+} AT91S_UHP, *AT91PS_UHP;\r
+#else\r
+#define HcRevision (AT91_CAST(AT91_REG *) 0x00000000) // (HcRevision) Revision\r
+#define HcControl (AT91_CAST(AT91_REG *) 0x00000004) // (HcControl) Operating modes for the Host Controller\r
+#define HcCommandStatus (AT91_CAST(AT91_REG *) 0x00000008) // (HcCommandStatus) Command & status Register\r
+#define HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0000000C) // (HcInterruptStatus) Interrupt Status Register\r
+#define HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00000010) // (HcInterruptEnable) Interrupt Enable Register\r
+#define HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00000014) // (HcInterruptDisable) Interrupt Disable Register\r
+#define HcHCCA (AT91_CAST(AT91_REG *) 0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area\r
+#define HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor\r
+#define HcControlHeadED (AT91_CAST(AT91_REG *) 0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list\r
+#define HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register\r
+#define HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list\r
+#define HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list\r
+#define HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor\r
+#define HcFmInterval (AT91_CAST(AT91_REG *) 0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs\r
+#define HcFmRemaining (AT91_CAST(AT91_REG *) 0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame\r
+#define HcFmNumber (AT91_CAST(AT91_REG *) 0x0000003C) // (HcFmNumber) Frame number\r
+#define HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00000040) // (HcPeriodicStart) Periodic Start\r
+#define HcLSThreshold (AT91_CAST(AT91_REG *) 0x00000044) // (HcLSThreshold) LS Threshold\r
+#define HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00000048) // (HcRhDescriptorA) Root Hub characteristics A\r
+#define HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B\r
+#define HcRhStatus (AT91_CAST(AT91_REG *) 0x00000050) // (HcRhStatus) Root Hub Status register\r
+#define HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00000054) // (HcRhPortStatus) Root Hub Port Status Register\r
+\r
+#endif\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Image Sensor Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_ISI {\r
+ AT91_REG ISI_CR1; // Control Register 1\r
+ AT91_REG ISI_CR2; // Control Register 2\r
+ AT91_REG ISI_SR; // Status Register\r
+ AT91_REG ISI_IER; // Interrupt Enable Register\r
+ AT91_REG ISI_IDR; // Interrupt Disable Register\r
+ AT91_REG ISI_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG ISI_PSIZE; // Preview Size Register\r
+ AT91_REG ISI_PDECF; // Preview Decimation Factor Register\r
+ AT91_REG ISI_PFBD; // Preview Frame Buffer Address Register\r
+ AT91_REG ISI_CDBA; // Codec Dma Address Register\r
+ AT91_REG ISI_Y2RSET0; // Color Space Conversion Register\r
+ AT91_REG ISI_Y2RSET1; // Color Space Conversion Register\r
+ AT91_REG ISI_R2YSET0; // Color Space Conversion Register\r
+ AT91_REG ISI_R2YSET1; // Color Space Conversion Register\r
+ AT91_REG ISI_R2YSET2; // Color Space Conversion Register\r
+} AT91S_ISI, *AT91PS_ISI;\r
+#else\r
+#define ISI_CR1 (AT91_CAST(AT91_REG *) 0x00000000) // (ISI_CR1) Control Register 1\r
+#define ISI_CR2 (AT91_CAST(AT91_REG *) 0x00000004) // (ISI_CR2) Control Register 2\r
+#define ISI_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ISI_SR) Status Register\r
+#define ISI_IER (AT91_CAST(AT91_REG *) 0x0000000C) // (ISI_IER) Interrupt Enable Register\r
+#define ISI_IDR (AT91_CAST(AT91_REG *) 0x00000010) // (ISI_IDR) Interrupt Disable Register\r
+#define ISI_IMR (AT91_CAST(AT91_REG *) 0x00000014) // (ISI_IMR) Interrupt Mask Register\r
+#define ISI_PSIZE (AT91_CAST(AT91_REG *) 0x00000020) // (ISI_PSIZE) Preview Size Register\r
+#define ISI_PDECF (AT91_CAST(AT91_REG *) 0x00000024) // (ISI_PDECF) Preview Decimation Factor Register\r
+#define ISI_PFBD (AT91_CAST(AT91_REG *) 0x00000028) // (ISI_PFBD) Preview Frame Buffer Address Register\r
+#define ISI_CDBA (AT91_CAST(AT91_REG *) 0x0000002C) // (ISI_CDBA) Codec Dma Address Register\r
+#define ISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0x00000030) // (ISI_Y2RSET0) Color Space Conversion Register\r
+#define ISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0x00000034) // (ISI_Y2RSET1) Color Space Conversion Register\r
+#define ISI_R2YSET0 (AT91_CAST(AT91_REG *) 0x00000038) // (ISI_R2YSET0) Color Space Conversion Register\r
+#define ISI_R2YSET1 (AT91_CAST(AT91_REG *) 0x0000003C) // (ISI_R2YSET1) Color Space Conversion Register\r
+#define ISI_R2YSET2 (AT91_CAST(AT91_REG *) 0x00000040) // (ISI_R2YSET2) Color Space Conversion Register\r
+\r
+#endif\r
+// -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 -------- \r
+#define AT91C_ISI_RST (0x1 << 0) // (ISI) Image sensor interface reset\r
+#define AT91C_ISI_DISABLE (0x1 << 1) // (ISI) image sensor disable.\r
+#define AT91C_ISI_HSYNC_POL (0x1 << 2) // (ISI) Horizontal synchronisation polarity\r
+#define AT91C_ISI_PIXCLK_POL (0x1 << 4) // (ISI) Pixel Clock Polarity\r
+#define AT91C_ISI_EMB_SYNC (0x1 << 6) // (ISI) Embedded synchronisation\r
+#define AT91C_ISI_CRC_SYNC (0x1 << 7) // (ISI) CRC correction\r
+#define AT91C_ISI_FULL (0x1 << 12) // (ISI) Full mode is allowed\r
+#define AT91C_ISI_THMASK (0x3 << 13) // (ISI) DMA Burst Mask\r
+#define AT91C_ISI_THMASK_4_8_16_BURST (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed\r
+#define AT91C_ISI_THMASK_8_16_BURST (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed\r
+#define AT91C_ISI_THMASK_16_BURST (0x2 << 13) // (ISI) Only 16 AHB burst are allowed\r
+#define AT91C_ISI_CODEC_ON (0x1 << 15) // (ISI) Enable the codec path\r
+#define AT91C_ISI_SLD (0xFF << 16) // (ISI) Start of Line Delay\r
+#define AT91C_ISI_SFD (0xFF << 24) // (ISI) Start of frame Delay\r
+// -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 -------- \r
+#define AT91C_ISI_IM_VSIZE (0x7FF << 0) // (ISI) Vertical size of the Image sensor [0..2047]\r
+#define AT91C_ISI_GS_MODE (0x1 << 11) // (ISI) Grayscale Memory Mode\r
+#define AT91C_ISI_RGB_MODE (0x3 << 12) // (ISI) RGB mode\r
+#define AT91C_ISI_RGB_MODE_RGB_888 (0x0 << 12) // (ISI) RGB 8:8:8 24 bits\r
+#define AT91C_ISI_RGB_MODE_RGB_565 (0x1 << 12) // (ISI) RGB 5:6:5 16 bits\r
+#define AT91C_ISI_RGB_MODE_RGB_555 (0x2 << 12) // (ISI) RGB 5:5:5 16 bits\r
+#define AT91C_ISI_GRAYSCALE (0x1 << 13) // (ISI) Grayscale Mode\r
+#define AT91C_ISI_RGB_SWAP (0x1 << 14) // (ISI) RGB Swap\r
+#define AT91C_ISI_COL_SPACE (0x1 << 15) // (ISI) Color space for the image data\r
+#define AT91C_ISI_IM_HSIZE (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047]\r
+#define AT91C_ISI_RGB_MODE_YCC_DEF (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1)\r
+#define AT91C_ISI_RGB_MODE_YCC_MOD1 (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1)\r
+#define AT91C_ISI_RGB_MODE_YCC_MOD2 (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i)\r
+#define AT91C_ISI_RGB_MODE_YCC_MOD3 (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i)\r
+#define AT91C_ISI_RGB_CFG (0x3 << 30) // (ISI) RGB configuration\r
+#define AT91C_ISI_RGB_CFG_RGB_DEF (0x0 << 30) // (ISI) R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B\r
+#define AT91C_ISI_RGB_CFG_RGB_MOD1 (0x1 << 30) // (ISI) B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R\r
+#define AT91C_ISI_RGB_CFG_RGB_MOD2 (0x2 << 30) // (ISI) G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB)\r
+#define AT91C_ISI_RGB_CFG_RGB_MOD3 (0x3 << 30) // (ISI) G(LSB)/B R/G(MSB) G(LSB)/B R/G(MSB)\r
+// -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register -------- \r
+#define AT91C_ISI_SOF (0x1 << 0) // (ISI) Start of Frame\r
+#define AT91C_ISI_DIS (0x1 << 1) // (ISI) Image Sensor Interface disable\r
+#define AT91C_ISI_SOFTRST (0x1 << 2) // (ISI) Software Reset\r
+#define AT91C_ISI_CRC_ERR (0x1 << 4) // (ISI) CRC synchronisation error\r
+#define AT91C_ISI_FO_C_OVF (0x1 << 5) // (ISI) Fifo Codec Overflow \r
+#define AT91C_ISI_FO_P_OVF (0x1 << 6) // (ISI) Fifo Preview Overflow \r
+#define AT91C_ISI_FO_P_EMP (0x1 << 7) // (ISI) Fifo Preview Empty\r
+#define AT91C_ISI_FO_C_EMP (0x1 << 8) // (ISI) Fifo Codec Empty\r
+#define AT91C_ISI_FR_OVR (0x1 << 9) // (ISI) Frame rate overun\r
+// -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register -------- \r
+// -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register -------- \r
+// -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register -------- \r
+// -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register -------- \r
+#define AT91C_ISI_PREV_VSIZE (0x3FF << 0) // (ISI) Vertical size for the preview path\r
+#define AT91C_ISI_PREV_HSIZE (0x3FF << 16) // (ISI) Horizontal size for the preview path\r
+// -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register -------- \r
+#define AT91C_ISI_Y2R_C0 (0xFF << 0) // (ISI) Color Space Conversion Matrix Coefficient C0\r
+#define AT91C_ISI_Y2R_C1 (0xFF << 8) // (ISI) Color Space Conversion Matrix Coefficient C1\r
+#define AT91C_ISI_Y2R_C2 (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2\r
+#define AT91C_ISI_Y2R_C3 (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3\r
+// -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register -------- \r
+#define AT91C_ISI_Y2R_C4 (0x1FF << 0) // (ISI) Color Space Conversion Matrix Coefficient C4\r
+#define AT91C_ISI_Y2R_YOFF (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset\r
+#define AT91C_ISI_Y2R_CROFF (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset\r
+#define AT91C_ISI_Y2R_CBFF (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset\r
+// -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register -------- \r
+#define AT91C_ISI_R2Y_C0 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0\r
+#define AT91C_ISI_R2Y_C1 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1\r
+#define AT91C_ISI_R2Y_C2 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2\r
+#define AT91C_ISI_R2Y_ROFF (0x1 << 4) // (ISI) Color Space Conversion Red component offset\r
+// -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register -------- \r
+#define AT91C_ISI_R2Y_C3 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3\r
+#define AT91C_ISI_R2Y_C4 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4\r
+#define AT91C_ISI_R2Y_C5 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5\r
+#define AT91C_ISI_R2Y_GOFF (0x1 << 4) // (ISI) Color Space Conversion Green component offset\r
+// -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register -------- \r
+#define AT91C_ISI_R2Y_C6 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6\r
+#define AT91C_ISI_R2Y_C7 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7\r
+#define AT91C_ISI_R2Y_C8 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8\r
+#define AT91C_ISI_R2Y_BOFF (0x1 << 4) // (ISI) Color Space Conversion Blue component offset\r
+\r
+// *****************************************************************************\r
+// REGISTER ADDRESS DEFINITION FOR AT91SAM9XE256\r
+// *****************************************************************************\r
+// ========== Register definition for SYS peripheral ========== \r
+#define AT91C_SYS_GPBR (AT91_CAST(AT91_REG *) 0xFFFFFFFF) // (SYS) General Purpose Register\r
+// ========== Register definition for EBI peripheral ========== \r
+#define AT91C_EBI_DUMMY (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (EBI) Dummy register - Do not use\r
+// ========== Register definition for HECC peripheral ========== \r
+#define AT91C_HECC_VR (AT91_CAST(AT91_REG *) 0xFFFFE8FC) // (HECC) ECC Version register\r
+#define AT91C_HECC_NPR (AT91_CAST(AT91_REG *) 0xFFFFE810) // (HECC) ECC Parity N register\r
+#define AT91C_HECC_SR (AT91_CAST(AT91_REG *) 0xFFFFE808) // (HECC) ECC Status register\r
+#define AT91C_HECC_PR (AT91_CAST(AT91_REG *) 0xFFFFE80C) // (HECC) ECC Parity register\r
+#define AT91C_HECC_MR (AT91_CAST(AT91_REG *) 0xFFFFE804) // (HECC) ECC Page size register\r
+#define AT91C_HECC_CR (AT91_CAST(AT91_REG *) 0xFFFFE800) // (HECC) ECC reset register\r
+// ========== Register definition for SDRAMC peripheral ========== \r
+#define AT91C_SDRAMC_MR (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register\r
+#define AT91C_SDRAMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register\r
+#define AT91C_SDRAMC_LPR (AT91_CAST(AT91_REG *) 0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register\r
+#define AT91C_SDRAMC_ISR (AT91_CAST(AT91_REG *) 0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register\r
+#define AT91C_SDRAMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register\r
+#define AT91C_SDRAMC_CR (AT91_CAST(AT91_REG *) 0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register\r
+#define AT91C_SDRAMC_TR (AT91_CAST(AT91_REG *) 0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register\r
+#define AT91C_SDRAMC_MDR (AT91_CAST(AT91_REG *) 0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register\r
+#define AT91C_SDRAMC_HSR (AT91_CAST(AT91_REG *) 0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register\r
+#define AT91C_SDRAMC_IER (AT91_CAST(AT91_REG *) 0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register\r
+// ========== Register definition for SMC peripheral ========== \r
+#define AT91C_SMC_CTRL1 (AT91_CAST(AT91_REG *) 0xFFFFEC1C) // (SMC) Control Register for CS 1\r
+#define AT91C_SMC_PULSE7 (AT91_CAST(AT91_REG *) 0xFFFFEC74) // (SMC) Pulse Register for CS 7\r
+#define AT91C_SMC_PULSE6 (AT91_CAST(AT91_REG *) 0xFFFFEC64) // (SMC) Pulse Register for CS 6\r
+#define AT91C_SMC_SETUP4 (AT91_CAST(AT91_REG *) 0xFFFFEC40) // (SMC) Setup Register for CS 4\r
+#define AT91C_SMC_PULSE3 (AT91_CAST(AT91_REG *) 0xFFFFEC34) // (SMC) Pulse Register for CS 3\r
+#define AT91C_SMC_CYCLE5 (AT91_CAST(AT91_REG *) 0xFFFFEC58) // (SMC) Cycle Register for CS 5\r
+#define AT91C_SMC_CYCLE2 (AT91_CAST(AT91_REG *) 0xFFFFEC28) // (SMC) Cycle Register for CS 2\r
+#define AT91C_SMC_CTRL2 (AT91_CAST(AT91_REG *) 0xFFFFEC2C) // (SMC) Control Register for CS 2\r
+#define AT91C_SMC_CTRL0 (AT91_CAST(AT91_REG *) 0xFFFFEC0C) // (SMC) Control Register for CS 0\r
+#define AT91C_SMC_PULSE5 (AT91_CAST(AT91_REG *) 0xFFFFEC54) // (SMC) Pulse Register for CS 5\r
+#define AT91C_SMC_PULSE1 (AT91_CAST(AT91_REG *) 0xFFFFEC14) // (SMC) Pulse Register for CS 1\r
+#define AT91C_SMC_PULSE0 (AT91_CAST(AT91_REG *) 0xFFFFEC04) // (SMC) Pulse Register for CS 0\r
+#define AT91C_SMC_CYCLE7 (AT91_CAST(AT91_REG *) 0xFFFFEC78) // (SMC) Cycle Register for CS 7\r
+#define AT91C_SMC_CTRL4 (AT91_CAST(AT91_REG *) 0xFFFFEC4C) // (SMC) Control Register for CS 4\r
+#define AT91C_SMC_CTRL3 (AT91_CAST(AT91_REG *) 0xFFFFEC3C) // (SMC) Control Register for CS 3\r
+#define AT91C_SMC_SETUP7 (AT91_CAST(AT91_REG *) 0xFFFFEC70) // (SMC) Setup Register for CS 7\r
+#define AT91C_SMC_CTRL7 (AT91_CAST(AT91_REG *) 0xFFFFEC7C) // (SMC) Control Register for CS 7\r
+#define AT91C_SMC_SETUP1 (AT91_CAST(AT91_REG *) 0xFFFFEC10) // (SMC) Setup Register for CS 1\r
+#define AT91C_SMC_CYCLE0 (AT91_CAST(AT91_REG *) 0xFFFFEC08) // (SMC) Cycle Register for CS 0\r
+#define AT91C_SMC_CTRL5 (AT91_CAST(AT91_REG *) 0xFFFFEC5C) // (SMC) Control Register for CS 5\r
+#define AT91C_SMC_CYCLE1 (AT91_CAST(AT91_REG *) 0xFFFFEC18) // (SMC) Cycle Register for CS 1\r
+#define AT91C_SMC_CTRL6 (AT91_CAST(AT91_REG *) 0xFFFFEC6C) // (SMC) Control Register for CS 6\r
+#define AT91C_SMC_SETUP0 (AT91_CAST(AT91_REG *) 0xFFFFEC00) // (SMC) Setup Register for CS 0\r
+#define AT91C_SMC_PULSE4 (AT91_CAST(AT91_REG *) 0xFFFFEC44) // (SMC) Pulse Register for CS 4\r
+#define AT91C_SMC_SETUP5 (AT91_CAST(AT91_REG *) 0xFFFFEC50) // (SMC) Setup Register for CS 5\r
+#define AT91C_SMC_SETUP2 (AT91_CAST(AT91_REG *) 0xFFFFEC20) // (SMC) Setup Register for CS 2\r
+#define AT91C_SMC_CYCLE3 (AT91_CAST(AT91_REG *) 0xFFFFEC38) // (SMC) Cycle Register for CS 3\r
+#define AT91C_SMC_CYCLE6 (AT91_CAST(AT91_REG *) 0xFFFFEC68) // (SMC) Cycle Register for CS 6\r
+#define AT91C_SMC_SETUP6 (AT91_CAST(AT91_REG *) 0xFFFFEC60) // (SMC) Setup Register for CS 6\r
+#define AT91C_SMC_CYCLE4 (AT91_CAST(AT91_REG *) 0xFFFFEC48) // (SMC) Cycle Register for CS 4\r
+#define AT91C_SMC_PULSE2 (AT91_CAST(AT91_REG *) 0xFFFFEC24) // (SMC) Pulse Register for CS 2\r
+#define AT91C_SMC_SETUP3 (AT91_CAST(AT91_REG *) 0xFFFFEC30) // (SMC) Setup Register for CS 3\r
+// ========== Register definition for MATRIX peripheral ========== \r
+#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE00) // (MATRIX) Master Configuration Register 0 (ram96k) \r
+#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0xFFFFEE1C) // (MATRIX) Master Configuration Register 7 (teak_prog) \r
+#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE44) // (MATRIX) Slave Configuration Register 1 (rom) \r
+#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE10) // (MATRIX) Master Configuration Register 4 (bridge) \r
+#define AT91C_MATRIX_VERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (MATRIX) Version Register\r
+#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE08) // (MATRIX) Master Configuration Register 2 (hperiphs) \r
+#define AT91C_MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA4) // (MATRIX) PRBS4 : ebi\r
+#define AT91C_MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0xFFFFEE84) // (MATRIX) PRBS0 (ram0) \r
+#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE4C) // (MATRIX) Slave Configuration Register 3 (ebi)\r
+#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0xFFFFEE18) // (MATRIX) Master Configuration Register 6 (ram16k) \r
+#define AT91C_MATRIX_EBI (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (MATRIX) Slave 3 (ebi) Special Function Register\r
+#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE40) // (MATRIX) Slave Configuration Register 0 (ram96k) \r
+#define AT91C_MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0xFFFFEE9C) // (MATRIX) PRBS3 : usb_dev_hs\r
+#define AT91C_MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0xFFFFEE98) // (MATRIX) PRAS3 : usb_dev_hs\r
+#define AT91C_MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0xFFFFEE80) // (MATRIX) PRAS0 (ram0) \r
+#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE0C) // (MATRIX) Master Configuration Register 3 (ebi)\r
+#define AT91C_MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0xFFFFEE88) // (MATRIX) PRAS1 (ram1) \r
+#define AT91C_MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0xFFFFEE90) // (MATRIX) PRAS2 (ram2) \r
+#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE48) // (MATRIX) Slave Configuration Register 2 (hperiphs) \r
+#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0xFFFFEE14) // (MATRIX) Master Configuration Register 5 (mailbox) \r
+#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE04) // (MATRIX) Master Configuration Register 1 (rom) \r
+#define AT91C_MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA0) // (MATRIX) PRAS4 : ebi\r
+#define AT91C_MATRIX_MRCR (AT91_CAST(AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register \r
+#define AT91C_MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0xFFFFEE94) // (MATRIX) PRBS2 (ram2) \r
+#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE50) // (MATRIX) Slave Configuration Register 4 (bridge) \r
+#define AT91C_MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0xFFFFEF2C) // (MATRIX) Slave 7 (teak_prog) Special Function Register\r
+#define AT91C_MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0xFFFFEE8C) // (MATRIX) PRBS1 (ram1) \r
+// ========== Register definition for CCFG peripheral ========== \r
+#define AT91C_CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (CCFG) Version Register\r
+#define AT91C_CCFG_EBICSA (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register\r
+// ========== Register definition for PDC_DBGU peripheral ========== \r
+#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\r
+#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\r
+#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\r
+#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\r
+#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\r
+#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register\r
+#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\r
+#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\r
+#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\r
+#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\r
+// ========== Register definition for DBGU peripheral ========== \r
+#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register\r
+#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register\r
+#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register\r
+#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register\r
+#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register\r
+#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register\r
+#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register\r
+#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register\r
+#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register\r
+#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register\r
+#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register\r
+#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register\r
+// ========== Register definition for AIC peripheral ========== \r
+#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register\r
+#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register\r
+#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register\r
+#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)\r
+#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register\r
+#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register\r
+#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register\r
+#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register\r
+#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register\r
+#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register\r
+#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register\r
+#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register\r
+#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register\r
+#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register\r
+#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register\r
+#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register\r
+#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register\r
+#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register\r
+// ========== Register definition for PIOA peripheral ========== \r
+#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr\r
+#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register\r
+#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register\r
+#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register\r
+#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register\r
+#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register\r
+#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register\r
+#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register\r
+#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register\r
+#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register\r
+#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register\r
+#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register\r
+#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register\r
+#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register\r
+#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register\r
+#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register\r
+#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register\r
+#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register\r
+#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register\r
+#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register\r
+#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register\r
+#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register\r
+#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register\r
+#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register\r
+#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register\r
+#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register\r
+#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register\r
+#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register\r
+#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register\r
+// ========== Register definition for PIOB peripheral ========== \r
+#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register\r
+#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register\r
+#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register\r
+#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register\r
+#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register\r
+#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register\r
+#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register\r
+#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register\r
+#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register\r
+#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register\r
+#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register\r
+#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register\r
+#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register\r
+#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register\r
+#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register\r
+#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register\r
+#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr\r
+#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register\r
+#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register\r
+#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register\r
+#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register\r
+#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register\r
+#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register\r
+#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register\r
+#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register\r
+#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register\r
+#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register\r
+#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register\r
+#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register\r
+// ========== Register definition for PIOC peripheral ========== \r
+#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register\r
+#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register\r
+#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register\r
+#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register\r
+#define AT91C_PIOC_PSR (AT91_CAST(AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register\r
+#define AT91C_PIOC_PDR (AT91_CAST(AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register\r
+#define AT91C_PIOC_ODR (AT91_CAST(AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr\r
+#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF868) // (PIOC) Pull-up Status Register\r
+#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register\r
+#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register\r
+#define AT91C_PIOC_OER (AT91_CAST(AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register\r
+#define AT91C_PIOC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register\r
+#define AT91C_PIOC_ASR (AT91_CAST(AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register\r
+#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register\r
+#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register\r
+#define AT91C_PIOC_PER (AT91_CAST(AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register\r
+#define AT91C_PIOC_IDR (AT91_CAST(AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register\r
+#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register\r
+#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register\r
+#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register\r
+#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register\r
+#define AT91C_PIOC_BSR (AT91_CAST(AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register\r
+#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register\r
+#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register\r
+#define AT91C_PIOC_IER (AT91_CAST(AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register\r
+#define AT91C_PIOC_OSR (AT91_CAST(AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register\r
+#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register\r
+#define AT91C_PIOC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register\r
+#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register\r
+// ========== Register definition for EFC peripheral ========== \r
+#define AT91C_EFC_FVR (AT91_CAST(AT91_REG *) 0xFFFFFA10) // (EFC) EFC Flash Version Register\r
+#define AT91C_EFC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFA04) // (EFC) EFC Flash Command Register\r
+#define AT91C_EFC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFA00) // (EFC) EFC Flash Mode Register\r
+#define AT91C_EFC_FRR (AT91_CAST(AT91_REG *) 0xFFFFFA0C) // (EFC) EFC Flash Result Register\r
+#define AT91C_EFC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFA08) // (EFC) EFC Flash Status Register\r
+// ========== Register definition for CKGR peripheral ========== \r
+#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register\r
+#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register\r
+#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register\r
+#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register\r
+// ========== Register definition for PMC peripheral ========== \r
+#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\r
+#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register\r
+#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register\r
+#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register\r
+#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\r
+#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register\r
+#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register\r
+#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register\r
+#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register\r
+#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register\r
+#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register\r
+#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register\r
+#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register\r
+#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register\r
+#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register\r
+#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register\r
+// ========== Register definition for RSTC peripheral ========== \r
+#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register\r
+#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register\r
+#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register\r
+// ========== Register definition for SHDWC peripheral ========== \r
+#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register\r
+#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register\r
+#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register\r
+// ========== Register definition for RTTC peripheral ========== \r
+#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register\r
+#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register\r
+#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register\r
+#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register\r
+// ========== Register definition for PITC peripheral ========== \r
+#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register\r
+#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register\r
+#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register\r
+#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register\r
+// ========== Register definition for WDTC peripheral ========== \r
+#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register\r
+#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register\r
+#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register\r
+#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C\r
+#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B\r
+#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register\r
+#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A\r
+#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value\r
+#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B\r
+#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register\r
+#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register\r
+#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A\r
+#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C\r
+#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register\r
+#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value\r
+#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A\r
+#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B\r
+#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register\r
+#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C\r
+#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register\r
+// ========== Register definition for TC3 peripheral ========== \r
+#define AT91C_TC3_IER (AT91_CAST(AT91_REG *) 0xFFFDC024) // (TC3) Interrupt Enable Register\r
+#define AT91C_TC3_RB (AT91_CAST(AT91_REG *) 0xFFFDC018) // (TC3) Register B\r
+#define AT91C_TC3_CMR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC3_RC (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (TC3) Register C\r
+#define AT91C_TC3_CCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (TC3) Channel Control Register\r
+#define AT91C_TC3_SR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (TC3) Status Register\r
+#define AT91C_TC3_CV (AT91_CAST(AT91_REG *) 0xFFFDC010) // (TC3) Counter Value\r
+#define AT91C_TC3_RA (AT91_CAST(AT91_REG *) 0xFFFDC014) // (TC3) Register A\r
+#define AT91C_TC3_IDR (AT91_CAST(AT91_REG *) 0xFFFDC028) // (TC3) Interrupt Disable Register\r
+#define AT91C_TC3_IMR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (TC3) Interrupt Mask Register\r
+// ========== Register definition for TC4 peripheral ========== \r
+#define AT91C_TC4_CMR (AT91_CAST(AT91_REG *) 0xFFFDC044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC4_RC (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (TC4) Register C\r
+#define AT91C_TC4_SR (AT91_CAST(AT91_REG *) 0xFFFDC060) // (TC4) Status Register\r
+#define AT91C_TC4_RB (AT91_CAST(AT91_REG *) 0xFFFDC058) // (TC4) Register B\r
+#define AT91C_TC4_IER (AT91_CAST(AT91_REG *) 0xFFFDC064) // (TC4) Interrupt Enable Register\r
+#define AT91C_TC4_CV (AT91_CAST(AT91_REG *) 0xFFFDC050) // (TC4) Counter Value\r
+#define AT91C_TC4_RA (AT91_CAST(AT91_REG *) 0xFFFDC054) // (TC4) Register A\r
+#define AT91C_TC4_IDR (AT91_CAST(AT91_REG *) 0xFFFDC068) // (TC4) Interrupt Disable Register\r
+#define AT91C_TC4_IMR (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (TC4) Interrupt Mask Register\r
+#define AT91C_TC4_CCR (AT91_CAST(AT91_REG *) 0xFFFDC040) // (TC4) Channel Control Register\r
+// ========== Register definition for TC5 peripheral ========== \r
+#define AT91C_TC5_RB (AT91_CAST(AT91_REG *) 0xFFFDC098) // (TC5) Register B\r
+#define AT91C_TC5_RA (AT91_CAST(AT91_REG *) 0xFFFDC094) // (TC5) Register A\r
+#define AT91C_TC5_CV (AT91_CAST(AT91_REG *) 0xFFFDC090) // (TC5) Counter Value\r
+#define AT91C_TC5_CCR (AT91_CAST(AT91_REG *) 0xFFFDC080) // (TC5) Channel Control Register\r
+#define AT91C_TC5_SR (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (TC5) Status Register\r
+#define AT91C_TC5_IER (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (TC5) Interrupt Enable Register\r
+#define AT91C_TC5_IDR (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (TC5) Interrupt Disable Register\r
+#define AT91C_TC5_RC (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (TC5) Register C\r
+#define AT91C_TC5_IMR (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (TC5) Interrupt Mask Register\r
+#define AT91C_TC5_CMR (AT91_CAST(AT91_REG *) 0xFFFDC084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode)\r
+// ========== Register definition for TCB0 peripheral ========== \r
+#define AT91C_TCB0_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register\r
+#define AT91C_TCB0_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register\r
+// ========== Register definition for TCB1 peripheral ========== \r
+#define AT91C_TCB1_BCR (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (TCB1) TC Block Control Register\r
+#define AT91C_TCB1_BMR (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (TCB1) TC Block Mode Register\r
+// ========== Register definition for PDC_MCI peripheral ========== \r
+#define AT91C_MCI_RNCR (AT91_CAST(AT91_REG *) 0xFFFA8114) // (PDC_MCI) Receive Next Counter Register\r
+#define AT91C_MCI_TCR (AT91_CAST(AT91_REG *) 0xFFFA810C) // (PDC_MCI) Transmit Counter Register\r
+#define AT91C_MCI_RCR (AT91_CAST(AT91_REG *) 0xFFFA8104) // (PDC_MCI) Receive Counter Register\r
+#define AT91C_MCI_TNPR (AT91_CAST(AT91_REG *) 0xFFFA8118) // (PDC_MCI) Transmit Next Pointer Register\r
+#define AT91C_MCI_RNPR (AT91_CAST(AT91_REG *) 0xFFFA8110) // (PDC_MCI) Receive Next Pointer Register\r
+#define AT91C_MCI_RPR (AT91_CAST(AT91_REG *) 0xFFFA8100) // (PDC_MCI) Receive Pointer Register\r
+#define AT91C_MCI_TNCR (AT91_CAST(AT91_REG *) 0xFFFA811C) // (PDC_MCI) Transmit Next Counter Register\r
+#define AT91C_MCI_TPR (AT91_CAST(AT91_REG *) 0xFFFA8108) // (PDC_MCI) Transmit Pointer Register\r
+#define AT91C_MCI_PTSR (AT91_CAST(AT91_REG *) 0xFFFA8124) // (PDC_MCI) PDC Transfer Status Register\r
+#define AT91C_MCI_PTCR (AT91_CAST(AT91_REG *) 0xFFFA8120) // (PDC_MCI) PDC Transfer Control Register\r
+// ========== Register definition for MCI peripheral ========== \r
+#define AT91C_MCI_RDR (AT91_CAST(AT91_REG *) 0xFFFA8030) // (MCI) MCI Receive Data Register\r
+#define AT91C_MCI_CMDR (AT91_CAST(AT91_REG *) 0xFFFA8014) // (MCI) MCI Command Register\r
+#define AT91C_MCI_VR (AT91_CAST(AT91_REG *) 0xFFFA80FC) // (MCI) MCI Version Register\r
+#define AT91C_MCI_IDR (AT91_CAST(AT91_REG *) 0xFFFA8048) // (MCI) MCI Interrupt Disable Register\r
+#define AT91C_MCI_DTOR (AT91_CAST(AT91_REG *) 0xFFFA8008) // (MCI) MCI Data Timeout Register\r
+#define AT91C_MCI_TDR (AT91_CAST(AT91_REG *) 0xFFFA8034) // (MCI) MCI Transmit Data Register\r
+#define AT91C_MCI_IER (AT91_CAST(AT91_REG *) 0xFFFA8044) // (MCI) MCI Interrupt Enable Register\r
+#define AT91C_MCI_BLKR (AT91_CAST(AT91_REG *) 0xFFFA8018) // (MCI) MCI Block Register\r
+#define AT91C_MCI_MR (AT91_CAST(AT91_REG *) 0xFFFA8004) // (MCI) MCI Mode Register\r
+#define AT91C_MCI_IMR (AT91_CAST(AT91_REG *) 0xFFFA804C) // (MCI) MCI Interrupt Mask Register\r
+#define AT91C_MCI_CR (AT91_CAST(AT91_REG *) 0xFFFA8000) // (MCI) MCI Control Register\r
+#define AT91C_MCI_ARGR (AT91_CAST(AT91_REG *) 0xFFFA8010) // (MCI) MCI Argument Register\r
+#define AT91C_MCI_SDCR (AT91_CAST(AT91_REG *) 0xFFFA800C) // (MCI) MCI SD Card Register\r
+#define AT91C_MCI_SR (AT91_CAST(AT91_REG *) 0xFFFA8040) // (MCI) MCI Status Register\r
+#define AT91C_MCI_RSPR (AT91_CAST(AT91_REG *) 0xFFFA8020) // (MCI) MCI Response Register\r
+// ========== Register definition for PDC_TWI0 peripheral ========== \r
+#define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFAC124) // (PDC_TWI0) PDC Transfer Status Register\r
+#define AT91C_TWI0_RPR (AT91_CAST(AT91_REG *) 0xFFFAC100) // (PDC_TWI0) Receive Pointer Register\r
+#define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFAC114) // (PDC_TWI0) Receive Next Counter Register\r
+#define AT91C_TWI0_RCR (AT91_CAST(AT91_REG *) 0xFFFAC104) // (PDC_TWI0) Receive Counter Register\r
+#define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFAC120) // (PDC_TWI0) PDC Transfer Control Register\r
+#define AT91C_TWI0_TPR (AT91_CAST(AT91_REG *) 0xFFFAC108) // (PDC_TWI0) Transmit Pointer Register\r
+#define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFAC110) // (PDC_TWI0) Receive Next Pointer Register\r
+#define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFAC118) // (PDC_TWI0) Transmit Next Pointer Register\r
+#define AT91C_TWI0_TCR (AT91_CAST(AT91_REG *) 0xFFFAC10C) // (PDC_TWI0) Transmit Counter Register\r
+#define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFAC11C) // (PDC_TWI0) Transmit Next Counter Register\r
+// ========== Register definition for TWI0 peripheral ========== \r
+#define AT91C_TWI0_THR (AT91_CAST(AT91_REG *) 0xFFFAC034) // (TWI0) Transmit Holding Register\r
+#define AT91C_TWI0_IDR (AT91_CAST(AT91_REG *) 0xFFFAC028) // (TWI0) Interrupt Disable Register\r
+#define AT91C_TWI0_SMR (AT91_CAST(AT91_REG *) 0xFFFAC008) // (TWI0) Slave Mode Register\r
+#define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *) 0xFFFAC010) // (TWI0) Clock Waveform Generator Register\r
+#define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *) 0xFFFAC00C) // (TWI0) Internal Address Register\r
+#define AT91C_TWI0_RHR (AT91_CAST(AT91_REG *) 0xFFFAC030) // (TWI0) Receive Holding Register\r
+#define AT91C_TWI0_IER (AT91_CAST(AT91_REG *) 0xFFFAC024) // (TWI0) Interrupt Enable Register\r
+#define AT91C_TWI0_MMR (AT91_CAST(AT91_REG *) 0xFFFAC004) // (TWI0) Master Mode Register\r
+#define AT91C_TWI0_SR (AT91_CAST(AT91_REG *) 0xFFFAC020) // (TWI0) Status Register\r
+#define AT91C_TWI0_IMR (AT91_CAST(AT91_REG *) 0xFFFAC02C) // (TWI0) Interrupt Mask Register\r
+#define AT91C_TWI0_CR (AT91_CAST(AT91_REG *) 0xFFFAC000) // (TWI0) Control Register\r
+// ========== Register definition for PDC_TWI1 peripheral ========== \r
+#define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_TWI1) PDC Transfer Status Register\r
+#define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_TWI1) PDC Transfer Control Register\r
+#define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_TWI1) Transmit Next Pointer Register\r
+#define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_TWI1) Transmit Next Counter Register\r
+#define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_TWI1) Receive Next Pointer Register\r
+#define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_TWI1) Receive Next Counter Register\r
+#define AT91C_TWI1_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_TWI1) Receive Pointer Register\r
+#define AT91C_TWI1_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_TWI1) Transmit Counter Register\r
+#define AT91C_TWI1_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_TWI1) Transmit Pointer Register\r
+#define AT91C_TWI1_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_TWI1) Receive Counter Register\r
+// ========== Register definition for TWI1 peripheral ========== \r
+#define AT91C_TWI1_RHR (AT91_CAST(AT91_REG *) 0xFFFD8030) // (TWI1) Receive Holding Register\r
+#define AT91C_TWI1_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (TWI1) Interrupt Enable Register\r
+#define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *) 0xFFFD8010) // (TWI1) Clock Waveform Generator Register\r
+#define AT91C_TWI1_MMR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (TWI1) Master Mode Register\r
+#define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *) 0xFFFD800C) // (TWI1) Internal Address Register\r
+#define AT91C_TWI1_THR (AT91_CAST(AT91_REG *) 0xFFFD8034) // (TWI1) Transmit Holding Register\r
+#define AT91C_TWI1_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (TWI1) Interrupt Mask Register\r
+#define AT91C_TWI1_SR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (TWI1) Status Register\r
+#define AT91C_TWI1_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (TWI1) Interrupt Disable Register\r
+#define AT91C_TWI1_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (TWI1) Control Register\r
+#define AT91C_TWI1_SMR (AT91_CAST(AT91_REG *) 0xFFFD8008) // (TWI1) Slave Mode Register\r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFB010C) // (PDC_US0) Transmit Counter Register\r
+#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFB0120) // (PDC_US0) PDC Transfer Control Register\r
+#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFB0114) // (PDC_US0) Receive Next Counter Register\r
+#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFB0124) // (PDC_US0) PDC Transfer Status Register\r
+#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFB011C) // (PDC_US0) Transmit Next Counter Register\r
+#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFB0110) // (PDC_US0) Receive Next Pointer Register\r
+#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFB0104) // (PDC_US0) Receive Counter Register\r
+#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFB0108) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register\r
+#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFB0100) // (PDC_US0) Receive Pointer Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFB0044) // (US0) Nb Errors Register\r
+#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFB0008) // (US0) Interrupt Enable Register\r
+#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFB0000) // (US0) Control Register\r
+#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (US0) Transmitter Holding Register\r
+#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (US0) Channel Status Register\r
+#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFB0024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFB0028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFB000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFB0004) // (US0) Mode Register\r
+#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFB004C) // (US0) IRDA_FILTER Register\r
+#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFB0040) // (US0) FI_DI_Ratio Register\r
+#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFB0010) // (US0) Interrupt Mask Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFB4120) // (PDC_US1) PDC Transfer Control Register\r
+#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFB4104) // (PDC_US1) Receive Counter Register\r
+#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFB4100) // (PDC_US1) Receive Pointer Register\r
+#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFB4124) // (PDC_US1) PDC Transfer Status Register\r
+#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFB4108) // (PDC_US1) Transmit Pointer Register\r
+#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFB410C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFB4110) // (PDC_US1) Receive Next Pointer Register\r
+#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFB411C) // (PDC_US1) Transmit Next Counter Register\r
+#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFB4114) // (PDC_US1) Receive Next Counter Register\r
+#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFB401C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFB4028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFB4020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFB400C) // (US1) Interrupt Disable Register\r
+#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFB4004) // (US1) Mode Register\r
+#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFB4024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFB4000) // (US1) Control Register\r
+#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFB4010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFB4040) // (US1) FI_DI_Ratio Register\r
+#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFB4018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFB4008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFB4014) // (US1) Channel Status Register\r
+#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFB404C) // (US1) IRDA_FILTER Register\r
+#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFB4044) // (US1) Nb Errors Register\r
+// ========== Register definition for PDC_US2 peripheral ========== \r
+#define AT91C_US2_TNCR (AT91_CAST(AT91_REG *) 0xFFFB811C) // (PDC_US2) Transmit Next Counter Register\r
+#define AT91C_US2_RNCR (AT91_CAST(AT91_REG *) 0xFFFB8114) // (PDC_US2) Receive Next Counter Register\r
+#define AT91C_US2_TNPR (AT91_CAST(AT91_REG *) 0xFFFB8118) // (PDC_US2) Transmit Next Pointer Register\r
+#define AT91C_US2_PTCR (AT91_CAST(AT91_REG *) 0xFFFB8120) // (PDC_US2) PDC Transfer Control Register\r
+#define AT91C_US2_TCR (AT91_CAST(AT91_REG *) 0xFFFB810C) // (PDC_US2) Transmit Counter Register\r
+#define AT91C_US2_RPR (AT91_CAST(AT91_REG *) 0xFFFB8100) // (PDC_US2) Receive Pointer Register\r
+#define AT91C_US2_TPR (AT91_CAST(AT91_REG *) 0xFFFB8108) // (PDC_US2) Transmit Pointer Register\r
+#define AT91C_US2_RCR (AT91_CAST(AT91_REG *) 0xFFFB8104) // (PDC_US2) Receive Counter Register\r
+#define AT91C_US2_PTSR (AT91_CAST(AT91_REG *) 0xFFFB8124) // (PDC_US2) PDC Transfer Status Register\r
+#define AT91C_US2_RNPR (AT91_CAST(AT91_REG *) 0xFFFB8110) // (PDC_US2) Receive Next Pointer Register\r
+// ========== Register definition for US2 peripheral ========== \r
+#define AT91C_US2_RTOR (AT91_CAST(AT91_REG *) 0xFFFB8024) // (US2) Receiver Time-out Register\r
+#define AT91C_US2_CSR (AT91_CAST(AT91_REG *) 0xFFFB8014) // (US2) Channel Status Register\r
+#define AT91C_US2_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (US2) Control Register\r
+#define AT91C_US2_BRGR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (US2) Baud Rate Generator Register\r
+#define AT91C_US2_NER (AT91_CAST(AT91_REG *) 0xFFFB8044) // (US2) Nb Errors Register\r
+#define AT91C_US2_FIDI (AT91_CAST(AT91_REG *) 0xFFFB8040) // (US2) FI_DI_Ratio Register\r
+#define AT91C_US2_TTGR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (US2) Transmitter Time-guard Register\r
+#define AT91C_US2_RHR (AT91_CAST(AT91_REG *) 0xFFFB8018) // (US2) Receiver Holding Register\r
+#define AT91C_US2_IDR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (US2) Interrupt Disable Register\r
+#define AT91C_US2_THR (AT91_CAST(AT91_REG *) 0xFFFB801C) // (US2) Transmitter Holding Register\r
+#define AT91C_US2_MR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (US2) Mode Register\r
+#define AT91C_US2_IMR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (US2) Interrupt Mask Register\r
+#define AT91C_US2_IF (AT91_CAST(AT91_REG *) 0xFFFB804C) // (US2) IRDA_FILTER Register\r
+#define AT91C_US2_IER (AT91_CAST(AT91_REG *) 0xFFFB8008) // (US2) Interrupt Enable Register\r
+// ========== Register definition for PDC_US3 peripheral ========== \r
+#define AT91C_US3_RNPR (AT91_CAST(AT91_REG *) 0xFFFD0110) // (PDC_US3) Receive Next Pointer Register\r
+#define AT91C_US3_RNCR (AT91_CAST(AT91_REG *) 0xFFFD0114) // (PDC_US3) Receive Next Counter Register\r
+#define AT91C_US3_PTSR (AT91_CAST(AT91_REG *) 0xFFFD0124) // (PDC_US3) PDC Transfer Status Register\r
+#define AT91C_US3_PTCR (AT91_CAST(AT91_REG *) 0xFFFD0120) // (PDC_US3) PDC Transfer Control Register\r
+#define AT91C_US3_TCR (AT91_CAST(AT91_REG *) 0xFFFD010C) // (PDC_US3) Transmit Counter Register\r
+#define AT91C_US3_TNPR (AT91_CAST(AT91_REG *) 0xFFFD0118) // (PDC_US3) Transmit Next Pointer Register\r
+#define AT91C_US3_RCR (AT91_CAST(AT91_REG *) 0xFFFD0104) // (PDC_US3) Receive Counter Register\r
+#define AT91C_US3_TPR (AT91_CAST(AT91_REG *) 0xFFFD0108) // (PDC_US3) Transmit Pointer Register\r
+#define AT91C_US3_TNCR (AT91_CAST(AT91_REG *) 0xFFFD011C) // (PDC_US3) Transmit Next Counter Register\r
+#define AT91C_US3_RPR (AT91_CAST(AT91_REG *) 0xFFFD0100) // (PDC_US3) Receive Pointer Register\r
+// ========== Register definition for US3 peripheral ========== \r
+#define AT91C_US3_NER (AT91_CAST(AT91_REG *) 0xFFFD0044) // (US3) Nb Errors Register\r
+#define AT91C_US3_RTOR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (US3) Receiver Time-out Register\r
+#define AT91C_US3_IDR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (US3) Interrupt Disable Register\r
+#define AT91C_US3_MR (AT91_CAST(AT91_REG *) 0xFFFD0004) // (US3) Mode Register\r
+#define AT91C_US3_FIDI (AT91_CAST(AT91_REG *) 0xFFFD0040) // (US3) FI_DI_Ratio Register\r
+#define AT91C_US3_BRGR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (US3) Baud Rate Generator Register\r
+#define AT91C_US3_THR (AT91_CAST(AT91_REG *) 0xFFFD001C) // (US3) Transmitter Holding Register\r
+#define AT91C_US3_CR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (US3) Control Register\r
+#define AT91C_US3_IF (AT91_CAST(AT91_REG *) 0xFFFD004C) // (US3) IRDA_FILTER Register\r
+#define AT91C_US3_IER (AT91_CAST(AT91_REG *) 0xFFFD0008) // (US3) Interrupt Enable Register\r
+#define AT91C_US3_TTGR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (US3) Transmitter Time-guard Register\r
+#define AT91C_US3_RHR (AT91_CAST(AT91_REG *) 0xFFFD0018) // (US3) Receiver Holding Register\r
+#define AT91C_US3_IMR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (US3) Interrupt Mask Register\r
+#define AT91C_US3_CSR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (US3) Channel Status Register\r
+// ========== Register definition for PDC_US4 peripheral ========== \r
+#define AT91C_US4_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_US4) Transmit Next Counter Register\r
+#define AT91C_US4_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_US4) Receive Pointer Register\r
+#define AT91C_US4_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_US4) Receive Next Counter Register\r
+#define AT91C_US4_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_US4) Transmit Pointer Register\r
+#define AT91C_US4_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_US4) PDC Transfer Control Register\r
+#define AT91C_US4_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_US4) Transmit Counter Register\r
+#define AT91C_US4_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_US4) Receive Counter Register\r
+#define AT91C_US4_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_US4) Receive Next Pointer Register\r
+#define AT91C_US4_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_US4) Transmit Next Pointer Register\r
+#define AT91C_US4_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_US4) PDC Transfer Status Register\r
+// ========== Register definition for US4 peripheral ========== \r
+#define AT91C_US4_BRGR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (US4) Baud Rate Generator Register\r
+#define AT91C_US4_THR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (US4) Transmitter Holding Register\r
+#define AT91C_US4_RTOR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (US4) Receiver Time-out Register\r
+#define AT91C_US4_IMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (US4) Interrupt Mask Register\r
+#define AT91C_US4_NER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (US4) Nb Errors Register\r
+#define AT91C_US4_TTGR (AT91_CAST(AT91_REG *) 0xFFFD4028) // (US4) Transmitter Time-guard Register\r
+#define AT91C_US4_FIDI (AT91_CAST(AT91_REG *) 0xFFFD4040) // (US4) FI_DI_Ratio Register\r
+#define AT91C_US4_MR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (US4) Mode Register\r
+#define AT91C_US4_IER (AT91_CAST(AT91_REG *) 0xFFFD4008) // (US4) Interrupt Enable Register\r
+#define AT91C_US4_RHR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (US4) Receiver Holding Register\r
+#define AT91C_US4_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (US4) Control Register\r
+#define AT91C_US4_IF (AT91_CAST(AT91_REG *) 0xFFFD404C) // (US4) IRDA_FILTER Register\r
+#define AT91C_US4_IDR (AT91_CAST(AT91_REG *) 0xFFFD400C) // (US4) Interrupt Disable Register\r
+#define AT91C_US4_CSR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (US4) Channel Status Register\r
+// ========== Register definition for PDC_SSC0 peripheral ========== \r
+#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 0xFFFBC118) // (PDC_SSC0) Transmit Next Pointer Register\r
+#define AT91C_SSC0_TCR (AT91_CAST(AT91_REG *) 0xFFFBC10C) // (PDC_SSC0) Transmit Counter Register\r
+#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 0xFFFBC114) // (PDC_SSC0) Receive Next Counter Register\r
+#define AT91C_SSC0_RPR (AT91_CAST(AT91_REG *) 0xFFFBC100) // (PDC_SSC0) Receive Pointer Register\r
+#define AT91C_SSC0_TPR (AT91_CAST(AT91_REG *) 0xFFFBC108) // (PDC_SSC0) Transmit Pointer Register\r
+#define AT91C_SSC0_RCR (AT91_CAST(AT91_REG *) 0xFFFBC104) // (PDC_SSC0) Receive Counter Register\r
+#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 0xFFFBC110) // (PDC_SSC0) Receive Next Pointer Register\r
+#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 0xFFFBC120) // (PDC_SSC0) PDC Transfer Control Register\r
+#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 0xFFFBC11C) // (PDC_SSC0) Transmit Next Counter Register\r
+#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 0xFFFBC124) // (PDC_SSC0) PDC Transfer Status Register\r
+// ========== Register definition for SSC0 peripheral ========== \r
+#define AT91C_SSC0_IMR (AT91_CAST(AT91_REG *) 0xFFFBC04C) // (SSC0) Interrupt Mask Register\r
+#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 0xFFFBC014) // (SSC0) Receive Frame Mode Register\r
+#define AT91C_SSC0_CR (AT91_CAST(AT91_REG *) 0xFFFBC000) // (SSC0) Control Register\r
+#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 0xFFFBC01C) // (SSC0) Transmit Frame Mode Register\r
+#define AT91C_SSC0_CMR (AT91_CAST(AT91_REG *) 0xFFFBC004) // (SSC0) Clock Mode Register\r
+#define AT91C_SSC0_IER (AT91_CAST(AT91_REG *) 0xFFFBC044) // (SSC0) Interrupt Enable Register\r
+#define AT91C_SSC0_RHR (AT91_CAST(AT91_REG *) 0xFFFBC020) // (SSC0) Receive Holding Register\r
+#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 0xFFFBC010) // (SSC0) Receive Clock ModeRegister\r
+#define AT91C_SSC0_SR (AT91_CAST(AT91_REG *) 0xFFFBC040) // (SSC0) Status Register\r
+#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 0xFFFBC030) // (SSC0) Receive Sync Holding Register\r
+#define AT91C_SSC0_THR (AT91_CAST(AT91_REG *) 0xFFFBC024) // (SSC0) Transmit Holding Register\r
+#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 0xFFFBC018) // (SSC0) Transmit Clock Mode Register\r
+#define AT91C_SSC0_IDR (AT91_CAST(AT91_REG *) 0xFFFBC048) // (SSC0) Interrupt Disable Register\r
+#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 0xFFFBC034) // (SSC0) Transmit Sync Holding Register\r
+// ========== Register definition for PDC_SPI0 peripheral ========== \r
+#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC8120) // (PDC_SPI0) PDC Transfer Control Register\r
+#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFC810C) // (PDC_SPI0) Transmit Counter Register\r
+#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFC8100) // (PDC_SPI0) Receive Pointer Register\r
+#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFC8108) // (PDC_SPI0) Transmit Pointer Register\r
+#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC8124) // (PDC_SPI0) PDC Transfer Status Register\r
+#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC8114) // (PDC_SPI0) Receive Next Counter Register\r
+#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC8118) // (PDC_SPI0) Transmit Next Pointer Register\r
+#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFC8104) // (PDC_SPI0) Receive Counter Register\r
+#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC8110) // (PDC_SPI0) Receive Next Pointer Register\r
+#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC811C) // (PDC_SPI0) Transmit Next Counter Register\r
+// ========== Register definition for SPI0 peripheral ========== \r
+#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFC8018) // (SPI0) Interrupt Disable Register\r
+#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFC800C) // (SPI0) Transmit Data Register\r
+#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFC8010) // (SPI0) Status Register\r
+#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFC8000) // (SPI0) Control Register\r
+#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFC8030) // (SPI0) Chip Select Register\r
+#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFC8008) // (SPI0) Receive Data Register\r
+#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFC8004) // (SPI0) Mode Register\r
+#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFC8014) // (SPI0) Interrupt Enable Register\r
+#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFC801C) // (SPI0) Interrupt Mask Register\r
+// ========== Register definition for PDC_SPI1 peripheral ========== \r
+#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFCC120) // (PDC_SPI1) PDC Transfer Control Register\r
+#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFCC110) // (PDC_SPI1) Receive Next Pointer Register\r
+#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFCC104) // (PDC_SPI1) Receive Counter Register\r
+#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFCC108) // (PDC_SPI1) Transmit Pointer Register\r
+#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFCC124) // (PDC_SPI1) PDC Transfer Status Register\r
+#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFCC11C) // (PDC_SPI1) Transmit Next Counter Register\r
+#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFCC100) // (PDC_SPI1) Receive Pointer Register\r
+#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFCC10C) // (PDC_SPI1) Transmit Counter Register\r
+#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFCC114) // (PDC_SPI1) Receive Next Counter Register\r
+#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFCC118) // (PDC_SPI1) Transmit Next Pointer Register\r
+// ========== Register definition for SPI1 peripheral ========== \r
+#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFCC014) // (SPI1) Interrupt Enable Register\r
+#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFCC008) // (SPI1) Receive Data Register\r
+#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFCC010) // (SPI1) Status Register\r
+#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (SPI1) Interrupt Mask Register\r
+#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (SPI1) Transmit Data Register\r
+#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (SPI1) Interrupt Disable Register\r
+#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFCC030) // (SPI1) Chip Select Register\r
+#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (SPI1) Control Register\r
+#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFCC004) // (SPI1) Mode Register\r
+// ========== Register definition for PDC_ADC peripheral ========== \r
+#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_ADC) PDC Transfer Control Register\r
+#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_ADC) Transmit Pointer Register\r
+#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_ADC) Transmit Counter Register\r
+#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_ADC) Receive Counter Register\r
+#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_ADC) PDC Transfer Status Register\r
+#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_ADC) Receive Next Pointer Register\r
+#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_ADC) Receive Pointer Register\r
+#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_ADC) Transmit Next Counter Register\r
+#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_ADC) Receive Next Counter Register\r
+#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_ADC) Transmit Next Pointer Register\r
+// ========== Register definition for ADC peripheral ========== \r
+#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFE0014) // (ADC) ADC Channel Disable Register\r
+#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFE003C) // (ADC) ADC Channel Data Register 3\r
+#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (ADC) ADC Control Register\r
+#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFE002C) // (ADC) ADC Interrupt Mask Register\r
+#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFE0038) // (ADC) ADC Channel Data Register 2\r
+#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (ADC) ADC Status Register\r
+#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFE0024) // (ADC) ADC Interrupt Enable Register\r
+#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFE004C) // (ADC) ADC Channel Data Register 7\r
+#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFE0030) // (ADC) ADC Channel Data Register 0\r
+#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFE0044) // (ADC) ADC Channel Data Register 5\r
+#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFE0040) // (ADC) ADC Channel Data Register 4\r
+#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFE0010) // (ADC) ADC Channel Enable Register\r
+#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (ADC) ADC Channel Status Register\r
+#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (ADC) ADC Mode Register\r
+#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFE0048) // (ADC) ADC Channel Data Register 6\r
+#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFE0020) // (ADC) ADC Last Converted Data Register\r
+#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFE0034) // (ADC) ADC Channel Data Register 1\r
+#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFE0028) // (ADC) ADC Interrupt Disable Register\r
+// ========== Register definition for EMACB peripheral ========== \r
+#define AT91C_EMACB_USRIO (AT91_CAST(AT91_REG *) 0xFFFC40C0) // (EMACB) USER Input/Output Register\r
+#define AT91C_EMACB_RSE (AT91_CAST(AT91_REG *) 0xFFFC4074) // (EMACB) Receive Symbol Errors Register\r
+#define AT91C_EMACB_SCF (AT91_CAST(AT91_REG *) 0xFFFC4044) // (EMACB) Single Collision Frame Register\r
+#define AT91C_EMACB_STE (AT91_CAST(AT91_REG *) 0xFFFC4084) // (EMACB) SQE Test Error Register\r
+#define AT91C_EMACB_SA1H (AT91_CAST(AT91_REG *) 0xFFFC409C) // (EMACB) Specific Address 1 Top, Last 2 bytes\r
+#define AT91C_EMACB_ROV (AT91_CAST(AT91_REG *) 0xFFFC4070) // (EMACB) Receive Overrun Errors Register\r
+#define AT91C_EMACB_TBQP (AT91_CAST(AT91_REG *) 0xFFFC401C) // (EMACB) Transmit Buffer Queue Pointer\r
+#define AT91C_EMACB_IMR (AT91_CAST(AT91_REG *) 0xFFFC4030) // (EMACB) Interrupt Mask Register\r
+#define AT91C_EMACB_IER (AT91_CAST(AT91_REG *) 0xFFFC4028) // (EMACB) Interrupt Enable Register\r
+#define AT91C_EMACB_REV (AT91_CAST(AT91_REG *) 0xFFFC40FC) // (EMACB) Revision Register\r
+#define AT91C_EMACB_SA3L (AT91_CAST(AT91_REG *) 0xFFFC40A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes\r
+#define AT91C_EMACB_ELE (AT91_CAST(AT91_REG *) 0xFFFC4078) // (EMACB) Excessive Length Errors Register\r
+#define AT91C_EMACB_HRT (AT91_CAST(AT91_REG *) 0xFFFC4094) // (EMACB) Hash Address Top[63:32]\r
+#define AT91C_EMACB_SA2L (AT91_CAST(AT91_REG *) 0xFFFC40A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes\r
+#define AT91C_EMACB_RRE (AT91_CAST(AT91_REG *) 0xFFFC406C) // (EMACB) Receive Ressource Error Register\r
+#define AT91C_EMACB_FRO (AT91_CAST(AT91_REG *) 0xFFFC404C) // (EMACB) Frames Received OK Register\r
+#define AT91C_EMACB_TPQ (AT91_CAST(AT91_REG *) 0xFFFC40BC) // (EMACB) Transmit Pause Quantum Register\r
+#define AT91C_EMACB_ISR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (EMACB) Interrupt Status Register\r
+#define AT91C_EMACB_TSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (EMACB) Transmit Status Register\r
+#define AT91C_EMACB_RLE (AT91_CAST(AT91_REG *) 0xFFFC4088) // (EMACB) Receive Length Field Mismatch Register\r
+#define AT91C_EMACB_USF (AT91_CAST(AT91_REG *) 0xFFFC4080) // (EMACB) Undersize Frames Register\r
+#define AT91C_EMACB_WOL (AT91_CAST(AT91_REG *) 0xFFFC40C4) // (EMACB) Wake On LAN Register\r
+#define AT91C_EMACB_TPF (AT91_CAST(AT91_REG *) 0xFFFC408C) // (EMACB) Transmitted Pause Frames Register\r
+#define AT91C_EMACB_PTR (AT91_CAST(AT91_REG *) 0xFFFC4038) // (EMACB) Pause Time Register\r
+#define AT91C_EMACB_TUND (AT91_CAST(AT91_REG *) 0xFFFC4064) // (EMACB) Transmit Underrun Error Register\r
+#define AT91C_EMACB_MAN (AT91_CAST(AT91_REG *) 0xFFFC4034) // (EMACB) PHY Maintenance Register\r
+#define AT91C_EMACB_RJA (AT91_CAST(AT91_REG *) 0xFFFC407C) // (EMACB) Receive Jabbers Register\r
+#define AT91C_EMACB_SA4L (AT91_CAST(AT91_REG *) 0xFFFC40B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes\r
+#define AT91C_EMACB_CSE (AT91_CAST(AT91_REG *) 0xFFFC4068) // (EMACB) Carrier Sense Error Register\r
+#define AT91C_EMACB_HRB (AT91_CAST(AT91_REG *) 0xFFFC4090) // (EMACB) Hash Address Bottom[31:0]\r
+#define AT91C_EMACB_ALE (AT91_CAST(AT91_REG *) 0xFFFC4054) // (EMACB) Alignment Error Register\r
+#define AT91C_EMACB_SA1L (AT91_CAST(AT91_REG *) 0xFFFC4098) // (EMACB) Specific Address 1 Bottom, First 4 bytes\r
+#define AT91C_EMACB_NCR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (EMACB) Network Control Register\r
+#define AT91C_EMACB_FTO (AT91_CAST(AT91_REG *) 0xFFFC4040) // (EMACB) Frames Transmitted OK Register\r
+#define AT91C_EMACB_ECOL (AT91_CAST(AT91_REG *) 0xFFFC4060) // (EMACB) Excessive Collision Register\r
+#define AT91C_EMACB_DTF (AT91_CAST(AT91_REG *) 0xFFFC4058) // (EMACB) Deferred Transmission Frame Register\r
+#define AT91C_EMACB_SA4H (AT91_CAST(AT91_REG *) 0xFFFC40B4) // (EMACB) Specific Address 4 Top, Last 2 bytes\r
+#define AT91C_EMACB_FCSE (AT91_CAST(AT91_REG *) 0xFFFC4050) // (EMACB) Frame Check Sequence Error Register\r
+#define AT91C_EMACB_TID (AT91_CAST(AT91_REG *) 0xFFFC40B8) // (EMACB) Type ID Checking Register\r
+#define AT91C_EMACB_PFR (AT91_CAST(AT91_REG *) 0xFFFC403C) // (EMACB) Pause Frames received Register\r
+#define AT91C_EMACB_IDR (AT91_CAST(AT91_REG *) 0xFFFC402C) // (EMACB) Interrupt Disable Register\r
+#define AT91C_EMACB_SA3H (AT91_CAST(AT91_REG *) 0xFFFC40AC) // (EMACB) Specific Address 3 Top, Last 2 bytes\r
+#define AT91C_EMACB_NSR (AT91_CAST(AT91_REG *) 0xFFFC4008) // (EMACB) Network Status Register\r
+#define AT91C_EMACB_MCF (AT91_CAST(AT91_REG *) 0xFFFC4048) // (EMACB) Multiple Collision Frame Register\r
+#define AT91C_EMACB_RBQP (AT91_CAST(AT91_REG *) 0xFFFC4018) // (EMACB) Receive Buffer Queue Pointer\r
+#define AT91C_EMACB_RSR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (EMACB) Receive Status Register\r
+#define AT91C_EMACB_SA2H (AT91_CAST(AT91_REG *) 0xFFFC40A4) // (EMACB) Specific Address 2 Top, Last 2 bytes\r
+#define AT91C_EMACB_NCFGR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (EMACB) Network Configuration Register\r
+#define AT91C_EMACB_LCOL (AT91_CAST(AT91_REG *) 0xFFFC405C) // (EMACB) Late Collision Register\r
+// ========== Register definition for UDP peripheral ========== \r
+#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFA4004) // (UDP) Global State Register\r
+#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFA4050) // (UDP) Endpoint FIFO Data Register\r
+#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFA4028) // (UDP) Reset Endpoint Register\r
+#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFA4008) // (UDP) Function Address Register\r
+#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFA4000) // (UDP) Frame Number Register\r
+#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFA4014) // (UDP) Interrupt Disable Register\r
+#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFA4018) // (UDP) Interrupt Mask Register\r
+#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFA4030) // (UDP) Endpoint Control and Status Register\r
+#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFA4010) // (UDP) Interrupt Enable Register\r
+#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFA4020) // (UDP) Interrupt Clear Register\r
+#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFA4074) // (UDP) Transceiver Control Register\r
+#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFA401C) // (UDP) Interrupt Status Register\r
+// ========== Register definition for UHP peripheral ========== \r
+#define AT91C_UHP_HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0050000C) // (UHP) Interrupt Status Register\r
+#define AT91C_UHP_HcCommandStatus (AT91_CAST(AT91_REG *) 0x00500008) // (UHP) Command & status Register\r
+#define AT91C_UHP_HcRhStatus (AT91_CAST(AT91_REG *) 0x00500050) // (UHP) Root Hub Status register\r
+#define AT91C_UHP_HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00500014) // (UHP) Interrupt Disable Register\r
+#define AT91C_UHP_HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00500040) // (UHP) Periodic Start\r
+#define AT91C_UHP_HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00500024) // (UHP) Endpoint Control and Status Register\r
+#define AT91C_UHP_HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0050001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor\r
+#define AT91C_UHP_HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00500028) // (UHP) First endpoint register of the Bulk list\r
+#define AT91C_UHP_HcRevision (AT91_CAST(AT91_REG *) 0x00500000) // (UHP) Revision\r
+#define AT91C_UHP_HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0050002C) // (UHP) Current endpoint of the Bulk list\r
+#define AT91C_UHP_HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0050004C) // (UHP) Root Hub characteristics B\r
+#define AT91C_UHP_HcControlHeadED (AT91_CAST(AT91_REG *) 0x00500020) // (UHP) First Endpoint Descriptor of the Control list\r
+#define AT91C_UHP_HcFmRemaining (AT91_CAST(AT91_REG *) 0x00500038) // (UHP) Bit time remaining in the current Frame\r
+#define AT91C_UHP_HcHCCA (AT91_CAST(AT91_REG *) 0x00500018) // (UHP) Pointer to the Host Controller Communication Area\r
+#define AT91C_UHP_HcLSThreshold (AT91_CAST(AT91_REG *) 0x00500044) // (UHP) LS Threshold\r
+#define AT91C_UHP_HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00500054) // (UHP) Root Hub Port Status Register\r
+#define AT91C_UHP_HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00500010) // (UHP) Interrupt Enable Register\r
+#define AT91C_UHP_HcFmNumber (AT91_CAST(AT91_REG *) 0x0050003C) // (UHP) Frame number\r
+#define AT91C_UHP_HcFmInterval (AT91_CAST(AT91_REG *) 0x00500034) // (UHP) Bit time between 2 consecutive SOFs\r
+#define AT91C_UHP_HcControl (AT91_CAST(AT91_REG *) 0x00500004) // (UHP) Operating modes for the Host Controller\r
+#define AT91C_UHP_HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00500030) // (UHP) Last completed transfer descriptor\r
+#define AT91C_UHP_HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00500048) // (UHP) Root Hub characteristics A\r
+// ========== Register definition for HECC peripheral ========== \r
+// ========== Register definition for HISI peripheral ========== \r
+#define AT91C_HISI_PSIZE (AT91_CAST(AT91_REG *) 0xFFFC0020) // (HISI) Preview Size Register\r
+#define AT91C_HISI_CR1 (AT91_CAST(AT91_REG *) 0xFFFC0000) // (HISI) Control Register 1\r
+#define AT91C_HISI_R2YSET1 (AT91_CAST(AT91_REG *) 0xFFFC003C) // (HISI) Color Space Conversion Register\r
+#define AT91C_HISI_CDBA (AT91_CAST(AT91_REG *) 0xFFFC002C) // (HISI) Codec Dma Address Register\r
+#define AT91C_HISI_IDR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (HISI) Interrupt Disable Register\r
+#define AT91C_HISI_R2YSET2 (AT91_CAST(AT91_REG *) 0xFFFC0040) // (HISI) Color Space Conversion Register\r
+#define AT91C_HISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0xFFFC0034) // (HISI) Color Space Conversion Register\r
+#define AT91C_HISI_PFBD (AT91_CAST(AT91_REG *) 0xFFFC0028) // (HISI) Preview Frame Buffer Address Register\r
+#define AT91C_HISI_CR2 (AT91_CAST(AT91_REG *) 0xFFFC0004) // (HISI) Control Register 2\r
+#define AT91C_HISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0xFFFC0030) // (HISI) Color Space Conversion Register\r
+#define AT91C_HISI_PDECF (AT91_CAST(AT91_REG *) 0xFFFC0024) // (HISI) Preview Decimation Factor Register\r
+#define AT91C_HISI_IMR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (HISI) Interrupt Mask Register\r
+#define AT91C_HISI_IER (AT91_CAST(AT91_REG *) 0xFFFC000C) // (HISI) Interrupt Enable Register\r
+#define AT91C_HISI_R2YSET0 (AT91_CAST(AT91_REG *) 0xFFFC0038) // (HISI) Color Space Conversion Register\r
+#define AT91C_HISI_SR (AT91_CAST(AT91_REG *) 0xFFFC0008) // (HISI) Status Register\r
+\r
+// *****************************************************************************\r
+// PIO DEFINITIONS FOR AT91SAM9XE256\r
+// *****************************************************************************\r
+#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0\r
+#define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) // SPI 0 Master In Slave\r
+#define AT91C_PA0_MCDB0 (AT91C_PIO_PA0) // Multimedia Card B Data 0\r
+#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1\r
+#define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) // SPI 0 Master Out Slave\r
+#define AT91C_PA1_MCCDB (AT91C_PIO_PA1) // Multimedia Card B Command\r
+#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10\r
+#define AT91C_PA10_MCDA2 (AT91C_PIO_PA10) // Multimedia Card A Data 2\r
+#define AT91C_PA10_ETX2_0 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 2\r
+#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11\r
+#define AT91C_PA11_MCDA3 (AT91C_PIO_PA11) // Multimedia Card A Data 3\r
+#define AT91C_PA11_ETX3_0 (AT91C_PIO_PA11) // Ethernet MAC Transmit Data 3\r
+#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12\r
+#define AT91C_PA12_ETX0 (AT91C_PIO_PA12) // Ethernet MAC Transmit Data 0\r
+#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13\r
+#define AT91C_PA13_ETX1 (AT91C_PIO_PA13) // Ethernet MAC Transmit Data 1\r
+#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14\r
+#define AT91C_PA14_ERX0 (AT91C_PIO_PA14) // Ethernet MAC Receive Data 0\r
+#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15\r
+#define AT91C_PA15_ERX1 (AT91C_PIO_PA15) // Ethernet MAC Receive Data 1\r
+#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16\r
+#define AT91C_PA16_ETXEN (AT91C_PIO_PA16) // Ethernet MAC Transmit Enable\r
+#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17\r
+#define AT91C_PA17_ERXDV (AT91C_PIO_PA17) // Ethernet MAC Receive Data Valid\r
+#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18\r
+#define AT91C_PA18_ERXER (AT91C_PIO_PA18) // Ethernet MAC Receive Error\r
+#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19\r
+#define AT91C_PA19_ETXCK (AT91C_PIO_PA19) // Ethernet MAC Transmit Clock/Reference Clock\r
+#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2\r
+#define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) // SPI 0 Serial Clock\r
+#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20\r
+#define AT91C_PA20_EMDC (AT91C_PIO_PA20) // Ethernet MAC Management Data Clock\r
+#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21\r
+#define AT91C_PA21_EMDIO (AT91C_PIO_PA21) // Ethernet MAC Management Data Input/Output\r
+#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22\r
+#define AT91C_PA22_ADTRG (AT91C_PIO_PA22) // ADC Trigger\r
+#define AT91C_PA22_ETXER (AT91C_PIO_PA22) // Ethernet MAC Transmikt Coding Error\r
+#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23\r
+#define AT91C_PA23_TWD0 (AT91C_PIO_PA23) // TWI Two-wire Serial Data 0\r
+#define AT91C_PA23_ETX2_1 (AT91C_PIO_PA23) // Ethernet MAC Transmit Data 2\r
+#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24\r
+#define AT91C_PA24_TWCK0 (AT91C_PIO_PA24) // TWI Two-wire Serial Clock 0\r
+#define AT91C_PA24_ETX3_1 (AT91C_PIO_PA24) // Ethernet MAC Transmit Data 3\r
+#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25\r
+#define AT91C_PA25_TCLK0 (AT91C_PIO_PA25) // Timer Counter 0 external clock input\r
+#define AT91C_PA25_ERX2 (AT91C_PIO_PA25) // Ethernet MAC Receive Data 2\r
+#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26\r
+#define AT91C_PA26_TIOA0 (AT91C_PIO_PA26) // Timer Counter 0 Multipurpose Timer I/O Pin A\r
+#define AT91C_PA26_ERX3 (AT91C_PIO_PA26) // Ethernet MAC Receive Data 3\r
+#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27\r
+#define AT91C_PA27_TIOA1 (AT91C_PIO_PA27) // Timer Counter 1 Multipurpose Timer I/O Pin A\r
+#define AT91C_PA27_ERXCK (AT91C_PIO_PA27) // Ethernet MAC Receive Clock\r
+#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28\r
+#define AT91C_PA28_TIOA2 (AT91C_PIO_PA28) // Timer Counter 2 Multipurpose Timer I/O Pin A\r
+#define AT91C_PA28_ECRS (AT91C_PIO_PA28) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\r
+#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29\r
+#define AT91C_PA29_SCK1 (AT91C_PIO_PA29) // USART 1 Serial Clock\r
+#define AT91C_PA29_ECOL (AT91C_PIO_PA29) // Ethernet MAC Collision Detected\r
+#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3\r
+#define AT91C_PA3_SPI0_NPCS0 (AT91C_PIO_PA3) // SPI 0 Peripheral Chip Select 0\r
+#define AT91C_PA3_MCDB3 (AT91C_PIO_PA3) // Multimedia Card B Data 3\r
+#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30\r
+#define AT91C_PA30_SCK2 (AT91C_PIO_PA30) // USART 2 Serial Clock\r
+#define AT91C_PA30_RXD4 (AT91C_PIO_PA30) // USART 4 Receive Data\r
+#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31\r
+#define AT91C_PA31_SCK0 (AT91C_PIO_PA31) // USART 0 Serial Clock\r
+#define AT91C_PA31_TXD4 (AT91C_PIO_PA31) // USART 4 Transmit Data\r
+#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4\r
+#define AT91C_PA4_RTS2 (AT91C_PIO_PA4) // USART 2 Ready To Send\r
+#define AT91C_PA4_MCDB2 (AT91C_PIO_PA4) // Multimedia Card B Data 2\r
+#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5\r
+#define AT91C_PA5_CTS2 (AT91C_PIO_PA5) // USART 2 Clear To Send\r
+#define AT91C_PA5_MCDB1 (AT91C_PIO_PA5) // Multimedia Card B Data 1\r
+#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6\r
+#define AT91C_PA6_MCDA0 (AT91C_PIO_PA6) // Multimedia Card A Data 0\r
+#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7\r
+#define AT91C_PA7_MCCDA (AT91C_PIO_PA7) // Multimedia Card A Command\r
+#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8\r
+#define AT91C_PA8_MCCK (AT91C_PIO_PA8) // Multimedia Card Clock\r
+#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9\r
+#define AT91C_PA9_MCDA1 (AT91C_PIO_PA9) // Multimedia Card A Data 1\r
+#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0\r
+#define AT91C_PB0_SPI1_MISO (AT91C_PIO_PB0) // SPI 1 Master In Slave\r
+#define AT91C_PB0_TIOA3 (AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin A\r
+#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1\r
+#define AT91C_PB1_SPI1_MOSI (AT91C_PIO_PB1) // SPI 1 Master Out Slave\r
+#define AT91C_PB1_TIOB3 (AT91C_PIO_PB1) // Timer Counter 3 Multipurpose Timer I/O Pin B\r
+#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10\r
+#define AT91C_PB10_TXD3 (AT91C_PIO_PB10) // USART 3 Transmit Data\r
+#define AT91C_PB10_ISI_D8 (AT91C_PIO_PB10) // Image Sensor Data 8\r
+#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11\r
+#define AT91C_PB11_RXD3 (AT91C_PIO_PB11) // USART 3 Receive Data\r
+#define AT91C_PB11_ISI_D9 (AT91C_PIO_PB11) // Image Sensor Data 9\r
+#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12\r
+#define AT91C_PB12_TWD1 (AT91C_PIO_PB12) // TWI Two-wire Serial Data 1\r
+#define AT91C_PB12_ISI_D10 (AT91C_PIO_PB12) // Image Sensor Data 10\r
+#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13\r
+#define AT91C_PB13_TWCK1 (AT91C_PIO_PB13) // TWI Two-wire Serial Clock 1\r
+#define AT91C_PB13_ISI_D11 (AT91C_PIO_PB13) // Image Sensor Data 11\r
+#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14\r
+#define AT91C_PB14_DRXD (AT91C_PIO_PB14) // DBGU Debug Receive Data\r
+#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15\r
+#define AT91C_PB15_DTXD (AT91C_PIO_PB15) // DBGU Debug Transmit Data\r
+#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16\r
+#define AT91C_PB16_TK0 (AT91C_PIO_PB16) // SSC0 Transmit Clock\r
+#define AT91C_PB16_TCLK3 (AT91C_PIO_PB16) // Timer Counter 3 external clock input\r
+#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17\r
+#define AT91C_PB17_TF0 (AT91C_PIO_PB17) // SSC0 Transmit Frame Sync\r
+#define AT91C_PB17_TCLK4 (AT91C_PIO_PB17) // Timer Counter 4 external clock input\r
+#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18\r
+#define AT91C_PB18_TD0 (AT91C_PIO_PB18) // SSC0 Transmit data\r
+#define AT91C_PB18_TIOB4 (AT91C_PIO_PB18) // Timer Counter 4 Multipurpose Timer I/O Pin B\r
+#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19\r
+#define AT91C_PB19_RD0 (AT91C_PIO_PB19) // SSC0 Receive Data\r
+#define AT91C_PB19_TIOB5 (AT91C_PIO_PB19) // Timer Counter 5 Multipurpose Timer I/O Pin B\r
+#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2\r
+#define AT91C_PB2_SPI1_SPCK (AT91C_PIO_PB2) // SPI 1 Serial Clock\r
+#define AT91C_PB2_TIOA4 (AT91C_PIO_PB2) // Timer Counter 4 Multipurpose Timer I/O Pin A\r
+#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20\r
+#define AT91C_PB20_RK0 (AT91C_PIO_PB20) // SSC0 Receive Clock\r
+#define AT91C_PB20_ISI_D0 (AT91C_PIO_PB20) // Image Sensor Data 0\r
+#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21\r
+#define AT91C_PB21_RF0 (AT91C_PIO_PB21) // SSC0 Receive Frame Sync\r
+#define AT91C_PB21_ISI_D1 (AT91C_PIO_PB21) // Image Sensor Data 1\r
+#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22\r
+#define AT91C_PB22_DSR0 (AT91C_PIO_PB22) // USART 0 Data Set ready\r
+#define AT91C_PB22_ISI_D2 (AT91C_PIO_PB22) // Image Sensor Data 2\r
+#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23\r
+#define AT91C_PB23_DCD0 (AT91C_PIO_PB23) // USART 0 Data Carrier Detect\r
+#define AT91C_PB23_ISI_D3 (AT91C_PIO_PB23) // Image Sensor Data 3\r
+#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24\r
+#define AT91C_PB24_DTR0 (AT91C_PIO_PB24) // USART 0 Data Terminal ready\r
+#define AT91C_PB24_ISI_D4 (AT91C_PIO_PB24) // Image Sensor Data 4\r
+#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25\r
+#define AT91C_PB25_RI0 (AT91C_PIO_PB25) // USART 0 Ring Indicator\r
+#define AT91C_PB25_ISI_D5 (AT91C_PIO_PB25) // Image Sensor Data 5\r
+#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26\r
+#define AT91C_PB26_RTS0 (AT91C_PIO_PB26) // USART 0 Ready To Send\r
+#define AT91C_PB26_ISI_D6 (AT91C_PIO_PB26) // Image Sensor Data 6\r
+#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27\r
+#define AT91C_PB27_CTS0 (AT91C_PIO_PB27) // USART 0 Clear To Send\r
+#define AT91C_PB27_ISI_D7 (AT91C_PIO_PB27) // Image Sensor Data 7\r
+#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28\r
+#define AT91C_PB28_RTS1 (AT91C_PIO_PB28) // USART 1 Ready To Send\r
+#define AT91C_PB28_ISI_PCK (AT91C_PIO_PB28) // Image Sensor Data Clock\r
+#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29\r
+#define AT91C_PB29_CTS1 (AT91C_PIO_PB29) // USART 1 Clear To Send\r
+#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) // Image Sensor Vertical Synchro\r
+#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3\r
+#define AT91C_PB3_SPI1_NPCS0 (AT91C_PIO_PB3) // SPI 1 Peripheral Chip Select 0\r
+#define AT91C_PB3_TIOA5 (AT91C_PIO_PB3) // Timer Counter 5 Multipurpose Timer I/O Pin A\r
+#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30\r
+#define AT91C_PB30_PCK0_0 (AT91C_PIO_PB30) // PMC Programmable Clock Output 0\r
+#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) // Image Sensor Horizontal Synchro\r
+#define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31\r
+#define AT91C_PB31_PCK1_0 (AT91C_PIO_PB31) // PMC Programmable Clock Output 1\r
+#define AT91C_PB31_ISI_MCK (AT91C_PIO_PB31) // Image Sensor Reference Clock\r
+#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4\r
+#define AT91C_PB4_TXD0 (AT91C_PIO_PB4) // USART 0 Transmit Data\r
+#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5\r
+#define AT91C_PB5_RXD0 (AT91C_PIO_PB5) // USART 0 Receive Data\r
+#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6\r
+#define AT91C_PB6_TXD1 (AT91C_PIO_PB6) // USART 1 Transmit Data\r
+#define AT91C_PB6_TCLK1 (AT91C_PIO_PB6) // Timer Counter 1 external clock input\r
+#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7\r
+#define AT91C_PB7_RXD1 (AT91C_PIO_PB7) // USART 1 Receive Data\r
+#define AT91C_PB7_TCLK2 (AT91C_PIO_PB7) // Timer Counter 2 external clock input\r
+#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8\r
+#define AT91C_PB8_TXD2 (AT91C_PIO_PB8) // USART 2 Transmit Data\r
+#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9\r
+#define AT91C_PB9_RXD2 (AT91C_PIO_PB9) // USART 2 Receive Data\r
+#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0\r
+#define AT91C_PC0_AD0 (AT91C_PIO_PC0) // ADC Analog Input 0\r
+#define AT91C_PC0_SCK3 (AT91C_PIO_PC0) // USART 3 Serial Clock\r
+#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1\r
+#define AT91C_PC1_AD1 (AT91C_PIO_PC1) // ADC Analog Input 1\r
+#define AT91C_PC1_PCK0 (AT91C_PIO_PC1) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10\r
+#define AT91C_PC10_A25_CFRNW (AT91C_PIO_PC10) // Address Bus[25]\r
+#define AT91C_PC10_CTS3 (AT91C_PIO_PC10) // USART 3 Clear To Send\r
+#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11\r
+#define AT91C_PC11_NCS2 (AT91C_PIO_PC11) // Chip Select Line 2\r
+#define AT91C_PC11_SPI0_NPCS1 (AT91C_PIO_PC11) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12\r
+#define AT91C_PC12_IRQ0 (AT91C_PIO_PC12) // External Interrupt 0\r
+#define AT91C_PC12_NCS7 (AT91C_PIO_PC12) // Chip Select Line 7\r
+#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13\r
+#define AT91C_PC13_FIQ (AT91C_PIO_PC13) // AIC Fast Interrupt Input\r
+#define AT91C_PC13_NCS6 (AT91C_PIO_PC13) // Chip Select Line 6\r
+#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14\r
+#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) // Chip Select Line 3\r
+#define AT91C_PC14_IRQ2 (AT91C_PIO_PC14) // External Interrupt 2\r
+#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15\r
+#define AT91C_PC15_NWAIT (AT91C_PIO_PC15) // External Wait Signal\r
+#define AT91C_PC15_IRQ1 (AT91C_PIO_PC15) // External Interrupt 1\r
+#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16\r
+#define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus[16]\r
+#define AT91C_PC16_SPI0_NPCS2 (AT91C_PIO_PC16) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17\r
+#define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus[17]\r
+#define AT91C_PC17_SPI0_NPCS3 (AT91C_PIO_PC17) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18\r
+#define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus[18]\r
+#define AT91C_PC18_SPI1_NPCS1_1 (AT91C_PIO_PC18) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19\r
+#define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus[19]\r
+#define AT91C_PC19_SPI1_NPCS2_1 (AT91C_PIO_PC19) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2\r
+#define AT91C_PC2_AD2 (AT91C_PIO_PC2) // ADC Analog Input 2\r
+#define AT91C_PC2_PCK1 (AT91C_PIO_PC2) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20\r
+#define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus[20]\r
+#define AT91C_PC20_SPI1_NPCS3_1 (AT91C_PIO_PC20) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21\r
+#define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus[21]\r
+#define AT91C_PC21_EF100 (AT91C_PIO_PC21) // Ethernet MAC Force 100 Mbits/sec\r
+#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22\r
+#define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus[22]\r
+#define AT91C_PC22_TCLK5 (AT91C_PIO_PC22) // Timer Counter 5 external clock input\r
+#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23\r
+#define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus[23]\r
+#define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24\r
+#define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus[24]\r
+#define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25\r
+#define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus[25]\r
+#define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26\r
+#define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus[26]\r
+#define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27\r
+#define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus[27]\r
+#define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28\r
+#define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus[28]\r
+#define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29\r
+#define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus[29]\r
+#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3\r
+#define AT91C_PC3_AD3 (AT91C_PIO_PC3) // ADC Analog Input 3\r
+#define AT91C_PC3_SPI1_NPCS3_0 (AT91C_PIO_PC3) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30\r
+#define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus[30]\r
+#define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31\r
+#define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus[31]\r
+#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4\r
+#define AT91C_PC4_A23 (AT91C_PIO_PC4) // Address Bus[23]\r
+#define AT91C_PC4_SPI1_NPCS2_0 (AT91C_PIO_PC4) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5\r
+#define AT91C_PC5_A24 (AT91C_PIO_PC5) // Address Bus[24]\r
+#define AT91C_PC5_SPI1_NPCS1_0 (AT91C_PIO_PC5) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6\r
+#define AT91C_PC6_TIOB2 (AT91C_PIO_PC6) // Timer Counter 2 Multipurpose Timer I/O Pin B\r
+#define AT91C_PC6_CFCE1 (AT91C_PIO_PC6) // Compact Flash Enable 1\r
+#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7\r
+#define AT91C_PC7_TIOB1 (AT91C_PIO_PC7) // Timer Counter 1 Multipurpose Timer I/O Pin B\r
+#define AT91C_PC7_CFCE2 (AT91C_PIO_PC7) // Compact Flash Enable 2\r
+#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8\r
+#define AT91C_PC8_NCS4_CFCS0 (AT91C_PIO_PC8) // Chip Select Line 4\r
+#define AT91C_PC8_RTS3 (AT91C_PIO_PC8) // USART 3 Ready To Send\r
+#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9\r
+#define AT91C_PC9_NCS5_CFCS1 (AT91C_PIO_PC9) // Chip Select Line 5\r
+#define AT91C_PC9_TIOB0 (AT91C_PIO_PC9) // Timer Counter 0 Multipurpose Timer I/O Pin B\r
+\r
+// *****************************************************************************\r
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM9XE256\r
+// *****************************************************************************\r
+#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)\r
+#define AT91C_ID_SYS ( 1) // System Controller\r
+#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A\r
+#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B\r
+#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C\r
+#define AT91C_ID_ADC ( 5) // ADC\r
+#define AT91C_ID_US0 ( 6) // USART 0\r
+#define AT91C_ID_US1 ( 7) // USART 1\r
+#define AT91C_ID_US2 ( 8) // USART 2\r
+#define AT91C_ID_MCI ( 9) // Multimedia Card Interface 0\r
+#define AT91C_ID_UDP (10) // USB Device Port\r
+#define AT91C_ID_TWI0 (11) // Two-Wire Interface 0\r
+#define AT91C_ID_SPI0 (12) // Serial Peripheral Interface 0\r
+#define AT91C_ID_SPI1 (13) // Serial Peripheral Interface 1\r
+#define AT91C_ID_SSC0 (14) // Serial Synchronous Controller 0\r
+#define AT91C_ID_TC0 (17) // Timer Counter 0\r
+#define AT91C_ID_TC1 (18) // Timer Counter 1\r
+#define AT91C_ID_TC2 (19) // Timer Counter 2\r
+#define AT91C_ID_UHP (20) // USB Host Port\r
+#define AT91C_ID_EMAC (21) // Ethernet Mac\r
+#define AT91C_ID_HISI (22) // Image Sensor Interface\r
+#define AT91C_ID_US3 (23) // USART 3\r
+#define AT91C_ID_US4 (24) // USART 4\r
+#define AT91C_ID_TWI1 (25) // Two-Wire Interface 1\r
+#define AT91C_ID_TC3 (26) // Timer Counter 3\r
+#define AT91C_ID_TC4 (27) // Timer Counter 4\r
+#define AT91C_ID_TC5 (28) // Timer Counter 5\r
+#define AT91C_ID_IRQ0 (29) // Advanced Interrupt Controller (IRQ0)\r
+#define AT91C_ID_IRQ1 (30) // Advanced Interrupt Controller (IRQ1)\r
+#define AT91C_ID_IRQ2 (31) // Advanced Interrupt Controller (IRQ2)\r
+#define AT91C_ALL_INT (0xFFFE7FFF) // ALL VALID INTERRUPTS\r
+\r
+// *****************************************************************************\r
+// BASE ADDRESS DEFINITIONS FOR AT91SAM9XE256\r
+// *****************************************************************************\r
+#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFFD00) // (SYS) Base Address\r
+#define AT91C_BASE_EBI (AT91_CAST(AT91PS_EBI) 0xFFFFEA00) // (EBI) Base Address\r
+#define AT91C_BASE_HECC (AT91_CAST(AT91PS_ECC) 0xFFFFE800) // (HECC) Base Address\r
+#define AT91C_BASE_SDRAMC (AT91_CAST(AT91PS_SDRAMC) 0xFFFFEA00) // (SDRAMC) Base Address\r
+#define AT91C_BASE_SMC (AT91_CAST(AT91PS_SMC) 0xFFFFEC00) // (SMC) Base Address\r
+#define AT91C_BASE_MATRIX (AT91_CAST(AT91PS_MATRIX) 0xFFFFEE00) // (MATRIX) Base Address\r
+#define AT91C_BASE_CCFG (AT91_CAST(AT91PS_CCFG) 0xFFFFEF10) // (CCFG) Base Address\r
+#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address\r
+#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address\r
+#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address\r
+#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address\r
+#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address\r
+#define AT91C_BASE_PIOC (AT91_CAST(AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address\r
+#define AT91C_BASE_EFC (AT91_CAST(AT91PS_EFC) 0xFFFFFA00) // (EFC) Base Address\r
+#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address\r
+#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address\r
+#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address\r
+#define AT91C_BASE_SHDWC (AT91_CAST(AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address\r
+#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address\r
+#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address\r
+#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address\r
+#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address\r
+#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address\r
+#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address\r
+#define AT91C_BASE_TC3 (AT91_CAST(AT91PS_TC) 0xFFFDC000) // (TC3) Base Address\r
+#define AT91C_BASE_TC4 (AT91_CAST(AT91PS_TC) 0xFFFDC040) // (TC4) Base Address\r
+#define AT91C_BASE_TC5 (AT91_CAST(AT91PS_TC) 0xFFFDC080) // (TC5) Base Address\r
+#define AT91C_BASE_TCB0 (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address\r
+#define AT91C_BASE_TCB1 (AT91_CAST(AT91PS_TCB) 0xFFFDC000) // (TCB1) Base Address\r
+#define AT91C_BASE_PDC_MCI (AT91_CAST(AT91PS_PDC) 0xFFFA8100) // (PDC_MCI) Base Address\r
+#define AT91C_BASE_MCI (AT91_CAST(AT91PS_MCI) 0xFFFA8000) // (MCI) Base Address\r
+#define AT91C_BASE_PDC_TWI0 (AT91_CAST(AT91PS_PDC) 0xFFFAC100) // (PDC_TWI0) Base Address\r
+#define AT91C_BASE_TWI0 (AT91_CAST(AT91PS_TWI) 0xFFFAC000) // (TWI0) Base Address\r
+#define AT91C_BASE_PDC_TWI1 (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_TWI1) Base Address\r
+#define AT91C_BASE_TWI1 (AT91_CAST(AT91PS_TWI) 0xFFFD8000) // (TWI1) Base Address\r
+#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFB0100) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFB0000) // (US0) Base Address\r
+#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFB4100) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFB4000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US2 (AT91_CAST(AT91PS_PDC) 0xFFFB8100) // (PDC_US2) Base Address\r
+#define AT91C_BASE_US2 (AT91_CAST(AT91PS_USART) 0xFFFB8000) // (US2) Base Address\r
+#define AT91C_BASE_PDC_US3 (AT91_CAST(AT91PS_PDC) 0xFFFD0100) // (PDC_US3) Base Address\r
+#define AT91C_BASE_US3 (AT91_CAST(AT91PS_USART) 0xFFFD0000) // (US3) Base Address\r
+#define AT91C_BASE_PDC_US4 (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_US4) Base Address\r
+#define AT91C_BASE_US4 (AT91_CAST(AT91PS_USART) 0xFFFD4000) // (US4) Base Address\r
+#define AT91C_BASE_PDC_SSC0 (AT91_CAST(AT91PS_PDC) 0xFFFBC100) // (PDC_SSC0) Base Address\r
+#define AT91C_BASE_SSC0 (AT91_CAST(AT91PS_SSC) 0xFFFBC000) // (SSC0) Base Address\r
+#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFC8100) // (PDC_SPI0) Base Address\r
+#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFC8000) // (SPI0) Base Address\r
+#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFCC100) // (PDC_SPI1) Base Address\r
+#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFCC000) // (SPI1) Base Address\r
+#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_ADC) Base Address\r
+#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFE0000) // (ADC) Base Address\r
+#define AT91C_BASE_EMACB (AT91_CAST(AT91PS_EMAC) 0xFFFC4000) // (EMACB) Base Address\r
+#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFA4000) // (UDP) Base Address\r
+#define AT91C_BASE_UHP (AT91_CAST(AT91PS_UHP) 0x00500000) // (UHP) Base Address\r
+#define AT91C_BASE_HISI (AT91_CAST(AT91PS_ISI) 0xFFFC0000) // (HISI) Base Address\r
+\r
+// *****************************************************************************\r
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM9XE256\r
+// *****************************************************************************\r
+// IROM\r
+#define AT91C_IROM (0x00100000) // Internal ROM base address\r
+#define AT91C_IROM_SIZE (0x00008000) // Internal ROM size in byte (32 Kbytes)\r
+// ISRAM\r
+#define AT91C_ISRAM (0x00300000) // Maximum IRAM Area : 32Kbyte base address\r
+#define AT91C_ISRAM_SIZE (0x00008000) // Maximum IRAM Area : 32Kbyte size in byte (32 Kbytes)\r
+// ISRAM_MIN\r
+#define AT91C_ISRAM_MIN (0x00300000) // Minimun IRAM Area : 32Kbyte base address\r
+#define AT91C_ISRAM_MIN_SIZE (0x00008000) // Minimun IRAM Area : 32Kbyte size in byte (32 Kbytes)\r
+// IFLASH\r
+#define AT91C_IFLASH (0x00200000) // Maximum IFLASH Area : 256Kbyte base address\r
+#define AT91C_IFLASH_SIZE (0x00040000) // Maximum IFLASH Area : 256Kbyte size in byte (256 Kbytes)\r
+#define AT91C_IFLASH_PAGE_SIZE (512) // Maximum IFLASH Area : 256Kbyte Page Size: 512 bytes\r
+#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Maximum IFLASH Area : 256Kbyte Lock Region Size: 16 Kbytes\r
+#define AT91C_IFLASH_NB_OF_PAGES (512) // Maximum IFLASH Area : 256Kbyte Number of Pages: 512 bytes\r
+#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Maximum IFLASH Area : 256Kbyte Number of Lock Bits: 16 bytes\r
+// EBI_CS0\r
+#define AT91C_EBI_CS0 (0x10000000) // EBI Chip Select 0 base address\r
+#define AT91C_EBI_CS0_SIZE (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)\r
+// EBI_CS1\r
+#define AT91C_EBI_CS1 (0x20000000) // EBI Chip Select 1 base address\r
+#define AT91C_EBI_CS1_SIZE (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)\r
+// EBI_SDRAM\r
+#define AT91C_EBI_SDRAM (0x20000000) // SDRAM on EBI Chip Select 1 base address\r
+#define AT91C_EBI_SDRAM_SIZE (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes)\r
+// EBI_SDRAM_16BIT\r
+#define AT91C_EBI_SDRAM_16BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address\r
+#define AT91C_EBI_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes)\r
+// EBI_SDRAM_32BIT\r
+#define AT91C_EBI_SDRAM_32BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address\r
+#define AT91C_EBI_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes)\r
+// EBI_CS2\r
+#define AT91C_EBI_CS2 (0x30000000) // EBI Chip Select 2 base address\r
+#define AT91C_EBI_CS2_SIZE (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)\r
+// EBI_CS3\r
+#define AT91C_EBI_CS3 (0x40000000) // EBI Chip Select 3 base address\r
+#define AT91C_EBI_CS3_SIZE (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)\r
+// EBI_SM\r
+#define AT91C_EBI_SM (0x40000000) // SmartMedia on Chip Select 3 base address\r
+#define AT91C_EBI_SM_SIZE (0x10000000) // SmartMedia on Chip Select 3 size in byte (262144 Kbytes)\r
+// EBI_CS4\r
+#define AT91C_EBI_CS4 (0x50000000) // EBI Chip Select 4 base address\r
+#define AT91C_EBI_CS4_SIZE (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)\r
+// EBI_CF0\r
+#define AT91C_EBI_CF0 (0x50000000) // CompactFlash 0 on Chip Select 4 base address\r
+#define AT91C_EBI_CF0_SIZE (0x10000000) // CompactFlash 0 on Chip Select 4 size in byte (262144 Kbytes)\r
+// EBI_CS5\r
+#define AT91C_EBI_CS5 (0x60000000) // EBI Chip Select 5 base address\r
+#define AT91C_EBI_CS5_SIZE (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)\r
+// EBI_CF1\r
+#define AT91C_EBI_CF1 (0x60000000) // CompactFlash 1 on Chip Select 5 base address\r
+#define AT91C_EBI_CF1_SIZE (0x10000000) // CompactFlash 1 on Chip Select 5 size in byte (262144 Kbytes)\r
+// EBI_CS6\r
+#define AT91C_EBI_CS6 (0x70000000) // EBI Chip Select 6 base address\r
+#define AT91C_EBI_CS6_SIZE (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes)\r
+// EBI_CS7\r
+#define AT91C_EBI_CS7 (0x80000000) // EBI Chip Select 7 base address\r
+#define AT91C_EBI_CS7_SIZE (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes)\r
+\r
+#endif\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x200000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x23FFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x300000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_startup__ = 0x100;\r
+define symbol __ICFEDIT_size_vectors__ = 0x100;\r
+define symbol __ICFEDIT_size_cstack__ = 0x1000;\r
+define symbol __ICFEDIT_size_svcstack__ = 0x60;\r
+define symbol __ICFEDIT_size_irqstack__ = 0x60;\r
+define symbol __ICFEDIT_size_heap__ = 0x0;\r
+/*-Exports-*/\r
+export symbol __ICFEDIT_region_ROM_start__;\r
+export symbol __ICFEDIT_region_ROM_end__;\r
+export symbol __ICFEDIT_region_RAM_start__;\r
+export symbol __ICFEDIT_region_RAM_end__;\r
+export symbol __ICFEDIT_size_startup__;\r
+export symbol __ICFEDIT_size_vectors__;\r
+export symbol __ICFEDIT_size_cstack__;\r
+export symbol __ICFEDIT_size_svcstack__;\r
+export symbol __ICFEDIT_size_irqstack__;\r
+export symbol __ICFEDIT_size_heap__;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region STA_region = mem:[from __ICFEDIT_region_ROM_start__ size __ICFEDIT_size_startup__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_ROM_end__];\r
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };\r
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+initialize by copy { section .vectors };\r
+do not initialize { section .noinit };\r
+\r
+place in STA_region { section .cstartup };\r
+place in ROM_region { readonly };\r
+place in VEC_region { section .vectors };\r
+place in RAM_region { readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };\r
+\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_SDRAM_end__ = 0x21FFFFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x300000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_startup__ = 0x100;\r
+define symbol __ICFEDIT_size_vectors__ = 0x100;\r
+define symbol __ICFEDIT_size_cstack__ = 0x1000;\r
+define symbol __ICFEDIT_size_svcstack__ = 0x60;\r
+define symbol __ICFEDIT_size_irqstack__ = 0x60;\r
+define symbol __ICFEDIT_size_heap__ = 0x0;\r
+/*-Exports-*/\r
+export symbol __ICFEDIT_region_SDRAM_start__;\r
+export symbol __ICFEDIT_region_SDRAM_end__;\r
+export symbol __ICFEDIT_region_RAM_start__;\r
+export symbol __ICFEDIT_region_RAM_end__;\r
+export symbol __ICFEDIT_size_startup__;\r
+export symbol __ICFEDIT_size_vectors__;\r
+export symbol __ICFEDIT_size_cstack__;\r
+export symbol __ICFEDIT_size_svcstack__;\r
+export symbol __ICFEDIT_size_irqstack__;\r
+export symbol __ICFEDIT_size_heap__;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region STA_region = mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__];\r
+define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__];\r
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };\r
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { section .vectors };\r
+do not initialize { section .noinit };\r
+\r
+place in STA_region { section .cstartup };\r
+place in VEC_region { section .vectors };\r
+place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };\r
+\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x300000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_vectors__ = 0x100;\r
+define symbol __ICFEDIT_size_cstack__ = 0x800;\r
+define symbol __ICFEDIT_size_svcstack__ = 0x60;\r
+define symbol __ICFEDIT_size_irqstack__ = 0x60;\r
+define symbol __ICFEDIT_size_heap__ = 0x0;\r
+/*-Exports-*/\r
+export symbol __ICFEDIT_region_RAM_start__;\r
+export symbol __ICFEDIT_region_RAM_end__;\r
+export symbol __ICFEDIT_size_vectors__;\r
+export symbol __ICFEDIT_size_cstack__;\r
+export symbol __ICFEDIT_size_svcstack__;\r
+export symbol __ICFEDIT_size_irqstack__;\r
+export symbol __ICFEDIT_size_heap__;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };\r
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+do not initialize { section .noinit };\r
+\r
+place in VEC_region { section .vectors };\r
+place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };\r
+\r
--- /dev/null
+// ----------------------------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ----------------------------------------------------------------------------\r
+// Copyright (c) 2006, Atmel Corporation\r
+// \r
+// All rights reserved.\r
+// \r
+// Redistribution and use in source and binary forms, with or without\r
+// modification, are permitted provided that the following conditions are met:\r
+// \r
+// - Redistributions of source code must retain the above copyright notice,\r
+// this list of conditions and the disclaimer below.\r
+// \r
+// - Redistributions in binary form must reproduce the above copyright notice,\r
+// this list of conditions and the disclaimer below in the documentation and/or\r
+// other materials provided with the distribution. \r
+// \r
+// Atmel's name may not be used to endorse or promote products derived from\r
+// this software without specific prior written permission. \r
+// \r
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+// ----------------------------------------------------------------------------\r
+// File Name : AT91SAM9XE512.h\r
+// Object : AT91SAM9XE512 definitions\r
+// Generated : AT91 SW Application Group 02/13/2008 (18:25:59)\r
+// \r
+// CVS Reference : /AT91SAM9XE512.pl/1.16/Wed Jan 30 14:02:22 2008//\r
+// CVS Reference : /SYS_SAM9260.pl/1.2/Wed Feb 13 13:29:23 2008//\r
+// CVS Reference : /HMATRIX1_SAM9260.pl/1.7/Mon Apr 23 10:39:45 2007//\r
+// CVS Reference : /CCR_SAM9260.pl/1.2/Mon Apr 16 10:47:39 2007//\r
+// CVS Reference : /PMC_SAM9262.pl/1.4/Mon Mar 7 18:03:13 2005//\r
+// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//\r
+// CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004//\r
+// CVS Reference : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//\r
+// CVS Reference : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//\r
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//\r
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//\r
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//\r
+// CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004//\r
+// CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 6 14:16:58 2004//\r
+// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//\r
+// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//\r
+// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//\r
+// CVS Reference : /EFC2_IGS036.pl/1.2/Fri Nov 10 10:47:53 2006//\r
+// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//\r
+// CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 3 13:20:23 2005//\r
+// CVS Reference : /TWI_6061B.pl/1.2/Fri Aug 4 08:53:02 2006//\r
+// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//\r
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//\r
+// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//\r
+// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//\r
+// CVS Reference : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006//\r
+// CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//\r
+// CVS Reference : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005//\r
+// CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 9 17:16:57 2005//\r
+// CVS Reference : /ISI_xxxxx.pl/1.3/Thu Mar 3 11:11:48 2005//\r
+// ----------------------------------------------------------------------------\r
+\r
+#ifndef AT91SAM9XE512_H\r
+#define AT91SAM9XE512_H\r
+\r
+#ifndef __ASSEMBLY__\r
+typedef volatile unsigned int AT91_REG;// Hardware register definition\r
+#define AT91_CAST(a) (a)\r
+#else\r
+#define AT91_CAST(a)\r
+#endif\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR System Peripherals\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SYS {\r
+ AT91_REG Reserved0[2560]; // \r
+ AT91_REG ECC_CR; // ECC reset register\r
+ AT91_REG ECC_MR; // ECC Page size register\r
+ AT91_REG ECC_SR; // ECC Status register\r
+ AT91_REG ECC_PR; // ECC Parity register\r
+ AT91_REG ECC_NPR; // ECC Parity N register\r
+ AT91_REG Reserved1[58]; // \r
+ AT91_REG ECC_VR; // ECC Version register\r
+ AT91_REG Reserved2[64]; // \r
+ AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register\r
+ AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register\r
+ AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register\r
+ AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register\r
+ AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register\r
+ AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register\r
+ AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register\r
+ AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register\r
+ AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register\r
+ AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register\r
+ AT91_REG Reserved3[118]; // \r
+ AT91_REG SMC_SETUP0; // Setup Register for CS 0\r
+ AT91_REG SMC_PULSE0; // Pulse Register for CS 0\r
+ AT91_REG SMC_CYCLE0; // Cycle Register for CS 0\r
+ AT91_REG SMC_CTRL0; // Control Register for CS 0\r
+ AT91_REG SMC_SETUP1; // Setup Register for CS 1\r
+ AT91_REG SMC_PULSE1; // Pulse Register for CS 1\r
+ AT91_REG SMC_CYCLE1; // Cycle Register for CS 1\r
+ AT91_REG SMC_CTRL1; // Control Register for CS 1\r
+ AT91_REG SMC_SETUP2; // Setup Register for CS 2\r
+ AT91_REG SMC_PULSE2; // Pulse Register for CS 2\r
+ AT91_REG SMC_CYCLE2; // Cycle Register for CS 2\r
+ AT91_REG SMC_CTRL2; // Control Register for CS 2\r
+ AT91_REG SMC_SETUP3; // Setup Register for CS 3\r
+ AT91_REG SMC_PULSE3; // Pulse Register for CS 3\r
+ AT91_REG SMC_CYCLE3; // Cycle Register for CS 3\r
+ AT91_REG SMC_CTRL3; // Control Register for CS 3\r
+ AT91_REG SMC_SETUP4; // Setup Register for CS 4\r
+ AT91_REG SMC_PULSE4; // Pulse Register for CS 4\r
+ AT91_REG SMC_CYCLE4; // Cycle Register for CS 4\r
+ AT91_REG SMC_CTRL4; // Control Register for CS 4\r
+ AT91_REG SMC_SETUP5; // Setup Register for CS 5\r
+ AT91_REG SMC_PULSE5; // Pulse Register for CS 5\r
+ AT91_REG SMC_CYCLE5; // Cycle Register for CS 5\r
+ AT91_REG SMC_CTRL5; // Control Register for CS 5\r
+ AT91_REG SMC_SETUP6; // Setup Register for CS 6\r
+ AT91_REG SMC_PULSE6; // Pulse Register for CS 6\r
+ AT91_REG SMC_CYCLE6; // Cycle Register for CS 6\r
+ AT91_REG SMC_CTRL6; // Control Register for CS 6\r
+ AT91_REG SMC_SETUP7; // Setup Register for CS 7\r
+ AT91_REG SMC_PULSE7; // Pulse Register for CS 7\r
+ AT91_REG SMC_CYCLE7; // Cycle Register for CS 7\r
+ AT91_REG SMC_CTRL7; // Control Register for CS 7\r
+ AT91_REG Reserved4[96]; // \r
+ AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k) \r
+ AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom) \r
+ AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs) \r
+ AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi)\r
+ AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge) \r
+ AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox) \r
+ AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k) \r
+ AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog) \r
+ AT91_REG Reserved5[8]; // \r
+ AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k) \r
+ AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom) \r
+ AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs) \r
+ AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi)\r
+ AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge) \r
+ AT91_REG Reserved6[11]; // \r
+ AT91_REG MATRIX_PRAS0; // PRAS0 (ram0) \r
+ AT91_REG MATRIX_PRBS0; // PRBS0 (ram0) \r
+ AT91_REG MATRIX_PRAS1; // PRAS1 (ram1) \r
+ AT91_REG MATRIX_PRBS1; // PRBS1 (ram1) \r
+ AT91_REG MATRIX_PRAS2; // PRAS2 (ram2) \r
+ AT91_REG MATRIX_PRBS2; // PRBS2 (ram2) \r
+ AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs\r
+ AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs\r
+ AT91_REG MATRIX_PRAS4; // PRAS4 : ebi\r
+ AT91_REG MATRIX_PRBS4; // PRBS4 : ebi\r
+ AT91_REG Reserved7[22]; // \r
+ AT91_REG MATRIX_MRCR; // Master Remp Control Register \r
+ AT91_REG Reserved8[6]; // \r
+ AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register\r
+ AT91_REG Reserved9[3]; // \r
+ AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register\r
+ AT91_REG Reserved10[51]; // \r
+ AT91_REG CCFG_MATRIXVERSION; // Version Register\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved11[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved12[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+ AT91_REG Reserved13[45]; // \r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved14[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved15[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+ AT91_REG Reserved16[54]; // \r
+ AT91_REG PIOA_PER; // PIO Enable Register\r
+ AT91_REG PIOA_PDR; // PIO Disable Register\r
+ AT91_REG PIOA_PSR; // PIO Status Register\r
+ AT91_REG Reserved17[1]; // \r
+ AT91_REG PIOA_OER; // Output Enable Register\r
+ AT91_REG PIOA_ODR; // Output Disable Registerr\r
+ AT91_REG PIOA_OSR; // Output Status Register\r
+ AT91_REG Reserved18[1]; // \r
+ AT91_REG PIOA_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOA_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved19[1]; // \r
+ AT91_REG PIOA_SODR; // Set Output Data Register\r
+ AT91_REG PIOA_CODR; // Clear Output Data Register\r
+ AT91_REG PIOA_ODSR; // Output Data Status Register\r
+ AT91_REG PIOA_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOA_IER; // Interrupt Enable Register\r
+ AT91_REG PIOA_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOA_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOA_ISR; // Interrupt Status Register\r
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved20[1]; // \r
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved21[1]; // \r
+ AT91_REG PIOA_ASR; // Select A Register\r
+ AT91_REG PIOA_BSR; // Select B Register\r
+ AT91_REG PIOA_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved22[9]; // \r
+ AT91_REG PIOA_OWER; // Output Write Enable Register\r
+ AT91_REG PIOA_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOA_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved23[213]; // \r
+ AT91_REG PIOB_PER; // PIO Enable Register\r
+ AT91_REG PIOB_PDR; // PIO Disable Register\r
+ AT91_REG PIOB_PSR; // PIO Status Register\r
+ AT91_REG Reserved24[1]; // \r
+ AT91_REG PIOB_OER; // Output Enable Register\r
+ AT91_REG PIOB_ODR; // Output Disable Registerr\r
+ AT91_REG PIOB_OSR; // Output Status Register\r
+ AT91_REG Reserved25[1]; // \r
+ AT91_REG PIOB_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOB_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved26[1]; // \r
+ AT91_REG PIOB_SODR; // Set Output Data Register\r
+ AT91_REG PIOB_CODR; // Clear Output Data Register\r
+ AT91_REG PIOB_ODSR; // Output Data Status Register\r
+ AT91_REG PIOB_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOB_IER; // Interrupt Enable Register\r
+ AT91_REG PIOB_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOB_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOB_ISR; // Interrupt Status Register\r
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved27[1]; // \r
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved28[1]; // \r
+ AT91_REG PIOB_ASR; // Select A Register\r
+ AT91_REG PIOB_BSR; // Select B Register\r
+ AT91_REG PIOB_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved29[9]; // \r
+ AT91_REG PIOB_OWER; // Output Write Enable Register\r
+ AT91_REG PIOB_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOB_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved30[85]; // \r
+ AT91_REG PIOC_PER; // PIO Enable Register\r
+ AT91_REG PIOC_PDR; // PIO Disable Register\r
+ AT91_REG PIOC_PSR; // PIO Status Register\r
+ AT91_REG Reserved31[1]; // \r
+ AT91_REG PIOC_OER; // Output Enable Register\r
+ AT91_REG PIOC_ODR; // Output Disable Registerr\r
+ AT91_REG PIOC_OSR; // Output Status Register\r
+ AT91_REG Reserved32[1]; // \r
+ AT91_REG PIOC_IFER; // Input Filter Enable Register\r
+ AT91_REG PIOC_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIOC_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved33[1]; // \r
+ AT91_REG PIOC_SODR; // Set Output Data Register\r
+ AT91_REG PIOC_CODR; // Clear Output Data Register\r
+ AT91_REG PIOC_ODSR; // Output Data Status Register\r
+ AT91_REG PIOC_PDSR; // Pin Data Status Register\r
+ AT91_REG PIOC_IER; // Interrupt Enable Register\r
+ AT91_REG PIOC_IDR; // Interrupt Disable Register\r
+ AT91_REG PIOC_IMR; // Interrupt Mask Register\r
+ AT91_REG PIOC_ISR; // Interrupt Status Register\r
+ AT91_REG PIOC_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIOC_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIOC_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved34[1]; // \r
+ AT91_REG PIOC_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIOC_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIOC_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved35[1]; // \r
+ AT91_REG PIOC_ASR; // Select A Register\r
+ AT91_REG PIOC_BSR; // Select B Register\r
+ AT91_REG PIOC_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved36[9]; // \r
+ AT91_REG PIOC_OWER; // Output Write Enable Register\r
+ AT91_REG PIOC_OWDR; // Output Write Disable Register\r
+ AT91_REG PIOC_OWSR; // Output Write Status Register\r
+ AT91_REG Reserved37[85]; // \r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved38[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved39[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG PMC_PLLAR; // PLL A Register\r
+ AT91_REG PMC_PLLBR; // PLL B Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved40[3]; // \r
+ AT91_REG PMC_PCKR[8]; // Programmable Clock Register\r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved41[36]; // \r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+ AT91_REG Reserved42[1]; // \r
+ AT91_REG SHDWC_SHCR; // Shut Down Control Register\r
+ AT91_REG SHDWC_SHMR; // Shut Down Mode Register\r
+ AT91_REG SHDWC_SHSR; // Shut Down Status Register\r
+ AT91_REG Reserved43[1]; // \r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+ AT91_REG Reserved44[1]; // \r
+ AT91_REG SYS_GPBR[4]; // General Purpose Register\r
+} AT91S_SYS, *AT91PS_SYS;\r
+#else\r
+#define SYS_GPBR (AT91_CAST(AT91_REG *) 0x00003D50) // (SYS_GPBR) General Purpose Register\r
+\r
+#endif\r
+// -------- GPBR : (SYS Offset: 0x3d50) GPBR General Purpose Register -------- \r
+#define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR External Bus Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_EBI {\r
+ AT91_REG EBI_DUMMY; // Dummy register - Do not use\r
+} AT91S_EBI, *AT91PS_EBI;\r
+#else\r
+#define EBI_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI_DUMMY) Dummy register - Do not use\r
+\r
+#endif\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Error Correction Code controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_ECC {\r
+ AT91_REG ECC_CR; // ECC reset register\r
+ AT91_REG ECC_MR; // ECC Page size register\r
+ AT91_REG ECC_SR; // ECC Status register\r
+ AT91_REG ECC_PR; // ECC Parity register\r
+ AT91_REG ECC_NPR; // ECC Parity N register\r
+ AT91_REG Reserved0[58]; // \r
+ AT91_REG ECC_VR; // ECC Version register\r
+} AT91S_ECC, *AT91PS_ECC;\r
+#else\r
+#define ECC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ECC_CR) ECC reset register\r
+#define ECC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ECC_MR) ECC Page size register\r
+#define ECC_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ECC_SR) ECC Status register\r
+#define ECC_PR (AT91_CAST(AT91_REG *) 0x0000000C) // (ECC_PR) ECC Parity register\r
+#define ECC_NPR (AT91_CAST(AT91_REG *) 0x00000010) // (ECC_NPR) ECC Parity N register\r
+#define ECC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (ECC_VR) ECC Version register\r
+\r
+#endif\r
+// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register -------- \r
+#define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity\r
+// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register -------- \r
+#define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size\r
+// -------- ECC_SR : (ECC Offset: 0x8) ECC status register -------- \r
+#define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error\r
+#define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error\r
+#define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR\r
+// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register -------- \r
+#define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error\r
+#define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit\r
+// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register -------- \r
+#define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N \r
+// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register -------- \r
+#define AT91C_ECC_VR (0xF << 0) // (ECC) ECC version register\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR SDRAM Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SDRAMC {\r
+ AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register\r
+ AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register\r
+ AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register\r
+ AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register\r
+ AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register\r
+ AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register\r
+ AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register\r
+ AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register\r
+ AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register\r
+ AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register\r
+} AT91S_SDRAMC, *AT91PS_SDRAMC;\r
+#else\r
+#define SDRAMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register\r
+#define SDRAMC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register\r
+#define SDRAMC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register\r
+#define SDRAMC_HSR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register\r
+#define SDRAMC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register\r
+#define SDRAMC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register\r
+#define SDRAMC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register\r
+#define SDRAMC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register\r
+#define SDRAMC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register\r
+#define SDRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register\r
+\r
+#endif\r
+// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register -------- \r
+#define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode\r
+#define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode\r
+#define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access\r
+#define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access\r
+#define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access\r
+#define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh\r
+#define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register\r
+#define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode\r
+// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register -------- \r
+#define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter\r
+// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register -------- \r
+#define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits\r
+#define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits\r
+#define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits\r
+#define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits\r
+#define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits\r
+#define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits\r
+#define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits\r
+#define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits\r
+#define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits\r
+#define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks\r
+#define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks\r
+#define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks\r
+#define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency\r
+#define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles\r
+#define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles\r
+#define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width\r
+#define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus\r
+#define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus\r
+#define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles\r
+#define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15\r
+#define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles\r
+#define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15\r
+#define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles\r
+#define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15\r
+#define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles\r
+#define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15\r
+#define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles\r
+#define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15\r
+#define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles\r
+#define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0\r
+#define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1\r
+#define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2\r
+#define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3\r
+#define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4\r
+#define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5\r
+#define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6\r
+#define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7\r
+#define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8\r
+#define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9\r
+#define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10\r
+#define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11\r
+#define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12\r
+#define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13\r
+#define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14\r
+#define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15\r
+// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register -------- \r
+#define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit\r
+#define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle\r
+#define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle\r
+// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register -------- \r
+#define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations\r
+#define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features\r
+#define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH\r
+#define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN\r
+#define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN\r
+#define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)\r
+#define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)\r
+#define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)\r
+#define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled\r
+#define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately\r
+#define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer\r
+#define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer\r
+// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- \r
+#define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status\r
+// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- \r
+// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- \r
+// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- \r
+// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register -------- \r
+#define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type\r
+#define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode\r
+#define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Static Memory Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SMC {\r
+ AT91_REG SMC_SETUP0; // Setup Register for CS 0\r
+ AT91_REG SMC_PULSE0; // Pulse Register for CS 0\r
+ AT91_REG SMC_CYCLE0; // Cycle Register for CS 0\r
+ AT91_REG SMC_CTRL0; // Control Register for CS 0\r
+ AT91_REG SMC_SETUP1; // Setup Register for CS 1\r
+ AT91_REG SMC_PULSE1; // Pulse Register for CS 1\r
+ AT91_REG SMC_CYCLE1; // Cycle Register for CS 1\r
+ AT91_REG SMC_CTRL1; // Control Register for CS 1\r
+ AT91_REG SMC_SETUP2; // Setup Register for CS 2\r
+ AT91_REG SMC_PULSE2; // Pulse Register for CS 2\r
+ AT91_REG SMC_CYCLE2; // Cycle Register for CS 2\r
+ AT91_REG SMC_CTRL2; // Control Register for CS 2\r
+ AT91_REG SMC_SETUP3; // Setup Register for CS 3\r
+ AT91_REG SMC_PULSE3; // Pulse Register for CS 3\r
+ AT91_REG SMC_CYCLE3; // Cycle Register for CS 3\r
+ AT91_REG SMC_CTRL3; // Control Register for CS 3\r
+ AT91_REG SMC_SETUP4; // Setup Register for CS 4\r
+ AT91_REG SMC_PULSE4; // Pulse Register for CS 4\r
+ AT91_REG SMC_CYCLE4; // Cycle Register for CS 4\r
+ AT91_REG SMC_CTRL4; // Control Register for CS 4\r
+ AT91_REG SMC_SETUP5; // Setup Register for CS 5\r
+ AT91_REG SMC_PULSE5; // Pulse Register for CS 5\r
+ AT91_REG SMC_CYCLE5; // Cycle Register for CS 5\r
+ AT91_REG SMC_CTRL5; // Control Register for CS 5\r
+ AT91_REG SMC_SETUP6; // Setup Register for CS 6\r
+ AT91_REG SMC_PULSE6; // Pulse Register for CS 6\r
+ AT91_REG SMC_CYCLE6; // Cycle Register for CS 6\r
+ AT91_REG SMC_CTRL6; // Control Register for CS 6\r
+ AT91_REG SMC_SETUP7; // Setup Register for CS 7\r
+ AT91_REG SMC_PULSE7; // Pulse Register for CS 7\r
+ AT91_REG SMC_CYCLE7; // Cycle Register for CS 7\r
+ AT91_REG SMC_CTRL7; // Control Register for CS 7\r
+} AT91S_SMC, *AT91PS_SMC;\r
+#else\r
+#define SETUP0 (AT91_CAST(AT91_REG *) 0x00000000) // (SETUP0) Setup Register for CS 0\r
+#define PULSE0 (AT91_CAST(AT91_REG *) 0x00000004) // (PULSE0) Pulse Register for CS 0\r
+#define CYCLE0 (AT91_CAST(AT91_REG *) 0x00000008) // (CYCLE0) Cycle Register for CS 0\r
+#define CTRL0 (AT91_CAST(AT91_REG *) 0x0000000C) // (CTRL0) Control Register for CS 0\r
+#define SETUP1 (AT91_CAST(AT91_REG *) 0x00000010) // (SETUP1) Setup Register for CS 1\r
+#define PULSE1 (AT91_CAST(AT91_REG *) 0x00000014) // (PULSE1) Pulse Register for CS 1\r
+#define CYCLE1 (AT91_CAST(AT91_REG *) 0x00000018) // (CYCLE1) Cycle Register for CS 1\r
+#define CTRL1 (AT91_CAST(AT91_REG *) 0x0000001C) // (CTRL1) Control Register for CS 1\r
+#define SETUP2 (AT91_CAST(AT91_REG *) 0x00000020) // (SETUP2) Setup Register for CS 2\r
+#define PULSE2 (AT91_CAST(AT91_REG *) 0x00000024) // (PULSE2) Pulse Register for CS 2\r
+#define CYCLE2 (AT91_CAST(AT91_REG *) 0x00000028) // (CYCLE2) Cycle Register for CS 2\r
+#define CTRL2 (AT91_CAST(AT91_REG *) 0x0000002C) // (CTRL2) Control Register for CS 2\r
+#define SETUP3 (AT91_CAST(AT91_REG *) 0x00000030) // (SETUP3) Setup Register for CS 3\r
+#define PULSE3 (AT91_CAST(AT91_REG *) 0x00000034) // (PULSE3) Pulse Register for CS 3\r
+#define CYCLE3 (AT91_CAST(AT91_REG *) 0x00000038) // (CYCLE3) Cycle Register for CS 3\r
+#define CTRL3 (AT91_CAST(AT91_REG *) 0x0000003C) // (CTRL3) Control Register for CS 3\r
+#define SETUP4 (AT91_CAST(AT91_REG *) 0x00000040) // (SETUP4) Setup Register for CS 4\r
+#define PULSE4 (AT91_CAST(AT91_REG *) 0x00000044) // (PULSE4) Pulse Register for CS 4\r
+#define CYCLE4 (AT91_CAST(AT91_REG *) 0x00000048) // (CYCLE4) Cycle Register for CS 4\r
+#define CTRL4 (AT91_CAST(AT91_REG *) 0x0000004C) // (CTRL4) Control Register for CS 4\r
+#define SETUP5 (AT91_CAST(AT91_REG *) 0x00000050) // (SETUP5) Setup Register for CS 5\r
+#define PULSE5 (AT91_CAST(AT91_REG *) 0x00000054) // (PULSE5) Pulse Register for CS 5\r
+#define CYCLE5 (AT91_CAST(AT91_REG *) 0x00000058) // (CYCLE5) Cycle Register for CS 5\r
+#define CTRL5 (AT91_CAST(AT91_REG *) 0x0000005C) // (CTRL5) Control Register for CS 5\r
+#define SETUP6 (AT91_CAST(AT91_REG *) 0x00000060) // (SETUP6) Setup Register for CS 6\r
+#define PULSE6 (AT91_CAST(AT91_REG *) 0x00000064) // (PULSE6) Pulse Register for CS 6\r
+#define CYCLE6 (AT91_CAST(AT91_REG *) 0x00000068) // (CYCLE6) Cycle Register for CS 6\r
+#define CTRL6 (AT91_CAST(AT91_REG *) 0x0000006C) // (CTRL6) Control Register for CS 6\r
+#define SETUP7 (AT91_CAST(AT91_REG *) 0x00000070) // (SETUP7) Setup Register for CS 7\r
+#define PULSE7 (AT91_CAST(AT91_REG *) 0x00000074) // (PULSE7) Pulse Register for CS 7\r
+#define CYCLE7 (AT91_CAST(AT91_REG *) 0x00000078) // (CYCLE7) Cycle Register for CS 7\r
+#define CTRL7 (AT91_CAST(AT91_REG *) 0x0000007C) // (CTRL7) Control Register for CS 7\r
+\r
+#endif\r
+// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x -------- \r
+#define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length\r
+#define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access\r
+#define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length\r
+#define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access\r
+// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x -------- \r
+#define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length\r
+#define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access\r
+#define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length\r
+#define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access\r
+// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x -------- \r
+#define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length\r
+#define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length\r
+// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x -------- \r
+#define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode\r
+#define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode\r
+#define AT91C_SMC_NWAITM (0x3 << 4) // (SMC) NWAIT Mode\r
+#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 4) // (SMC) External NWAIT disabled.\r
+#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 4) // (SMC) External NWAIT enabled in frozen mode.\r
+#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 4) // (SMC) External NWAIT enabled in ready mode.\r
+#define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type\r
+#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.\r
+#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.\r
+#define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width\r
+#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits.\r
+#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits.\r
+#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.\r
+#define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time.\r
+#define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled.\r
+#define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled.\r
+#define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size\r
+#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes.\r
+#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes.\r
+#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes.\r
+#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.\r
+// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- \r
+// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- \r
+// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- \r
+// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- \r
+// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR AHB Matrix Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_MATRIX {\r
+ AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k) \r
+ AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom) \r
+ AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs) \r
+ AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi)\r
+ AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge) \r
+ AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox) \r
+ AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k) \r
+ AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog) \r
+ AT91_REG Reserved0[8]; // \r
+ AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k) \r
+ AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom) \r
+ AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs) \r
+ AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi)\r
+ AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge) \r
+ AT91_REG Reserved1[11]; // \r
+ AT91_REG MATRIX_PRAS0; // PRAS0 (ram0) \r
+ AT91_REG MATRIX_PRBS0; // PRBS0 (ram0) \r
+ AT91_REG MATRIX_PRAS1; // PRAS1 (ram1) \r
+ AT91_REG MATRIX_PRBS1; // PRBS1 (ram1) \r
+ AT91_REG MATRIX_PRAS2; // PRAS2 (ram2) \r
+ AT91_REG MATRIX_PRBS2; // PRBS2 (ram2) \r
+ AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs\r
+ AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs\r
+ AT91_REG MATRIX_PRAS4; // PRAS4 : ebi\r
+ AT91_REG MATRIX_PRBS4; // PRBS4 : ebi\r
+ AT91_REG Reserved2[22]; // \r
+ AT91_REG MATRIX_MRCR; // Master Remp Control Register \r
+ AT91_REG Reserved3[6]; // \r
+ AT91_REG MATRIX_EBI; // Slave 3 (ebi) Special Function Register\r
+ AT91_REG Reserved4[3]; // \r
+ AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register\r
+ AT91_REG Reserved5[51]; // \r
+ AT91_REG MATRIX_VERSION; // Version Register\r
+} AT91S_MATRIX, *AT91PS_MATRIX;\r
+#else\r
+#define MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG0) Master Configuration Register 0 (ram96k) \r
+#define MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_MCFG1) Master Configuration Register 1 (rom) \r
+#define MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_MCFG2) Master Configuration Register 2 (hperiphs) \r
+#define MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_MCFG3) Master Configuration Register 3 (ebi)\r
+#define MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_MCFG4) Master Configuration Register 4 (bridge) \r
+#define MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_MCFG5) Master Configuration Register 5 (mailbox) \r
+#define MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x00000018) // (MATRIX_MCFG6) Master Configuration Register 6 (ram16k) \r
+#define MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x0000001C) // (MATRIX_MCFG7) Master Configuration Register 7 (teak_prog) \r
+#define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG0) Slave Configuration Register 0 (ram96k) \r
+#define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_SCFG1) Slave Configuration Register 1 (rom) \r
+#define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x00000048) // (MATRIX_SCFG2) Slave Configuration Register 2 (hperiphs) \r
+#define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x0000004C) // (MATRIX_SCFG3) Slave Configuration Register 3 (ebi)\r
+#define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000050) // (MATRIX_SCFG4) Slave Configuration Register 4 (bridge) \r
+#define MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0x00000080) // (MATRIX_PRAS0) PRAS0 (ram0) \r
+#define MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0x00000084) // (MATRIX_PRBS0) PRBS0 (ram0) \r
+#define MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0x00000088) // (MATRIX_PRAS1) PRAS1 (ram1) \r
+#define MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0x0000008C) // (MATRIX_PRBS1) PRBS1 (ram1) \r
+#define MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0x00000090) // (MATRIX_PRAS2) PRAS2 (ram2) \r
+#define MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0x00000094) // (MATRIX_PRBS2) PRBS2 (ram2) \r
+#define MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0x00000098) // (MATRIX_PRAS3) PRAS3 : usb_dev_hs\r
+#define MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0x0000009C) // (MATRIX_PRBS3) PRBS3 : usb_dev_hs\r
+#define MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0x000000A0) // (MATRIX_PRAS4) PRAS4 : ebi\r
+#define MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0x000000A4) // (MATRIX_PRBS4) PRBS4 : ebi\r
+#define MATRIX_MRCR (AT91_CAST(AT91_REG *) 0x00000100) // (MATRIX_MRCR) Master Remp Control Register \r
+#define MATRIX_EBI (AT91_CAST(AT91_REG *) 0x0000011C) // (MATRIX_EBI) Slave 3 (ebi) Special Function Register\r
+#define MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0x0000012C) // (MATRIX_TEAKCFG) Slave 7 (teak_prog) Special Function Register\r
+#define MATRIX_VERSION (AT91_CAST(AT91_REG *) 0x000001FC) // (MATRIX_VERSION) Version Register\r
+\r
+#endif\r
+// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- \r
+#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst\r
+#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type\r
+#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.\r
+#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.\r
+#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master\r
+// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master\r
+// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master\r
+// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR3_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master\r
+// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master\r
+#define AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master\r
+// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register -------- \r
+#define AT91C_MATRIX_M0PR (0x3 << 0) // (MATRIX) ARM926EJ-S Instruction priority\r
+#define AT91C_MATRIX_M1PR (0x3 << 4) // (MATRIX) ARM926EJ-S Data priority\r
+#define AT91C_MATRIX_M2PR (0x3 << 8) // (MATRIX) PDC priority\r
+#define AT91C_MATRIX_M3PR (0x3 << 12) // (MATRIX) LCDC priority\r
+#define AT91C_MATRIX_M4PR (0x3 << 16) // (MATRIX) 2DGC priority\r
+#define AT91C_MATRIX_M5PR (0x3 << 20) // (MATRIX) ISI priority\r
+#define AT91C_MATRIX_M6PR (0x3 << 24) // (MATRIX) DMA priority\r
+#define AT91C_MATRIX_M7PR (0x3 << 28) // (MATRIX) EMAC priority\r
+// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register -------- \r
+#define AT91C_MATRIX_M8PR (0x3 << 0) // (MATRIX) USB priority\r
+// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register -------- \r
+// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register -------- \r
+// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register -------- \r
+// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register -------- \r
+// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register -------- \r
+// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register -------- \r
+// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register -------- \r
+// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register -------- \r
+// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register -------- \r
+#define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master\r
+#define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command for ARM926EJ-S Data Master\r
+// -------- MATRIX_EBI : (MATRIX Offset: 0x11c) EBI (Slave 3) Special Function Register -------- \r
+#define AT91C_MATRIX_CS1A (0x1 << 1) // (MATRIX) Chip Select 1 Assignment\r
+#define AT91C_MATRIX_CS1A_SMC (0x0 << 1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller.\r
+#define AT91C_MATRIX_CS1A_SDRAMC (0x1 << 1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller.\r
+#define AT91C_MATRIX_CS3A (0x1 << 3) // (MATRIX) Chip Select 3 Assignment\r
+#define AT91C_MATRIX_CS3A_SMC (0x0 << 3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.\r
+#define AT91C_MATRIX_CS3A_SM (0x1 << 3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.\r
+#define AT91C_MATRIX_CS4A (0x1 << 4) // (MATRIX) Chip Select 4 Assignment\r
+#define AT91C_MATRIX_CS4A_SMC (0x0 << 4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.\r
+#define AT91C_MATRIX_CS4A_CF (0x1 << 4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.\r
+#define AT91C_MATRIX_CS5A (0x1 << 5) // (MATRIX) Chip Select 5 Assignment\r
+#define AT91C_MATRIX_CS5A_SMC (0x0 << 5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC\r
+#define AT91C_MATRIX_CS5A_CF (0x1 << 5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.\r
+#define AT91C_MATRIX_DBPUC (0x1 << 8) // (MATRIX) Data Bus Pull-up Configuration\r
+// -------- MATRIX_TEAKCFG : (MATRIX Offset: 0x12c) Slave 7 Special Function Register -------- \r
+#define AT91C_TEAK_PROGRAM_ACCESS (0x1 << 0) // (MATRIX) TEAK program memory access from AHB\r
+#define AT91C_TEAK_PROGRAM_ACCESS_DISABLED (0x0) // (MATRIX) TEAK program access disabled\r
+#define AT91C_TEAK_PROGRAM_ACCESS_ENABLED (0x1) // (MATRIX) TEAK program access enabled\r
+#define AT91C_TEAK_BOOT (0x1 << 1) // (MATRIX) TEAK program start from boot routine\r
+#define AT91C_TEAK_BOOT_DISABLED (0x0 << 1) // (MATRIX) TEAK program starts from boot routine disabled\r
+#define AT91C_TEAK_BOOT_ENABLED (0x1 << 1) // (MATRIX) TEAK program starts from boot routine enabled\r
+#define AT91C_TEAK_NRESET (0x1 << 2) // (MATRIX) active low TEAK reset\r
+#define AT91C_TEAK_NRESET_ENABLED (0x0 << 2) // (MATRIX) active low TEAK reset enabled\r
+#define AT91C_TEAK_NRESET_DISABLED (0x1 << 2) // (MATRIX) active low TEAK reset disabled\r
+#define AT91C_TEAK_LVECTORP (0x3FFFF << 14) // (MATRIX) boot routine start address\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Chip Configuration Registers\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_CCFG {\r
+ AT91_REG Reserved0[3]; // \r
+ AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register\r
+ AT91_REG Reserved1[55]; // \r
+ AT91_REG CCFG_MATRIXVERSION; // Version Register\r
+} AT91S_CCFG, *AT91PS_CCFG;\r
+#else\r
+#define CCFG_EBICSA (AT91_CAST(AT91_REG *) 0x0000000C) // (CCFG_EBICSA) EBI Chip Select Assignement Register\r
+#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0x000000EC) // (CCFG_MATRIXVERSION) Version Register\r
+\r
+#endif\r
+// -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register -------- \r
+#define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment\r
+#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.\r
+#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller.\r
+#define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment\r
+#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.\r
+#define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.\r
+#define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment\r
+#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.\r
+#define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.\r
+#define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment\r
+#define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC\r
+#define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.\r
+#define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration\r
+#define AT91C_EBI_SUPPLY (0x1 << 16) // (CCFG) EBI supply selection\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PDC {\r
+ AT91_REG PDC_RPR; // Receive Pointer Register\r
+ AT91_REG PDC_RCR; // Receive Counter Register\r
+ AT91_REG PDC_TPR; // Transmit Pointer Register\r
+ AT91_REG PDC_TCR; // Transmit Counter Register\r
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG PDC_RNCR; // Receive Next Counter Register\r
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register\r
+} AT91S_PDC, *AT91PS_PDC;\r
+#else\r
+#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register\r
+#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register\r
+#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register\r
+#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register\r
+#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register\r
+#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register\r
+#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register\r
+#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register\r
+#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register\r
+#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register\r
+\r
+#endif\r
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable\r
+#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable\r
+#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable\r
+#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable\r
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Debug Unit\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_DBGU {\r
+ AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_MR; // Mode Register\r
+ AT91_REG DBGU_IER; // Interrupt Enable Register\r
+ AT91_REG DBGU_IDR; // Interrupt Disable Register\r
+ AT91_REG DBGU_IMR; // Interrupt Mask Register\r
+ AT91_REG DBGU_CSR; // Channel Status Register\r
+ AT91_REG DBGU_RHR; // Receiver Holding Register\r
+ AT91_REG DBGU_THR; // Transmitter Holding Register\r
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
+ AT91_REG Reserved0[7]; // \r
+ AT91_REG DBGU_CIDR; // Chip ID Register\r
+ AT91_REG DBGU_EXID; // Chip ID Extension Register\r
+ AT91_REG DBGU_FNTR; // Force NTRST Register\r
+ AT91_REG Reserved1[45]; // \r
+ AT91_REG DBGU_RPR; // Receive Pointer Register\r
+ AT91_REG DBGU_RCR; // Receive Counter Register\r
+ AT91_REG DBGU_TPR; // Transmit Pointer Register\r
+ AT91_REG DBGU_TCR; // Transmit Counter Register\r
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
+} AT91S_DBGU, *AT91PS_DBGU;\r
+#else\r
+#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register\r
+#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register\r
+#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register\r
+#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register\r
+#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register\r
+#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register\r
+#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register\r
+#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register\r
+#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register\r
+#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register\r
+#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register\r
+#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register\r
+\r
+#endif\r
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver\r
+#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter\r
+#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable\r
+#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable\r
+#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable\r
+#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable\r
+#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits\r
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type\r
+#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity\r
+#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity\r
+#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)\r
+#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)\r
+#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity\r
+#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode\r
+#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode\r
+#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt\r
+#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt\r
+#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt\r
+#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt\r
+#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt\r
+#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt\r
+#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt\r
+#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt\r
+#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt\r
+#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt\r
+#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt\r
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_AIC {\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SVR[32]; // Source Vector Register\r
+ AT91_REG AIC_IVR; // IRQ Vector Register\r
+ AT91_REG AIC_FVR; // FIQ Vector Register\r
+ AT91_REG AIC_ISR; // Interrupt Status Register\r
+ AT91_REG AIC_IPR; // Interrupt Pending Register\r
+ AT91_REG AIC_IMR; // Interrupt Mask Register\r
+ AT91_REG AIC_CISR; // Core Interrupt Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
+ AT91_REG AIC_SPU; // Spurious Vector Register\r
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
+} AT91S_AIC, *AT91PS_AIC;\r
+#else\r
+#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register\r
+#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register\r
+#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register\r
+#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register\r
+#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register\r
+#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register\r
+#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register\r
+#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register\r
+#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register\r
+#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register\r
+#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register\r
+#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register\r
+#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register\r
+#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register\r
+#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)\r
+#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register\r
+#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register\r
+#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register\r
+\r
+#endif\r
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \r
+#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level\r
+#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level\r
+#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level\r
+#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type\r
+#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive\r
+#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered\r
+#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive\r
+#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered\r
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \r
+#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status\r
+#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status\r
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \r
+#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode\r
+#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PIO {\r
+ AT91_REG PIO_PER; // PIO Enable Register\r
+ AT91_REG PIO_PDR; // PIO Disable Register\r
+ AT91_REG PIO_PSR; // PIO Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PIO_OER; // Output Enable Register\r
+ AT91_REG PIO_ODR; // Output Disable Registerr\r
+ AT91_REG PIO_OSR; // Output Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PIO_IFER; // Input Filter Enable Register\r
+ AT91_REG PIO_IFDR; // Input Filter Disable Register\r
+ AT91_REG PIO_IFSR; // Input Filter Status Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG PIO_SODR; // Set Output Data Register\r
+ AT91_REG PIO_CODR; // Clear Output Data Register\r
+ AT91_REG PIO_ODSR; // Output Data Status Register\r
+ AT91_REG PIO_PDSR; // Pin Data Status Register\r
+ AT91_REG PIO_IER; // Interrupt Enable Register\r
+ AT91_REG PIO_IDR; // Interrupt Disable Register\r
+ AT91_REG PIO_IMR; // Interrupt Mask Register\r
+ AT91_REG PIO_ISR; // Interrupt Status Register\r
+ AT91_REG PIO_MDER; // Multi-driver Enable Register\r
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register\r
+ AT91_REG PIO_MDSR; // Multi-driver Status Register\r
+ AT91_REG Reserved3[1]; // \r
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register\r
+ AT91_REG PIO_PPUER; // Pull-up Enable Register\r
+ AT91_REG PIO_PPUSR; // Pull-up Status Register\r
+ AT91_REG Reserved4[1]; // \r
+ AT91_REG PIO_ASR; // Select A Register\r
+ AT91_REG PIO_BSR; // Select B Register\r
+ AT91_REG PIO_ABSR; // AB Select Status Register\r
+ AT91_REG Reserved5[9]; // \r
+ AT91_REG PIO_OWER; // Output Write Enable Register\r
+ AT91_REG PIO_OWDR; // Output Write Disable Register\r
+ AT91_REG PIO_OWSR; // Output Write Status Register\r
+} AT91S_PIO, *AT91PS_PIO;\r
+#else\r
+#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register\r
+#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register\r
+#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register\r
+#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register\r
+#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr\r
+#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register\r
+#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register\r
+#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register\r
+#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register\r
+#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register\r
+#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register\r
+#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register\r
+#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register\r
+#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register\r
+#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register\r
+#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register\r
+#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register\r
+#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register\r
+#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register\r
+#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register\r
+#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register\r
+#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register\r
+#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register\r
+#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register\r
+#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register\r
+#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register\r
+#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register\r
+#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register\r
+#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register\r
+\r
+#endif\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Embedded Flash Controller 2.0\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_EFC {\r
+ AT91_REG EFC_FMR; // EFC Flash Mode Register\r
+ AT91_REG EFC_FCR; // EFC Flash Command Register\r
+ AT91_REG EFC_FSR; // EFC Flash Status Register\r
+ AT91_REG EFC_FRR; // EFC Flash Result Register\r
+ AT91_REG EFC_FVR; // EFC Flash Version Register\r
+} AT91S_EFC, *AT91PS_EFC;\r
+#else\r
+#define EFC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (EFC_FMR) EFC Flash Mode Register\r
+#define EFC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (EFC_FCR) EFC Flash Command Register\r
+#define EFC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (EFC_FSR) EFC Flash Status Register\r
+#define EFC_FRR (AT91_CAST(AT91_REG *) 0x0000000C) // (EFC_FRR) EFC Flash Result Register\r
+#define EFC_FVR (AT91_CAST(AT91_REG *) 0x00000010) // (EFC_FVR) EFC Flash Version Register\r
+\r
+#endif\r
+// -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register -------- \r
+#define AT91C_EFC_FRDY (0x1 << 0) // (EFC) Ready Interrupt Enable\r
+#define AT91C_EFC_FWS (0xF << 8) // (EFC) Flash Wait State.\r
+#define AT91C_EFC_FWS_0WS (0x0 << 8) // (EFC) 0 Wait State\r
+#define AT91C_EFC_FWS_1WS (0x1 << 8) // (EFC) 1 Wait State\r
+#define AT91C_EFC_FWS_2WS (0x2 << 8) // (EFC) 2 Wait States\r
+#define AT91C_EFC_FWS_3WS (0x3 << 8) // (EFC) 3 Wait States\r
+// -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register -------- \r
+#define AT91C_EFC_FCMD (0xFF << 0) // (EFC) Flash Command\r
+#define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor\r
+#define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page\r
+#define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock\r
+#define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page\r
+#define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock\r
+#define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All\r
+#define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase Plane\r
+#define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase Pages\r
+#define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit\r
+#define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit\r
+#define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit\r
+#define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit\r
+#define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit\r
+#define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit\r
+#define AT91C_EFC_FARG (0xFFFF << 8) // (EFC) Flash Command Argument\r
+#define AT91C_EFC_FKEY (0xFF << 24) // (EFC) Flash Writing Protection Key\r
+// -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register -------- \r
+#define AT91C_EFC_FRDY_S (0x1 << 0) // (EFC) Flash Ready Status\r
+#define AT91C_EFC_FCMDE (0x1 << 1) // (EFC) Flash Command Error Status\r
+#define AT91C_EFC_LOCKE (0x1 << 2) // (EFC) Flash Lock Error Status\r
+// -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register -------- \r
+#define AT91C_EFC_FVALUE (0x0 << 0) // (EFC) Flash Result Value\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_CKGR {\r
+ AT91_REG CKGR_MOR; // Main Oscillator Register\r
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register\r
+ AT91_REG CKGR_PLLAR; // PLL A Register\r
+ AT91_REG CKGR_PLLBR; // PLL B Register\r
+} AT91S_CKGR, *AT91PS_CKGR;\r
+#else\r
+#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register\r
+#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register\r
+#define CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x00000008) // (CKGR_PLLAR) PLL A Register\r
+#define CKGR_PLLBR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLBR) PLL B Register\r
+\r
+#endif\r
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \r
+#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable\r
+#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass\r
+#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time\r
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \r
+#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency\r
+#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready\r
+// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- \r
+#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected\r
+#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0\r
+#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed\r
+#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter\r
+#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range\r
+#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet\r
+#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet\r
+#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet\r
+#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet\r
+#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier\r
+#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR) \r
+// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- \r
+#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected\r
+#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0\r
+#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed\r
+#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter\r
+#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range\r
+#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet\r
+#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet\r
+#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet\r
+#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet\r
+#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier\r
+#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks\r
+#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output\r
+#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2\r
+#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Power Management Controler\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PMC {\r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCDR; // System Clock Disable Register\r
+ AT91_REG PMC_SCSR; // System Clock Status Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG PMC_MOR; // Main Oscillator Register\r
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
+ AT91_REG PMC_PLLAR; // PLL A Register\r
+ AT91_REG PMC_PLLBR; // PLL B Register\r
+ AT91_REG PMC_MCKR; // Master Clock Register\r
+ AT91_REG Reserved2[3]; // \r
+ AT91_REG PMC_PCKR[8]; // Programmable Clock Register\r
+ AT91_REG PMC_IER; // Interrupt Enable Register\r
+ AT91_REG PMC_IDR; // Interrupt Disable Register\r
+ AT91_REG PMC_SR; // Status Register\r
+ AT91_REG PMC_IMR; // Interrupt Mask Register\r
+} AT91S_PMC, *AT91PS_PMC;\r
+#else\r
+#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register\r
+#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register\r
+#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register\r
+#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register\r
+#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register\r
+#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register\r
+#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register\r
+#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register\r
+#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register\r
+#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register\r
+#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register\r
+#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register\r
+\r
+#endif\r
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock\r
+#define AT91C_PMC_OTG (0x1 << 5) // (PMC) USB OTG Clock\r
+#define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock\r
+#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock\r
+#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output\r
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- \r
+// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- \r
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection\r
+#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected\r
+#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected\r
+#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected\r
+#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected\r
+#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler\r
+#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock\r
+#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2\r
+#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4\r
+#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8\r
+#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16\r
+#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32\r
+#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64\r
+#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division\r
+#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same\r
+#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock\r
+#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is four times faster than the master clock\r
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask\r
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_RSTC {\r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RSR; // Reset Status Register\r
+ AT91_REG RSTC_RMR; // Reset Mode Register\r
+} AT91S_RSTC, *AT91PS_RSTC;\r
+#else\r
+#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register\r
+#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register\r
+#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register\r
+\r
+#endif\r
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset\r
+#define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset\r
+#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset\r
+#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset\r
+#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password\r
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status\r
+#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type\r
+#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.\r
+#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.\r
+#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.\r
+#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.\r
+#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level\r
+#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable\r
+#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Shut Down Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SHDWC {\r
+ AT91_REG SHDWC_SHCR; // Shut Down Control Register\r
+ AT91_REG SHDWC_SHMR; // Shut Down Mode Register\r
+ AT91_REG SHDWC_SHSR; // Shut Down Status Register\r
+} AT91S_SHDWC, *AT91PS_SHDWC;\r
+#else\r
+#define SHDWC_SHCR (AT91_CAST(AT91_REG *) 0x00000000) // (SHDWC_SHCR) Shut Down Control Register\r
+#define SHDWC_SHMR (AT91_CAST(AT91_REG *) 0x00000004) // (SHDWC_SHMR) Shut Down Mode Register\r
+#define SHDWC_SHSR (AT91_CAST(AT91_REG *) 0x00000008) // (SHDWC_SHSR) Shut Down Status Register\r
+\r
+#endif\r
+// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- \r
+#define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset\r
+#define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password\r
+// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- \r
+#define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection\r
+#define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input.\r
+#define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level.\r
+#define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level.\r
+#define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change.\r
+#define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0\r
+#define AT91C_SHDWC_WKMODE1 (0x3 << 8) // (SHDWC) Wake Up 1 Mode Selection\r
+#define AT91C_SHDWC_WKMODE1_NONE (0x0 << 8) // (SHDWC) None. No detection is performed on the wake up input.\r
+#define AT91C_SHDWC_WKMODE1_HIGH (0x1 << 8) // (SHDWC) High Level.\r
+#define AT91C_SHDWC_WKMODE1_LOW (0x2 << 8) // (SHDWC) Low Level.\r
+#define AT91C_SHDWC_WKMODE1_ANYLEVEL (0x3 << 8) // (SHDWC) Any level change.\r
+#define AT91C_SHDWC_CPTWK1 (0xF << 12) // (SHDWC) Counter On Wake Up 1\r
+#define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable\r
+#define AT91C_SHDWC_RTCWKEN (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable\r
+// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- \r
+#define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status\r
+#define AT91C_SHDWC_WAKEUP1 (0x1 << 1) // (SHDWC) Wake Up 1 Status\r
+#define AT91C_SHDWC_FWKUP (0x1 << 2) // (SHDWC) Force Wake Up Status\r
+#define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up\r
+#define AT91C_SHDWC_RTCWK (0x1 << 17) // (SHDWC) Real Time Clock wake Up\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_RTTC {\r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
+ AT91_REG RTTC_RTVR; // Real-time Value Register\r
+ AT91_REG RTTC_RTSR; // Real-time Status Register\r
+} AT91S_RTTC, *AT91PS_RTTC;\r
+#else\r
+#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register\r
+#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register\r
+#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register\r
+#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register\r
+\r
+#endif\r
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
+#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
+#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
+#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart\r
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value\r
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value\r
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status\r
+#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PITC {\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PISR; // Period Interval Status Register\r
+ AT91_REG PITC_PIVR; // Period Interval Value Register\r
+ AT91_REG PITC_PIIR; // Period Interval Image Register\r
+} AT91S_PITC, *AT91PS_PITC;\r
+#else\r
+#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register\r
+#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register\r
+#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register\r
+#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register\r
+\r
+#endif\r
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- \r
+#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value\r
+#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
+#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable\r
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- \r
+#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status\r
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- \r
+#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value\r
+#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter\r
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_WDTC {\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
+ AT91_REG WDTC_WDSR; // Watchdog Status Register\r
+} AT91S_WDTC, *AT91PS_WDTC;\r
+#else\r
+#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register\r
+#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register\r
+#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register\r
+\r
+#endif\r
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart\r
+#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password\r
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
+#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable\r
+#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable\r
+#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value\r
+#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt\r
+#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt\r
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow\r
+#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_TC {\r
+ AT91_REG TC_CCR; // Channel Control Register\r
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG TC_CV; // Counter Value\r
+ AT91_REG TC_RA; // Register A\r
+ AT91_REG TC_RB; // Register B\r
+ AT91_REG TC_RC; // Register C\r
+ AT91_REG TC_SR; // Status Register\r
+ AT91_REG TC_IER; // Interrupt Enable Register\r
+ AT91_REG TC_IDR; // Interrupt Disable Register\r
+ AT91_REG TC_IMR; // Interrupt Mask Register\r
+} AT91S_TC, *AT91PS_TC;\r
+#else\r
+#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register\r
+#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value\r
+#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A\r
+#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B\r
+#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C\r
+#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register\r
+#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register\r
+#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register\r
+#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register\r
+\r
+#endif\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection\r
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
+#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0\r
+#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1\r
+#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2\r
+#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert\r
+#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection\r
+#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal\r
+#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock\r
+#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock\r
+#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading\r
+#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading\r
+#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection\r
+#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection\r
+#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None\r
+#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge\r
+#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge\r
+#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection\r
+#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
+#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection\r
+#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE (0x1 << 15) // (TC) \r
+#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none\r
+#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set\r
+#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear\r
+#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection\r
+#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None\r
+#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none\r
+#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set\r
+#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear\r
+#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection\r
+#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None\r
+#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA\r
+#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA\r
+#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none\r
+#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set\r
+#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear\r
+#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none\r
+#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set\r
+#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear\r
+#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none\r
+#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set\r
+#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear\r
+#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none\r
+#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set\r
+#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear\r
+#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none\r
+#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set\r
+#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear\r
+#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none\r
+#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set\r
+#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear\r
+#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading\r
+#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger\r
+#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_TCB {\r
+ AT91S_TC TCB_TC0; // TC Channel 0\r
+ AT91_REG Reserved0[4]; // \r
+ AT91S_TC TCB_TC1; // TC Channel 1\r
+ AT91_REG Reserved1[4]; // \r
+ AT91S_TC TCB_TC2; // TC Channel 2\r
+ AT91_REG Reserved2[4]; // \r
+ AT91_REG TCB_BCR; // TC Block Control Register\r
+ AT91_REG TCB_BMR; // TC Block Mode Register\r
+} AT91S_TCB, *AT91PS_TCB;\r
+#else\r
+#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register\r
+#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register\r
+\r
+#endif\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection\r
+#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0\r
+#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection\r
+#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1\r
+#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection\r
+#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2\r
+#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Multimedia Card Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_MCI {\r
+ AT91_REG MCI_CR; // MCI Control Register\r
+ AT91_REG MCI_MR; // MCI Mode Register\r
+ AT91_REG MCI_DTOR; // MCI Data Timeout Register\r
+ AT91_REG MCI_SDCR; // MCI SD Card Register\r
+ AT91_REG MCI_ARGR; // MCI Argument Register\r
+ AT91_REG MCI_CMDR; // MCI Command Register\r
+ AT91_REG MCI_BLKR; // MCI Block Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG MCI_RSPR[4]; // MCI Response Register\r
+ AT91_REG MCI_RDR; // MCI Receive Data Register\r
+ AT91_REG MCI_TDR; // MCI Transmit Data Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG MCI_SR; // MCI Status Register\r
+ AT91_REG MCI_IER; // MCI Interrupt Enable Register\r
+ AT91_REG MCI_IDR; // MCI Interrupt Disable Register\r
+ AT91_REG MCI_IMR; // MCI Interrupt Mask Register\r
+ AT91_REG Reserved2[43]; // \r
+ AT91_REG MCI_VR; // MCI Version Register\r
+ AT91_REG MCI_RPR; // Receive Pointer Register\r
+ AT91_REG MCI_RCR; // Receive Counter Register\r
+ AT91_REG MCI_TPR; // Transmit Pointer Register\r
+ AT91_REG MCI_TCR; // Transmit Counter Register\r
+ AT91_REG MCI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG MCI_RNCR; // Receive Next Counter Register\r
+ AT91_REG MCI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG MCI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG MCI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG MCI_PTSR; // PDC Transfer Status Register\r
+} AT91S_MCI, *AT91PS_MCI;\r
+#else\r
+#define MCI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (MCI_CR) MCI Control Register\r
+#define MCI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (MCI_MR) MCI Mode Register\r
+#define MCI_DTOR (AT91_CAST(AT91_REG *) 0x00000008) // (MCI_DTOR) MCI Data Timeout Register\r
+#define MCI_SDCR (AT91_CAST(AT91_REG *) 0x0000000C) // (MCI_SDCR) MCI SD Card Register\r
+#define MCI_ARGR (AT91_CAST(AT91_REG *) 0x00000010) // (MCI_ARGR) MCI Argument Register\r
+#define MCI_CMDR (AT91_CAST(AT91_REG *) 0x00000014) // (MCI_CMDR) MCI Command Register\r
+#define MCI_BLKR (AT91_CAST(AT91_REG *) 0x00000018) // (MCI_BLKR) MCI Block Register\r
+#define MCI_RSPR (AT91_CAST(AT91_REG *) 0x00000020) // (MCI_RSPR) MCI Response Register\r
+#define MCI_RDR (AT91_CAST(AT91_REG *) 0x00000030) // (MCI_RDR) MCI Receive Data Register\r
+#define MCI_TDR (AT91_CAST(AT91_REG *) 0x00000034) // (MCI_TDR) MCI Transmit Data Register\r
+#define MCI_SR (AT91_CAST(AT91_REG *) 0x00000040) // (MCI_SR) MCI Status Register\r
+#define MCI_IER (AT91_CAST(AT91_REG *) 0x00000044) // (MCI_IER) MCI Interrupt Enable Register\r
+#define MCI_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (MCI_IDR) MCI Interrupt Disable Register\r
+#define MCI_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register\r
+#define MCI_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (MCI_VR) MCI Version Register\r
+\r
+#endif\r
+// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- \r
+#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable\r
+#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable\r
+#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable\r
+#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable\r
+#define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset\r
+// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- \r
+#define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider\r
+#define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider\r
+#define AT91C_MCI_RDPROOF (0x1 << 11) // (MCI) Read Proof Enable\r
+#define AT91C_MCI_WRPROOF (0x1 << 12) // (MCI) Write Proof Enable\r
+#define AT91C_MCI_PDCFBYTE (0x1 << 13) // (MCI) PDC Force Byte Transfer\r
+#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value\r
+#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode\r
+#define AT91C_MCI_BLKLEN (0xFFFF << 16) // (MCI) Data Block Length\r
+// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- \r
+#define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number\r
+#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier\r
+#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1\r
+#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16\r
+#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128\r
+#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256\r
+#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024\r
+#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096\r
+#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536\r
+#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576\r
+// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- \r
+#define AT91C_MCI_SCDSEL (0x3 << 0) // (MCI) SD Card Selector\r
+#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SDCard/SDIO Bus Width\r
+// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- \r
+#define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number\r
+#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type\r
+#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response\r
+#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response\r
+#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response\r
+#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD\r
+#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD\r
+#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD\r
+#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD\r
+#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command\r
+#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response\r
+#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command\r
+#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond\r
+#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD\r
+#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer\r
+#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer\r
+#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer\r
+#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction\r
+#define AT91C_MCI_TRTYP (0x7 << 19) // (MCI) Transfer Type\r
+#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type\r
+#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type\r
+#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) MMC Stream transfer type\r
+#define AT91C_MCI_TRTYP_SDIO_BYTE (0x4 << 19) // (MCI) SDIO Byte transfer type\r
+#define AT91C_MCI_TRTYP_SDIO_BLOCK (0x5 << 19) // (MCI) SDIO Block transfer type\r
+#define AT91C_MCI_IOSPCMD (0x3 << 24) // (MCI) SDIO Special Command\r
+#define AT91C_MCI_IOSPCMD_NONE (0x0 << 24) // (MCI) NOT a special command\r
+#define AT91C_MCI_IOSPCMD_SUSPEND (0x1 << 24) // (MCI) SDIO Suspend Command\r
+#define AT91C_MCI_IOSPCMD_RESUME (0x2 << 24) // (MCI) SDIO Resume Command\r
+// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register -------- \r
+#define AT91C_MCI_BCNT (0xFFFF << 0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count\r
+// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- \r
+#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag\r
+#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag\r
+#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag\r
+#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag\r
+#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag\r
+#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag\r
+#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag\r
+#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag\r
+#define AT91C_MCI_SDIOIRQA (0x1 << 8) // (MCI) SDIO Interrupt for Slot A\r
+#define AT91C_MCI_SDIOIRQB (0x1 << 9) // (MCI) SDIO Interrupt for Slot B\r
+#define AT91C_MCI_SDIOIRQC (0x1 << 10) // (MCI) SDIO Interrupt for Slot C\r
+#define AT91C_MCI_SDIOIRQD (0x1 << 11) // (MCI) SDIO Interrupt for Slot D\r
+#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag\r
+#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag\r
+#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag\r
+#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag\r
+#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag\r
+#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag\r
+#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag\r
+#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag\r
+#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag\r
+#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag\r
+#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag\r
+// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- \r
+// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- \r
+// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Two-wire Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_TWI {\r
+ AT91_REG TWI_CR; // Control Register\r
+ AT91_REG TWI_MMR; // Master Mode Register\r
+ AT91_REG TWI_SMR; // Slave Mode Register\r
+ AT91_REG TWI_IADR; // Internal Address Register\r
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register\r
+ AT91_REG Reserved0[3]; // \r
+ AT91_REG TWI_SR; // Status Register\r
+ AT91_REG TWI_IER; // Interrupt Enable Register\r
+ AT91_REG TWI_IDR; // Interrupt Disable Register\r
+ AT91_REG TWI_IMR; // Interrupt Mask Register\r
+ AT91_REG TWI_RHR; // Receive Holding Register\r
+ AT91_REG TWI_THR; // Transmit Holding Register\r
+ AT91_REG Reserved1[50]; // \r
+ AT91_REG TWI_RPR; // Receive Pointer Register\r
+ AT91_REG TWI_RCR; // Receive Counter Register\r
+ AT91_REG TWI_TPR; // Transmit Pointer Register\r
+ AT91_REG TWI_TCR; // Transmit Counter Register\r
+ AT91_REG TWI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG TWI_RNCR; // Receive Next Counter Register\r
+ AT91_REG TWI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG TWI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG TWI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG TWI_PTSR; // PDC Transfer Status Register\r
+} AT91S_TWI, *AT91PS_TWI;\r
+#else\r
+#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register\r
+#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register\r
+#define TWI_SMR (AT91_CAST(AT91_REG *) 0x00000008) // (TWI_SMR) Slave Mode Register\r
+#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register\r
+#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register\r
+#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register\r
+#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register\r
+#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register\r
+#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register\r
+#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register\r
+#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register\r
+\r
+#endif\r
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition\r
+#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition\r
+#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled\r
+#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled\r
+#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave mode Enabled\r
+#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave mode Disabled\r
+#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset\r
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size\r
+#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address\r
+#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address\r
+#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address\r
+#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address\r
+#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction\r
+#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address\r
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- \r
+#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Address\r
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider\r
+#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider\r
+#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider\r
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+#define AT91C_TWI_TXCOMP_SLAVE (0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_TXCOMP_MASTER (0x1 << 0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY\r
+#define AT91C_TWI_TXRDY_MASTER (0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_TXRDY_SLAVE (0x1 << 2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave READ (used only in Slave mode)\r
+#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave ACCess (used only in Slave mode)\r
+#define AT91C_TWI_GACC (0x1 << 5) // (TWI) General Call ACcess (used only in Slave mode)\r
+#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error (used only in Master and Multi-master mode)\r
+#define AT91C_TWI_NACK_SLAVE (0x1 << 8) // (TWI) Not Acknowledged\r
+#define AT91C_TWI_NACK_MASTER (0x1 << 8) // (TWI) Not Acknowledged\r
+#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 << 9) // (TWI) Arbitration Lost (used only in Multimaster mode)\r
+#define AT91C_TWI_SCLWS (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)\r
+#define AT91C_TWI_EOSACC (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)\r
+#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) End of Receiver Transfer\r
+#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) End of Receiver Transfer\r
+#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) RXBUFF Interrupt\r
+#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) TXBUFE Interrupt\r
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Usart\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_USART {\r
+ AT91_REG US_CR; // Control Register\r
+ AT91_REG US_MR; // Mode Register\r
+ AT91_REG US_IER; // Interrupt Enable Register\r
+ AT91_REG US_IDR; // Interrupt Disable Register\r
+ AT91_REG US_IMR; // Interrupt Mask Register\r
+ AT91_REG US_CSR; // Channel Status Register\r
+ AT91_REG US_RHR; // Receiver Holding Register\r
+ AT91_REG US_THR; // Transmitter Holding Register\r
+ AT91_REG US_BRGR; // Baud Rate Generator Register\r
+ AT91_REG US_RTOR; // Receiver Time-out Register\r
+ AT91_REG US_TTGR; // Transmitter Time-guard Register\r
+ AT91_REG Reserved0[5]; // \r
+ AT91_REG US_FIDI; // FI_DI_Ratio Register\r
+ AT91_REG US_NER; // Nb Errors Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG US_IF; // IRDA_FILTER Register\r
+ AT91_REG Reserved2[44]; // \r
+ AT91_REG US_RPR; // Receive Pointer Register\r
+ AT91_REG US_RCR; // Receive Counter Register\r
+ AT91_REG US_TPR; // Transmit Pointer Register\r
+ AT91_REG US_TCR; // Transmit Counter Register\r
+ AT91_REG US_RNPR; // Receive Next Pointer Register\r
+ AT91_REG US_RNCR; // Receive Next Counter Register\r
+ AT91_REG US_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG US_TNCR; // Transmit Next Counter Register\r
+ AT91_REG US_PTCR; // PDC Transfer Control Register\r
+ AT91_REG US_PTSR; // PDC Transfer Status Register\r
+} AT91S_USART, *AT91PS_USART;\r
+#else\r
+#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register\r
+#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register\r
+#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register\r
+#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register\r
+#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register\r
+#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register\r
+#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register\r
+#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register\r
+#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register\r
+#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register\r
+#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register\r
+#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register\r
+#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register\r
+#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register\r
+\r
+#endif\r
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break\r
+#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address\r
+#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations\r
+#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge\r
+#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out\r
+#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable\r
+#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable\r
+#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable\r
+#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable\r
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode\r
+#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal\r
+#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485\r
+#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking\r
+#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem\r
+#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0\r
+#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1\r
+#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA\r
+#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking\r
+#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock\r
+#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1\r
+#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)\r
+#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits\r
+#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits\r
+#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits\r
+#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits\r
+#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit\r
+#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order\r
+#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select\r
+#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode\r
+#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge\r
+#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK\r
+#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions\r
+#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter\r
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break\r
+#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out\r
+#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached\r
+#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge\r
+#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
+#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
+#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag\r
+#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag\r
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \r
+#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input\r
+#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input\r
+#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input\r
+#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SSC {\r
+ AT91_REG SSC_CR; // Control Register\r
+ AT91_REG SSC_CMR; // Clock Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister\r
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register\r
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register\r
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register\r
+ AT91_REG SSC_RHR; // Receive Holding Register\r
+ AT91_REG SSC_THR; // Transmit Holding Register\r
+ AT91_REG Reserved1[2]; // \r
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register\r
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register\r
+ AT91_REG Reserved2[2]; // \r
+ AT91_REG SSC_SR; // Status Register\r
+ AT91_REG SSC_IER; // Interrupt Enable Register\r
+ AT91_REG SSC_IDR; // Interrupt Disable Register\r
+ AT91_REG SSC_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved3[44]; // \r
+ AT91_REG SSC_RPR; // Receive Pointer Register\r
+ AT91_REG SSC_RCR; // Receive Counter Register\r
+ AT91_REG SSC_TPR; // Transmit Pointer Register\r
+ AT91_REG SSC_TCR; // Transmit Counter Register\r
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SSC_RNCR; // Receive Next Counter Register\r
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register\r
+} AT91S_SSC, *AT91PS_SSC;\r
+#else\r
+#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register\r
+#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register\r
+#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister\r
+#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register\r
+#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register\r
+#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register\r
+#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register\r
+#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register\r
+#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register\r
+#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register\r
+#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register\r
+#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register\r
+#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register\r
+#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register\r
+\r
+#endif\r
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable\r
+#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable\r
+#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable\r
+#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable\r
+#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset\r
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection\r
+#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock\r
+#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal\r
+#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin\r
+#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
+#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion\r
+#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection\r
+#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start\r
+#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input\r
+#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input\r
+#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input\r
+#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input\r
+#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input\r
+#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input\r
+#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0\r
+#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
+#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length\r
+#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode\r
+#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First\r
+#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame\r
+#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
+#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
+#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection\r
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value\r
+#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable\r
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready\r
+#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty\r
+#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission\r
+#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty\r
+#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready\r
+#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun\r
+#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception\r
+#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full\r
+#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync\r
+#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync\r
+#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable\r
+#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable\r
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SPI {\r
+ AT91_REG SPI_CR; // Control Register\r
+ AT91_REG SPI_MR; // Mode Register\r
+ AT91_REG SPI_RDR; // Receive Data Register\r
+ AT91_REG SPI_TDR; // Transmit Data Register\r
+ AT91_REG SPI_SR; // Status Register\r
+ AT91_REG SPI_IER; // Interrupt Enable Register\r
+ AT91_REG SPI_IDR; // Interrupt Disable Register\r
+ AT91_REG SPI_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved0[4]; // \r
+ AT91_REG SPI_CSR[4]; // Chip Select Register\r
+ AT91_REG Reserved1[48]; // \r
+ AT91_REG SPI_RPR; // Receive Pointer Register\r
+ AT91_REG SPI_RCR; // Receive Counter Register\r
+ AT91_REG SPI_TPR; // Transmit Pointer Register\r
+ AT91_REG SPI_TCR; // Transmit Counter Register\r
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register\r
+ AT91_REG SPI_RNCR; // Receive Next Counter Register\r
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register\r
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register\r
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register\r
+} AT91S_SPI, *AT91PS_SPI;\r
+#else\r
+#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register\r
+#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register\r
+#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register\r
+#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register\r
+#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register\r
+#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register\r
+#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register\r
+#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register\r
+#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register\r
+\r
+#endif\r
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable\r
+#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable\r
+#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset\r
+#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer\r
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode\r
+#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select\r
+#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select\r
+#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select\r
+#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode\r
+#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection\r
+#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection\r
+#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection\r
+#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select\r
+#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects\r
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data\r
+#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data\r
+#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full\r
+#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty\r
+#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error\r
+#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status\r
+#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt\r
+#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt\r
+#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt\r
+#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt\r
+#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status\r
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity\r
+#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase\r
+#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer\r
+#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer\r
+#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer\r
+#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer\r
+#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer\r
+#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer\r
+#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer\r
+#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer\r
+#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer\r
+#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer\r
+#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer\r
+#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK\r
+#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_ADC {\r
+ AT91_REG ADC_CR; // ADC Control Register\r
+ AT91_REG ADC_MR; // ADC Mode Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG ADC_CHER; // ADC Channel Enable Register\r
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register\r
+ AT91_REG ADC_CHSR; // ADC Channel Status Register\r
+ AT91_REG ADC_SR; // ADC Status Register\r
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register\r
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register\r
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register\r
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register\r
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0\r
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1\r
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2\r
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3\r
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4\r
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5\r
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6\r
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7\r
+ AT91_REG Reserved1[44]; // \r
+ AT91_REG ADC_RPR; // Receive Pointer Register\r
+ AT91_REG ADC_RCR; // Receive Counter Register\r
+ AT91_REG ADC_TPR; // Transmit Pointer Register\r
+ AT91_REG ADC_TCR; // Transmit Counter Register\r
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register\r
+ AT91_REG ADC_RNCR; // Receive Next Counter Register\r
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register\r
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register\r
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register\r
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register\r
+} AT91S_ADC, *AT91PS_ADC;\r
+#else\r
+#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register\r
+#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register\r
+#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register\r
+#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register\r
+#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register\r
+#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register\r
+#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register\r
+#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register\r
+#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register\r
+#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register\r
+#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0\r
+#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1\r
+#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2\r
+#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3\r
+#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4\r
+#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5\r
+#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6\r
+#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7\r
+\r
+#endif\r
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset\r
+#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion\r
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable\r
+#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection\r
+#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0\r
+#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1\r
+#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2\r
+#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3\r
+#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4\r
+#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5\r
+#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger\r
+#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.\r
+#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution\r
+#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution\r
+#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode\r
+#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection\r
+#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time\r
+#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time\r
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0\r
+#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1\r
+#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2\r
+#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3\r
+#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4\r
+#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5\r
+#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6\r
+#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7\r
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion\r
+#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error\r
+#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready\r
+#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun\r
+#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer\r
+#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt\r
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted\r
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data\r
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_EMAC {\r
+ AT91_REG EMAC_NCR; // Network Control Register\r
+ AT91_REG EMAC_NCFGR; // Network Configuration Register\r
+ AT91_REG EMAC_NSR; // Network Status Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG EMAC_TSR; // Transmit Status Register\r
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer\r
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer\r
+ AT91_REG EMAC_RSR; // Receive Status Register\r
+ AT91_REG EMAC_ISR; // Interrupt Status Register\r
+ AT91_REG EMAC_IER; // Interrupt Enable Register\r
+ AT91_REG EMAC_IDR; // Interrupt Disable Register\r
+ AT91_REG EMAC_IMR; // Interrupt Mask Register\r
+ AT91_REG EMAC_MAN; // PHY Maintenance Register\r
+ AT91_REG EMAC_PTR; // Pause Time Register\r
+ AT91_REG EMAC_PFR; // Pause Frames received Register\r
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register\r
+ AT91_REG EMAC_SCF; // Single Collision Frame Register\r
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register\r
+ AT91_REG EMAC_FRO; // Frames Received OK Register\r
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register\r
+ AT91_REG EMAC_ALE; // Alignment Error Register\r
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register\r
+ AT91_REG EMAC_LCOL; // Late Collision Register\r
+ AT91_REG EMAC_ECOL; // Excessive Collision Register\r
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register\r
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register\r
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register\r
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register\r
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register\r
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register\r
+ AT91_REG EMAC_RJA; // Receive Jabbers Register\r
+ AT91_REG EMAC_USF; // Undersize Frames Register\r
+ AT91_REG EMAC_STE; // SQE Test Error Register\r
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register\r
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register\r
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]\r
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]\r
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes\r
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes\r
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes\r
+ AT91_REG EMAC_TID; // Type ID Checking Register\r
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register\r
+ AT91_REG EMAC_USRIO; // USER Input/Output Register\r
+ AT91_REG EMAC_WOL; // Wake On LAN Register\r
+ AT91_REG Reserved1[13]; // \r
+ AT91_REG EMAC_REV; // Revision Register\r
+} AT91S_EMAC, *AT91PS_EMAC;\r
+#else\r
+#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register\r
+#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register\r
+#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register\r
+#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register\r
+#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer\r
+#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer\r
+#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register\r
+#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register\r
+#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register\r
+#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register\r
+#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register\r
+#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register\r
+#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register\r
+#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register\r
+#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register\r
+#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register\r
+#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register\r
+#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register\r
+#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register\r
+#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register\r
+#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register\r
+#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register\r
+#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register\r
+#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register\r
+#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register\r
+#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register\r
+#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register\r
+#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register\r
+#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register\r
+#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register\r
+#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register\r
+#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register\r
+#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register\r
+#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register\r
+#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]\r
+#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32]\r
+#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes\r
+#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes\r
+#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes\r
+#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes\r
+#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes\r
+#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes\r
+#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes\r
+#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes\r
+#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register\r
+#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register\r
+#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register\r
+#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register\r
+#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register\r
+\r
+#endif\r
+// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- \r
+#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.\r
+#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. \r
+#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. \r
+#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. \r
+#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. \r
+#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. \r
+#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. \r
+#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. \r
+#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. \r
+#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. \r
+#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. \r
+#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame \r
+#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame\r
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- \r
+#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. \r
+#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. \r
+#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. \r
+#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. \r
+#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. \r
+#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable\r
+#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. \r
+#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. \r
+#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. \r
+#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) \r
+#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8\r
+#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16\r
+#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32\r
+#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64\r
+#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) \r
+#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) \r
+#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer\r
+#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable\r
+#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS\r
+#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) \r
+#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS\r
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- \r
+#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) \r
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- \r
+#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go\r
+#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame\r
+#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) \r
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \r
+#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) \r
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \r
+#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) \r
+#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) \r
+#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) \r
+#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) \r
+#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) \r
+#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) \r
+#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) \r
+#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) \r
+#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) \r
+#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) \r
+#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) \r
+#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) \r
+#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) \r
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \r
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \r
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \r
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \r
+#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) \r
+#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) \r
+#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) \r
+#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) \r
+#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) \r
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- \r
+#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII\r
+#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable\r
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- \r
+#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address\r
+#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable\r
+#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable\r
+#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable\r
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- \r
+#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) \r
+#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) \r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Device Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_UDP {\r
+ AT91_REG UDP_NUM; // Frame Number Register\r
+ AT91_REG UDP_GLBSTATE; // Global State Register\r
+ AT91_REG UDP_FADDR; // Function Address Register\r
+ AT91_REG Reserved0[1]; // \r
+ AT91_REG UDP_IER; // Interrupt Enable Register\r
+ AT91_REG UDP_IDR; // Interrupt Disable Register\r
+ AT91_REG UDP_IMR; // Interrupt Mask Register\r
+ AT91_REG UDP_ISR; // Interrupt Status Register\r
+ AT91_REG UDP_ICR; // Interrupt Clear Register\r
+ AT91_REG Reserved1[1]; // \r
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register\r
+ AT91_REG Reserved2[1]; // \r
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register\r
+ AT91_REG Reserved3[2]; // \r
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register\r
+ AT91_REG Reserved4[3]; // \r
+ AT91_REG UDP_TXVC; // Transceiver Control Register\r
+} AT91S_UDP, *AT91PS_UDP;\r
+#else\r
+#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register\r
+#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register\r
+#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register\r
+#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register\r
+#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register\r
+#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register\r
+#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register\r
+#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register\r
+#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register\r
+#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register\r
+#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register\r
+#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register\r
+\r
+#endif\r
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \r
+#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
+#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error\r
+#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK\r
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \r
+#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable\r
+#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured\r
+#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume\r
+#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host\r
+#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable\r
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \r
+#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value\r
+#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable\r
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \r
+#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt\r
+#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt\r
+#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt\r
+#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt\r
+#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt\r
+#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt\r
+#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt\r
+#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt\r
+#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt\r
+#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt\r
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \r
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \r
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \r
+#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\r
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \r
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \r
+#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0\r
+#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1\r
+#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2\r
+#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3\r
+#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4\r
+#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5\r
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \r
+#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR\r
+#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0\r
+#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)\r
+#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)\r
+#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)\r
+#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready\r
+#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
+#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
+#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction\r
+#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type\r
+#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control\r
+#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT\r
+#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT\r
+#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT\r
+#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN\r
+#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN\r
+#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN\r
+#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle\r
+#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable\r
+#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\r
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- \r
+#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) \r
+#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR USB Host Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_UHP {\r
+ AT91_REG UHP_HcRevision; // Revision\r
+ AT91_REG UHP_HcControl; // Operating modes for the Host Controller\r
+ AT91_REG UHP_HcCommandStatus; // Command & status Register\r
+ AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register\r
+ AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register\r
+ AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register\r
+ AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area\r
+ AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor\r
+ AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list\r
+ AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register\r
+ AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list\r
+ AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list\r
+ AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor\r
+ AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs\r
+ AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame\r
+ AT91_REG UHP_HcFmNumber; // Frame number\r
+ AT91_REG UHP_HcPeriodicStart; // Periodic Start\r
+ AT91_REG UHP_HcLSThreshold; // LS Threshold\r
+ AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A\r
+ AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B\r
+ AT91_REG UHP_HcRhStatus; // Root Hub Status register\r
+ AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register\r
+} AT91S_UHP, *AT91PS_UHP;\r
+#else\r
+#define HcRevision (AT91_CAST(AT91_REG *) 0x00000000) // (HcRevision) Revision\r
+#define HcControl (AT91_CAST(AT91_REG *) 0x00000004) // (HcControl) Operating modes for the Host Controller\r
+#define HcCommandStatus (AT91_CAST(AT91_REG *) 0x00000008) // (HcCommandStatus) Command & status Register\r
+#define HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0000000C) // (HcInterruptStatus) Interrupt Status Register\r
+#define HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00000010) // (HcInterruptEnable) Interrupt Enable Register\r
+#define HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00000014) // (HcInterruptDisable) Interrupt Disable Register\r
+#define HcHCCA (AT91_CAST(AT91_REG *) 0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area\r
+#define HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor\r
+#define HcControlHeadED (AT91_CAST(AT91_REG *) 0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list\r
+#define HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register\r
+#define HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list\r
+#define HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list\r
+#define HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor\r
+#define HcFmInterval (AT91_CAST(AT91_REG *) 0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs\r
+#define HcFmRemaining (AT91_CAST(AT91_REG *) 0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame\r
+#define HcFmNumber (AT91_CAST(AT91_REG *) 0x0000003C) // (HcFmNumber) Frame number\r
+#define HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00000040) // (HcPeriodicStart) Periodic Start\r
+#define HcLSThreshold (AT91_CAST(AT91_REG *) 0x00000044) // (HcLSThreshold) LS Threshold\r
+#define HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00000048) // (HcRhDescriptorA) Root Hub characteristics A\r
+#define HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B\r
+#define HcRhStatus (AT91_CAST(AT91_REG *) 0x00000050) // (HcRhStatus) Root Hub Status register\r
+#define HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00000054) // (HcRhPortStatus) Root Hub Port Status Register\r
+\r
+#endif\r
+\r
+// *****************************************************************************\r
+// SOFTWARE API DEFINITION FOR Image Sensor Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_ISI {\r
+ AT91_REG ISI_CR1; // Control Register 1\r
+ AT91_REG ISI_CR2; // Control Register 2\r
+ AT91_REG ISI_SR; // Status Register\r
+ AT91_REG ISI_IER; // Interrupt Enable Register\r
+ AT91_REG ISI_IDR; // Interrupt Disable Register\r
+ AT91_REG ISI_IMR; // Interrupt Mask Register\r
+ AT91_REG Reserved0[2]; // \r
+ AT91_REG ISI_PSIZE; // Preview Size Register\r
+ AT91_REG ISI_PDECF; // Preview Decimation Factor Register\r
+ AT91_REG ISI_PFBD; // Preview Frame Buffer Address Register\r
+ AT91_REG ISI_CDBA; // Codec Dma Address Register\r
+ AT91_REG ISI_Y2RSET0; // Color Space Conversion Register\r
+ AT91_REG ISI_Y2RSET1; // Color Space Conversion Register\r
+ AT91_REG ISI_R2YSET0; // Color Space Conversion Register\r
+ AT91_REG ISI_R2YSET1; // Color Space Conversion Register\r
+ AT91_REG ISI_R2YSET2; // Color Space Conversion Register\r
+} AT91S_ISI, *AT91PS_ISI;\r
+#else\r
+#define ISI_CR1 (AT91_CAST(AT91_REG *) 0x00000000) // (ISI_CR1) Control Register 1\r
+#define ISI_CR2 (AT91_CAST(AT91_REG *) 0x00000004) // (ISI_CR2) Control Register 2\r
+#define ISI_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ISI_SR) Status Register\r
+#define ISI_IER (AT91_CAST(AT91_REG *) 0x0000000C) // (ISI_IER) Interrupt Enable Register\r
+#define ISI_IDR (AT91_CAST(AT91_REG *) 0x00000010) // (ISI_IDR) Interrupt Disable Register\r
+#define ISI_IMR (AT91_CAST(AT91_REG *) 0x00000014) // (ISI_IMR) Interrupt Mask Register\r
+#define ISI_PSIZE (AT91_CAST(AT91_REG *) 0x00000020) // (ISI_PSIZE) Preview Size Register\r
+#define ISI_PDECF (AT91_CAST(AT91_REG *) 0x00000024) // (ISI_PDECF) Preview Decimation Factor Register\r
+#define ISI_PFBD (AT91_CAST(AT91_REG *) 0x00000028) // (ISI_PFBD) Preview Frame Buffer Address Register\r
+#define ISI_CDBA (AT91_CAST(AT91_REG *) 0x0000002C) // (ISI_CDBA) Codec Dma Address Register\r
+#define ISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0x00000030) // (ISI_Y2RSET0) Color Space Conversion Register\r
+#define ISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0x00000034) // (ISI_Y2RSET1) Color Space Conversion Register\r
+#define ISI_R2YSET0 (AT91_CAST(AT91_REG *) 0x00000038) // (ISI_R2YSET0) Color Space Conversion Register\r
+#define ISI_R2YSET1 (AT91_CAST(AT91_REG *) 0x0000003C) // (ISI_R2YSET1) Color Space Conversion Register\r
+#define ISI_R2YSET2 (AT91_CAST(AT91_REG *) 0x00000040) // (ISI_R2YSET2) Color Space Conversion Register\r
+\r
+#endif\r
+// -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 -------- \r
+#define AT91C_ISI_RST (0x1 << 0) // (ISI) Image sensor interface reset\r
+#define AT91C_ISI_DISABLE (0x1 << 1) // (ISI) image sensor disable.\r
+#define AT91C_ISI_HSYNC_POL (0x1 << 2) // (ISI) Horizontal synchronisation polarity\r
+#define AT91C_ISI_PIXCLK_POL (0x1 << 4) // (ISI) Pixel Clock Polarity\r
+#define AT91C_ISI_EMB_SYNC (0x1 << 6) // (ISI) Embedded synchronisation\r
+#define AT91C_ISI_CRC_SYNC (0x1 << 7) // (ISI) CRC correction\r
+#define AT91C_ISI_FULL (0x1 << 12) // (ISI) Full mode is allowed\r
+#define AT91C_ISI_THMASK (0x3 << 13) // (ISI) DMA Burst Mask\r
+#define AT91C_ISI_THMASK_4_8_16_BURST (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed\r
+#define AT91C_ISI_THMASK_8_16_BURST (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed\r
+#define AT91C_ISI_THMASK_16_BURST (0x2 << 13) // (ISI) Only 16 AHB burst are allowed\r
+#define AT91C_ISI_CODEC_ON (0x1 << 15) // (ISI) Enable the codec path\r
+#define AT91C_ISI_SLD (0xFF << 16) // (ISI) Start of Line Delay\r
+#define AT91C_ISI_SFD (0xFF << 24) // (ISI) Start of frame Delay\r
+// -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 -------- \r
+#define AT91C_ISI_IM_VSIZE (0x7FF << 0) // (ISI) Vertical size of the Image sensor [0..2047]\r
+#define AT91C_ISI_GS_MODE (0x1 << 11) // (ISI) Grayscale Memory Mode\r
+#define AT91C_ISI_RGB_MODE (0x3 << 12) // (ISI) RGB mode\r
+#define AT91C_ISI_RGB_MODE_RGB_888 (0x0 << 12) // (ISI) RGB 8:8:8 24 bits\r
+#define AT91C_ISI_RGB_MODE_RGB_565 (0x1 << 12) // (ISI) RGB 5:6:5 16 bits\r
+#define AT91C_ISI_RGB_MODE_RGB_555 (0x2 << 12) // (ISI) RGB 5:5:5 16 bits\r
+#define AT91C_ISI_GRAYSCALE (0x1 << 13) // (ISI) Grayscale Mode\r
+#define AT91C_ISI_RGB_SWAP (0x1 << 14) // (ISI) RGB Swap\r
+#define AT91C_ISI_COL_SPACE (0x1 << 15) // (ISI) Color space for the image data\r
+#define AT91C_ISI_IM_HSIZE (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047]\r
+#define AT91C_ISI_RGB_MODE_YCC_DEF (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1)\r
+#define AT91C_ISI_RGB_MODE_YCC_MOD1 (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1)\r
+#define AT91C_ISI_RGB_MODE_YCC_MOD2 (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i)\r
+#define AT91C_ISI_RGB_MODE_YCC_MOD3 (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i)\r
+#define AT91C_ISI_RGB_CFG (0x3 << 30) // (ISI) RGB configuration\r
+#define AT91C_ISI_RGB_CFG_RGB_DEF (0x0 << 30) // (ISI) R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B\r
+#define AT91C_ISI_RGB_CFG_RGB_MOD1 (0x1 << 30) // (ISI) B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R\r
+#define AT91C_ISI_RGB_CFG_RGB_MOD2 (0x2 << 30) // (ISI) G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB)\r
+#define AT91C_ISI_RGB_CFG_RGB_MOD3 (0x3 << 30) // (ISI) G(LSB)/B R/G(MSB) G(LSB)/B R/G(MSB)\r
+// -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register -------- \r
+#define AT91C_ISI_SOF (0x1 << 0) // (ISI) Start of Frame\r
+#define AT91C_ISI_DIS (0x1 << 1) // (ISI) Image Sensor Interface disable\r
+#define AT91C_ISI_SOFTRST (0x1 << 2) // (ISI) Software Reset\r
+#define AT91C_ISI_CRC_ERR (0x1 << 4) // (ISI) CRC synchronisation error\r
+#define AT91C_ISI_FO_C_OVF (0x1 << 5) // (ISI) Fifo Codec Overflow \r
+#define AT91C_ISI_FO_P_OVF (0x1 << 6) // (ISI) Fifo Preview Overflow \r
+#define AT91C_ISI_FO_P_EMP (0x1 << 7) // (ISI) Fifo Preview Empty\r
+#define AT91C_ISI_FO_C_EMP (0x1 << 8) // (ISI) Fifo Codec Empty\r
+#define AT91C_ISI_FR_OVR (0x1 << 9) // (ISI) Frame rate overun\r
+// -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register -------- \r
+// -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register -------- \r
+// -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register -------- \r
+// -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register -------- \r
+#define AT91C_ISI_PREV_VSIZE (0x3FF << 0) // (ISI) Vertical size for the preview path\r
+#define AT91C_ISI_PREV_HSIZE (0x3FF << 16) // (ISI) Horizontal size for the preview path\r
+// -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register -------- \r
+#define AT91C_ISI_Y2R_C0 (0xFF << 0) // (ISI) Color Space Conversion Matrix Coefficient C0\r
+#define AT91C_ISI_Y2R_C1 (0xFF << 8) // (ISI) Color Space Conversion Matrix Coefficient C1\r
+#define AT91C_ISI_Y2R_C2 (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2\r
+#define AT91C_ISI_Y2R_C3 (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3\r
+// -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register -------- \r
+#define AT91C_ISI_Y2R_C4 (0x1FF << 0) // (ISI) Color Space Conversion Matrix Coefficient C4\r
+#define AT91C_ISI_Y2R_YOFF (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset\r
+#define AT91C_ISI_Y2R_CROFF (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset\r
+#define AT91C_ISI_Y2R_CBFF (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset\r
+// -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register -------- \r
+#define AT91C_ISI_R2Y_C0 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0\r
+#define AT91C_ISI_R2Y_C1 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1\r
+#define AT91C_ISI_R2Y_C2 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2\r
+#define AT91C_ISI_R2Y_ROFF (0x1 << 4) // (ISI) Color Space Conversion Red component offset\r
+// -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register -------- \r
+#define AT91C_ISI_R2Y_C3 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3\r
+#define AT91C_ISI_R2Y_C4 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4\r
+#define AT91C_ISI_R2Y_C5 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5\r
+#define AT91C_ISI_R2Y_GOFF (0x1 << 4) // (ISI) Color Space Conversion Green component offset\r
+// -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register -------- \r
+#define AT91C_ISI_R2Y_C6 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6\r
+#define AT91C_ISI_R2Y_C7 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7\r
+#define AT91C_ISI_R2Y_C8 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8\r
+#define AT91C_ISI_R2Y_BOFF (0x1 << 4) // (ISI) Color Space Conversion Blue component offset\r
+\r
+// *****************************************************************************\r
+// REGISTER ADDRESS DEFINITION FOR AT91SAM9XE512\r
+// *****************************************************************************\r
+// ========== Register definition for SYS peripheral ========== \r
+#define AT91C_SYS_GPBR (AT91_CAST(AT91_REG *) 0xFFFFFFFF) // (SYS) General Purpose Register\r
+// ========== Register definition for EBI peripheral ========== \r
+#define AT91C_EBI_DUMMY (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (EBI) Dummy register - Do not use\r
+// ========== Register definition for HECC peripheral ========== \r
+#define AT91C_HECC_VR (AT91_CAST(AT91_REG *) 0xFFFFE8FC) // (HECC) ECC Version register\r
+#define AT91C_HECC_NPR (AT91_CAST(AT91_REG *) 0xFFFFE810) // (HECC) ECC Parity N register\r
+#define AT91C_HECC_SR (AT91_CAST(AT91_REG *) 0xFFFFE808) // (HECC) ECC Status register\r
+#define AT91C_HECC_PR (AT91_CAST(AT91_REG *) 0xFFFFE80C) // (HECC) ECC Parity register\r
+#define AT91C_HECC_MR (AT91_CAST(AT91_REG *) 0xFFFFE804) // (HECC) ECC Page size register\r
+#define AT91C_HECC_CR (AT91_CAST(AT91_REG *) 0xFFFFE800) // (HECC) ECC reset register\r
+// ========== Register definition for SDRAMC peripheral ========== \r
+#define AT91C_SDRAMC_MR (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register\r
+#define AT91C_SDRAMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register\r
+#define AT91C_SDRAMC_LPR (AT91_CAST(AT91_REG *) 0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register\r
+#define AT91C_SDRAMC_ISR (AT91_CAST(AT91_REG *) 0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register\r
+#define AT91C_SDRAMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register\r
+#define AT91C_SDRAMC_CR (AT91_CAST(AT91_REG *) 0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register\r
+#define AT91C_SDRAMC_TR (AT91_CAST(AT91_REG *) 0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register\r
+#define AT91C_SDRAMC_MDR (AT91_CAST(AT91_REG *) 0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register\r
+#define AT91C_SDRAMC_HSR (AT91_CAST(AT91_REG *) 0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register\r
+#define AT91C_SDRAMC_IER (AT91_CAST(AT91_REG *) 0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register\r
+// ========== Register definition for SMC peripheral ========== \r
+#define AT91C_SMC_CTRL1 (AT91_CAST(AT91_REG *) 0xFFFFEC1C) // (SMC) Control Register for CS 1\r
+#define AT91C_SMC_PULSE7 (AT91_CAST(AT91_REG *) 0xFFFFEC74) // (SMC) Pulse Register for CS 7\r
+#define AT91C_SMC_PULSE6 (AT91_CAST(AT91_REG *) 0xFFFFEC64) // (SMC) Pulse Register for CS 6\r
+#define AT91C_SMC_SETUP4 (AT91_CAST(AT91_REG *) 0xFFFFEC40) // (SMC) Setup Register for CS 4\r
+#define AT91C_SMC_PULSE3 (AT91_CAST(AT91_REG *) 0xFFFFEC34) // (SMC) Pulse Register for CS 3\r
+#define AT91C_SMC_CYCLE5 (AT91_CAST(AT91_REG *) 0xFFFFEC58) // (SMC) Cycle Register for CS 5\r
+#define AT91C_SMC_CYCLE2 (AT91_CAST(AT91_REG *) 0xFFFFEC28) // (SMC) Cycle Register for CS 2\r
+#define AT91C_SMC_CTRL2 (AT91_CAST(AT91_REG *) 0xFFFFEC2C) // (SMC) Control Register for CS 2\r
+#define AT91C_SMC_CTRL0 (AT91_CAST(AT91_REG *) 0xFFFFEC0C) // (SMC) Control Register for CS 0\r
+#define AT91C_SMC_PULSE5 (AT91_CAST(AT91_REG *) 0xFFFFEC54) // (SMC) Pulse Register for CS 5\r
+#define AT91C_SMC_PULSE1 (AT91_CAST(AT91_REG *) 0xFFFFEC14) // (SMC) Pulse Register for CS 1\r
+#define AT91C_SMC_PULSE0 (AT91_CAST(AT91_REG *) 0xFFFFEC04) // (SMC) Pulse Register for CS 0\r
+#define AT91C_SMC_CYCLE7 (AT91_CAST(AT91_REG *) 0xFFFFEC78) // (SMC) Cycle Register for CS 7\r
+#define AT91C_SMC_CTRL4 (AT91_CAST(AT91_REG *) 0xFFFFEC4C) // (SMC) Control Register for CS 4\r
+#define AT91C_SMC_CTRL3 (AT91_CAST(AT91_REG *) 0xFFFFEC3C) // (SMC) Control Register for CS 3\r
+#define AT91C_SMC_SETUP7 (AT91_CAST(AT91_REG *) 0xFFFFEC70) // (SMC) Setup Register for CS 7\r
+#define AT91C_SMC_CTRL7 (AT91_CAST(AT91_REG *) 0xFFFFEC7C) // (SMC) Control Register for CS 7\r
+#define AT91C_SMC_SETUP1 (AT91_CAST(AT91_REG *) 0xFFFFEC10) // (SMC) Setup Register for CS 1\r
+#define AT91C_SMC_CYCLE0 (AT91_CAST(AT91_REG *) 0xFFFFEC08) // (SMC) Cycle Register for CS 0\r
+#define AT91C_SMC_CTRL5 (AT91_CAST(AT91_REG *) 0xFFFFEC5C) // (SMC) Control Register for CS 5\r
+#define AT91C_SMC_CYCLE1 (AT91_CAST(AT91_REG *) 0xFFFFEC18) // (SMC) Cycle Register for CS 1\r
+#define AT91C_SMC_CTRL6 (AT91_CAST(AT91_REG *) 0xFFFFEC6C) // (SMC) Control Register for CS 6\r
+#define AT91C_SMC_SETUP0 (AT91_CAST(AT91_REG *) 0xFFFFEC00) // (SMC) Setup Register for CS 0\r
+#define AT91C_SMC_PULSE4 (AT91_CAST(AT91_REG *) 0xFFFFEC44) // (SMC) Pulse Register for CS 4\r
+#define AT91C_SMC_SETUP5 (AT91_CAST(AT91_REG *) 0xFFFFEC50) // (SMC) Setup Register for CS 5\r
+#define AT91C_SMC_SETUP2 (AT91_CAST(AT91_REG *) 0xFFFFEC20) // (SMC) Setup Register for CS 2\r
+#define AT91C_SMC_CYCLE3 (AT91_CAST(AT91_REG *) 0xFFFFEC38) // (SMC) Cycle Register for CS 3\r
+#define AT91C_SMC_CYCLE6 (AT91_CAST(AT91_REG *) 0xFFFFEC68) // (SMC) Cycle Register for CS 6\r
+#define AT91C_SMC_SETUP6 (AT91_CAST(AT91_REG *) 0xFFFFEC60) // (SMC) Setup Register for CS 6\r
+#define AT91C_SMC_CYCLE4 (AT91_CAST(AT91_REG *) 0xFFFFEC48) // (SMC) Cycle Register for CS 4\r
+#define AT91C_SMC_PULSE2 (AT91_CAST(AT91_REG *) 0xFFFFEC24) // (SMC) Pulse Register for CS 2\r
+#define AT91C_SMC_SETUP3 (AT91_CAST(AT91_REG *) 0xFFFFEC30) // (SMC) Setup Register for CS 3\r
+// ========== Register definition for MATRIX peripheral ========== \r
+#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE00) // (MATRIX) Master Configuration Register 0 (ram96k) \r
+#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0xFFFFEE1C) // (MATRIX) Master Configuration Register 7 (teak_prog) \r
+#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE44) // (MATRIX) Slave Configuration Register 1 (rom) \r
+#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE10) // (MATRIX) Master Configuration Register 4 (bridge) \r
+#define AT91C_MATRIX_VERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (MATRIX) Version Register\r
+#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE08) // (MATRIX) Master Configuration Register 2 (hperiphs) \r
+#define AT91C_MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA4) // (MATRIX) PRBS4 : ebi\r
+#define AT91C_MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0xFFFFEE84) // (MATRIX) PRBS0 (ram0) \r
+#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE4C) // (MATRIX) Slave Configuration Register 3 (ebi)\r
+#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0xFFFFEE18) // (MATRIX) Master Configuration Register 6 (ram16k) \r
+#define AT91C_MATRIX_EBI (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (MATRIX) Slave 3 (ebi) Special Function Register\r
+#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE40) // (MATRIX) Slave Configuration Register 0 (ram96k) \r
+#define AT91C_MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0xFFFFEE9C) // (MATRIX) PRBS3 : usb_dev_hs\r
+#define AT91C_MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0xFFFFEE98) // (MATRIX) PRAS3 : usb_dev_hs\r
+#define AT91C_MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0xFFFFEE80) // (MATRIX) PRAS0 (ram0) \r
+#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE0C) // (MATRIX) Master Configuration Register 3 (ebi)\r
+#define AT91C_MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0xFFFFEE88) // (MATRIX) PRAS1 (ram1) \r
+#define AT91C_MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0xFFFFEE90) // (MATRIX) PRAS2 (ram2) \r
+#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE48) // (MATRIX) Slave Configuration Register 2 (hperiphs) \r
+#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0xFFFFEE14) // (MATRIX) Master Configuration Register 5 (mailbox) \r
+#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE04) // (MATRIX) Master Configuration Register 1 (rom) \r
+#define AT91C_MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA0) // (MATRIX) PRAS4 : ebi\r
+#define AT91C_MATRIX_MRCR (AT91_CAST(AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register \r
+#define AT91C_MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0xFFFFEE94) // (MATRIX) PRBS2 (ram2) \r
+#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE50) // (MATRIX) Slave Configuration Register 4 (bridge) \r
+#define AT91C_MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0xFFFFEF2C) // (MATRIX) Slave 7 (teak_prog) Special Function Register\r
+#define AT91C_MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0xFFFFEE8C) // (MATRIX) PRBS1 (ram1) \r
+// ========== Register definition for CCFG peripheral ========== \r
+#define AT91C_CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (CCFG) Version Register\r
+#define AT91C_CCFG_EBICSA (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register\r
+// ========== Register definition for PDC_DBGU peripheral ========== \r
+#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\r
+#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\r
+#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\r
+#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\r
+#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\r
+#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register\r
+#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\r
+#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\r
+#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\r
+#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\r
+// ========== Register definition for DBGU peripheral ========== \r
+#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register\r
+#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register\r
+#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register\r
+#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register\r
+#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register\r
+#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register\r
+#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register\r
+#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register\r
+#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register\r
+#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register\r
+#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register\r
+#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register\r
+// ========== Register definition for AIC peripheral ========== \r
+#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register\r
+#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register\r
+#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register\r
+#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)\r
+#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register\r
+#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register\r
+#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register\r
+#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register\r
+#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register\r
+#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register\r
+#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register\r
+#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register\r
+#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register\r
+#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register\r
+#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register\r
+#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register\r
+#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register\r
+#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register\r
+// ========== Register definition for PIOA peripheral ========== \r
+#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr\r
+#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register\r
+#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register\r
+#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register\r
+#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register\r
+#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register\r
+#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register\r
+#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register\r
+#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register\r
+#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register\r
+#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register\r
+#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register\r
+#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register\r
+#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register\r
+#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register\r
+#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register\r
+#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register\r
+#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register\r
+#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register\r
+#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register\r
+#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register\r
+#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register\r
+#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register\r
+#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register\r
+#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register\r
+#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register\r
+#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register\r
+#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register\r
+#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register\r
+// ========== Register definition for PIOB peripheral ========== \r
+#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register\r
+#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register\r
+#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register\r
+#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register\r
+#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register\r
+#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register\r
+#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register\r
+#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register\r
+#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register\r
+#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register\r
+#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register\r
+#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register\r
+#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register\r
+#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register\r
+#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register\r
+#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register\r
+#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr\r
+#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register\r
+#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register\r
+#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register\r
+#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register\r
+#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register\r
+#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register\r
+#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register\r
+#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register\r
+#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register\r
+#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register\r
+#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register\r
+#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register\r
+// ========== Register definition for PIOC peripheral ========== \r
+#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register\r
+#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register\r
+#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register\r
+#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register\r
+#define AT91C_PIOC_PSR (AT91_CAST(AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register\r
+#define AT91C_PIOC_PDR (AT91_CAST(AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register\r
+#define AT91C_PIOC_ODR (AT91_CAST(AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr\r
+#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF868) // (PIOC) Pull-up Status Register\r
+#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register\r
+#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register\r
+#define AT91C_PIOC_OER (AT91_CAST(AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register\r
+#define AT91C_PIOC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register\r
+#define AT91C_PIOC_ASR (AT91_CAST(AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register\r
+#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register\r
+#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register\r
+#define AT91C_PIOC_PER (AT91_CAST(AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register\r
+#define AT91C_PIOC_IDR (AT91_CAST(AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register\r
+#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register\r
+#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register\r
+#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register\r
+#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register\r
+#define AT91C_PIOC_BSR (AT91_CAST(AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register\r
+#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register\r
+#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register\r
+#define AT91C_PIOC_IER (AT91_CAST(AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register\r
+#define AT91C_PIOC_OSR (AT91_CAST(AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register\r
+#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register\r
+#define AT91C_PIOC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register\r
+#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register\r
+// ========== Register definition for EFC peripheral ========== \r
+#define AT91C_EFC_FVR (AT91_CAST(AT91_REG *) 0xFFFFFA10) // (EFC) EFC Flash Version Register\r
+#define AT91C_EFC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFA04) // (EFC) EFC Flash Command Register\r
+#define AT91C_EFC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFA00) // (EFC) EFC Flash Mode Register\r
+#define AT91C_EFC_FRR (AT91_CAST(AT91_REG *) 0xFFFFFA0C) // (EFC) EFC Flash Result Register\r
+#define AT91C_EFC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFA08) // (EFC) EFC Flash Status Register\r
+// ========== Register definition for CKGR peripheral ========== \r
+#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register\r
+#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register\r
+#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register\r
+#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register\r
+// ========== Register definition for PMC peripheral ========== \r
+#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\r
+#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register\r
+#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register\r
+#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register\r
+#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\r
+#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register\r
+#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register\r
+#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register\r
+#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register\r
+#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register\r
+#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register\r
+#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register\r
+#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register\r
+#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register\r
+#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register\r
+#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register\r
+// ========== Register definition for RSTC peripheral ========== \r
+#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register\r
+#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register\r
+#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register\r
+// ========== Register definition for SHDWC peripheral ========== \r
+#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register\r
+#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register\r
+#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register\r
+// ========== Register definition for RTTC peripheral ========== \r
+#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register\r
+#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register\r
+#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register\r
+#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register\r
+// ========== Register definition for PITC peripheral ========== \r
+#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register\r
+#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register\r
+#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register\r
+#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register\r
+// ========== Register definition for WDTC peripheral ========== \r
+#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register\r
+#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register\r
+#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register\r
+#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C\r
+#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B\r
+#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register\r
+#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A\r
+#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value\r
+#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B\r
+#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register\r
+#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register\r
+#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A\r
+#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C\r
+#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register\r
+#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value\r
+#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A\r
+#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B\r
+#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register\r
+#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C\r
+#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register\r
+// ========== Register definition for TC3 peripheral ========== \r
+#define AT91C_TC3_IER (AT91_CAST(AT91_REG *) 0xFFFDC024) // (TC3) Interrupt Enable Register\r
+#define AT91C_TC3_RB (AT91_CAST(AT91_REG *) 0xFFFDC018) // (TC3) Register B\r
+#define AT91C_TC3_CMR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC3_RC (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (TC3) Register C\r
+#define AT91C_TC3_CCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (TC3) Channel Control Register\r
+#define AT91C_TC3_SR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (TC3) Status Register\r
+#define AT91C_TC3_CV (AT91_CAST(AT91_REG *) 0xFFFDC010) // (TC3) Counter Value\r
+#define AT91C_TC3_RA (AT91_CAST(AT91_REG *) 0xFFFDC014) // (TC3) Register A\r
+#define AT91C_TC3_IDR (AT91_CAST(AT91_REG *) 0xFFFDC028) // (TC3) Interrupt Disable Register\r
+#define AT91C_TC3_IMR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (TC3) Interrupt Mask Register\r
+// ========== Register definition for TC4 peripheral ========== \r
+#define AT91C_TC4_CMR (AT91_CAST(AT91_REG *) 0xFFFDC044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC4_RC (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (TC4) Register C\r
+#define AT91C_TC4_SR (AT91_CAST(AT91_REG *) 0xFFFDC060) // (TC4) Status Register\r
+#define AT91C_TC4_RB (AT91_CAST(AT91_REG *) 0xFFFDC058) // (TC4) Register B\r
+#define AT91C_TC4_IER (AT91_CAST(AT91_REG *) 0xFFFDC064) // (TC4) Interrupt Enable Register\r
+#define AT91C_TC4_CV (AT91_CAST(AT91_REG *) 0xFFFDC050) // (TC4) Counter Value\r
+#define AT91C_TC4_RA (AT91_CAST(AT91_REG *) 0xFFFDC054) // (TC4) Register A\r
+#define AT91C_TC4_IDR (AT91_CAST(AT91_REG *) 0xFFFDC068) // (TC4) Interrupt Disable Register\r
+#define AT91C_TC4_IMR (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (TC4) Interrupt Mask Register\r
+#define AT91C_TC4_CCR (AT91_CAST(AT91_REG *) 0xFFFDC040) // (TC4) Channel Control Register\r
+// ========== Register definition for TC5 peripheral ========== \r
+#define AT91C_TC5_RB (AT91_CAST(AT91_REG *) 0xFFFDC098) // (TC5) Register B\r
+#define AT91C_TC5_RA (AT91_CAST(AT91_REG *) 0xFFFDC094) // (TC5) Register A\r
+#define AT91C_TC5_CV (AT91_CAST(AT91_REG *) 0xFFFDC090) // (TC5) Counter Value\r
+#define AT91C_TC5_CCR (AT91_CAST(AT91_REG *) 0xFFFDC080) // (TC5) Channel Control Register\r
+#define AT91C_TC5_SR (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (TC5) Status Register\r
+#define AT91C_TC5_IER (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (TC5) Interrupt Enable Register\r
+#define AT91C_TC5_IDR (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (TC5) Interrupt Disable Register\r
+#define AT91C_TC5_RC (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (TC5) Register C\r
+#define AT91C_TC5_IMR (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (TC5) Interrupt Mask Register\r
+#define AT91C_TC5_CMR (AT91_CAST(AT91_REG *) 0xFFFDC084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode)\r
+// ========== Register definition for TCB0 peripheral ========== \r
+#define AT91C_TCB0_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register\r
+#define AT91C_TCB0_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register\r
+// ========== Register definition for TCB1 peripheral ========== \r
+#define AT91C_TCB1_BCR (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (TCB1) TC Block Control Register\r
+#define AT91C_TCB1_BMR (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (TCB1) TC Block Mode Register\r
+// ========== Register definition for PDC_MCI peripheral ========== \r
+#define AT91C_MCI_RNCR (AT91_CAST(AT91_REG *) 0xFFFA8114) // (PDC_MCI) Receive Next Counter Register\r
+#define AT91C_MCI_TCR (AT91_CAST(AT91_REG *) 0xFFFA810C) // (PDC_MCI) Transmit Counter Register\r
+#define AT91C_MCI_RCR (AT91_CAST(AT91_REG *) 0xFFFA8104) // (PDC_MCI) Receive Counter Register\r
+#define AT91C_MCI_TNPR (AT91_CAST(AT91_REG *) 0xFFFA8118) // (PDC_MCI) Transmit Next Pointer Register\r
+#define AT91C_MCI_RNPR (AT91_CAST(AT91_REG *) 0xFFFA8110) // (PDC_MCI) Receive Next Pointer Register\r
+#define AT91C_MCI_RPR (AT91_CAST(AT91_REG *) 0xFFFA8100) // (PDC_MCI) Receive Pointer Register\r
+#define AT91C_MCI_TNCR (AT91_CAST(AT91_REG *) 0xFFFA811C) // (PDC_MCI) Transmit Next Counter Register\r
+#define AT91C_MCI_TPR (AT91_CAST(AT91_REG *) 0xFFFA8108) // (PDC_MCI) Transmit Pointer Register\r
+#define AT91C_MCI_PTSR (AT91_CAST(AT91_REG *) 0xFFFA8124) // (PDC_MCI) PDC Transfer Status Register\r
+#define AT91C_MCI_PTCR (AT91_CAST(AT91_REG *) 0xFFFA8120) // (PDC_MCI) PDC Transfer Control Register\r
+// ========== Register definition for MCI peripheral ========== \r
+#define AT91C_MCI_RDR (AT91_CAST(AT91_REG *) 0xFFFA8030) // (MCI) MCI Receive Data Register\r
+#define AT91C_MCI_CMDR (AT91_CAST(AT91_REG *) 0xFFFA8014) // (MCI) MCI Command Register\r
+#define AT91C_MCI_VR (AT91_CAST(AT91_REG *) 0xFFFA80FC) // (MCI) MCI Version Register\r
+#define AT91C_MCI_IDR (AT91_CAST(AT91_REG *) 0xFFFA8048) // (MCI) MCI Interrupt Disable Register\r
+#define AT91C_MCI_DTOR (AT91_CAST(AT91_REG *) 0xFFFA8008) // (MCI) MCI Data Timeout Register\r
+#define AT91C_MCI_TDR (AT91_CAST(AT91_REG *) 0xFFFA8034) // (MCI) MCI Transmit Data Register\r
+#define AT91C_MCI_IER (AT91_CAST(AT91_REG *) 0xFFFA8044) // (MCI) MCI Interrupt Enable Register\r
+#define AT91C_MCI_BLKR (AT91_CAST(AT91_REG *) 0xFFFA8018) // (MCI) MCI Block Register\r
+#define AT91C_MCI_MR (AT91_CAST(AT91_REG *) 0xFFFA8004) // (MCI) MCI Mode Register\r
+#define AT91C_MCI_IMR (AT91_CAST(AT91_REG *) 0xFFFA804C) // (MCI) MCI Interrupt Mask Register\r
+#define AT91C_MCI_CR (AT91_CAST(AT91_REG *) 0xFFFA8000) // (MCI) MCI Control Register\r
+#define AT91C_MCI_ARGR (AT91_CAST(AT91_REG *) 0xFFFA8010) // (MCI) MCI Argument Register\r
+#define AT91C_MCI_SDCR (AT91_CAST(AT91_REG *) 0xFFFA800C) // (MCI) MCI SD Card Register\r
+#define AT91C_MCI_SR (AT91_CAST(AT91_REG *) 0xFFFA8040) // (MCI) MCI Status Register\r
+#define AT91C_MCI_RSPR (AT91_CAST(AT91_REG *) 0xFFFA8020) // (MCI) MCI Response Register\r
+// ========== Register definition for PDC_TWI0 peripheral ========== \r
+#define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFAC124) // (PDC_TWI0) PDC Transfer Status Register\r
+#define AT91C_TWI0_RPR (AT91_CAST(AT91_REG *) 0xFFFAC100) // (PDC_TWI0) Receive Pointer Register\r
+#define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFAC114) // (PDC_TWI0) Receive Next Counter Register\r
+#define AT91C_TWI0_RCR (AT91_CAST(AT91_REG *) 0xFFFAC104) // (PDC_TWI0) Receive Counter Register\r
+#define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFAC120) // (PDC_TWI0) PDC Transfer Control Register\r
+#define AT91C_TWI0_TPR (AT91_CAST(AT91_REG *) 0xFFFAC108) // (PDC_TWI0) Transmit Pointer Register\r
+#define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFAC110) // (PDC_TWI0) Receive Next Pointer Register\r
+#define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFAC118) // (PDC_TWI0) Transmit Next Pointer Register\r
+#define AT91C_TWI0_TCR (AT91_CAST(AT91_REG *) 0xFFFAC10C) // (PDC_TWI0) Transmit Counter Register\r
+#define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFAC11C) // (PDC_TWI0) Transmit Next Counter Register\r
+// ========== Register definition for TWI0 peripheral ========== \r
+#define AT91C_TWI0_THR (AT91_CAST(AT91_REG *) 0xFFFAC034) // (TWI0) Transmit Holding Register\r
+#define AT91C_TWI0_IDR (AT91_CAST(AT91_REG *) 0xFFFAC028) // (TWI0) Interrupt Disable Register\r
+#define AT91C_TWI0_SMR (AT91_CAST(AT91_REG *) 0xFFFAC008) // (TWI0) Slave Mode Register\r
+#define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *) 0xFFFAC010) // (TWI0) Clock Waveform Generator Register\r
+#define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *) 0xFFFAC00C) // (TWI0) Internal Address Register\r
+#define AT91C_TWI0_RHR (AT91_CAST(AT91_REG *) 0xFFFAC030) // (TWI0) Receive Holding Register\r
+#define AT91C_TWI0_IER (AT91_CAST(AT91_REG *) 0xFFFAC024) // (TWI0) Interrupt Enable Register\r
+#define AT91C_TWI0_MMR (AT91_CAST(AT91_REG *) 0xFFFAC004) // (TWI0) Master Mode Register\r
+#define AT91C_TWI0_SR (AT91_CAST(AT91_REG *) 0xFFFAC020) // (TWI0) Status Register\r
+#define AT91C_TWI0_IMR (AT91_CAST(AT91_REG *) 0xFFFAC02C) // (TWI0) Interrupt Mask Register\r
+#define AT91C_TWI0_CR (AT91_CAST(AT91_REG *) 0xFFFAC000) // (TWI0) Control Register\r
+// ========== Register definition for PDC_TWI1 peripheral ========== \r
+#define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_TWI1) PDC Transfer Status Register\r
+#define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_TWI1) PDC Transfer Control Register\r
+#define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_TWI1) Transmit Next Pointer Register\r
+#define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_TWI1) Transmit Next Counter Register\r
+#define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_TWI1) Receive Next Pointer Register\r
+#define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_TWI1) Receive Next Counter Register\r
+#define AT91C_TWI1_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_TWI1) Receive Pointer Register\r
+#define AT91C_TWI1_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_TWI1) Transmit Counter Register\r
+#define AT91C_TWI1_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_TWI1) Transmit Pointer Register\r
+#define AT91C_TWI1_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_TWI1) Receive Counter Register\r
+// ========== Register definition for TWI1 peripheral ========== \r
+#define AT91C_TWI1_RHR (AT91_CAST(AT91_REG *) 0xFFFD8030) // (TWI1) Receive Holding Register\r
+#define AT91C_TWI1_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (TWI1) Interrupt Enable Register\r
+#define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *) 0xFFFD8010) // (TWI1) Clock Waveform Generator Register\r
+#define AT91C_TWI1_MMR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (TWI1) Master Mode Register\r
+#define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *) 0xFFFD800C) // (TWI1) Internal Address Register\r
+#define AT91C_TWI1_THR (AT91_CAST(AT91_REG *) 0xFFFD8034) // (TWI1) Transmit Holding Register\r
+#define AT91C_TWI1_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (TWI1) Interrupt Mask Register\r
+#define AT91C_TWI1_SR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (TWI1) Status Register\r
+#define AT91C_TWI1_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (TWI1) Interrupt Disable Register\r
+#define AT91C_TWI1_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (TWI1) Control Register\r
+#define AT91C_TWI1_SMR (AT91_CAST(AT91_REG *) 0xFFFD8008) // (TWI1) Slave Mode Register\r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFB010C) // (PDC_US0) Transmit Counter Register\r
+#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFB0120) // (PDC_US0) PDC Transfer Control Register\r
+#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFB0114) // (PDC_US0) Receive Next Counter Register\r
+#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFB0124) // (PDC_US0) PDC Transfer Status Register\r
+#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFB011C) // (PDC_US0) Transmit Next Counter Register\r
+#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFB0110) // (PDC_US0) Receive Next Pointer Register\r
+#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFB0104) // (PDC_US0) Receive Counter Register\r
+#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFB0108) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register\r
+#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFB0100) // (PDC_US0) Receive Pointer Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFB0044) // (US0) Nb Errors Register\r
+#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFB0008) // (US0) Interrupt Enable Register\r
+#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFB0000) // (US0) Control Register\r
+#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (US0) Transmitter Holding Register\r
+#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (US0) Channel Status Register\r
+#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFB0024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFB0028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFB000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFB0004) // (US0) Mode Register\r
+#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFB004C) // (US0) IRDA_FILTER Register\r
+#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFB0040) // (US0) FI_DI_Ratio Register\r
+#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFB0010) // (US0) Interrupt Mask Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFB4120) // (PDC_US1) PDC Transfer Control Register\r
+#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFB4104) // (PDC_US1) Receive Counter Register\r
+#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFB4100) // (PDC_US1) Receive Pointer Register\r
+#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFB4124) // (PDC_US1) PDC Transfer Status Register\r
+#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFB4108) // (PDC_US1) Transmit Pointer Register\r
+#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFB410C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFB4110) // (PDC_US1) Receive Next Pointer Register\r
+#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFB411C) // (PDC_US1) Transmit Next Counter Register\r
+#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFB4114) // (PDC_US1) Receive Next Counter Register\r
+#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFB401C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFB4028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFB4020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFB400C) // (US1) Interrupt Disable Register\r
+#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFB4004) // (US1) Mode Register\r
+#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFB4024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFB4000) // (US1) Control Register\r
+#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFB4010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFB4040) // (US1) FI_DI_Ratio Register\r
+#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFB4018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFB4008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFB4014) // (US1) Channel Status Register\r
+#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFB404C) // (US1) IRDA_FILTER Register\r
+#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFB4044) // (US1) Nb Errors Register\r
+// ========== Register definition for PDC_US2 peripheral ========== \r
+#define AT91C_US2_TNCR (AT91_CAST(AT91_REG *) 0xFFFB811C) // (PDC_US2) Transmit Next Counter Register\r
+#define AT91C_US2_RNCR (AT91_CAST(AT91_REG *) 0xFFFB8114) // (PDC_US2) Receive Next Counter Register\r
+#define AT91C_US2_TNPR (AT91_CAST(AT91_REG *) 0xFFFB8118) // (PDC_US2) Transmit Next Pointer Register\r
+#define AT91C_US2_PTCR (AT91_CAST(AT91_REG *) 0xFFFB8120) // (PDC_US2) PDC Transfer Control Register\r
+#define AT91C_US2_TCR (AT91_CAST(AT91_REG *) 0xFFFB810C) // (PDC_US2) Transmit Counter Register\r
+#define AT91C_US2_RPR (AT91_CAST(AT91_REG *) 0xFFFB8100) // (PDC_US2) Receive Pointer Register\r
+#define AT91C_US2_TPR (AT91_CAST(AT91_REG *) 0xFFFB8108) // (PDC_US2) Transmit Pointer Register\r
+#define AT91C_US2_RCR (AT91_CAST(AT91_REG *) 0xFFFB8104) // (PDC_US2) Receive Counter Register\r
+#define AT91C_US2_PTSR (AT91_CAST(AT91_REG *) 0xFFFB8124) // (PDC_US2) PDC Transfer Status Register\r
+#define AT91C_US2_RNPR (AT91_CAST(AT91_REG *) 0xFFFB8110) // (PDC_US2) Receive Next Pointer Register\r
+// ========== Register definition for US2 peripheral ========== \r
+#define AT91C_US2_RTOR (AT91_CAST(AT91_REG *) 0xFFFB8024) // (US2) Receiver Time-out Register\r
+#define AT91C_US2_CSR (AT91_CAST(AT91_REG *) 0xFFFB8014) // (US2) Channel Status Register\r
+#define AT91C_US2_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (US2) Control Register\r
+#define AT91C_US2_BRGR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (US2) Baud Rate Generator Register\r
+#define AT91C_US2_NER (AT91_CAST(AT91_REG *) 0xFFFB8044) // (US2) Nb Errors Register\r
+#define AT91C_US2_FIDI (AT91_CAST(AT91_REG *) 0xFFFB8040) // (US2) FI_DI_Ratio Register\r
+#define AT91C_US2_TTGR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (US2) Transmitter Time-guard Register\r
+#define AT91C_US2_RHR (AT91_CAST(AT91_REG *) 0xFFFB8018) // (US2) Receiver Holding Register\r
+#define AT91C_US2_IDR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (US2) Interrupt Disable Register\r
+#define AT91C_US2_THR (AT91_CAST(AT91_REG *) 0xFFFB801C) // (US2) Transmitter Holding Register\r
+#define AT91C_US2_MR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (US2) Mode Register\r
+#define AT91C_US2_IMR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (US2) Interrupt Mask Register\r
+#define AT91C_US2_IF (AT91_CAST(AT91_REG *) 0xFFFB804C) // (US2) IRDA_FILTER Register\r
+#define AT91C_US2_IER (AT91_CAST(AT91_REG *) 0xFFFB8008) // (US2) Interrupt Enable Register\r
+// ========== Register definition for PDC_US3 peripheral ========== \r
+#define AT91C_US3_RNPR (AT91_CAST(AT91_REG *) 0xFFFD0110) // (PDC_US3) Receive Next Pointer Register\r
+#define AT91C_US3_RNCR (AT91_CAST(AT91_REG *) 0xFFFD0114) // (PDC_US3) Receive Next Counter Register\r
+#define AT91C_US3_PTSR (AT91_CAST(AT91_REG *) 0xFFFD0124) // (PDC_US3) PDC Transfer Status Register\r
+#define AT91C_US3_PTCR (AT91_CAST(AT91_REG *) 0xFFFD0120) // (PDC_US3) PDC Transfer Control Register\r
+#define AT91C_US3_TCR (AT91_CAST(AT91_REG *) 0xFFFD010C) // (PDC_US3) Transmit Counter Register\r
+#define AT91C_US3_TNPR (AT91_CAST(AT91_REG *) 0xFFFD0118) // (PDC_US3) Transmit Next Pointer Register\r
+#define AT91C_US3_RCR (AT91_CAST(AT91_REG *) 0xFFFD0104) // (PDC_US3) Receive Counter Register\r
+#define AT91C_US3_TPR (AT91_CAST(AT91_REG *) 0xFFFD0108) // (PDC_US3) Transmit Pointer Register\r
+#define AT91C_US3_TNCR (AT91_CAST(AT91_REG *) 0xFFFD011C) // (PDC_US3) Transmit Next Counter Register\r
+#define AT91C_US3_RPR (AT91_CAST(AT91_REG *) 0xFFFD0100) // (PDC_US3) Receive Pointer Register\r
+// ========== Register definition for US3 peripheral ========== \r
+#define AT91C_US3_NER (AT91_CAST(AT91_REG *) 0xFFFD0044) // (US3) Nb Errors Register\r
+#define AT91C_US3_RTOR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (US3) Receiver Time-out Register\r
+#define AT91C_US3_IDR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (US3) Interrupt Disable Register\r
+#define AT91C_US3_MR (AT91_CAST(AT91_REG *) 0xFFFD0004) // (US3) Mode Register\r
+#define AT91C_US3_FIDI (AT91_CAST(AT91_REG *) 0xFFFD0040) // (US3) FI_DI_Ratio Register\r
+#define AT91C_US3_BRGR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (US3) Baud Rate Generator Register\r
+#define AT91C_US3_THR (AT91_CAST(AT91_REG *) 0xFFFD001C) // (US3) Transmitter Holding Register\r
+#define AT91C_US3_CR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (US3) Control Register\r
+#define AT91C_US3_IF (AT91_CAST(AT91_REG *) 0xFFFD004C) // (US3) IRDA_FILTER Register\r
+#define AT91C_US3_IER (AT91_CAST(AT91_REG *) 0xFFFD0008) // (US3) Interrupt Enable Register\r
+#define AT91C_US3_TTGR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (US3) Transmitter Time-guard Register\r
+#define AT91C_US3_RHR (AT91_CAST(AT91_REG *) 0xFFFD0018) // (US3) Receiver Holding Register\r
+#define AT91C_US3_IMR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (US3) Interrupt Mask Register\r
+#define AT91C_US3_CSR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (US3) Channel Status Register\r
+// ========== Register definition for PDC_US4 peripheral ========== \r
+#define AT91C_US4_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_US4) Transmit Next Counter Register\r
+#define AT91C_US4_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_US4) Receive Pointer Register\r
+#define AT91C_US4_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_US4) Receive Next Counter Register\r
+#define AT91C_US4_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_US4) Transmit Pointer Register\r
+#define AT91C_US4_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_US4) PDC Transfer Control Register\r
+#define AT91C_US4_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_US4) Transmit Counter Register\r
+#define AT91C_US4_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_US4) Receive Counter Register\r
+#define AT91C_US4_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_US4) Receive Next Pointer Register\r
+#define AT91C_US4_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_US4) Transmit Next Pointer Register\r
+#define AT91C_US4_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_US4) PDC Transfer Status Register\r
+// ========== Register definition for US4 peripheral ========== \r
+#define AT91C_US4_BRGR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (US4) Baud Rate Generator Register\r
+#define AT91C_US4_THR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (US4) Transmitter Holding Register\r
+#define AT91C_US4_RTOR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (US4) Receiver Time-out Register\r
+#define AT91C_US4_IMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (US4) Interrupt Mask Register\r
+#define AT91C_US4_NER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (US4) Nb Errors Register\r
+#define AT91C_US4_TTGR (AT91_CAST(AT91_REG *) 0xFFFD4028) // (US4) Transmitter Time-guard Register\r
+#define AT91C_US4_FIDI (AT91_CAST(AT91_REG *) 0xFFFD4040) // (US4) FI_DI_Ratio Register\r
+#define AT91C_US4_MR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (US4) Mode Register\r
+#define AT91C_US4_IER (AT91_CAST(AT91_REG *) 0xFFFD4008) // (US4) Interrupt Enable Register\r
+#define AT91C_US4_RHR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (US4) Receiver Holding Register\r
+#define AT91C_US4_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (US4) Control Register\r
+#define AT91C_US4_IF (AT91_CAST(AT91_REG *) 0xFFFD404C) // (US4) IRDA_FILTER Register\r
+#define AT91C_US4_IDR (AT91_CAST(AT91_REG *) 0xFFFD400C) // (US4) Interrupt Disable Register\r
+#define AT91C_US4_CSR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (US4) Channel Status Register\r
+// ========== Register definition for PDC_SSC0 peripheral ========== \r
+#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 0xFFFBC118) // (PDC_SSC0) Transmit Next Pointer Register\r
+#define AT91C_SSC0_TCR (AT91_CAST(AT91_REG *) 0xFFFBC10C) // (PDC_SSC0) Transmit Counter Register\r
+#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 0xFFFBC114) // (PDC_SSC0) Receive Next Counter Register\r
+#define AT91C_SSC0_RPR (AT91_CAST(AT91_REG *) 0xFFFBC100) // (PDC_SSC0) Receive Pointer Register\r
+#define AT91C_SSC0_TPR (AT91_CAST(AT91_REG *) 0xFFFBC108) // (PDC_SSC0) Transmit Pointer Register\r
+#define AT91C_SSC0_RCR (AT91_CAST(AT91_REG *) 0xFFFBC104) // (PDC_SSC0) Receive Counter Register\r
+#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 0xFFFBC110) // (PDC_SSC0) Receive Next Pointer Register\r
+#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 0xFFFBC120) // (PDC_SSC0) PDC Transfer Control Register\r
+#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 0xFFFBC11C) // (PDC_SSC0) Transmit Next Counter Register\r
+#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 0xFFFBC124) // (PDC_SSC0) PDC Transfer Status Register\r
+// ========== Register definition for SSC0 peripheral ========== \r
+#define AT91C_SSC0_IMR (AT91_CAST(AT91_REG *) 0xFFFBC04C) // (SSC0) Interrupt Mask Register\r
+#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 0xFFFBC014) // (SSC0) Receive Frame Mode Register\r
+#define AT91C_SSC0_CR (AT91_CAST(AT91_REG *) 0xFFFBC000) // (SSC0) Control Register\r
+#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 0xFFFBC01C) // (SSC0) Transmit Frame Mode Register\r
+#define AT91C_SSC0_CMR (AT91_CAST(AT91_REG *) 0xFFFBC004) // (SSC0) Clock Mode Register\r
+#define AT91C_SSC0_IER (AT91_CAST(AT91_REG *) 0xFFFBC044) // (SSC0) Interrupt Enable Register\r
+#define AT91C_SSC0_RHR (AT91_CAST(AT91_REG *) 0xFFFBC020) // (SSC0) Receive Holding Register\r
+#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 0xFFFBC010) // (SSC0) Receive Clock ModeRegister\r
+#define AT91C_SSC0_SR (AT91_CAST(AT91_REG *) 0xFFFBC040) // (SSC0) Status Register\r
+#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 0xFFFBC030) // (SSC0) Receive Sync Holding Register\r
+#define AT91C_SSC0_THR (AT91_CAST(AT91_REG *) 0xFFFBC024) // (SSC0) Transmit Holding Register\r
+#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 0xFFFBC018) // (SSC0) Transmit Clock Mode Register\r
+#define AT91C_SSC0_IDR (AT91_CAST(AT91_REG *) 0xFFFBC048) // (SSC0) Interrupt Disable Register\r
+#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 0xFFFBC034) // (SSC0) Transmit Sync Holding Register\r
+// ========== Register definition for PDC_SPI0 peripheral ========== \r
+#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC8120) // (PDC_SPI0) PDC Transfer Control Register\r
+#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFC810C) // (PDC_SPI0) Transmit Counter Register\r
+#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFC8100) // (PDC_SPI0) Receive Pointer Register\r
+#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFC8108) // (PDC_SPI0) Transmit Pointer Register\r
+#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC8124) // (PDC_SPI0) PDC Transfer Status Register\r
+#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC8114) // (PDC_SPI0) Receive Next Counter Register\r
+#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC8118) // (PDC_SPI0) Transmit Next Pointer Register\r
+#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFC8104) // (PDC_SPI0) Receive Counter Register\r
+#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC8110) // (PDC_SPI0) Receive Next Pointer Register\r
+#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC811C) // (PDC_SPI0) Transmit Next Counter Register\r
+// ========== Register definition for SPI0 peripheral ========== \r
+#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFC8018) // (SPI0) Interrupt Disable Register\r
+#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFC800C) // (SPI0) Transmit Data Register\r
+#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFC8010) // (SPI0) Status Register\r
+#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFC8000) // (SPI0) Control Register\r
+#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFC8030) // (SPI0) Chip Select Register\r
+#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFC8008) // (SPI0) Receive Data Register\r
+#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFC8004) // (SPI0) Mode Register\r
+#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFC8014) // (SPI0) Interrupt Enable Register\r
+#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFC801C) // (SPI0) Interrupt Mask Register\r
+// ========== Register definition for PDC_SPI1 peripheral ========== \r
+#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFCC120) // (PDC_SPI1) PDC Transfer Control Register\r
+#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFCC110) // (PDC_SPI1) Receive Next Pointer Register\r
+#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFCC104) // (PDC_SPI1) Receive Counter Register\r
+#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFCC108) // (PDC_SPI1) Transmit Pointer Register\r
+#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFCC124) // (PDC_SPI1) PDC Transfer Status Register\r
+#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFCC11C) // (PDC_SPI1) Transmit Next Counter Register\r
+#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFCC100) // (PDC_SPI1) Receive Pointer Register\r
+#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFCC10C) // (PDC_SPI1) Transmit Counter Register\r
+#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFCC114) // (PDC_SPI1) Receive Next Counter Register\r
+#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFCC118) // (PDC_SPI1) Transmit Next Pointer Register\r
+// ========== Register definition for SPI1 peripheral ========== \r
+#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFCC014) // (SPI1) Interrupt Enable Register\r
+#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFCC008) // (SPI1) Receive Data Register\r
+#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFCC010) // (SPI1) Status Register\r
+#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (SPI1) Interrupt Mask Register\r
+#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (SPI1) Transmit Data Register\r
+#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (SPI1) Interrupt Disable Register\r
+#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFCC030) // (SPI1) Chip Select Register\r
+#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (SPI1) Control Register\r
+#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFCC004) // (SPI1) Mode Register\r
+// ========== Register definition for PDC_ADC peripheral ========== \r
+#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_ADC) PDC Transfer Control Register\r
+#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_ADC) Transmit Pointer Register\r
+#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_ADC) Transmit Counter Register\r
+#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_ADC) Receive Counter Register\r
+#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_ADC) PDC Transfer Status Register\r
+#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_ADC) Receive Next Pointer Register\r
+#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_ADC) Receive Pointer Register\r
+#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_ADC) Transmit Next Counter Register\r
+#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_ADC) Receive Next Counter Register\r
+#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_ADC) Transmit Next Pointer Register\r
+// ========== Register definition for ADC peripheral ========== \r
+#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFE0014) // (ADC) ADC Channel Disable Register\r
+#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFE003C) // (ADC) ADC Channel Data Register 3\r
+#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (ADC) ADC Control Register\r
+#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFE002C) // (ADC) ADC Interrupt Mask Register\r
+#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFE0038) // (ADC) ADC Channel Data Register 2\r
+#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (ADC) ADC Status Register\r
+#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFE0024) // (ADC) ADC Interrupt Enable Register\r
+#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFE004C) // (ADC) ADC Channel Data Register 7\r
+#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFE0030) // (ADC) ADC Channel Data Register 0\r
+#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFE0044) // (ADC) ADC Channel Data Register 5\r
+#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFE0040) // (ADC) ADC Channel Data Register 4\r
+#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFE0010) // (ADC) ADC Channel Enable Register\r
+#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (ADC) ADC Channel Status Register\r
+#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (ADC) ADC Mode Register\r
+#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFE0048) // (ADC) ADC Channel Data Register 6\r
+#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFE0020) // (ADC) ADC Last Converted Data Register\r
+#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFE0034) // (ADC) ADC Channel Data Register 1\r
+#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFE0028) // (ADC) ADC Interrupt Disable Register\r
+// ========== Register definition for EMACB peripheral ========== \r
+#define AT91C_EMACB_USRIO (AT91_CAST(AT91_REG *) 0xFFFC40C0) // (EMACB) USER Input/Output Register\r
+#define AT91C_EMACB_RSE (AT91_CAST(AT91_REG *) 0xFFFC4074) // (EMACB) Receive Symbol Errors Register\r
+#define AT91C_EMACB_SCF (AT91_CAST(AT91_REG *) 0xFFFC4044) // (EMACB) Single Collision Frame Register\r
+#define AT91C_EMACB_STE (AT91_CAST(AT91_REG *) 0xFFFC4084) // (EMACB) SQE Test Error Register\r
+#define AT91C_EMACB_SA1H (AT91_CAST(AT91_REG *) 0xFFFC409C) // (EMACB) Specific Address 1 Top, Last 2 bytes\r
+#define AT91C_EMACB_ROV (AT91_CAST(AT91_REG *) 0xFFFC4070) // (EMACB) Receive Overrun Errors Register\r
+#define AT91C_EMACB_TBQP (AT91_CAST(AT91_REG *) 0xFFFC401C) // (EMACB) Transmit Buffer Queue Pointer\r
+#define AT91C_EMACB_IMR (AT91_CAST(AT91_REG *) 0xFFFC4030) // (EMACB) Interrupt Mask Register\r
+#define AT91C_EMACB_IER (AT91_CAST(AT91_REG *) 0xFFFC4028) // (EMACB) Interrupt Enable Register\r
+#define AT91C_EMACB_REV (AT91_CAST(AT91_REG *) 0xFFFC40FC) // (EMACB) Revision Register\r
+#define AT91C_EMACB_SA3L (AT91_CAST(AT91_REG *) 0xFFFC40A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes\r
+#define AT91C_EMACB_ELE (AT91_CAST(AT91_REG *) 0xFFFC4078) // (EMACB) Excessive Length Errors Register\r
+#define AT91C_EMACB_HRT (AT91_CAST(AT91_REG *) 0xFFFC4094) // (EMACB) Hash Address Top[63:32]\r
+#define AT91C_EMACB_SA2L (AT91_CAST(AT91_REG *) 0xFFFC40A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes\r
+#define AT91C_EMACB_RRE (AT91_CAST(AT91_REG *) 0xFFFC406C) // (EMACB) Receive Ressource Error Register\r
+#define AT91C_EMACB_FRO (AT91_CAST(AT91_REG *) 0xFFFC404C) // (EMACB) Frames Received OK Register\r
+#define AT91C_EMACB_TPQ (AT91_CAST(AT91_REG *) 0xFFFC40BC) // (EMACB) Transmit Pause Quantum Register\r
+#define AT91C_EMACB_ISR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (EMACB) Interrupt Status Register\r
+#define AT91C_EMACB_TSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (EMACB) Transmit Status Register\r
+#define AT91C_EMACB_RLE (AT91_CAST(AT91_REG *) 0xFFFC4088) // (EMACB) Receive Length Field Mismatch Register\r
+#define AT91C_EMACB_USF (AT91_CAST(AT91_REG *) 0xFFFC4080) // (EMACB) Undersize Frames Register\r
+#define AT91C_EMACB_WOL (AT91_CAST(AT91_REG *) 0xFFFC40C4) // (EMACB) Wake On LAN Register\r
+#define AT91C_EMACB_TPF (AT91_CAST(AT91_REG *) 0xFFFC408C) // (EMACB) Transmitted Pause Frames Register\r
+#define AT91C_EMACB_PTR (AT91_CAST(AT91_REG *) 0xFFFC4038) // (EMACB) Pause Time Register\r
+#define AT91C_EMACB_TUND (AT91_CAST(AT91_REG *) 0xFFFC4064) // (EMACB) Transmit Underrun Error Register\r
+#define AT91C_EMACB_MAN (AT91_CAST(AT91_REG *) 0xFFFC4034) // (EMACB) PHY Maintenance Register\r
+#define AT91C_EMACB_RJA (AT91_CAST(AT91_REG *) 0xFFFC407C) // (EMACB) Receive Jabbers Register\r
+#define AT91C_EMACB_SA4L (AT91_CAST(AT91_REG *) 0xFFFC40B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes\r
+#define AT91C_EMACB_CSE (AT91_CAST(AT91_REG *) 0xFFFC4068) // (EMACB) Carrier Sense Error Register\r
+#define AT91C_EMACB_HRB (AT91_CAST(AT91_REG *) 0xFFFC4090) // (EMACB) Hash Address Bottom[31:0]\r
+#define AT91C_EMACB_ALE (AT91_CAST(AT91_REG *) 0xFFFC4054) // (EMACB) Alignment Error Register\r
+#define AT91C_EMACB_SA1L (AT91_CAST(AT91_REG *) 0xFFFC4098) // (EMACB) Specific Address 1 Bottom, First 4 bytes\r
+#define AT91C_EMACB_NCR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (EMACB) Network Control Register\r
+#define AT91C_EMACB_FTO (AT91_CAST(AT91_REG *) 0xFFFC4040) // (EMACB) Frames Transmitted OK Register\r
+#define AT91C_EMACB_ECOL (AT91_CAST(AT91_REG *) 0xFFFC4060) // (EMACB) Excessive Collision Register\r
+#define AT91C_EMACB_DTF (AT91_CAST(AT91_REG *) 0xFFFC4058) // (EMACB) Deferred Transmission Frame Register\r
+#define AT91C_EMACB_SA4H (AT91_CAST(AT91_REG *) 0xFFFC40B4) // (EMACB) Specific Address 4 Top, Last 2 bytes\r
+#define AT91C_EMACB_FCSE (AT91_CAST(AT91_REG *) 0xFFFC4050) // (EMACB) Frame Check Sequence Error Register\r
+#define AT91C_EMACB_TID (AT91_CAST(AT91_REG *) 0xFFFC40B8) // (EMACB) Type ID Checking Register\r
+#define AT91C_EMACB_PFR (AT91_CAST(AT91_REG *) 0xFFFC403C) // (EMACB) Pause Frames received Register\r
+#define AT91C_EMACB_IDR (AT91_CAST(AT91_REG *) 0xFFFC402C) // (EMACB) Interrupt Disable Register\r
+#define AT91C_EMACB_SA3H (AT91_CAST(AT91_REG *) 0xFFFC40AC) // (EMACB) Specific Address 3 Top, Last 2 bytes\r
+#define AT91C_EMACB_NSR (AT91_CAST(AT91_REG *) 0xFFFC4008) // (EMACB) Network Status Register\r
+#define AT91C_EMACB_MCF (AT91_CAST(AT91_REG *) 0xFFFC4048) // (EMACB) Multiple Collision Frame Register\r
+#define AT91C_EMACB_RBQP (AT91_CAST(AT91_REG *) 0xFFFC4018) // (EMACB) Receive Buffer Queue Pointer\r
+#define AT91C_EMACB_RSR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (EMACB) Receive Status Register\r
+#define AT91C_EMACB_SA2H (AT91_CAST(AT91_REG *) 0xFFFC40A4) // (EMACB) Specific Address 2 Top, Last 2 bytes\r
+#define AT91C_EMACB_NCFGR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (EMACB) Network Configuration Register\r
+#define AT91C_EMACB_LCOL (AT91_CAST(AT91_REG *) 0xFFFC405C) // (EMACB) Late Collision Register\r
+// ========== Register definition for UDP peripheral ========== \r
+#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFA4004) // (UDP) Global State Register\r
+#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFA4050) // (UDP) Endpoint FIFO Data Register\r
+#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFA4028) // (UDP) Reset Endpoint Register\r
+#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFA4008) // (UDP) Function Address Register\r
+#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFA4000) // (UDP) Frame Number Register\r
+#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFA4014) // (UDP) Interrupt Disable Register\r
+#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFA4018) // (UDP) Interrupt Mask Register\r
+#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFA4030) // (UDP) Endpoint Control and Status Register\r
+#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFA4010) // (UDP) Interrupt Enable Register\r
+#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFA4020) // (UDP) Interrupt Clear Register\r
+#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFA4074) // (UDP) Transceiver Control Register\r
+#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFA401C) // (UDP) Interrupt Status Register\r
+// ========== Register definition for UHP peripheral ========== \r
+#define AT91C_UHP_HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0050000C) // (UHP) Interrupt Status Register\r
+#define AT91C_UHP_HcCommandStatus (AT91_CAST(AT91_REG *) 0x00500008) // (UHP) Command & status Register\r
+#define AT91C_UHP_HcRhStatus (AT91_CAST(AT91_REG *) 0x00500050) // (UHP) Root Hub Status register\r
+#define AT91C_UHP_HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00500014) // (UHP) Interrupt Disable Register\r
+#define AT91C_UHP_HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00500040) // (UHP) Periodic Start\r
+#define AT91C_UHP_HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00500024) // (UHP) Endpoint Control and Status Register\r
+#define AT91C_UHP_HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0050001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor\r
+#define AT91C_UHP_HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00500028) // (UHP) First endpoint register of the Bulk list\r
+#define AT91C_UHP_HcRevision (AT91_CAST(AT91_REG *) 0x00500000) // (UHP) Revision\r
+#define AT91C_UHP_HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0050002C) // (UHP) Current endpoint of the Bulk list\r
+#define AT91C_UHP_HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0050004C) // (UHP) Root Hub characteristics B\r
+#define AT91C_UHP_HcControlHeadED (AT91_CAST(AT91_REG *) 0x00500020) // (UHP) First Endpoint Descriptor of the Control list\r
+#define AT91C_UHP_HcFmRemaining (AT91_CAST(AT91_REG *) 0x00500038) // (UHP) Bit time remaining in the current Frame\r
+#define AT91C_UHP_HcHCCA (AT91_CAST(AT91_REG *) 0x00500018) // (UHP) Pointer to the Host Controller Communication Area\r
+#define AT91C_UHP_HcLSThreshold (AT91_CAST(AT91_REG *) 0x00500044) // (UHP) LS Threshold\r
+#define AT91C_UHP_HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00500054) // (UHP) Root Hub Port Status Register\r
+#define AT91C_UHP_HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00500010) // (UHP) Interrupt Enable Register\r
+#define AT91C_UHP_HcFmNumber (AT91_CAST(AT91_REG *) 0x0050003C) // (UHP) Frame number\r
+#define AT91C_UHP_HcFmInterval (AT91_CAST(AT91_REG *) 0x00500034) // (UHP) Bit time between 2 consecutive SOFs\r
+#define AT91C_UHP_HcControl (AT91_CAST(AT91_REG *) 0x00500004) // (UHP) Operating modes for the Host Controller\r
+#define AT91C_UHP_HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00500030) // (UHP) Last completed transfer descriptor\r
+#define AT91C_UHP_HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00500048) // (UHP) Root Hub characteristics A\r
+// ========== Register definition for HECC peripheral ========== \r
+// ========== Register definition for HISI peripheral ========== \r
+#define AT91C_HISI_PSIZE (AT91_CAST(AT91_REG *) 0xFFFC0020) // (HISI) Preview Size Register\r
+#define AT91C_HISI_CR1 (AT91_CAST(AT91_REG *) 0xFFFC0000) // (HISI) Control Register 1\r
+#define AT91C_HISI_R2YSET1 (AT91_CAST(AT91_REG *) 0xFFFC003C) // (HISI) Color Space Conversion Register\r
+#define AT91C_HISI_CDBA (AT91_CAST(AT91_REG *) 0xFFFC002C) // (HISI) Codec Dma Address Register\r
+#define AT91C_HISI_IDR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (HISI) Interrupt Disable Register\r
+#define AT91C_HISI_R2YSET2 (AT91_CAST(AT91_REG *) 0xFFFC0040) // (HISI) Color Space Conversion Register\r
+#define AT91C_HISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0xFFFC0034) // (HISI) Color Space Conversion Register\r
+#define AT91C_HISI_PFBD (AT91_CAST(AT91_REG *) 0xFFFC0028) // (HISI) Preview Frame Buffer Address Register\r
+#define AT91C_HISI_CR2 (AT91_CAST(AT91_REG *) 0xFFFC0004) // (HISI) Control Register 2\r
+#define AT91C_HISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0xFFFC0030) // (HISI) Color Space Conversion Register\r
+#define AT91C_HISI_PDECF (AT91_CAST(AT91_REG *) 0xFFFC0024) // (HISI) Preview Decimation Factor Register\r
+#define AT91C_HISI_IMR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (HISI) Interrupt Mask Register\r
+#define AT91C_HISI_IER (AT91_CAST(AT91_REG *) 0xFFFC000C) // (HISI) Interrupt Enable Register\r
+#define AT91C_HISI_R2YSET0 (AT91_CAST(AT91_REG *) 0xFFFC0038) // (HISI) Color Space Conversion Register\r
+#define AT91C_HISI_SR (AT91_CAST(AT91_REG *) 0xFFFC0008) // (HISI) Status Register\r
+\r
+// *****************************************************************************\r
+// PIO DEFINITIONS FOR AT91SAM9XE512\r
+// *****************************************************************************\r
+#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0\r
+#define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) // SPI 0 Master In Slave\r
+#define AT91C_PA0_MCDB0 (AT91C_PIO_PA0) // Multimedia Card B Data 0\r
+#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1\r
+#define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) // SPI 0 Master Out Slave\r
+#define AT91C_PA1_MCCDB (AT91C_PIO_PA1) // Multimedia Card B Command\r
+#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10\r
+#define AT91C_PA10_MCDA2 (AT91C_PIO_PA10) // Multimedia Card A Data 2\r
+#define AT91C_PA10_ETX2_0 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 2\r
+#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11\r
+#define AT91C_PA11_MCDA3 (AT91C_PIO_PA11) // Multimedia Card A Data 3\r
+#define AT91C_PA11_ETX3_0 (AT91C_PIO_PA11) // Ethernet MAC Transmit Data 3\r
+#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12\r
+#define AT91C_PA12_ETX0 (AT91C_PIO_PA12) // Ethernet MAC Transmit Data 0\r
+#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13\r
+#define AT91C_PA13_ETX1 (AT91C_PIO_PA13) // Ethernet MAC Transmit Data 1\r
+#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14\r
+#define AT91C_PA14_ERX0 (AT91C_PIO_PA14) // Ethernet MAC Receive Data 0\r
+#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15\r
+#define AT91C_PA15_ERX1 (AT91C_PIO_PA15) // Ethernet MAC Receive Data 1\r
+#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16\r
+#define AT91C_PA16_ETXEN (AT91C_PIO_PA16) // Ethernet MAC Transmit Enable\r
+#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17\r
+#define AT91C_PA17_ERXDV (AT91C_PIO_PA17) // Ethernet MAC Receive Data Valid\r
+#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18\r
+#define AT91C_PA18_ERXER (AT91C_PIO_PA18) // Ethernet MAC Receive Error\r
+#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19\r
+#define AT91C_PA19_ETXCK (AT91C_PIO_PA19) // Ethernet MAC Transmit Clock/Reference Clock\r
+#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2\r
+#define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) // SPI 0 Serial Clock\r
+#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20\r
+#define AT91C_PA20_EMDC (AT91C_PIO_PA20) // Ethernet MAC Management Data Clock\r
+#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21\r
+#define AT91C_PA21_EMDIO (AT91C_PIO_PA21) // Ethernet MAC Management Data Input/Output\r
+#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22\r
+#define AT91C_PA22_ADTRG (AT91C_PIO_PA22) // ADC Trigger\r
+#define AT91C_PA22_ETXER (AT91C_PIO_PA22) // Ethernet MAC Transmikt Coding Error\r
+#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23\r
+#define AT91C_PA23_TWD0 (AT91C_PIO_PA23) // TWI Two-wire Serial Data 0\r
+#define AT91C_PA23_ETX2_1 (AT91C_PIO_PA23) // Ethernet MAC Transmit Data 2\r
+#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24\r
+#define AT91C_PA24_TWCK0 (AT91C_PIO_PA24) // TWI Two-wire Serial Clock 0\r
+#define AT91C_PA24_ETX3_1 (AT91C_PIO_PA24) // Ethernet MAC Transmit Data 3\r
+#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25\r
+#define AT91C_PA25_TCLK0 (AT91C_PIO_PA25) // Timer Counter 0 external clock input\r
+#define AT91C_PA25_ERX2 (AT91C_PIO_PA25) // Ethernet MAC Receive Data 2\r
+#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26\r
+#define AT91C_PA26_TIOA0 (AT91C_PIO_PA26) // Timer Counter 0 Multipurpose Timer I/O Pin A\r
+#define AT91C_PA26_ERX3 (AT91C_PIO_PA26) // Ethernet MAC Receive Data 3\r
+#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27\r
+#define AT91C_PA27_TIOA1 (AT91C_PIO_PA27) // Timer Counter 1 Multipurpose Timer I/O Pin A\r
+#define AT91C_PA27_ERXCK (AT91C_PIO_PA27) // Ethernet MAC Receive Clock\r
+#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28\r
+#define AT91C_PA28_TIOA2 (AT91C_PIO_PA28) // Timer Counter 2 Multipurpose Timer I/O Pin A\r
+#define AT91C_PA28_ECRS (AT91C_PIO_PA28) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\r
+#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29\r
+#define AT91C_PA29_SCK1 (AT91C_PIO_PA29) // USART 1 Serial Clock\r
+#define AT91C_PA29_ECOL (AT91C_PIO_PA29) // Ethernet MAC Collision Detected\r
+#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3\r
+#define AT91C_PA3_SPI0_NPCS0 (AT91C_PIO_PA3) // SPI 0 Peripheral Chip Select 0\r
+#define AT91C_PA3_MCDB3 (AT91C_PIO_PA3) // Multimedia Card B Data 3\r
+#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30\r
+#define AT91C_PA30_SCK2 (AT91C_PIO_PA30) // USART 2 Serial Clock\r
+#define AT91C_PA30_RXD4 (AT91C_PIO_PA30) // USART 4 Receive Data\r
+#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31\r
+#define AT91C_PA31_SCK0 (AT91C_PIO_PA31) // USART 0 Serial Clock\r
+#define AT91C_PA31_TXD4 (AT91C_PIO_PA31) // USART 4 Transmit Data\r
+#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4\r
+#define AT91C_PA4_RTS2 (AT91C_PIO_PA4) // USART 2 Ready To Send\r
+#define AT91C_PA4_MCDB2 (AT91C_PIO_PA4) // Multimedia Card B Data 2\r
+#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5\r
+#define AT91C_PA5_CTS2 (AT91C_PIO_PA5) // USART 2 Clear To Send\r
+#define AT91C_PA5_MCDB1 (AT91C_PIO_PA5) // Multimedia Card B Data 1\r
+#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6\r
+#define AT91C_PA6_MCDA0 (AT91C_PIO_PA6) // Multimedia Card A Data 0\r
+#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7\r
+#define AT91C_PA7_MCCDA (AT91C_PIO_PA7) // Multimedia Card A Command\r
+#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8\r
+#define AT91C_PA8_MCCK (AT91C_PIO_PA8) // Multimedia Card Clock\r
+#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9\r
+#define AT91C_PA9_MCDA1 (AT91C_PIO_PA9) // Multimedia Card A Data 1\r
+#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0\r
+#define AT91C_PB0_SPI1_MISO (AT91C_PIO_PB0) // SPI 1 Master In Slave\r
+#define AT91C_PB0_TIOA3 (AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin A\r
+#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1\r
+#define AT91C_PB1_SPI1_MOSI (AT91C_PIO_PB1) // SPI 1 Master Out Slave\r
+#define AT91C_PB1_TIOB3 (AT91C_PIO_PB1) // Timer Counter 3 Multipurpose Timer I/O Pin B\r
+#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10\r
+#define AT91C_PB10_TXD3 (AT91C_PIO_PB10) // USART 3 Transmit Data\r
+#define AT91C_PB10_ISI_D8 (AT91C_PIO_PB10) // Image Sensor Data 8\r
+#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11\r
+#define AT91C_PB11_RXD3 (AT91C_PIO_PB11) // USART 3 Receive Data\r
+#define AT91C_PB11_ISI_D9 (AT91C_PIO_PB11) // Image Sensor Data 9\r
+#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12\r
+#define AT91C_PB12_TWD1 (AT91C_PIO_PB12) // TWI Two-wire Serial Data 1\r
+#define AT91C_PB12_ISI_D10 (AT91C_PIO_PB12) // Image Sensor Data 10\r
+#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13\r
+#define AT91C_PB13_TWCK1 (AT91C_PIO_PB13) // TWI Two-wire Serial Clock 1\r
+#define AT91C_PB13_ISI_D11 (AT91C_PIO_PB13) // Image Sensor Data 11\r
+#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14\r
+#define AT91C_PB14_DRXD (AT91C_PIO_PB14) // DBGU Debug Receive Data\r
+#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15\r
+#define AT91C_PB15_DTXD (AT91C_PIO_PB15) // DBGU Debug Transmit Data\r
+#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16\r
+#define AT91C_PB16_TK0 (AT91C_PIO_PB16) // SSC0 Transmit Clock\r
+#define AT91C_PB16_TCLK3 (AT91C_PIO_PB16) // Timer Counter 3 external clock input\r
+#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17\r
+#define AT91C_PB17_TF0 (AT91C_PIO_PB17) // SSC0 Transmit Frame Sync\r
+#define AT91C_PB17_TCLK4 (AT91C_PIO_PB17) // Timer Counter 4 external clock input\r
+#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18\r
+#define AT91C_PB18_TD0 (AT91C_PIO_PB18) // SSC0 Transmit data\r
+#define AT91C_PB18_TIOB4 (AT91C_PIO_PB18) // Timer Counter 4 Multipurpose Timer I/O Pin B\r
+#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19\r
+#define AT91C_PB19_RD0 (AT91C_PIO_PB19) // SSC0 Receive Data\r
+#define AT91C_PB19_TIOB5 (AT91C_PIO_PB19) // Timer Counter 5 Multipurpose Timer I/O Pin B\r
+#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2\r
+#define AT91C_PB2_SPI1_SPCK (AT91C_PIO_PB2) // SPI 1 Serial Clock\r
+#define AT91C_PB2_TIOA4 (AT91C_PIO_PB2) // Timer Counter 4 Multipurpose Timer I/O Pin A\r
+#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20\r
+#define AT91C_PB20_RK0 (AT91C_PIO_PB20) // SSC0 Receive Clock\r
+#define AT91C_PB20_ISI_D0 (AT91C_PIO_PB20) // Image Sensor Data 0\r
+#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21\r
+#define AT91C_PB21_RF0 (AT91C_PIO_PB21) // SSC0 Receive Frame Sync\r
+#define AT91C_PB21_ISI_D1 (AT91C_PIO_PB21) // Image Sensor Data 1\r
+#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22\r
+#define AT91C_PB22_DSR0 (AT91C_PIO_PB22) // USART 0 Data Set ready\r
+#define AT91C_PB22_ISI_D2 (AT91C_PIO_PB22) // Image Sensor Data 2\r
+#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23\r
+#define AT91C_PB23_DCD0 (AT91C_PIO_PB23) // USART 0 Data Carrier Detect\r
+#define AT91C_PB23_ISI_D3 (AT91C_PIO_PB23) // Image Sensor Data 3\r
+#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24\r
+#define AT91C_PB24_DTR0 (AT91C_PIO_PB24) // USART 0 Data Terminal ready\r
+#define AT91C_PB24_ISI_D4 (AT91C_PIO_PB24) // Image Sensor Data 4\r
+#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25\r
+#define AT91C_PB25_RI0 (AT91C_PIO_PB25) // USART 0 Ring Indicator\r
+#define AT91C_PB25_ISI_D5 (AT91C_PIO_PB25) // Image Sensor Data 5\r
+#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26\r
+#define AT91C_PB26_RTS0 (AT91C_PIO_PB26) // USART 0 Ready To Send\r
+#define AT91C_PB26_ISI_D6 (AT91C_PIO_PB26) // Image Sensor Data 6\r
+#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27\r
+#define AT91C_PB27_CTS0 (AT91C_PIO_PB27) // USART 0 Clear To Send\r
+#define AT91C_PB27_ISI_D7 (AT91C_PIO_PB27) // Image Sensor Data 7\r
+#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28\r
+#define AT91C_PB28_RTS1 (AT91C_PIO_PB28) // USART 1 Ready To Send\r
+#define AT91C_PB28_ISI_PCK (AT91C_PIO_PB28) // Image Sensor Data Clock\r
+#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29\r
+#define AT91C_PB29_CTS1 (AT91C_PIO_PB29) // USART 1 Clear To Send\r
+#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) // Image Sensor Vertical Synchro\r
+#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3\r
+#define AT91C_PB3_SPI1_NPCS0 (AT91C_PIO_PB3) // SPI 1 Peripheral Chip Select 0\r
+#define AT91C_PB3_TIOA5 (AT91C_PIO_PB3) // Timer Counter 5 Multipurpose Timer I/O Pin A\r
+#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30\r
+#define AT91C_PB30_PCK0_0 (AT91C_PIO_PB30) // PMC Programmable Clock Output 0\r
+#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) // Image Sensor Horizontal Synchro\r
+#define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31\r
+#define AT91C_PB31_PCK1_0 (AT91C_PIO_PB31) // PMC Programmable Clock Output 1\r
+#define AT91C_PB31_ISI_MCK (AT91C_PIO_PB31) // Image Sensor Reference Clock\r
+#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4\r
+#define AT91C_PB4_TXD0 (AT91C_PIO_PB4) // USART 0 Transmit Data\r
+#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5\r
+#define AT91C_PB5_RXD0 (AT91C_PIO_PB5) // USART 0 Receive Data\r
+#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6\r
+#define AT91C_PB6_TXD1 (AT91C_PIO_PB6) // USART 1 Transmit Data\r
+#define AT91C_PB6_TCLK1 (AT91C_PIO_PB6) // Timer Counter 1 external clock input\r
+#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7\r
+#define AT91C_PB7_RXD1 (AT91C_PIO_PB7) // USART 1 Receive Data\r
+#define AT91C_PB7_TCLK2 (AT91C_PIO_PB7) // Timer Counter 2 external clock input\r
+#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8\r
+#define AT91C_PB8_TXD2 (AT91C_PIO_PB8) // USART 2 Transmit Data\r
+#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9\r
+#define AT91C_PB9_RXD2 (AT91C_PIO_PB9) // USART 2 Receive Data\r
+#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0\r
+#define AT91C_PC0_AD0 (AT91C_PIO_PC0) // ADC Analog Input 0\r
+#define AT91C_PC0_SCK3 (AT91C_PIO_PC0) // USART 3 Serial Clock\r
+#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1\r
+#define AT91C_PC1_AD1 (AT91C_PIO_PC1) // ADC Analog Input 1\r
+#define AT91C_PC1_PCK0 (AT91C_PIO_PC1) // PMC Programmable Clock Output 0\r
+#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10\r
+#define AT91C_PC10_A25_CFRNW (AT91C_PIO_PC10) // Address Bus[25]\r
+#define AT91C_PC10_CTS3 (AT91C_PIO_PC10) // USART 3 Clear To Send\r
+#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11\r
+#define AT91C_PC11_NCS2 (AT91C_PIO_PC11) // Chip Select Line 2\r
+#define AT91C_PC11_SPI0_NPCS1 (AT91C_PIO_PC11) // SPI 0 Peripheral Chip Select 1\r
+#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12\r
+#define AT91C_PC12_IRQ0 (AT91C_PIO_PC12) // External Interrupt 0\r
+#define AT91C_PC12_NCS7 (AT91C_PIO_PC12) // Chip Select Line 7\r
+#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13\r
+#define AT91C_PC13_FIQ (AT91C_PIO_PC13) // AIC Fast Interrupt Input\r
+#define AT91C_PC13_NCS6 (AT91C_PIO_PC13) // Chip Select Line 6\r
+#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14\r
+#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) // Chip Select Line 3\r
+#define AT91C_PC14_IRQ2 (AT91C_PIO_PC14) // External Interrupt 2\r
+#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15\r
+#define AT91C_PC15_NWAIT (AT91C_PIO_PC15) // External Wait Signal\r
+#define AT91C_PC15_IRQ1 (AT91C_PIO_PC15) // External Interrupt 1\r
+#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16\r
+#define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus[16]\r
+#define AT91C_PC16_SPI0_NPCS2 (AT91C_PIO_PC16) // SPI 0 Peripheral Chip Select 2\r
+#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17\r
+#define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus[17]\r
+#define AT91C_PC17_SPI0_NPCS3 (AT91C_PIO_PC17) // SPI 0 Peripheral Chip Select 3\r
+#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18\r
+#define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus[18]\r
+#define AT91C_PC18_SPI1_NPCS1_1 (AT91C_PIO_PC18) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19\r
+#define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus[19]\r
+#define AT91C_PC19_SPI1_NPCS2_1 (AT91C_PIO_PC19) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2\r
+#define AT91C_PC2_AD2 (AT91C_PIO_PC2) // ADC Analog Input 2\r
+#define AT91C_PC2_PCK1 (AT91C_PIO_PC2) // PMC Programmable Clock Output 1\r
+#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20\r
+#define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus[20]\r
+#define AT91C_PC20_SPI1_NPCS3_1 (AT91C_PIO_PC20) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21\r
+#define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus[21]\r
+#define AT91C_PC21_EF100 (AT91C_PIO_PC21) // Ethernet MAC Force 100 Mbits/sec\r
+#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22\r
+#define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus[22]\r
+#define AT91C_PC22_TCLK5 (AT91C_PIO_PC22) // Timer Counter 5 external clock input\r
+#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23\r
+#define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus[23]\r
+#define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24\r
+#define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus[24]\r
+#define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25\r
+#define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus[25]\r
+#define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26\r
+#define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus[26]\r
+#define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27\r
+#define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus[27]\r
+#define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28\r
+#define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus[28]\r
+#define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29\r
+#define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus[29]\r
+#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3\r
+#define AT91C_PC3_AD3 (AT91C_PIO_PC3) // ADC Analog Input 3\r
+#define AT91C_PC3_SPI1_NPCS3_0 (AT91C_PIO_PC3) // SPI 1 Peripheral Chip Select 3\r
+#define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30\r
+#define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus[30]\r
+#define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31\r
+#define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus[31]\r
+#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4\r
+#define AT91C_PC4_A23 (AT91C_PIO_PC4) // Address Bus[23]\r
+#define AT91C_PC4_SPI1_NPCS2_0 (AT91C_PIO_PC4) // SPI 1 Peripheral Chip Select 2\r
+#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5\r
+#define AT91C_PC5_A24 (AT91C_PIO_PC5) // Address Bus[24]\r
+#define AT91C_PC5_SPI1_NPCS1_0 (AT91C_PIO_PC5) // SPI 1 Peripheral Chip Select 1\r
+#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6\r
+#define AT91C_PC6_TIOB2 (AT91C_PIO_PC6) // Timer Counter 2 Multipurpose Timer I/O Pin B\r
+#define AT91C_PC6_CFCE1 (AT91C_PIO_PC6) // Compact Flash Enable 1\r
+#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7\r
+#define AT91C_PC7_TIOB1 (AT91C_PIO_PC7) // Timer Counter 1 Multipurpose Timer I/O Pin B\r
+#define AT91C_PC7_CFCE2 (AT91C_PIO_PC7) // Compact Flash Enable 2\r
+#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8\r
+#define AT91C_PC8_NCS4_CFCS0 (AT91C_PIO_PC8) // Chip Select Line 4\r
+#define AT91C_PC8_RTS3 (AT91C_PIO_PC8) // USART 3 Ready To Send\r
+#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9\r
+#define AT91C_PC9_NCS5_CFCS1 (AT91C_PIO_PC9) // Chip Select Line 5\r
+#define AT91C_PC9_TIOB0 (AT91C_PIO_PC9) // Timer Counter 0 Multipurpose Timer I/O Pin B\r
+\r
+// *****************************************************************************\r
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM9XE512\r
+// *****************************************************************************\r
+#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)\r
+#define AT91C_ID_SYS ( 1) // System Controller\r
+#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A\r
+#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B\r
+#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C\r
+#define AT91C_ID_ADC ( 5) // ADC\r
+#define AT91C_ID_US0 ( 6) // USART 0\r
+#define AT91C_ID_US1 ( 7) // USART 1\r
+#define AT91C_ID_US2 ( 8) // USART 2\r
+#define AT91C_ID_MCI ( 9) // Multimedia Card Interface 0\r
+#define AT91C_ID_UDP (10) // USB Device Port\r
+#define AT91C_ID_TWI0 (11) // Two-Wire Interface 0\r
+#define AT91C_ID_SPI0 (12) // Serial Peripheral Interface 0\r
+#define AT91C_ID_SPI1 (13) // Serial Peripheral Interface 1\r
+#define AT91C_ID_SSC0 (14) // Serial Synchronous Controller 0\r
+#define AT91C_ID_TC0 (17) // Timer Counter 0\r
+#define AT91C_ID_TC1 (18) // Timer Counter 1\r
+#define AT91C_ID_TC2 (19) // Timer Counter 2\r
+#define AT91C_ID_UHP (20) // USB Host Port\r
+#define AT91C_ID_EMAC (21) // Ethernet Mac\r
+#define AT91C_ID_HISI (22) // Image Sensor Interface\r
+#define AT91C_ID_US3 (23) // USART 3\r
+#define AT91C_ID_US4 (24) // USART 4\r
+#define AT91C_ID_TWI1 (25) // Two-Wire Interface 1\r
+#define AT91C_ID_TC3 (26) // Timer Counter 3\r
+#define AT91C_ID_TC4 (27) // Timer Counter 4\r
+#define AT91C_ID_TC5 (28) // Timer Counter 5\r
+#define AT91C_ID_IRQ0 (29) // Advanced Interrupt Controller (IRQ0)\r
+#define AT91C_ID_IRQ1 (30) // Advanced Interrupt Controller (IRQ1)\r
+#define AT91C_ID_IRQ2 (31) // Advanced Interrupt Controller (IRQ2)\r
+#define AT91C_ALL_INT (0xFFFE7FFF) // ALL VALID INTERRUPTS\r
+\r
+// *****************************************************************************\r
+// BASE ADDRESS DEFINITIONS FOR AT91SAM9XE512\r
+// *****************************************************************************\r
+#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFFD00) // (SYS) Base Address\r
+#define AT91C_BASE_EBI (AT91_CAST(AT91PS_EBI) 0xFFFFEA00) // (EBI) Base Address\r
+#define AT91C_BASE_HECC (AT91_CAST(AT91PS_ECC) 0xFFFFE800) // (HECC) Base Address\r
+#define AT91C_BASE_SDRAMC (AT91_CAST(AT91PS_SDRAMC) 0xFFFFEA00) // (SDRAMC) Base Address\r
+#define AT91C_BASE_SMC (AT91_CAST(AT91PS_SMC) 0xFFFFEC00) // (SMC) Base Address\r
+#define AT91C_BASE_MATRIX (AT91_CAST(AT91PS_MATRIX) 0xFFFFEE00) // (MATRIX) Base Address\r
+#define AT91C_BASE_CCFG (AT91_CAST(AT91PS_CCFG) 0xFFFFEF10) // (CCFG) Base Address\r
+#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address\r
+#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address\r
+#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address\r
+#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address\r
+#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address\r
+#define AT91C_BASE_PIOC (AT91_CAST(AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address\r
+#define AT91C_BASE_EFC (AT91_CAST(AT91PS_EFC) 0xFFFFFA00) // (EFC) Base Address\r
+#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address\r
+#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address\r
+#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address\r
+#define AT91C_BASE_SHDWC (AT91_CAST(AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address\r
+#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address\r
+#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address\r
+#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address\r
+#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address\r
+#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address\r
+#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address\r
+#define AT91C_BASE_TC3 (AT91_CAST(AT91PS_TC) 0xFFFDC000) // (TC3) Base Address\r
+#define AT91C_BASE_TC4 (AT91_CAST(AT91PS_TC) 0xFFFDC040) // (TC4) Base Address\r
+#define AT91C_BASE_TC5 (AT91_CAST(AT91PS_TC) 0xFFFDC080) // (TC5) Base Address\r
+#define AT91C_BASE_TCB0 (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address\r
+#define AT91C_BASE_TCB1 (AT91_CAST(AT91PS_TCB) 0xFFFDC000) // (TCB1) Base Address\r
+#define AT91C_BASE_PDC_MCI (AT91_CAST(AT91PS_PDC) 0xFFFA8100) // (PDC_MCI) Base Address\r
+#define AT91C_BASE_MCI (AT91_CAST(AT91PS_MCI) 0xFFFA8000) // (MCI) Base Address\r
+#define AT91C_BASE_PDC_TWI0 (AT91_CAST(AT91PS_PDC) 0xFFFAC100) // (PDC_TWI0) Base Address\r
+#define AT91C_BASE_TWI0 (AT91_CAST(AT91PS_TWI) 0xFFFAC000) // (TWI0) Base Address\r
+#define AT91C_BASE_PDC_TWI1 (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_TWI1) Base Address\r
+#define AT91C_BASE_TWI1 (AT91_CAST(AT91PS_TWI) 0xFFFD8000) // (TWI1) Base Address\r
+#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFB0100) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFB0000) // (US0) Base Address\r
+#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFB4100) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFB4000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US2 (AT91_CAST(AT91PS_PDC) 0xFFFB8100) // (PDC_US2) Base Address\r
+#define AT91C_BASE_US2 (AT91_CAST(AT91PS_USART) 0xFFFB8000) // (US2) Base Address\r
+#define AT91C_BASE_PDC_US3 (AT91_CAST(AT91PS_PDC) 0xFFFD0100) // (PDC_US3) Base Address\r
+#define AT91C_BASE_US3 (AT91_CAST(AT91PS_USART) 0xFFFD0000) // (US3) Base Address\r
+#define AT91C_BASE_PDC_US4 (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_US4) Base Address\r
+#define AT91C_BASE_US4 (AT91_CAST(AT91PS_USART) 0xFFFD4000) // (US4) Base Address\r
+#define AT91C_BASE_PDC_SSC0 (AT91_CAST(AT91PS_PDC) 0xFFFBC100) // (PDC_SSC0) Base Address\r
+#define AT91C_BASE_SSC0 (AT91_CAST(AT91PS_SSC) 0xFFFBC000) // (SSC0) Base Address\r
+#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFC8100) // (PDC_SPI0) Base Address\r
+#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFC8000) // (SPI0) Base Address\r
+#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFCC100) // (PDC_SPI1) Base Address\r
+#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFCC000) // (SPI1) Base Address\r
+#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_ADC) Base Address\r
+#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFE0000) // (ADC) Base Address\r
+#define AT91C_BASE_EMACB (AT91_CAST(AT91PS_EMAC) 0xFFFC4000) // (EMACB) Base Address\r
+#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFA4000) // (UDP) Base Address\r
+#define AT91C_BASE_UHP (AT91_CAST(AT91PS_UHP) 0x00500000) // (UHP) Base Address\r
+#define AT91C_BASE_HISI (AT91_CAST(AT91PS_ISI) 0xFFFC0000) // (HISI) Base Address\r
+\r
+// *****************************************************************************\r
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM9XE512\r
+// *****************************************************************************\r
+// IROM\r
+#define AT91C_IROM (0x00100000) // Internal ROM base address\r
+#define AT91C_IROM_SIZE (0x00008000) // Internal ROM size in byte (32 Kbytes)\r
+// ISRAM\r
+#define AT91C_ISRAM (0x00300000) // Maximum IRAM Area : 32Kbyte base address\r
+#define AT91C_ISRAM_SIZE (0x00008000) // Maximum IRAM Area : 32Kbyte size in byte (32 Kbytes)\r
+// ISRAM_MIN\r
+#define AT91C_ISRAM_MIN (0x00300000) // Minimun IRAM Area : 32Kbyte base address\r
+#define AT91C_ISRAM_MIN_SIZE (0x00008000) // Minimun IRAM Area : 32Kbyte size in byte (32 Kbytes)\r
+// IFLASH\r
+#define AT91C_IFLASH (0x00200000) // Maximum IFLASH Area : 512Kbyte base address\r
+#define AT91C_IFLASH_SIZE (0x00080000) // Maximum IFLASH Area : 512Kbyte size in byte (512 Kbytes)\r
+#define AT91C_IFLASH_PAGE_SIZE (512) // Maximum IFLASH Area : 512Kbyte Page Size: 512 bytes\r
+#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Maximum IFLASH Area : 512Kbyte Lock Region Size: 16 Kbytes\r
+#define AT91C_IFLASH_NB_OF_PAGES (1024) // Maximum IFLASH Area : 512Kbyte Number of Pages: 1024 bytes\r
+#define AT91C_IFLASH_NB_OF_LOCK_BITS (32) // Maximum IFLASH Area : 512Kbyte Number of Lock Bits: 32 bytes\r
+// EBI_CS0\r
+#define AT91C_EBI_CS0 (0x10000000) // EBI Chip Select 0 base address\r
+#define AT91C_EBI_CS0_SIZE (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)\r
+// EBI_CS1\r
+#define AT91C_EBI_CS1 (0x20000000) // EBI Chip Select 1 base address\r
+#define AT91C_EBI_CS1_SIZE (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)\r
+// EBI_SDRAM\r
+#define AT91C_EBI_SDRAM (0x20000000) // SDRAM on EBI Chip Select 1 base address\r
+#define AT91C_EBI_SDRAM_SIZE (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes)\r
+// EBI_SDRAM_16BIT\r
+#define AT91C_EBI_SDRAM_16BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address\r
+#define AT91C_EBI_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes)\r
+// EBI_SDRAM_32BIT\r
+#define AT91C_EBI_SDRAM_32BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address\r
+#define AT91C_EBI_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes)\r
+// EBI_CS2\r
+#define AT91C_EBI_CS2 (0x30000000) // EBI Chip Select 2 base address\r
+#define AT91C_EBI_CS2_SIZE (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)\r
+// EBI_CS3\r
+#define AT91C_EBI_CS3 (0x40000000) // EBI Chip Select 3 base address\r
+#define AT91C_EBI_CS3_SIZE (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)\r
+// EBI_SM\r
+#define AT91C_EBI_SM (0x40000000) // SmartMedia on Chip Select 3 base address\r
+#define AT91C_EBI_SM_SIZE (0x10000000) // SmartMedia on Chip Select 3 size in byte (262144 Kbytes)\r
+// EBI_CS4\r
+#define AT91C_EBI_CS4 (0x50000000) // EBI Chip Select 4 base address\r
+#define AT91C_EBI_CS4_SIZE (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)\r
+// EBI_CF0\r
+#define AT91C_EBI_CF0 (0x50000000) // CompactFlash 0 on Chip Select 4 base address\r
+#define AT91C_EBI_CF0_SIZE (0x10000000) // CompactFlash 0 on Chip Select 4 size in byte (262144 Kbytes)\r
+// EBI_CS5\r
+#define AT91C_EBI_CS5 (0x60000000) // EBI Chip Select 5 base address\r
+#define AT91C_EBI_CS5_SIZE (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)\r
+// EBI_CF1\r
+#define AT91C_EBI_CF1 (0x60000000) // CompactFlash 1 on Chip Select 5 base address\r
+#define AT91C_EBI_CF1_SIZE (0x10000000) // CompactFlash 1 on Chip Select 5 size in byte (262144 Kbytes)\r
+// EBI_CS6\r
+#define AT91C_EBI_CS6 (0x70000000) // EBI Chip Select 6 base address\r
+#define AT91C_EBI_CS6_SIZE (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes)\r
+// EBI_CS7\r
+#define AT91C_EBI_CS7 (0x80000000) // EBI Chip Select 7 base address\r
+#define AT91C_EBI_CS7_SIZE (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes)\r
+\r
+#endif\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x200000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x27FFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x300000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_startup__ = 0x100;\r
+define symbol __ICFEDIT_size_vectors__ = 0x100;\r
+define symbol __ICFEDIT_size_cstack__ = 0x1000;\r
+define symbol __ICFEDIT_size_svcstack__ = 0x60;\r
+define symbol __ICFEDIT_size_irqstack__ = 0x60;\r
+define symbol __ICFEDIT_size_heap__ = 0x0;\r
+/*-Exports-*/\r
+export symbol __ICFEDIT_region_ROM_start__;\r
+export symbol __ICFEDIT_region_ROM_end__;\r
+export symbol __ICFEDIT_region_RAM_start__;\r
+export symbol __ICFEDIT_region_RAM_end__;\r
+export symbol __ICFEDIT_size_startup__;\r
+export symbol __ICFEDIT_size_vectors__;\r
+export symbol __ICFEDIT_size_cstack__;\r
+export symbol __ICFEDIT_size_svcstack__;\r
+export symbol __ICFEDIT_size_irqstack__;\r
+export symbol __ICFEDIT_size_heap__;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region STA_region = mem:[from __ICFEDIT_region_ROM_start__ size __ICFEDIT_size_startup__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_ROM_end__];\r
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };\r
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+initialize by copy { section .vectors };\r
+do not initialize { section .noinit };\r
+\r
+place in STA_region { section .cstartup };\r
+place in ROM_region { readonly };\r
+place in VEC_region { section .vectors };\r
+place in RAM_region { readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };\r
+\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_SDRAM_end__ = 0x21FFFFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x300000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_startup__ = 0x100;\r
+define symbol __ICFEDIT_size_vectors__ = 0x100;\r
+define symbol __ICFEDIT_size_cstack__ = 0x1000;\r
+define symbol __ICFEDIT_size_svcstack__ = 0x60;\r
+define symbol __ICFEDIT_size_irqstack__ = 0x60;\r
+define symbol __ICFEDIT_size_heap__ = 0x0;\r
+/*-Exports-*/\r
+export symbol __ICFEDIT_region_SDRAM_start__;\r
+export symbol __ICFEDIT_region_SDRAM_end__;\r
+export symbol __ICFEDIT_region_RAM_start__;\r
+export symbol __ICFEDIT_region_RAM_end__;\r
+export symbol __ICFEDIT_size_startup__;\r
+export symbol __ICFEDIT_size_vectors__;\r
+export symbol __ICFEDIT_size_cstack__;\r
+export symbol __ICFEDIT_size_svcstack__;\r
+export symbol __ICFEDIT_size_irqstack__;\r
+export symbol __ICFEDIT_size_heap__;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region STA_region = mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__];\r
+define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__];\r
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };\r
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { section .vectors };\r
+do not initialize { section .noinit };\r
+\r
+place in STA_region { section .cstartup };\r
+place in VEC_region { section .vectors };\r
+place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };\r
+\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x300000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_vectors__ = 0x100;\r
+define symbol __ICFEDIT_size_cstack__ = 0x800;\r
+define symbol __ICFEDIT_size_svcstack__ = 0x60;\r
+define symbol __ICFEDIT_size_irqstack__ = 0x60;\r
+define symbol __ICFEDIT_size_heap__ = 0x0;\r
+/*-Exports-*/\r
+export symbol __ICFEDIT_region_RAM_start__;\r
+export symbol __ICFEDIT_region_RAM_end__;\r
+export symbol __ICFEDIT_size_vectors__;\r
+export symbol __ICFEDIT_size_cstack__;\r
+export symbol __ICFEDIT_size_svcstack__;\r
+export symbol __ICFEDIT_size_irqstack__;\r
+export symbol __ICFEDIT_size_heap__;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };\r
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+do not initialize { section .noinit };\r
+\r
+place in VEC_region { section .vectors };\r
+place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \dir\r
+/// !Purpose\r
+///\r
+/// Definition and functions for using AT91SAM9XE-related features, such\r
+/// has PIO pins, memories, etc.\r
+///\r
+/// !Usage\r
+/// -# The code for booting the board is provided by board_cstartup.S and\r
+/// board_lowlevel.c.\r
+/// -# For using board PIOs, board characteristics (clock, etc.) and external\r
+/// components, see board.h.\r
+/// -# For manipulating memories (remapping, SDRAM, etc.), see board_memories.h.\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+/// !Purpose\r
+///\r
+/// Definition of AT91SAM9XE-EK characteristics, AT91SAM9XE-dependant PIOs and\r
+/// external components interfacing.\r
+///\r
+/// !Usage\r
+/// -# For operating frequency information, see "SAM9XE-EK - Operating frequencies".\r
+/// -# For using portable PIO definitions, see "SAM9XE-EK - PIO definitions".\r
+/// -# Several USB definitions are included here (see "SAM9XE-EK - USB device").\r
+/// -# For external components definitions, see "SAM79260-EK - External components".\r
+/// -# For memory-related definitions, see "SAM79260-EK - Memories".\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef BOARD_H\r
+#define BOARD_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(at91sam9xe128)\r
+ #include "at91sam9xe128/AT91SAM9XE128.h"\r
+#elif defined(at91sam9xe256)\r
+ #include "at91sam9xe256/AT91SAM9XE256.h"\r
+#elif defined(at91sam9xe512)\r
+ #include "at91sam9xe512/AT91SAM9XE512.h"\r
+#else\r
+ #error Board does not support the specified chip.\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SAM9XE-EK - Board Description"\r
+/// This page lists several definition related to the board description.\r
+///\r
+/// !Definitions\r
+/// - BOARD_NAME\r
+\r
+/// Name of the board.\r
+#define BOARD_NAME "AT91SAM9XE-EK"\r
+/// Board definition.\r
+#define at91sam9xeek\r
+/// Family definition.\r
+#define at91sam9xe\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SAM9XE-EK - Operating frequencies"\r
+/// This page lists several definition related to the board operating frequency\r
+/// (when using the initialization done by board_lowlevel.c).\r
+///\r
+/// !Definitions\r
+/// - BOARD_MAINOSC\r
+/// - BOARD_MCK\r
+\r
+/// Frequency of the board main oscillator.\r
+#define BOARD_MAINOSC 18432000\r
+\r
+/// Master clock frequency (when using board_lowlevel.c).\r
+#define BOARD_MCK ((18432000 * 97 / 9) / 2)\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SAM9XE-EK - USB device"\r
+/// This page lists constants describing several characteristics (controller\r
+/// type, D+ pull-up type, etc.) of the USB device controller of the chip/board.\r
+///\r
+/// !Constants\r
+/// - BOARD_USB_UDP\r
+/// - BOARD_USB_PULLUP_INTERNAL\r
+/// - BOARD_USB_NUMENDPOINTS\r
+/// - BOARD_USB_ENDPOINTS_MAXPACKETSIZE\r
+/// - BOARD_USB_ENDPOINTS_BANKS\r
+/// - BOARD_USB_BMATTRIBUTES\r
+\r
+/// Chip has a UDP controller.\r
+#define BOARD_USB_UDP\r
+\r
+/// Indicates the D+ pull-up is internal to the USB controller.\r
+#define BOARD_USB_PULLUP_INTERNAL\r
+\r
+/// Number of endpoints in the USB controller.\r
+#define BOARD_USB_NUMENDPOINTS 6\r
+\r
+/// Returns the maximum packet size of the given endpoint.\r
+#define BOARD_USB_ENDPOINTS_MAXPACKETSIZE(i) ((i >= 4) ? 512 : 64)\r
+#define BOARD_USB_ENDPOINTS_MAXPACKETSIZE_FS 64\r
+\r
+/// Returns the number of FIFO banks for the given endpoint.\r
+#define BOARD_USB_ENDPOINTS_BANKS(i) (((i == 0) || (i == 3)) ? 1 : 2)\r
+\r
+/// USB attributes configuration descriptor (bus or self powered, remote wakeup)\r
+#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SAM9XE-EK - PIO definitions"\r
+/// This pages lists all the pio definitions contained in board.h. The constants\r
+/// are named using the following convention: PIN_* for a constant which defines\r
+/// a single Pin instance (but may include several PIOs sharing the same\r
+/// controller), and PINS_* for a list of Pin instances.\r
+///\r
+/// !DBGU\r
+/// - PINS_DBGU\r
+///\r
+/// !LEDs\r
+/// - PIN_LED_0\r
+/// - PIN_LED_1\r
+/// - PINS_LEDS\r
+/// - LED_POWER\r
+/// - LED_DS1\r
+///\r
+/// !Push buttons\r
+/// - PIN_PUSHBUTTON_1\r
+/// - PIN_PUSHBUTTON_2\r
+/// - PINS_PUSHBUTTONS\r
+/// - PUSHBUTTON_BP1\r
+/// - PUSHBUTTON_BP2\r
+///\r
+/// !USART0\r
+/// - PIN_USART0_RXD\r
+/// - PIN_USART0_TXD\r
+/// - PIN_USART0_SCK\r
+///\r
+/// !SPI0\r
+/// - PIN_SPI0_MISO\r
+/// - PIN_SPI0_MOSI\r
+/// - PIN_SPI0_SPCK\r
+/// - PINS_SPI0\r
+/// - PIN_SPI0_NPCS0\r
+/// - PIN_SPI0_NPCS1\r
+///\r
+/// !SSC\r
+/// - PINS_SSC_TX\r
+///\r
+/// !USB\r
+/// - PIN_USB_VBUS\r
+///\r
+/// !MCI\r
+/// - PINS_MCI\r
+///\r
+/// !TWI0\r
+/// - PINS_TWI0\r
+\r
+/// List of all DBGU pin definitions.\r
+#define PINS_DBGU {(1<<14) | (1<<15), AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+/// LED #0 pin definition.\r
+#define PIN_LED_0 {1 << 9, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}\r
+/// LED #1 pin definition.\r
+#define PIN_LED_1 {1 << 6, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}\r
+/// List of all LED definitions.\r
+#define PINS_LEDS PIN_LED_0, PIN_LED_1\r
+/// Power LED index.\r
+#define LED_POWER 0\r
+/// DS1 LED index.\r
+#define LED_DS1 1\r
+\r
+/// Push button #1 pin definition.\r
+#define PIN_PUSHBUTTON_1 {1 << 30, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+/// Pusb button #2 pin definition.\r
+#define PIN_PUSHBUTTON_2 {1UL << 31, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+/// List of all pushbutton pin definitions.\r
+#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2\r
+/// Push button #1 index.\r
+#define PUSHBUTTON_BP1 0\r
+/// Push button #2 index.\r
+#define PUSHBUTTON_BP2 1\r
+\r
+/// USART0 TXD pin definition.\r
+#define PIN_USART0_TXD {1 << 4, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/// USART0 RXD pin definition.\r
+#define PIN_USART0_RXD {1 << 5, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/// USART0 RTS pin definition.\r
+#define PIN_USART0_RTS {1 << 26, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/// USART0 CTS pin definition.\r
+#define PIN_USART0_CTS {1 << 27, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/// USART0 SCK pin definition.\r
+#define PIN_USART0_SCK {1UL << 31, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+/// SPI0 MISO pin definition.\r
+#define PIN_SPI0_MISO {1 << 0, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}\r
+/// SPI0 MOSI pin definition.\r
+#define PIN_SPI0_MOSI {1 << 1, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/// SPI0 SPCK pin definition.\r
+#define PIN_SPI0_SPCK {1 << 2, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/// List of SPI0 pin definitions (MISO, MOSI & SPCK).\r
+#define PINS_SPI0 PIN_SPI0_MISO, PIN_SPI0_MOSI, PIN_SPI0_SPCK \r
+/// SPI0 chip select 0 pin definition.\r
+#define PIN_SPI0_NPCS0 {AT91C_PA3_SPI0_NPCS0, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/// SPI0 chip select 1 pin definition.\r
+#define PIN_SPI0_NPCS1 {AT91C_PC11_SPI0_NPCS1, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}\r
+\r
+/// SSC transmitter pins definition.\r
+#define PINS_SSC_TX {0x00038000, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+/// USB VBus monitoring pin definition.\r
+#define PIN_USB_VBUS {1 << 5, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+\r
+/// List of MCI pins definitions.\r
+#define PINS_MCI {0x0000003B, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}, \\r
+ {1 << 8, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+/// TWI0 pins definition.\r
+#define PINS_TWI0 {0x01800000, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SAM9XE-EK - External components"\r
+/// This page lists the definitions related to external on-board components\r
+/// located in the board.h file for the AT91SAM9XE-EK.\r
+///\r
+/// !AT45 Dataflash Card (A)\r
+/// - BOARD_AT45_A_SPI_BASE\r
+/// - BOARD_AT45_A_SPI_ID\r
+/// - BOARD_AT45_A_SPI_PINS\r
+/// - BOARD_AT45_A_SPI\r
+/// - BOARD_AT45_A_NPCS\r
+/// - BOARD_AT45_A_NPCS_PIN\r
+///\r
+/// !AT45 Dataflash (B)\r
+/// - BOARD_AT45_B_SPI_BASE\r
+/// - BOARD_AT45_B_SPI_ID\r
+/// - BOARD_AT45_B_SPI_PINS\r
+/// - BOARD_AT45_B_SPI\r
+/// - BOARD_AT45_B_NPCS\r
+/// - BOARD_AT45_B_NPCS_PIN\r
+///\r
+/// !SD Card\r
+/// - BOARD_SD_MCI_BASE\r
+/// - BOARD_SD_MCI_ID\r
+/// - BOARD_SD_PINS\r
+/// - BOARD_SD_SLOT\r
+///\r
+///\r
+/// !EMAC\r
+/// - AT91C_BASE_EMAC\r
+/// - BOARD_EMAC_POWER_ALWAYS_ON\r
+/// - BOARD_EMAC_MODE_RMII\r
+/// - BOARD_EMAC_PINS\r
+/// - BOARD_EMAC_PIN_TEST\r
+/// - BOARD_EMAC_PIN_RPTR\r
+/// - BOARD_EMAC_RST_PINS\r
+/// - BOARD_EMAC_RUN_PINS\r
+\r
+\r
+/// Base address of SPI peripheral connected to the dataflash.\r
+#define BOARD_AT45_A_SPI_BASE AT91C_BASE_SPI0\r
+/// Identifier of SPI peripheral connected to the dataflash.\r
+#define BOARD_AT45_A_SPI_ID AT91C_ID_SPI0\r
+/// Pins of the SPI peripheral connected to the dataflash.\r
+#define BOARD_AT45_A_SPI_PINS PINS_SPI0\r
+/// Dataflahs SPI number.\r
+#define BOARD_AT45_A_SPI 0\r
+/// Chip select connected to the dataflash.\r
+#define BOARD_AT45_A_NPCS 0\r
+/// Chip select pin connected to the dataflash.\r
+#define BOARD_AT45_A_NPCS_PIN PIN_SPI0_NPCS0\r
+\r
+/// Base address of SPI peripheral connected to the dataflash.\r
+#define BOARD_AT45_B_SPI_BASE AT91C_BASE_SPI0\r
+/// Identifier of SPI peripheral connected to the dataflash.\r
+#define BOARD_AT45_B_SPI_ID AT91C_ID_SPI0\r
+/// Pins of the SPI peripheral connected to the dataflash.\r
+#define BOARD_AT45_B_SPI_PINS PINS_SPI0\r
+/// Dataflahs SPI number.\r
+#define BOARD_AT45_B_SPI 0\r
+/// Chip select connected to the dataflash.\r
+#define BOARD_AT45_B_NPCS 1\r
+/// Chip select pin connected to the dataflash.\r
+#define BOARD_AT45_B_NPCS_PIN PIN_SPI0_NPCS1\r
+\r
+/// Base address of SPI peripheral connected to the serialflash.\r
+#define BOARD_AT26_A_SPI_BASE AT91C_BASE_SPI0\r
+/// Identifier of SPI peripheral connected to the dataflash.\r
+#define BOARD_AT26_A_SPI_ID AT91C_ID_SPI0\r
+/// Pins of the SPI peripheral connected to the dataflash.\r
+#define BOARD_AT26_A_SPI_PINS PINS_SPI0\r
+/// Dataflahs SPI number.\r
+#define BOARD_AT26_A_SPI 0\r
+/// Chip select connected to the dataflash.\r
+#define BOARD_AT26_A_NPCS 0\r
+/// Chip select pin connected to the dataflash.\r
+#define BOARD_AT26_A_NPCS_PIN PIN_SPI0_NPCS0\r
+\r
+/// Base address of the MCI peripheral connected to the SD card.\r
+#define BOARD_SD_MCI_BASE AT91C_BASE_MCI\r
+/// Peripheral identifier of the MCI connected to the SD card.\r
+#define BOARD_SD_MCI_ID AT91C_ID_MCI\r
+/// MCI pins that shall be configured to access the SD card.\r
+#define BOARD_SD_PINS PINS_MCI\r
+/// MCI slot to which the SD card is connected to.\r
+#define BOARD_SD_SLOT MCI_SD_SLOTB\r
+\r
+/// Board EMAC base address\r
+#if !defined(AT91C_BASE_EMAC) && defined(AT91C_BASE_EMACB)\r
+#define AT91C_BASE_EMAC AT91C_BASE_EMACB\r
+#endif\r
+/// Board EMAC power control - ALWAYS ON\r
+#define BOARD_EMAC_POWER_ALWAYS_ON\r
+/// Board EMAC work mode - RMII/MII ( 1 / 0 )\r
+#define BOARD_EMAC_MODE_RMII 1\r
+/// The PIN list of PIO for EMAC\r
+#define BOARD_EMAC_PINS { ((1<<19)|(1<<13)|(1<<12)|(1<<16)|(1<<15)|(1<<14)\\r
+ |(1<<17)|(1<<18)|(1<<20)|(1<<21)|(1<<7)),\\r
+ AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT},\\r
+ { ((1<<11)|(1<<10)|(1<<26)|(1<<25)|(1<<27)|(1<<22)\\r
+ |(1<<29)|(1<<28)),\\r
+ AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+/// The power up reset latch PIO for PHY\r
+#define BOARD_EMAC_PIN_TEST {(1<<17), AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}\r
+//#define BOARD_EMAC_PIN_RMII : connected to 3v3 (RMII)\r
+// We force the address\r
+// (1<<14) PHY address 0, (1<<15) PHY address 1 (PIO A, perih A)\r
+// (1<<25) PHY address 2, (1<<26) PHY address 3 (PIO A, perih B)\r
+#define BOARD_EMAC_PINS_PHYAD { ((1<<14)|(1<<15)),\\r
+ AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT},\\r
+ { ((1<<25)|(1<<26)),\\r
+ AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}\r
+//#define BOARD_EMAC_PIN_10BT : not connected\r
+#define BOARD_EMAC_PIN_RPTR {(1<<27), AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}\r
+/// The PIN Configure list for EMAC on power up reset\r
+#define BOARD_EMAC_RST_PINS BOARD_EMAC_PINS_PHYAD,\\r
+ BOARD_EMAC_PIN_TEST,\\r
+ BOARD_EMAC_PIN_RPTR\r
+/// The runtime pin configure list for EMAC\r
+#define BOARD_EMAC_RUN_PINS BOARD_EMAC_PINS\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SAM9XE-EK - Memories"\r
+/// This page lists definitions related to external on-board memories.\r
+///\r
+/// !Embedded Flash\r
+/// - BOARD_FLASH_EEFC\r
+///\r
+/// !SDRAM\r
+/// - BOARD_SDRAM_SIZE\r
+/// - PINS_SDRAM\r
+///\r
+/// !Nandflash\r
+/// - PINS_NANDFLASH\r
+/// - BOARD_NF_COMMAND_ADDR\r
+/// - BOARD_NF_ADDRESS_ADDR\r
+/// - BOARD_NF_DATA_ADDR\r
+/// - BOARD_NF_CE_PIN\r
+/// - BOARD_NF_RB_PIN\r
+\r
+/// Indicates chip has an Enhanced EFC.\r
+#define BOARD_FLASH_EEFC\r
+/// Address of the IAP function in ROM.\r
+#define BOARD_FLASH_IAP_ADDRESS 0x100008\r
+\r
+/// Board SDRAM size\r
+#define BOARD_SDRAM_SIZE 0x02000000\r
+/// List of all SDRAM pins definitions.\r
+#define PINS_SDRAM {0xFFFF0000, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+\r
+/// Nandflash controller peripheral pins definition.\r
+#define PINS_NANDFLASH BOARD_NF_CE_PIN, BOARD_NF_RB_PIN\r
+/// Nandflash chip enable pin definition.\r
+#define BOARD_NF_CE_PIN {1 << 14, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}\r
+/// Nandflash ready/busy pin definition.\r
+#define BOARD_NF_RB_PIN {1 << 13, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_PULLUP}\r
+/// Address for transferring command bytes to the nandflash.\r
+#define BOARD_NF_COMMAND_ADDR 0x40400000\r
+/// Address for transferring address bytes to the nandflash.\r
+#define BOARD_NF_ADDRESS_ADDR 0x40200000\r
+/// Address for transferring data bytes to the nandflash.\r
+#define BOARD_NF_DATA_ADDR 0x40000000\r
+\r
+/// Address for transferring command bytes to the norflash.\r
+#define BOARD_NORFLASH_ADDR 0x10000000\r
+//------------------------------------------------------------------------------\r
+\r
+#endif //#ifndef BOARD_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#include "ISR_Support.h"\r
+\r
+/*\r
+ IAR startup file for AT91SAM9XE microcontrollers.\r
+ */\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION IRQ_STACK:DATA:NOROOT(2)\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#define __ASSEMBLY__\r
+#include "board.h"\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+#define ARM_MODE_ABT 0x17\r
+#define ARM_MODE_FIQ 0x11\r
+#define ARM_MODE_IRQ 0x12\r
+#define ARM_MODE_SVC 0x13\r
+#define ARM_MODE_SYS 0x1F\r
+\r
+#define I_BIT 0x80\r
+#define F_BIT 0x40\r
+\r
+//------------------------------------------------------------------------------\r
+// Startup routine\r
+//------------------------------------------------------------------------------\r
+\r
+/*\r
+ Exception vectors\r
+ */\r
+ SECTION .vectors:CODE:NOROOT(2)\r
+\r
+ PUBLIC resetVector\r
+ PUBLIC irqHandler\r
+\r
+ EXTERN Undefined_Handler\r
+ EXTERN vPortYieldProcessor\r
+ EXTERN Prefetch_Handler\r
+ EXTERN Abort_Handler\r
+ EXTERN FIQ_Handler\r
+\r
+ ARM\r
+\r
+__iar_init$$done: ; The interrupt vector is not needed\r
+ ; until after copy initialization is done\r
+\r
+resetVector:\r
+ ; All default exception handlers (except reset) are\r
+ ; defined as weak symbol definitions.\r
+ ; If a handler is defined by the application it will take precedence.\r
+ LDR pc, =resetHandler ; Reset\r
+ LDR pc, Undefined_Addr ; Undefined instructions\r
+ LDR pc, SWI_Addr ; Software interrupt (SWI/SVC)\r
+ LDR pc, Prefetch_Addr ; Prefetch abort\r
+ LDR pc, Abort_Addr ; Data abort\r
+ B . ; RESERVED\r
+ LDR pc, =irqHandler ; IRQ\r
+ LDR pc, FIQ_Addr ; FIQ\r
+\r
+Undefined_Addr: DCD Undefined_Handler\r
+SWI_Addr: DCD vPortYieldProcessor\r
+Prefetch_Addr: DCD Prefetch_Handler\r
+Abort_Addr: DCD Abort_Handler\r
+FIQ_Addr: DCD FIQ_Handler\r
+ \r
+/*\r
+ Handles incoming interrupt requests by branching to the corresponding\r
+ handler, as defined in the AIC. Supports interrupt nesting.\r
+ */\r
+irqHandler:\r
+ portSAVE_CONTEXT\r
+\r
+ /* Write in the IVR to support Protect Mode */\r
+ LDR lr, =AT91C_BASE_AIC\r
+ LDR r0, [r14, #AIC_IVR]\r
+ STR lr, [r14, #AIC_IVR]\r
+\r
+ /* Branch to interrupt handler in Supervisor mode */\r
+ MSR CPSR_c, #ARM_MODE_SVC\r
+ STMFD sp!, {r1-r3, r12, lr}\r
+ MOV lr, pc\r
+ BX r0\r
+ LDMIA sp!, {r1-r3, r12, lr}\r
+ MSR CPSR_c, #ARM_MODE_IRQ | I_BIT\r
+\r
+ /* Acknowledge interrupt */\r
+ LDR lr, =AT91C_BASE_AIC\r
+ STR lr, [r14, #AIC_EOICR]\r
+\r
+ portRESTORE_CONTEXT\r
+\r
+ /* Won't progress to here. */\r
+\r
+ /* Save interrupt context on the stack to allow nesting */\r
+ SUB lr, lr, #4\r
+ STMFD sp!, {lr}\r
+ MRS lr, SPSR\r
+ STMFD sp!, {r0, lr}\r
+\r
+ /* Write in the IVR to support Protect Mode */\r
+ LDR lr, =AT91C_BASE_AIC\r
+ LDR r0, [r14, #AIC_IVR]\r
+ STR lr, [r14, #AIC_IVR]\r
+\r
+ /* Branch to interrupt handler in Supervisor mode */\r
+ MSR CPSR_c, #ARM_MODE_SVC\r
+ STMFD sp!, {r1-r3, r12, lr}\r
+ MOV lr, pc\r
+ BX r0\r
+ LDMIA sp!, {r1-r3, r12, lr}\r
+ MSR CPSR_c, #ARM_MODE_IRQ | I_BIT\r
+\r
+ /* Acknowledge interrupt */\r
+ LDR lr, =AT91C_BASE_AIC\r
+ STR lr, [r14, #AIC_EOICR]\r
+\r
+ /* Restore interrupt context and branch back to calling code */\r
+ LDMIA sp!, {r0, lr}\r
+ MSR SPSR_cxsf, lr\r
+ LDMIA sp!, {pc}^\r
+\r
+\r
+/*\r
+ After a reset, execution starts here, the mode is ARM, supervisor\r
+ with interrupts disabled.\r
+ Initializes the chip and branches to the main() function.\r
+ */\r
+ SECTION .cstartup:CODE:NOROOT(2)\r
+\r
+ PUBLIC resetHandler\r
+ EXTERN LowLevelInit\r
+ EXTERN ?main\r
+ REQUIRE resetVector\r
+ ARM\r
+\r
+resetHandler:\r
+\r
+ /* Set pc to actual code location (i.e. not in remap zone) */\r
+ LDR pc, =label\r
+\r
+ /* Perform low-level initialization of the chip using LowLevelInit() */\r
+label:\r
+ LDR r0, =LowLevelInit\r
+ LDR r4, =SFE(CSTACK)\r
+ MOV sp, r4\r
+ MOV lr, pc\r
+ BX r0\r
+\r
+ /* Set up the interrupt stack pointer. */\r
+ MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode\r
+ LDR sp, =SFE(IRQ_STACK)\r
+\r
+ /* Set up the SVC stack pointer. */\r
+ MSR cpsr_c, #ARM_MODE_SVC | F_BIT ; Change the mode\r
+ LDR sp, =SFE(CSTACK)\r
+\r
+ /* Branch to main() */\r
+ LDR r0, =?main\r
+ MOV lr, pc\r
+ BX r0\r
+\r
+ /* Loop indefinitely when program is finished */\r
+loop4:\r
+ B loop4\r
+\r
+ END\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "board.h"\r
+#include "board_memories.h"\r
+\r
+//------------------------------------------------------------------------------\r
+// Local definitions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SAM9XE - Oscillator & PLL Parameters"\r
+/// This page lists the parameters which are set for the PLL and main\r
+/// oscillator configuration.\r
+///\r
+/// !Parameters\r
+/// - BOARD_OSCOUNT\r
+/// - BOARD_CKGR_PLLA\r
+/// - BOARD_PLLACOUNT\r
+/// - BOARD_MULA\r
+/// - BOARD_DIVA\r
+/// - BOARD_CKGR_PLLB\r
+/// - BOARD_PLLBCOUNT\r
+/// - BOARD_MULB\r
+/// - BOARD_DIVB\r
+/// - BOARD_USBDIV\r
+/// - BOARD_PRESCALER\r
+\r
+/// Main oscillator startup time (in number of slow clock ticks). \r
+#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8))\r
+\r
+/// PLLA frequency range.\r
+#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_2)\r
+/// PLLA startup time (in number of slow clock ticks).\r
+#define BOARD_PLLACOUNT (63 << 8)\r
+/// PLLA MUL value.\r
+#define BOARD_MULA (AT91C_CKGR_MULA & (96 << 16))\r
+/// PLLA DIV value.\r
+#define BOARD_DIVA (AT91C_CKGR_DIVA & 9)\r
+\r
+/// PLLB frequency range\r
+#define BOARD_CKGR_PLLB AT91C_CKGR_OUTB_1\r
+/// PLLB startup time (in number of slow clock ticks).\r
+#define BOARD_PLLBCOUNT BOARD_PLLACOUNT\r
+/// PLLB MUL value.\r
+#define BOARD_MULB (124 << 16)\r
+/// PLLB DIV value.\r
+#define BOARD_DIVB 12\r
+\r
+/// USB PLL divisor value to obtain a 48MHz clock.\r
+#define BOARD_USBDIV AT91C_CKGR_USBDIV_2\r
+/// Master clock prescaler value.\r
+#define BOARD_PRESCALER AT91C_PMC_MDIV_2\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+// Local functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Default spurious interrupt handler\r
+//------------------------------------------------------------------------------\r
+void DefaultSpuriousHandler(void)\r
+{\r
+ while (1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Default handler for fast interrupt requests.\r
+//------------------------------------------------------------------------------\r
+void DefaultFiqHandler(void)\r
+{\r
+ while (1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Default handler for standard interrupt requests.\r
+//------------------------------------------------------------------------------\r
+void DefaultIrqHandler(void)\r
+{\r
+ while (1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Performs the low-level initialization of the chip.\r
+//------------------------------------------------------------------------------\r
+void LowLevelInit(void)\r
+{\r
+ unsigned char i;\r
+\r
+ // Set flash wait states\r
+ //----------------------\r
+ AT91C_BASE_EFC->EFC_FMR = 6 << 8;\r
+\r
+//#if !defined(sdram)\r
+ // Initialize main oscillator\r
+ //---------------------------\r
+ AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN;\r
+ while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));\r
+\r
+ // Initialize PLLA at 200MHz (198.656)\r
+ AT91C_BASE_PMC->PMC_PLLAR = BOARD_CKGR_PLLA\r
+ | BOARD_PLLACOUNT\r
+ | BOARD_MULA\r
+ | BOARD_DIVA;\r
+ while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA));\r
+\r
+ // Initialize PLLB for USB usage\r
+ AT91C_BASE_PMC->PMC_PLLBR = BOARD_USBDIV\r
+ | BOARD_CKGR_PLLB\r
+ | BOARD_PLLBCOUNT\r
+ | BOARD_MULB\r
+ | BOARD_DIVB;\r
+ while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKB));\r
+\r
+ // Wait for the master clock if it was already initialized\r
+ while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));\r
+\r
+ // Switch to fast clock\r
+ //---------------------\r
+ // Switch to main oscillator + prescaler\r
+ AT91C_BASE_PMC->PMC_MCKR = BOARD_PRESCALER;\r
+ while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));\r
+\r
+ // Switch to PLL + prescaler\r
+ AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLLA_CLK;\r
+ while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));\r
+//#endif //#if !defined(sdram)\r
+\r
+ // Initialize AIC\r
+ //---------------\r
+ AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;\r
+ AT91C_BASE_AIC->AIC_SVR[0] = (unsigned int) DefaultFiqHandler;\r
+ for (i = 1; i < 31; i++) {\r
+\r
+ AT91C_BASE_AIC->AIC_SVR[i] = (unsigned int) DefaultIrqHandler;\r
+ }\r
+ AT91C_BASE_AIC->AIC_SPU = (unsigned int) DefaultSpuriousHandler;\r
+\r
+ // Unstack nested interrupts\r
+ for (i = 0; i < 8 ; i++) {\r
+\r
+ AT91C_BASE_AIC->AIC_EOICR = 0;\r
+ }\r
+\r
+ // Watchdog initialization\r
+ //------------------------\r
+ AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;\r
+\r
+ // Remap\r
+ //------\r
+ BOARD_RemapRam();\r
+\r
+ // Disable RTT and PIT interrupts (potential problem when program A\r
+ // configures RTT, then program B wants to use PIT only, interrupts\r
+ // from the RTT will still occur since they both use AT91C_ID_SYS)\r
+ AT91C_BASE_RTTC->RTTC_RTMR &= ~(AT91C_RTTC_ALMIEN | AT91C_RTTC_RTTINCIEN);\r
+ AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+#include <pio/pio.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Local macros\r
+//------------------------------------------------------------------------------\r
+\r
+/// Reads a register value. Useful to add trace information to read accesses.\r
+#define READ(peripheral, register) (peripheral->register)\r
+/// Writes data in a register. Useful to add trace information to write accesses.\r
+#define WRITE(peripheral, register, value) (peripheral->register = value)\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Changes the mapping of the chip so that the remap area mirrors the\r
+/// internal ROM or the EBI CS0 (depending on the BMS input).\r
+//------------------------------------------------------------------------------\r
+void BOARD_RemapRom(void)\r
+{\r
+ WRITE(AT91C_BASE_MATRIX, MATRIX_MRCR, 0);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Changes the mapping of the chip so that the remap area mirrors the\r
+/// internal RAM.\r
+//------------------------------------------------------------------------------\r
+void BOARD_RemapRam(void)\r
+{\r
+ WRITE(AT91C_BASE_MATRIX,\r
+ MATRIX_MRCR,\r
+ (AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D));\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initialize and configure the external SDRAM.\r
+//------------------------------------------------------------------------------\r
+void BOARD_ConfigureSdram(void)\r
+{\r
+ volatile unsigned int i;\r
+ static const Pin pinsSdram = PINS_SDRAM;\r
+ volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;\r
+ \r
+ // Enable corresponding PIOs\r
+ PIO_Configure(&pinsSdram, 1);\r
+ \r
+ // Enable EBI chip select for the SDRAM\r
+ WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC);\r
+ \r
+\r
+ // CFG Control Register\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9\r
+ | AT91C_SDRAMC_NR_13 \r
+ | AT91C_SDRAMC_CAS_2 \r
+ | AT91C_SDRAMC_NB_4_BANKS\r
+ | AT91C_SDRAMC_DBW_32_BITS\r
+ | AT91C_SDRAMC_TWR_2\r
+ | AT91C_SDRAMC_TRC_7\r
+ | AT91C_SDRAMC_TRP_2\r
+ | AT91C_SDRAMC_TRCD_2\r
+ | AT91C_SDRAMC_TRAS_5\r
+ | AT91C_SDRAMC_TXSR_8);\r
+\r
+ for (i = 0; i < 1000; i++);\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP\r
+ pSdram[0] = 0x00000000;\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL\r
+ pSdram[0] = 0x00000000; // Perform PRCHG\r
+\r
+ for (i = 0; i < 10000; i++);\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR\r
+ pSdram[1] = 0x00000001; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR\r
+ pSdram[2] = 0x00000002; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR\r
+ pSdram[3] = 0x00000003; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR\r
+ pSdram[4] = 0x00000004; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR\r
+ pSdram[5] = 0x00000005; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR\r
+ pSdram[6] = 0x00000006; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR\r
+ pSdram[7] = 0x00000007; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR\r
+ pSdram[8] = 0x00000008; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation\r
+ pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (BOARD_MCK * 7) / 1000000); // Set Refresh Timer\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode\r
+ pSdram[0] = 0x00000000; // Perform Normal mode\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initialize and configure the SDRAM for a 48 MHz MCK (ROM code clock settings).\r
+//------------------------------------------------------------------------------\r
+void BOARD_ConfigureSdram48MHz(void)\r
+{\r
+ volatile unsigned int i;\r
+ static const Pin pinsSdram = PINS_SDRAM;\r
+ volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;\r
+ \r
+ // Enable corresponding PIOs\r
+ PIO_Configure(&pinsSdram, 1);\r
+ \r
+ // Enable EBI chip select for the SDRAM\r
+ WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC);\r
+ \r
+\r
+ // CFG Control Register\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9\r
+ | AT91C_SDRAMC_NR_13 \r
+ | AT91C_SDRAMC_CAS_2 \r
+ | AT91C_SDRAMC_NB_4_BANKS\r
+ | AT91C_SDRAMC_DBW_32_BITS\r
+ | AT91C_SDRAMC_TWR_1\r
+ | AT91C_SDRAMC_TRC_4\r
+ | AT91C_SDRAMC_TRP_1\r
+ | AT91C_SDRAMC_TRCD_1\r
+ | AT91C_SDRAMC_TRAS_2\r
+ | AT91C_SDRAMC_TXSR_3);\r
+\r
+ for (i = 0; i < 1000; i++);\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP\r
+ pSdram[0] = 0x00000000;\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL\r
+ pSdram[0] = 0x00000000; // Perform PRCHG\r
+\r
+ for (i = 0; i < 10000; i++);\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR\r
+ pSdram[1] = 0x00000001; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR\r
+ pSdram[2] = 0x00000002; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR\r
+ pSdram[3] = 0x00000003; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR\r
+ pSdram[4] = 0x00000004; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR\r
+ pSdram[5] = 0x00000005; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR\r
+ pSdram[6] = 0x00000006; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR\r
+ pSdram[7] = 0x00000007; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR\r
+ pSdram[8] = 0x00000008; // Perform CBR\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation\r
+ pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (48000000 * 7) / 1000000); // Set Refresh Timer\r
+\r
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode\r
+ pSdram[0] = 0x00000000; // Perform Normal mode\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the EBI for NandFlash access. Pins must be configured after or\r
+/// before calling this function.\r
+//------------------------------------------------------------------------------\r
+void BOARD_ConfigureNandFlash(unsigned char busWidth)\r
+{\r
+ // Configure EBI\r
+ AT91C_BASE_MATRIX->MATRIX_EBI |= AT91C_MATRIX_CS3A_SM;\r
+\r
+ // Configure SMC\r
+ AT91C_BASE_SMC->SMC_SETUP3 = 0x00000000;\r
+ AT91C_BASE_SMC->SMC_PULSE3 = 0x00030003;\r
+ AT91C_BASE_SMC->SMC_CYCLE3 = 0x00050005;\r
+ AT91C_BASE_SMC->SMC_CTRL3 = 0x00002003;\r
+\r
+ if (busWidth == 8) {\r
+\r
+ AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;\r
+ }\r
+ else if (busWidth == 16) {\r
+ \r
+ AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the EBI for NandFlash access at 48MHz. Pins must be configured\r
+/// after or before calling this function.\r
+//------------------------------------------------------------------------------\r
+void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth)\r
+{\r
+ // Configure EBI\r
+ AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM;\r
+\r
+ // Configure SMC\r
+ AT91C_BASE_SMC->SMC_SETUP3 = 0x00010001;\r
+ AT91C_BASE_SMC->SMC_PULSE3 = 0x04030302;\r
+ AT91C_BASE_SMC->SMC_CYCLE3 = 0x00070004;\r
+ AT91C_BASE_SMC->SMC_CTRL3 = (AT91C_SMC_READMODE\r
+ | AT91C_SMC_WRITEMODE\r
+ | AT91C_SMC_NWAITM_NWAIT_DISABLE\r
+ | ((0x1 << 16) & AT91C_SMC_TDF));\r
+ \r
+ if (busWidth == 8) {\r
+\r
+ AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;\r
+ }\r
+ else if (busWidth == 16) {\r
+ \r
+ AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the EBI for NorFlash access at 48MHz.\r
+/// \Param busWidth Bus width \r
+//------------------------------------------------------------------------------\r
+void BOARD_ConfigureNorFlash48MHz(unsigned char busWidth)\r
+{\r
+ // Configure SMC\r
+ AT91C_BASE_SMC->SMC_SETUP0 = 0x00000001;\r
+ AT91C_BASE_SMC->SMC_PULSE0 = 0x07070703;\r
+ AT91C_BASE_SMC->SMC_CYCLE0 = 0x00070007;\r
+ AT91C_BASE_SMC->SMC_CTRL0 = (AT91C_SMC_READMODE\r
+ | AT91C_SMC_WRITEMODE\r
+ | AT91C_SMC_NWAITM_NWAIT_DISABLE\r
+ | ((0x1 << 16) & AT91C_SMC_TDF));\r
+ \r
+ if (busWidth == 8) {\r
+\r
+ AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;\r
+ }\r
+ else if (busWidth == 16) {\r
+ \r
+ AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;\r
+ }\r
+ else if (busWidth == 32) {\r
+ \r
+ AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Set flash wait states in the EFC for 48MHz\r
+//------------------------------------------------------------------------------\r
+void BOARD_ConfigureFlash48MHz(void)\r
+{\r
+ // Set flash wait states\r
+ //----------------------\r
+ AT91C_BASE_EFC->EFC_FMR = 6 << 8;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef BOARD_MEMORIES_H\r
+#define BOARD_MEMORIES_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void BOARD_RemapRom(void);\r
+\r
+extern void BOARD_RemapRam(void);\r
+\r
+extern void BOARD_ConfigureSdram(void);\r
+\r
+extern void BOARD_ConfigureSdram48MHz(void);\r
+\r
+extern void BOARD_ConfigureNandFlash(unsigned char busWidth);\r
+\r
+extern void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth);\r
+\r
+extern void BOARD_ConfigureNorFlash48MHz(unsigned char busWidth);\r
+\r
+extern void BOARD_ConfigureFlash48MHz(void);\r
+\r
+#endif //#ifndef BOARD_MEMORIES_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "ac97c.h"\r
+#include <board.h>\r
+#include <aic/aic.h>\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+#include <utility/math.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Local constants\r
+//------------------------------------------------------------------------------\r
+\r
+/// Maximum size of one PDC buffer (in bytes).\r
+#define MAX_PDC_COUNTER 65535\r
+\r
+//------------------------------------------------------------------------------\r
+// Local types\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// AC97 transfer descriptor. Tracks the status and parameters of a transfer\r
+/// on the AC97 bus.\r
+//------------------------------------------------------------------------------\r
+typedef struct _Ac97Transfer {\r
+\r
+ /// Buffer containing the slots to send.\r
+ unsigned char *pBuffer;\r
+ /// Total number of samples to send.\r
+ volatile unsigned int numSamples;\r
+ /// Optional callback function.\r
+ Ac97Callback callback;\r
+ /// Optional argument to the callback function.\r
+ void *pArg;\r
+\r
+} Ac97Transfer;\r
+\r
+//------------------------------------------------------------------------------\r
+/// AC97 controller driver structure. Monitors the status of transfers on all\r
+/// AC97 channels.\r
+//------------------------------------------------------------------------------\r
+typedef struct _Ac97c {\r
+\r
+ /// List of transfers occuring on each channel.\r
+ Ac97Transfer transfers[5];\r
+} Ac97c;\r
+\r
+//------------------------------------------------------------------------------\r
+// Local variables\r
+//------------------------------------------------------------------------------\r
+\r
+/// Global AC97 controller instance.\r
+static Ac97c ac97c;\r
+\r
+//------------------------------------------------------------------------------\r
+// Local functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the size of one sample (in bytes) on the given channel.\r
+/// \param channel Channel number.\r
+//------------------------------------------------------------------------------\r
+static unsigned char GetSampleSize(unsigned char channel)\r
+{\r
+ unsigned int size = 0;\r
+\r
+ SANITY_CHECK((channel == AC97C_CHANNEL_A)\r
+ || (channel == AC97C_CHANNEL_B)\r
+ || (channel == AC97C_CHANNEL_CODEC));\r
+\r
+ // Check selected channel\r
+ switch (channel) {\r
+ case AC97C_CHANNEL_CODEC: return 2;\r
+ case AC97C_CHANNEL_A: size = (AT91C_BASE_AC97C->AC97C_CAMR & AT91C_AC97C_SIZE) >> 16; break;\r
+ case AC97C_CHANNEL_B: size = (AT91C_BASE_AC97C->AC97C_CBMR & AT91C_AC97C_SIZE) >> 16; break;\r
+ }\r
+\r
+ // Compute size in bytes given SIZE field\r
+ if ((size & 2) != 0) {\r
+\r
+ return 2;\r
+ }\r
+ else {\r
+\r
+ return 4;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Interrupt service routine for Codec, is invoked by AC97C_Handler.\r
+//------------------------------------------------------------------------------\r
+static void CodecHandler(void)\r
+{\r
+ unsigned int status;\r
+ unsigned int data;\r
+ Ac97Transfer *pTransfer = &(ac97c.transfers[AC97C_CODEC_TRANSFER]);\r
+\r
+ // Read CODEC status register\r
+ status = AT91C_BASE_AC97C->AC97C_COSR;\r
+ status &= AT91C_BASE_AC97C->AC97C_COMR;\r
+\r
+ // A sample has been transmitted\r
+ if (status & AT91C_AC97C_TXRDY) {\r
+\r
+ pTransfer->numSamples--;\r
+\r
+ // If there are remaining samples, transmit one\r
+ if (pTransfer->numSamples > 0) {\r
+\r
+ data = *((unsigned int *) pTransfer->pBuffer);\r
+ AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_TXRDY);\r
+ AT91C_BASE_AC97C->AC97C_COTHR = data;\r
+\r
+ // Check if transfer is read or write\r
+ if ((data & AT91C_AC97C_READ) != 0) {\r
+ \r
+ AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_RXRDY;\r
+ }\r
+ else {\r
+ \r
+ pTransfer->pBuffer += sizeof(unsigned int);\r
+ AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_TXRDY;\r
+ }\r
+ }\r
+ // Transfer finished\r
+ else {\r
+\r
+ AT91C_BASE_AC97C->AC97C_IDR = AT91C_AC97C_COEVT;\r
+ AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_TXRDY);\r
+ if (pTransfer->callback) {\r
+\r
+ pTransfer->callback(pTransfer->pArg, 0, 0);\r
+ }\r
+ } \r
+ }\r
+\r
+ // A sample has been received\r
+ if (status & AT91C_AC97C_RXRDY) {\r
+\r
+ // Store sample\r
+ data = AT91C_BASE_AC97C->AC97C_CORHR;\r
+ *((unsigned int *) pTransfer->pBuffer) = data;\r
+\r
+ pTransfer->pBuffer += sizeof(unsigned int);\r
+ pTransfer->numSamples--;\r
+\r
+ // Transfer finished\r
+ if (pTransfer->numSamples > 0) {\r
+\r
+ data = *((unsigned int *) pTransfer->pBuffer);\r
+ AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_RXRDY);\r
+ AT91C_BASE_AC97C->AC97C_COTHR = data;\r
+\r
+ // Check if transfer is read or write\r
+ if ((data & AT91C_AC97C_READ) != 0) {\r
+ \r
+ AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_RXRDY;\r
+ }\r
+ else {\r
+ \r
+ pTransfer->pBuffer += sizeof(unsigned int);\r
+ AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_TXRDY;\r
+ }\r
+ }\r
+ else {\r
+\r
+ AT91C_BASE_AC97C->AC97C_IDR = AT91C_AC97C_COEVT;\r
+ AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_RXRDY);\r
+ if (pTransfer->callback) {\r
+\r
+ pTransfer->callback(pTransfer->pArg, 0, 0);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Interrupt service routine for channel A, is invoked by AC97C_Handler.\r
+//------------------------------------------------------------------------------\r
+static void ChannelAHandler(void)\r
+{\r
+ unsigned int status;\r
+ Ac97Transfer *pTransmit = &(ac97c.transfers[AC97C_CHANNEL_A_TRANSMIT]);\r
+ Ac97Transfer *pReceive = &(ac97c.transfers[AC97C_CHANNEL_A_RECEIVE]);\r
+\r
+ // Read channel A status register\r
+ status = AT91C_BASE_AC97C->AC97C_CASR;\r
+\r
+ // A buffer has been transmitted\r
+ if ((status & AT91C_AC97C_ENDTX) != 0) {\r
+\r
+ // Update transfer information\r
+ if (pTransmit->numSamples > MAX_PDC_COUNTER) {\r
+\r
+ pTransmit->numSamples -= MAX_PDC_COUNTER;\r
+ }\r
+ else {\r
+\r
+ pTransmit->numSamples = 0;\r
+ }\r
+\r
+ // Transmit new buffers if necessary\r
+ if (pTransmit->numSamples > MAX_PDC_COUNTER) {\r
+\r
+ // Fill next PDC\r
+ AT91C_BASE_AC97C->AC97C_TNPR = (unsigned int) pTransmit->pBuffer;\r
+ if (pTransmit->numSamples > 2 * MAX_PDC_COUNTER) {\r
+\r
+ AT91C_BASE_AC97C->AC97C_TNCR = MAX_PDC_COUNTER;\r
+ pTransmit->pBuffer += MAX_PDC_COUNTER * GetSampleSize(AC97C_CHANNEL_A);\r
+ }\r
+ else {\r
+\r
+ AT91C_BASE_AC97C->AC97C_TNCR = pTransmit->numSamples - MAX_PDC_COUNTER;\r
+ }\r
+ }\r
+ // Only one buffer remaining\r
+ else {\r
+\r
+ AT91C_BASE_AC97C->AC97C_CAMR &= ~AT91C_AC97C_ENDTX;\r
+ AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_TXBUFE;\r
+ }\r
+ }\r
+\r
+ // Transmit completed\r
+ if ((status & AT91C_AC97C_TXBUFE) != 0) {\r
+\r
+ pTransmit->numSamples = 0;\r
+ AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS;\r
+ AT91C_BASE_AC97C->AC97C_CAMR &= ~AT91C_AC97C_TXBUFE;\r
+ if (pTransmit->callback) {\r
+\r
+ pTransmit->callback(pTransmit->pArg, 0, 0);\r
+ }\r
+ }\r
+\r
+ // A buffer has been received\r
+ if (status & AT91C_AC97C_ENDRX) {\r
+\r
+ if (pReceive->numSamples > MAX_PDC_COUNTER) {\r
+ \r
+ pReceive->numSamples -= MAX_PDC_COUNTER;\r
+ }\r
+ else {\r
+\r
+ pReceive->numSamples = 0;\r
+ }\r
+\r
+ // Transfer remaining samples\r
+ if (pReceive->numSamples > MAX_PDC_COUNTER) {\r
+\r
+ AT91C_BASE_AC97C->AC97C_RNPR = (unsigned int) pReceive->pBuffer;\r
+ if (pReceive->numSamples > 2 * MAX_PDC_COUNTER) {\r
+ \r
+ AT91C_BASE_AC97C->AC97C_RNCR = MAX_PDC_COUNTER;\r
+ pReceive->pBuffer += MAX_PDC_COUNTER * GetSampleSize(AC97C_CHANNEL_A);\r
+ }\r
+ else {\r
+\r
+ AT91C_BASE_AC97C->AC97C_RNCR = pReceive->numSamples - MAX_PDC_COUNTER;\r
+ }\r
+ }\r
+ // Only one buffer remaining\r
+ else {\r
+\r
+ AT91C_BASE_AC97C->AC97C_CAMR &= ~(AT91C_AC97C_ENDRX);\r
+ AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_RXBUFF;\r
+ }\r
+ }\r
+\r
+ // Receive complete\r
+ if ((status & AT91C_AC97C_RXBUFF) != 0) {\r
+\r
+ pReceive->numSamples = 0;\r
+ AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTDIS;\r
+ AT91C_BASE_AC97C->AC97C_CAMR &= ~AT91C_AC97C_RXBUFF;\r
+ if (pReceive->callback) {\r
+\r
+ pReceive->callback(pReceive->pArg, 0, 0);\r
+ }\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// This handler function must be called by the AC97C interrupt service routine.\r
+/// Identifies which event was activated and calls the associated function.\r
+//------------------------------------------------------------------------------ \r
+void AC97C_Handler(void)\r
+{\r
+ unsigned int status;\r
+\r
+ // Get the real interrupt source\r
+ status = AT91C_BASE_AC97C->AC97C_SR;\r
+ status &= AT91C_BASE_AC97C->AC97C_IMR;\r
+ \r
+ // Check if an event on the codec channel is active\r
+ if ((status & AT91C_AC97C_COEVT) != 0) {\r
+\r
+ CodecHandler(); \r
+ }\r
+ // Check if an event on channel A is active\r
+ if ((status & AT91C_AC97C_CAEVT) != 0) {\r
+\r
+ ChannelAHandler(); \r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts a read or write transfer on the given channel\r
+/// \param channel particular channel (AC97C_CHANNEL_A or AC97C_CHANNEL_B).\r
+/// \param pBuffer buffer containing the slots to send.\r
+/// \param numSamples total number of samples to send. \r
+/// \param callback optional callback function.\r
+/// \param pArg optional argument to the callback function.\r
+//------------------------------------------------------------------------------\r
+unsigned char AC97C_Transfer(\r
+ unsigned char channel,\r
+ unsigned char *pBuffer,\r
+ unsigned int numSamples,\r
+ Ac97Callback callback,\r
+ void *pArg)\r
+{\r
+ unsigned int size;\r
+ unsigned int data;\r
+ Ac97Transfer *pTransfer;\r
+\r
+ SANITY_CHECK(channel <= 5);\r
+ SANITY_CHECK(pBuffer);\r
+ SANITY_CHECK(numSamples > 0);\r
+\r
+ // Check that no transfer is pending on the channel\r
+ pTransfer = &(ac97c.transfers[channel]);\r
+ if (pTransfer->numSamples > 0) {\r
+\r
+ trace_LOG(trace_WARNING, "-W- AC97C_Transfer: Channel %d is busy\n\r", channel);\r
+ return AC97C_ERROR_BUSY;\r
+ }\r
+\r
+ // Fill transfer information\r
+ pTransfer->pBuffer = pBuffer;\r
+ pTransfer->numSamples = numSamples;\r
+ pTransfer->callback = callback;\r
+ pTransfer->pArg = pArg;\r
+\r
+ // Transmit or receive over codec channel\r
+ if (channel == AC97C_CODEC_TRANSFER) {\r
+\r
+ // Send command\r
+ data = *((unsigned int *) pTransfer->pBuffer); \r
+ AT91C_BASE_AC97C->AC97C_COTHR = data;\r
+\r
+ // Check if transfer is read or write\r
+ if ((data & AT91C_AC97C_READ) != 0) {\r
+\r
+ AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_RXRDY;\r
+ }\r
+ else {\r
+ \r
+ pTransfer->pBuffer += sizeof(unsigned int);\r
+ AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_TXRDY;\r
+ }\r
+\r
+ // Enable interrupts\r
+ AT91C_BASE_AC97C->AC97C_IER |= AT91C_AC97C_COEVT;\r
+ }\r
+ // Transmit over channel A\r
+ else if (channel == AC97C_CHANNEL_A_TRANSMIT) {\r
+\r
+ // Disable PDC\r
+ AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS;\r
+\r
+ // Fill PDC buffers\r
+ size = min(pTransfer->numSamples, MAX_PDC_COUNTER);\r
+ AT91C_BASE_AC97C->AC97C_TPR = (unsigned int) pTransfer->pBuffer;\r
+ AT91C_BASE_AC97C->AC97C_TCR = size;\r
+ pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);\r
+\r
+ size = min(pTransfer->numSamples - size, MAX_PDC_COUNTER);\r
+ if (size > 0) {\r
+\r
+ AT91C_BASE_AC97C->AC97C_TNPR = (unsigned int) pTransfer->pBuffer;\r
+ AT91C_BASE_AC97C->AC97C_TNCR = size;\r
+ pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);\r
+ }\r
+\r
+ // Enable interrupts\r
+ AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_PDCEN | AT91C_AC97C_ENDTX;\r
+ AT91C_BASE_AC97C->AC97C_IER |= AT91C_AC97C_CAEVT;\r
+\r
+ // Start transfer\r
+ AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTEN;\r
+ }\r
+ // Receive over channel A\r
+ else if (channel == AC97C_CHANNEL_A_RECEIVE) {\r
+\r
+ // Disable PDC\r
+ AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTDIS;\r
+\r
+ // Fill PDC buffers\r
+ size = min(pTransfer->numSamples, MAX_PDC_COUNTER);\r
+ AT91C_BASE_AC97C->AC97C_RPR = (unsigned int) pTransfer->pBuffer;\r
+ AT91C_BASE_AC97C->AC97C_RCR = size;\r
+ pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);\r
+\r
+ size = min(pTransfer->numSamples - size, MAX_PDC_COUNTER);\r
+ if (size > 0) {\r
+\r
+ AT91C_BASE_AC97C->AC97C_RNPR = (unsigned int) pTransfer->pBuffer;\r
+ AT91C_BASE_AC97C->AC97C_RNCR = size;\r
+ pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);\r
+ }\r
+\r
+ // Enable interrupts\r
+ AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_PDCEN | AT91C_AC97C_ENDRX;\r
+ AT91C_BASE_AC97C->AC97C_IER |= AT91C_AC97C_CAEVT;\r
+\r
+ // Start transfer\r
+ AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTEN;\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Stop read or write transfer on the given channel.\r
+/// \param channel Channel number.\r
+//------------------------------------------------------------------------------\r
+void AC97C_CancelTransfer(unsigned char channel)\r
+{ \r
+ unsigned int size = 0;\r
+ Ac97Transfer *pTransfer;\r
+\r
+ SANITY_CHECK(channel <= AC97C_CHANNEL_B_TRANSMIT);\r
+\r
+ // Save remaining size\r
+ pTransfer = &(ac97c.transfers[channel]);\r
+ size = pTransfer->numSamples;\r
+ pTransfer->numSamples = 0;\r
+\r
+ // Stop PDC\r
+ if (channel == AC97C_CHANNEL_A_TRANSMIT) {\r
+\r
+ AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS;\r
+ size -= min(size, MAX_PDC_COUNTER) - AT91C_BASE_AC97C->AC97C_TCR;\r
+ }\r
+ if (channel == AC97C_CHANNEL_A_RECEIVE) {\r
+\r
+ AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTDIS;\r
+ size -= min(size, MAX_PDC_COUNTER) - AT91C_BASE_AC97C->AC97C_RCR;\r
+ }\r
+\r
+ // Invoke callback if provided\r
+ if (pTransfer->callback) {\r
+\r
+ pTransfer->callback(pTransfer->pArg, AC97C_ERROR_STOPPED, size);\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initializes the AC97 controller.\r
+//------------------------------------------------------------------------------\r
+void AC97C_Configure(void)\r
+{\r
+ unsigned char channel;\r
+\r
+ // Enable the AC97 controller peripheral clock\r
+ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_AC97C); \r
+ \r
+ // Enable the peripheral and variable rate adjustment\r
+ AT91C_BASE_AC97C->AC97C_MR = AT91C_AC97C_ENA | AT91C_AC97C_VRA;\r
+\r
+ // Unassigns all input & output slots\r
+ AC97C_AssignInputSlots(0, 0xFFFF);\r
+ AC97C_AssignOutputSlots(0, 0xFFFF);\r
+\r
+ // Install the AC97C interrupt handler\r
+ AT91C_BASE_AC97C->AC97C_IDR = 0xFFFFFFFF;\r
+ AIC_ConfigureIT(AT91C_ID_AC97C, 0, AC97C_Handler);\r
+ AIC_EnableIT(AT91C_ID_AC97C); \r
+\r
+ // Disable PDC transfers\r
+ AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS;\r
+\r
+ // Clear channel transfers\r
+ for (channel = 0; channel < AC97C_CHANNEL_B_TRANSMIT; channel++) {\r
+\r
+ ac97c.transfers[channel].numSamples = 0;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the desired channel with the given value.\r
+/// \param channel Channel number.\r
+/// \param cfg Configuration value.\r
+//------------------------------------------------------------------------------\r
+void AC97C_ConfigureChannel(unsigned char channel, unsigned int cfg)\r
+{\r
+ SANITY_CHECK((channel == AC97C_CHANNEL_A) || (channel == AC97C_CHANNEL_B));\r
+\r
+ if (channel == AC97C_CHANNEL_A) {\r
+\r
+ AT91C_BASE_AC97C->AC97C_CAMR = cfg;\r
+ }\r
+ else {\r
+\r
+ AT91C_BASE_AC97C->AC97C_CBMR = cfg;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Assigns the desired input slots to a particular channel.\r
+/// \param channel Channel number (or 0 to unassign slots).\r
+/// \param slots Bitfield value of slots to assign.\r
+//------------------------------------------------------------------------------\r
+void AC97C_AssignInputSlots(unsigned char channel, unsigned int slots)\r
+{\r
+ unsigned int value;\r
+ unsigned int i;\r
+\r
+ SANITY_CHECK(channel <= AC97C_CHANNEL_B);\r
+\r
+ // Assign all slots\r
+ slots >>= 3;\r
+ for (i = 3; i < 15; i++) {\r
+\r
+ // Check if slots is selected\r
+ if (slots & 1) {\r
+\r
+ value = AT91C_BASE_AC97C->AC97C_ICA;\r
+ value &= ~(0x07 << ((i - 3) * 3));\r
+ value |= channel << ((i - 3) * 3);\r
+ AT91C_BASE_AC97C->AC97C_ICA = value;\r
+ }\r
+ slots >>= 1;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Assigns the desired output slots to a particular channel.\r
+/// \param channel Channel number (or 0 to unassign slots).\r
+/// \param slots Bitfield value of slots to assign.\r
+//------------------------------------------------------------------------------\r
+void AC97C_AssignOutputSlots(unsigned char channel, unsigned int slots)\r
+{\r
+ unsigned int value;\r
+ unsigned int i;\r
+\r
+ SANITY_CHECK(channel <= AC97C_CHANNEL_B);\r
+\r
+ // Assign all slots\r
+ slots >>= 3;\r
+ for (i = 3; i < 15; i++) {\r
+\r
+ // Check if slots is selected\r
+ if (slots & 1) {\r
+\r
+ value = AT91C_BASE_AC97C->AC97C_OCA;\r
+ value &= ~(0x07 << ((i - 3) * 3));\r
+ value |= channel << ((i - 3) * 3);\r
+ AT91C_BASE_AC97C->AC97C_OCA = value;\r
+ }\r
+ slots >>= 1;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns 1 if no transfer is currently pending on the given channel;\r
+/// otherwise, returns 0.\r
+/// \param channel Channel number.\r
+//------------------------------------------------------------------------------\r
+unsigned char AC97C_IsFinished(unsigned char channel)\r
+{\r
+ SANITY_CHECK(channel <= AC97C_CHANNEL_B_TRANSMIT);\r
+\r
+ if (ac97c.transfers[channel].numSamples > 0) {\r
+\r
+ return 0;\r
+ }\r
+ else {\r
+\r
+ return 1;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Convenience function for synchronously sending commands to the codec.\r
+/// \param address Register address.\r
+/// \param data Command data.\r
+//------------------------------------------------------------------------------\r
+void AC97C_WriteCodec(unsigned char address, unsigned short data)\r
+{\r
+ unsigned int sample;\r
+\r
+ sample = (address << 16) | data;\r
+ AC97C_Transfer(AC97C_CODEC_TRANSFER, (unsigned char *) &sample, 1, 0, 0);\r
+ while (!AC97C_IsFinished(AC97C_CODEC_TRANSFER));\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Convenience function for receiving data from the AC97 codec.\r
+/// \param address Register address.\r
+//------------------------------------------------------------------------------\r
+unsigned short AC97C_ReadCodec(unsigned char address)\r
+{\r
+ unsigned int sample;\r
+\r
+ sample = AT91C_AC97C_READ | (address << 16);\r
+ AC97C_Transfer(AC97C_CODEC_TRANSFER, (unsigned char *) &sample, 1, 0, 0);\r
+ while (!AC97C_IsFinished(AC97C_CODEC_TRANSFER));\r
+\r
+ return sample;\r
+}\r
+ \r
+//------------------------------------------------------------------------------\r
+/// Sets the size in bits of one sample on the given channel.\r
+/// \param channel Channel number.\r
+/// \param size Size of one sample in bits (10, 16, 18 or 24).\r
+//------------------------------------------------------------------------------ \r
+void AC97C_SetChannelSize(unsigned char channel, unsigned char size)\r
+{\r
+ unsigned int bits = 0;\r
+\r
+ SANITY_CHECK((size == 10) || (size == 16) || (size == 18) || (size == 24));\r
+ SANITY_CHECK((channel == AC97C_CHANNEL_A) || (channel == AC97C_CHANNEL_B));\r
+\r
+ switch (size) {\r
+\r
+ case 10 : bits = AT91C_AC97C_SIZE_10_BITS; break;\r
+ case 16 : bits = AT91C_AC97C_SIZE_16_BITS; break;\r
+ case 18 : bits = AT91C_AC97C_SIZE_18_BITS; break;\r
+ case 20 : bits = AT91C_AC97C_SIZE_20_BITS; break;\r
+ }\r
+\r
+ if (channel == AC97C_CHANNEL_A) {\r
+\r
+ AT91C_BASE_AC97C->AC97C_CAMR &= ~(AT91C_AC97C_SIZE);\r
+ AT91C_BASE_AC97C->AC97C_CAMR |= bits;\r
+ }\r
+ else {\r
+\r
+ AT91C_BASE_AC97C->AC97C_CBMR &= ~(AT91C_AC97C_SIZE);\r
+ AT91C_BASE_AC97C->AC97C_CBMR |= bits;\r
+ }\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+#ifndef AC97C_H\r
+#define AC97C_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Constants\r
+//------------------------------------------------------------------------------\r
+\r
+/// The channel is already busy with a transfer.\r
+#define AC97C_ERROR_BUSY 1\r
+/// The transfer has been stopped by the user.\r
+#define AC97C_ERROR_STOPPED 2\r
+\r
+/// Codec channel index.\r
+#define AC97C_CHANNEL_CODEC 0\r
+/// Channel A index.\r
+#define AC97C_CHANNEL_A 1\r
+/// Channel B index.\r
+#define AC97C_CHANNEL_B 2\r
+\r
+/// Codec transmit/receive transfer index.\r
+#define AC97C_CODEC_TRANSFER 0\r
+/// Channel A receive transfer index.\r
+#define AC97C_CHANNEL_A_RECEIVE 1\r
+/// Channel A transmit transfer index.\r
+#define AC97C_CHANNEL_A_TRANSMIT 2\r
+/// Channel B receive transfer index.\r
+#define AC97C_CHANNEL_B_RECEIVE 3\r
+/// Channel B transmit transfer index.\r
+#define AC97C_CHANNEL_B_TRANSMIT 4\r
+\r
+//------------------------------------------------------------------------------\r
+// Types\r
+//------------------------------------------------------------------------------\r
+\r
+/// AC97C transfer callback function.\r
+typedef void (*Ac97Callback)(void *pArg,\r
+ unsigned char status,\r
+ unsigned int remaining);\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void AC97C_Configure();\r
+\r
+extern void AC97C_ConfigureChannel(unsigned char channel, unsigned int cfg);\r
+\r
+extern void AC97C_AssignInputSlots(unsigned char channel, unsigned int slots);\r
+\r
+extern void AC97C_AssignOutputSlots(unsigned char channel, unsigned int slots);\r
+\r
+extern unsigned char AC97C_Transfer(\r
+ unsigned char channel,\r
+ unsigned char *pBuffer,\r
+ unsigned int numSamples,\r
+ Ac97Callback callback,\r
+ void *pArg);\r
+\r
+extern unsigned char AC97C_IsFinished(unsigned char channel);\r
+\r
+extern void AC97C_WriteCodec(unsigned char address, unsigned short data);\r
+\r
+extern unsigned short AC97C_ReadCodec(unsigned char address);\r
+\r
+extern void AC97C_SetChannelSize(unsigned char channel, unsigned char size);\r
+\r
+extern void AC97C_CancelTransfer(unsigned char channel);\r
+\r
+#endif //#ifndef AC97C_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef trace_LEVEL\r
+ #define trace_LEVEL 1\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "aes.h"\r
+#include <board.h>\r
+#include <utility/trace.h>\r
+#include <utility/assert.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the AES peripheral to encrypt/decrypt, start mode (manual, auto,\r
+/// PDC) and operating mode (ECB, CBC, OFB, CFB, CTR).\r
+/// \param cipher Indicates if the peripheral should encrypt or decrypt data.\r
+/// \param smode Start mode.\r
+/// \param opmode Operating mode.\r
+//------------------------------------------------------------------------------\r
+void AES_Configure(\r
+ unsigned char cipher,\r
+ unsigned int smode,\r
+ unsigned int opmode)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- AES_Configure()\n\r");\r
+ SANITY_CHECK((cipher & 0xFFFFFFFE) == 0);\r
+ SANITY_CHECK((smode & 0xFFFFFCFF) == 0);\r
+ SANITY_CHECK((opmode & 0xFFFF8FFF) == 0);\r
+\r
+ // Reset the peripheral first\r
+ AT91C_BASE_AES->AES_CR = AT91C_AES_SWRST;\r
+\r
+ // Configure mode register\r
+ AT91C_BASE_AES->AES_MR = cipher | smode | opmode;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the key used by the AES algorithm to cipher the plain text or\r
+/// decipher the encrypted text.\r
+/// \param pKey Pointer to a 16-bytes cipher key.\r
+//------------------------------------------------------------------------------\r
+void AES_SetKey(const unsigned int *pKey)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- AES_SetKey()\n\r");\r
+ SANITY_CHECK(pKey);\r
+\r
+ AT91C_BASE_AES->AES_KEYWxR[0] = pKey[0];\r
+ AT91C_BASE_AES->AES_KEYWxR[1] = pKey[1];\r
+ AT91C_BASE_AES->AES_KEYWxR[2] = pKey[2];\r
+ AT91C_BASE_AES->AES_KEYWxR[3] = pKey[3];\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the initialization vector that is used to encrypt the plain text or\r
+/// decrypt the cipher text in chained block modes (CBC, CFB, OFB & CTR).\r
+/// \param pVector Pointer to a 16-bytes initialization vector.\r
+//------------------------------------------------------------------------------\r
+void AES_SetVector(const unsigned int *pVector)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- AES_SetVector()\n\r");\r
+ SANITY_CHECK(pVector);\r
+\r
+ AT91C_BASE_AES->AES_IVxR[0] = pVector[0];\r
+ AT91C_BASE_AES->AES_IVxR[1] = pVector[1];\r
+ AT91C_BASE_AES->AES_IVxR[2] = pVector[2];\r
+ AT91C_BASE_AES->AES_IVxR[3] = pVector[3];\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the input data of the AES algorithm (i.e. plain text in cipher mode,\r
+/// ciphered text in decipher mode). If auto mode is active, the encryption is\r
+/// started automatically after writing the last word.\r
+/// \param pData Pointer to the 16-bytes data to cipher/decipher.\r
+//------------------------------------------------------------------------------\r
+void AES_SetInputData(const unsigned int *pData)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- AES_SetInputData()\n\r");\r
+ SANITY_CHECK(pData);\r
+\r
+ AT91C_BASE_AES->AES_IDATAxR[0] = pData[0];\r
+ AT91C_BASE_AES->AES_IDATAxR[1] = pData[1];\r
+ AT91C_BASE_AES->AES_IDATAxR[2] = pData[2];\r
+ AT91C_BASE_AES->AES_IDATAxR[3] = pData[3];\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Stores the result of the last AES operation (encrypt/decrypt) in the\r
+/// provided buffer.\r
+/// \param pData Pointer to a 16-bytes buffer.\r
+//------------------------------------------------------------------------------\r
+void AES_GetOutputData(unsigned int *pData)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- AES_GetOutputData()\n\r");\r
+ SANITY_CHECK(pData);\r
+\r
+ pData[0] = AT91C_BASE_AES->AES_ODATAxR[0];\r
+ pData[1] = AT91C_BASE_AES->AES_ODATAxR[1];\r
+ pData[2] = AT91C_BASE_AES->AES_ODATAxR[2];\r
+ pData[3] = AT91C_BASE_AES->AES_ODATAxR[3];\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the input buffer to use when in PDC mode.\r
+/// \param pInput Pointer to the input buffer.\r
+//------------------------------------------------------------------------------\r
+void AES_SetInputBuffer(const unsigned int *pInput)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- AES_SetInputBuffer()\n\r");\r
+ SANITY_CHECK(pInput);\r
+\r
+ AT91C_BASE_AES->AES_TPR = (unsigned int) pInput;\r
+ AT91C_BASE_AES->AES_TCR = 4;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the output buffer to use when in PDC mode.\r
+/// \param pOutput Pointer to the output buffer.\r
+//------------------------------------------------------------------------------\r
+void AES_SetOutputBuffer(unsigned int *pOutput)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- AES_SetOutputBuffer()\n\r");\r
+ SANITY_CHECK(pOutput);\r
+\r
+ AT91C_BASE_AES->AES_RPR = (unsigned int) pOutput;\r
+ AT91C_BASE_AES->AES_RCR = 4;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts the encryption/decryption process when in manual or PDC mode. In\r
+/// manual mode, the key and input data must have been entered using\r
+/// AES_SetKey() and AES_SetInputData(). In PDC mode, the key, input & output\r
+/// buffer must have been set using AES_SetKey(), AES_SetInputBuffer() and\r
+/// AES_SetOutputBuffer().\r
+//------------------------------------------------------------------------------\r
+void AES_Start(void)\r
+{\r
+ trace_LOG(trace_DEBUG, "AES_Start()\n\r");\r
+ SANITY_CHECK(((AT91C_BASE_AES->AES_MR & AT91C_AES_SMOD) == AT91C_AES_SMOD_MANUAL)\r
+ || ((AT91C_BASE_AES->AES_MR & AT91C_AES_SMOD) == AT91C_AES_SMOD_PDC));\r
+\r
+ // Manual mode\r
+ if ((AT91C_BASE_AES->AES_MR & AT91C_AES_SMOD) == AT91C_AES_SMOD_MANUAL) {\r
+\r
+ AT91C_BASE_AES->AES_CR = AT91C_AES_START;\r
+ }\r
+ // PDC\r
+ else {\r
+\r
+ AT91C_BASE_AES->AES_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the current value of the AES interrupt status register.\r
+//------------------------------------------------------------------------------\r
+unsigned int AES_GetStatus(void)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- AES_GetStatus()\n\r");\r
+\r
+ return AT91C_BASE_AES->AES_ISR;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef AES_H\r
+#define AES_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void AES_Configure(\r
+ unsigned char cipher,\r
+ unsigned int smode,\r
+ unsigned int opmode);\r
+\r
+extern void AES_SetKey(const unsigned int *pKey);\r
+\r
+extern void AES_SetVector(const unsigned int *pVector);\r
+\r
+extern void AES_SetInputData(const unsigned int *pData);\r
+\r
+extern void AES_GetOutputData(unsigned int *pData);\r
+\r
+extern void AES_SetInputBuffer(const unsigned int *pInput);\r
+\r
+extern void AES_SetOutputBuffer(unsigned int *pOutput);\r
+\r
+extern void AES_Start(void);\r
+\r
+extern unsigned int AES_GetStatus(void);\r
+\r
+#endif //#ifndef AES_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "aic.h"\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the interrupt associated with the given source, using the\r
+/// specified mode and interrupt handler.\r
+/// \param source Interrupt source to configure.\r
+/// \param mode Triggering mode of the interrupt.\r
+/// \param handler Interrupt handler function.\r
+//------------------------------------------------------------------------------\r
+void AIC_ConfigureIT(unsigned int source,\r
+ unsigned int mode,\r
+ void (*handler)( void ))\r
+{\r
+ // Disable the interrupt first\r
+ AT91C_BASE_AIC->AIC_IDCR = 1 << source;\r
+\r
+ // Configure mode and handler\r
+ AT91C_BASE_AIC->AIC_SMR[source] = mode;\r
+ AT91C_BASE_AIC->AIC_SVR[source] = (unsigned int) handler;\r
+\r
+ // Clear interrupt\r
+ AT91C_BASE_AIC->AIC_ICCR = 1 << source;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables interrupts coming from the given (unique) source.\r
+/// \param source Interrupt source to enable.\r
+//------------------------------------------------------------------------------\r
+void AIC_EnableIT(unsigned int source)\r
+{\r
+ AT91C_BASE_AIC->AIC_IECR = 1 << source;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables interrupts coming from the given (unique) source.\r
+/// \param source Interrupt source to enable.\r
+//------------------------------------------------------------------------------\r
+void AIC_DisableIT(unsigned int source)\r
+{\r
+ AT91C_BASE_AIC->AIC_IDCR = 1 << source;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \dir\r
+/// !Purpose\r
+/// \r
+/// Methods and definitions for configuring interrupts using the Advanced\r
+/// Interrupt Controller (AIC).\r
+/// \r
+/// !Usage\r
+/// -# Configure an interrupt source using AIC_ConfigureIT\r
+/// -# Enable or disable interrupt generation of a particular source with\r
+/// AIC_EnableIT and AIC_DisableIT.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef AIC_H\r
+#define AIC_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL\r
+ /// Redefinition of missing constant.\r
+ #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void AIC_ConfigureIT(unsigned int source,\r
+ unsigned int mode,\r
+ void (*handler)( void ));\r
+\r
+extern void AIC_EnableIT(unsigned int source);\r
+\r
+extern void AIC_DisableIT(unsigned int source);\r
+\r
+#endif //#ifndef AIC_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+#include <pio/pio.h>\r
+#include <utility/trace.h>\r
+#include <aic/aic.h>\r
+#include "can.h"\r
+\r
+//------------------------------------------------------------------------------\r
+// Local definitions\r
+//------------------------------------------------------------------------------\r
+// CAN state\r
+#define CAN_DISABLED 0\r
+#define CAN_HALTED 1\r
+#define CAN_IDLE 2\r
+#define CAN_SENDING 3\r
+#define CAN_RECEIVING 4\r
+\r
+// MOT: Mailbox Object Type\r
+#define CAN_MOT_DISABLE 0 // Mailbox is disabled\r
+#define CAN_MOT_RECEPT 1 // Reception Mailbox\r
+#define CAN_MOT_RECEPT_OW 2 // Reception mailbox with overwrite\r
+#define CAN_MOT_TRANSMIT 3 // Transmit mailbox\r
+#define CAN_MOT_CONSUMER 4 // Consumer mailbox\r
+#define CAN_MOT_PRODUCER 5 // Producer mailbox\r
+\r
+//------------------------------------------------------------------------------\r
+// Local variables\r
+//------------------------------------------------------------------------------\r
+#if defined (PINS_CAN_TRANSCEIVER_TXD)\r
+static const Pin pins_can_transceiver_txd[] = {PINS_CAN_TRANSCEIVER_TXD};\r
+#endif\r
+#if defined (PINS_CAN_TRANSCEIVER_RXD)\r
+static const Pin pins_can_transceiver_rxd[] = {PINS_CAN_TRANSCEIVER_RXD};\r
+#endif\r
+static const Pin pin_can_transceiver_rs = PIN_CAN_TRANSCEIVER_RS;\r
+#if defined (PIN_CAN_TRANSCEIVER_RXEN)\r
+static const Pin pin_can_transceiver_rxen = PIN_CAN_TRANSCEIVER_RXEN;\r
+#endif\r
+\r
+static CanTransfer *pCAN0Transfer=NULL;\r
+#ifdef AT91C_BASE_CAN1\r
+static CanTransfer *pCAN1Transfer=NULL;\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Local functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// CAN Error Detection\r
+/// \param status error type\r
+/// \param can_number can nulber\r
+//------------------------------------------------------------------------------\r
+static void CAN_ErrorHandling( unsigned int status, unsigned char can_number)\r
+{\r
+ if( (status&AT91C_CAN_ERRA) == AT91C_CAN_ERRA) {\r
+ trace_LOG( trace_ERROR, "-E- (CAN) CAN is in active Error Active mode\n\r");\r
+ }\r
+ else if( (status&AT91C_CAN_ERRP) == AT91C_CAN_ERRP) {\r
+ trace_LOG( trace_ERROR, "-E- (CAN) CAN is in Error Passive mode\n\r");\r
+ }\r
+ else if( (status&AT91C_CAN_BOFF) == AT91C_CAN_BOFF) {\r
+ trace_LOG( trace_ERROR, "-E- (CAN) CAN is in Buff Off mode\n\r");\r
+ // CAN reset\r
+ trace_LOG( trace_ERROR, "-E- (CAN) CAN%d reset\n\r", can_number);\r
+ // CAN Controller Disable\r
+ if (can_number == 0) {\r
+ AT91C_BASE_CAN0->CAN_MR &= ~AT91C_CAN_CANEN;\r
+ // CAN Controller Enable\r
+ AT91C_BASE_CAN0->CAN_MR |= AT91C_CAN_CANEN;\r
+ }\r
+#ifdef AT91C_BASE_CAN1\r
+ else if (can_number == 1) {\r
+ AT91C_BASE_CAN1->CAN_MR &= ~AT91C_CAN_CANEN;\r
+ // CAN Controller Enable\r
+ AT91C_BASE_CAN1->CAN_MR |= AT91C_CAN_CANEN;\r
+ }\r
+#endif\r
+ }\r
+\r
+ // Error for Frame dataframe\r
+ // CRC error\r
+ if( (status&AT91C_CAN_CERR) == AT91C_CAN_CERR) {\r
+ trace_LOG( trace_ERROR, "-E- (CAN) CRC Error\n\r");\r
+ }\r
+ // Bit-stuffing error\r
+ else if( (status&AT91C_CAN_SERR) == AT91C_CAN_SERR) {\r
+ trace_LOG( trace_ERROR, "-E- (CAN) Stuffing Error\n\r");\r
+ }\r
+ // Bit error\r
+ else if( (status&AT91C_CAN_BERR) == AT91C_CAN_BERR) {\r
+ trace_LOG( trace_ERROR, "-E- (CAN) Bit Error\n\r");\r
+ }\r
+ // Form error\r
+ else if( (status&AT91C_CAN_FERR) == AT91C_CAN_FERR) {\r
+ trace_LOG( trace_ERROR, "-E- (CAN) Form Error\n\r");\r
+ }\r
+ // Acknowledgment error\r
+ else if( (status&AT91C_CAN_AERR) == AT91C_CAN_AERR) {\r
+ trace_LOG( trace_ERROR, "-E- (CAN) Acknowledgment Error\n\r");\r
+ }\r
+\r
+ // Error interrupt handler\r
+ // Represent the current status of the CAN bus and are not latched.\r
+ // See CAN, par. Error Interrupt Handler\r
+ // AT91C_CAN_WARN\r
+ // AT91C_CAN_ERRA\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Generic CAN Interrupt handler\r
+/// \param can_number can nulber\r
+//------------------------------------------------------------------------------\r
+static void CAN_Handler( unsigned char can_number ) \r
+{\r
+ AT91PS_CAN base_can;\r
+ AT91PS_CAN_MB CAN_Mailbox;\r
+\r
+ unsigned int status;\r
+ unsigned int can_msr;\r
+ unsigned int* pCan_mcr;\r
+ unsigned int message_mode;\r
+ unsigned char numMailbox;\r
+ unsigned char state0;\r
+ unsigned char state1;\r
+\r
+ if( can_number == 0 ) {\r
+ base_can = AT91C_BASE_CAN0;\r
+ CAN_Mailbox = AT91C_BASE_CAN0_MB0;\r
+ state0 = pCAN0Transfer->state;\r
+ }\r
+#ifdef AT91C_BASE_CAN1\r
+ else {\r
+ base_can = AT91C_BASE_CAN1;\r
+ CAN_Mailbox = AT91C_BASE_CAN1_MB0;\r
+ state1 = pCAN1Transfer->state;\r
+ }\r
+#endif\r
+ status = (base_can->CAN_SR) & (base_can->CAN_IMR);\r
+ base_can->CAN_IDR = status;\r
+\r
+ trace_LOG( trace_DEBUG, "CAN0 status=0x%X\n\r", status);\r
+ if(status & AT91C_CAN_WAKEUP) {\r
+ if( can_number == 0 ) {\r
+ pCAN0Transfer->test_can = AT91C_TEST_OK;\r
+ pCAN0Transfer->state = CAN_IDLE;\r
+ }\r
+#ifdef AT91C_BASE_CAN1\r
+ else {\r
+ pCAN1Transfer->test_can = AT91C_TEST_OK;\r
+ pCAN1Transfer->state = CAN_IDLE;\r
+ }\r
+#endif\r
+ }\r
+ // Mailbox event ?\r
+ else if ((status&0x0000FFFF) != 0) {\r
+ trace_LOG( trace_DEBUG, "Mailbox event\n\r");\r
+\r
+ // Handle Mailbox interrupts\r
+ for (numMailbox = 0; numMailbox < NUM_MAILBOX_MAX; numMailbox++) {\r
+\r
+ can_msr = *(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x10+(0x20*numMailbox)));\r
+ if ((AT91C_CAN_MRDY & can_msr) == AT91C_CAN_MRDY) {\r
+ // Mailbox object type\r
+ message_mode = ((*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x00+(0x20*numMailbox))))>>24)&0x7;\r
+ trace_LOG( trace_DEBUG, "message_mode 0x%X\n\r", message_mode);\r
+ trace_LOG( trace_DEBUG, "numMailbox 0x%X\n\r", numMailbox);\r
+\r
+ if( message_mode == 0 ) {\r
+ trace_LOG( trace_ERROR, "-E-Error in MOT\n\r");\r
+ }\r
+ else if( ( message_mode == CAN_MOT_RECEPT ) \r
+ || ( message_mode == CAN_MOT_RECEPT_OW ) \r
+ || ( message_mode == CAN_MOT_PRODUCER ) ) {\r
+ trace_LOG( trace_DEBUG, "Mailbox is in RECEPTION\n\r");\r
+ trace_LOG( trace_DEBUG, "Length 0x%X\n\r", (can_msr>>16)&0xF);\r
+ trace_LOG( trace_DEBUG, "CAN_MB_MID 0x%X\n\r", ((*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x08+(0x20*numMailbox)))&AT91C_CAN_MIDvA)>>18));\r
+\r
+ trace_LOG( trace_DEBUG, "can_number %d\n\r", can_number);\r
+ if( can_number == 0 ) {\r
+ //CAN_MB_MDLx\r
+ pCAN0Transfer->data_low_reg = \r
+ (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x14+(0x20*numMailbox))));\r
+ //CAN_MB_MDHx\r
+ pCAN0Transfer->data_high_reg = \r
+ (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x18+(0x20*numMailbox))));\r
+ pCAN0Transfer->size = (can_msr>>16)&0xF;\r
+ pCAN0Transfer->mailbox_number = numMailbox;\r
+ state0 = CAN_IDLE;\r
+ }\r
+#ifdef AT91C_BASE_CAN1\r
+ else {\r
+ //CAN_MB_MDLx\r
+ pCAN1Transfer->data_low_reg = \r
+ (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x14+(0x20*numMailbox))));\r
+ //CAN_MB_MDHx\r
+ pCAN1Transfer->data_high_reg = \r
+ (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x18+(0x20*numMailbox))));\r
+ pCAN1Transfer->size = (can_msr>>16)&0xF;\r
+ pCAN1Transfer->mailbox_number = numMailbox;\r
+ state1 = CAN_IDLE;\r
+ }\r
+#endif\r
+ // Message Data has been received\r
+ pCan_mcr = (unsigned int*)((unsigned int)CAN_Mailbox+0x1C+(0x20*numMailbox));\r
+ *pCan_mcr = AT91C_CAN_MTCR;\r
+\r
+ }\r
+ else {\r
+ trace_LOG( trace_DEBUG, "Mailbox is in TRANSMIT\n\r");\r
+ trace_LOG( trace_DEBUG, "Length 0x%X\n\r", (can_msr>>16)&0xF);\r
+ trace_LOG( trace_DEBUG, "can_number %d\n\r", can_number);\r
+ if( can_number == 0 ) {\r
+ state0 = CAN_IDLE;\r
+ }\r
+ else {\r
+ state1 = CAN_IDLE;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ if( can_number == 0 ) {\r
+ pCAN0Transfer->state = state0;\r
+ }\r
+#ifdef AT91C_BASE_CAN1\r
+ else {\r
+ pCAN1Transfer->state = state1;\r
+ }\r
+#endif\r
+ }\r
+ if ((status&0xFFCF0000) != 0) {\r
+ CAN_ErrorHandling(status, 0);\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// CAN 0 Interrupt handler\r
+//------------------------------------------------------------------------------\r
+static void CAN0_Handler(void)\r
+{\r
+ CAN_Handler( 0 );\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// CAN 1 Interrupt handler\r
+//------------------------------------------------------------------------------\r
+#if defined AT91C_BASE_CAN1\r
+static void CAN1_Handler(void)\r
+{\r
+ CAN_Handler( 1 );\r
+}\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configure the corresponding mailbox\r
+/// \param pTransfer can transfer structure\r
+//------------------------------------------------------------------------------\r
+void CAN_InitMailboxRegisters( CanTransfer *pTransfer )\r
+{\r
+ AT91PS_CAN base_can;\r
+ AT91PS_CAN_MB CAN_Mailbox;\r
+\r
+ if( pTransfer->can_number == 0 ) {\r
+ base_can = AT91C_BASE_CAN0;\r
+ CAN_Mailbox = AT91C_BASE_CAN0_MB0;\r
+ }\r
+#ifdef AT91C_BASE_CAN1\r
+ else {\r
+ base_can = AT91C_BASE_CAN1;\r
+ CAN_Mailbox = AT91C_BASE_CAN1_MB0;\r
+ }\r
+#endif\r
+ CAN_Mailbox = (AT91PS_CAN_MB)((unsigned int)CAN_Mailbox+(unsigned int)(0x20*pTransfer->mailbox_number));\r
+\r
+ pTransfer->mailbox_in_use |= 1<<(pTransfer->mailbox_number);\r
+ // MailBox Control Register\r
+ CAN_Mailbox->CAN_MB_MCR = 0x0;\r
+ // MailBox Mode Register\r
+ CAN_Mailbox->CAN_MB_MMR = 0x00;\r
+ // CAN Message Acceptance Mask Register\r
+ CAN_Mailbox->CAN_MB_MAM = pTransfer->acceptance_mask_reg;\r
+ // MailBox ID Register\r
+ // Disable the mailbox before writing to CAN_MIDx registers\r
+ if( pTransfer->identifier != 0 ) {\r
+ CAN_Mailbox->CAN_MB_MAM |= AT91C_CAN_MIDE;\r
+ CAN_Mailbox->CAN_MB_MID = pTransfer->identifier;\r
+ }\r
+ else {\r
+ CAN_Mailbox->CAN_MB_MAM &= ~AT91C_CAN_MIDE;\r
+ }\r
+ // MailBox Mode Register\r
+ CAN_Mailbox->CAN_MB_MMR = pTransfer->mode_reg;\r
+ // MailBox Data Low Register\r
+ CAN_Mailbox->CAN_MB_MDL = pTransfer->data_low_reg;\r
+ // MailBox Data High Register\r
+ CAN_Mailbox->CAN_MB_MDH = pTransfer->data_high_reg;\r
+ // MailBox Control Register\r
+ CAN_Mailbox->CAN_MB_MCR = pTransfer->control_reg;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Reset the MBx\r
+//------------------------------------------------------------------------------\r
+void CAN_ResetAllMailbox( void )\r
+{\r
+ unsigned char i;\r
+ \r
+#if defined (AT91C_BASE_CAN0_MB0)\r
+ CAN_ResetTransfer( pCAN0Transfer );\r
+ for( i=0; i<8; i++ ) {\r
+ pCAN0Transfer->can_number = 0;\r
+ pCAN0Transfer->mailbox_number = i;\r
+ pCAN0Transfer->mode_reg = AT91C_CAN_MOT_DIS;\r
+ pCAN0Transfer->acceptance_mask_reg = 0;\r
+ pCAN0Transfer->identifier = 0;\r
+ pCAN0Transfer->data_low_reg = 0x00000000;\r
+ pCAN0Transfer->data_high_reg = 0x00000000;\r
+ pCAN0Transfer->control_reg = 0x00000000;\r
+ CAN_InitMailboxRegisters( pCAN0Transfer );\r
+ }\r
+#endif\r
+#if defined (AT91C_BASE_CAN0_MB8)\r
+ for( i=0; i<8; i++ ) {\r
+ pCAN0Transfer->can_number = 0;\r
+ pCAN0Transfer->mailbox_number = i+8;\r
+ pCAN0Transfer->mode_reg = AT91C_CAN_MOT_DIS;\r
+ pCAN0Transfer->acceptance_mask_reg = 0;\r
+ pCAN0Transfer->identifier = 0;\r
+ pCAN0Transfer->data_low_reg = 0x00000000;\r
+ pCAN0Transfer->data_high_reg = 0x00000000;\r
+ pCAN0Transfer->control_reg = 0x00000000;\r
+ CAN_InitMailboxRegisters( pCAN0Transfer );\r
+ }\r
+#endif\r
+\r
+#if defined (AT91C_BASE_CAN1_MB0)\r
+ if( pCAN1Transfer != NULL ) {\r
+ CAN_ResetTransfer( pCAN1Transfer );\r
+ for( i=0; i<8; i++ ) {\r
+ pCAN1Transfer->can_number = 1;\r
+ pCAN1Transfer->mailbox_number = i;\r
+ pCAN1Transfer->mode_reg = AT91C_CAN_MOT_DIS;\r
+ pCAN1Transfer->acceptance_mask_reg = 0;\r
+ pCAN1Transfer->identifier = 0;\r
+ pCAN1Transfer->data_low_reg = 0x00000000;\r
+ pCAN1Transfer->data_high_reg = 0x00000000;\r
+ pCAN1Transfer->control_reg = 0x00000000;\r
+ CAN_InitMailboxRegisters( pCAN1Transfer );\r
+ }\r
+ }\r
+#endif\r
+#if defined (AT91C_BASE_CAN1_MB8)\r
+ if( pCAN1Transfer != NULL ) {\r
+ for( i=0; i<8; i++ ) {\r
+ pCAN1Transfer->can_number = 1;\r
+ pCAN1Transfer->mailbox_number = i+8;\r
+ pCAN1Transfer->mode_reg = AT91C_CAN_MOT_DIS;\r
+ pCAN1Transfer->acceptance_mask_reg = 0;\r
+ pCAN1Transfer->identifier = 0;\r
+ pCAN1Transfer->data_low_reg = 0x00000000;\r
+ pCAN1Transfer->data_high_reg = 0x00000000;\r
+ pCAN1Transfer->control_reg = 0x00000000;\r
+ CAN_InitMailboxRegisters( pCAN1Transfer );\r
+ }\r
+ }\r
+#endif\r
+\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// CAN reset Transfer descriptor\r
+/// \param pTransfer can transfer structure\r
+//------------------------------------------------------------------------------\r
+void CAN_ResetTransfer( CanTransfer *pTransfer )\r
+{\r
+ pTransfer->state = CAN_IDLE;\r
+ pTransfer->can_number = 0;\r
+ pTransfer->mailbox_number = 0;\r
+ pTransfer->test_can = 0;\r
+ pTransfer->mode_reg = 0;\r
+ pTransfer->acceptance_mask_reg = 0;\r
+ pTransfer->identifier = 0;\r
+ pTransfer->data_low_reg = 0;\r
+ pTransfer->data_high_reg = 0;\r
+ pTransfer->control_reg = 0;\r
+ pTransfer->mailbox_in_use = 0;\r
+ pTransfer->size = 0;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Wait for CAN synchronisation\r
+/// \return return 1 for good initialisation, otherwise return 0\r
+//------------------------------------------------------------------------------\r
+static unsigned char CAN_Synchronisation( void )\r
+{\r
+ unsigned int tick=0;\r
+\r
+ trace_LOG( trace_INFO, "CAN_Synchronisation\n\r");\r
+\r
+ pCAN0Transfer->test_can = AT91C_TEST_NOK;\r
+#ifdef AT91C_BASE_CAN1\r
+ if( pCAN1Transfer != NULL ) {\r
+ pCAN1Transfer->test_can = AT91C_TEST_NOK;\r
+ }\r
+#endif\r
+ // Enable CAN and Wait for WakeUp Interrupt\r
+ AT91C_BASE_CAN0->CAN_IER = AT91C_CAN_WAKEUP;\r
+ // CAN Controller Enable\r
+ AT91C_BASE_CAN0->CAN_MR = AT91C_CAN_CANEN;\r
+ // Enable Autobaud/Listen mode\r
+ // dangerous, CAN not answer in this mode\r
+\r
+ while( (pCAN0Transfer->test_can != AT91C_TEST_OK)\r
+ && (tick < AT91C_CAN_TIMEOUT) ) {\r
+ tick++;\r
+ }\r
+ if (tick == AT91C_CAN_TIMEOUT) {\r
+ trace_LOG( trace_ERROR, "-E- CAN0 Initialisations FAILED\n\r");\r
+ return 0;\r
+ } else {\r
+ trace_LOG( trace_INFO, "-I- CAN0 Initialisations Completed\n\r");\r
+ }\r
+\r
+#if defined AT91C_BASE_CAN1\r
+ if( pCAN1Transfer != NULL ) {\r
+ AT91C_BASE_CAN1->CAN_IER = AT91C_CAN_WAKEUP;\r
+ // CAN Controller Enable\r
+ AT91C_BASE_CAN1->CAN_MR = AT91C_CAN_CANEN;\r
+\r
+ tick = 0;\r
+ // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver\r
+ while( ((pCAN1Transfer->test_can != AT91C_TEST_OK)) \r
+ && (tick < AT91C_CAN_TIMEOUT) ) {\r
+ tick++;\r
+ }\r
+\r
+ if (tick == AT91C_CAN_TIMEOUT) {\r
+ trace_LOG( trace_ERROR, "-E- CAN1 Initialisations FAILED\n\r");\r
+ return 0;\r
+ } else {\r
+ trace_LOG( trace_INFO, "-I- CAN1 Initialisations Completed\n\r");\r
+ }\r
+ }\r
+#endif\r
+ return 1;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Write a CAN transfer\r
+/// \param pTransfer can transfer structure\r
+/// \return return CAN_STATUS_SUCCESS if command passed, otherwise \r
+/// return CAN_STATUS_LOCKED\r
+//------------------------------------------------------------------------------\r
+unsigned char CAN_Write( CanTransfer *pTransfer )\r
+{\r
+ AT91PS_CAN base_can;\r
+\r
+ if (pTransfer->state == CAN_RECEIVING) {\r
+ pTransfer->state = CAN_IDLE;\r
+ }\r
+\r
+ if (pTransfer->state != CAN_IDLE) {\r
+ return CAN_STATUS_LOCKED;\r
+ }\r
+\r
+ trace_LOG( trace_DEBUG, "CAN_Write\n\r");\r
+ pTransfer->state = CAN_SENDING;\r
+ if( pTransfer->can_number == 0 ) {\r
+ base_can = AT91C_BASE_CAN0;\r
+ }\r
+#ifdef AT91C_BASE_CAN1\r
+ else {\r
+ base_can = AT91C_BASE_CAN1;\r
+ }\r
+#endif\r
+ base_can->CAN_TCR = pTransfer->mailbox_in_use;\r
+ base_can->CAN_IER = pTransfer->mailbox_in_use;\r
+\r
+ return CAN_STATUS_SUCCESS;\r
+\r
+}\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/// Read a CAN transfer\r
+/// \param pTransfer can transfer structure\r
+/// \return return CAN_STATUS_SUCCESS if command passed, otherwise \r
+/// return CAN_STATUS_LOCKED\r
+//------------------------------------------------------------------------------\r
+unsigned char CAN_Read( CanTransfer *pTransfer )\r
+{\r
+ AT91PS_CAN base_can;\r
+\r
+ if (pTransfer->state != CAN_IDLE) {\r
+ return CAN_STATUS_LOCKED;\r
+ }\r
+\r
+ trace_LOG( trace_DEBUG, "CAN_Read\n\r");\r
+ pTransfer->state = CAN_RECEIVING;\r
+\r
+\r
+ if( pTransfer->can_number == 0 ) {\r
+ base_can = AT91C_BASE_CAN0;\r
+ }\r
+#ifdef AT91C_BASE_CAN1\r
+ else {\r
+ base_can = AT91C_BASE_CAN1;\r
+ }\r
+#endif\r
+ // enable interrupt\r
+ base_can->CAN_IER = pTransfer->mailbox_in_use;\r
+\r
+ return CAN_STATUS_SUCCESS;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Test if CAN is in IDLE state\r
+/// \param pTransfer can transfer structure\r
+/// \return return 0 if CAN is in IDLE, otherwise return 1\r
+//------------------------------------------------------------------------------\r
+unsigned char CAN_IsInIdle( CanTransfer *pTransfer )\r
+{\r
+ return( pTransfer->state != CAN_IDLE );\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Basic CAN test without Interrupt\r
+//------------------------------------------------------------------------------\r
+void CAN_BasicTestSuiteWithoutInterrupt(void)\r
+{\r
+#if defined AT91C_BASE_CAN1\r
+ unsigned int status;\r
+ unsigned int tick=0;\r
+\r
+ trace_LOG( trace_INFO, "Without Interrupt ");\r
+ trace_LOG( trace_INFO, "CAN0 Mailbox 0 transmitting to CAN1 Mailbox 0\n\r");\r
+ // Init CAN0 Mailbox 0, transmit\r
+ CAN_ResetTransfer( pCAN0Transfer );\r
+ pCAN0Transfer->can_number = 0;\r
+ pCAN0Transfer->mailbox_number = 0;\r
+ pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR;\r
+ pCAN0Transfer->acceptance_mask_reg = 0x00000000;\r
+ pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x07<<18);\r
+ pCAN0Transfer->data_low_reg = 0x11223344;\r
+ pCAN0Transfer->data_high_reg = 0x01234567;\r
+ pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16));\r
+ CAN_InitMailboxRegisters( pCAN0Transfer );\r
+\r
+ // Init CAN1 Mailbox 0, receive, \r
+ CAN_ResetTransfer( pCAN1Transfer );\r
+ pCAN1Transfer->can_number = 1;\r
+ pCAN1Transfer->mailbox_number = 0;\r
+ pCAN1Transfer->mode_reg = AT91C_CAN_MOT_RX;\r
+ pCAN1Transfer->acceptance_mask_reg = AT91C_CAN_MIDvA | AT91C_CAN_MIDvB;\r
+ pCAN1Transfer->identifier = AT91C_CAN_MIDvA & (0x07<<18);\r
+ pCAN1Transfer->data_low_reg = 0x00000000;\r
+ pCAN1Transfer->data_high_reg = 0x00000000;\r
+ pCAN1Transfer->control_reg = 0x00000000;\r
+ CAN_InitMailboxRegisters( pCAN1Transfer );\r
+\r
+ // Transfer Request for Mailbox 0\r
+ AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB0;\r
+\r
+ tick = 0;\r
+ do {\r
+ // CAN Message Status Register\r
+ status = AT91C_BASE_CAN0_MB0->CAN_MB_MSR;\r
+ }\r
+ while( !(status & AT91C_CAN_MRDY) && (++tick < AT91C_CAN_TIMEOUT) );\r
+\r
+ if (tick == AT91C_CAN_TIMEOUT) {\r
+ trace_LOG( trace_ERROR, "-E- Test FAILED\n\r");\r
+ } \r
+ else {\r
+ trace_LOG( trace_DEBUG, "-I- Transfer completed: CAN1 Mailbox 0 MRDY flag has raised\n\r");\r
+ if( AT91C_BASE_CAN0_MB0->CAN_MB_MDL != AT91C_BASE_CAN1_MB0->CAN_MB_MDL ) {\r
+ trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");\r
+ }\r
+ else if( AT91C_BASE_CAN0_MB0->CAN_MB_MDH != AT91C_BASE_CAN1_MB0->CAN_MB_MDH ) {\r
+ trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");\r
+ }\r
+ else {\r
+ trace_LOG( trace_INFO, "Test passed\n\r");\r
+ }\r
+ }\r
+\r
+ CAN_ResetAllMailbox();\r
+\r
+ trace_LOG( trace_INFO, "Without Interrupt ");\r
+ trace_LOG( trace_INFO, "CAN0 Mailboxes 1 & 2 transmitting to CAN1 Mailbox 15\n\r");\r
+ // Init CAN0 Mailbox 1, transmit\r
+ CAN_ResetTransfer( pCAN0Transfer );\r
+ pCAN0Transfer->can_number = 0;\r
+ pCAN0Transfer->mailbox_number = 1;\r
+ pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR;\r
+ pCAN0Transfer->acceptance_mask_reg = 0x00000000;\r
+ pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x09<<18); // ID 9\r
+ pCAN0Transfer->data_low_reg = 0xAABBCCDD;\r
+ pCAN0Transfer->data_high_reg = 0xCAFEDECA;\r
+ pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code\r
+ CAN_InitMailboxRegisters( pCAN0Transfer );\r
+\r
+ // Init CAN0 Mailbox 2, transmit\r
+ pCAN0Transfer->can_number = 0;\r
+ pCAN0Transfer->mailbox_number = 2;\r
+ pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | (AT91C_CAN_PRIOR-(1<<16));\r
+ pCAN0Transfer->acceptance_mask_reg = 0x00000000;\r
+ pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x0A<<18); // ID 10\r
+ pCAN0Transfer->data_low_reg = 0x55667788;\r
+ pCAN0Transfer->data_high_reg = 0x99AABBCC;\r
+ pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code\r
+ CAN_InitMailboxRegisters( pCAN0Transfer );\r
+\r
+ // Init CAN1 Mailbox 15, reception with overwrite\r
+ CAN_ResetTransfer( pCAN1Transfer );\r
+ pCAN1Transfer->can_number = 1;\r
+ pCAN1Transfer->mailbox_number = 15;\r
+ pCAN1Transfer->mode_reg = AT91C_CAN_MOT_RXOVERWRITE;\r
+ pCAN1Transfer->acceptance_mask_reg = 0;\r
+ pCAN1Transfer->identifier = 0x0;\r
+ pCAN1Transfer->data_low_reg = 0x00000000;\r
+ pCAN1Transfer->data_high_reg = 0x00000000;\r
+ pCAN1Transfer->control_reg = 0x00000000;\r
+ CAN_InitMailboxRegisters( pCAN1Transfer );\r
+\r
+ // Ask Transmissions on Mailbox 1 & 2 --> AT91C_CAN_MRDY & AT91C_CAN_MMI raises for Mailbox 15 CAN_MB_SR\r
+ AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB1 | AT91C_CAN_MB2;\r
+ \r
+ // Wait for Last Transmit Mailbox\r
+ tick = 0;\r
+ do {\r
+ status = AT91C_BASE_CAN1_MB15->CAN_MB_MSR;\r
+ }\r
+ while( !(status & AT91C_CAN_MMI) && (++tick < AT91C_CAN_TIMEOUT) );\r
+\r
+ if (tick == AT91C_CAN_TIMEOUT) {\r
+ }\r
+ else {\r
+ trace_LOG( trace_DEBUG, "-I- Transfer completed: CAN1 Mailbox 15 MRDY and MMI flags have raised\n\r");\r
+ if( AT91C_BASE_CAN0_MB1->CAN_MB_MDL != AT91C_BASE_CAN1_MB15->CAN_MB_MDL ) {\r
+ trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");\r
+ }\r
+ else if( AT91C_BASE_CAN0_MB1->CAN_MB_MDH != AT91C_BASE_CAN1_MB15->CAN_MB_MDH ) {\r
+ trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");\r
+ }\r
+ else {\r
+ trace_LOG( trace_INFO, "Test passed\n\r");\r
+ }\r
+ }\r
+\r
+ CAN_ResetAllMailbox();\r
+ trace_LOG( trace_INFO, "Without Interrupt ");\r
+ trace_LOG( trace_INFO, "CAN0 Mailboxes 1 & 2 transmitting to CAN1 Mailbox 15\n\r");\r
+ // Init CAN0 Mailbox 1, transmit\r
+ CAN_ResetTransfer( pCAN0Transfer );\r
+ pCAN0Transfer->can_number = 0;\r
+ pCAN0Transfer->mailbox_number = 1;\r
+ pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR;\r
+ pCAN0Transfer->acceptance_mask_reg = 0x00000000;\r
+ pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x09<<18); // ID 9\r
+ pCAN0Transfer->data_low_reg = 0xAABBCCDD;\r
+ pCAN0Transfer->data_high_reg = 0xCAFEDECA;\r
+ pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code\r
+ CAN_InitMailboxRegisters( pCAN0Transfer );\r
+\r
+ // Init CAN0 Mailbox 2, transmit\r
+ pCAN0Transfer->can_number = 0;\r
+ pCAN0Transfer->mailbox_number = 2;\r
+ pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | (AT91C_CAN_PRIOR-(1<<16));\r
+ pCAN0Transfer->acceptance_mask_reg = 0x00000000;\r
+ pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x0A<<18); // ID 10\r
+ pCAN0Transfer->data_low_reg = 0x55667788;\r
+ pCAN0Transfer->data_high_reg = 0x99AABBCC;\r
+ pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code\r
+ CAN_InitMailboxRegisters( pCAN0Transfer );\r
+\r
+ // Init CAN1 Mailbox 15, reception with overwrite\r
+ CAN_ResetTransfer( pCAN1Transfer );\r
+ pCAN1Transfer->can_number = 1;\r
+ pCAN1Transfer->mailbox_number = 15;\r
+ pCAN1Transfer->mode_reg = AT91C_CAN_MOT_RX;\r
+ pCAN1Transfer->acceptance_mask_reg = 0;\r
+ pCAN1Transfer->identifier = 0x0;\r
+ pCAN1Transfer->data_low_reg = 0x00000000;\r
+ pCAN1Transfer->data_high_reg = 0x00000000;\r
+ pCAN1Transfer->control_reg = 0x00000000;\r
+ CAN_InitMailboxRegisters( pCAN1Transfer );\r
+\r
+ // Ask Transmissions on Mailbox 1 & 2 --> AT91C_CAN_MRDY & AT91C_CAN_MMI raises for Mailbox 15 CAN_MB_SR\r
+ AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB1 | AT91C_CAN_MB2;\r
+ \r
+ // Wait for Last Transmit Mailbox\r
+ tick = 0;\r
+ do {\r
+ status = AT91C_BASE_CAN1_MB15->CAN_MB_MSR;\r
+ }\r
+ while( !(status & AT91C_CAN_MMI) && (++tick < AT91C_CAN_TIMEOUT) );\r
+\r
+ if (tick == AT91C_CAN_TIMEOUT) {\r
+ trace_LOG( trace_ERROR, "-E- Test FAILED\n\r");\r
+ }\r
+ else {\r
+ trace_LOG( trace_DEBUG, "Transfer completed: CAN1 Mailbox 15 MRDY and MMI flags have raised\n\r");\r
+ trace_LOG( trace_DEBUG, "MB_MDL: 0x%X\n\r", AT91C_BASE_CAN1_MB15->CAN_MB_MDL);\r
+ trace_LOG( trace_DEBUG, "MB_MDLH: 0x%X\n\r", AT91C_BASE_CAN1_MB15->CAN_MB_MDH);\r
+ if( AT91C_BASE_CAN0_MB2->CAN_MB_MDL != AT91C_BASE_CAN1_MB15->CAN_MB_MDL ) {\r
+ trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");\r
+ }\r
+ else if( AT91C_BASE_CAN0_MB2->CAN_MB_MDH != AT91C_BASE_CAN1_MB15->CAN_MB_MDH ) {\r
+ trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");\r
+ }\r
+ else {\r
+ trace_LOG( trace_INFO, "Test passed\n\r");\r
+ }\r
+ }\r
+\r
+ CAN_ResetAllMailbox();\r
+ trace_LOG( trace_INFO, "Without Interrupt ");\r
+ trace_LOG( trace_INFO, "CAN0 Mailbox 3 asking for CAN1 Mailbox 3 transmission\n\r");\r
+ // Init CAN0 Mailbox 3, consumer mailbox\r
+ // Sends a remote frame and waits for an answer\r
+ CAN_ResetTransfer( pCAN0Transfer );\r
+ pCAN0Transfer->can_number = 0;\r
+ pCAN0Transfer->mailbox_number = 3;\r
+ pCAN0Transfer->mode_reg = AT91C_CAN_MOT_CONSUMER | AT91C_CAN_PRIOR;\r
+ pCAN0Transfer->acceptance_mask_reg = AT91C_CAN_MIDvA | AT91C_CAN_MIDvB;\r
+ pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x0B<<18); // ID 11\r
+ pCAN0Transfer->data_low_reg = 0x00000000;\r
+ pCAN0Transfer->data_high_reg = 0x00000000;\r
+ pCAN0Transfer->control_reg = 0x00000000;\r
+ CAN_InitMailboxRegisters( pCAN0Transfer );\r
+\r
+ // Init CAN1 Mailbox 3, porducer mailbox\r
+ // Waits to receive a Remote Frame before sending its contents\r
+ CAN_ResetTransfer( pCAN1Transfer );\r
+ pCAN1Transfer->can_number = 1;\r
+ pCAN1Transfer->mailbox_number = 3;\r
+ pCAN1Transfer->mode_reg = AT91C_CAN_MOT_PRODUCER | AT91C_CAN_PRIOR;\r
+ pCAN1Transfer->acceptance_mask_reg = 0;\r
+ pCAN1Transfer->identifier = AT91C_CAN_MIDvA & (0x0B<<18); // ID 11\r
+ pCAN1Transfer->data_low_reg = 0xEEDDFF00;\r
+ pCAN1Transfer->data_high_reg = 0x34560022;\r
+ pCAN1Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16));\r
+ CAN_InitMailboxRegisters( pCAN1Transfer );\r
+\r
+ // Ask Transmissions on Mailbox 3 --> AT91C_CAN_MRDY raises for Mailbox 3 CAN_MB_SR\r
+ AT91C_BASE_CAN1->CAN_TCR = AT91C_CAN_MB3;\r
+ AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB3;\r
+\r
+ // Wait for Last Transmit Mailbox\r
+ tick = 0;\r
+ do {\r
+ status = AT91C_BASE_CAN0_MB3->CAN_MB_MSR;\r
+ }\r
+ while( !(status & AT91C_CAN_MRDY) && (++tick < AT91C_CAN_TIMEOUT) );\r
+\r
+ if (tick == AT91C_CAN_TIMEOUT) {\r
+ trace_LOG( trace_ERROR, "-E- Test FAILED\n\r");\r
+ }\r
+ else {\r
+ trace_LOG( trace_DEBUG, "-I- Transfer Completed: CAN0 & CAN1 Mailboxes 3 MRDY flags have raised\n\r");\r
+ if( AT91C_BASE_CAN0_MB3->CAN_MB_MDL != AT91C_BASE_CAN1_MB3->CAN_MB_MDL ) {\r
+ trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");\r
+ }\r
+ else if( AT91C_BASE_CAN0_MB3->CAN_MB_MDH != AT91C_BASE_CAN1_MB3->CAN_MB_MDH ) {\r
+ trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");\r
+ }\r
+ else {\r
+ trace_LOG( trace_INFO, "Test passed\n\r");\r
+ }\r
+ }\r
+#endif // AT91C_BASE_CAN1\r
+\r
+ return;\r
+}\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disable CAN and enter in low power\r
+//------------------------------------------------------------------------------\r
+void CAN_disable( void )\r
+{\r
+ // Disable the interrupt on the interrupt controller\r
+ AIC_DisableIT(AT91C_ID_CAN0);\r
+ // disable all IT\r
+ AT91C_BASE_CAN0->CAN_IDR = 0x1FFFFFFF;\r
+#if defined AT91C_BASE_CAN1\r
+ AIC_DisableIT(AT91C_ID_CAN1);\r
+ // disable all IT\r
+ AT91C_BASE_CAN1->CAN_IDR = 0x1FFFFFFF;\r
+#endif\r
+\r
+ // Enable Low Power mode\r
+ AT91C_BASE_CAN0->CAN_MR |= AT91C_CAN_LPM;\r
+\r
+ // Disable CANs Transceivers\r
+ // Enter standby mode\r
+ PIO_Set(&pin_can_transceiver_rs);\r
+#if defined (PIN_CAN_TRANSCEIVER_RXEN)\r
+ // Enable ultra Low Power mode\r
+ PIO_Clear(&pin_can_transceiver_rxen);\r
+#endif\r
+\r
+ // Disable clock for CAN PIO\r
+ AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_PIOA);\r
+\r
+ // Disable the CAN0 controller peripheral clock\r
+ AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_CAN0);\r
+\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// baudrate calcul\r
+/// \param base_CAN CAN base address\r
+/// \param baudrate Baudrate value\r
+/// allowed values: 1000, 800, 500, 250, 125, 50, 25, 10\r
+/// \return return 1 in success, otherwise return 0\r
+//------------------------------------------------------------------------------\r
+unsigned char CAN_BaudRateCalculate( AT91PS_CAN base_CAN, \r
+ unsigned int baudrate )\r
+{\r
+ unsigned int BRP;\r
+ unsigned int PROPAG;\r
+ unsigned int PHASE1;\r
+ unsigned int PHASE2;\r
+ unsigned int SJW;\r
+ unsigned int t1t2;\r
+\r
+ base_CAN->CAN_BR = 0;\r
+\r
+ BRP = (BOARD_MCK / (baudrate*1000*16))-1;\r
+ //trace_LOG( trace_DEBUG, "BRP = 0x%X\n\r", BRP);\r
+ // timing Delay:\r
+ // Delay Bus Driver: 50 ns\r
+ // Delay Receiver: 30 ns\r
+ // Delay Bus Line: 110 ns\r
+ if( (16*baudrate*2*(50+30+110)/1000000) >= 1) {\r
+ PROPAG = (16*baudrate*2*(50+30+110)/1000000)-1;\r
+ }\r
+ else {\r
+ PROPAG = 0;\r
+ }\r
+ //trace_LOG( trace_DEBUG, "PROPAG = 0x%X\n\r", PROPAG);\r
+\r
+ t1t2 = 15-(PROPAG+1);\r
+ //trace_LOG( trace_DEBUG, "t1t2 = 0x%X\n\r", t1t2);\r
+\r
+ if( (t1t2 & 0x01) == 0x01 ) {\r
+ // ODD\r
+ //trace_LOG( trace_DEBUG, "ODD\n\r");\r
+ PHASE1 = ((t1t2-1)/2)-1;\r
+ PHASE2 = PHASE1+1;\r
+ }\r
+ else {\r
+ // EVEN\r
+ //trace_LOG( trace_DEBUG, "EVEN\n\r");\r
+ PHASE1 = (t1t2/2)-1;\r
+ PHASE2 = PHASE1;\r
+ }\r
+ //trace_LOG( trace_DEBUG, "PHASE1 = 0x%X\n\r", PHASE1);\r
+ //trace_LOG( trace_DEBUG, "PHASE2 = 0x%X\n\r", PHASE2);\r
+\r
+ if( 1 > (4/(PHASE1+1)) ) {\r
+ //trace_LOG( trace_DEBUG, "4*Tcsc\n\r");\r
+ SJW = 3;\r
+ }\r
+ else {\r
+ //trace_LOG( trace_DEBUG, "Tphs1\n\r");\r
+ SJW = PHASE1;\r
+ }\r
+ //trace_LOG( trace_DEBUG, "SJW = 0x%X\n\r", SJW);\r
+ // Verif\r
+ if( BRP == 0 ) {\r
+ trace_LOG( trace_DEBUG, "BRP = 0 is not authorized\n\r");\r
+ return 0;\r
+ }\r
+ if( (PROPAG + PHASE1 + PHASE2) != 12 ) {\r
+ trace_LOG( trace_DEBUG, "(PROPAG + PHASE1 + PHASE2) != 12\n\r");\r
+ return 0;\r
+ }\r
+ base_CAN->CAN_BR = (AT91C_CAN_PHASE2 & (PHASE2 << 0))\r
+ + (AT91C_CAN_PHASE1 & (PHASE1 << 4))\r
+ + (AT91C_CAN_PROPAG & (PROPAG << 8))\r
+ + (AT91C_CAN_SYNC & (SJW << 12))\r
+ + (AT91C_CAN_BRP & (BRP << 16))\r
+ + (AT91C_CAN_SMP & (0 << 24));\r
+ return 1;\r
+\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// Init of the CAN peripheral\r
+/// \param baudrate Baudrate value\r
+/// allowed values: 1000, 800, 500, 250, 125, 50, 25, 10\r
+/// \param canTransfer0 CAN0 structure transfer\r
+/// \param canTransfer1 CAN1 structure transfer\r
+/// \return return 1 if CAN has good baudrate and CAN is synchronized, \r
+/// otherwise return 0\r
+//------------------------------------------------------------------------------\r
+unsigned char CAN_Init( unsigned int baudrate, \r
+ CanTransfer *canTransfer0, \r
+ CanTransfer *canTransfer1 ) \r
+{\r
+ unsigned char ret;\r
+\r
+ // CAN Transmit Serial Data\r
+#if defined (PINS_CAN_TRANSCEIVER_TXD)\r
+ PIO_Configure(pins_can_transceiver_txd, PIO_LISTSIZE(pins_can_transceiver_txd));\r
+#endif\r
+#if defined (PINS_CAN_TRANSCEIVER_RXD)\r
+ // CAN Receive Serial Data\r
+ PIO_Configure(pins_can_transceiver_rxd, PIO_LISTSIZE(pins_can_transceiver_rxd));\r
+#endif\r
+ // CAN RS\r
+ PIO_Configure(&pin_can_transceiver_rs, PIO_LISTSIZE(pin_can_transceiver_rs));\r
+#if defined (PIN_CAN_TRANSCEIVER_RXEN)\r
+ // CAN RXEN\r
+ PIO_Configure(&pin_can_transceiver_rxen, PIO_LISTSIZE(pin_can_transceiver_rxen));\r
+#endif\r
+\r
+ // Enable clock for CAN PIO\r
+ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA);\r
+\r
+ // Enable the CAN0 controller peripheral clock\r
+ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_CAN0);\r
+\r
+ // disable all IT\r
+ AT91C_BASE_CAN0->CAN_IDR = 0x1FFFFFFF;\r
+\r
+ // Enable CANs Transceivers\r
+#if defined (PIN_CAN_TRANSCEIVER_RXEN)\r
+ // Disable ultra Low Power mode\r
+ PIO_Set(&pin_can_transceiver_rxen);\r
+#endif\r
+ // Normal Mode (versus Standby mode)\r
+ PIO_Clear(&pin_can_transceiver_rs);\r
+\r
+ // Configure the AIC for CAN interrupts\r
+ AIC_ConfigureIT(AT91C_ID_CAN0, AT91C_AIC_PRIOR_HIGHEST, CAN0_Handler);\r
+\r
+ // Enable the interrupt on the interrupt controller\r
+ AIC_EnableIT(AT91C_ID_CAN0);\r
+\r
+ if( CAN_BaudRateCalculate(AT91C_BASE_CAN0, baudrate) == 0 ) {\r
+ // Baudrate problem\r
+ trace_LOG( trace_DEBUG, "Baudrate CAN0 problem\n\r");\r
+ return 0;\r
+ }\r
+\r
+ pCAN0Transfer = canTransfer0;\r
+\r
+#if defined AT91C_BASE_CAN1\r
+ if( canTransfer1 != NULL ) {\r
+ pCAN1Transfer = canTransfer1;\r
+ // Enable CAN1 Clocks\r
+ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_CAN1);\r
+\r
+ // disable all IT\r
+ AT91C_BASE_CAN1->CAN_IDR = 0x1FFFFFFF;\r
+\r
+ // Configure the AIC for CAN interrupts\r
+ AIC_ConfigureIT(AT91C_ID_CAN1, AT91C_AIC_PRIOR_HIGHEST, CAN1_Handler);\r
+\r
+ // Enable the interrupt on the interrupt controller\r
+ AIC_EnableIT(AT91C_ID_CAN1);\r
+\r
+ if( CAN_BaudRateCalculate(AT91C_BASE_CAN1, baudrate) == 0 ) {\r
+ // Baudrate problem\r
+ trace_LOG( trace_DEBUG, "Baudrate CAN1 problem\n\r");\r
+ return 0;\r
+ }\r
+ }\r
+#endif\r
+ // Reset all mailbox\r
+ CAN_ResetAllMailbox();\r
+\r
+ // Enable the interrupt with all error cases\r
+ AT91C_BASE_CAN0->CAN_IER = AT91C_CAN_CERR // (CAN) CRC Error\r
+ | AT91C_CAN_SERR // (CAN) Stuffing Error\r
+ | AT91C_CAN_BERR // (CAN) Bit Error\r
+ | AT91C_CAN_FERR // (CAN) Form Error\r
+ | AT91C_CAN_AERR; // (CAN) Acknowledgment Error\r
+\r
+#if defined AT91C_BASE_CAN1\r
+ if( canTransfer1 != NULL ) {\r
+ AT91C_BASE_CAN1->CAN_IER = AT91C_CAN_CERR // (CAN) CRC Error\r
+ | AT91C_CAN_SERR // (CAN) Stuffing Error\r
+ | AT91C_CAN_BERR // (CAN) Bit Error\r
+ | AT91C_CAN_FERR // (CAN) Form Error\r
+ | AT91C_CAN_AERR; // (CAN) Acknowledgment Error\r
+ }\r
+#endif\r
+\r
+ // Wait for CAN synchronisation\r
+ if( CAN_Synchronisation( ) == 1 ) {\r
+ ret = 1;\r
+ }\r
+ else {\r
+ ret = 0;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _CAN_H\r
+#define _CAN_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+#define AT91C_CAN_TIMEOUT 100000\r
+\r
+#define AT91C_TEST_NOK 0\r
+#define AT91C_TEST_OK 1\r
+\r
+#define CAN_STATUS_SUCCESS 0\r
+#define CAN_STATUS_LOCKED 1\r
+#define CAN_STATUS_ABORTED 2\r
+#define CAN_STATUS_RESET 3\r
+\r
+#if defined (AT91C_BASE_CAN)\r
+ #define AT91C_BASE_CAN0 AT91C_BASE_CAN\r
+#endif\r
+#if defined (AT91C_ID_CAN)\r
+ #define AT91C_ID_CAN0 AT91C_ID_CAN\r
+#endif\r
+#if defined (AT91C_BASE_CAN_MB0)\r
+ #define AT91C_BASE_CAN0_MB0 AT91C_BASE_CAN_MB0\r
+ #define AT91C_BASE_CAN0_MB1 AT91C_BASE_CAN_MB1\r
+ #define AT91C_BASE_CAN0_MB2 AT91C_BASE_CAN_MB2\r
+ #define AT91C_BASE_CAN0_MB3 AT91C_BASE_CAN_MB3\r
+ #define AT91C_BASE_CAN0_MB4 AT91C_BASE_CAN_MB4\r
+ #define AT91C_BASE_CAN0_MB5 AT91C_BASE_CAN_MB5\r
+ #define AT91C_BASE_CAN0_MB6 AT91C_BASE_CAN_MB6\r
+ #define AT91C_BASE_CAN0_MB7 AT91C_BASE_CAN_MB7\r
+#endif\r
+#if defined (AT91C_BASE_CAN_MB8)\r
+ #define AT91C_BASE_CAN0_MB8 AT91C_BASE_CAN_MB8\r
+ #define AT91C_BASE_CAN0_MB9 AT91C_BASE_CAN_MB9\r
+ #define AT91C_BASE_CAN0_MB10 AT91C_BASE_CAN_MB10\r
+ #define AT91C_BASE_CAN0_MB11 AT91C_BASE_CAN_MB11\r
+ #define AT91C_BASE_CAN0_MB12 AT91C_BASE_CAN_MB12\r
+ #define AT91C_BASE_CAN0_MB13 AT91C_BASE_CAN_MB13\r
+ #define AT91C_BASE_CAN0_MB14 AT91C_BASE_CAN_MB14\r
+ #define AT91C_BASE_CAN0_MB15 AT91C_BASE_CAN_MB15\r
+#endif\r
+\r
+#define NUM_MAILBOX_MAX 16\r
+\r
+//------------------------------------------------------------------------------\r
+// Types\r
+//------------------------------------------------------------------------------\r
+typedef struct\r
+{\r
+ volatile unsigned char state;\r
+ volatile unsigned char can_number;\r
+ volatile unsigned char mailbox_number;\r
+ volatile unsigned char test_can;\r
+ volatile unsigned int mode_reg;\r
+ volatile unsigned int acceptance_mask_reg;\r
+ volatile unsigned int identifier;\r
+ volatile unsigned int data_low_reg;\r
+ volatile unsigned int data_high_reg;\r
+ volatile unsigned int control_reg;\r
+ volatile unsigned int mailbox_in_use;\r
+ volatile int size;\r
+} CanTransfer;\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+extern unsigned char CAN_Init( unsigned int baudrate, \r
+ CanTransfer *canTransferRead, \r
+ CanTransfer *canTransferWrite );\r
+extern void CAN_BasicTestSuite(void);\r
+extern void CAN_disable( void );\r
+extern void CAN_ResetAllMailbox( void );\r
+extern void CAN_ResetTransfer( CanTransfer *pTransfer );\r
+extern void CAN_InitMailboxRegisters( CanTransfer *pTransfer );\r
+extern unsigned char CAN_IsInIdle( CanTransfer *pTransfer );\r
+\r
+extern unsigned char CAN_Write( CanTransfer *pTransfer );\r
+extern unsigned char CAN_Read( CanTransfer *pTransfer );\r
+\r
+extern void CAN_BasicTestSuiteWithoutInterrupt( void );\r
+extern unsigned char CAN_IsInIdle( CanTransfer *pTransfer );\r
+#endif // _CAN_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "dbgu.h"\r
+#include <stdarg.h>\r
+#include <board.h>\r
+ \r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// Initializes the DBGU with the given parameters, and enables both the\r
+/// transmitter and the receiver.\r
+/// \param mode Operating mode to configure (see <Modes>).\r
+/// \param baudrate Desired baudrate.\r
+/// \param mck Frequency of the system master clock.\r
+//------------------------------------------------------------------------------\r
+void DBGU_Configure(unsigned int mode,\r
+ unsigned int baudrate,\r
+ unsigned int mck)\r
+{ \r
+ // Reset & disable receiver and transmitter, disable interrupts\r
+ AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTRX | AT91C_US_RSTTX;\r
+ AT91C_BASE_DBGU->DBGU_IDR = 0xFFFFFFFF;\r
+ \r
+ // Configure baud rate\r
+ AT91C_BASE_DBGU->DBGU_BRGR = mck / (baudrate * 16);\r
+ \r
+ // Configure mode register\r
+ AT91C_BASE_DBGU->DBGU_MR = mode;\r
+ \r
+ // Disable DMA channel\r
+ AT91C_BASE_DBGU->DBGU_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;\r
+\r
+ // Enable receiver and transmitter\r
+ AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Outputs a character on the DBGU line.\r
+/// \param c Character to send.\r
+//------------------------------------------------------------------------------\r
+static void DBGU_PutChar(unsigned char c)\r
+{\r
+ // Wait for the transmitter to be ready\r
+ while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXEMPTY) == 0);\r
+ \r
+ // Send character\r
+ AT91C_BASE_DBGU->DBGU_THR = c;\r
+ \r
+ // Wait for the transfer to complete\r
+ while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXEMPTY) == 0);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Reads and returns a character from the DBGU.\r
+//------------------------------------------------------------------------------\r
+unsigned char DBGU_GetChar()\r
+{\r
+ while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_RXRDY) == 0);\r
+ return AT91C_BASE_DBGU->DBGU_RHR;\r
+}\r
+\r
+#ifndef NOFPUT\r
+\r
+#include <stdio.h>\r
+\r
+//------------------------------------------------------------------------------\r
+/// Implementation of fputc using the DBGU as the standard output. Required\r
+/// for printf().\r
+/// Returns the character written if successful, or -1 if the output stream is\r
+/// not stdout or stderr.\r
+/// \param c Character to write.\r
+/// \param pStream Output stream.\r
+//------------------------------------------------------------------------------\r
+signed int fputc(signed int c, FILE *pStream)\r
+{\r
+ if ((pStream == stdout) || (pStream == stderr)) {\r
+ \r
+ DBGU_PutChar(c);\r
+ return c;\r
+ }\r
+ else {\r
+\r
+ return EOF;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Implementation of fputs using the DBGU as the standard output. Required\r
+/// for printf(). Does NOT currently use the PDC.\r
+/// Returns the number of characters written if successful, or -1 if the output\r
+/// stream is not stdout or stderr.\r
+/// \param pStr String to write.\r
+/// \param pStream Output stream.\r
+//------------------------------------------------------------------------------\r
+signed int fputs(const char *pStr, FILE *pStream)\r
+{\r
+ signed int num = 0;\r
+\r
+ while (*pStr != 0) {\r
+\r
+ if (fputc(*pStr, pStream) == -1) {\r
+\r
+ return -1;\r
+ }\r
+ num++;\r
+ pStr++;\r
+ }\r
+\r
+ return num;\r
+}\r
+\r
+#undef putchar\r
+\r
+//------------------------------------------------------------------------------\r
+/// Outputs a character on the DBGU. Returns the character itself.\r
+/// \param c Character to output.\r
+//------------------------------------------------------------------------------\r
+signed int putchar(signed int c)\r
+{\r
+ return fputc(c, stdout);\r
+}\r
+\r
+#endif //#ifndef NOFPUT\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \dir\r
+/// !Purpose\r
+/// \r
+/// This module provides definitions and functions for using the DBGU.\r
+///\r
+/// !Usage\r
+/// \r
+/// -# Enable the DBGU pins (see pio.h).\r
+/// -# Configure the DBGU using DBGU_Configure.\r
+///\r
+/// \note Unless specified, all the functions defined here operate synchronously;\r
+/// i.e. they all wait the data is sent/received before returning.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef DBGU_H\r
+#define DBGU_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page Modes\r
+/// This page lists several common operating modes for the DBGU.\r
+/// !Modes\r
+/// - DBGU_STANDARD\r
+ \r
+/// Standard operating mode (asynchronous, 8bit, no parity)\r
+#define DBGU_STANDARD AT91C_US_PAR_NONE\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+extern void DBGU_Configure(unsigned int mode,\r
+ unsigned int baudrate,\r
+ unsigned int mck);\r
+\r
+extern unsigned char DBGU_GetChar();\r
+\r
+#endif //#ifndef DBGU_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef trace_LEVEL\r
+ #define trace_LEVEL trace_INFO\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "eefc.h"\r
+\r
+#ifdef BOARD_FLASH_EEFC\r
+\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the flash ready interrupt source on the EEFC peripheral.\r
+//------------------------------------------------------------------------------\r
+void EFC_EnableFrdyIt(void)\r
+{\r
+ AT91C_BASE_EFC->EFC_FMR |= AT91C_EFC_FRDY;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the flash ready interrupt source on the EEFC peripheral.\r
+//------------------------------------------------------------------------------\r
+void EFC_DisableFrdyIt(void)\r
+{\r
+ AT91C_BASE_EFC->EFC_FMR &= ~AT91C_EFC_FRDY;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Translates the given address page and offset values. The resulting\r
+/// values are stored in the provided variables if they are not null.\r
+/// \param address Address to translate.\r
+/// \param pPage First page accessed.\r
+/// \param pOffset Byte offset in first page.\r
+//------------------------------------------------------------------------------\r
+void EFC_TranslateAddress(\r
+ unsigned int address,\r
+ unsigned short *pPage,\r
+ unsigned short *pOffset)\r
+{\r
+ unsigned short page;\r
+ unsigned short offset;\r
+\r
+ SANITY_CHECK(address >= AT91C_IFLASH);\r
+ SANITY_CHECK(address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE));\r
+\r
+ // Calculate page & offset\r
+ page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE;\r
+ offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE;\r
+ trace_LOG(trace_DEBUG,\r
+ "-D- Translated 0x%08X to page=%d and offset=%d\n\r",\r
+ address, page, offset);\r
+\r
+ // Store values\r
+ if (pPage) {\r
+\r
+ *pPage = page;\r
+ }\r
+ if (pOffset) {\r
+\r
+ *pOffset = offset;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Computes the address of a flash access given the page and offset.\r
+/// \param page Page number.\r
+/// \param offset Byte offset inside page.\r
+/// \param pAddress Computed address (optional).\r
+//------------------------------------------------------------------------------\r
+void EFC_ComputeAddress(\r
+ unsigned short page,\r
+ unsigned short offset,\r
+ unsigned int *pAddress)\r
+{\r
+ unsigned int address;\r
+\r
+ SANITY_CHECK(page <= AT91C_IFLASH_NB_OF_PAGES);\r
+ SANITY_CHECK(offset < AT91C_IFLASH_PAGE_SIZE);\r
+\r
+ // Compute address\r
+ address = AT91C_IFLASH + page * AT91C_IFLASH_PAGE_SIZE + offset;\r
+\r
+ // Store result\r
+ if (pAddress) {\r
+\r
+ *pAddress = address;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts the executing the given command on the EEFC. This function returns\r
+/// as soon as the command is started. It does NOT set the FMCN field automatically.\r
+/// \param command Command to execute.\r
+/// \param argument Command argument (should be 0 if not used).\r
+//------------------------------------------------------------------------------\r
+void EFC_StartCommand(unsigned char command, unsigned short argument)\r
+{\r
+ // Check command & argument\r
+ switch (command) {\r
+\r
+ case AT91C_EFC_FCMD_WP:\r
+ case AT91C_EFC_FCMD_WPL:\r
+ case AT91C_EFC_FCMD_EWP: \r
+ case AT91C_EFC_FCMD_EWPL:\r
+ case AT91C_EFC_FCMD_EPL:\r
+ case AT91C_EFC_FCMD_EPA:\r
+ case AT91C_EFC_FCMD_SLB:\r
+ case AT91C_EFC_FCMD_CLB:\r
+ ASSERT(argument < AT91C_IFLASH_NB_OF_PAGES,\r
+ "-F- Embedded flash has only %d pages\n\r",\r
+ AT91C_IFLASH_NB_OF_PAGES);\r
+ break;\r
+\r
+ case AT91C_EFC_FCMD_SFB:\r
+ case AT91C_EFC_FCMD_CFB:\r
+ ASSERT(argument < EFC_NUM_GPNVMS, "-F- Embedded flash has only %d GPNVMs\n\r", EFC_NUM_GPNVMS);\r
+ break;\r
+\r
+ case AT91C_EFC_FCMD_GETD:\r
+ case AT91C_EFC_FCMD_EA:\r
+ case AT91C_EFC_FCMD_GLB:\r
+ case AT91C_EFC_FCMD_GFB:\r
+ ASSERT(argument == 0, "-F- Argument is meaningless for the given command.\n\r");\r
+ break;\r
+\r
+ default: ASSERT(0, "-F- Unknown command %d\n\r", command);\r
+ }\r
+\r
+ // Start commandEmbedded flash \r
+ ASSERT((AT91C_BASE_EFC->EFC_FSR & AT91C_EFC_FRDY) == AT91C_EFC_FRDY, "-F- EEFC is not ready\n\r");\r
+ AT91C_BASE_EFC->EFC_FCR = (0x5A << 24) | (argument << 8) | command;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Performs the given command and wait until its completion (or an error).\r
+/// Returns 0 if successful; otherwise returns an error code.\r
+/// \param command Command to perform.\r
+/// \param argument Optional command argument.\r
+//------------------------------------------------------------------------------\r
+#ifdef __ICCARM__\r
+__ramfunc\r
+#else\r
+__attribute__ ((section (".ramfunc")))\r
+#endif\r
+unsigned char EFC_PerformCommand(unsigned char command, unsigned short argument)\r
+{\r
+ unsigned int status;\r
+\r
+#ifdef BOARD_FLASH_IAP_ADDRESS\r
+ // Pointer on IAP function in ROM\r
+ static void (*IAP_PerformCommand)(unsigned int);\r
+ IAP_PerformCommand = (void (*)(unsigned int)) *((unsigned int *) BOARD_FLASH_IAP_ADDRESS);\r
+\r
+ // Check if IAP function is implemented (opcode in SWI != 'b' or 'ldr') */\r
+ if ((((((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xEA) &&\r
+ (((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xE5)) {\r
+\r
+ IAP_PerformCommand((0x5A << 24) | (argument << 8) | command);\r
+ return (AT91C_BASE_EFC->EFC_FSR & (AT91C_EFC_LOCKE | AT91C_EFC_FCMDE));\r
+ }\r
+#endif\r
+\r
+ AT91C_BASE_EFC->EFC_FCR = (0x5A << 24) | (argument << 8) | command;\r
+ do {\r
+\r
+ status = AT91C_BASE_EFC->EFC_FSR;\r
+ }\r
+ while ((status & AT91C_EFC_FRDY) != AT91C_EFC_FRDY);\r
+\r
+ return (status & (AT91C_EFC_LOCKE | AT91C_EFC_FCMDE));\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the current status of the EEFC. Keep in mind that this function clears\r
+/// the value of some status bits (LOCKE, PROGE).\r
+//------------------------------------------------------------------------------\r
+unsigned int EFC_GetStatus(void)\r
+{\r
+ return AT91C_BASE_EFC->EFC_FSR;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the result of the last executed command.\r
+//------------------------------------------------------------------------------\r
+unsigned int EFC_GetResult(void) {\r
+\r
+ return AT91C_BASE_EFC->EFC_FRR;\r
+}\r
+\r
+#endif //#ifdef BOARD_FLASH_EEFC\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef EEFC_H\r
+#define EEFC_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+#ifdef BOARD_FLASH_EEFC\r
+\r
+//------------------------------------------------------------------------------\r
+// Constants\r
+//------------------------------------------------------------------------------\r
+\r
+/// Number of GPNVMs available on each chip.\r
+#if defined(at91sam7l64) || defined(at91sam7l128)\r
+\r
+ #define EFC_NUM_GPNVMS 2\r
+\r
+#elif defined(at91sam9xe128) || defined(at91sam9xe256) || defined(at91sam9xe512)\r
+\r
+ #define EFC_NUM_GPNVMS 17\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Types\r
+//------------------------------------------------------------------------------\r
+\r
+// Needed when EEFC is integrated in MC.\r
+#if !defined(AT91C_BASE_EFC) && defined(AT91C_BASE_MC)\r
+typedef struct _AT91S_EFC {\r
+ AT91_REG EFC_FMR; // EFC Flash Mode Register\r
+ AT91_REG EFC_FCR; // EFC Flash Command Register\r
+ AT91_REG EFC_FSR; // EFC Flash Status Register\r
+ AT91_REG EFC_FRR; // EFC Flash Result Register\r
+ AT91_REG EFC_FVR; // EFC Flash Version Register\r
+} AT91S_EFC, *AT91PS_EFC;\r
+\r
+#define AT91C_EFC_FRDY AT91C_MC_FRDY\r
+#define AT91C_EFC_FWS AT91C_MC_FWS\r
+#define AT91C_EFC_FWS_0WS AT91C_MC_FWS_0WS\r
+#define AT91C_EFC_FWS_1WS AT91C_MC_FWS_1WS\r
+#define AT91C_EFC_FWS_2WS AT91C_MC_FWS_2WS\r
+#define AT91C_EFC_FWS_3WS AT91C_MC_FWS_3WS\r
+#define AT91C_EFC_FCMD AT91C_MC_FCMD\r
+#define AT91C_EFC_FCMD_GETD AT91C_MC_FCMD_GETD\r
+#define AT91C_EFC_FCMD_WP AT91C_MC_FCMD_WP \r
+#define AT91C_EFC_FCMD_WPL AT91C_MC_FCMD_WPL \r
+#define AT91C_EFC_FCMD_EWP AT91C_MC_FCMD_EWP \r
+#define AT91C_EFC_FCMD_EWPL AT91C_MC_FCMD_EWPL\r
+#define AT91C_EFC_FCMD_EA AT91C_MC_FCMD_EA \r
+#define AT91C_EFC_FCMD_EPL AT91C_MC_FCMD_EPL \r
+#define AT91C_EFC_FCMD_EPA AT91C_MC_FCMD_EPA \r
+#define AT91C_EFC_FCMD_SLB AT91C_MC_FCMD_SLB \r
+#define AT91C_EFC_FCMD_CLB AT91C_MC_FCMD_CLB \r
+#define AT91C_EFC_FCMD_GLB AT91C_MC_FCMD_GLB \r
+#define AT91C_EFC_FCMD_SFB AT91C_MC_FCMD_SFB \r
+#define AT91C_EFC_FCMD_CFB AT91C_MC_FCMD_CFB \r
+#define AT91C_EFC_FCMD_GFB AT91C_MC_FCMD_GFB \r
+#define AT91C_EFC_FARG AT91C_MC_FARG \r
+#define AT91C_EFC_FKEY AT91C_MC_FKEY \r
+#define AT91C_EFC_FRDY_S AT91C_MC_FRDY_S \r
+#define AT91C_EFC_FCMDE AT91C_MC_FCMDE \r
+#define AT91C_EFC_LOCKE AT91C_MC_LOCKE \r
+#define AT91C_EFC_FVALUE AT91C_MC_FVALUE \r
+\r
+#define AT91C_BASE_EFC (AT91_CAST(AT91PS_EFC) 0xFFFFFF60) \r
+\r
+#endif //#if !defined(AT91C_BASE_EFC) && defined(AT91C_BASE_MC)\r
+\r
+//------------------------------------------------------------------------------\r
+// Functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void EFC_EnableFrdyIt(void);\r
+\r
+extern void EFC_DisableFrdyIt(void);\r
+\r
+extern void EFC_TranslateAddress(\r
+ unsigned int address,\r
+ unsigned short *pPage,\r
+ unsigned short *pOffset);\r
+\r
+extern void EFC_ComputeAddress(\r
+ unsigned short page,\r
+ unsigned short offset,\r
+ unsigned int *pAddress);\r
+\r
+extern void EFC_StartCommand(\r
+ unsigned char command,\r
+ unsigned short argument);\r
+\r
+extern unsigned char EFC_PerformCommand(\r
+ unsigned char command,\r
+ unsigned short argument);\r
+\r
+extern unsigned int EFC_GetStatus(void);\r
+\r
+extern unsigned int EFC_GetResult(void);\r
+\r
+#endif //#ifdef BOARD_FLASH_EEFC\r
+#endif //#ifndef EEFC_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef trace_LEVEL\r
+ #define trace_LEVEL trace_INFO\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "efc.h"\r
+\r
+#ifdef BOARD_FLASH_EFC\r
+\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Local definitions\r
+//------------------------------------------------------------------------------\r
+\r
+// Round a number to the nearest integral value (number must have been\r
+// multiplied by 10, e.g. to round 10.3 enter 103).\r
+#define ROUND(n) ((((n) % 10) >= 5) ? (((n) / 10) + 1) : ((n) / 10))\r
+\r
+// Returns the FMCN field value when manipulating lock bits, given MCK.\r
+#if defined(at91sam7a3)\r
+ #define FMCN_BITS(mck) (ROUND((mck) / 100000) << 16) // <- Not correct according to the datasheet but it works\r
+#else\r
+ #define FMCN_BITS(mck) (ROUND((mck) / 100000) << 16)\r
+#endif\r
+\r
+// Returns the FMCN field value when manipulating the rest of the flash.\r
+#define FMCN_FLASH(mck) ((((mck) / 2000000) * 3) << 16)\r
+\r
+//------------------------------------------------------------------------------\r
+// Local functions\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+/// Master clock frequency, used to infer the value of the FMCN field.\r
+static unsigned int lMck;\r
+/// Calculated value of the FMCN field base on Master clock frequency.\r
+static unsigned int lMckFMCN;\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the system master clock so the FMCN field of the EFC(s) can be\r
+/// programmed properly.\r
+/// \param mck Master clock frequency in Hz.\r
+//------------------------------------------------------------------------------\r
+void EFC_SetMasterClock(unsigned int mck)\r
+{\r
+ lMck = mck;\r
+ lMckFMCN = FMCN_BITS(lMck);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the given interrupt sources on an EFC peripheral.\r
+/// \param pEfc Pointer to an AT91S_EFC structure.\r
+/// \param sources Interrupt sources to enable.\r
+//------------------------------------------------------------------------------\r
+void EFC_EnableIt(AT91S_EFC *pEfc, unsigned int sources)\r
+{\r
+ SANITY_CHECK(pEfc);\r
+ SANITY_CHECK((sources & ~0x0000000D) == 0);\r
+\r
+ pEfc->EFC_FMR |= sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the given interrupt sources on an EFC peripheral.\r
+/// \param pEfc Pointer to an AT91S_EFC structure.\r
+/// \param sources Interrupt sources to disable.\r
+//------------------------------------------------------------------------------\r
+void EFC_DisableIt(AT91S_EFC *pEfc, unsigned int sources)\r
+{\r
+ SANITY_CHECK(pEfc);\r
+ SANITY_CHECK((sources & ~(AT91C_MC_FRDY | AT91C_MC_LOCKE | AT91C_MC_PROGE)) == 0);\r
+\r
+ pEfc->EFC_FMR &= ~sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables or disable the "Erase before programming" feature of an EFC.\r
+/// \param pEfc Pointer to an AT91S_EFC structure.\r
+/// \param enable If 1, the feature is enabled; otherwise it is disabled.\r
+//------------------------------------------------------------------------------\r
+void EFC_SetEraseBeforeProgramming(AT91S_EFC *pEfc, unsigned char enable)\r
+{\r
+ SANITY_CHECK(pEfc);\r
+\r
+ if (enable) {\r
+\r
+ pEfc->EFC_FMR &= ~AT91C_MC_NEBP;\r
+ }\r
+ else {\r
+\r
+ pEfc->EFC_FMR |= AT91C_MC_NEBP;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Translates the given address into EFC, page and offset values. The resulting\r
+/// values are stored in the provided variables if they are not null.\r
+/// \param address Address to translate.\r
+/// \param ppEfc Pointer to target EFC peripheral.\r
+/// \param pPage First page accessed.\r
+/// \param pOffset Byte offset in first page.\r
+//------------------------------------------------------------------------------\r
+void EFC_TranslateAddress(\r
+ unsigned int address,\r
+ AT91S_EFC **ppEfc,\r
+ unsigned short *pPage,\r
+ unsigned short *pOffset)\r
+{\r
+ AT91S_EFC *pEfc;\r
+ unsigned short page;\r
+ unsigned short offset;\r
+\r
+ SANITY_CHECK(address >= AT91C_IFLASH);\r
+ SANITY_CHECK(address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE));\r
+\r
+#if defined(AT91C_BASE_EFC0)\r
+ if (address >= (AT91C_IFLASH + AT91C_IFLASH_SIZE / 2)) {\r
+\r
+ pEfc = AT91C_BASE_EFC1;\r
+ page = (address - AT91C_IFLASH - AT91C_IFLASH_SIZE / 2) / AT91C_IFLASH_PAGE_SIZE;\r
+ offset = (address - AT91C_IFLASH - AT91C_IFLASH_SIZE / 2) % AT91C_IFLASH_PAGE_SIZE;\r
+ }\r
+ else {\r
+\r
+ pEfc = AT91C_BASE_EFC0;\r
+ page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE;\r
+ offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE;\r
+ }\r
+#else\r
+ pEfc = AT91C_BASE_EFC;\r
+ page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE;\r
+ offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE;\r
+#endif\r
+ trace_LOG(trace_DEBUG,\r
+ "-D- Translated 0x%08X to EFC=0x%08X, page=%d and offset=%d\n\r",\r
+ address, (unsigned int) pEfc, page, offset);\r
+\r
+ // Store values\r
+ if (ppEfc) {\r
+\r
+ *ppEfc = pEfc;\r
+ }\r
+ if (pPage) {\r
+\r
+ *pPage = page;\r
+ }\r
+ if (pOffset) {\r
+\r
+ *pOffset = offset;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Computes the address of a flash access given the EFC, page and offset.\r
+/// \param pEfc Pointer to an AT91S_EFC structure.\r
+/// \param page Page number.\r
+/// \param offset Byte offset inside page.\r
+/// \param pAddress Computed address (optional).\r
+//------------------------------------------------------------------------------\r
+void EFC_ComputeAddress(\r
+ AT91S_EFC *pEfc,\r
+ unsigned short page,\r
+ unsigned short offset,\r
+ unsigned int *pAddress)\r
+{\r
+ unsigned int address;\r
+\r
+ SANITY_CHECK(pEfc);\r
+#if defined(AT91C_BASE_EFC1)\r
+ SANITY_CHECK(page <= (AT91C_IFLASH_NB_OF_PAGES / 2));\r
+#else\r
+ SANITY_CHECK(page <= AT91C_IFLASH_NB_OF_PAGES);\r
+#endif\r
+ SANITY_CHECK(offset < AT91C_IFLASH_PAGE_SIZE);\r
+\r
+ // Compute address\r
+ address = AT91C_IFLASH + page * AT91C_IFLASH_PAGE_SIZE + offset;\r
+#if defined(AT91C_BASE_EFC1)\r
+ if (pEfc == AT91C_BASE_EFC1) {\r
+\r
+ address += AT91C_IFLASH_SIZE / 2;\r
+ }\r
+#endif\r
+\r
+ // Store result\r
+ if (pAddress) {\r
+\r
+ *pAddress = address;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts the executing the given command on an EFC. This function returns\r
+/// as soon as the command is started. It does NOT set the FMCN field automatically.\r
+/// \param pEfc Pointer to an AT91S_EFC structure.\r
+/// \param command Command to execute.\r
+/// \param argument Command argument (should be 0 if not used).\r
+//------------------------------------------------------------------------------\r
+void EFC_StartCommand(\r
+ AT91S_EFC *pEfc,\r
+ unsigned char command,\r
+ unsigned short argument)\r
+{\r
+ SANITY_CHECK(pEfc);\r
+ ASSERT(lMck != 0, "-F- Master clock not set.\n\r");\r
+\r
+ // Check command & argument\r
+ switch (command) {\r
+\r
+ case AT91C_MC_FCMD_PROG_AND_LOCK:\r
+ ASSERT(0, "-F- Write and lock command cannot be carried out.\n\r");\r
+ break;\r
+\r
+ case AT91C_MC_FCMD_START_PROG:\r
+ case AT91C_MC_FCMD_LOCK:\r
+ case AT91C_MC_FCMD_UNLOCK:\r
+ ASSERT(argument < AT91C_IFLASH_NB_OF_PAGES,\r
+ "-F- Maximum number of pages is %d (argument was %d)\n\r",\r
+ AT91C_IFLASH_NB_OF_PAGES,\r
+ argument);\r
+ break;\r
+\r
+#if (EFC_NUM_GPNVMS > 0)\r
+ case AT91C_MC_FCMD_SET_GP_NVM:\r
+ case AT91C_MC_FCMD_CLR_GP_NVM:\r
+ ASSERT(argument < EFC_NUM_GPNVMS, "-F- A maximum of %d GPNVMs are available on the chip.\n\r", EFC_NUM_GPNVMS);\r
+ break;\r
+#endif\r
+\r
+ case AT91C_MC_FCMD_ERASE_ALL:\r
+\r
+#if !defined(EFC_NO_SECURITY_BIT)\r
+ case AT91C_MC_FCMD_SET_SECURITY:\r
+#endif\r
+ ASSERT(argument == 0, "-F- Argument is meaningless for the given command\n\r");\r
+ break;\r
+\r
+ default: ASSERT(0, "-F- Unknown command %d\n\r", command);\r
+ }\r
+\r
+ // Set FMCN\r
+ switch (command) {\r
+\r
+ case AT91C_MC_FCMD_LOCK:\r
+ case AT91C_MC_FCMD_UNLOCK:\r
+#if (EFC_NUM_GPNVMS > 0)\r
+ case AT91C_MC_FCMD_SET_GP_NVM:\r
+ case AT91C_MC_FCMD_CLR_GP_NVM:\r
+#endif\r
+#if !defined(EFC_NO_SECURITY_BIT)\r
+ case AT91C_MC_FCMD_SET_SECURITY:\r
+#endif\r
+ pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN;\r
+ break;\r
+\r
+ case AT91C_MC_FCMD_START_PROG:\r
+ case AT91C_MC_FCMD_ERASE_ALL:\r
+ pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN;\r
+ break;\r
+ }\r
+\r
+ // Start command\r
+ ASSERT((pEfc->EFC_FSR & AT91C_MC_FRDY) != 0, "-F- Efc is not ready\n\r");\r
+ pEfc->EFC_FCR = (0x5A << 24) | (argument << 8) | command;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Performs the given command and wait until its completion (or an error).\r
+/// Returns 0 if successful; otherwise returns an error code.\r
+/// \param pEfc Pointer to an AT91S_EFC structure.\r
+/// \param command Command to perform.\r
+/// \param argument Optional command argument.\r
+//------------------------------------------------------------------------------\r
+#ifdef __ICCARM__\r
+__ramfunc\r
+#else\r
+__attribute__ ((section (".ramfunc")))\r
+#endif\r
+unsigned char EFC_PerformCommand(\r
+ AT91S_EFC *pEfc,\r
+ unsigned char command,\r
+ unsigned short argument)\r
+{\r
+ unsigned int status;\r
+\r
+ // Set FMCN\r
+ switch (command) {\r
+\r
+ case AT91C_MC_FCMD_LOCK:\r
+ case AT91C_MC_FCMD_UNLOCK:\r
+#if (EFC_NUM_GPNVMS > 0)\r
+ case AT91C_MC_FCMD_SET_GP_NVM:\r
+ case AT91C_MC_FCMD_CLR_GP_NVM:\r
+#endif\r
+#if !defined(EFC_NO_SECURITY_BIT)\r
+ case AT91C_MC_FCMD_SET_SECURITY:\r
+#endif\r
+ pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN;\r
+ break;\r
+\r
+ case AT91C_MC_FCMD_START_PROG:\r
+ case AT91C_MC_FCMD_ERASE_ALL:\r
+ pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN;\r
+ break;\r
+ }\r
+\r
+#ifdef BOARD_FLASH_IAP_ADDRESS\r
+ // Pointer on IAP function in ROM\r
+ static void (*IAP_PerformCommand)(unsigned int, unsigned int);\r
+ unsigned int index = 0;\r
+#ifdef AT91C_BASE_EFC1\r
+ if (pEfc == AT91C_BASE_EFC1) {\r
+\r
+ index = 1;\r
+ }\r
+#endif\r
+ IAP_PerformCommand = (void (*)(unsigned int, unsigned int)) *((unsigned int *) BOARD_FLASH_IAP_ADDRESS);\r
+\r
+ // Check if IAP function is implemented (opcode in SWI != 'b' or 'ldr') */\r
+ if ((((((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xEA) &&\r
+ (((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xE5)) {\r
+\r
+ IAP_PerformCommand(index, (0x5A << 24) | (argument << 8) | command);\r
+ return (pEfc->EFC_FSR & (AT91C_MC_LOCKE | AT91C_MC_PROGE));\r
+ }\r
+#endif\r
+\r
+ pEfc->EFC_FCR = (0x5A << 24) | (argument << 8) | command;\r
+ do {\r
+\r
+ status = pEfc->EFC_FSR;\r
+ }\r
+ while ((status & AT91C_MC_FRDY) == 0);\r
+\r
+ return (status & (AT91C_MC_PROGE | AT91C_MC_LOCKE));\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the current status of an EFC. Keep in mind that this function clears\r
+/// the value of some status bits (LOCKE, PROGE).\r
+/// \param pEfc Pointer to an AT91S_EFC structure.\r
+//------------------------------------------------------------------------------\r
+unsigned int EFC_GetStatus(AT91S_EFC *pEfc)\r
+{\r
+ return pEfc->EFC_FSR;\r
+}\r
+\r
+#endif //#ifdef BOARD_FLASH_EFC\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef EFC_H\r
+#define EFC_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+#ifdef BOARD_FLASH_EFC\r
+\r
+//------------------------------------------------------------------------------\r
+// Constants\r
+//------------------------------------------------------------------------------\r
+\r
+/// Number of GPNVMs available on each chip.\r
+#if defined(at91sam7s16) || defined(at91sam7s161) || defined(at91sam7s32) \\r
+ || defined(at91sam7s321) || defined(at91sam7s64) || defined(at91sam7s128) \\r
+ || defined(at91sam7s256) || defined(at91sam7s512)\r
+\r
+ #define EFC_NUM_GPNVMS 2\r
+\r
+#elif defined(at91sam7se32) || defined(at91sam7se256) || defined(at91sam7se512) \\r
+ || defined(at91sam7x128) || defined(at91sam7x256) || defined(at91sam7x512) \\r
+ || defined(at91sam7xc128) || defined(at91sam7xc256) || defined(at91sam7xc512) \\r
+\r
+ #define EFC_NUM_GPNVMS 3\r
+\r
+#elif defined(at91sam7a3)\r
+\r
+ #define EFC_NUM_GPNVMS 0\r
+#endif\r
+\r
+// Missing FRDY bit for SAM7A3\r
+#if defined(at91sam7a3)\r
+ #define AT91C_MC_FRDY (AT91C_MC_EOP | AT91C_MC_EOL)\r
+#endif\r
+\r
+// No security bit on SAM7A3\r
+#if defined(at91sam7a3)\r
+ #define EFC_NO_SECURITY_BIT\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Types\r
+//------------------------------------------------------------------------------\r
+\r
+// For chips which do not define AT91S_EFC\r
+#if !defined(AT91C_BASE_EFC) && !defined(AT91C_BASE_EFC0)\r
+typedef struct _AT91S_EFC {\r
+\r
+ AT91_REG EFC_FMR;\r
+ AT91_REG EFC_FCR;\r
+ AT91_REG EFC_FSR;\r
+\r
+} AT91S_EFC, *AT91PS_EFC;\r
+ #define AT91C_BASE_EFC (AT91_CAST(AT91PS_EFC) 0xFFFFFF60) \r
+#endif \r
+\r
+//------------------------------------------------------------------------------\r
+// Functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void EFC_SetMasterClock(unsigned int mck);\r
+\r
+extern void EFC_EnableIt(AT91S_EFC *pEfc, unsigned int sources);\r
+\r
+extern void EFC_DisableIt(AT91S_EFC *pEfc, unsigned int sources);\r
+\r
+extern void EFC_SetEraseBeforeProgramming(AT91S_EFC *pEfc, unsigned char enable);\r
+\r
+extern void EFC_TranslateAddress(\r
+ unsigned int address,\r
+ AT91S_EFC **ppEfc,\r
+ unsigned short *pPage,\r
+ unsigned short *pOffset);\r
+\r
+extern void EFC_ComputeAddress(\r
+ AT91S_EFC *pEfc,\r
+ unsigned short page,\r
+ unsigned short offset,\r
+ unsigned int *pAddress);\r
+\r
+extern void EFC_StartCommand(\r
+ AT91S_EFC *pEfc,\r
+ unsigned char command,\r
+ unsigned short argument);\r
+\r
+extern unsigned char EFC_PerformCommand(\r
+ AT91S_EFC *pEfc,\r
+ unsigned char command,\r
+ unsigned short argument);\r
+\r
+extern unsigned int EFC_GetStatus(AT91S_EFC *pEfc);\r
+\r
+#endif //#ifdef BOARD_FLASH_EFC\r
+#endif //#ifndef EFC_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//-----------------------------------------------------------------------------\r
+// Headers\r
+//-----------------------------------------------------------------------------\r
+#include <board.h>\r
+#include "emac.h"\r
+#include <utility/trace.h>\r
+#include <utility/assert.h>\r
+#include <string.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+/// The buffer addresses written into the descriptors must be aligned so the\r
+/// last few bits are zero. These bits have special meaning for the EMAC\r
+/// peripheral and cannot be used as part of the address.\r
+#define EMAC_ADDRESS_MASK ((unsigned int)0xFFFFFFFC)\r
+#define EMAC_LENGTH_FRAME ((unsigned int)0x0FFF) /// Length of frame mask\r
+\r
+// receive buffer descriptor bits\r
+#define EMAC_RX_OWNERSHIP_BIT (1UL << 0)\r
+#define EMAC_RX_WRAP_BIT (1UL << 1)\r
+#define EMAC_RX_SOF_BIT (1UL << 14)\r
+#define EMAC_RX_EOF_BIT (1UL << 15)\r
+\r
+// Transmit buffer descriptor bits\r
+#define EMAC_TX_LAST_BUFFER_BIT (1UL << 15)\r
+#define EMAC_TX_WRAP_BIT (1UL << 30)\r
+#define EMAC_TX_USED_BIT (1UL << 31)\r
+\r
+//-----------------------------------------------------------------------------\r
+// Circular buffer management\r
+//-----------------------------------------------------------------------------\r
+// Return count in buffer\r
+#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1))\r
+\r
+// Return space available, 0..size-1\r
+// We always leave one free char as a completely full buffer\r
+// has head == tail, which is the same as empty\r
+#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))\r
+\r
+// Return count up to the end of the buffer.\r
+// Carefully avoid accessing head and tail more than once,\r
+// so they can change underneath us without returning inconsistent results\r
+#define CIRC_CNT_TO_END(head,tail,size) \\r
+ ({int end = (size) - (tail); \\r
+ int n = ((head) + end) & ((size)-1); \\r
+ n < end ? n : end;})\r
+\r
+// Return space available up to the end of the buffer\r
+#define CIRC_SPACE_TO_END(head,tail,size) \\r
+ ({int end = (size) - 1 - (head); \\r
+ int n = (end + (tail)) & ((size)-1); \\r
+ n <= end ? n : end+1;})\r
+\r
+// Increment head or tail\r
+#define CIRC_INC(headortail,size) \\r
+ headortail++; \\r
+ if(headortail >= size) { \\r
+ headortail = 0; \\r
+ }\r
+\r
+#define CIRC_EMPTY(circ) ((circ)->head == (circ)->tail)\r
+#define CIRC_CLEAR(circ) ((circ)->head = (circ)->tail = 0)\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+// Structures\r
+//------------------------------------------------------------------------------\r
+#ifdef __ICCARM__ // IAR\r
+#pragma pack(4) // IAR\r
+#define __attribute__(...) // IAR\r
+#endif // IAR\r
+/// Describes the type and attribute of Receive Transfer descriptor.\r
+typedef struct _EmacRxTDescriptor {\r
+ unsigned int addr;\r
+ unsigned int status;\r
+} __attribute__((packed, aligned(8))) EmacRxTDescriptor, *PEmacRxTDescriptor;\r
+\r
+/// Describes the type and attribute of Transmit Transfer descriptor.\r
+typedef struct _EmacTxTDescriptor {\r
+ unsigned int addr;\r
+ unsigned int status;\r
+} __attribute__((packed, aligned(8))) EmacTxTDescriptor, *PEmacTxTDescriptor;\r
+#ifdef __ICCARM__ // IAR\r
+#pragma pack() // IAR\r
+#endif // IAR\r
+\r
+/// Descriptors for RX (required aligned by 8)\r
+typedef struct {\r
+ volatile EmacRxTDescriptor td[RX_BUFFERS];\r
+ EMAC_RxCallback rxCb; /// Callback function to be invoked once a frame has been received\r
+ unsigned short idx;\r
+} RxTd;\r
+\r
+/// Descriptors for TX (required aligned by 8)\r
+typedef struct {\r
+ volatile EmacTxTDescriptor td[TX_BUFFERS];\r
+ EMAC_TxCallback txCb[TX_BUFFERS]; /// Callback function to be invoked once TD has been processed\r
+ EMAC_WakeupCallback wakeupCb; /// Callback function to be invoked once several TD have been released\r
+ unsigned short wakeupThreshold; /// Number of free TD before wakeupCb is invoked\r
+ unsigned short head; /// Circular buffer head pointer incremented by the upper layer (buffer to be sent)\r
+ unsigned short tail; /// Circular buffer head pointer incremented by the IT handler (buffer sent)\r
+} TxTd;\r
+\r
+//------------------------------------------------------------------------------\r
+// Internal variables\r
+//------------------------------------------------------------------------------\r
+// Receive Transfer Descriptor buffer\r
+#ifdef __ICCARM__ // IAR\r
+#pragma data_alignment=8 // IAR\r
+#endif // IAR\r
+static volatile RxTd rxTd;\r
+// Transmit Transfer Descriptor buffer\r
+#ifdef __ICCARM__ // IAR\r
+#pragma data_alignment=8 // IAR\r
+#endif // IAR\r
+static volatile TxTd txTd;\r
+/// Send Buffer\r
+// Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K Boundaries.\r
+// Receive buffer manager writes are burst of 2 words => 3 lsb bits of the address shall be set to 0\r
+#ifdef __ICCARM__ // IAR\r
+#pragma data_alignment=8 // IAR\r
+#endif // IAR\r
+static volatile unsigned char pTxBuffer[TX_BUFFERS * EMAC_TX_UNITSIZE] __attribute__((aligned(8)));\r
+\r
+#ifdef __ICCARM__ // IAR\r
+#pragma data_alignment=8 // IAR\r
+#endif // IAR\r
+/// Receive Buffer\r
+static volatile unsigned char pRxBuffer[RX_BUFFERS * EMAC_RX_UNITSIZE] __attribute__((aligned(8)));\r
+/// Statistics\r
+static volatile EmacStats EmacStatistics;\r
+\r
+//-----------------------------------------------------------------------------\r
+// Internal functions\r
+//-----------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Wait PHY operation complete.\r
+/// Return 1 if the operation completed successfully.\r
+/// May be need to re-implemented to reduce CPU load.\r
+/// \param retry: the retry times, 0 to wait forever until complete.\r
+//-----------------------------------------------------------------------------\r
+static unsigned char EMAC_WaitPhy( unsigned int retry )\r
+{\r
+ unsigned int retry_count = 0;\r
+\r
+ while((AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE) == 0) {\r
+\r
+ // Dead LOOP!\r
+ if (retry == 0) {\r
+\r
+ continue;\r
+ }\r
+\r
+ // Timeout check\r
+ retry_count++;\r
+ if(retry_count >= retry) {\r
+\r
+ trace_LOG(trace_ERROR, "E: Wait PHY time out\n\r");\r
+ return 0;\r
+ }\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Exported functions\r
+//-----------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+// PHY management functions\r
+//-----------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Set MDC clock according to current board clock. Per 802.3, MDC should be\r
+/// less then 2.5MHz.\r
+/// Return 1 if successfully, 0 if MDC clock not found.\r
+//-----------------------------------------------------------------------------\r
+unsigned char EMAC_SetMdcClock( unsigned int mck )\r
+{\r
+ int clock_dividor;\r
+\r
+ if (mck <= 20000000) {\r
+ clock_dividor = AT91C_EMAC_CLK_HCLK_8; /// MDC clock = MCK/8\r
+ }\r
+ else if (mck <= 40000000) {\r
+ clock_dividor = AT91C_EMAC_CLK_HCLK_16; /// MDC clock = MCK/16\r
+ }\r
+ else if (mck <= 80000000) {\r
+ clock_dividor = AT91C_EMAC_CLK_HCLK_32; /// MDC clock = MCK/32\r
+ }\r
+ else if (mck <= 160000000) {\r
+ clock_dividor = AT91C_EMAC_CLK_HCLK_64; /// MDC clock = MCK/64\r
+ }\r
+ else {\r
+ trace_LOG(trace_ERROR, "E: No valid MDC clock.\n\r");\r
+ return 0;\r
+ }\r
+ AT91C_BASE_EMAC->EMAC_NCFGR = (AT91C_BASE_EMAC->EMAC_NCFGR & (~AT91C_EMAC_CLK))\r
+ | clock_dividor;\r
+ return 1;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable MDI with PHY\r
+//-----------------------------------------------------------------------------\r
+void EMAC_EnableMdio( void )\r
+{\r
+ AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable MDI with PHY\r
+//-----------------------------------------------------------------------------\r
+void EMAC_DisableMdio( void )\r
+{\r
+ AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable MII mode for EMAC, called once after autonegotiate\r
+//-----------------------------------------------------------------------------\r
+void EMAC_EnableMII( void )\r
+{\r
+ AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable RMII mode for EMAC, called once after autonegotiate\r
+//-----------------------------------------------------------------------------\r
+void EMAC_EnableRMII( void )\r
+{\r
+ AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN | AT91C_EMAC_RMII;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Read PHY register.\r
+/// Return 1 if successfully, 0 if timeout.\r
+/// \param PhyAddress PHY Address\r
+/// \param Address Register Address\r
+/// \param pValue Pointer to a 32 bit location to store read data\r
+/// \param retry The retry times, 0 to wait forever until complete.\r
+//-----------------------------------------------------------------------------\r
+unsigned char EMAC_ReadPhy(unsigned char PhyAddress,\r
+ unsigned char Address,\r
+ unsigned int *pValue,\r
+ unsigned int retry)\r
+{\r
+ AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01 << 30))\r
+ | (AT91C_EMAC_CODE & (2 << 16))\r
+ | (AT91C_EMAC_RW & (2 << 28))\r
+ | (AT91C_EMAC_PHYA & ((PhyAddress & 0x1f) << 23))\r
+ | (AT91C_EMAC_REGA & (Address << 18));\r
+\r
+ if ( EMAC_WaitPhy(retry) == 0 ) {\r
+\r
+ trace_LOG(trace_ERROR, "TimeOut EMAC_ReadPhy\n\r");\r
+ return 0;\r
+ }\r
+ *pValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );\r
+ return 1;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Write PHY register\r
+/// Return 1 if successfully, 0 if timeout.\r
+/// \param PhyAddress PHY Address\r
+/// \param Address Register Address\r
+/// \param Value Data to write ( Actually 16 bit data )\r
+/// \param retry The retry times, 0 to wait forever until complete.\r
+//-----------------------------------------------------------------------------\r
+unsigned char EMAC_WritePhy(unsigned char PhyAddress,\r
+ unsigned char Address,\r
+ unsigned int Value,\r
+ unsigned int retry)\r
+{\r
+ AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01 << 30))\r
+ | (AT91C_EMAC_CODE & (2 << 16))\r
+ | (AT91C_EMAC_RW & (1 << 28))\r
+ | (AT91C_EMAC_PHYA & ((PhyAddress & 0x1f) << 23))\r
+ | (AT91C_EMAC_REGA & (Address << 18))\r
+ | (AT91C_EMAC_DATA & Value) ;\r
+ if ( EMAC_WaitPhy(retry) == 0 ) {\r
+\r
+ trace_LOG(trace_ERROR, "TimeOut EMAC_WritePhy\n\r");\r
+ return 0;\r
+ }\r
+ return 1;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Setup the EMAC for the link : speed 100M/10M and Full/Half duplex\r
+/// \param speed Link speed, 0 for 10M, 1 for 100M\r
+/// \param fullduplex 1 for Full Duplex mode\r
+//-----------------------------------------------------------------------------\r
+void EMAC_SetLinkSpeed(unsigned char speed, unsigned char fullduplex)\r
+{\r
+ unsigned int ncfgr;\r
+\r
+ ncfgr = AT91C_BASE_EMAC->EMAC_NCFGR;\r
+ ncfgr &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);\r
+ if (speed) {\r
+\r
+ ncfgr |= AT91C_EMAC_SPD;\r
+ }\r
+ if (fullduplex) {\r
+\r
+ ncfgr |= AT91C_EMAC_FD;\r
+ }\r
+ AT91C_BASE_EMAC->EMAC_NCFGR = ncfgr;\r
+}\r
+\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// EMAC functions\r
+//-----------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+/// EMAC Interrupt handler\r
+//-----------------------------------------------------------------------------\r
+void EMAC_Handler(void)\r
+{\r
+ volatile EmacTxTDescriptor *pTxTd;\r
+ volatile EMAC_TxCallback *pTxCb;\r
+ unsigned int isr;\r
+ unsigned int rsr;\r
+ unsigned int tsr;\r
+ unsigned int rxStatusFlag;\r
+ unsigned int txStatusFlag;\r
+\r
+ //trace_LOG(trace_DEBUG, "EMAC_Handler\n\r");\r
+ isr = AT91C_BASE_EMAC->EMAC_ISR & AT91C_BASE_EMAC->EMAC_IMR;\r
+ rsr = AT91C_BASE_EMAC->EMAC_RSR;\r
+ tsr = AT91C_BASE_EMAC->EMAC_TSR;\r
+\r
+ // RX packet\r
+ if ((isr & AT91C_EMAC_RCOMP) || (rsr & AT91C_EMAC_REC)) {\r
+ rxStatusFlag = AT91C_EMAC_REC;\r
+\r
+ // Frame received\r
+ EmacStatistics.rx_packets++;\r
+\r
+ // Check OVR\r
+ if (rsr & AT91C_EMAC_OVR) {\r
+ rxStatusFlag |= AT91C_EMAC_OVR;\r
+ EmacStatistics.rx_ovrs++;\r
+ }\r
+ // Check BNA\r
+ if (rsr & AT91C_EMAC_BNA) {\r
+ rxStatusFlag |= AT91C_EMAC_BNA;\r
+ EmacStatistics.rx_bnas++;\r
+ }\r
+ // Clear status\r
+ AT91C_BASE_EMAC->EMAC_RSR |= rxStatusFlag;\r
+\r
+ // Invoke callbacks\r
+ if (rxTd.rxCb) {\r
+ rxTd.rxCb(rxStatusFlag);\r
+ }\r
+ }\r
+\r
+ // TX packet\r
+ if ((isr & AT91C_EMAC_TCOMP) || (tsr & AT91C_EMAC_COMP)) {\r
+\r
+ txStatusFlag = AT91C_EMAC_COMP;\r
+ EmacStatistics.tx_comp ++;\r
+\r
+ // A frame transmitted\r
+ // Check RLE\r
+ if (tsr & AT91C_EMAC_RLES) {\r
+ txStatusFlag |= AT91C_EMAC_RLES;\r
+ EmacStatistics.tx_errors++;\r
+ }\r
+ // Check COL\r
+ if (tsr & AT91C_EMAC_COL) {\r
+ txStatusFlag |= AT91C_EMAC_COL;\r
+ EmacStatistics.collisions++;\r
+ }\r
+ // Check BEX\r
+ if (tsr & AT91C_EMAC_BEX) {\r
+ txStatusFlag |= AT91C_EMAC_BEX;\r
+ EmacStatistics.tx_exausts++;\r
+ }\r
+ // Check UND\r
+ if (tsr & AT91C_EMAC_UND) {\r
+ txStatusFlag |= AT91C_EMAC_UND;\r
+ EmacStatistics.tx_underruns++;\r
+ }\r
+ // Clear status\r
+ AT91C_BASE_EMAC->EMAC_TSR |= txStatusFlag;\r
+\r
+ // Sanity check: Tx buffers have to be scheduled\r
+ ASSERT(!CIRC_EMPTY(&txTd),\r
+ "-F- EMAC Tx interrupt received meanwhile no TX buffers has been scheduled\n\r");\r
+\r
+ // Check the buffers\r
+ while (CIRC_CNT(txTd.head, txTd.tail, TX_BUFFERS)) {\r
+ pTxTd = txTd.td + txTd.tail;\r
+ pTxCb = txTd.txCb + txTd.tail;\r
+\r
+ // Exit if buffer has not been sent yet\r
+ if ((pTxTd->status & EMAC_TX_USED_BIT) == 0) {\r
+ break;\r
+ }\r
+\r
+ // Notify upper layer that packet has been sent\r
+ if (*pTxCb) {\r
+ (*pTxCb)(txStatusFlag);\r
+ }\r
+\r
+ CIRC_INC( txTd.tail, TX_BUFFERS );\r
+ }\r
+\r
+ // If a wakeup has been scheduled, notify upper layer that it can send\r
+ // other packets, send will be successfull.\r
+ if( (CIRC_SPACE(txTd.head, txTd.tail, TX_BUFFERS) >= txTd.wakeupThreshold)\r
+ && txTd.wakeupCb) {\r
+ txTd.wakeupCb();\r
+ }\r
+ }\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Initialize the EMAC with the emac controller address\r
+/// \param id HW ID for power management\r
+/// \param pTxWakeUpfct Thresold TX Wakeup Callback\r
+/// \param pRxfct RX Wakeup Callback\r
+/// \param pMacAddress Mac Address\r
+/// \param enableCAF enable AT91C_EMAC_CAF if needed by application\r
+/// \param enableNBC AT91C_EMAC_NBC if needed by application\r
+//-----------------------------------------------------------------------------\r
+void EMAC_Init( unsigned char id, const unsigned char *pMacAddress,\r
+ unsigned char enableCAF, unsigned char enableNBC )\r
+{\r
+ int Index;\r
+ unsigned int Address;\r
+\r
+ // Check parameters\r
+ ASSERT(RX_BUFFERS * EMAC_RX_UNITSIZE > EMAC_FRAME_LENTGH_MAX,\r
+ "E: RX buffers too small\n\r");\r
+\r
+ trace_LOG(trace_DEBUG, "EMAC_Init\n\r");\r
+\r
+ // Power ON\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << id;\r
+\r
+ // Disable TX & RX and more\r
+ AT91C_BASE_EMAC->EMAC_NCR = 0;\r
+\r
+ // disable\r
+ AT91C_BASE_EMAC->EMAC_IDR = ~0;\r
+\r
+ rxTd.idx = 0;\r
+ CIRC_CLEAR(&txTd);\r
+\r
+ // Setup the RX descriptors.\r
+ for(Index = 0; Index < RX_BUFFERS; Index++) {\r
+\r
+ Address = (unsigned int)(&(pRxBuffer[Index * EMAC_RX_UNITSIZE]));\r
+ // Remove EMAC_RX_OWNERSHIP_BIT and EMAC_RX_WRAP_BIT\r
+ rxTd.td[Index].addr = Address & EMAC_ADDRESS_MASK;\r
+ rxTd.td[Index].status = 0;\r
+ }\r
+ rxTd.td[RX_BUFFERS - 1].addr |= EMAC_RX_WRAP_BIT;\r
+\r
+ // Setup the TX descriptors.\r
+ for(Index = 0; Index < TX_BUFFERS; Index++) {\r
+\r
+ Address = (unsigned int)(&(pTxBuffer[Index * EMAC_TX_UNITSIZE]));\r
+ txTd.td[Index].addr = Address;\r
+ txTd.td[Index].status = EMAC_TX_USED_BIT;\r
+ }\r
+ txTd.td[TX_BUFFERS - 1].status = EMAC_TX_USED_BIT | EMAC_TX_WRAP_BIT;\r
+\r
+ // Set the MAC address\r
+ if( pMacAddress != (unsigned char *)0 ) {\r
+ AT91C_BASE_EMAC->EMAC_SA1L = ( ((unsigned int)pMacAddress[3] << 24)\r
+ | ((unsigned int)pMacAddress[2] << 16)\r
+ | ((unsigned int)pMacAddress[1] << 8 )\r
+ | pMacAddress[0] );\r
+\r
+ AT91C_BASE_EMAC->EMAC_SA1H = ( ((unsigned int)pMacAddress[5] << 8 )\r
+ | pMacAddress[4] );\r
+ }\r
+ // Now setup the descriptors\r
+ // Receive Buffer Queue Pointer Register\r
+ AT91C_BASE_EMAC->EMAC_RBQP = (unsigned int) (rxTd.td);\r
+ // Transmit Buffer Queue Pointer Register\r
+ AT91C_BASE_EMAC->EMAC_TBQP = (unsigned int) (txTd.td);\r
+\r
+ AT91C_BASE_EMAC->EMAC_NCR = AT91C_EMAC_CLRSTAT;\r
+\r
+ // Clear all status bits in the receive status register.\r
+ AT91C_BASE_EMAC->EMAC_RSR = (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);\r
+\r
+ // Clear all status bits in the transmit status register\r
+ AT91C_BASE_EMAC->EMAC_TSR = ( AT91C_EMAC_UBR | AT91C_EMAC_COL | AT91C_EMAC_RLES\r
+ | AT91C_EMAC_BEX | AT91C_EMAC_COMP\r
+ | AT91C_EMAC_UND );\r
+\r
+ // Clear interrupts\r
+ AT91C_BASE_EMAC->EMAC_ISR;\r
+\r
+ // Enable the copy of data into the buffers\r
+ // ignore broadcasts, and don't copy FCS.\r
+ AT91C_BASE_EMAC->EMAC_NCFGR |= (AT91C_EMAC_DRFCS | AT91C_EMAC_PAE);\r
+\r
+ if( enableCAF == EMAC_CAF_ENABLE ) {\r
+ AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_CAF;\r
+ }\r
+ if( enableNBC == EMAC_NBC_ENABLE ) {\r
+ AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_NBC;\r
+ }\r
+\r
+ // Enable Rx and Tx, plus the stats register.\r
+ AT91C_BASE_EMAC->EMAC_NCR |= (AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT);\r
+\r
+ // Setup the interrupts for TX (and errors)\r
+ AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RXUBR\r
+ | AT91C_EMAC_TUNDR\r
+ | AT91C_EMAC_RLEX\r
+ | AT91C_EMAC_TXERR\r
+ | AT91C_EMAC_TCOMP\r
+ | AT91C_EMAC_ROVR\r
+ | AT91C_EMAC_HRESP;\r
+\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Get the statstic information & reset it\r
+/// \param pStats Pointer to EmacStats structure to copy the informations\r
+/// \param reset Reset the statistics after copy it\r
+//-----------------------------------------------------------------------------\r
+void EMAC_GetStatistics(EmacStats *pStats, unsigned char reset)\r
+{\r
+ unsigned int ncrBackup = 0;\r
+\r
+ trace_LOG(trace_DEBUG, "EMAC_GetStatistics\n\r");\r
+\r
+ // Sanity check\r
+ if (pStats == (EmacStats *) 0) {\r
+ return;\r
+ }\r
+\r
+ ncrBackup = AT91C_BASE_EMAC->EMAC_NCR & (AT91C_EMAC_TE | AT91C_EMAC_RE);\r
+\r
+ // Disable TX/RX\r
+ AT91C_BASE_EMAC->EMAC_NCR = ncrBackup & ~(AT91C_EMAC_TE | AT91C_EMAC_RE);\r
+\r
+ // Copy the informations\r
+ memcpy(pStats, (void*)&EmacStatistics, sizeof(EmacStats));\r
+\r
+ // Reset the statistics\r
+ if (reset) {\r
+ memset((void*)&EmacStatistics, 0x00, sizeof(EmacStats));\r
+ AT91C_BASE_EMAC->EMAC_NCR = ncrBackup | AT91C_EMAC_CLRSTAT;\r
+ }\r
+\r
+ // restore NCR\r
+ AT91C_BASE_EMAC->EMAC_NCR = ncrBackup;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Send a packet with EMAC.\r
+/// If the packet size is larger than transfer buffer size error returned.\r
+/// \param buffer The buffer to be send\r
+/// \param size The size of buffer to be send\r
+/// \param fEMAC_TxCallback Threshold Wakeup callback\r
+/// \param fWakeUpCb TX Wakeup\r
+/// \return OK, Busy or invalid packet\r
+//-----------------------------------------------------------------------------\r
+unsigned char EMAC_Send(void *pBuffer,\r
+ unsigned int size,\r
+ EMAC_TxCallback fEMAC_TxCallback)\r
+{\r
+ volatile EmacTxTDescriptor *pTxTd;\r
+ volatile EMAC_TxCallback *pTxCb;\r
+\r
+ //trace_LOG(trace_DEBUG, "EMAC_Send\n\r");\r
+\r
+ // Check parameter\r
+ if (size > EMAC_TX_UNITSIZE) {\r
+\r
+ trace_LOG(trace_ERROR, "-E- EMAC driver does not split send packets.");\r
+ trace_LOG(trace_ERROR, " It can send %d bytes max in one packet (%u bytes requested)\n\r",\r
+ EMAC_TX_UNITSIZE, size);\r
+ return EMAC_TX_INVALID_PACKET;\r
+ }\r
+\r
+ // If no free TxTd, buffer can't be sent, schedule the wakeup callback\r
+ if( CIRC_SPACE(txTd.head, txTd.tail, TX_BUFFERS) == 0) {\r
+ return EMAC_TX_BUFFER_BUSY;\r
+\r
+ }\r
+\r
+ // Pointers to the current TxTd\r
+ pTxTd = txTd.td + txTd.head;\r
+ pTxCb = txTd.txCb + txTd.head;\r
+\r
+ // Sanity check\r
+ ASSERT((pTxTd->status & EMAC_TX_USED_BIT) != 0,\r
+ "-F- Buffer is still under EMAC control\n\r");\r
+\r
+ // Setup/Copy data to transmition buffer\r
+ if (pBuffer && size) {\r
+ // Driver manage the ring buffer\r
+ memcpy((void *)pTxTd->addr, pBuffer, size);\r
+ }\r
+\r
+ // Tx Callback\r
+ *pTxCb = fEMAC_TxCallback;\r
+\r
+ // Update TD status\r
+ // The buffer size defined is length of ethernet frame\r
+ // so it's always the last buffer of the frame.\r
+ if (txTd.head == TX_BUFFERS-1) {\r
+ pTxTd->status =\r
+ (size & EMAC_LENGTH_FRAME) | EMAC_TX_LAST_BUFFER_BIT | EMAC_TX_WRAP_BIT;\r
+ }\r
+ else {\r
+ pTxTd->status = (size & EMAC_LENGTH_FRAME) | EMAC_TX_LAST_BUFFER_BIT;\r
+ }\r
+\r
+ CIRC_INC(txTd.head, TX_BUFFERS)\r
+\r
+ // Tx packets count\r
+ EmacStatistics.tx_packets++;\r
+\r
+ // Now start to transmit if it is not already done\r
+ AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;\r
+\r
+ return EMAC_TX_OK;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Receive a packet with EMAC\r
+/// If not enough buffer for the packet, the remaining data is lost but right\r
+/// frame length is returned.\r
+/// \param pFrame Buffer to store the frame\r
+/// \param frameSize Size of the frame\r
+/// \param pRcvSize Received size\r
+/// \return OK, no data, or frame too small\r
+//-----------------------------------------------------------------------------\r
+unsigned char EMAC_Poll(unsigned char *pFrame,\r
+ unsigned int frameSize,\r
+ unsigned int *pRcvSize)\r
+{\r
+ unsigned short bufferLength;\r
+ unsigned int tmpFrameSize=0;\r
+ unsigned char *pTmpFrame=0;\r
+ unsigned int tmpIdx = rxTd.idx;\r
+ volatile EmacRxTDescriptor *pRxTd = rxTd.td + rxTd.idx;\r
+\r
+ ASSERT(pFrame, "F: EMAC_Poll\n\r");\r
+\r
+ char isFrame = 0;\r
+ // Set the default return value\r
+ *pRcvSize = 0;\r
+\r
+ // Process received RxTd\r
+ while ((pRxTd->addr & EMAC_RX_OWNERSHIP_BIT) == EMAC_RX_OWNERSHIP_BIT) {\r
+\r
+ // A start of frame has been received, discard previous fragments\r
+ if ((pRxTd->status & EMAC_RX_SOF_BIT) == EMAC_RX_SOF_BIT) {\r
+ // Skip previous fragment\r
+ while (tmpIdx != rxTd.idx) {\r
+ pRxTd = rxTd.td + rxTd.idx;\r
+ pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);\r
+ CIRC_INC(rxTd.idx, RX_BUFFERS);\r
+ }\r
+ // Reset the temporary frame pointer\r
+ pTmpFrame = pFrame;\r
+ tmpFrameSize = 0;\r
+ // Start to gather buffers in a frame\r
+ isFrame = 1;\r
+ }\r
+\r
+ // Increment the pointer\r
+ CIRC_INC(tmpIdx, RX_BUFFERS);\r
+\r
+ // Copy data in the frame buffer\r
+ if (isFrame) {\r
+ if (tmpIdx == rxTd.idx) {\r
+ trace_LOG(trace_INFO,\r
+ "I: no EOF (Invalid of buffers too small)\n\r");\r
+\r
+ do {\r
+\r
+ pRxTd = rxTd.td + rxTd.idx;\r
+ pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);\r
+ CIRC_INC(rxTd.idx, RX_BUFFERS);\r
+ } while(tmpIdx != rxTd.idx);\r
+ return EMAC_RX_NO_DATA;\r
+ }\r
+ // Copy the buffer into the application frame\r
+ bufferLength = EMAC_RX_UNITSIZE;\r
+ if ((tmpFrameSize + bufferLength) > frameSize) {\r
+ bufferLength = frameSize - tmpFrameSize;\r
+ }\r
+\r
+ memcpy(pTmpFrame, (void*)(pRxTd->addr & EMAC_ADDRESS_MASK), bufferLength);\r
+ pTmpFrame += bufferLength;\r
+ tmpFrameSize += bufferLength;\r
+\r
+ // An end of frame has been received, return the data\r
+ if ((pRxTd->status & EMAC_RX_EOF_BIT) == EMAC_RX_EOF_BIT) {\r
+ // Frame size from the EMAC\r
+ *pRcvSize = (pRxTd->status & EMAC_LENGTH_FRAME);\r
+\r
+ // Application frame buffer is too small all data have not been copied\r
+ if (tmpFrameSize < *pRcvSize) {\r
+ printf("size req %u size allocated %u\n\r", *pRcvSize, frameSize);\r
+\r
+ return EMAC_RX_FRAME_SIZE_TOO_SMALL;\r
+ }\r
+\r
+ trace_LOG(trace_INFO, "packet %d-%u (%u)\n\r", rxTd.idx, tmpIdx, *pRcvSize);\r
+ // All data have been copied in the application frame buffer => release TD\r
+ while (rxTd.idx != tmpIdx) {\r
+ pRxTd = rxTd.td + rxTd.idx;\r
+ pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);\r
+ CIRC_INC(rxTd.idx, RX_BUFFERS);\r
+ }\r
+ EmacStatistics.rx_packets++;\r
+ return EMAC_RX_OK;\r
+ }\r
+ }\r
+\r
+ // SOF has not been detected, skip the fragment\r
+ else {\r
+ pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);\r
+ rxTd.idx = tmpIdx;\r
+ }\r
+\r
+ // Process the next buffer\r
+ pRxTd = rxTd.td + tmpIdx;\r
+ }\r
+\r
+ //trace_LOG(trace_DEBUG, "E");\r
+ return EMAC_RX_NO_DATA;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Registers pRxCb callback. Callback will be invoked after the next received\r
+/// frame.\r
+/// When EMAC_Poll() returns EMAC_RX_NO_DATA the application task call EMAC_Set_RxCb()\r
+/// to register pRxCb() callback and enters suspend state. The callback is in charge\r
+/// to resume the task once a new frame has been received. The next time EMAC_Poll()\r
+/// is called, it will be successfull.\r
+/// \param pRxCb Pointer to callback function\r
+//-----------------------------------------------------------------------------\r
+void EMAC_Set_RxCb(EMAC_RxCallback pRxCb)\r
+{\r
+ rxTd.rxCb = pRxCb;\r
+ AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Remove the RX callback function.\r
+/// This function is usually invoked from the RX callback itself. Once the callback\r
+/// has resumed the application task, there is no need to invoke the callback again.\r
+//-----------------------------------------------------------------------------\r
+void EMAC_Clear_RxCb(void)\r
+{\r
+ AT91C_BASE_EMAC->EMAC_IDR = AT91C_EMAC_RCOMP;\r
+ rxTd.rxCb = (EMAC_RxCallback) 0;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Registers TX wakeup callback callback. Callback will be invoked once several\r
+/// transfer descriptors are available.\r
+/// When EMAC_Send() returns EMAC_TX_BUFFER_BUSY (all TD busy) the application\r
+/// task calls EMAC_Set_TxWakeUpCb() to register pTxWakeUpCb() callback and\r
+/// enters suspend state. The callback is in charge to resume the task once\r
+/// several TD have been released. The next time EMAC_Send() will be called, it\r
+/// shall be successfull.\r
+/// \param pTxWakeUpCb Pointer to callback function\r
+/// \param threshold Minimum number of available transfer descriptors before pTxWakeUpCb() is invoked\r
+/// \return 0= success, 1 = threshold exceeds nuber of transfer descriptors\r
+//-----------------------------------------------------------------------------\r
+char EMAC_Set_TxWakeUpCb(EMAC_WakeupCallback pTxWakeUpCb, unsigned short threshold)\r
+{\r
+ if (threshold <= TX_BUFFERS) {\r
+ txTd.wakeupCb = pTxWakeUpCb;\r
+ txTd.wakeupThreshold = threshold;\r
+ return 0;\r
+ }\r
+ return 1;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Remove the TX wakeup callback function.\r
+/// This function is usually invoked from the TX wakeup callback itself. Once the callback\r
+/// has resumed the application task, there is no need to invoke the callback again.\r
+//-----------------------------------------------------------------------------\r
+void EMAC_Clear_TxWakeUpCb(void)\r
+{\r
+ txTd.wakeupCb = (EMAC_WakeupCallback) 0;\r
+}\r
+\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+// peripherals/emac/emac.h\r
+\r
+#ifndef EMAC_H\r
+#define EMAC_H\r
+\r
+//-----------------------------------------------------------------------------\r
+/// \dir\r
+/// !Purpose\r
+///\r
+/// Definition of methods and structures for using EMAC\r
+/// \r
+/// !Usage\r
+///\r
+/// -# Initialize EMAC with EMAC_Init.\r
+/// -# Setup EMAC with EMAC_SetupTx, EMAC_SetupRx, EMAC_SetupMacAddress\r
+/// and EMAC_SetupStack. \r
+/// -# Drive the EMAC status machine by EMAC_Task.\r
+/// -# EMAC_GetStatus give EMAC status machine current status \r
+/// -# Send a packet to network with EMAC_SendPacket.\r
+/// -# Get a packet from network with EMAC_GetPacket.\r
+///\r
+//-----------------------------------------------------------------------------\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Headers\r
+//-----------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+// Definitions\r
+//-----------------------------------------------------------------------------\r
+/// Number of buffer for RX, be carreful: MUST be 2^n\r
+#define RX_BUFFERS 16\r
+/// Number of buffer for TX, be carreful: MUST be 2^n\r
+#define TX_BUFFERS 8\r
+\r
+/// Buffer Size\r
+#define EMAC_RX_UNITSIZE 128 /// Fixed size for RX buffer\r
+#define EMAC_TX_UNITSIZE 1518 /// Size for ETH frame length\r
+\r
+// The MAC can support frame lengths up to 1536 bytes.\r
+#define EMAC_FRAME_LENTGH_MAX 1536\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Types\r
+//-----------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Describes the statistics of the EMAC.\r
+//-----------------------------------------------------------------------------\r
+typedef struct _EmacStats {\r
+\r
+ // TX errors\r
+ unsigned int tx_packets; /// Total Number of packets sent\r
+ unsigned int tx_comp; /// Packet complete\r
+ unsigned int tx_errors; /// TX errors ( Retry Limit Exceed )\r
+ unsigned int collisions; /// Collision\r
+ unsigned int tx_exausts; /// Buffer exhausted\r
+ unsigned int tx_underruns; /// Under Run, not able to read from memory\r
+ // RX errors\r
+ unsigned int rx_packets; /// Total Number of packets RX\r
+ unsigned int rx_eof; /// No EOF error\r
+ unsigned int rx_ovrs; /// Over Run, not able to store to memory\r
+ unsigned int rx_bnas; /// Buffer is not available\r
+\r
+} EmacStats, *PEmacStats;\r
+\r
+//-----------------------------------------------------------------------------\r
+// PHY Exported functions\r
+//-----------------------------------------------------------------------------\r
+extern unsigned char EMAC_SetMdcClock( unsigned int mck );\r
+\r
+extern void EMAC_EnableMdio( void );\r
+\r
+extern void EMAC_DisableMdio( void );\r
+\r
+extern void EMAC_EnableMII( void );\r
+\r
+extern void EMAC_EnableRMII( void );\r
+\r
+extern unsigned char EMAC_ReadPhy(unsigned char PhyAddress,\r
+ unsigned char Address,\r
+ unsigned int *pValue,\r
+ unsigned int retry);\r
+\r
+extern unsigned char EMAC_WritePhy(unsigned char PhyAddress,\r
+ unsigned char Address,\r
+ unsigned int Value,\r
+ unsigned int retry);\r
+\r
+extern void EMAC_SetLinkSpeed(unsigned char speed,\r
+ unsigned char fullduplex);\r
+\r
+//-----------------------------------------------------------------------------\r
+// EMAC Exported functions\r
+//-----------------------------------------------------------------------------\r
+/// Callback used by send function\r
+typedef void (*EMAC_TxCallback)(unsigned int status);\r
+typedef void (*EMAC_RxCallback)(unsigned int status);\r
+typedef void (*EMAC_WakeupCallback)(void);\r
+\r
+extern void EMAC_Init( unsigned char id, const unsigned char *pMacAddress,\r
+ unsigned char enableCAF, unsigned char enableNBC );\r
+#define EMAC_CAF_DISABLE 0\r
+#define EMAC_CAF_ENABLE 1\r
+#define EMAC_NBC_DISABLE 0\r
+#define EMAC_NBC_ENABLE 1\r
+\r
+extern void EMAC_Handler(void);\r
+\r
+extern unsigned char EMAC_Send(void *pBuffer, \r
+ unsigned int size, \r
+ EMAC_TxCallback fEMAC_TxCallback);\r
+/// Return for EMAC_Send function\r
+#define EMAC_TX_OK 0\r
+#define EMAC_TX_BUFFER_BUSY 1\r
+#define EMAC_TX_INVALID_PACKET 2\r
+\r
+\r
+extern unsigned char EMAC_Poll(unsigned char *pFrame,\r
+ unsigned int frameSize,\r
+ unsigned int *pRcvSize);\r
+/// Return for EMAC_Poll function\r
+#define EMAC_RX_OK 0\r
+#define EMAC_RX_NO_DATA 1\r
+#define EMAC_RX_FRAME_SIZE_TOO_SMALL 2\r
+\r
+extern void EMAC_GetStatistics(EmacStats *pStats, unsigned char reset);\r
+\r
+#endif // #ifndef EMAC_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "lcd.h"\r
+#include <board.h>\r
+#include <utility/assert.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the LCD controller, after waiting for the specified number of\r
+/// frames.\r
+/// \param frames Number of frames before the LCD is enabled.\r
+//------------------------------------------------------------------------------\r
+void LCD_Enable(unsigned int frames)\r
+{\r
+ ASSERT((frames & 0xFFFFFF80) == 0,\r
+ "LCD_Enable: Wrong frames value.\n\r");\r
+ AT91C_BASE_LCDC->LCDC_PWRCON = AT91C_LCDC_PWR | (frames << 1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the LCD controller, after waiting for the specified number of\r
+/// frames.\r
+/// \param frames Number of frames before the LCD is shut down.\r
+//------------------------------------------------------------------------------\r
+void LCD_Disable(unsigned int frames)\r
+{\r
+ ASSERT((frames & 0xFFFFFF80) == 0,\r
+ "LCD_Disable: Wrong frames value.\n\r");\r
+ AT91C_BASE_LCDC->LCDC_PWRCON = frames << 1;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the DMA of the LCD controller.\r
+//------------------------------------------------------------------------------\r
+void LCD_EnableDma()\r
+{\r
+ AT91C_BASE_LCDC->LCDC_DMACON = AT91C_LCDC_DMAEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the DMA of the LCD controller.\r
+//------------------------------------------------------------------------------\r
+void LCD_DisableDma()\r
+{\r
+ AT91C_BASE_LCDC->LCDC_DMACON = 0;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the internal clock of the LCD controller given the master clock of\r
+/// the system and the desired pixel clock in MHz.\r
+/// \param masterClock Master clock frequency.\r
+/// \param pixelClock Pixel clock frequency.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetPixelClock(unsigned int masterClock, unsigned int pixelClock)\r
+{\r
+ AT91C_BASE_LCDC->LCDC_LCDCON1 = ((masterClock / (2 * pixelClock)) - 1) << 12;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the type of display used with the LCD controller.\r
+/// \param displayType Type of display used.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetDisplayType(unsigned int displayType)\r
+{\r
+ unsigned int value;\r
+\r
+ ASSERT((displayType & ~AT91C_LCDC_DISTYPE) == 0,\r
+ "LCD_SetDisplayType: Wrong display type value.\n\r");\r
+\r
+ value = AT91C_BASE_LCDC->LCDC_LCDCON2;\r
+ value &= ~AT91C_LCDC_DISTYPE;\r
+ value |= displayType;\r
+ AT91C_BASE_LCDC->LCDC_LCDCON2 = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the scan mode used by the LCD (either single scan or double-scan).\r
+/// \param scanMode Scan mode to use.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetScanMode(unsigned int scanMode)\r
+{\r
+ unsigned int value;\r
+\r
+ ASSERT((scanMode & ~AT91C_LCDC_SCANMOD) == 0,\r
+ "LCD_SetScanMode: Wrong scan mode value.\n\r");\r
+\r
+ value = AT91C_BASE_LCDC->LCDC_LCDCON2;\r
+ value &= ~AT91C_LCDC_SCANMOD;\r
+ value |= scanMode;\r
+ AT91C_BASE_LCDC->LCDC_LCDCON2 = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the number of bits per pixel used by the LCD display.\r
+/// \param bitsPerPixel Number of bits per pixel to use.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetBitsPerPixel(unsigned int bitsPerPixel)\r
+{\r
+ unsigned int value;\r
+\r
+ ASSERT((bitsPerPixel & ~AT91C_LCDC_PIXELSIZE) == 0,\r
+ "LCD_SetScanMode: Wrong bitsPerPixel value.\n\r");\r
+\r
+ value = AT91C_BASE_LCDC->LCDC_LCDCON2;\r
+ value &= ~AT91C_LCDC_PIXELSIZE;\r
+ value |= bitsPerPixel;\r
+ AT91C_BASE_LCDC->LCDC_LCDCON2 = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the LCDD, LCDVSYNC, LCDHSYNC, LCDDOTCLK and LCDDEN signal polarities.\r
+/// \param lcdd LCDD signal polarity.\r
+/// \param lcdvsync LCDVSYNC signal polarity.\r
+/// \param lcdhsync LCDHSYNC signal polarity.\r
+/// \param lcddotclk LCDDOTCLK signal polarity.\r
+/// \param lcdden LCDDEN signal polarity.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetPolarities(\r
+ unsigned int lcdd,\r
+ unsigned int lcdvsync,\r
+ unsigned int lcdhsync,\r
+ unsigned int lcddotclk,\r
+ unsigned int lcdden)\r
+{\r
+ unsigned int value;\r
+\r
+ ASSERT((lcdd & ~AT91C_LCDC_INVVD) == 0,\r
+ "LCD_SetPolarities: Wrong lcdd value.\n\r");\r
+ ASSERT((lcdvsync & ~AT91C_LCDC_INVFRAME) == 0,\r
+ "LCD_SetPolarities: Wrong lcdvsync value.\n\r");\r
+ ASSERT((lcdhsync & ~AT91C_LCDC_INVLINE) == 0,\r
+ "LCD_SetPolarities: Wrong lcdhsync value.\n\r");\r
+ ASSERT((lcddotclk & ~AT91C_LCDC_INVCLK) == 0,\r
+ "LCD_SetPolarities: Wrong lcddotclk value.\n\r");\r
+ ASSERT((lcdden & ~AT91C_LCDC_INVDVAL) == 0,\r
+ "LCD_SetPolarities: Wrong lcdden value.\n\r");\r
+\r
+ value = AT91C_BASE_LCDC->LCDC_LCDCON2;\r
+ value &= 0xFFFFE0FF;\r
+ value |= lcdd | lcdvsync | lcdhsync | lcddotclk | lcdden;\r
+ AT91C_BASE_LCDC->LCDC_LCDCON2 = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the LCD clock mode, i.e. always active or active only during display\r
+/// period.\r
+/// \param clockMode Clock mode to use.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetClockMode(unsigned int clockMode)\r
+{\r
+ unsigned int value;\r
+\r
+ ASSERT((clockMode & ~AT91C_LCDC_CLKMOD) == 0,\r
+ "LCD_SetScanMode: Wrong scan mode value.\n\r");\r
+\r
+ value = AT91C_BASE_LCDC->LCDC_LCDCON2;\r
+ value &= ~AT91C_LCDC_CLKMOD;\r
+ value |= clockMode;\r
+ AT91C_BASE_LCDC->LCDC_LCDCON2 = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the format of the frame buffer memory.\r
+/// \param format Memory ordering format.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetMemoryFormat(unsigned int format)\r
+{\r
+ unsigned int value;\r
+\r
+ ASSERT((format & ~AT91C_LCDC_MEMOR) == 0,\r
+ "LCD_SetMemoryFormat: Wrong memory format value.\n\r");\r
+\r
+ value = AT91C_BASE_LCDC->LCDC_LCDCON2;\r
+ value &= ~AT91C_LCDC_MEMOR;\r
+ value |= format;\r
+ AT91C_BASE_LCDC->LCDC_LCDCON2 = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the size in pixel of the LCD display.\r
+/// \param width Width in pixel of the LCD display.\r
+/// \param height Height in pixel of the LCD display.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetSize(unsigned int width, unsigned int height)\r
+{\r
+ ASSERT(((width - 1) & 0xFFFFF800) == 0,\r
+ "LCD_SetSize: Wrong width value.\n\r");\r
+ ASSERT(((height - 1) & 0xFFFFF800) == 0,\r
+ "LCD_SetSize: Wrong height value.\n\r");\r
+\r
+ AT91C_BASE_LCDC->LCDC_LCDFRCFG = ((width - 1) << 21) | (height - 1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the vertical timings of the LCD controller. Only meaningful when\r
+/// using a TFT display.\r
+/// \param vfp Number of idle lines at the end of a frame.\r
+/// \param vbp Number of idle lines at the beginning of a frame.\r
+/// \param vpw Vertical synchronization pulse width in number of lines.\r
+/// \param vhdly Delay between LCDVSYNC edge and LCDHSYNC rising edge, in\r
+/// LCDDOTCLK cycles.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetVerticalTimings(\r
+ unsigned int vfp,\r
+ unsigned int vbp,\r
+ unsigned int vpw,\r
+ unsigned int vhdly)\r
+{\r
+ ASSERT((vfp & 0xFFFFFF00) == 0,\r
+ "LCD_SetVerticalTimings: Wrong vfp value.\n\r");\r
+ ASSERT((vbp & 0xFFFFFF00) == 0,\r
+ "LCD_SetVerticalTimings: Wrong vbp value.\n\r");\r
+ ASSERT(((vpw-1) & 0xFFFFFFC0) == 0,\r
+ "LCD_SetVerticalTimings: Wrong vpw value.\n\r");\r
+ ASSERT(((vhdly-1) & 0xFFFFFFF0) == 0,\r
+ "LCD_SetVerticalTimings: Wrong vhdly value.\n\r");\r
+\r
+ AT91C_BASE_LCDC->LCDC_TIM1 = vfp\r
+ | (vbp << 8)\r
+ | ((vpw-1) << 16)\r
+ | ((vhdly-1) << 24);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the horizontal timings of the LCD controller. Meaningful for both\r
+/// STN and TFT displays.\r
+/// \param hbp Number of idle LCDDOTCLK cycles at the beginning of a line.\r
+/// \param hpw Width of the LCDHSYNC pulse, in LCDDOTCLK cycles.\r
+/// \param hfp Number of idel LCDDOTCLK cycles at the end of a line.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetHorizontalTimings(\r
+ unsigned int hbp,\r
+ unsigned int hpw,\r
+ unsigned int hfp)\r
+{\r
+ ASSERT(((hbp-1) & 0xFFFFFF00) == 0,\r
+ "LCD_SetHorizontalTimings: Wrong hbp value.\n\r");\r
+ ASSERT(((hpw-1) & 0xFFFFFFC0) == 0,\r
+ "LCD_SetHorizontalTimings: Wrong hpw value.\n\r");\r
+ ASSERT(((hfp-1) & 0xFFFFFF00) == 0,\r
+ "LCD_SetHorizontalTimings: Wrong hfp value.\n\r");\r
+\r
+ AT91C_BASE_LCDC->LCDC_TIM2 = (hbp-1) | ((hpw-1) << 8) | ((hfp-1) << 24);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the address of the frame buffer in the LCD controller DMA. When using\r
+/// dual-scan mode, this is the upper frame buffer.\r
+/// \param address Frame buffer address.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetFrameBufferAddress(void *address)\r
+{\r
+ AT91C_BASE_LCDC->LCDC_BA1 = (unsigned int) address;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the size in pixels of a frame (height * width * bpp).\r
+/// \param frameSize Size of frame in pixels.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetFrameSize(unsigned int frameSize)\r
+{\r
+ ASSERT((frameSize & 0xFF800000) == 0,\r
+ "LCD_SetFrameSize: Wrong frameSize value.\n\r");\r
+\r
+ AT91C_BASE_LCDC->LCDC_FRMCFG = frameSize | (AT91C_BASE_LCDC->LCDC_FRMCFG & 0xFF000000);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the DMA controller burst length.\r
+/// \param burstLength Desired burst length.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetBurstLength(unsigned int burstLength)\r
+{\r
+ ASSERT(((burstLength-1) & 0xFFFFFF80) == 0,\r
+ "LCD_SetBurstLength: Wrong burstLength value.\n\r");\r
+\r
+ AT91C_BASE_LCDC->LCDC_FRMCFG &= 0x00FFFFFF;\r
+ AT91C_BASE_LCDC->LCDC_FRMCFG |= ((burstLength-1) << 24);\r
+\r
+ AT91C_BASE_LCDC->LCDC_FIFO = 2048 - (2 * burstLength + 3);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the prescaler value of the contrast control PWM.\r
+/// \param prescaler Desired prescaler value.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetContrastPrescaler(unsigned int prescaler)\r
+{\r
+ ASSERT((prescaler & ~AT91C_LCDC_PS) == 0,\r
+ "LCD_SetContrastPrescaler: Wrong prescaler value\n\r");\r
+\r
+ AT91C_BASE_LCDC->LCDC_CTRSTCON &= ~AT91C_LCDC_PS;\r
+ AT91C_BASE_LCDC->LCDC_CTRSTCON |= prescaler;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the polarity of the contrast PWM.\r
+/// \param polarity PWM polarity\r
+//------------------------------------------------------------------------------\r
+void LCD_SetContrastPolarity(unsigned int polarity)\r
+{\r
+ ASSERT((polarity & ~AT91C_LCDC_POL) == 0,\r
+ "LCD_SetContrastPolarity: Wrong polarity value\n\r");\r
+\r
+ AT91C_BASE_LCDC->LCDC_CTRSTCON &= ~AT91C_LCDC_POL;\r
+ AT91C_BASE_LCDC->LCDC_CTRSTCON |= polarity;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the threshold value of the constrast PWM.\r
+/// \param value PWM threshold value.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetContrastValue(unsigned int value)\r
+{\r
+ ASSERT((value & ~AT91C_LCDC_CVAL) == 0,\r
+ "LCD_SetContrastValue: Wrong value.\n\r");\r
+\r
+ AT91C_BASE_LCDC->LCDC_CTRSTVAL = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the contrast PWM generator.\r
+//------------------------------------------------------------------------------\r
+void LCD_EnableContrast()\r
+{\r
+ AT91C_BASE_LCDC->LCDC_CTRSTCON |= AT91C_LCDC_ENA_PWMGEMENABLED;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef LCD_H\r
+#define LCD_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void LCD_Enable(unsigned int frames);\r
+\r
+extern void LCD_Disable(unsigned int frames);\r
+\r
+extern void LCD_EnableDma();\r
+\r
+extern void LCD_DisableDma();\r
+\r
+extern void LCD_SetPixelClock(unsigned int masterClock, unsigned int pixelClock);\r
+\r
+extern void LCD_SetDisplayType(unsigned int displayType);\r
+\r
+extern void LCD_SetScanMode(unsigned int scanMode);\r
+\r
+extern void LCD_SetBitsPerPixel(unsigned int bitsPerPixel);\r
+\r
+extern void LCD_SetPolarities(\r
+ unsigned int lcdd,\r
+ unsigned int lcdvsync,\r
+ unsigned int lcdhsync,\r
+ unsigned int lcddotclk,\r
+ unsigned int lcdden);\r
+\r
+extern void LCD_SetClockMode(unsigned int clockMode);\r
+\r
+extern void LCD_SetMemoryFormat(unsigned int format);\r
+\r
+extern void LCD_SetSize(unsigned int width, unsigned int height);\r
+\r
+extern void LCD_SetVerticalTimings(\r
+ unsigned int vfp,\r
+ unsigned int vbp,\r
+ unsigned int vpw,\r
+ unsigned int vhdly);\r
+\r
+extern void LCD_SetHorizontalTimings(\r
+ unsigned int hbp,\r
+ unsigned int hpw,\r
+ unsigned int hfp);\r
+\r
+extern void LCD_SetFrameBufferAddress(void *address);\r
+\r
+extern void LCD_SetFrameSize(unsigned int frameSize);\r
+\r
+extern void LCD_SetBurstLength(unsigned int burstLength);\r
+\r
+extern void LCD_SetContrastPrescaler(unsigned int prescaler);\r
+\r
+extern void LCD_SetContrastPolarity(unsigned int polarity);\r
+\r
+extern void LCD_SetContrastValue(unsigned int value);\r
+\r
+extern void LCD_EnableContrast();\r
+\r
+#endif //#ifndef LCD_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support - ROUSSET -\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2006, Atmel Corporation\r
+\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * - Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the disclaimer below in the documentation and/or\r
+ * other materials provided with the distribution.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "mci.h"\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Local constants\r
+//------------------------------------------------------------------------------\r
+\r
+/// Bit mask for status register errors.\r
+#define STATUS_ERRORS (AT91C_MCI_UNRE \\r
+ | AT91C_MCI_OVRE \\r
+ | AT91C_MCI_DTOE \\r
+ | AT91C_MCI_DCRCE \\r
+ | AT91C_MCI_RTOE \\r
+ | AT91C_MCI_RENDE \\r
+ | AT91C_MCI_RCRCE \\r
+ | AT91C_MCI_RDIRE \\r
+ | AT91C_MCI_RINDE)\r
+\r
+/// MCI data timeout configuration with 1048576 MCK cycles between 2 data transfers.\r
+#define DTOR_1MEGA_CYCLES (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL)\r
+\r
+#define SDCARD_APP_OP_COND_CMD (41 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO )\r
+#define MMC_SEND_OP_COND_CMD (1 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_OPDCMD)\r
+\r
+\r
+#define DISABLE 0 // Disable MCI interface\r
+#define ENABLE 1 // Enable MCI interface\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+// Local macros\r
+//------------------------------------------------------------------------------\r
+\r
+/// Used to write in PMC registers.\r
+#define WRITE_PMC(pPmc, regName, value) pPmc->regName = (value)\r
+\r
+/// Used to write in MCI registers.\r
+#define WRITE_MCI(pMci, regName, value) pMci->regName = (value)\r
+\r
+/// Used to read from MCI registers.\r
+#define READ_MCI(pMci, regName) (pMci->regName)\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enable/disable a MCI driver instance.\r
+/// \param pMci Pointer to a MCI driver instance.\r
+/// \param enb 0 for disable MCI and 1 for enable MCI.\r
+//------------------------------------------------------------------------------\r
+void MCI_Enable(Mci *pMci, unsigned char enb)\r
+{\r
+ AT91S_MCI *pMciHw = pMci->pMciHw;\r
+\r
+ SANITY_CHECK(pMci);\r
+ SANITY_CHECK(pMci->pMciHw);\r
+\r
+ // Set the Control Register: Enable/Disable MCI interface clock\r
+ if(enb == DISABLE) {\r
+ WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS);\r
+ }\r
+ else {\r
+ WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIEN);\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initializes a MCI driver instance and the underlying peripheral.\r
+/// \param pMci Pointer to a MCI driver instance.\r
+/// \param pMciHw Pointer to a MCI peripheral.\r
+/// \param mciId MCI peripheral identifier.\r
+/// \param mode Slot and type of connected card.\r
+//------------------------------------------------------------------------------\r
+void MCI_Init(\r
+ Mci *pMci,\r
+ AT91S_MCI *pMciHw,\r
+ unsigned char mciId,\r
+ unsigned int mode)\r
+{\r
+ unsigned short clkDiv;\r
+\r
+ SANITY_CHECK(pMci);\r
+ SANITY_CHECK(pMciHw);\r
+ SANITY_CHECK((mode == MCI_MMC_SLOTA) || (mode == MCI_MMC_SLOTB)\r
+ || (mode == MCI_SD_SLOTA) || (mode == MCI_SD_SLOTB));\r
+\r
+ // Initialize the MCI driver structure\r
+ pMci->pMciHw = pMciHw;\r
+ pMci->mciId = mciId;\r
+ pMci->semaphore = 1;\r
+ pMci->pCommand = 0;\r
+\r
+ // Enable the MCI clock\r
+ WRITE_PMC(AT91C_BASE_PMC, PMC_PCER, (1 << mciId));\r
+ \r
+ // Reset the MCI\r
+ WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_SWRST);\r
+\r
+ // Disable the MCI\r
+ WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_PWSDIS);\r
+\r
+ // Disable all the interrupts\r
+ WRITE_MCI(pMciHw, MCI_IDR, 0xFFFFFFFF);\r
+\r
+ // Set the Data Timeout Register\r
+ WRITE_MCI(pMciHw, MCI_DTOR, DTOR_1MEGA_CYCLES);\r
+\r
+ // Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58)\r
+ clkDiv = (BOARD_MCK / (400000 * 2)) - 1;\r
+ WRITE_MCI(pMciHw, MCI_MR, (clkDiv | (AT91C_MCI_PWSDIV & (0x7 << 8))));\r
+\r
+ // Set the SDCard Register\r
+ WRITE_MCI(pMciHw, MCI_SDCR, mode);\r
+\r
+ // Enable the MCI and the Power Saving\r
+ WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIEN);\r
+\r
+ // Disable the MCI peripheral clock.\r
+ WRITE_PMC(AT91C_BASE_PMC, PMC_PCDR, (1 << mciId));\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Close a MCI driver instance and the underlying peripheral.\r
+/// \param pMci Pointer to a MCI driver instance.\r
+/// \param pMciHw Pointer to a MCI peripheral.\r
+/// \param mciId MCI peripheral identifier.\r
+//------------------------------------------------------------------------------\r
+void MCI_Close(Mci *pMci)\r
+{\r
+ AT91S_MCI *pMciHw = pMci->pMciHw;\r
+\r
+ SANITY_CHECK(pMci);\r
+ SANITY_CHECK(pMciHw);\r
+\r
+ // Initialize the MCI driver structure\r
+ pMci->semaphore = 1;\r
+ pMci->pCommand = 0;\r
+\r
+ // Disable the MCI peripheral clock.\r
+ WRITE_PMC(AT91C_BASE_PMC, PMC_PCDR, (1 << pMci->mciId));\r
+ \r
+ // Disable the MCI\r
+ WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS);\r
+\r
+ // Disable all the interrupts\r
+ WRITE_MCI(pMciHw, MCI_IDR, 0xFFFFFFFF);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configure the MCI CLKDIV in the MCI_MR register. The max. for MCI clock is \r
+/// MCK/2 and corresponds to CLKDIV = 0\r
+/// \param pMci Pointer to the low level MCI driver.\r
+/// \param mciSpeed MCI clock speed in Hz.\r
+//------------------------------------------------------------------------------\r
+void MCI_SetSpeed(Mci *pMci, unsigned int mciSpeed)\r
+{\r
+ AT91S_MCI *pMciHw = pMci->pMciHw;\r
+ unsigned int mciMr;\r
+ unsigned short clkdiv;\r
+\r
+ SANITY_CHECK(pMci);\r
+ SANITY_CHECK(pMci->pMciHw);\r
+\r
+ // Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58)\r
+ mciMr = READ_MCI(pMciHw, MCI_MR) & (~AT91C_MCI_CLKDIV);\r
+\r
+ // Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)\r
+ // divided by (2*(CLKDIV+1))\r
+ if (mciSpeed > 0) {\r
+\r
+ clkdiv = (BOARD_MCK / (mciSpeed * 2));\r
+ if (clkdiv > 0) {\r
+\r
+ clkdiv -= 1;\r
+ }\r
+ }\r
+ else {\r
+\r
+ clkdiv = 0;\r
+ }\r
+\r
+ WRITE_MCI(pMciHw, MCI_MR, mciMr | clkdiv);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configure the MCI SDCBUS in the MCI_SDCR register. Only two modes available\r
+/// \r
+/// \param pMci Pointer to the low level MCI driver.\r
+/// \param busWidth MCI bus width mode.\r
+//------------------------------------------------------------------------------\r
+void MCI_SetBusWidth(Mci *pMci, unsigned char busWidth)\r
+{\r
+ AT91S_MCI *pMciHw = pMci->pMciHw;\r
+ unsigned int mciSdcr;\r
+\r
+ SANITY_CHECK(pMci);\r
+ SANITY_CHECK(pMci->pMciHw);\r
+\r
+ mciSdcr = (READ_MCI(pMciHw, MCI_SDCR) & ~(AT91C_MCI_SCDBUS));\r
+\r
+ WRITE_MCI(pMciHw, MCI_SDCR, mciSdcr | busWidth);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts a MCI transfer. This is a non blocking function. It will return\r
+/// as soon as the transfer is started.\r
+/// Return 0 if successful; otherwise returns MCI_ERROR_LOCK if the driver is\r
+/// already in use.\r
+/// \param pMci Pointer to an MCI driver instance.\r
+/// \param pCommand Pointer to the command to execute.\r
+//------------------------------------------------------------------------------\r
+unsigned char MCI_SendCommand(Mci *pMci, MciCmd *pCommand)\r
+{\r
+ AT91PS_MCI pMciHw = pMci->pMciHw;\r
+ unsigned int mciIer, mciMr;\r
+\r
+ SANITY_CHECK(pMci);\r
+ SANITY_CHECK(pMciHw);\r
+ SANITY_CHECK(pCommand);\r
+\r
+ // Try to acquire the MCI semaphore\r
+ if (pMci->semaphore == 0) {\r
+ \r
+ return MCI_ERROR_LOCK;\r
+ }\r
+ pMci->semaphore--;\r
+ // trace_LOG(trace_DEBUG, "MCI_SendCommand %x %d\n\r", READ_MCI(pMciHw, MCI_SR), pCommand->cmd & 0x3f);\r
+\r
+ // Command is now being executed\r
+ pMci->pCommand = pCommand;\r
+ pCommand->status = MCI_STATUS_PENDING;\r
+\r
+ // Enable the MCI clock\r
+ WRITE_PMC(AT91C_BASE_PMC, PMC_PCER, (1 << pMci->mciId));\r
+\r
+ //Disable MCI clock, for multi-block data transfer\r
+ MCI_Enable(pMci, DISABLE);\r
+\r
+ // Set PDC data transfer direction\r
+ if(pCommand->blockSize > 0) {\r
+ if(pCommand->isRead) {\r
+ WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTEN);\r
+ }\r
+ else {\r
+ WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_TXTEN);\r
+ }\r
+ }\r
+ // Disable transmitter and receiver\r
+ WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS);\r
+\r
+ mciMr = READ_MCI(pMciHw, MCI_MR) & (~(AT91C_MCI_BLKLEN | AT91C_MCI_PDCMODE));\r
+\r
+ // Command with DATA stage\r
+ if (pCommand->blockSize > 0) {\r
+ // Enable PDC mode and set block size\r
+ if(pCommand->conTrans != MCI_CONTINUE_TRANSFER) {\r
+\r
+ WRITE_MCI(pMciHw, MCI_MR, mciMr | AT91C_MCI_PDCMODE | (pCommand->blockSize << 16));\r
+ }\r
+\r
+ // DATA transfer from card to host\r
+ if (pCommand->isRead) { \r
+ WRITE_MCI(pMciHw, MCI_RPR, (int) pCommand->pData);\r
+\r
+ // If Multiblock command set the BLKR register\r
+ /* if (pCommand->nbBlock > 1) { \r
+ WRITE_MCI(pMciHw, MCI_BLKR, pCommand->nbBlock | (pCommand->blockSize << 16));\r
+ }\r
+ else {\r
+ WRITE_MCI(pMciHw, MCI_BLKR, (pCommand->blockSize << 16)); \r
+ }*/\r
+\r
+ // Sanity check\r
+ if (pCommand->nbBlock == 0)\r
+ pCommand->nbBlock = 1;\r
+ ////////\r
+ if ((pCommand->blockSize & 0x3) != 0) {\r
+ WRITE_MCI(pMciHw, MCI_RCR, (pCommand->nbBlock * pCommand->blockSize) / 4 + 1);\r
+ }\r
+ else {\r
+ WRITE_MCI(pMciHw, MCI_RCR, (pCommand->nbBlock * pCommand->blockSize) / 4);\r
+ }\r
+\r
+ WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTEN);\r
+ mciIer = AT91C_MCI_ENDRX | STATUS_ERRORS;\r
+ // mciIer = AT91C_MCI_RXBUFF | STATUS_ERRORS;\r
+ }\r
+\r
+ // DATA transfer from host to card\r
+ else {\r
+ // Sanity check\r
+ if (pCommand->nbBlock == 0)\r
+ pCommand->nbBlock = 1;\r
+ WRITE_MCI(pMciHw, MCI_TPR, (int) pCommand->pData);\r
+ // Update the PDC counter\r
+ if ((pCommand->blockSize & 0x3) != 0) {\r
+ WRITE_MCI(pMciHw, MCI_TCR, (pCommand->nbBlock * pCommand->blockSize) / 4 + 1);\r
+ }\r
+ else {\r
+ WRITE_MCI(pMciHw, MCI_TCR, (pCommand->nbBlock * pCommand->blockSize) / 4);\r
+ }\r
+ // MCI_BLKE notifies the end of Multiblock command\r
+ mciIer = AT91C_MCI_BLKE | STATUS_ERRORS;\r
+ }\r
+ }\r
+ // No data transfer: stop at the end of the command\r
+ else {\r
+ WRITE_MCI(pMciHw, MCI_MR, mciMr);\r
+ mciIer = AT91C_MCI_CMDRDY | STATUS_ERRORS;\r
+ }\r
+ // Enable MCI clock\r
+ MCI_Enable(pMci, ENABLE);\r
+\r
+ // Send the command\r
+ if((pCommand->conTrans != MCI_CONTINUE_TRANSFER) \r
+ || (pCommand->blockSize == 0)) {\r
+\r
+ WRITE_MCI(pMciHw, MCI_ARGR, pCommand->arg);\r
+ WRITE_MCI(pMciHw, MCI_CMDR, pCommand->cmd);\r
+ }\r
+\r
+ // In case of transmit, the PDC shall be enabled after sending the command\r
+ if ((pCommand->blockSize > 0) && !(pCommand->isRead)) {\r
+ WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_TXTEN);\r
+ }\r
+\r
+ // Ignore data error\r
+// if (pCommand->blockSize == 0) {\r
+ {\r
+ mciIer &= ~(AT91C_MCI_UNRE | AT91C_MCI_OVRE \\r
+ | AT91C_MCI_DTOE | AT91C_MCI_DCRCE);\r
+ }\r
+\r
+ // Interrupt enable shall be done after PDC TXTEN and RXTEN\r
+ WRITE_MCI(pMciHw, MCI_IER, mciIer);\r
+\r
+ return 0;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Check NOTBUSY and DTIP bits of status register on the given MCI driver.\r
+/// Return value, 0 for bus ready, 1 for bus busy\r
+/// \param pMci Pointer to a MCI driver instance.\r
+//------------------------------------------------------------------------------\r
+unsigned char MCI_CheckBusy(Mci *pMci)\r
+{\r
+ AT91S_MCI *pMciHw = pMci->pMciHw;\r
+ unsigned int status;\r
+\r
+ // Enable MCI clock\r
+ MCI_Enable(pMci, ENABLE);\r
+\r
+ status = READ_MCI(pMciHw, MCI_SR);\r
+ // trace_LOG(trace_DEBUG, "status %x\n\r",status);\r
+\r
+\r
+ if(((status & AT91C_MCI_NOTBUSY)!=0)\r
+ && ((status & AT91C_MCI_DTIP)==0)) {\r
+\r
+ // Disable MCI clock\r
+ MCI_Enable(pMci, DISABLE);\r
+\r
+ return 0;\r
+ }\r
+ else {\r
+ return 1;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Check BLKE bit of status register on the given MCI driver.\r
+/// \param pMci Pointer to a MCI driver instance.\r
+//------------------------------------------------------------------------------\r
+unsigned char MCI_CheckBlke(Mci *pMci)\r
+{\r
+ AT91S_MCI *pMciHw = pMci->pMciHw;\r
+ unsigned int status;\r
+\r
+ status = READ_MCI(pMciHw, MCI_SR);\r
+ // trace_LOG(trace_DEBUG, "status %x\n\r",status);\r
+\r
+ if((status & AT91C_MCI_BLKE)!=0) {\r
+ return 0;\r
+ }\r
+ else {\r
+ return 1;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Processes pending events on the given MCI driver.\r
+/// \param pMci Pointer to a MCI driver instance.\r
+//------------------------------------------------------------------------------\r
+void MCI_Handler(Mci *pMci)\r
+{\r
+ AT91S_MCI *pMciHw = pMci->pMciHw;\r
+ MciCmd *pCommand = pMci->pCommand;\r
+ unsigned int status;\r
+ unsigned char i;\r
+ #if defined(at91rm9200)\r
+ unsigned int mciCr, mciSdcr, mciMr, mciDtor;\r
+ #endif\r
+\r
+ SANITY_CHECK(pMci);\r
+ SANITY_CHECK(pMciHw);\r
+ SANITY_CHECK(pCommand);\r
+\r
+ // Read the status register\r
+ status = READ_MCI(pMciHw, MCI_SR) & READ_MCI(pMciHw, MCI_IMR);\r
+ // trace_LOG(trace_DEBUG, "status %x\n\r", status);\r
+\r
+ // Check if an error has occured\r
+ if ((status & STATUS_ERRORS) != 0) {\r
+\r
+ // Check error code\r
+ if ((status & STATUS_ERRORS) == AT91C_MCI_RTOE) {\r
+ \r
+ pCommand->status = MCI_STATUS_NORESPONSE;\r
+ }\r
+ // if the command is SEND_OP_COND the CRC error flag is always present\r
+ // (cf : R3 response)\r
+ else if (((status & STATUS_ERRORS) != AT91C_MCI_RCRCE)\r
+ || ((pCommand->cmd != SDCARD_APP_OP_COND_CMD)\r
+ && (pCommand->cmd != MMC_SEND_OP_COND_CMD))) {\r
+\r
+ pCommand->status = MCI_STATUS_ERROR;\r
+ }\r
+ }\r
+\r
+ // Check if a transfer has been completed\r
+ if (((status & AT91C_MCI_CMDRDY) != 0)\r
+ || ((status & AT91C_MCI_ENDRX) != 0)\r
+ || ((status & AT91C_MCI_RXBUFF) != 0)\r
+ || ((status & AT91C_MCI_ENDTX) != 0)\r
+ || ((status & AT91C_MCI_BLKE) != 0)\r
+ || ((status & AT91C_MCI_RTOE) != 0)) {\r
+\r
+ if (((status & AT91C_MCI_ENDRX) != 0)\r
+ || ((status & AT91C_MCI_RXBUFF) != 0)\r
+ || ((status & AT91C_MCI_ENDTX) != 0)) {\r
+\r
+ MCI_Enable(pMci, DISABLE);\r
+ }\r
+\r
+ /// On AT91RM9200-EK, if stop transmission, software reset MCI.\r
+ #if defined(at91rm9200)\r
+ if ((pCommand->cmd & AT91C_MCI_TRCMD_STOP) != 0) {\r
+ mciMr = READ_MCI(pMciHw, MCI_MR);\r
+ mciSdcr = READ_MCI(pMciHw, MCI_SDCR);\r
+ mciDtor = READ_MCI(pMciHw, MCI_DTOR);\r
+ WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_SWRST);\r
+ // trace_LOG(trace_DEBUG, "reset MCI\n\r");\r
+\r
+ WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_PWSDIS);\r
+ WRITE_MCI(pMciHw, MCI_MR, mciMr);\r
+ WRITE_MCI(pMciHw, MCI_SDCR, mciSdcr);\r
+ WRITE_MCI(pMciHw, MCI_DTOR, mciDtor);\r
+ }\r
+ #endif\r
+\r
+ // If no error occured, the transfer is successful\r
+ if (pCommand->status == MCI_STATUS_PENDING) {\r
+ pCommand->status = 0;\r
+ }\r
+#if 0\r
+ if ((status & AT91C_MCI_CMDRDY) != 0)\r
+ trace_LOG(trace_DEBUG, ".");\r
+ if ((status & AT91C_MCI_ENDRX) != 0)\r
+ trace_LOG(trace_DEBUG, "<");\r
+ if ((status & AT91C_MCI_ENDTX) != 0)\r
+ trace_LOG(trace_DEBUG, "-");\r
+ if ((status & AT91C_MCI_BLKE) != 0)\r
+ trace_LOG(trace_DEBUG, ">");\r
+ trace_LOG(trace_DEBUG, "\n\r");\r
+#endif \r
+ // Store the card response in the provided buffer\r
+ if (pCommand->pResp) {\r
+\r
+ for (i=0; i < pCommand->resSize; i++) {\r
+\r
+ pCommand->pResp[i] = READ_MCI(pMciHw, MCI_RSPR[0]);\r
+ }\r
+ }\r
+\r
+ // Disable interrupts\r
+ WRITE_MCI(pMciHw, MCI_IDR, READ_MCI(pMciHw, MCI_IMR));\r
+\r
+ // Release the semaphore\r
+ pMci->semaphore++;\r
+\r
+ // Invoke the callback associated with the current command (if any)\r
+ if (pCommand->callback) {\r
+ (pCommand->callback)(pCommand->status, pCommand);\r
+ }\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns 1 if the given MCI transfer is complete; otherwise returns 0.\r
+/// \param pCommand Pointer to a MciCmd instance.\r
+//------------------------------------------------------------------------------\r
+unsigned char MCI_IsTxComplete(MciCmd *pCommand)\r
+{\r
+ if (pCommand->status != MCI_STATUS_PENDING) {\r
+ if (pCommand->status != 0)\r
+ printf("MCI_IsTxComplete %d\n\r", pCommand->status);\r
+ return 1;\r
+ }\r
+ else {\r
+ return 0;\r
+ }\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support - ROUSSET -\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2006, Atmel Corporation\r
+\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * - Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the disclaimer below in the documentation and/or\r
+ * other materials provided with the distribution.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef MCI_H\r
+#define MCI_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Constants\r
+//------------------------------------------------------------------------------\r
+\r
+/// Transfer is pending.\r
+#define MCI_STATUS_PENDING 1\r
+/// Transfer has been aborted because an error occured.\r
+#define MCI_STATUS_ERROR 2\r
+/// Card did not answer command.\r
+#define MCI_STATUS_NORESPONSE 3\r
+\r
+/// MCI driver is currently in use.\r
+#define MCI_ERROR_LOCK 1\r
+\r
+/// MCI configuration with 1-bit data bus on slot A (for MMC cards).\r
+#define MCI_MMC_SLOTA 0\r
+/// MCI configuration with 1-bit data bus on slot B (for MMC cards).\r
+#define MCI_MMC_SLOTB 1\r
+/// MCI configuration with 4-bit data bus on slot A (for SD cards).\r
+#define MCI_SD_SLOTA AT91C_MCI_SCDBUS\r
+/// MCI configuration with 4-bit data bus on slot B (for SD cards).\r
+#define MCI_SD_SLOTB (AT91C_MCI_SCDBUS | 1)\r
+\r
+/// Start new data transfer\r
+#define MCI_NEW_TRANSFER 0\r
+/// Continue data transfer\r
+#define MCI_CONTINUE_TRANSFER 1\r
+\r
+/// MCI SD Bus Width 1-bit\r
+#define MCI_SDCBUS_1BIT (0 << 7)\r
+/// MCI SD Bus Width 4-bit\r
+#define MCI_SDCBUS_4BIT (1 << 7)\r
+\r
+//------------------------------------------------------------------------------\r
+// Types\r
+//------------------------------------------------------------------------------\r
+\r
+/// MCI end-of-transfer callback function.\r
+typedef void (*MciCallback)(unsigned char status, void *pCommand);\r
+\r
+//------------------------------------------------------------------------------\r
+/// MCI Transfer Request prepared by the application upper layer. This structure\r
+/// is sent to the MCI_SendCommand function to start the transfer. At the end of \r
+/// the transfer, the callback is invoked by the interrupt handler.\r
+//------------------------------------------------------------------------------\r
+typedef struct _MciCmd {\r
+\r
+ /// Command status.\r
+ volatile char status;\r
+ /// Command code.\r
+ unsigned int cmd;\r
+ /// Command argument.\r
+ unsigned int arg;\r
+ /// Data buffer.\r
+ unsigned char *pData;\r
+ /// Size of data buffer in bytes.\r
+ unsigned short blockSize;\r
+ /// Number of blocks to be transfered\r
+ unsigned short nbBlock;\r
+ /// Indicate if continue to transfer data\r
+ unsigned char conTrans;\r
+ /// Indicates if the command is a read operation.\r
+ unsigned char isRead;\r
+ /// Response buffer.\r
+ unsigned int *pResp;\r
+ /// Size of SD card response in bytes.\r
+ unsigned char resSize;\r
+ /// Optional user-provided callback function.\r
+ MciCallback callback;\r
+ /// Optional argument to the callback function.\r
+ void *pArg;\r
+\r
+} MciCmd;\r
+\r
+//------------------------------------------------------------------------------\r
+/// MCI driver structure. Holds the internal state of the MCI driver and\r
+/// prevents parallel access to a MCI peripheral.\r
+//------------------------------------------------------------------------------\r
+typedef struct {\r
+\r
+ /// Pointer to a MCI peripheral.\r
+ AT91S_MCI *pMciHw;\r
+ /// MCI peripheral identifier.\r
+ unsigned char mciId;\r
+ /// Pointer to currently executing command.\r
+ MciCmd *pCommand;\r
+ /// Mutex.\r
+ volatile char semaphore;\r
+\r
+} Mci;\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void MCI_Init(\r
+ Mci *pMci,\r
+ AT91PS_MCI pMciHw,\r
+ unsigned char mciId,\r
+ unsigned int mode);\r
+\r
+extern void MCI_SetSpeed(Mci *pMci, unsigned int mciSpeed);\r
+\r
+extern unsigned char MCI_SendCommand(Mci *pMci, MciCmd *pMciCmd);\r
+\r
+extern void MCI_Handler(Mci *pMci);\r
+\r
+extern unsigned char MCI_IsTxComplete(MciCmd *pMciCmd);\r
+\r
+extern unsigned char MCI_CheckBusy(Mci *pMci);\r
+\r
+extern void MCI_Close(Mci *pMci);\r
+\r
+extern void MCI_SetBusWidth(Mci *pMci, unsigned char busWidth);\r
+\r
+#endif //#ifndef MCI_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "pio.h"\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Internal definitions\r
+//------------------------------------------------------------------------------\r
+/// \internal Returns the current value of a register.\r
+#define READ(peripheral, register) (peripheral->register)\r
+/// \internal Modifies the current value of a register.\r
+#define WRITE(peripheral, register, value) (peripheral->register = value)\r
+\r
+//------------------------------------------------------------------------------\r
+// Internal functions\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// Configures one or more pin(s) of a PIO controller as being controlled by\r
+/// peripheral A. Optionally, the corresponding internal pull-up(s) can be\r
+/// enabled.\r
+/// \param pio Pointer to a PIO controller.\r
+/// \param mask Bitmask of one or more pin(s) to configure.\r
+/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be\r
+/// configured.\r
+//------------------------------------------------------------------------------\r
+static void PIO_SetPeripheralA(AT91S_PIO *pio,\r
+ unsigned int mask,\r
+ unsigned char enablePullUp)\r
+{\r
+ // Disable interrupts on the pin(s)\r
+ WRITE(pio, PIO_IDR, mask);\r
+\r
+ // Enable the pull-up(s) if necessary\r
+ if (enablePullUp) {\r
+\r
+ WRITE(pio, PIO_PPUER, mask);\r
+ }\r
+ else {\r
+\r
+ WRITE(pio, PIO_PPUDR, mask);\r
+ }\r
+\r
+ // Configure pin\r
+ WRITE(pio, PIO_ASR, mask);\r
+ WRITE(pio, PIO_PDR, mask);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures one or more pin(s) of a PIO controller as being controlled by\r
+/// peripheral A. Optionally, the corresponding internal pull-up(s) can be\r
+/// enabled.\r
+/// \param pio Pointer to a PIO controller.\r
+/// \param mask Bitmask of one or more pin(s) to configure.\r
+/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be\r
+/// configured.\r
+//------------------------------------------------------------------------------\r
+static void PIO_SetPeripheralB(AT91S_PIO *pio,\r
+ unsigned int mask,\r
+ unsigned char enablePullUp)\r
+{\r
+ // Disable interrupts on the pin(s)\r
+ WRITE(pio, PIO_IDR, mask);\r
+\r
+ // Enable the pull-up(s) if necessary\r
+ if (enablePullUp) {\r
+\r
+ WRITE(pio, PIO_PPUER, mask);\r
+ }\r
+ else {\r
+\r
+ WRITE(pio, PIO_PPUDR, mask);\r
+ }\r
+\r
+ // Configure pin\r
+ WRITE(pio, PIO_BSR, mask);\r
+ WRITE(pio, PIO_PDR, mask);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures one or more pin(s) or a PIO controller as inputs. Optionally,\r
+/// the corresponding internal pull-up(s) and glitch filter(s) can be\r
+/// enabled.\r
+/// \param pio Pointer to a PIO controller.\r
+/// \param mask Bitmask indicating which pin(s) to configure as input(s).\r
+/// \param enablePullUp Indicates if the internal pull-up(s) must be enabled.\r
+/// \param enableFilter Indicates if the glitch filter(s) must be enabled.\r
+//------------------------------------------------------------------------------\r
+static void PIO_SetInput(AT91S_PIO *pio,\r
+ unsigned int mask,\r
+ unsigned char enablePullUp,\r
+ unsigned char enableFilter)\r
+{\r
+ // Disable interrupts\r
+ WRITE(pio, PIO_IDR, mask);\r
+\r
+ // Enable pull-up(s) if necessary\r
+ if (enablePullUp) {\r
+ \r
+ WRITE(pio, PIO_PPUER, mask);\r
+ }\r
+ else {\r
+ \r
+ WRITE(pio, PIO_PPUDR, mask);\r
+ }\r
+\r
+ // Enable filter(s) if necessary\r
+ if (enableFilter) {\r
+ \r
+ WRITE(pio, PIO_IFER, mask);\r
+ }\r
+ else {\r
+ \r
+ WRITE(pio, PIO_IFDR, mask);\r
+ }\r
+\r
+ // Configure pin as input\r
+ WRITE(pio, PIO_ODR, mask);\r
+ WRITE(pio, PIO_PER, mask);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures one or more pin(s) of a PIO controller as outputs, with the\r
+/// given default value. Optionally, the multi-drive feature can be enabled\r
+/// on the pin(s).\r
+/// \param pio Pointer to a PIO controller.\r
+/// \param mask Bitmask indicating which pin(s) to configure.\r
+/// \param defaultValue Default level on the pin(s).\r
+/// \param enableMultiDrive Indicates if the pin(s) shall be configured as\r
+/// open-drain.\r
+/// \param enablePullUp Indicates if the pin shall have its pull-up activated.\r
+//------------------------------------------------------------------------------\r
+static void PIO_SetOutput(AT91S_PIO *pio,\r
+ unsigned int mask,\r
+ unsigned char defaultValue,\r
+ unsigned char enableMultiDrive,\r
+ unsigned char enablePullUp)\r
+{\r
+ // Disable interrupts\r
+ WRITE(pio, PIO_IDR, mask);\r
+\r
+ // Enable pull-up(s) if necessary\r
+ if (enablePullUp) {\r
+ \r
+ WRITE(pio, PIO_PPUER, mask);\r
+ }\r
+ else {\r
+ \r
+ WRITE(pio, PIO_PPUDR, mask);\r
+ }\r
+\r
+ // Enable multi-drive if necessary\r
+ if (enableMultiDrive) {\r
+ \r
+ WRITE(pio, PIO_MDER, mask);\r
+ }\r
+ else {\r
+ \r
+ WRITE(pio, PIO_MDDR, mask);\r
+ }\r
+\r
+ // Set default value\r
+ if (defaultValue) {\r
+\r
+ WRITE(pio, PIO_SODR, mask);\r
+ }\r
+ else {\r
+\r
+ WRITE(pio, PIO_CODR, mask);\r
+ }\r
+\r
+ // Configure pin(s) as output(s)\r
+ WRITE(pio, PIO_OER, mask);\r
+ WRITE(pio, PIO_PER, mask);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// Configures a list of Pin instances, which can either hold a single pin or a \r
+/// group of pins, depending on the mask value; all pins are configured by this \r
+/// function.\r
+/// Returns 1 if the configuration has been performed successfully; otherwise 0.\r
+/// \param list Pointer to a list of Pin instances.\r
+/// \param size Size of the Pin list (see <PIO_LISTSIZE>).\r
+//------------------------------------------------------------------------------\r
+unsigned char PIO_Configure(const Pin *list, unsigned int size)\r
+{\r
+ // Configure pins\r
+ while (size > 0) {\r
+ \r
+ switch (list->type) {\r
+ \r
+ case PIO_PERIPH_A:\r
+ PIO_SetPeripheralA(list->pio,\r
+ list->mask,\r
+ (list->attribute & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+ \r
+ case PIO_PERIPH_B:\r
+ PIO_SetPeripheralB(list->pio,\r
+ list->mask,\r
+ (list->attribute & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+ \r
+ case PIO_INPUT:\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << list->id;\r
+ PIO_SetInput(list->pio,\r
+ list->mask,\r
+ (list->attribute & PIO_PULLUP) ? 1 : 0,\r
+ (list->attribute & PIO_DEGLITCH)? 1 : 0);\r
+ break;\r
+ \r
+ case PIO_OUTPUT_0:\r
+ case PIO_OUTPUT_1:\r
+ PIO_SetOutput(list->pio,\r
+ list->mask,\r
+ (list->type == PIO_OUTPUT_1),\r
+ (list->attribute & PIO_OPENDRAIN) ? 1 : 0,\r
+ (list->attribute & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+ \r
+ default: return 0;\r
+ }\r
+\r
+ list++;\r
+ size--;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets a high output level on one or more pin(s) (if configured as output(s)).\r
+/// \param pin Pointer to a Pin instance describing one or more pins.\r
+//------------------------------------------------------------------------------\r
+void PIO_Set(const Pin *pin)\r
+{\r
+ WRITE(pin->pio, PIO_SODR, pin->mask);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets a low output level on one or more pin(s) (if configured as output(s)).\r
+/// \param pin Pointer to a Pin instance describing one or more pins.\r
+//------------------------------------------------------------------------------\r
+void PIO_Clear(const Pin *pin)\r
+{\r
+ WRITE(pin->pio, PIO_CODR, pin->mask);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns 1 if one or more PIO of the given Pin instance currently have a high\r
+/// level; otherwise returns 0.\r
+/// \param pin Pointer to a Pin instance describing one or more pins.\r
+//------------------------------------------------------------------------------\r
+unsigned char PIO_Get(const Pin *pin)\r
+{\r
+ unsigned int reg;\r
+ if ((pin->type == PIO_OUTPUT_0) || (pin->type == PIO_OUTPUT_1)) {\r
+\r
+ reg = READ(pin->pio, PIO_ODSR);\r
+ }\r
+ else {\r
+\r
+ reg = READ(pin->pio, PIO_PDSR);\r
+ }\r
+\r
+ if ((reg & pin->mask) == 0) {\r
+\r
+ return 0;\r
+ }\r
+ else {\r
+\r
+ return 1;\r
+ }\r
+}\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns 1 if one or more PIO of the given Pin data to be driven on the I/O line\r
+/// level; otherwise returns 0.\r
+/// \param pin Pointer to a Pin instance describing one or more pins.\r
+//------------------------------------------------------------------------------\r
+unsigned char PIO_GetOutputDataStatus(const Pin *pin)\r
+{\r
+ if ((READ(pin->pio, PIO_ODSR) & pin->mask) == 0) {\r
+\r
+ return 0;\r
+ }\r
+ else {\r
+\r
+ return 1;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the value of ISR for the PIO controller of the pin.\r
+/// Reading this register acknoledges all the ITs.\r
+/// \param pin Pointer to a Pin instance describing one or more pins.\r
+//------------------------------------------------------------------------------\r
+unsigned int PIO_GetISR(const Pin *pin)\r
+{\r
+ return (READ(pin->pio, PIO_ISR));\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \dir\r
+/// !Purpose\r
+///\r
+/// Definition of methods and structures for using PIOs in a transparent\r
+/// way. The main purpose is to allow portability between several boards.\r
+///\r
+/// !Usage\r
+///\r
+/// -# To configure and use pins, see pio.h.\r
+/// -# To enable and use interrupt generation on PIO status change, see\r
+/// pio_it.h.\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+/// !Purpose\r
+/// \r
+/// Simple & portable usage of PIO pins.\r
+/// \r
+/// !Usage\r
+/// \r
+/// -# Define a constant pin description array such as the following one:\r
+/// \code\r
+/// const Pin at91board_dbgu[] = {\r
+/// {AT91C_BASE_PIOA, (1 << 30), PIO_PERIPH_A, PIO_DEFAULT},\r
+/// {AT91C_BASE_PIOA, (1 << 31), PIO_PERIPH_A, PIO_DEFAULT},\r
+/// };\r
+/// \endcode\r
+/// Alternatively, constants defined in the piodefs.h header file of the\r
+/// board module can be used:\r
+/// \code\r
+/// const Pin at91board_dbgu[] = {PINS_DBGU};\r
+/// const Pin at91board_usart[] = {PIN_USART0_RXD, PIN_USART0_TXD};\r
+/// \endcode\r
+/// It is possible to group multiple pins if they share the same\r
+/// attributes, to save memory. Here is the previous DBGU example\r
+/// rewritten in such a way:\r
+/// \code\r
+/// const Pin at91board_dbgu[] = {\r
+/// {AT91C_BASE_PIOA, 0xC0000000, PIO_PERIPH_A, PIO_DEFAULT}\r
+/// };\r
+/// \endcode\r
+/// -# For pins configured as inputs, the PIO controller must be enabled\r
+/// in the PMC (*enabled by PIO_Configure at the moment*).\r
+/// -# Configure a pin array by calling PIO_Configure, using\r
+/// the PIO_LISTSIZE macro to calculate the array size if needed. Do not\r
+/// forget to check the return value for any error.\r
+/// -# Set and get the value of a pin using the PIO_Set, PIO_Clear and\r
+/// PIO_Get methods.\r
+//------------------------------------------------------------------------------\r
+ \r
+#ifndef PIO_H\r
+#define PIO_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// \page "Pin types" \r
+/// This page lists the available types for a Pin instance (in its type field).\r
+/// !Types\r
+/// - PIO_PERIPH_A \r
+/// - PIO_PERIPH_B \r
+/// - PIO_INPUT \r
+/// - PIO_OUTPUT_0 \r
+/// - PIO_OUTPUT_1 \r
+\r
+/// The pin is controlled by the associated signal of peripheral A.\r
+#define PIO_PERIPH_A 0\r
+/// The pin is controlled by the associated signal of peripheral B.\r
+#define PIO_PERIPH_B 1\r
+/// The pin is an input.\r
+#define PIO_INPUT 2\r
+/// The pin is an output and has a default level of 0.\r
+#define PIO_OUTPUT_0 3\r
+/// The pin is an output and has a default level of 1.\r
+#define PIO_OUTPUT_1 4\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "Pin attributes"\r
+/// This page lists the valid values for the attribute field of a Pin instance.\r
+/// !Attributes\r
+/// - PIO_DEFAULT\r
+/// - PIO_PULLUP\r
+/// - PIO_DEGLITCH\r
+/// - PIO_OPENDRAIN\r
+\r
+/// Default pin configuration (no attribute).\r
+#define PIO_DEFAULT (0 << 0)\r
+/// The internal pin pull-up is active.\r
+#define PIO_PULLUP (1 << 0)\r
+/// The internal glitch filter is active.\r
+#define PIO_DEGLITCH (1 << 1)\r
+/// The pin is open-drain.\r
+#define PIO_OPENDRAIN (1 << 2)\r
+//------------------------------------------------------------------------------\r
+\r
+/// Calculates the size of a Pin instances array. The array must be local (i.e.\r
+/// not a pointer), otherwise the computation will not be correct.\r
+#define PIO_LISTSIZE(list) (sizeof(list) / sizeof(Pin))\r
+\r
+//------------------------------------------------------------------------------\r
+// Types\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// Describes the type and attribute of one PIO pin or a group of similar pins.\r
+typedef struct {\r
+ /// Bitmask indicating which pin(s) to configure.\r
+ unsigned int mask; \r
+ /// Pointer to the PIO controller which has the pin(s).\r
+ AT91S_PIO *pio;\r
+ /// Peripheral ID of the PIO controller which has the pin(s).\r
+ unsigned char id;\r
+ /// Pin type (see "Pin types").\r
+ unsigned char type;\r
+ /// Pin attribute (see "Pin attributes").\r
+ unsigned char attribute;\r
+} Pin;\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+extern unsigned char PIO_Configure(const Pin *list, unsigned int size);\r
+extern void PIO_Set(const Pin *pin );\r
+extern void PIO_Clear(const Pin *pin);\r
+extern unsigned char PIO_Get(const Pin *pin);\r
+extern unsigned int PIO_GetISR(const Pin *pin);\r
+extern unsigned char PIO_GetOutputDataStatus(const Pin *pin);\r
+\r
+#endif //#ifndef PIO_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/// Disable traces for this file\r
+#ifndef NOTRACE\r
+ #define NOTRACE\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "pio_it.h"\r
+#include "pio.h"\r
+#include <aic/aic.h>\r
+#include <board.h>\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Local definitions\r
+//------------------------------------------------------------------------------\r
+\r
+/// Returns the current value of a register.\r
+#define READ(peripheral, register) (peripheral->register)\r
+/// Modifies the current value of a register.\r
+#define WRITE(peripheral, register, value) (peripheral->register = value)\r
+\r
+/// Maximum number of interrupt sources that can be defined.\r
+#define MAX_INTERRUPT_SOURCES 7\r
+\r
+//------------------------------------------------------------------------------\r
+// Local types\r
+//------------------------------------------------------------------------------\r
+\r
+/// Describes a PIO interrupt source, including the PIO instance triggering the\r
+/// interrupt and the associated interrupt handler.\r
+typedef struct _InterruptSource {\r
+\r
+ /// Interrupt source pin.\r
+ const Pin *pPin;\r
+\r
+ /// Interrupt handler.\r
+ void (*handler)(const Pin *);\r
+\r
+} InterruptSource;\r
+\r
+//------------------------------------------------------------------------------\r
+// Local variables\r
+//------------------------------------------------------------------------------\r
+\r
+/// List of interrupt sources.\r
+static InterruptSource pSources[MAX_INTERRUPT_SOURCES];\r
+\r
+/// Number of currently defined interrupt sources.\r
+static unsigned int numSources;\r
+\r
+//------------------------------------------------------------------------------\r
+// Local functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Handles all interrupts on the given PIO controller.\r
+/// \param id PIO controller ID.\r
+/// \param pBase PIO controller base address.\r
+//------------------------------------------------------------------------------\r
+void PioInterruptHandler(unsigned int id, AT91S_PIO *pBase)\r
+{\r
+ unsigned int status;\r
+ unsigned int i;\r
+\r
+ // Check PIO controller status\r
+ status = pBase->PIO_ISR;\r
+ status &= pBase->PIO_IMR;\r
+ if (status != 0) {\r
+\r
+ trace_LOG(trace_DEBUG, "-D- PIO interrupt on PIO controller #%d\n\r", id);\r
+\r
+ // Check all sources\r
+ i = 0;\r
+ while (status != 0) {\r
+\r
+ // There cannot be an unconfigured source enabled.\r
+ SANITY_CHECK(i < numSources);\r
+\r
+ // Source if configured on PIOA\r
+ if (pSources[i].pPin->id == id) {\r
+\r
+ // Source has PIOs which have changed\r
+ if ((status & pSources[i].pPin->mask) != 0) {\r
+\r
+ trace_LOG(trace_DEBUG, "-D- Interrupt source #%d triggered\n\r", i);\r
+\r
+ pSources[i].handler(pSources[i].pPin);\r
+ status &= ~(pSources[i].pPin->mask);\r
+ }\r
+ }\r
+ i++;\r
+ }\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Generic PIO interrupt handler. Single entry point for interrupts coming\r
+/// from any PIO controller (PIO A, B, C ...). Dispatches the interrupt to\r
+/// the user-configured handlers.\r
+//------------------------------------------------------------------------------\r
+void InterruptHandler()\r
+{\r
+#if defined(AT91C_ID_PIOA)\r
+ // Treat PIOA interrupts\r
+ PioInterruptHandler(AT91C_ID_PIOA, AT91C_BASE_PIOA);\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOB)\r
+ // Treat PIOB interrupts\r
+ PioInterruptHandler(AT91C_ID_PIOB, AT91C_BASE_PIOB);\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOC)\r
+ // Treat PIOC interrupts\r
+ PioInterruptHandler(AT91C_ID_PIOC, AT91C_BASE_PIOC);\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOD)\r
+ // Treat PIOD interrupts\r
+ PioInterruptHandler(AT91C_ID_PIOD, AT91C_BASE_PIOD);\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOE)\r
+ // Treat PIOE interrupts\r
+ PioInterruptHandler(AT91C_ID_PIOE, AT91C_BASE_PIOE);\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOABCD)\r
+ // Treat PIOABCD interrupts\r
+ #if !defined(AT91C_ID_PIOA)\r
+ PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOA);\r
+ #endif\r
+ #if !defined(AT91C_ID_PIOB)\r
+ PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOB);\r
+ #endif\r
+ #if !defined(AT91C_ID_PIOC)\r
+ PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOC);\r
+ #endif\r
+ #if !defined(AT91C_ID_PIOD)\r
+ PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOD);\r
+ #endif\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOABCDE)\r
+ // Treat PIOABCDE interrupts\r
+ #if !defined(AT91C_ID_PIOA)\r
+ PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOA);\r
+ #endif\r
+ #if !defined(AT91C_ID_PIOB)\r
+ PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOB);\r
+ #endif\r
+ #if !defined(AT91C_ID_PIOC)\r
+ PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOC);\r
+ #endif\r
+ #if !defined(AT91C_ID_PIOD)\r
+ PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOD);\r
+ #endif\r
+ #if !defined(AT91C_ID_PIOE)\r
+ PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOE);\r
+ #endif\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOCDE)\r
+ // Treat PIOCDE interrupts\r
+ #if !defined(AT91C_ID_PIOC)\r
+ PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOC);\r
+ #endif\r
+ #if !defined(AT91C_ID_PIOD)\r
+ PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOD);\r
+ #endif\r
+ #if !defined(AT91C_ID_PIOE)\r
+ PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOE);\r
+ #endif\r
+#endif\r
+\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initializes the PIO interrupt management logic.\r
+/// \param priority PIO controller interrupts priority.\r
+//------------------------------------------------------------------------------\r
+void PIO_InitializeInterrupts(unsigned int priority)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- PIO_Initialize()\n\r");\r
+\r
+ SANITY_CHECK((priority & ~AT91C_AIC_PRIOR) == 0);\r
+\r
+ // Reset sources\r
+ numSources = 0;\r
+\r
+#ifdef AT91C_ID_PIOA\r
+ // Configure PIO interrupt sources\r
+ trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOA\n\r");\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA;\r
+ AT91C_BASE_PIOA->PIO_ISR;\r
+ AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF;\r
+ AIC_ConfigureIT(AT91C_ID_PIOA, priority, InterruptHandler);\r
+ AIC_EnableIT(AT91C_ID_PIOA);\r
+#endif\r
+\r
+#ifdef AT91C_ID_PIOB\r
+ trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOB\n\r");\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB;\r
+ AT91C_BASE_PIOB->PIO_ISR;\r
+ AT91C_BASE_PIOB->PIO_IDR = 0xFFFFFFFF;\r
+ AIC_ConfigureIT(AT91C_ID_PIOB, priority, InterruptHandler);\r
+ AIC_EnableIT(AT91C_ID_PIOB);\r
+#endif\r
+\r
+#ifdef AT91C_ID_PIOC\r
+ trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOC\n\r");\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOC;\r
+ AT91C_BASE_PIOC->PIO_ISR;\r
+ AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;\r
+ AIC_ConfigureIT(AT91C_ID_PIOC, priority, InterruptHandler);\r
+ AIC_EnableIT(AT91C_ID_PIOC);\r
+#endif\r
+\r
+#ifdef AT91C_ID_PIOD\r
+ trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOD\n\r");\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOD;\r
+ AT91C_BASE_PIOC->PIO_ISR;\r
+ AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;\r
+ AIC_ConfigureIT(AT91C_ID_PIOD, priority, InterruptHandler);\r
+ AIC_EnableIT(AT91C_ID_PIOD);\r
+#endif\r
+\r
+#ifdef AT91C_ID_PIOE\r
+ trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOE\n\r");\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOE;\r
+ AT91C_BASE_PIOC->PIO_ISR;\r
+ AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;\r
+ AIC_ConfigureIT(AT91C_ID_PIOE, priority, InterruptHandler);\r
+ AIC_EnableIT(AT91C_ID_PIOE);\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOABCD)\r
+ // Treat PIOABCD interrupts\r
+ #if !defined(AT91C_ID_PIOA) \\r
+ && !defined(AT91C_ID_PIOB) \\r
+ && !defined(AT91C_ID_PIOC) \\r
+ && !defined(AT91C_ID_PIOD)\r
+\r
+ trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOABCD\n\r");\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;\r
+ AT91C_BASE_PIOA->PIO_ISR;\r
+ AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF;\r
+ AIC_ConfigureIT(AT91C_ID_PIOABCD, priority, InterruptHandler);\r
+ AIC_EnableIT(AT91C_ID_PIOABCD);\r
+ #endif\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOABCDE)\r
+ // Treat PIOABCDE interrupts\r
+ #if !defined(AT91C_ID_PIOA) \\r
+ && !defined(AT91C_ID_PIOB) \\r
+ && !defined(AT91C_ID_PIOC) \\r
+ && !defined(AT91C_ID_PIOD) \\r
+ && !defined(AT91C_ID_PIOE)\r
+\r
+ trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOABCDE\n\r");\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCDE;\r
+ AT91C_BASE_PIOA->PIO_ISR;\r
+ AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF;\r
+ AIC_ConfigureIT(AT91C_ID_PIOABCDE, priority, InterruptHandler);\r
+ AIC_EnableIT(AT91C_ID_PIOABCDE);\r
+ #endif\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOCDE)\r
+ // Treat PIOCDE interrupts\r
+ #if !defined(AT91C_ID_PIOC) \\r
+ && !defined(AT91C_ID_PIOD) \\r
+ && !defined(AT91C_ID_PIOE)\r
+\r
+ trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOC\n\r");\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOCDE;\r
+ AT91C_BASE_PIOC->PIO_ISR;\r
+ AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;\r
+ AIC_ConfigureIT(AT91C_ID_PIOCDE, priority, InterruptHandler);\r
+ AIC_EnableIT(AT91C_ID_PIOCDE);\r
+ #endif\r
+#endif\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures an interrupt source.\r
+/// \param pPin Interrupt source.\r
+/// \param handler Desired interrupt handler for the source.\r
+//------------------------------------------------------------------------------\r
+void PIO_ConfigureIt(const Pin *pPin, void (*handler)(const Pin *))\r
+{\r
+ InterruptSource *pSource;\r
+\r
+ trace_LOG(trace_DEBUG, "-D- PIO_ConfigureIt()\n\r");\r
+\r
+ SANITY_CHECK(pPin);\r
+ ASSERT(numSources < MAX_INTERRUPT_SOURCES,\r
+ "-F- PIO_ConfigureIt: Increase MAX_INTERRUPT_SOURCES\n\r");\r
+\r
+ // Define new source\r
+ trace_LOG(trace_DEBUG, "-D- PIO_ConfigureIt: Defining new source #%d.\n\r", numSources);\r
+\r
+ pSource = &(pSources[numSources]);\r
+ pSource->pPin = pPin;\r
+ pSource->handler = handler;\r
+ numSources++;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the given interrupt source if it has been configured.\r
+/// \param pPin Interrupt source to enable.\r
+//------------------------------------------------------------------------------\r
+void PIO_EnableIt(const Pin *pPin)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- PIO_EnableIt()\n\r");\r
+\r
+ SANITY_CHECK(pPin);\r
+\r
+#ifndef NOASSERT\r
+ unsigned int i = 0;\r
+ unsigned char found = 0;\r
+ while ((i < numSources) && !found) {\r
+\r
+ if (pSources[i].pPin == pPin) {\r
+\r
+ found = 1;\r
+ }\r
+ i++;\r
+ }\r
+ ASSERT(found, "-F- PIO_EnableIt: Interrupt source has not been configured\n\r");\r
+#endif\r
+\r
+ pPin->pio->PIO_ISR;\r
+ pPin->pio->PIO_IER = pPin->mask;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables a given interrupt source.\r
+/// \param pPin Interrupt source to disable.\r
+//------------------------------------------------------------------------------\r
+void PIO_DisableIt(const Pin *pPin)\r
+{\r
+ SANITY_CHECK(pPin);\r
+\r
+ trace_LOG(trace_DEBUG, "-D- PIO_DisableIt()\n\r");\r
+\r
+ pPin->pio->PIO_IDR = pPin->mask;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+/// !Purpose\r
+/// \r
+/// Configuration and handling of interrupts on PIO status changes.\r
+/// \r
+/// !Usage\r
+/// \r
+/// -# Configure an status change interrupt on one or more pin(s) with\r
+/// PIO_ConfigureIt.\r
+/// -# Enable & disable interrupts on pins using PIO_EnableIt and\r
+/// PIO_DisableIt.\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "pio.h"\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void PIO_InitializeInterrupts(unsigned int priority);\r
+\r
+extern void PIO_ConfigureIt(const Pin *pPin, void (*handler)(const Pin *));\r
+\r
+extern void PIO_EnableIt(const Pin *pPin);\r
+\r
+extern void PIO_DisableIt(const Pin *pPin);\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "pit.h"\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// Initialize the System timer for a period in µsecond with a system clock\r
+/// freq in MHz\r
+/// \param period Period in µsecond.\r
+/// \param pit_frequency System clock frequency in MHz.\r
+//------------------------------------------------------------------------------\r
+void PIT_Init(unsigned int period,\r
+ unsigned int pit_frequency)\r
+{\r
+ AT91C_BASE_PITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10\r
+ AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Set the PIT Periodic Interval Value\r
+//------------------------------------------------------------------------------\r
+void PIT_SetPIV(unsigned int piv)\r
+{\r
+ AT91C_BASE_PITC->PITC_PIMR = piv | (AT91C_BASE_PITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enable the PIT\r
+//------------------------------------------------------------------------------\r
+void PIT_Enable(void)\r
+{\r
+ AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN;\r
+}\r
+\r
+//----------------------------------------------------------------------------\r
+/// Enable PIT periodic interrupt\r
+//----------------------------------------------------------------------------\r
+void PIT_EnableIT(void)\r
+{\r
+ AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITIEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disable PIT periodic interrupt\r
+//------------------------------------------------------------------------------\r
+void PIT_DisableIT(void)\r
+{\r
+ AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Read PIT mode register\r
+//------------------------------------------------------------------------------\r
+unsigned int PIT_GetMode(void)\r
+{\r
+ return(AT91C_BASE_PITC->PITC_PIMR);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Read PIT status register\r
+//------------------------------------------------------------------------------\r
+unsigned int PIT_GetStatus(void)\r
+{\r
+ return(AT91C_BASE_PITC->PITC_PISR);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Read PIT CPIV and PICNT without ressetting the counters\r
+//------------------------------------------------------------------------------\r
+unsigned int PIT_GetPIIR(void)\r
+{\r
+ return(AT91C_BASE_PITC->PITC_PIIR);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Read System timer CPIV and PICNT without ressetting the counters\r
+//------------------------------------------------------------------------------\r
+unsigned int PIT_GetPIVR(void)\r
+{\r
+ return(AT91C_BASE_PITC->PITC_PIVR);\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+/// !Purpose\r
+///\r
+/// Configuration and handling of PIT.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Initialize System timer for a period in µsecond with\r
+/// PIT_Init\r
+/// -# Set the PIT Periodic Interval Value with PIT_SetPIV\r
+/// -# Enable the PIT with PIT_Enable\r
+/// -# Enable & disable PIT interrupts using PIT_EnableInt and\r
+/// PIT_DisableInt\r
+/// -# Read PIT mode register\r
+/// PIT_GetMode\r
+/// -# Read PIT status register\r
+/// PIT_GetStatus\r
+/// -# Read PIT CPIV and PICNT without ressetting the counters\r
+/// PIT_GetPIIR\r
+/// -# Read System timer CPIV and PICNT without ressetting the counters\r
+/// PIT_GetPIVR\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef PIT_H\r
+#define PIT_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+extern void PIT_Init(unsigned int period, unsigned int pit_frequency);\r
+extern void PIT_SetPIV(unsigned int piv);\r
+extern void PIT_Enable(void);\r
+extern void PIT_EnableIT(void);\r
+extern void PIT_DisableIT(void);\r
+extern unsigned int PIT_GetMode(void);\r
+extern unsigned int PIT_GetStatus(void);\r
+extern unsigned int PIT_GetPIIR(void);\r
+extern unsigned int PIT_GetPIVR(void);\r
+\r
+#endif //#ifndef PIT_H\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "pmc.h"\r
+#include <board.h>\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(at91sam7l64) || defined(at91sam7l128)\r
+//------------------------------------------------------------------------------\r
+/// Sets the fast wake-up inputs that can get the device out of Wait mode.\r
+/// \param inputs Fast wake-up inputs to enable.\r
+//------------------------------------------------------------------------------\r
+void PMC_SetFastWakeUpInputs(unsigned int inputs)\r
+{\r
+ SANITY_CHECK((inputs & ~0xFF) == 0);\r
+ AT91C_BASE_PMC->PMC_FSMR = inputs;\r
+}\r
+\r
+#if !defined(__ICCARM__)\r
+__attribute__ ((section (".ramfunc"))) // GCC\r
+#endif\r
+//------------------------------------------------------------------------------\r
+/// Disables the main oscillator, making the device enter Wait mode.\r
+//------------------------------------------------------------------------------\r
+void PMC_DisableMainOscillatorForWaitMode(void)\r
+{\r
+ AT91C_BASE_PMC->PMC_MOR = 0x37 << 16;\r
+ while ((AT91C_BASE_PMC->PMC_MOR & AT91C_PMC_MAINSELS) != AT91C_PMC_MAINSELS);\r
+}\r
+\r
+#endif\r
+\r
+#if defined(at91sam7l)\r
+//------------------------------------------------------------------------------\r
+/// Disables the main oscillator when NOT running on it.\r
+//------------------------------------------------------------------------------\r
+void PMC_DisableMainOscillator(void)\r
+{\r
+ AT91C_BASE_PMC->PMC_MOR = 0x37 << 16;\r
+ while ((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MAINSELS) == AT91C_PMC_MAINSELS);\r
+}\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the processor clock, making the device enter Idle mode.\r
+//------------------------------------------------------------------------------\r
+void PMC_DisableProcessorClock(void)\r
+{\r
+ AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_PCK;\r
+ while ((AT91C_BASE_PMC->PMC_SCSR & AT91C_PMC_PCK) != AT91C_PMC_PCK);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the clock of a peripheral. The peripheral ID (AT91C_ID_xxx) is used\r
+/// to identify which peripheral is targetted.\r
+/// Note that the ID must NOT be shifted (i.e. 1 << AT91C_ID_xxx).\r
+/// \param id Peripheral ID (AT91C_ID_xxx).\r
+//------------------------------------------------------------------------------\r
+void PMC_EnablePeripheral(unsigned int id)\r
+{\r
+ SANITY_CHECK(id < 32);\r
+\r
+ if ((AT91C_BASE_PMC->PMC_PCSR & (1 << id)) == (1 << id)) {\r
+\r
+ trace_LOG(trace_INFO,\r
+ "-I- PMC_EnablePeripheral: clock of peripheral"\r
+ " %u is already enabled\n\r",\r
+ id);\r
+ }\r
+ else {\r
+\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << id;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the clock of a peripheral. The peripheral ID (AT91C_ID_xxx) is used\r
+/// to identify which peripheral is targetted.\r
+/// Note that the ID must NOT be shifted (i.e. 1 << AT91C_ID_xxx).\r
+/// \param id Peripheral ID (AT91C_ID_xxx).\r
+//------------------------------------------------------------------------------\r
+void PMC_DisablePeripheral(unsigned int id)\r
+{\r
+ SANITY_CHECK(id < 32);\r
+\r
+ if ((AT91C_BASE_PMC->PMC_PCSR & (1 << id)) != (1 << id)) {\r
+\r
+ trace_LOG(trace_INFO,\r
+ "-I- PMC_DisablePeripheral: clock of peripheral"\r
+ " %u is not enabled\n\r",\r
+ id);\r
+ }\r
+ else {\r
+\r
+ AT91C_BASE_PMC->PMC_PCDR = 1 << id;\r
+ }\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef PMC_H\r
+#define PMC_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(at91sam7l64) || defined(at91sam7l128)\r
+extern void PMC_SetFastWakeUpInputs(unsigned int inputs);\r
+extern void PMC_DisableMainOscillator(void);\r
+extern\r
+#ifdef __ICCARM__\r
+__ramfunc\r
+#endif\r
+void PMC_DisableMainOscillatorForWaitMode(void);\r
+#endif\r
+\r
+extern void PMC_DisableProcessorClock(void);\r
+\r
+extern void PMC_EnablePeripheral(unsigned int id);\r
+\r
+extern void PMC_DisablePeripheral(unsigned int id);\r
+#endif //#ifndef PMC_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "pwmc.h"\r
+#include <board.h>\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Local functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Finds a prescaler/divisor couple to generate the desired frequency from\r
+/// MCK.\r
+/// Returns the value to enter in PWMC_MR or 0 if the configuration cannot be\r
+/// met.\r
+/// \param frequency Desired frequency in Hz.\r
+/// \param mck Master clock frequency in Hz.\r
+//------------------------------------------------------------------------------\r
+static unsigned short FindClockConfiguration(\r
+ unsigned int frequency,\r
+ unsigned int mck)\r
+{\r
+ unsigned int divisors[11] = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024};\r
+ unsigned char divisor = 0;\r
+ unsigned int prescaler;\r
+\r
+ SANITY_CHECK(frequency < mck);\r
+\r
+ // Find prescaler and divisor values\r
+ prescaler = (mck / divisors[divisor]) / frequency;\r
+ while ((prescaler > 255) && (divisor < 11)) {\r
+\r
+ divisor++;\r
+ prescaler = (mck / divisors[divisor]) / frequency;\r
+ }\r
+\r
+ // Return result\r
+ if (divisor < 11) {\r
+\r
+ trace_LOG(trace_DEBUG, "-D- Found divisor=%u and prescaler=%u for freq=%uHz\n\r",\r
+ divisors[divisor], prescaler, frequency);\r
+ return prescaler | (divisor << 8);\r
+ }\r
+ else {\r
+\r
+ return 0;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures PWM a channel with the given parameters.\r
+/// The PWM controller must have been clocked in the PMC prior to calling this\r
+/// function.\r
+/// \param channel Channel number.\r
+/// \param prescaler Channel prescaler.\r
+/// \param alignment Channel alignment.\r
+/// \param polarity Channel polarity.\r
+//------------------------------------------------------------------------------\r
+void PWMC_ConfigureChannel(\r
+ unsigned char channel,\r
+ unsigned int prescaler,\r
+ unsigned int alignment,\r
+ unsigned int polarity)\r
+{\r
+ SANITY_CHECK(prescaler < AT91C_PWMC_CPRE_MCKB);\r
+ SANITY_CHECK((alignment & ~AT91C_PWMC_CALG) == 0);\r
+ SANITY_CHECK((polarity & ~AT91C_PWMC_CPOL) == 0);\r
+\r
+ // Disable channel\r
+ AT91C_BASE_PWMC->PWMC_DIS = 1 << channel;\r
+\r
+ // Configure channel\r
+ AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR = prescaler | alignment | polarity;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures PWM clocks A & B to run at the given frequencies. This function\r
+/// finds the best MCK divisor and prescaler values automatically.\r
+/// \param clka Desired clock A frequency (0 if not used).\r
+/// \param clkb Desired clock B frequency (0 if not used).\r
+/// \param mck Master clock frequency.\r
+//------------------------------------------------------------------------------\r
+void PWMC_ConfigureClocks(unsigned int clka, unsigned int clkb, unsigned int mck)\r
+{\r
+ unsigned int mode = 0;\r
+ unsigned int result;\r
+\r
+ // Clock A\r
+ if (clka != 0) {\r
+\r
+ result = FindClockConfiguration(clka, mck);\r
+ ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", clka);\r
+ mode |= result;\r
+ }\r
+\r
+ // Clock B\r
+ if (clkb != 0) {\r
+\r
+ result = FindClockConfiguration(clkb, mck);\r
+ ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", clkb);\r
+ mode |= (result << 16);\r
+ }\r
+\r
+ // Configure clocks\r
+ trace_LOG(trace_DEBUG, "-D- Setting PWMC_MR = 0x%08X\n\r", mode);\r
+ AT91C_BASE_PWMC->PWMC_MR = mode;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the period value used by a PWM channel. This function writes directly\r
+/// to the CPRD register if the channel is disabled; otherwise, it uses the\r
+/// update register CUPD.\r
+/// \param channel Channel number.\r
+/// \param period Period value.\r
+//------------------------------------------------------------------------------\r
+void PWMC_SetPeriod(unsigned char channel, unsigned short period)\r
+{\r
+ // If channel is disabled, write to CPRD\r
+ if ((AT91C_BASE_PWMC->PWMC_SR & (1 << channel)) == 0) {\r
+\r
+ AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CPRDR = period;\r
+ }\r
+ // Otherwise use update register\r
+ else {\r
+\r
+ AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR |= AT91C_PWMC_CPD;\r
+ AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CUPDR = period;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the duty cycle used by a PWM channel. This function writes directly to\r
+/// the CDTY register if the channel is disabled; otherwise it uses the\r
+/// update register CUPD.\r
+/// Note that the duty cycle must always be inferior or equal to the channel\r
+/// period.\r
+/// \param channel Channel number.\r
+/// \param duty Duty cycle value.\r
+//------------------------------------------------------------------------------\r
+void PWMC_SetDutyCycle(unsigned char channel, unsigned short duty)\r
+{\r
+ SANITY_CHECK(duty <= AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CPRDR);\r
+\r
+ // SAM7S errata\r
+#if defined(at91sam7s16) || defined(at91sam7s161) || defined(at91sam7s32) \\r
+ || defined(at91sam7s321) || defined(at91sam7s64) || defined(at91sam7s128) \\r
+ || defined(at91sam7s256) || defined(at91sam7s512)\r
+ ASSERT(duty > 0, "-F- Duty cycle value 0 is not permitted on SAM7S chips.\n\r");\r
+ ASSERT((duty > 1) || (AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR & AT91C_PWMC_CALG),\r
+ "-F- Duty cycle value 1 is not permitted in left-aligned mode on SAM7S chips.\n\r");\r
+#endif\r
+\r
+ // If channel is disabled, write to CDTY\r
+ if ((AT91C_BASE_PWMC->PWMC_SR & (1 << channel)) == 0) {\r
+\r
+ AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CDTYR = duty;\r
+ }\r
+ // Otherwise use update register\r
+ else {\r
+\r
+ AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR &= ~AT91C_PWMC_CPD;\r
+ AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CUPDR = duty;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the given PWM channel. This does NOT enable the corresponding pin;\r
+/// this must be done in the user code.\r
+/// \param channel Channel number.\r
+//------------------------------------------------------------------------------\r
+void PWMC_EnableChannel(unsigned char channel)\r
+{\r
+ AT91C_BASE_PWMC->PWMC_ENA = 1 << channel;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the given PWM channel.\r
+/// \param channel Channel number.\r
+//------------------------------------------------------------------------------\r
+void PWMC_DisableChannel(unsigned char channel)\r
+{\r
+ AT91C_BASE_PWMC->PWMC_DIS = 1 << channel;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the period interrupt for the given PWM channel.\r
+/// \param channel Channel number.\r
+//------------------------------------------------------------------------------\r
+void PWMC_EnableChannelIt(unsigned char channel)\r
+{\r
+ AT91C_BASE_PWMC->PWMC_IER = 1 << channel;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the period interrupt for the given PWM channel.\r
+/// \param channel Channel number.\r
+//------------------------------------------------------------------------------\r
+void PWMC_DisableChannelIt(unsigned char channel)\r
+{\r
+ AT91C_BASE_PWMC->PWMC_IDR = 1 << channel;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef PWMC_H\r
+#define PWMC_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void PWMC_ConfigureChannel(\r
+ unsigned char channel,\r
+ unsigned int prescaler,\r
+ unsigned int alignment,\r
+ unsigned int polarity);\r
+\r
+extern void PWMC_ConfigureClocks\r
+ (unsigned int clka,\r
+ unsigned int clkb,\r
+ unsigned int mck);\r
+\r
+extern void PWMC_SetPeriod(unsigned char channel, unsigned short period);\r
+\r
+extern void PWMC_SetDutyCycle(unsigned char channel, unsigned short duty);\r
+\r
+extern void PWMC_EnableChannel(unsigned char channel);\r
+\r
+extern void PWMC_DisableChannel(unsigned char channel);\r
+\r
+extern void PWMC_EnableChannelIt(unsigned char channel);\r
+\r
+extern void PWMC_DisableChannelIt(unsigned char channel);\r
+\r
+#endif //#ifndef PWMC_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//-----------------------------------------------------------------------------\r
+// Headers\r
+//-----------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//-----------------------------------------------------------------------------\r
+// Macros\r
+//-----------------------------------------------------------------------------\r
+\r
+/// WRITE_RSTC: Write RSTC register\r
+#define WRITE_RSTC(pRstc, regName, value) pRstc->regName = (value)\r
+\r
+/// READ_RSTC: Read RSTC registers\r
+#define READ_RSTC(pRstc, regName) (pRstc->regName)\r
+\r
+//-----------------------------------------------------------------------------\r
+// Defines\r
+//-----------------------------------------------------------------------------\r
+\r
+/// Keywords to write to the reset registers\r
+#define RSTC_KEY_PASSWORD (0xA5UL << 24)\r
+\r
+//-----------------------------------------------------------------------------\r
+// Exported functions\r
+//-----------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Configure the mode of the RSTC peripheral.\r
+/// The configuration is computed by the lib (AT91C_RSTC_*).\r
+/// \param rstc Pointer to an RSTC peripheral.\r
+/// \param rmr Desired mode configuration.\r
+//-----------------------------------------------------------------------------\r
+void RSTC_ConfigureMode(AT91PS_RSTC rstc, unsigned int rmr)\r
+{\r
+ rmr &= ~AT91C_RSTC_KEY;\r
+ WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable/Disable the detection of a low level on the pin NRST as User Reset\r
+/// \param rstc Pointer to an RSTC peripheral.\r
+/// \param enable 1 to enable & 0 to disable.\r
+//-----------------------------------------------------------------------------\r
+void RSTC_SetUserResetEnable(AT91PS_RSTC rstc, unsigned char enable)\r
+{\r
+ unsigned int rmr = READ_RSTC(rstc, RSTC_RMR) & (~AT91C_RSTC_KEY);\r
+ if (enable) {\r
+\r
+ rmr |= AT91C_RSTC_URSTEN;\r
+ }\r
+ else {\r
+\r
+ rmr &= ~AT91C_RSTC_URSTEN;\r
+ }\r
+ WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable/Disable the interrupt of a User Reset (USRTS bit in RSTC_RST).\r
+/// \param rstc Pointer to an RSTC peripheral.\r
+/// \param enable 1 to enable & 0 to disable.\r
+//-----------------------------------------------------------------------------\r
+void RSTC_SetUserResetInterruptEnable(AT91PS_RSTC rstc, unsigned char enable)\r
+{\r
+ unsigned int rmr = READ_RSTC(rstc, RSTC_RMR) & (~AT91C_RSTC_KEY);\r
+ if (enable) {\r
+\r
+ rmr |= AT91C_RSTC_URSTIEN;\r
+ }\r
+ else {\r
+\r
+ rmr &= ~AT91C_RSTC_URSTIEN;\r
+ }\r
+ WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Setup the external reset length. The length is asserted during a time of\r
+/// pow(2, powl+1) Slow Clock(32KHz). The duration is between 60us and 2s.\r
+/// \param rstc Pointer to an RSTC peripheral.\r
+/// \param powl Power length defined.\r
+//-----------------------------------------------------------------------------\r
+void RSTC_SetExtResetLength(AT91PS_RSTC rstc, unsigned char powl)\r
+{\r
+ unsigned int rmr = READ_RSTC(rstc, RSTC_RMR);\r
+ rmr &= ~(AT91C_RSTC_KEY | AT91C_RSTC_ERSTL);\r
+ rmr |= (powl << 8) & AT91C_RSTC_ERSTL;\r
+ WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD);\r
+}\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Resets the processor.\r
+/// \param rstc Pointer to an RSTC peripheral.\r
+//-----------------------------------------------------------------------------\r
+void RSTC_ProcessorReset(AT91PS_RSTC rstc)\r
+{\r
+ WRITE_RSTC(rstc, RSTC_RCR, AT91C_RSTC_PROCRST | RSTC_KEY_PASSWORD);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Resets the peripherals.\r
+/// \param rstc Pointer to an RSTC peripheral.\r
+//-----------------------------------------------------------------------------\r
+void RSTC_PeripheralReset(AT91PS_RSTC rstc)\r
+{\r
+ WRITE_RSTC(rstc, RSTC_RCR, AT91C_RSTC_PERRST | RSTC_KEY_PASSWORD);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Asserts the NRST pin for external resets.\r
+/// \param rstc Pointer to an RSTC peripheral.\r
+//-----------------------------------------------------------------------------\r
+void RSTC_ExtReset(AT91PS_RSTC rstc)\r
+{\r
+ WRITE_RSTC(rstc, RSTC_RCR, AT91C_RSTC_EXTRST | RSTC_KEY_PASSWORD);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Return NRST pin level ( 1 or 0 ).\r
+/// \param rstc Pointer to an RSTC peripheral.\r
+//-----------------------------------------------------------------------------\r
+unsigned char RSTC_GetNrstLevel(AT91PS_RSTC rstc)\r
+{\r
+ if (READ_RSTC(rstc, RSTC_RSR) & AT91C_RSTC_NRSTL) {\r
+\r
+ return 1;\r
+ }\r
+ return 0;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Returns 1 if at least one high-to-low transition of NRST (User Reset) has\r
+/// been detected since the last read of RSTC_RSR.\r
+/// \param rstc Pointer to an RSTC peripheral.\r
+//-----------------------------------------------------------------------------\r
+unsigned char RSTC_IsUserReseetDetected(AT91PS_RSTC rstc)\r
+{\r
+ if (READ_RSTC(rstc, RSTC_RSR) & AT91C_RSTC_URSTS) {\r
+\r
+ return 1;\r
+ }\r
+ return 0;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Return 1 if a software reset command is being performed by the reset\r
+/// controller. The reset controller is busy.\r
+/// \param rstc Pointer to an RSTC peripheral.\r
+//-----------------------------------------------------------------------------\r
+unsigned char RSTC_IsBusy(AT91PS_RSTC rstc)\r
+{\r
+ if (READ_RSTC(rstc, RSTC_RSR) & AT91C_RSTC_SRCMP) {\r
+\r
+ return 1;\r
+ }\r
+ return 0;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _RSTC_H\r
+#define _RSTC_H\r
+\r
+//-----------------------------------------------------------------------------\r
+// Exported functions\r
+//-----------------------------------------------------------------------------\r
+\r
+extern void RSTC_ConfigureMode(AT91PS_RSTC rstc, unsigned int rmr);\r
+\r
+extern void RSTC_SetUserResetEnable(AT91PS_RSTC rstc, unsigned char enable);\r
+\r
+extern void RSTC_SetUserResetInterruptEnable(AT91PS_RSTC rstc,\r
+ unsigned char enable);\r
+\r
+extern void RSTC_SetExtResetLength(AT91PS_RSTC rstc, unsigned char powl);\r
+\r
+extern void RSTC_ProcessorReset(AT91PS_RSTC rstc);\r
+\r
+extern void RSTC_PeripheralReset(AT91PS_RSTC rstc);\r
+\r
+extern void RSTC_ExtReset(AT91PS_RSTC rstc);\r
+\r
+extern unsigned char RSTC_GetNrstLevel(AT91PS_RSTC rstc);\r
+\r
+extern unsigned char RSTC_IsUserReseetDetected(AT91PS_RSTC rstc);\r
+\r
+extern unsigned char RSTC_IsBusy(AT91PS_RSTC rstc);\r
+\r
+#endif // #ifndef _RSTC_H\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef trace_LEVEL\r
+ #define trace_LEVEL trace_INFO\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "rtc.h"\r
+#include <board.h>\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the RTC in either 12- or 24-hour mode.\r
+/// \param mode Hour mode.\r
+//------------------------------------------------------------------------------\r
+void RTC_SetHourMode(unsigned int mode)\r
+{\r
+ SANITY_CHECK((mode & 0xFFFFFFFE) == 0);\r
+\r
+ trace_LOG(trace_DEBUG, "-D- RTC_SetHourMode()\n\r");\r
+\r
+ AT91C_BASE_RTC->RTC_MR = mode;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the selected interrupt sources of the RTC.\r
+/// \param sources Interrupt sources to enable.\r
+//------------------------------------------------------------------------------\r
+void RTC_EnableIt(unsigned int sources)\r
+{\r
+ SANITY_CHECK((sources & ~0x1F) == 0);\r
+\r
+ trace_LOG(trace_DEBUG, "-D- RTC_EnableIt()\n\r");\r
+\r
+ AT91C_BASE_RTC->RTC_IER = sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the selected interrupt sources of the RTC.\r
+/// \param sources Interrupt sources to disable.\r
+//------------------------------------------------------------------------------\r
+void RTC_DisableIt(unsigned int sources)\r
+{\r
+ SANITY_CHECK((sources & ~0x1F) == 0);\r
+\r
+ trace_LOG(trace_DEBUG, "-D- RTC_DisableIt()\n\r");\r
+\r
+ AT91C_BASE_RTC->RTC_IDR = sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the current time in the RTC.\r
+/// \param hour Current hour.\r
+/// \param minute Current minute.\r
+/// \param second Current second.\r
+//------------------------------------------------------------------------------\r
+void RTC_SetTime(unsigned char hour, unsigned char minute, unsigned char second)\r
+{\r
+ unsigned int time;\r
+\r
+ SANITY_CHECK(hour < 24);\r
+ SANITY_CHECK(minute < 60);\r
+ SANITY_CHECK(second < 60);\r
+\r
+ trace_LOG(trace_DEBUG, "-D- RTC_SetTime(%02d:%02d:%02d)\n\r", hour, minute, second);\r
+\r
+ time = (second % 10) | ((second / 10) << 4)\r
+ | ((minute % 10) << 8) | ((minute / 10) << 12);\r
+\r
+ // 12-hour mode\r
+ if ((AT91C_BASE_RTC->RTC_MR & AT91C_RTC_HRMOD) == AT91C_RTC_HRMOD) {\r
+\r
+ if (hour > 12) {\r
+\r
+ hour -= 12;\r
+ time |= AT91C_RTC_AMPM;\r
+ }\r
+ }\r
+\r
+ time |= ((hour % 10) << 16) | ((hour / 10) << 20);\r
+\r
+ // Set time\r
+ AT91C_BASE_RTC->RTC_CR |= AT91C_RTC_UPDTIM;\r
+ while ((AT91C_BASE_RTC->RTC_SR & AT91C_RTC_ACKUPD) != AT91C_RTC_ACKUPD);\r
+ AT91C_BASE_RTC->RTC_SCCR = AT91C_RTC_ACKUPD;\r
+ AT91C_BASE_RTC->RTC_TIMR = time;\r
+ AT91C_BASE_RTC->RTC_CR &= ~AT91C_RTC_UPDTIM;\r
+ SANITY_CHECK((AT91C_BASE_RTC->RTC_CR & AT91C_RTC_UPDTIM) != AT91C_RTC_UPDTIM);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Retrieves the current time as stored in the RTC in several variables.\r
+/// \param pHour If not null, current hour is stored in this variable.\r
+/// \param pMinute If not null, current minute is stored in this variable.\r
+/// \param pSecond If not null, current second is stored in this variable.\r
+//------------------------------------------------------------------------------\r
+void RTC_GetTime(\r
+ unsigned char *pHour,\r
+ unsigned char *pMinute,\r
+ unsigned char *pSecond)\r
+{\r
+ unsigned int time;\r
+\r
+ SANITY_CHECK(pHour || pMinute || pSecond);\r
+\r
+ trace_LOG(trace_DEBUG, "-D- RTC_GetTime()\n\r");\r
+\r
+ // Get current RTC time\r
+ time = AT91C_BASE_RTC->RTC_TIMR;\r
+ while (time != AT91C_BASE_RTC->RTC_TIMR) {\r
+\r
+ time = AT91C_BASE_RTC->RTC_TIMR;\r
+ }\r
+\r
+ // Hour\r
+ if (pHour) {\r
+\r
+ *pHour = ((time & 0x00300000) >> 20) * 10\r
+ + ((time & 0x000F0000) >> 16);\r
+ if ((time & AT91C_RTC_AMPM) == AT91C_RTC_AMPM) {\r
+\r
+ *pHour += 12;\r
+ }\r
+ }\r
+ \r
+ // Minute\r
+ if (pMinute) {\r
+\r
+ *pMinute = ((time & 0x00007000) >> 12) * 10\r
+ + ((time & 0x00000F00) >> 8);\r
+ }\r
+\r
+ // Second\r
+ if (pSecond) {\r
+\r
+ *pSecond = ((time & 0x00000070) >> 4) * 10\r
+ + (time & 0x0000000F);\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets a time alarm on the RTC. The match is performed only on the provided\r
+/// variables; setting all pointers to 0 disables the time alarm.\r
+/// Note: in AM/PM mode, the hour value must have bit #7 set for PM, cleared for\r
+/// AM (as expected in the time registers).\r
+/// \param pHour If not null, the time alarm will hour-match this value.\r
+/// \param pMinute If not null, the time alarm will minute-match this value.\r
+/// \param pSecond If not null, the time alarm will second-match this value.\r
+//------------------------------------------------------------------------------\r
+void RTC_SetTimeAlarm(\r
+ unsigned char *pHour,\r
+ unsigned char *pMinute,\r
+ unsigned char *pSecond)\r
+{\r
+ unsigned int alarm = 0;\r
+\r
+ SANITY_CHECK(!pHour || ((*pHour & 0x80) == 0));\r
+ SANITY_CHECK(!pMinute || (*pMinute < 60));\r
+ SANITY_CHECK(!pSecond || (*pSecond < 60));\r
+\r
+ trace_LOG(trace_DEBUG, "-D- RTC_SetTimeAlarm()\n\r");\r
+\r
+ // Hour\r
+ if (pHour) {\r
+\r
+ alarm |= AT91C_RTC_HOUREN | ((*pHour / 10) << 20) | ((*pHour % 10) << 16);\r
+ }\r
+\r
+ // Minute\r
+ if (pMinute) {\r
+\r
+ alarm |= AT91C_RTC_MINEN | ((*pMinute / 10) << 12) | ((*pMinute % 10) << 8);\r
+ }\r
+\r
+ // Second\r
+ if (pSecond) {\r
+\r
+ alarm |= AT91C_RTC_SECEN | ((*pSecond / 10) << 4) | (*pSecond % 10);\r
+ }\r
+\r
+ AT91C_BASE_RTC->RTC_TIMALR = alarm;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Retrieves the current year, month and day from the RTC. Month, day and week\r
+/// values are numbered starting at 1.\r
+/// \param pYear Current year (optional).\r
+/// \param pMonth Current month (optional).\r
+/// \param pDay Current day (optional).\r
+/// \param pWeek Current day in current week (optional).\r
+//------------------------------------------------------------------------------\r
+void RTC_GetDate(\r
+ unsigned short *pYear,\r
+ unsigned char *pMonth,\r
+ unsigned char *pDay,\r
+ unsigned char *pWeek)\r
+{\r
+ unsigned int date;\r
+\r
+ // Get current date (multiple reads are necessary to insure a stable value)\r
+ do {\r
+\r
+ date = AT91C_BASE_RTC->RTC_CALR;\r
+ }\r
+ while (date != AT91C_BASE_RTC->RTC_CALR);\r
+\r
+ // Retrieve year\r
+ if (pYear) {\r
+\r
+ *pYear = (((date >> 4) & 0x7) * 1000)\r
+ + ((date & 0xF) * 100)\r
+ + (((date >> 12) & 0xF) * 10)\r
+ + ((date >> 8) & 0xF);\r
+ }\r
+\r
+ // Retrieve month\r
+ if (pMonth) {\r
+\r
+ *pMonth = (((date >> 20) & 1) * 10) + ((date >> 16) & 0xF);\r
+ }\r
+\r
+ // Retrieve day\r
+ if (pDay) {\r
+\r
+ *pDay = (((date >> 28) & 0x3) * 10) + ((date >> 24) & 0xF);\r
+ }\r
+\r
+ // Retrieve week\r
+ if (pWeek) {\r
+\r
+ *pWeek = ((date >> 21) & 0x7);\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the current year, month and day in the RTC. Month, day and week values\r
+/// must be numbered starting from 1.\r
+/// \param year Current year.\r
+/// \param month Current month.\r
+/// \param day Current day.\r
+/// \param week Day number in current week.\r
+//------------------------------------------------------------------------------\r
+void RTC_SetDate(\r
+ unsigned short year,\r
+ unsigned char month,\r
+ unsigned char day,\r
+ unsigned char week)\r
+{\r
+ unsigned int date;\r
+\r
+ SANITY_CHECK((year >= 1900) && (year <= 2099));\r
+ SANITY_CHECK((month >= 1) && (month <= 12));\r
+ SANITY_CHECK((day >= 1) && (day <= 31));\r
+ SANITY_CHECK((week >= 1) && (week <= 7));\r
+\r
+ // Convert values to date register value\r
+ date = ((year / 100) % 10)\r
+ | ((year / 1000) << 4)\r
+ | ((year % 10) << 8)\r
+ | (((year / 10) % 10) << 12)\r
+ | ((month % 10) << 16)\r
+ | ((month / 10) << 20)\r
+ | (week << 21)\r
+ | ((day % 10) << 24)\r
+ | ((day / 10) << 28);\r
+\r
+ // Update calendar register\r
+ AT91C_BASE_RTC->RTC_CR |= AT91C_RTC_UPDCAL;\r
+ while ((AT91C_BASE_RTC->RTC_SR & AT91C_RTC_ACKUPD) != AT91C_RTC_ACKUPD);\r
+ AT91C_BASE_RTC->RTC_SCCR = AT91C_RTC_ACKUPD;\r
+ AT91C_BASE_RTC->RTC_CALR = date;\r
+ AT91C_BASE_RTC->RTC_CR &= ~AT91C_RTC_UPDCAL;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets a date alarm in the RTC. The alarm will match only the provided values;\r
+/// passing a null-pointer disables the corresponding field match.\r
+/// \param pMonth If not null, the RTC alarm will month-match this value.\r
+/// \param pDay If not null, the RTC alarm will day-match this value.\r
+//------------------------------------------------------------------------------\r
+void RTC_SetDateAlarm(unsigned char *pMonth, unsigned char *pDay)\r
+{\r
+ unsigned int alarm = 0;\r
+\r
+ SANITY_CHECK(!pMonth || ((*pMonth >= 1) && (*pMonth <= 12)));\r
+ SANITY_CHECK(!pDay || ((*pDay >= 1) && (*pDay <= 31)));\r
+\r
+ trace_LOG(trace_DEBUG, "-D- RTC_SetDateAlarm()\n\r");\r
+\r
+ // Compute alarm field value\r
+ if (pMonth) {\r
+\r
+ alarm |= AT91C_RTC_MONTHEN | ((*pMonth / 10) << 20) | ((*pMonth % 10) << 16);\r
+ }\r
+ if (pDay) {\r
+\r
+ alarm |= AT91C_RTC_DATEEN | ((*pDay / 10) << 28) | ((*pDay % 10) << 24);\r
+ }\r
+\r
+ // Set alarm\r
+ AT91C_BASE_RTC->RTC_CALALR = alarm;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef RTC_H\r
+#define RTC_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void RTC_SetHourMode(unsigned int mode);\r
+\r
+extern void RTC_EnableIt(unsigned int sources);\r
+\r
+extern void RTC_DisableIt(unsigned int sources);\r
+\r
+extern void RTC_SetTime(\r
+ unsigned char hour,\r
+ unsigned char minute,\r
+ unsigned char second);\r
+\r
+extern void RTC_GetTime(\r
+ unsigned char *pHour,\r
+ unsigned char *pMinute,\r
+ unsigned char *pSecond);\r
+\r
+extern void RTC_SetTimeAlarm(\r
+ unsigned char *pHour,\r
+ unsigned char *pMinute,\r
+ unsigned char *pSecond);\r
+\r
+void RTC_GetDate(\r
+ unsigned short *pYear,\r
+ unsigned char *pMonth,\r
+ unsigned char *pDay,\r
+ unsigned char *pWeek);\r
+\r
+extern void RTC_SetDate(\r
+ unsigned short year,\r
+ unsigned char month,\r
+ unsigned char day,\r
+ unsigned char week);\r
+\r
+extern void RTC_SetDateAlarm(unsigned char *pMonth, unsigned char *pDay);\r
+\r
+#endif //#ifndef RTC_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "rtt.h"\r
+#include <utility/assert.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Changes the prescaler value of the given RTT and restarts it. This function\r
+/// disables RTT interrupt sources.\r
+/// \param rtt Pointer to a AT91S_RTTC instance.\r
+/// \param prescaler Prescaler value for the RTT.\r
+//------------------------------------------------------------------------------\r
+void RTT_SetPrescaler(AT91S_RTTC *rtt, unsigned short prescaler)\r
+{\r
+ rtt->RTTC_RTMR = (prescaler | AT91C_RTTC_RTTRST);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the current value of the RTT timer value.\r
+/// \param rtt Pointer to a AT91S_RTTC instance.\r
+//------------------------------------------------------------------------------\r
+unsigned int RTT_GetTime(AT91S_RTTC *rtt)\r
+{\r
+ return rtt->RTTC_RTVR;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the specified RTT interrupt sources.\r
+/// \param rtt Pointer to a AT91S_RTTC instance.\r
+/// \param sources Bitmask of interrupts to enable.\r
+//------------------------------------------------------------------------------\r
+void RTT_EnableIT(AT91S_RTTC *rtt, unsigned int sources)\r
+{\r
+ ASSERT((sources & 0x0004FFFF) == 0,\r
+ "RTT_EnableIT: Wrong sources value.\n\r");\r
+ rtt->RTTC_RTMR |= sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the status register value of the given RTT.\r
+/// \param rtt Pointer to an AT91S_RTTC instance.\r
+//------------------------------------------------------------------------------\r
+unsigned int RTT_GetStatus(AT91S_RTTC *rtt)\r
+{\r
+ return rtt->RTTC_RTSR;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the RTT to generate an alarm at the given time.\r
+/// \param pRtt Pointer to an AT91S_RTTC instance.\r
+/// \param time Alarm time.\r
+//------------------------------------------------------------------------------\r
+void RTT_SetAlarm(AT91S_RTTC *pRtt, unsigned int time)\r
+{\r
+ SANITY_CHECK(time > 0);\r
+\r
+ pRtt->RTTC_RTAR = time - 1;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef RTT_H\r
+#define RTT_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef AT91C_BASE_RTTC\r
+ #define AT91C_BASE_RTTC AT91C_BASE_RTTC0\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void RTT_SetPrescaler(AT91S_RTTC *rtt, unsigned short prescaler);\r
+\r
+extern unsigned int RTT_GetTime(AT91S_RTTC *rtt);\r
+\r
+extern void RTT_EnableIT(AT91S_RTTC *rtt, unsigned int sources);\r
+\r
+extern unsigned int RTT_GetStatus(AT91S_RTTC *rtt);\r
+\r
+extern void RTT_SetAlarm(AT91S_RTTC *pRtt, unsigned int time);\r
+\r
+#endif //#ifndef RTT_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "slcdc.h"\r
+#include <board.h>\r
+#include <utility/assert.h>\r
+\r
+#include <string.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Local definitions\r
+//------------------------------------------------------------------------------\r
+\r
+/// Size of SLCDC buffer in bytes.\r
+#define BUFFER_SIZE 320\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initializes the Segment LCD controller.\r
+/// \param commons Number of commons used by the display.\r
+/// \param segments Number of segments used by the display.\r
+/// \param bias Bias value.\r
+/// \param timeSetting Buffer timing value.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_Configure(\r
+ unsigned int commons,\r
+ unsigned int segments,\r
+ unsigned int bias,\r
+ unsigned int timeSetting)\r
+{\r
+ SANITY_CHECK((commons > 0) && (commons <= 10));\r
+ SANITY_CHECK((segments > 0) && (segments <= 40));\r
+ SANITY_CHECK((bias & ~AT91C_SLCDC_BIAS) == 0);\r
+ SANITY_CHECK((timeSetting & ~(0xF << 16)) == 0); \r
+ SANITY_CHECK((timeSetting >> 16) < 0x0A);\r
+\r
+ // Enable peripheral clock\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SLCD;\r
+ AT91C_BASE_SLCDC->SLCDC_MR = (commons - 1) | ((segments - 1) << 8) | bias | timeSetting;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Clears the SLCD display buffer.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_Clear(void)\r
+{\r
+ memset((void *) AT91C_BASE_SLCDC->SLCDC_MEM, 0, BUFFER_SIZE);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the SLCD controller.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_Enable(void)\r
+{\r
+ AT91C_BASE_SLCDC->SLCDC_CR = AT91C_SLCDC_LCDEN;\r
+ while (AT91C_BASE_SLCDC -> SLCDC_SR != AT91C_SLCDC_ENA);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the SLCD controller.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_Disable(void)\r
+{\r
+ AT91C_BASE_SLCDC->SLCDC_CR = AT91C_SLCDC_LCDDIS;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the SLCD low power mode.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_EnableLowPowerMode(void)\r
+{\r
+ unsigned int value;\r
+\r
+ value = AT91C_BASE_SLCDC->SLCDC_MR;\r
+ value &= ~AT91C_SLCDC_LPMODE;\r
+ value |=AT91C_SLCDC_LPMODE;\r
+ AT91C_BASE_SLCDC->SLCDC_MR = value;\r
+}\r
+ \r
+//------------------------------------------------------------------------------\r
+/// Disables the SLCD low power mode\r
+//------------------------------------------------------------------------------\r
+void SLCDC_DisableLowPowerMode(void)\r
+{\r
+ unsigned int value;\r
+\r
+ value = AT91C_BASE_SLCDC->SLCDC_MR;\r
+ value &= ~AT91C_SLCDC_LPMODE;\r
+ AT91C_BASE_SLCDC->SLCDC_MR = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Adjusts the frame frequency. Frequency = FsCLK / (prescaler * divider . NCOM)\r
+/// \param prescalerValue Prescaler value\r
+/// \param dividerValue Divider value\r
+//------------------------------------------------------------------------------\r
+void SLCDC_SetFrameFreq(unsigned int prescalerValue, unsigned int dividerValue)\r
+{\r
+ SANITY_CHECK((prescalerValue & ~AT91C_SLCDC_PRESC) == 0);\r
+ SANITY_CHECK((dividerValue & (~(0x07 << 8))) == 0);\r
+\r
+ AT91C_BASE_SLCDC->SLCDC_FRR = prescalerValue | dividerValue;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the display mode (normal/force off/force on/blinking).\r
+/// \param mode Display mode to be set\r
+//------------------------------------------------------------------------------\r
+void SLCDC_SetDisplayMode(unsigned int mode)\r
+{\r
+ unsigned int value;\r
+\r
+ SANITY_CHECK(mode < 8);\r
+ \r
+ value = AT91C_BASE_SLCDC->SLCDC_DR;\r
+ value &= ~AT91C_SLCDC_DISPMODE;\r
+ value |= mode;\r
+ AT91C_BASE_SLCDC->SLCDC_DR = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Adjusts the display blinking frequency.\r
+/// Blinking frequency = Frame Frequency / LCDBLKFREQ.\r
+/// \param frequency Frequency value.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_SetBlinkFreq(unsigned int frequency)\r
+{\r
+ unsigned int value;\r
+\r
+ SANITY_CHECK((frequency & ~(0xFF << 8)) == 0);\r
+\r
+ value = AT91C_BASE_SLCDC->SLCDC_DR;\r
+ value &= ~AT91C_SLCDC_BLKFREQ;\r
+ value |= frequency; \r
+ AT91C_BASE_SLCDC->SLCDC_DR = frequency;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the selected SLCDC interrupt sources.\r
+/// \param sources Interrupt sources to enable.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_EnableInterrupts(unsigned int sources)\r
+{\r
+ SANITY_CHECK((sources & 0xFFFFFFFA) == 0);\r
+\r
+ AT91C_BASE_SLCDC->SLCDC_IER = sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the selected SLCDC interrupt sources.\r
+/// \param sources Interrupt sources to disable.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_DisableInterrupts(unsigned int sources)\r
+{\r
+ SANITY_CHECK((sources & 0xFFFFFFFA) == 0);\r
+\r
+ AT91C_BASE_SLCDC->SLCDC_IDR = sources;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef SLCDC_H\r
+#define SLCDC_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Global definitions\r
+//------------------------------------------------------------------------------\r
+\r
+/// Number of segments in SLCD.\r
+#define S7LEKLCD_NUM_SEGMENTS 40\r
+/// Number of commons in SLCD.\r
+#define S7LEKLCD_NUM_COMMONS 10\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void SLCDC_Configure(\r
+ unsigned int commons,\r
+ unsigned int segments,\r
+ unsigned int bias,\r
+ unsigned int timeSetting);\r
+\r
+extern void SLCDC_Clear(void);\r
+\r
+extern void SLCDC_Enable(void);\r
+\r
+extern void SLCDC_Disable(void);\r
+\r
+extern void SLCDC_SetFrameFreq(\r
+ unsigned int prescalerValue,\r
+ unsigned int dividerValue);\r
+\r
+extern void SLCDC_SetDisplayMode(unsigned int mode);\r
+\r
+extern void SLCDC_SetBlinkFreq(unsigned int frequency);\r
+\r
+extern void SLCDC_EnableInterrupts(unsigned int sources);\r
+\r
+extern void SLCDC_DisableInterrupts(unsigned int sources);\r
+\r
+#endif //#ifndef SLCDC_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "spi.h"\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// Enables a SPI peripheral\r
+/// \param spi Pointer to an AT91S_SPI instance.\r
+//------------------------------------------------------------------------------\r
+void SPI_Enable(AT91S_SPI *spi)\r
+{\r
+ spi->SPI_CR = AT91C_SPI_SPIEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables a SPI peripheral.\r
+/// \param spi Pointer to an AT91S_SPI instance.\r
+//------------------------------------------------------------------------------\r
+void SPI_Disable(AT91S_SPI *spi)\r
+{\r
+ spi->SPI_CR = AT91C_SPI_SPIDIS;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures a SPI peripheral as specified. The configuration can be computed\r
+/// using several macros (see "SPI configuration macros") and the constants\r
+/// defined in LibV3 (AT91C_SPI_*).\r
+/// \param spi Pointer to an AT91S_SPI instance.\r
+/// \param id Peripheral ID of the SPI.\r
+/// \param configuration Value of the SPI configuration register.\r
+//------------------------------------------------------------------------------\r
+void SPI_Configure(AT91S_SPI *spi,\r
+ unsigned int id,\r
+ unsigned int configuration)\r
+{\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << id;\r
+ spi->SPI_CR = AT91C_SPI_SPIDIS | AT91C_SPI_SWRST;\r
+ spi->SPI_MR = configuration;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures a chip select of a SPI peripheral. The chip select configuration\r
+/// is computed using the definition provided by the LibV3 (AT91C_SPI_*).\r
+/// \param spi Pointer to an AT91S_SPI instance.\r
+/// \param npcs Chip select to configure (1, 2, 3 or 4).\r
+/// \param configuration Desired chip select configuration.\r
+//------------------------------------------------------------------------------\r
+void SPI_ConfigureNPCS(AT91S_SPI *spi,\r
+ unsigned int npcs,\r
+ unsigned int configuration)\r
+{\r
+ spi->SPI_CSR[npcs] = configuration;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sends data through a SPI peripheral. If the SPI is configured to use a fixed\r
+/// peripheral select, the npcs value is meaningless. Otherwise, it identifies\r
+/// the component which shall be addressed.\r
+/// \param spi Pointer to an AT91S_SPI instance.\r
+/// \param npcs Chip select of the component to address (1, 2, 3 or 4).\r
+/// \param data Word of data to send.\r
+//------------------------------------------------------------------------------\r
+void SPI_Write(AT91S_SPI *spi, unsigned int npcs, unsigned short data)\r
+{\r
+ // Discard contents of RDR register\r
+ //volatile unsigned int discard = spi->SPI_RDR;\r
+\r
+ // Send data\r
+ while ((spi->SPI_SR & AT91C_SPI_TXEMPTY) == 0);\r
+ spi->SPI_TDR = data | SPI_PCS(npcs);\r
+ while ((spi->SPI_SR & AT91C_SPI_TDRE) == 0);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sends the contents of buffer through a SPI peripheral, using the PDC to\r
+/// take care of the transfer.\r
+/// \param spi Pointer to an AT91S_SPI instance.\r
+/// \param buffer Data buffer to send.\r
+/// \param length Length of the data buffer.\r
+//------------------------------------------------------------------------------\r
+unsigned char SPI_WriteBuffer(AT91S_SPI *spi,\r
+ void *buffer,\r
+ unsigned int length)\r
+{\r
+ // Check if first bank is free\r
+ if (spi->SPI_TCR == 0) {\r
+\r
+ spi->SPI_TPR = (unsigned int) buffer;\r
+ spi->SPI_TCR = length;\r
+ spi->SPI_PTCR = AT91C_PDC_TXTEN;\r
+ return 1;\r
+ }\r
+ // Check if second bank is free\r
+ else if (spi->SPI_TNCR == 0) {\r
+\r
+ spi->SPI_TNPR = (unsigned int) buffer;\r
+ spi->SPI_TNCR = length;\r
+ return 1;\r
+ }\r
+ \r
+ // No free banks\r
+ return 0;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns 1 if there is no pending write operation on the SPI; otherwise\r
+/// returns 0.\r
+/// \param pSpi Pointer to an AT91S_SPI instance.\r
+//------------------------------------------------------------------------------\r
+unsigned char SPI_IsFinished(AT91S_SPI *pSpi)\r
+{\r
+ return ((pSpi->SPI_SR & AT91C_SPI_TXEMPTY) != 0);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Reads and returns the last word of data received by a SPI peripheral. This\r
+/// method must be called after a successful SPI_Write call.\r
+/// \param spi Pointer to an AT91S_SPI instance.\r
+//------------------------------------------------------------------------------\r
+unsigned short SPI_Read(AT91S_SPI *spi)\r
+{\r
+ while ((spi->SPI_SR & AT91C_SPI_RDRF) == 0);\r
+ return spi->SPI_RDR & 0xFFFF;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Reads data from a SPI peripheral until the provided buffer is filled. This\r
+/// method does NOT need to be called after SPI_Write or SPI_WriteBuffer.\r
+/// \param spi Pointer to an AT91S_SPI instance.\r
+/// \param buffer Data buffer to store incoming bytes.\r
+/// \param length Length in bytes of the data buffer.\r
+//------------------------------------------------------------------------------\r
+unsigned char SPI_ReadBuffer(AT91S_SPI *spi,\r
+ void *buffer,\r
+ unsigned int length)\r
+{\r
+ // Check if the first bank is free\r
+ if (spi->SPI_RCR == 0) {\r
+\r
+ spi->SPI_RPR = (unsigned int) buffer;\r
+ spi->SPI_RCR = length;\r
+ spi->SPI_PTCR = AT91C_PDC_RXTEN;\r
+ return 1;\r
+ }\r
+ // Check if second bank is free\r
+ else if (spi->SPI_RNCR == 0) {\r
+\r
+ spi->SPI_RNPR = (unsigned int) buffer;\r
+ spi->SPI_RNCR = length;\r
+ return 1;\r
+ }\r
+\r
+ // No free bank\r
+ return 0;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \dir\r
+/// !Purpose\r
+/// \r
+/// Definitions for SPI peripheral usage.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Enable the SPI pins required by the application (see pio.h).\r
+/// -# Configure the SPI using the SPI_Configure function. This enables the\r
+/// peripheral clock. The mode register is loaded with the given value.\r
+/// -# Configure all the necessary chip selects with SPI_ConfigureNPCS.\r
+/// -# Enable the SPI by calling SPI_Enable.\r
+/// -# Send/receive data using SPI_Write and SPI_Read. Note that SPI_Read\r
+/// must be called after SPI_Write to retrieve the last value read.\r
+/// -# Send/receive data using the PDC with the SPI_WriteBuffer and\r
+/// SPI_ReadBuffer functions.\r
+/// -# Disable the SPI by calling SPI_Disable.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef SPI_H\r
+#define SPI_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SPI configuration macros"\r
+/// This page lists several macros which should be used when configuring a SPI\r
+/// peripheral.\r
+/// \r
+/// !Macros\r
+/// - SPI_PCS\r
+/// - SPI_SCBR\r
+/// - SPI_DLYBS\r
+/// - SPI_DLYBCT\r
+\r
+/// Calculate the PCS field value given the chip select NPCS value\r
+#define SPI_PCS(npcs) ((~(1 << npcs) & 0xF) << 16)\r
+\r
+/// Calculates the value of the CSR SCBR field given the baudrate and MCK.\r
+#define SPI_SCBR(baudrate, masterClock) \\r
+ ((unsigned int) (masterClock / baudrate) << 8)\r
+\r
+/// Calculates the value of the CSR DLYBS field given the desired delay (in ns)\r
+#define SPI_DLYBS(delay, masterClock) \\r
+ ((unsigned int) (((masterClock / 1000000) * delay) / 1000) << 16)\r
+\r
+/// Calculates the value of the CSR DLYBCT field given the desired delay (in ns)\r
+#define SPI_DLYBCT(delay, masterClock) \\r
+ ((unsigned int) (((masterClock / 1000000) * delay) / 32000) << 16)\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+extern void SPI_Enable(AT91S_SPI *spi);\r
+extern void SPI_Disable(AT91S_SPI *spi);\r
+extern void SPI_Configure(AT91S_SPI *spi,\r
+ unsigned int id,\r
+ unsigned int configuration);\r
+extern void SPI_ConfigureNPCS(AT91S_SPI *spi,\r
+ unsigned int npcs,\r
+ unsigned int configuration);\r
+extern void SPI_Write(AT91S_SPI *spi, unsigned int npcs, unsigned short data);\r
+extern unsigned char SPI_WriteBuffer(AT91S_SPI *spi,\r
+ void *buffer,\r
+ unsigned int length);\r
+\r
+extern unsigned char SPI_IsFinished(AT91S_SPI *pSpi);\r
+\r
+extern unsigned short SPI_Read(AT91S_SPI *spi);\r
+extern unsigned char SPI_ReadBuffer(AT91S_SPI *spi,\r
+ void *buffer,\r
+ unsigned int length);\r
+\r
+#endif //#ifndef SPI_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "ssc.h"\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// Configures a SSC peripheral. If the divided clock is not used, the master\r
+/// clock frequency can be set to 0.\r
+/// \note The emitter and transmitter are disabled by this function.\r
+/// \param ssc Pointer to an AT91S_SSC instance.\r
+/// \param id Peripheral ID of the SSC.\r
+//------------------------------------------------------------------------------\r
+void SSC_Configure(AT91S_SSC *ssc,\r
+ unsigned int id,\r
+ unsigned int bitRate,\r
+ unsigned int masterClock)\r
+{\r
+ // Enable SSC peripheral clock\r
+ AT91C_BASE_PMC->PMC_PCER = 1 << id;\r
+\r
+ // Reset, disable receiver & transmitter\r
+ ssc->SSC_CR = AT91C_SSC_RXDIS | AT91C_SSC_TXDIS | AT91C_SSC_SWRST;\r
+ ssc->SSC_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;\r
+\r
+ // Configure clock frequency\r
+ if (bitRate != 0) {\r
+ \r
+ ssc->SSC_CMR = masterClock / (2 * bitRate);\r
+ }\r
+ else {\r
+\r
+ ssc->SSC_CMR = 0;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the transmitter of a SSC peripheral. Several macros can be used\r
+/// to compute the values of the Transmit Clock Mode Register (TCMR) and the\r
+/// Transmit Frame Mode Register (TFMR) (see "SSC configuration macros").\r
+/// \param ssc Pointer to a AT91S_SSC instance.\r
+/// \param tcmr Transmit Clock Mode Register value.\r
+/// \param tfmr Transmit Frame Mode Register value.\r
+//------------------------------------------------------------------------------\r
+void SSC_ConfigureTransmitter(AT91S_SSC *ssc,\r
+ unsigned int tcmr,\r
+ unsigned int tfmr)\r
+{\r
+ ssc->SSC_TCMR = tcmr;\r
+ ssc->SSC_TFMR = tfmr;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the receiver of a SSC peripheral. Several macros can be used\r
+/// to compute the values of the Receive Clock Mode Register (TCMR) and the\r
+/// Receive Frame Mode Register (TFMR) (see "SSC configuration macros").\r
+/// \param ssc Pointer to a AT91S_SSC instance.\r
+/// \param rcmr Receive Clock Mode Register value.\r
+/// \param rfmr Receive Frame Mode Register value.\r
+//------------------------------------------------------------------------------\r
+void SSC_ConfigureReceiver(AT91S_SSC *ssc,\r
+ unsigned int rcmr,\r
+ unsigned int rfmr)\r
+{\r
+ ssc->SSC_RCMR = rcmr;\r
+ ssc->SSC_RFMR = rfmr;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the transmitter of a SSC peripheral.\r
+/// \param ssc Pointer to an AT91S_SSC instance.\r
+//------------------------------------------------------------------------------\r
+void SSC_EnableTransmitter(AT91S_SSC *ssc)\r
+{\r
+ ssc->SSC_CR = AT91C_SSC_TXEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the transmitter of a SSC peripheral.\r
+/// \param ssc Pointer to an AT91S_SSC instance.\r
+//------------------------------------------------------------------------------\r
+void SSC_DisableTransmitter(AT91S_SSC *ssc)\r
+{\r
+ ssc->SSC_CR = AT91C_SSC_TXDIS;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the receiver of a SSC peripheral.\r
+/// \param ssc Pointer to an AT91S_SSC instance.\r
+//------------------------------------------------------------------------------\r
+void SSC_EnableReceiver(AT91S_SSC *ssc)\r
+{\r
+ ssc->SSC_CR = AT91C_SSC_RXEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the receiver of a SSC peripheral.\r
+/// \param ssc Pointer to an AT91S_SSC instance.\r
+//------------------------------------------------------------------------------\r
+void SSC_DisableReceiver(AT91S_SSC *ssc)\r
+{\r
+ ssc->SSC_CR = AT91C_SSC_RXDIS;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables one or more interrupt sources of a SSC peripheral.\r
+/// \param ssc Pointer to an AT91S_SSC instance.\r
+/// \param sources Interrupt sources to enable.\r
+//------------------------------------------------------------------------------\r
+void SSC_EnableInterrupts(AT91S_SSC *ssc, unsigned int sources)\r
+{\r
+ ssc->SSC_IER = sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables one or more interrupt sources of a SSC peripheral.\r
+/// \param ssc Pointer to an AT91S_SSC instance.\r
+/// \param sources Interrupt source to disable.\r
+//------------------------------------------------------------------------------\r
+void SSC_DisableInterrupts(AT91S_SSC *ssc, unsigned int sources)\r
+{\r
+ ssc->SSC_IDR = sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sends one data frame through a SSC peripheral. If another frame is currently\r
+/// being sent, this function waits for the previous transfer to complete.\r
+/// \param ssc Pointer to an AT91S_SSC instance.\r
+/// \param frame Data frame to send.\r
+//------------------------------------------------------------------------------\r
+void SSC_Write(AT91S_SSC *ssc, unsigned int frame)\r
+{\r
+ while ((ssc->SSC_SR & AT91C_SSC_TXRDY) == 0);\r
+ ssc->SSC_THR = frame;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sends the contents of a data buffer a SSC peripheral, using the PDC. Returns\r
+/// true if the buffer has been queued for transmission; otherwise returns\r
+/// false.\r
+/// \param ssc Pointer to an AT91S_SSC instance.\r
+/// \param buffer Data buffer to send.\r
+/// \param length Size of the data buffer.\r
+//------------------------------------------------------------------------------\r
+unsigned char SSC_WriteBuffer(AT91S_SSC *ssc,\r
+ void *buffer,\r
+ unsigned int length)\r
+{\r
+ // Check if first bank is free\r
+ if (ssc->SSC_TCR == 0) {\r
+\r
+ ssc->SSC_TPR = (unsigned int) buffer;\r
+ ssc->SSC_TCR = length;\r
+ ssc->SSC_PTCR = AT91C_PDC_TXTEN;\r
+ return 1;\r
+ }\r
+ // Check if second bank is free\r
+ else if (ssc->SSC_TNCR == 0) {\r
+\r
+ ssc->SSC_TNPR = (unsigned int) buffer;\r
+ ssc->SSC_TNCR = length;\r
+ return 1;\r
+ }\r
+ \r
+ // No free banks\r
+ return 0;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Waits until one frame is received on a SSC peripheral, and returns it.\r
+/// \param ssc Pointer to an AT91S_SSC instance.\r
+//------------------------------------------------------------------------------\r
+unsigned int SSC_Read(AT91S_SSC *ssc)\r
+{\r
+ while ((ssc->SSC_SR & AT91C_SSC_RXRDY) == 0);\r
+ return ssc->SSC_RHR;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Reads data coming from a SSC peripheral receiver and stores it into the\r
+/// provided buffer. Returns true if the buffer has been queued for reception;\r
+/// otherwise returns false.\r
+/// \param ssc Pointer to an AT91S_SSC instance.\r
+/// \param buffer Data buffer used for reception.\r
+/// \param length Size in bytes of the data buffer.\r
+//------------------------------------------------------------------------------\r
+unsigned char SSC_ReadBuffer(AT91S_SSC *ssc,\r
+ void *buffer,\r
+ unsigned int length)\r
+{\r
+ // Check if the first bank is free\r
+ if (ssc->SSC_RCR == 0) {\r
+\r
+ ssc->SSC_RPR = (unsigned int) buffer;\r
+ ssc->SSC_RCR = length;\r
+ ssc->SSC_PTCR = AT91C_PDC_RXTEN;\r
+ return 1;\r
+ }\r
+ // Check if second bank is free\r
+ else if (ssc->SSC_RNCR == 0) {\r
+\r
+ ssc->SSC_RNPR = (unsigned int) buffer;\r
+ ssc->SSC_RNCR = length;\r
+ return 1;\r
+ }\r
+\r
+ // No free bank\r
+ return 0;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \dir\r
+/// !Purpose\r
+///\r
+/// Set of functions and definition for using a SSC\r
+/// peripheral.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Configure the SSC to operate at a specific frequency by calling\r
+/// SSC_Configure(). This function enables the peripheral clock of the SSC,\r
+/// but not its PIOs.\r
+/// -# Configure the transmitter and/or the receiver using the\r
+/// SSC_ConfigureTransmitter() and SSC_ConfigureEmitter() functions.\r
+/// -# Enable the PIOs or the transmitter and/or the received using\r
+/// CHIP_EnableSSCTransmitter() and CHIP_EnableSSCReceiver().\r
+/// -# Enable the transmitter and/or the receiver using SSC_EnableTransmitter()\r
+/// and SSC_EnableReceiver()\r
+/// -# Send data through the transmitter using SSC_Write() and SSC_WriteBuffer()\r
+/// -# Receive data from the receiver using SSC_Read() and SSC_ReadBuffer()\r
+/// -# Disable the transmitter and/or the receiver using SSC_DisableTransmitter()\r
+/// and SSC_DisableReceiver()\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef SSC_H\r
+#define SSC_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SSC configuration macros"\r
+/// This page lists several macros which are used when configuring a SSC\r
+/// peripheral.\r
+/// \r
+/// !Macros\r
+/// - SSC_STTDLY\r
+/// - SSC_PERIOD\r
+/// - SSC_DATLEN\r
+/// - SSC_DATNB\r
+/// - SSC_FSLEN\r
+\r
+/// Calculates the value of the STTDLY field given the number of clock cycles\r
+/// before the first bit of a new frame is transmitted.\r
+#define SSC_STTDLY(bits) (bits << 16)\r
+\r
+/// Calculates the value of the PERIOD field of the Transmit Clock Mode Register\r
+/// of an SSC interface, given the desired clock divider.\r
+#define SSC_PERIOD(divider) (((divider / 2) - 1) << 24)\r
+\r
+/// Calculates the value of the DATLEN field of the Transmit Frame Mode Register\r
+/// of an SSC interface, given the number of bits in one sample.\r
+#define SSC_DATLEN(bits) (bits - 1)\r
+\r
+/// Calculates the value of the DATNB field of the Transmit Frame Mode Register\r
+/// of an SSC interface, given the number of samples in one frame.\r
+#define SSC_DATNB(samples) ((samples -1) << 8)\r
+\r
+/// Calculates the value of the FSLEN field of the Transmit Frame Mode Register\r
+/// of an SSC interface, given the number of transmit clock periods that the \r
+/// frame sync signal should take.\r
+#define SSC_FSLEN(periods) ((periods - 1) << 16)\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+extern void SSC_Configure(AT91S_SSC *ssc,\r
+ unsigned int id,\r
+ unsigned int bitRate,\r
+ unsigned int masterClock);\r
+extern void SSC_ConfigureTransmitter(AT91S_SSC *ssc,\r
+ unsigned int tcmr,\r
+ unsigned int tfmr);\r
+extern void SSC_ConfigureReceiver(AT91S_SSC *ssc,\r
+ unsigned int rcmr,\r
+ unsigned int rfmr);\r
+\r
+extern void SSC_EnableTransmitter(AT91S_SSC *ssc);\r
+extern void SSC_DisableTransmitter(AT91S_SSC *ssc);\r
+extern void SSC_EnableReceiver(AT91S_SSC *ssc);\r
+extern void SSC_DisableReceiver(AT91S_SSC *ssc);\r
+\r
+extern void SSC_EnableInterrupts(AT91S_SSC *ssc, unsigned int sources);\r
+extern void SSC_DisableInterrupts(AT91S_SSC *ssc, unsigned int sources);\r
+\r
+extern void SSC_Write(AT91S_SSC *ssc, unsigned int frame);\r
+extern unsigned char SSC_WriteBuffer(AT91S_SSC *ssc,\r
+ void *buffer,\r
+ unsigned int length);\r
+extern unsigned int SSC_Read(AT91S_SSC *ssc);\r
+extern unsigned char SSC_ReadBuffer(AT91S_SSC *ssc,\r
+ void *buffer,\r
+ unsigned int length);\r
+\r
+#endif //#ifndef SSC_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "supc.h"\r
+#include <board.h>\r
+#include <utility/assert.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Local definitions\r
+//------------------------------------------------------------------------------\r
+\r
+/// Key value for the SUPC_MR register.\r
+#define SUPC_KEY ((unsigned int) (0xA5 << 24))\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the SLCD power supply.\r
+/// \param internal If 1, the power supply is configured as internal; otherwise\r
+/// it is set at external.\r
+//------------------------------------------------------------------------------\r
+void SUPC_EnableSlcd(unsigned char internal)\r
+{\r
+ if (internal) {\r
+\r
+ AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDMODE) | AT91C_SUPC_LCDMODE_INTERNAL;\r
+ }\r
+ else {\r
+\r
+ AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDMODE) | AT91C_SUPC_LCDMODE_EXTERNAL;\r
+ }\r
+ while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_LCDS) != AT91C_SUPC_LCDS);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the SLCD power supply.\r
+//------------------------------------------------------------------------------\r
+void SUPC_DisableSlcd(void)\r
+{\r
+ AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDMODE);\r
+ while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_LCDS) == AT91C_SUPC_LCDS);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the output voltage of the SLCD charge pump.\r
+/// \param voltage Output voltage.\r
+//------------------------------------------------------------------------------\r
+void SUPC_SetSlcdVoltage(unsigned int voltage)\r
+{\r
+ SANITY_CHECK((voltage & ~AT91C_SUPC_LCDOUT) == 0);\r
+ AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDOUT) | voltage;\r
+}\r
+\r
+#if !defined(__ICCARM__)\r
+__attribute__ ((section (".ramfunc"))) // GCC\r
+#endif\r
+//------------------------------------------------------------------------------\r
+/// Enables the flash power supply with the given wake-up setting.\r
+/// \param time Wake-up time.\r
+//------------------------------------------------------------------------------\r
+void SUPC_EnableFlash(unsigned int time)\r
+{\r
+ AT91C_BASE_SUPC->SUPC_FWUTR = time;\r
+ AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_FLASHON;\r
+ while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_FLASHS) != AT91C_SUPC_FLASHS);\r
+}\r
+\r
+#if !defined(__ICCARM__)\r
+__attribute__ ((section (".ramfunc"))) // GCC\r
+#endif\r
+//------------------------------------------------------------------------------\r
+/// Disables the flash power supply.\r
+//------------------------------------------------------------------------------\r
+void SUPC_DisableFlash(void)\r
+{\r
+ AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_FLASHON);\r
+ while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_FLASHS) == AT91C_SUPC_FLASHS);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the voltage regulator output voltage.\r
+/// \param voltage Voltage to set.\r
+//------------------------------------------------------------------------------\r
+void SUPC_SetVoltageOutput(unsigned int voltage)\r
+{\r
+ SANITY_CHECK((voltage & ~AT91C_SUPC_VRVDD) == 0);\r
+ AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_VRVDD) | voltage;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Puts the voltage regulator in deep mode.\r
+//------------------------------------------------------------------------------\r
+void SUPC_EnableDeepMode(void)\r
+{\r
+ AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_VRDEEP;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Puts the voltage regulator in normal mode.\r
+//------------------------------------------------------------------------------\r
+void SUPC_DisableDeepMode(void)\r
+{\r
+ AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_VRDEEP);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enables the backup SRAM power supply, so its data is saved while the device\r
+/// is in backup mode.\r
+//-----------------------------------------------------------------------------\r
+void SUPC_EnableSram(void)\r
+{\r
+ AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_SRAMON;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Disables the backup SRAM power supply.\r
+//-----------------------------------------------------------------------------\r
+void SUPC_DisableSram(void)\r
+{\r
+ AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_SRAMON);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enables the RTC power supply.\r
+//-----------------------------------------------------------------------------\r
+void SUPC_EnableRtc(void)\r
+{\r
+ AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_RTCON;\r
+ while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_RTS) != AT91C_SUPC_RTS);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Disables the RTC power supply.\r
+//-----------------------------------------------------------------------------\r
+void SUPC_DisableRtc(void)\r
+{\r
+ AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_RTCON);\r
+ while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_RTS) == AT91C_SUPC_RTS);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Sets the BOD sampling mode (or disables it).\r
+/// \param mode BOD sampling mode.\r
+//-----------------------------------------------------------------------------\r
+void SUPC_SetBodSampling(unsigned int mode)\r
+{\r
+ SANITY_CHECK((mode & ~AT91C_SUPC_BODSMPL) == 0);\r
+ AT91C_BASE_SUPC->SUPC_BOMR &= ~AT91C_SUPC_BODSMPL;\r
+ AT91C_BASE_SUPC->SUPC_BOMR |= mode;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the voltage regulator, which makes the device enter backup mode.\r
+//------------------------------------------------------------------------------\r
+void SUPC_DisableVoltageRegulator(void)\r
+{\r
+ AT91C_BASE_SUPC->SUPC_CR = SUPC_KEY | AT91C_SUPC_VROFF;\r
+ while (1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Shuts the device down so it enters Off mode.\r
+//------------------------------------------------------------------------------\r
+void SUPC_Shutdown(void)\r
+{\r
+ AT91C_BASE_SUPC->SUPC_CR = SUPC_KEY | AT91C_SUPC_SHDW;\r
+ while (1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the wake-up sources when in backup mode.\r
+/// \param sources Wake-up sources to enable.\r
+//------------------------------------------------------------------------------\r
+void SUPC_SetWakeUpSources(unsigned int sources)\r
+{\r
+ SANITY_CHECK((sources & ~0x0000000B) == 0);\r
+ AT91C_BASE_SUPC->SUPC_WUMR &= ~0x0000000B;\r
+ AT91C_BASE_SUPC->SUPC_WUMR |= sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the wake-up inputs when in backup mode.\r
+/// \param inputs Wake up inputs to enable.\r
+//------------------------------------------------------------------------------\r
+void SUPC_SetWakeUpInputs(unsigned int inputs)\r
+{\r
+ SANITY_CHECK((inputs & ~0xFFFF) == 0);\r
+ AT91C_BASE_SUPC->SUPC_WUIR &= ~0xFFFF;\r
+ AT91C_BASE_SUPC->SUPC_WUIR |= inputs;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef SUPC_H\r
+#define SUPC_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void SUPC_EnableSlcd(unsigned char internal);\r
+\r
+extern void SUPC_DisableSlcd(void);\r
+\r
+extern void SUPC_SetSlcdVoltage(unsigned int voltage);\r
+\r
+extern\r
+#ifdef __ICCARM__\r
+__ramfunc // IAR\r
+#endif\r
+void SUPC_EnableFlash(unsigned int time);\r
+\r
+extern\r
+#ifdef __ICCARM__\r
+__ramfunc // IAR\r
+#endif\r
+void SUPC_DisableFlash(void);\r
+\r
+extern void SUPC_SetVoltageOutput(unsigned int voltage);\r
+\r
+extern void SUPC_EnableDeepMode(void);\r
+\r
+extern void SUPC_EnableSram(void);\r
+\r
+extern void SUPC_DisableSram(void);\r
+\r
+extern void SUPC_EnableRtc(void);\r
+\r
+extern void SUPC_DisableRtc(void);\r
+\r
+extern void SUPC_SetBodSampling(unsigned int mode);\r
+\r
+extern void SUPC_DisableDeepMode(void);\r
+\r
+extern void SUPC_DisableVoltageRegulator(void);\r
+\r
+extern void SUPC_Shutdown(void);\r
+\r
+extern void SUPC_SetWakeUpSources(unsigned int sources);\r
+\r
+extern void SUPC_SetWakeUpInputs(unsigned int inputs);\r
+\r
+#endif //#ifndef SUPC_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "tc.h"\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures a Timer Counter to operate in the given mode. Timer is stopped\r
+/// after configuration and must be restarted with TC_Start().\r
+/// to obtain the target frequency.\r
+/// \param pTc Pointer to an AT91S_TC instance.\r
+/// \param mode Operating mode.\r
+//------------------------------------------------------------------------------\r
+void TC_Configure(AT91S_TC *pTc, unsigned int mode)\r
+{\r
+ // Disable TC clock\r
+ pTc->TC_CCR = AT91C_TC_CLKDIS;\r
+\r
+ // Disable interrupts\r
+ pTc->TC_IDR = 0xFFFFFFFF;\r
+\r
+ // Clear status register\r
+ pTc->TC_SR;\r
+\r
+ // Set mode\r
+ pTc->TC_CMR = mode;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts the timer clock.\r
+/// \param pTc Pointer to an AT91S_TC instance.\r
+//------------------------------------------------------------------------------\r
+void TC_Start(AT91S_TC *pTc)\r
+{\r
+ pTc->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Stops the timer clock.\r
+/// \param pTc Pointer to an AT91S_TC instance.\r
+//------------------------------------------------------------------------------\r
+void TC_Stop(AT91S_TC *pTc)\r
+{\r
+ pTc->TC_CCR = AT91C_TC_CLKDIS;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Finds the best MCK divisor given the timer frequency and MCK. The result\r
+/// is guaranteed to satisfy the following equation:\r
+/// (MCK / (DIV * 65536)) <= freq <= (MCK / DIV)\r
+/// with DIV being the highest possible value.\r
+/// Returns 1 if a divisor could be found; otherwise returns 0.\r
+/// \param freq Desired timer frequency.\r
+/// \param mck Master clock frequency.\r
+/// \param div Divisor value.\r
+/// \param tcclks TCCLKS field value for divisor.\r
+//------------------------------------------------------------------------------\r
+unsigned char TC_FindMckDivisor(\r
+ unsigned int freq,\r
+ unsigned int mck,\r
+ unsigned int *div,\r
+ unsigned int *tcclks)\r
+{\r
+ const unsigned int divisors[5] = {2, 8, 32, 128,\r
+#if defined(at91sam9260) || defined(at91sam9261) || defined(at91sam9263) \\r
+ || defined(at91sam9xe) || defined(at91sam9rl64) || defined(at91cap9)\r
+ BOARD_MCK / 32768};\r
+#else\r
+ 1024};\r
+#endif\r
+ unsigned int index = 0;\r
+\r
+ // Satisfy lower bound\r
+ while (freq < ((mck / divisors[index]) / 65536)) {\r
+\r
+ index++;\r
+\r
+ // If no divisor can be found, return 0\r
+ if (index == 5) {\r
+\r
+ return 0;\r
+ }\r
+ }\r
+\r
+ // Try to maximise DIV while satisfying upper bound\r
+ while (index < 4) {\r
+\r
+ if (freq > (mck / divisors[index + 1])) {\r
+\r
+ break;\r
+ }\r
+ index++;\r
+ }\r
+\r
+ // Store results\r
+ if (div) {\r
+\r
+ *div = divisors[index];\r
+ }\r
+ if (tcclks) {\r
+\r
+ *tcclks = index;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef TC_H\r
+#define TC_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+#if !defined(AT91C_ID_TC0) && defined(AT91C_ID_TC012)\r
+ #define AT91C_ID_TC0 AT91C_ID_TC012\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void TC_Configure(AT91S_TC *pTc, unsigned int mode);\r
+\r
+extern void TC_Start(AT91S_TC *pTc);\r
+\r
+extern void TC_Stop(AT91S_TC *pTc);\r
+\r
+extern unsigned char TC_FindMckDivisor(\r
+ unsigned int freq,\r
+ unsigned int mck,\r
+ unsigned int *div,\r
+ unsigned int *tcclks);\r
+\r
+#endif //#ifndef TC_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef trace_LEVEL\r
+ #define trace_LEVEL 1\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "tdes.h"\r
+#include <board.h>\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the triple-DES peripheral to cipher/decipher, use single-DES or\r
+/// triple-DES, use two or three keys (when in triple-DES mode), start manually,\r
+/// automatically or via the PDC and use the given operating mode (ECB, CBC,\r
+/// CFB or OFB).\r
+/// \param cipher Encrypts if 1, decrypts if 0.\r
+/// \param tdesmod Single- or triple-DES mode.\r
+/// \param keymod Use two or three keys (must be 0 in single-DES mode).\r
+/// \param smod Start mode.\r
+/// \param opmod Encryption/decryption mode.\r
+//------------------------------------------------------------------------------\r
+void TDES_Configure(\r
+ unsigned char cipher,\r
+ unsigned int tdesmod,\r
+ unsigned int keymod,\r
+ unsigned int smod,\r
+ unsigned int opmod)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- TDES_Configure()\n\r");\r
+ SANITY_CHECK((cipher & 0xFFFFFFFE) == 0);\r
+ SANITY_CHECK((tdesmod & 0xFFFFFFFD) == 0);\r
+ SANITY_CHECK((keymod & 0xFFFFFFEF) == 0);\r
+ SANITY_CHECK((smod & 0xFFFFFCFF) == 0);\r
+ SANITY_CHECK((opmod & 0xFFFFCFFF) == 0);\r
+\r
+ // Reset peripheral\r
+ AT91C_BASE_TDES->TDES_CR = AT91C_TDES_SWRST;\r
+\r
+ // Configure mode register\r
+ AT91C_BASE_TDES->TDES_MR = cipher | tdesmod | keymod | smod | opmod;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts the encryption or decryption process if the TDES peripheral is\r
+/// configured in manual or PDC mode.\r
+//------------------------------------------------------------------------------\r
+void TDES_Start(void)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- TDES_Start()\n\r");\r
+ SANITY_CHECK(((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_SMOD) == AT91C_TDES_SMOD_MANUAL)\r
+ || ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_SMOD) == AT91C_TDES_SMOD_PDC));\r
+\r
+ // Manual mode\r
+ if ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_SMOD) == AT91C_TDES_SMOD_MANUAL) {\r
+\r
+ AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START;\r
+ }\r
+ // PDC mode\r
+ else {\r
+\r
+ AT91C_BASE_TDES->TDES_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the current status register value of the TDES peripheral.\r
+//------------------------------------------------------------------------------\r
+unsigned int TDES_GetStatus(void)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- TDES_GetStatus()\n\r");\r
+\r
+ return AT91C_BASE_TDES->TDES_ISR;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the 64-bits keys (one, two or three depending on the configuration)\r
+/// that shall be used by the TDES algorithm.\r
+/// \param pKey1 Pointer to key #1.\r
+/// \param pKey2 Pointer to key #2 (shall be 0 in single-DES mode).\r
+/// \param pKey3 Pointer to key #3 (shall be 0 when using two keys).\r
+//------------------------------------------------------------------------------\r
+void TDES_SetKeys(\r
+ const unsigned int *pKey1,\r
+ const unsigned int *pKey2,\r
+ const unsigned int *pKey3)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- TDES_SetKeys()\n\r");\r
+ SANITY_CHECK(pKey1);\r
+ SANITY_CHECK((pKey2 && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == AT91C_TDES_TDESMOD))\r
+ || (!pKey2 && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == 0)));\r
+ SANITY_CHECK((pKey3\r
+ && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == AT91C_TDES_TDESMOD)\r
+ && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_KEYMOD) == 0))\r
+ ||\r
+ (!pKey3\r
+ && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == AT91C_TDES_TDESMOD)\r
+ && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_KEYMOD) == AT91C_TDES_KEYMOD))\r
+ ||\r
+ (!pKey3\r
+ && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == 0)\r
+ && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_KEYMOD) == 0)));\r
+\r
+ // Write key #1\r
+ if (pKey1) {\r
+\r
+ AT91C_BASE_TDES->TDES_KEY1WxR[0] = pKey1[0];\r
+ AT91C_BASE_TDES->TDES_KEY1WxR[1] = pKey1[1];\r
+ }\r
+\r
+ // Write key #2\r
+ if (pKey1) {\r
+\r
+ AT91C_BASE_TDES->TDES_KEY2WxR[0] = pKey2[0];\r
+ AT91C_BASE_TDES->TDES_KEY2WxR[1] = pKey2[1];\r
+ }\r
+\r
+ // Write key #2\r
+ if (pKey1) {\r
+\r
+ AT91C_BASE_TDES->TDES_KEY3WxR[0] = pKey3[0];\r
+ AT91C_BASE_TDES->TDES_KEY3WxR[1] = pKey3[1];\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the input data to encrypt/decrypt using TDES.\r
+/// \param pInput Pointer to the 64-bits input data.\r
+//------------------------------------------------------------------------------\r
+void TDES_SetInputData(const unsigned int *pInput)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- TDES_SetInputData()\n\r");\r
+ SANITY_CHECK(pInput);\r
+\r
+ AT91C_BASE_TDES->TDES_IDATAxR[0] = pInput[0];\r
+ AT91C_BASE_TDES->TDES_IDATAxR[1] = pInput[1];\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the input data buffer to encrypt/decrypt when in PDC mode.\r
+/// \param pInput Pointer to the input data.\r
+/// \param size Size of buffer in bytes.\r
+//------------------------------------------------------------------------------\r
+void TDES_SetInputBuffer(const unsigned int *pInput, unsigned int size)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- TDES_SetInputBuffer()\n\r");\r
+ SANITY_CHECK(pInput);\r
+ SANITY_CHECK((size > 0) && ((size % 8) == 0));\r
+\r
+ AT91C_BASE_TDES->TDES_TPR = (unsigned int) pInput;\r
+ AT91C_BASE_TDES->TDES_TCR = size / 4;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Stores the output data from the last TDES operation into the given 64-bits\r
+/// buffers.\r
+/// \param pOutput Pointer to a 64-bits output buffer.\r
+//------------------------------------------------------------------------------\r
+void TDES_GetOutputData(unsigned int *pOutput)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- TDES_GetOutputData()\n\r");\r
+ SANITY_CHECK(pOutput);\r
+\r
+ pOutput[0] = AT91C_BASE_TDES->TDES_ODATAxR[0];\r
+ pOutput[1] = AT91C_BASE_TDES->TDES_ODATAxR[1];\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the output buffer which will receive the encrypted/decrypted data when\r
+/// using the PDC.\r
+/// \param pOutput Pointer to the output data.\r
+/// \param size Size of buffer in bytes.\r
+//------------------------------------------------------------------------------\r
+void TDES_SetOutputBuffer(unsigned int *pOutput, unsigned int size)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- TDES_SetOutputBuffer()\n\r");\r
+ SANITY_CHECK(pOutput);\r
+ SANITY_CHECK((size > 0) && ((size % 8) == 0));\r
+\r
+ AT91C_BASE_TDES->TDES_RPR = (unsigned int) pOutput;\r
+ AT91C_BASE_TDES->TDES_RCR = size / 4;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the initialization vector to use when the TDES algorithm is configured\r
+/// in a chained block mode (CBC, CFB or OFB).\r
+/// \param pVector Pointer to the 64-bits vector.\r
+//------------------------------------------------------------------------------\r
+void TDES_SetVector(const unsigned int *pVector)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- TDES_SetVector()\n\r");\r
+ SANITY_CHECK(pVector);\r
+\r
+ AT91C_BASE_TDES->TDES_IVxR[0] = pVector[0];\r
+ AT91C_BASE_TDES->TDES_IVxR[1] = pVector[1];\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef TDES_H\r
+#define TDES_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void TDES_Configure(\r
+ unsigned char cipher,\r
+ unsigned int tdesmod,\r
+ unsigned int keymod,\r
+ unsigned int smod,\r
+ unsigned int opmod);\r
+\r
+extern void TDES_Start(void);\r
+\r
+extern unsigned int TDES_GetStatus(void);\r
+\r
+extern void TDES_SetKeys(\r
+ const unsigned int *pKey1,\r
+ const unsigned int *pKey2,\r
+ const unsigned int *pKey3);\r
+\r
+extern void TDES_SetInputData(const unsigned int *pInput);\r
+\r
+extern void TDES_SetInputBuffer(const unsigned int *pInput, unsigned int size);\r
+\r
+extern void TDES_GetOutputData(unsigned int *pOutput);\r
+\r
+extern void TDES_SetOutputBuffer(unsigned int *pOutput, unsigned int size);\r
+\r
+extern void TDES_SetVector(const unsigned int *pVector);\r
+\r
+#endif //#ifndef TDES_H\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef trace_LEVEL\r
+ #define trace_LEVEL 1\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "twi.h"\r
+#include <utility/math.h>\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures a TWI peripheral to operate in master mode, at the given\r
+/// frequency (in Hz). The duty cycle of the TWI clock is set to 50%.\r
+/// \param pTwi Pointer to an AT91S_TWI instance.\r
+/// \param twck Desired TWI clock frequency.\r
+/// \param mck Master clock frequency.\r
+//------------------------------------------------------------------------------\r
+void TWI_Configure(AT91S_TWI *pTwi, unsigned int twck, unsigned int mck)\r
+{\r
+ unsigned int ckdiv = 0;\r
+ unsigned int cldiv;\r
+ unsigned char ok = 0;\r
+\r
+ trace_LOG(trace_DEBUG, "-D- TWI_Configure()\n\r");\r
+ SANITY_CHECK(pTwi);\r
+\r
+ // Reset the TWI\r
+ pTwi->TWI_CR = AT91C_TWI_SWRST;\r
+\r
+ // Set master mode\r
+ pTwi->TWI_CR = AT91C_TWI_MSEN;\r
+\r
+ // Configure clock\r
+ while (!ok) {\r
+ \r
+ cldiv = ((mck / (2 * twck)) - 3) / power(2, ckdiv);\r
+ if (cldiv <= 255) {\r
+\r
+ ok = 1;\r
+ }\r
+ else {\r
+\r
+ ckdiv++;\r
+ }\r
+ }\r
+\r
+ ASSERT(ckdiv < 8, "-F- Cannot find valid TWI clock parameters\n\r");\r
+ trace_LOG(trace_INFO, "-D- Using CKDIV = %u and CLDIV/CHDIV = %u\n\r", ckdiv, cldiv);\r
+ pTwi->TWI_CWGR = (ckdiv << 16) | (cldiv << 8) | cldiv;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sends a STOP condition on the TWI.\r
+/// \param pTwi Pointer to an AT91S_TWI instance.\r
+//------------------------------------------------------------------------------\r
+void TWI_Stop(AT91S_TWI *pTwi)\r
+{\r
+ SANITY_CHECK(pTwi);\r
+\r
+ pTwi->TWI_CR = AT91C_TWI_STOP;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts a read operation on the TWI bus with the specified slave, and returns\r
+/// immediately. Data must then be read using TWI_ReadByte() whenever a byte is\r
+/// available (poll using TWI_ByteReceived()).\r
+/// \param pTwi Pointer to an AT91S_TWI instance.\r
+/// \param address Slave address on the bus.\r
+/// \param iaddress Optional internal address bytes.\r
+/// \param isize Number of internal address bytes.\r
+//-----------------------------------------------------------------------------\r
+void TWI_StartRead(\r
+ AT91S_TWI *pTwi,\r
+ unsigned char address,\r
+ unsigned int iaddress,\r
+ unsigned char isize)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- TWI_StartRead()\n\r");\r
+ SANITY_CHECK(pTwi);\r
+ SANITY_CHECK((address & 0x80) == 0);\r
+ SANITY_CHECK((iaddress & 0xFF000000) == 0);\r
+ SANITY_CHECK(isize < 4);\r
+\r
+ // Set slave address and number of internal address bytes\r
+ pTwi->TWI_MMR = (isize << 8) | AT91C_TWI_MREAD | (address << 16);\r
+\r
+ // Set internal address bytes\r
+ pTwi->TWI_IADR = iaddress;\r
+\r
+ // Send START condition\r
+ pTwi->TWI_CR = AT91C_TWI_START;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Reads a byte from the TWI bus. The read operation must have been started\r
+/// using TWI_StartRead() and a byte must be available (check with\r
+/// TWI_ByteReceived()).\r
+/// Returns the byte read.\r
+/// \param pTwi Pointer to an AT91S_TWI instance.\r
+//-----------------------------------------------------------------------------\r
+unsigned char TWI_ReadByte(AT91S_TWI *pTwi)\r
+{\r
+ SANITY_CHECK(pTwi);\r
+\r
+ return pTwi->TWI_RHR;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Sends a byte of data to one of the TWI slaves on the bus. This function\r
+/// must be called once before TWI_StartWrite() with the first byte of data\r
+/// to send, then it shall be called repeatedly after that to send the\r
+/// remaining bytes.\r
+/// \param pTwi Pointer to an AT91S_TWI instance.\r
+/// \param byte Byte to send.\r
+//-----------------------------------------------------------------------------\r
+void TWI_WriteByte(AT91S_TWI *pTwi, unsigned char byte)\r
+{\r
+ SANITY_CHECK(pTwi);\r
+\r
+ pTwi->TWI_THR = byte;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Starts a write operation on the TWI to access the selected slave, then\r
+/// returns immediately. A byte of data must be provided to start the write;\r
+/// other bytes are written next.\r
+/// \param pTwi Pointer to an AT91S_TWI instance.\r
+/// \param address Address of slave to acccess on the bus.\r
+/// \param iaddress Optional slave internal address.\r
+/// \param isize Number of internal address bytes.\r
+/// \param byte First byte to send.\r
+//-----------------------------------------------------------------------------\r
+void TWI_StartWrite(\r
+ AT91S_TWI *pTwi,\r
+ unsigned char address,\r
+ unsigned int iaddress,\r
+ unsigned char isize,\r
+ unsigned char byte)\r
+{\r
+ trace_LOG(trace_DEBUG, "-D- TWI_StartWrite()\n\r");\r
+ SANITY_CHECK(pTwi);\r
+ SANITY_CHECK((address & 0x80) == 0);\r
+ SANITY_CHECK((iaddress & 0xFF000000) == 0);\r
+ SANITY_CHECK(isize < 4);\r
+\r
+ // Set slave address and number of internal address bytes\r
+ pTwi->TWI_MMR = (isize << 8) | (address << 16);\r
+\r
+ // Set internal address bytes\r
+ pTwi->TWI_IADR = iaddress;\r
+\r
+ // Write first byte to send\r
+ TWI_WriteByte(pTwi, byte);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Returns 1 if a byte has been received and can be read on the given TWI\r
+/// peripheral; otherwise, returns 0. This function resets the status register\r
+/// of the TWI.\r
+/// \param pTwi Pointer to an AT91S_TWI instance.\r
+//-----------------------------------------------------------------------------\r
+unsigned char TWI_ByteReceived(AT91S_TWI *pTwi)\r
+{\r
+ return ((pTwi->TWI_SR & AT91C_TWI_RXRDY) == AT91C_TWI_RXRDY);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Returns 1 if a byte has been sent, so another one can be stored for\r
+/// transmission; otherwise returns 0. This function clears the status register\r
+/// of the TWI.\r
+/// \param pTwi Pointer to an AT91S_TWI instance.\r
+//-----------------------------------------------------------------------------\r
+unsigned char TWI_ByteSent(AT91S_TWI *pTwi)\r
+{\r
+ return ((pTwi->TWI_SR & AT91C_TWI_TXRDY) == AT91C_TWI_TXRDY);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Returns 1 if the current transmission is complete (the STOP has been sent);\r
+/// otherwise returns 0.\r
+/// \param pTwi Pointer to an AT91S_TWI instance.\r
+//-----------------------------------------------------------------------------\r
+unsigned char TWI_TransferComplete(AT91S_TWI *pTwi)\r
+{\r
+ return ((pTwi->TWI_SR & AT91C_TWI_TXCOMP) == AT91C_TWI_TXCOMP);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enables the selected interrupts sources on a TWI peripheral.\r
+/// \param pTwi Pointer to an AT91S_TWI instance.\r
+/// \param sources Bitwise OR of selected interrupt sources.\r
+//-----------------------------------------------------------------------------\r
+void TWI_EnableIt(AT91S_TWI *pTwi, unsigned int sources)\r
+{\r
+ SANITY_CHECK(pTwi);\r
+ SANITY_CHECK((sources & 0xFFFFFEF8) == 0);\r
+\r
+ pTwi->TWI_IER = sources;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Disables the selected interrupts sources on a TWI peripheral.\r
+/// \param pTwi Pointer to an AT91S_TWI instance.\r
+/// \param sources Bitwise OR of selected interrupt sources.\r
+//-----------------------------------------------------------------------------\r
+void TWI_DisableIt(AT91S_TWI *pTwi, unsigned int sources)\r
+{\r
+ SANITY_CHECK(pTwi);\r
+ SANITY_CHECK((sources & 0xFFFFFEF8) == 0);\r
+\r
+ pTwi->TWI_IDR = sources;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Returns the current status register of the given TWI peripheral. This\r
+/// resets the internal value of the status register, so further read may yield\r
+/// different values.\r
+/// \param pTwi Pointer to an AT91S_TWI instance.\r
+//-----------------------------------------------------------------------------\r
+unsigned int TWI_GetStatus(AT91S_TWI *pTwi)\r
+{\r
+ SANITY_CHECK(pTwi);\r
+\r
+ return pTwi->TWI_SR;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Returns the current status register of the given TWI peripheral, but\r
+/// masking interrupt sources which are not currently enabled.\r
+/// This resets the internal value of the status register, so further read may\r
+/// yield different values.\r
+/// \param pTwi Pointer to an AT91S_TWI instance.\r
+//-----------------------------------------------------------------------------\r
+unsigned int TWI_GetMaskedStatus(AT91S_TWI *pTwi)\r
+{\r
+ unsigned int status;\r
+ \r
+ SANITY_CHECK(pTwi);\r
+ \r
+ status = pTwi->TWI_SR;\r
+ status &= pTwi->TWI_IMR;\r
+\r
+ return status;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef TWI_H\r
+#define TWI_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Global definitions\r
+//------------------------------------------------------------------------------\r
+\r
+// Missing AT91C_TWI_TXRDY definition.\r
+#ifndef AT91C_TWI_TXRDY\r
+ #define AT91C_TWI_TXRDY AT91C_TWI_TXRDY_MASTER\r
+#endif\r
+\r
+// Missing AT91C_TWI_TXCOMP definition.\r
+#ifndef AT91C_TWI_TXCOMP\r
+ #define AT91C_TWI_TXCOMP AT91C_TWI_TXCOMP_MASTER\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Global macros\r
+//------------------------------------------------------------------------------\r
+\r
+/// Returns 1 if the TXRDY bit (ready to transmit data) is set in the given\r
+/// status register value.\r
+#define TWI_STATUS_TXRDY(status) ((status & AT91C_TWI_TXRDY) == AT91C_TWI_TXRDY)\r
+\r
+/// Returns 1 if the RXRDY bit (ready to receive data) is set in the given\r
+/// status register value.\r
+#define TWI_STATUS_RXRDY(status) ((status & AT91C_TWI_RXRDY) == AT91C_TWI_RXRDY)\r
+\r
+/// Returns 1 if the TXCOMP bit (transfer complete) is set in the given\r
+/// status register value.\r
+#define TWI_STATUS_TXCOMP(status) ((status & AT91C_TWI_TXCOMP) == AT91C_TWI_TXCOMP)\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void TWI_Configure(AT91S_TWI *pTwi, unsigned int twck, unsigned int mck);\r
+\r
+extern void TWI_Stop(AT91S_TWI *pTwi);\r
+\r
+extern void TWI_StartRead(\r
+ AT91S_TWI *pTwi,\r
+ unsigned char address,\r
+ unsigned int iaddress,\r
+ unsigned char isize);\r
+\r
+extern unsigned char TWI_ReadByte(AT91S_TWI *pTwi);\r
+\r
+extern void TWI_WriteByte(AT91S_TWI *pTwi, unsigned char byte);\r
+\r
+extern void TWI_StartWrite(\r
+ AT91S_TWI *pTwi,\r
+ unsigned char address,\r
+ unsigned int iaddress,\r
+ unsigned char isize,\r
+ unsigned char byte);\r
+\r
+extern unsigned char TWI_ByteReceived(AT91S_TWI *pTwi);\r
+\r
+extern unsigned char TWI_ByteSent(AT91S_TWI *pTwi);\r
+\r
+extern unsigned char TWI_TransferComplete(AT91S_TWI *pTwi);\r
+\r
+extern void TWI_EnableIt(AT91S_TWI *pTwi, unsigned int sources);\r
+\r
+extern void TWI_DisableIt(AT91S_TWI *pTwi, unsigned int sources);\r
+\r
+extern unsigned int TWI_GetStatus(AT91S_TWI *pTwi);\r
+\r
+extern unsigned int TWI_GetMaskedStatus(AT91S_TWI *pTwi);\r
+\r
+#endif //#ifndef TWI_H\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "usart.h"\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// Configures an USART peripheral with the specified parameters.\r
+/// \param usart Pointer to the USART peripheral to configure.\r
+/// \param mode Desired value for the USART mode register (see the datasheet).\r
+/// \param baudrate Baudrate at which the USART should operate (in Hz).\r
+/// \param masterClock Frequency of the system master clock (in Hz).\r
+//------------------------------------------------------------------------------\r
+void USART_Configure(AT91S_USART *usart,\r
+ unsigned int mode,\r
+ unsigned int baudrate,\r
+ unsigned int masterClock)\r
+{\r
+ // Reset and disable receiver & transmitter\r
+ usart->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX\r
+ | AT91C_US_RXDIS | AT91C_US_TXDIS;\r
+\r
+ // Configure mode\r
+ usart->US_MR = mode;\r
+\r
+ // Configure baudrate\r
+ // Asynchronous, no oversampling\r
+ if (((mode & AT91C_US_SYNC) == 0)\r
+ && ((mode & AT91C_US_OVER) == 0)) {\r
+ \r
+ usart->US_BRGR = (masterClock / baudrate) / 16;\r
+ }\r
+ // TODO other modes\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables or disables the transmitter of an USART peripheral.\r
+/// \param usart Pointer to an USART peripheral\r
+/// \param enabled If true, the transmitter is enabled; otherwise it is\r
+/// disabled.\r
+//------------------------------------------------------------------------------\r
+void USART_SetTransmitterEnabled(AT91S_USART *usart,\r
+ unsigned char enabled)\r
+{\r
+ if (enabled) {\r
+\r
+ usart->US_CR = AT91C_US_TXEN;\r
+ }\r
+ else {\r
+\r
+ usart->US_CR = AT91C_US_TXDIS;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables or disables the receiver of an USART peripheral\r
+/// \param usart Pointer to an USART peripheral\r
+/// \param enabled If true, the receiver is enabled; otherwise it is disabled.\r
+//------------------------------------------------------------------------------\r
+void USART_SetReceiverEnabled(AT91S_USART *usart,\r
+ unsigned char enabled)\r
+{\r
+ if (enabled) {\r
+\r
+ usart->US_CR = AT91C_US_RXEN;\r
+ }\r
+ else {\r
+\r
+ usart->US_CR = AT91C_US_RXDIS;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sends one packet of data through the specified USART peripheral. This\r
+/// function operates synchronously, so it only returns when the data has been\r
+/// actually sent.\r
+/// \param usart Pointer to an USART peripheral.\r
+/// \param data Data to send including 9nth bit and sync field if necessary (in\r
+/// the same format as the US_THR register in the datasheet).\r
+/// \param timeOut Time out value (0 = no timeout).\r
+//------------------------------------------------------------------------------\r
+void USART_Write(\r
+ AT91S_USART *usart,\r
+ unsigned short data,\r
+ volatile unsigned int timeOut)\r
+{\r
+ if (timeOut == 0) {\r
+\r
+ while ((usart->US_CSR & AT91C_US_TXEMPTY) == 0);\r
+ }\r
+ else {\r
+\r
+ while ((usart->US_CSR & AT91C_US_TXEMPTY) == 0) {\r
+\r
+ if (timeOut == 0) {\r
+\r
+ trace_LOG(trace_ERROR, "-E- USART_Write: Timed out.\n\r");\r
+ return;\r
+ }\r
+ timeOut--;\r
+ }\r
+ }\r
+\r
+ usart->US_THR = data;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sends the contents of a data buffer through the specified USART peripheral.\r
+/// This function returns immediately (1 if the buffer has been queued, 0\r
+/// otherwise); poll the ENDTX and TXBUFE bits of the USART status register\r
+/// to check for the transfer completion.\r
+/// \param usart Pointer to an USART peripheral.\r
+/// \param buffer Pointer to the data buffer to send.\r
+/// \param size Size of the data buffer (in bytes).\r
+//------------------------------------------------------------------------------\r
+unsigned char USART_WriteBuffer(\r
+ AT91S_USART *usart,\r
+ void *buffer,\r
+ unsigned int size)\r
+{\r
+ // Check if the first PDC bank is free\r
+ if ((usart->US_TCR == 0) && (usart->US_TNCR == 0)) {\r
+\r
+ usart->US_TPR = (unsigned int) buffer;\r
+ usart->US_TCR = size;\r
+ usart->US_PTCR = AT91C_PDC_TXTEN;\r
+\r
+ return 1;\r
+ }\r
+ // Check if the second PDC bank is free\r
+ else if (usart->US_TNCR == 0) {\r
+\r
+ usart->US_TNPR = (unsigned int) buffer;\r
+ usart->US_TNCR = size;\r
+\r
+ return 1;\r
+ }\r
+ else {\r
+\r
+ return 0;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Reads and return a packet of data on the specified USART peripheral. This\r
+/// function operates asynchronously, so it waits until some data has been\r
+/// received.\r
+/// \param usart Pointer to an USART peripheral.\r
+/// \param timeOut Time out value (0 -> no timeout).\r
+//------------------------------------------------------------------------------\r
+unsigned short USART_Read(\r
+ AT91S_USART *usart,\r
+ volatile unsigned int timeOut)\r
+{\r
+ if (timeOut == 0) {\r
+\r
+ while ((usart->US_CSR & AT91C_US_RXRDY) == 0);\r
+ }\r
+ else {\r
+\r
+ while ((usart->US_CSR & AT91C_US_RXRDY) == 0) {\r
+\r
+ if (timeOut == 0) {\r
+\r
+ trace_LOG(trace_ERROR, "-E- USART_Read: Timed out.\n\r");\r
+ return 0;\r
+ }\r
+ timeOut--;\r
+ }\r
+ }\r
+\r
+ return usart->US_RHR;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Reads data from an USART peripheral, filling the provided buffer until it\r
+/// becomes full. This function returns immediately with 1 if the buffer has\r
+/// been queued for transmission; otherwise 0.\r
+/// \param usart Pointer to an USART peripheral.\r
+/// \param buffer Pointer to the buffer where the received data will be stored.\r
+/// \param size Size of the data buffer (in bytes).\r
+//------------------------------------------------------------------------------\r
+unsigned char USART_ReadBuffer(AT91S_USART *usart,\r
+ void *buffer,\r
+ unsigned int size)\r
+{\r
+ // Check if the first PDC bank is free\r
+ if ((usart->US_RCR == 0) && (usart->US_RNCR == 0)) {\r
+\r
+ usart->US_RPR = (unsigned int) buffer;\r
+ usart->US_RCR = size;\r
+ usart->US_PTCR = AT91C_PDC_RXTEN;\r
+\r
+ return 1;\r
+ }\r
+ // Check if the second PDC bank is free\r
+ else if (usart->US_RNCR == 0) {\r
+\r
+ usart->US_RNPR = (unsigned int) buffer;\r
+ usart->US_RNCR = size;\r
+\r
+ return 1;\r
+ }\r
+ else {\r
+\r
+ return 0;\r
+ }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns 1 if some data has been received and can be read from an USART;\r
+/// otherwise returns 0.\r
+/// \param usart Pointer to an AT91S_USART instance.\r
+//------------------------------------------------------------------------------\r
+unsigned char USART_IsDataAvailable(AT91S_USART *usart)\r
+{\r
+ if ((usart->US_CSR & AT91C_US_RXRDY) != 0) {\r
+\r
+ return 1;\r
+ }\r
+ else {\r
+\r
+ return 0;\r
+ }\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \dir\r
+/// !Purpose\r
+/// \r
+/// This module provides several definitions and methods for using an USART\r
+/// peripheral.\r
+///\r
+/// !Usage\r
+/// -# Enable the USART peripheral clock in the PMC.\r
+/// -# Enable the required USART PIOs (see pio.h).\r
+/// -# Configure the UART by calling USART_Configure.\r
+/// -# Enable the transmitter and/or the receiver of the USART using\r
+/// USART_SetTransmitterEnabled and USART_SetReceiverEnabled.\r
+/// -# Send data through the USART using the USART_Write and\r
+/// USART_WriteBuffer methods.\r
+/// -# Receive data from the USART using the USART_Read and\r
+/// USART_ReadBuffer functions; the availability of data can be polled\r
+/// with USART_IsDataAvailable.\r
+/// -# Disable the transmitter and/or the receiver of the USART with\r
+/// USART_SetTransmitterEnabled and USART_SetReceiverEnabled.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef USART_H\r
+#define USART_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "USART modes"\r
+/// This page lists several common operating modes for an USART peripheral.\r
+/// \r
+/// !Modes\r
+/// - USART_MODE_ASYNCHRONOUS\r
+\r
+/// Basic asynchronous mode, i.e. 8 bits no parity.\r
+#define USART_MODE_ASYNCHRONOUS (AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE)\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void USART_Configure(\r
+ AT91S_USART *usart,\r
+ unsigned int mode,\r
+ unsigned int baudrate,\r
+ unsigned int masterClock);\r
+\r
+extern void USART_SetTransmitterEnabled(AT91S_USART *usart, unsigned char enabled);\r
+\r
+extern void USART_SetReceiverEnabled(AT91S_USART *usart, unsigned char enabled);\r
+\r
+extern void USART_Write(\r
+ AT91S_USART *usart, \r
+ unsigned short data, \r
+ volatile unsigned int timeOut);\r
+\r
+extern unsigned char USART_WriteBuffer(\r
+ AT91S_USART *usart,\r
+ void *buffer,\r
+ unsigned int size);\r
+\r
+extern unsigned short USART_Read(\r
+ AT91S_USART *usart, \r
+ volatile unsigned int timeOut);\r
+\r
+extern unsigned char USART_ReadBuffer(\r
+ AT91S_USART *usart,\r
+ void *buffer,\r
+ unsigned int size);\r
+\r
+extern unsigned char USART_IsDataAvailable(AT91S_USART *usart);\r
+\r
+#endif //#ifndef USART_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*\r
+ Title: Assert\r
+\r
+ About: Purpose\r
+ Definition of the ASSERT() macro, which is used for runtime condition\r
+ verifying.\r
+\r
+ About: Usage\r
+ 1 - Use <ASSERT> in your code to check the value of function parameters,\r
+ return values, etc. *Warning:* the ASSERT condition must not have\r
+ any side-effect; otherwise, the program may not work properly\r
+ anymore when assertions are disabled.\r
+ 2 - Use SANITY_CHECK to perform checks with a default error message\r
+ (outputs the file and line number where the error occured). This \r
+ reduces memory overhead caused by assertion error strings.\r
+ 3 - Initialize the <DBGU> to see failed assertions at run-time.\r
+ 4 - Disable assertions by defining the NOASSERT symbol at compilation\r
+ time.\r
+*/\r
+\r
+#ifndef ASSERT_H\r
+#define ASSERT_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <stdio.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+/*\r
+ Macro: ASSERT\r
+ Check that the given condition is true, otherwise displays an error\r
+ message and stops the program execution.\r
+\r
+ Parameters:\r
+ condition - Condition to verify.\r
+ string - Formatted string to output if the condition fails.\r
+ ... - Additional arguments depending on the formatted string.\r
+*/\r
+#if !defined(NOASSERT) && !defined(NOTRACE)\r
+\r
+ //char sanityError[] = "Sanity check failed at %s:%d\n\r";\r
+\r
+ #define ASSERT(condition, ...) { \\r
+ if (!(condition)) { \\r
+ printf(__VA_ARGS__); \\r
+ while (1); \\r
+ } \\r
+ }\r
+ #define SANITY_ERROR "Sanity check failed at %s:%d\n\r"\r
+ #define SANITY_CHECK(condition) ASSERT(condition, SANITY_ERROR, __FILE__, __LINE__)\r
+#else\r
+ #define ASSERT(...)\r
+ #define SANITY_CHECK(...)\r
+#endif\r
+\r
+#endif //#ifndef ASSERT_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*\r
+ Title: LED implementation\r
+\r
+ About: Purpose\r
+ Implementation of LED-related functionalities.\r
+*/\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "led.h"\r
+#include <board.h>\r
+#include <pio/pio.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Internal variables\r
+//------------------------------------------------------------------------------\r
+\r
+#ifdef PINS_LEDS\r
+static const Pin pinsLeds[] = {PINS_LEDS};\r
+static const unsigned int numLeds = PIO_LISTSIZE(pinsLeds);\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+/*\r
+ Function: LED_Configure\r
+ Configures the pin associated with the given LED number.\r
+\r
+ Parameters:\r
+ led - Number of the LED to configure.\r
+\r
+ Returns:\r
+ 1 if the LED exists and has been configured; otherwise 0.\r
+*/\r
+unsigned char LED_Configure(unsigned int led)\r
+{\r
+#ifdef PINS_LEDS\r
+ // Check that LED exists\r
+ if (led >= numLeds) {\r
+\r
+ return 0;\r
+ }\r
+\r
+ // Configure LED\r
+ return (PIO_Configure(&pinsLeds[led], 1));\r
+#else\r
+ return 0;\r
+#endif\r
+}\r
+\r
+/*\r
+ Function: LED_Set\r
+ Turns a LED on.\r
+\r
+ Parameters:\r
+ led - Number of the LED to turn on.\r
+\r
+ Returns:\r
+ 1 if the LED has been turned on; 0 otherwise.\r
+*/\r
+unsigned char LED_Set(unsigned int led)\r
+{\r
+#ifdef PINS_LEDS\r
+ // Check if LED exists\r
+ if (led >= numLeds) {\r
+\r
+ return 0;\r
+ }\r
+\r
+ // Turn LED on\r
+ if (pinsLeds[led].type == PIO_OUTPUT_0) {\r
+\r
+ PIO_Set(&pinsLeds[led]);\r
+ }\r
+ else {\r
+\r
+ PIO_Clear(&pinsLeds[led]);\r
+ }\r
+\r
+ return 1;\r
+#else\r
+ return 0;\r
+#endif\r
+}\r
+\r
+/*\r
+ Function: LED_Clear\r
+ Turns a LED off.\r
+\r
+ Parameters:\r
+ led - Number of the LED to turn off.\r
+\r
+ Returns:\r
+ 1 if the LED has been turned off; 0 otherwise.\r
+*/\r
+unsigned char LED_Clear(unsigned int led)\r
+{\r
+#ifdef PINS_LEDS\r
+ // Check if LED exists\r
+ if (led >= numLeds) {\r
+\r
+ return 0;\r
+ }\r
+\r
+ // Turn LED off\r
+ if (pinsLeds[led].type == PIO_OUTPUT_0) {\r
+\r
+ PIO_Clear(&pinsLeds[led]);\r
+ }\r
+ else {\r
+\r
+ PIO_Set(&pinsLeds[led]);\r
+ }\r
+\r
+ return 1;\r
+#else\r
+ return 0;\r
+#endif\r
+}\r
+\r
+/*\r
+ Function: LED_Toggle\r
+ Toggles the current state of a LED.\r
+\r
+ Parameters:\r
+ led - Number of the LED to toggle.\r
+\r
+ Returns:\r
+ 1 if the LED has been toggled; otherwise 0.\r
+*/\r
+unsigned char LED_Toggle(unsigned int led)\r
+{\r
+#ifdef PINS_LEDS\r
+ // Check if LED exists\r
+ if (led >= numLeds) {\r
+\r
+ return 0;\r
+ }\r
+\r
+ // Toggle LED\r
+ if (PIO_GetOutputDataStatus(&pinsLeds[led])) {\r
+\r
+ PIO_Clear(&pinsLeds[led]);\r
+ }\r
+ else {\r
+\r
+ PIO_Set(&pinsLeds[led]);\r
+ }\r
+\r
+ return 1;\r
+#else\r
+ return 0;\r
+#endif\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*\r
+ Title: LED\r
+\r
+ About: Purpose\r
+ Small set of functions for simple and portable LED usage.\r
+\r
+ About: Usage\r
+ 1 - Configure one or more LEDs using <LED_Configure> and\r
+ <LED_ConfigureAll>.\r
+ 2 - Set, clear and toggle LEDs using <LED_Set>, <LED_Clear> and\r
+ <LED_Toggle>.\r
+ 3 - Get the current status of a LED using <LED_Get>.\r
+\r
+ LEDs are numbered starting from 0; the number of LEDs depend on the\r
+ board being used. All the functions defined here will compile properly\r
+ regardless of whether the LED is defined or not; they will simply\r
+ return 0 when a LED which does not exist is given as an argument.\r
+ Also, these functions take into account how each LED is connected on to\r
+ board; thus, <LED_Set> might change the level on the corresponding pin\r
+ to 0 or 1, but it will always light the LED on; same thing for the other\r
+ methods.\r
+*/\r
+\r
+#ifndef LED_H\r
+#define LED_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern unsigned char LED_Configure(unsigned int led);\r
+extern unsigned char LED_Set(unsigned int led);\r
+extern unsigned char LED_Clear(unsigned int led);\r
+extern unsigned char LED_Toggle(unsigned int led);\r
+\r
+#endif //#ifndef LED_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*\r
+ Title: Trace\r
+\r
+ About: Purpose\r
+ Standard output methods for reporting debug information, warnings and\r
+ errors, which can be turned on/off.\r
+\r
+ About: Usage\r
+ 1 - Initialize the DBGU using <trace_CONFIGURE>.\r
+ 2 - Uses the <trace_LOG> macro to output traces throughout the program.\r
+ 3 - Turn off all traces by defining the NOTRACE symbol during\r
+ compilation.\r
+ 4 - Disable a group of trace by changing the value of <trace_LEVEL>\r
+ during compilation; traces with a level below <trace_LEVEL> are not\r
+ generated.\r
+*/\r
+\r
+#ifndef TRACE_H\r
+#define TRACE_H\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#if !defined(NOTRACE)\r
+ #include <board.h>\r
+ #include <dbgu/dbgu.h>\r
+ #include <pio/pio.h>\r
+ #include <stdio.h>\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+/*\r
+ Constants: Trace levels\r
+ trace_FATAL - Indicates a major error which prevents the program from\r
+ going any further.\r
+ trace_ERROR - Indicates an error which may not stop the program\r
+ execution, but which indicates there is a problem with the code.\r
+ trace_WARNING - Indicates that a minor error has happened. In most case\r
+ it can be discarded safely; it may even be expected.\r
+ trace_INFO - Informational trace about the program execution. Should\r
+ enable the user to see the execution flow.\r
+ trace_DEBUG - Traces whose only purpose is for debugging the program,\r
+ and which do not produce meaningful information otherwise.\r
+*/\r
+#define trace_DEBUG 0\r
+#define trace_INFO 1\r
+#define trace_WARNING 2\r
+#define trace_ERROR 3\r
+#define trace_FATAL 4\r
+\r
+/*\r
+ Constant: trace_LEVEL\r
+ Minimum level of traces that are output. By default, all traces are\r
+ output; change the value of this symbol during compilation for a more\r
+ restrictive behavior.\r
+*/\r
+#if !defined(trace_LEVEL)\r
+ #define trace_LEVEL 0\r
+#endif\r
+\r
+/*\r
+ Macro: trace_CONFIGURE\r
+ Initializes the DBGU unless the NOTRACE symbol has been defined.\r
+\r
+ Parameters:\r
+ mode - DBGU mode.\r
+ baudrate - DBGU baudrate.\r
+ mck - Master clock frequency.\r
+*/\r
+#if !defined(NOTRACE)\r
+ #define trace_CONFIGURE(mode, baudrate, mck) { \\r
+ const Pin pinsDbgu[] = {PINS_DBGU}; \\r
+ PIO_Configure(pinsDbgu, PIO_LISTSIZE(pinsDbgu)); \\r
+ DBGU_Configure(mode, baudrate, mck); \\r
+ }\r
+#else\r
+ #define trace_CONFIGURE(...)\r
+#endif\r
+\r
+/*\r
+ Macro: trace_LOG\r
+ Outputs a formatted string using <printf> if the log level is high\r
+ enough. Can be disabled by defining the NOTRACE symbol during\r
+ compilation.\r
+\r
+ Parameters:\r
+ level - Trace level (see <Trace levels>).\r
+ format - Formatted string to output.\r
+ ... - Additional parameters, depending on the formatted string.\r
+*/\r
+#if !defined(NOTRACE)\r
+ #define trace_LOG(level, ...) { \\r
+ if (level >= trace_LEVEL) { \\r
+ printf(__VA_ARGS__); \\r
+ } \\r
+ }\r
+#else\r
+ #define trace_LOG(...)\r
+#endif\r
+\r
+#endif //#ifndef TRACE_H\r
+\r
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