--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * SmartFusion A2FxxxM3 Cortex Microcontroller Software Interface - Peripheral\r
+ * Access Layer.\r
+ *\r
+ * This file describes the interrupt assignment and peripheral registers for\r
+ * the SmartFusion A2FxxxM3 familly of devices. \r
+ *\r
+ * SVN $Revision: 2331 $\r
+ * SVN $Date: 2010-02-26 12:02:06 +0000 (Fri, 26 Feb 2010) $\r
+ */\r
+#ifndef __A2FXXXM3_H__\r
+#define __A2FXXXM3_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/*\r
+ * ==========================================================================\r
+ * ---------- Interrupt Number Definition -----------------------------------\r
+ * ==========================================================================\r
+ */\r
+\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers *********************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /*!< 2 Hard Fault Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
+\r
+/****** SmartFusion specific Interrupt Numbers *********************************************************/\r
+ WdogWakeup_IRQn = 0, /*!< WatchDog wakeup interrupt */\r
+ BrownOut_1_5V_IRQn = 1, /*!< Supply dropped below 1.5V */\r
+ BrownOut_3_3V_IRQn = 2, /*!< Supply dropped below 1.5V */\r
+ RTC_Match_IRQn = 3, /*!< RTC match interrupt */\r
+ RTCIF_Pub_IRQn = 4, /*!< RTC interface push button interrupt */\r
+ EthernetMAC_IRQn = 5, /*!< Ethernet MAC interrupt */\r
+ IAP_IRQn = 6, /*!< In Application Programming (IAP) interrupt */\r
+ ENVM0_IRQn = 7, /*!< eNVM0 operation completion interrupt */\r
+ ENVM1_IRQn = 8, /*!< eNVM1 operation completion interrupt */\r
+ DMA_IRQn = 9, /*!< Peripheral DMA interrupt */\r
+ UART0_IRQn = 10, /*!< UART0 interrupt */\r
+ UART1_IRQn = 11, /*!< UART1 interrupt */\r
+ SPI0_IRQn = 12, /*!< SPI0 interrupt */\r
+ SPI1_IRQn = 13, /*!< SP1 interrupt */\r
+ I2C0_IRQn = 14, /*!< I2C0 interrupt */\r
+ I2C0_SMBAlert_IRQn = 15, /*!< I2C0 SMBus Alert interrupt */\r
+ I2C0_SMBus_IRQn = 16, /*!< I2C0 SMBus Suspend interrupt */\r
+ I2C1_IRQn = 17, /*!< I2C1 interrupt */\r
+ I2C1_SMBAlert_IRQn = 18, /*!< I2C1 SMBus Alert interrupt */\r
+ I2C1_SMBus_IRQn = 19, /*!< I2C1 SMBus Suspend interrupt */\r
+ Timer1_IRQn = 20, /*!< Timer1 interrupt */\r
+ Timer2_IRQn = 21, /*!< Timer2 interrupt */\r
+ PLL_Lock_IRQn = 22, /*!< PLL lock interrupt */\r
+ PLL_LockLost_IRQn = 23, /*!< PLL loss of lock interrupt */\r
+ CommError_IRQn = 24, /*!< Communications Matrix error interrupt */\r
+ Fabric_IRQn = 31, /*!< FPGA fabric interrupt */\r
+ GPIO0_IRQn = 32, /*!< GPIO 0 interrupt */\r
+ GPIO1_IRQn = 33, /*!< GPIO 1 interrupt */\r
+ GPIO2_IRQn = 34, /*!< GPIO 2 interrupt */\r
+ GPIO3_IRQn = 35, /*!< GPIO 3 interrupt */\r
+ GPIO4_IRQn = 36, /*!< GPIO 4 interrupt */\r
+ GPIO5_IRQn = 37, /*!< GPIO 5 interrupt */\r
+ GPIO6_IRQn = 38, /*!< GPIO 6 interrupt */\r
+ GPIO7_IRQn = 39, /*!< GPIO 7 interrupt */\r
+ GPIO8_IRQn = 40, /*!< GPIO 8 interrupt */\r
+ GPIO9_IRQn = 41, /*!< GPIO 9 interrupt */\r
+ GPIO10_IRQn = 42, /*!< GPIO 10 interrupt */\r
+ GPIO11_IRQn = 43, /*!< GPIO 11 interrupt */\r
+ GPIO12_IRQn = 44, /*!< GPIO 12 interrupt */\r
+ GPIO13_IRQn = 45, /*!< GPIO 13 interrupt */\r
+ GPIO14_IRQn = 46, /*!< GPIO 14 interrupt */\r
+ GPIO15_IRQn = 47, /*!< GPIO 15 interrupt */\r
+ GPIO16_IRQn = 48, /*!< GPIO 16 interrupt */\r
+ GPIO17_IRQn = 49, /*!< GPIO 17 interrupt */\r
+ GPIO18_IRQn = 50, /*!< GPIO 18 interrupt */\r
+ GPIO19_IRQn = 51, /*!< GPIO 19 interrupt */\r
+ GPIO20_IRQn = 52, /*!< GPIO 20 interrupt */\r
+ GPIO21_IRQn = 53, /*!< GPIO 21 interrupt */\r
+ GPIO22_IRQn = 54, /*!< GPIO 22 interrupt */\r
+ GPIO23_IRQn = 55, /*!< GPIO 23 interrupt */\r
+ GPIO24_IRQn = 56, /*!< GPIO 24 interrupt */\r
+ GPIO25_IRQn = 57, /*!< GPIO 25 interrupt */\r
+ GPIO26_IRQn = 58, /*!< GPIO 26 interrupt */\r
+ GPIO27_IRQn = 59, /*!< GPIO 27 interrupt */\r
+ GPIO28_IRQn = 60, /*!< GPIO 28 interrupt */\r
+ GPIO29_IRQn = 61, /*!< GPIO 29 interrupt */\r
+ GPIO30_IRQn = 62, /*!< GPIO 30 interrupt */\r
+ GPIO31_IRQn = 63, /*!< GPIO 31 interrupt */\r
+ ACE_PC0_Flag0_IRQn = 64, /*!< ACE SSE program counter 0 flag 0 interrupt */\r
+ ACE_PC0_Flag1_IRQn = 65, /*!< ACE SSE program counter 0 flag 1 interrupt */\r
+ ACE_PC0_Flag2_IRQn = 66, /*!< ACE SSE program counter 0 flag 2 interrupt */\r
+ ACE_PC0_Flag3_IRQn = 67, /*!< ACE SSE program counter 0 flag 3 interrupt */\r
+ ACE_PC1_Flag0_IRQn = 68, /*!< ACE SSE program counter 1 flag 0 interrupt */\r
+ ACE_PC1_Flag1_IRQn = 69, /*!< ACE SSE program counter 1 flag 1 interrupt */\r
+ ACE_PC1_Flag2_IRQn = 70, /*!< ACE SSE program counter 1 flag 2 interrupt */\r
+ ACE_PC1_Flag3_IRQn = 71, /*!< ACE SSE program counter 1 flag 3 interrupt */\r
+ ACE_PC2_Flag0_IRQn = 72, /*!< ACE SSE program counter 2 flag 0 interrupt */\r
+ ACE_PC2_Flag1_IRQn = 73, /*!< ACE SSE program counter 2 flag 1 interrupt */\r
+ ACE_PC2_Flag2_IRQn = 74, /*!< ACE SSE program counter 2 flag 2 interrupt */\r
+ ACE_PC2_Flag3_IRQn = 75, /*!< ACE SSE program counter 2 flag 3 interrupt */\r
+ ACE_ADC0_DataValid_IRQn = 76, /*!< ACE ADC0 data valid interrupt */\r
+ ACE_ADC1_DataValid_IRQn = 77, /*!< ACE ADC1 data valid interrupt */\r
+ ACE_ADC2_DataValid_IRQn = 78, /*!< ACE ADC2 data valid interrupt */\r
+ ACE_ADC0_CalDone_IRQn = 79, /*!< ACE ADC0 calibration done interrupt */\r
+ ACE_ADC1_CalDone_IRQn = 80, /*!< ACE ADC1 calibration done interrupt */\r
+ ACE_ADC2_CalDone_IRQn = 81, /*!< ACE ADC2 calibration done interrupt */\r
+ ACE_ADC0_CalStart_IRQn = 82, /*!< ACE ADC0 calibration start interrupt */\r
+ ACE_ADC1_CalStart_IRQn = 83, /*!< ACE ADC1 calibration start interrupt */\r
+ ACE_ADC2_CalStart_IRQn = 84, /*!< ACE ADC2 calibration start interrupt */\r
+ ACE_Comp0_Fall_IRQn = 85, /*!< ACE comparator 0 falling under reference interrupt */\r
+ ACE_Comp1_Fall_IRQn = 86, /*!< ACE comparator 1 falling under reference interrupt */\r
+ ACE_Comp2_Fall_IRQn = 87, /*!< ACE comparator 2 falling under reference interrupt */\r
+ ACE_Comp3_Fall_IRQn = 88, /*!< ACE comparator 3 falling under reference interrupt */\r
+ ACE_Comp4_Fall_IRQn = 89, /*!< ACE comparator 4 falling under reference interrupt */\r
+ ACE_Comp5_Fall_IRQn = 90, /*!< ACE comparator 5 falling under reference interrupt */\r
+ ACE_Comp6_Fall_IRQn = 91, /*!< ACE comparator 6 falling under reference interrupt */\r
+ ACE_Comp7_Fall_IRQn = 92, /*!< ACE comparator 7 falling under reference interrupt */\r
+ ACE_Comp8_Fall_IRQn = 93, /*!< ACE comparator 8 falling under reference interrupt */\r
+ ACE_Comp9_Fall_IRQn = 94, /*!< ACE comparator 9 falling under reference interrupt */\r
+ ACE_Comp10_Fall_IRQn = 95, /*!< ACE comparator 10 falling under reference interrupt */\r
+ ACE_Comp11_Fall_IRQn = 96, /*!< ACE comparator 11 falling under reference interrupt */\r
+ ACE_Comp0_Rise_IRQn = 97, /*!< ACE comparator 0 rising over reference interrupt */\r
+ ACE_Comp1_Rise_IRQn = 98, /*!< ACE comparator 1 rising over reference interrupt */\r
+ ACE_Comp2_Rise_IRQn = 99, /*!< ACE comparator 2 rising over reference interrupt */\r
+ ACE_Comp3_Rise_IRQn = 100, /*!< ACE comparator 3 rising over reference interrupt */\r
+ ACE_Comp4_Rise_IRQn = 101, /*!< ACE comparator 4 rising over reference interrupt */\r
+ ACE_Comp5_Rise_IRQn = 102, /*!< ACE comparator 5 rising over reference interrupt */\r
+ ACE_Comp6_Rise_IRQn = 103, /*!< ACE comparator 6 rising over reference interrupt */\r
+ ACE_Comp7_Rise_IRQn = 104, /*!< ACE comparator 7 rising over reference interrupt */\r
+ ACE_Comp8_Rise_IRQn = 105, /*!< ACE comparator 8 rising over reference interrupt */\r
+ ACE_Comp9_Rise_IRQn = 106, /*!< ACE comparator 9 rising over reference interrupt */\r
+ ACE_Comp10_Rise_IRQn = 107, /*!< ACE comparator 10 rising over reference interrupt */\r
+ ACE_Comp11_Rise_IRQn = 108, /*!< ACE comparator 11 rising over reference interrupt */\r
+ ACE_ADC0_FifoFull_IRQn = 109, /*!< ACE ADC0 FIFO full interrupt */\r
+ ACE_ADC0_FifoAFull_IRQn = 110, /*!< ACE ADC0 FIFO almost full interrupt */\r
+ ACE_ADC0_FifoEmpty_IRQn = 111, /*!< ACE ADC0 FIFO empty interrupt */\r
+ ACE_ADC1_FifoFull_IRQn = 112, /*!< ACE ADC1 FIFO full interrupt */\r
+ ACE_ADC1_FifoAFull_IRQn = 113, /*!< ACE ADC1 FIFO almost full interrupt */\r
+ ACE_ADC1_FifoEmpty_IRQn = 114, /*!< ACE ADC1 FIFO empty interrupt */\r
+ ACE_ADC2_FifoFull_IRQn = 115, /*!< ACE ADC2 FIFO full interrupt */\r
+ ACE_ADC2_FifoAFull_IRQn = 116, /*!< ACE ADC2 FIFO almost full interrupt */\r
+ ACE_ADC2_FifoEmpty_IRQn = 117, /*!< ACE ADC2 FIFO empty interrupt */\r
+ ACE_PPE_Flag0_IRQn = 118, /*!< ACE post processing engine flag 0 interrupt */\r
+ ACE_PPE_Flag1_IRQn = 119, /*!< ACE post processing engine flag 1 interrupt */\r
+ ACE_PPE_Flag2_IRQn = 120, /*!< ACE post processing engine flag 2 interrupt */\r
+ ACE_PPE_Flag3_IRQn = 121, /*!< ACE post processing engine flag 3 interrupt */\r
+ ACE_PPE_Flag4_IRQn = 122, /*!< ACE post processing engine flag 4 interrupt */\r
+ ACE_PPE_Flag5_IRQn = 123, /*!< ACE post processing engine flag 5 interrupt */\r
+ ACE_PPE_Flag6_IRQn = 124, /*!< ACE post processing engine flag 6 interrupt */\r
+ ACE_PPE_Flag7_IRQn = 125, /*!< ACE post processing engine flag 7 interrupt */\r
+ ACE_PPE_Flag8_IRQn = 126, /*!< ACE post processing engine flag 8 interrupt */\r
+ ACE_PPE_Flag9_IRQn = 127, /*!< ACE post processing engine flag 9 interrupt */\r
+ ACE_PPE_Flag10_IRQn = 128, /*!< ACE post processing engine flag 10 interrupt */\r
+ ACE_PPE_Flag11_IRQn = 129, /*!< ACE post processing engine flag 11 interrupt */\r
+ ACE_PPE_Flag12_IRQn = 130, /*!< ACE post processing engine flag 12 interrupt */\r
+ ACE_PPE_Flag13_IRQn = 131, /*!< ACE post processing engine flag 13 interrupt */\r
+ ACE_PPE_Flag14_IRQn = 132, /*!< ACE post processing engine flag 14 interrupt */\r
+ ACE_PPE_Flag15_IRQn = 133, /*!< ACE post processing engine flag 15 interrupt */\r
+ ACE_PPE_Flag16_IRQn = 134, /*!< ACE post processing engine flag 16 interrupt */\r
+ ACE_PPE_Flag17_IRQn = 135, /*!< ACE post processing engine flag 17 interrupt */\r
+ ACE_PPE_Flag18_IRQn = 136, /*!< ACE post processing engine flag 18 interrupt */\r
+ ACE_PPE_Flag19_IRQn = 137, /*!< ACE post processing engine flag 19 interrupt */\r
+ ACE_PPE_Flag20_IRQn = 138, /*!< ACE post processing engine flag 20 interrupt */\r
+ ACE_PPE_Flag21_IRQn = 139, /*!< ACE post processing engine flag 21 interrupt */\r
+ ACE_PPE_Flag22_IRQn = 140, /*!< ACE post processing engine flag 22 interrupt */\r
+ ACE_PPE_Flag23_IRQn = 141, /*!< ACE post processing engine flag 23 interrupt */\r
+ ACE_PPE_Flag24_IRQn = 142, /*!< ACE post processing engine flag 24 interrupt */\r
+ ACE_PPE_Flag25_IRQn = 143, /*!< ACE post processing engine flag 25 interrupt */\r
+ ACE_PPE_Flag26_IRQn = 144, /*!< ACE post processing engine flag 26 interrupt */\r
+ ACE_PPE_Flag27_IRQn = 145, /*!< ACE post processing engine flag 27 interrupt */\r
+ ACE_PPE_Flag28_IRQn = 146, /*!< ACE post processing engine flag 28 interrupt */\r
+ ACE_PPE_Flag29_IRQn = 147, /*!< ACE post processing engine flag 29 interrupt */\r
+ ACE_PPE_Flag30_IRQn = 148, /*!< ACE post processing engine flag 30 interrupt */\r
+ ACE_PPE_Flag31_IRQn = 149 /*!< ACE post processing engine flag 31 interrupt */\r
+} IRQn_Type;\r
+\r
+\r
+/*\r
+ * ==========================================================================\r
+ * ----------- Processor and Core Peripheral Section ------------------------\r
+ * ==========================================================================\r
+ */\r
+\r
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */\r
+#define __MPU_PRESENT 1 /*!< SmartFusion includes a MPU */\r
+#define __NVIC_PRIO_BITS 5 /*!< SmartFusion uses 5 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+\r
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
+#include "system_a2fxxxm3.h" /* SmartFusion System */\r
+\r
+/******************************************************************************/\r
+/* Device Specific Peripheral registers structures */\r
+/******************************************************************************/\r
+#if defined ( __CC_ARM )\r
+ /* Enable anonymous unions when building using Keil-MDK */\r
+ #pragma anon_unions\r
+#endif\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------------- UART -----------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ union\r
+ {\r
+ __I uint8_t RBR;\r
+ __O uint8_t THR;\r
+ __IO uint8_t DLR;\r
+ uint32_t RESERVED0;\r
+ };\r
+\r
+ union\r
+ {\r
+ __IO uint8_t DMR;\r
+ __IO uint8_t IER;\r
+ uint32_t RESERVED1;\r
+ };\r
+\r
+ union\r
+ {\r
+ __IO uint8_t IIR;\r
+ __IO uint8_t FCR;\r
+ uint32_t RESERVED2;\r
+ }; \r
+\r
+ __IO uint8_t LCR;\r
+ uint8_t RESERVED3;\r
+ uint16_t RESERVED4;\r
+ __IO uint8_t MCR;\r
+ uint8_t RESERVED5;\r
+ uint16_t RESERVED6;\r
+ __I uint8_t LSR;\r
+ uint8_t RESERVED7;\r
+ uint16_t RESERVED8;\r
+ __I uint8_t MSR;\r
+ uint8_t RESERVED9;\r
+ uint16_t RESERVED10;\r
+ __IO uint8_t SR;\r
+ uint8_t RESERVED11;\r
+ uint16_t RESERVED12;\r
+} UART_TypeDef;\r
+\r
+/*------------------------------------------------------------------------------\r
+ *\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[32];\r
+ \r
+ __IO uint32_t IER_ERBFI;\r
+ __IO uint32_t IER_ETBEI;\r
+ __IO uint32_t IER_ELSI;\r
+ __IO uint32_t IER_EDSSI;\r
+ \r
+ uint32_t RESERVED1[28];\r
+ \r
+ __IO uint32_t FCR_ENABLE;\r
+ __IO uint32_t FCR_CLEAR_RX_FIFO;\r
+ __IO uint32_t FCR_CLEAR_TX_FIFO;\r
+ __IO uint32_t FCR_RXRDY_TXRDYN_EN;\r
+ __IO uint32_t FCR_RESERVED0;\r
+ __IO uint32_t FCR_RESERVED1;\r
+ __IO uint32_t FCR_RX_TRIG0;\r
+ __IO uint32_t FCR_RX_TRIG1;\r
+ \r
+ uint32_t RESERVED2[24];\r
+ \r
+ __IO uint32_t LCR_WLS0;\r
+ __IO uint32_t LCR_WLS1;\r
+ __IO uint32_t LCR_STB;\r
+ __IO uint32_t LCR_PEN;\r
+ __IO uint32_t LCR_EPS;\r
+ __IO uint32_t LCR_SP;\r
+ __IO uint32_t LCR_SB;\r
+ __IO uint32_t LCR_DLAB;\r
+ \r
+ uint32_t RESERVED3[24];\r
+ \r
+ __IO uint32_t MCR_DTR;\r
+ __IO uint32_t MCR_RTS;\r
+ __IO uint32_t MCR_OUT1;\r
+ __IO uint32_t MCR_OUT2;\r
+ __IO uint32_t MCR_LOOP;\r
+ \r
+ uint32_t RESERVED4[27];\r
+ \r
+ __I uint32_t LSR_DR;\r
+ __I uint32_t LSR_OE;\r
+ __I uint32_t LSR_PE;\r
+ __I uint32_t LSR_FE;\r
+ __I uint32_t LSR_BI;\r
+ __I uint32_t LSR_THRE;\r
+ __I uint32_t LSR_TEMT;\r
+ __I uint32_t LSR_FIER;\r
+ \r
+ uint32_t RESERVED5[24];\r
+ \r
+ __I uint32_t MSR_DCTS;\r
+ __I uint32_t MSR_DDSR;\r
+ __I uint32_t MSR_TERI;\r
+ __I uint32_t MSR_DDCD;\r
+ __I uint32_t MSR_CTS;\r
+ __I uint32_t MSR_DSR;\r
+ __I uint32_t MSR_RI;\r
+ __I uint32_t MSR_DCD;\r
+ \r
+} UART_BitBand_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------------- I2C ------------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint8_t CTRL;\r
+ uint8_t RESERVED0;\r
+ uint16_t RESERVED1;\r
+ uint8_t STATUS;\r
+ uint8_t RESERVED2;\r
+ uint16_t RESERVED3;\r
+ __IO uint8_t DATA;\r
+ uint8_t RESERVED4;\r
+ uint16_t RESERVED5;\r
+ __IO uint8_t ADDR;\r
+ uint8_t RESERVED6;\r
+ uint16_t RESERVED7;\r
+ __IO uint8_t SMBUS;\r
+ uint8_t RESERVED8;\r
+ uint16_t RESERVED9;\r
+ __IO uint8_t FREQ;\r
+ uint8_t RESERVED10;\r
+ uint16_t RESERVED11;\r
+ __IO uint8_t GLITCHREG;\r
+ uint8_t RESERVED12;\r
+ uint16_t RESERVED13;\r
+} I2C_TypeDef;\r
+\r
+/*------------------------------------------------------------------------------\r
+ *\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t CTRL_CR0;\r
+ uint32_t CTRL_CR1;\r
+ uint32_t CTRL_AA;\r
+ uint32_t CTRL_SI;\r
+ uint32_t CTRL_STO;\r
+ uint32_t CTRL_STA;\r
+ uint32_t CTRL_ENS1;\r
+ uint32_t CTRL_CR2;\r
+ uint32_t RESERVED0[56];\r
+ uint32_t DATA_DIR;\r
+ uint32_t RESERVED1[31];\r
+ uint32_t ADDR_GC;\r
+} I2C_BitBand_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------------- SPI ------------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t CONTROL;\r
+ __IO uint32_t TXRXDF_SIZE;\r
+ __I uint32_t STATUS;\r
+ __O uint32_t INT_CLEAR;\r
+ __I uint32_t RX_DATA;\r
+ __O uint32_t TX_DATA;\r
+ __IO uint32_t CLK_GEN;\r
+ __IO uint32_t SLAVE_SELECT;\r
+ __I uint32_t MIS;\r
+ __I uint32_t RIS;\r
+} SPI_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL_ENABLE;\r
+ __IO uint32_t CTRL_MASTER;\r
+ __IO uint32_t CTRL_MODE[2];\r
+ __IO uint32_t CTRL_RX_INT_EN;\r
+ __IO uint32_t CTRL_TX_INT_EN;\r
+ __IO uint32_t CTRL_RX_OVERFLOW_INT_EN;\r
+ __IO uint32_t CTRL_TX_UNDERRUN_INT_EN;\r
+ __IO uint32_t CTRL_TXRXDFCOUNT[16];\r
+ __IO uint32_t CTRL_SPO;\r
+ __IO uint32_t CTRL_SPH;\r
+ __IO uint32_t CTRL_RESERVED[6];\r
+ \r
+ __IO uint32_t TXRXDF_SIZE[32];\r
+ \r
+ __I uint32_t STATUS_TX_DONE;\r
+ __I uint32_t STATUS_RX_RDY;\r
+ __I uint32_t STATUS_RX_CH_OV;\r
+ __I uint32_t STATUS_TX_CH_UV;\r
+ __I uint32_t STATUS_RX_FIFO_FULL;\r
+ __I uint32_t STATUS_RX_FIFO_FULL_NEXT;\r
+ __I uint32_t STATUS_RX_FIFO_EMPTY;\r
+ __I uint32_t STATUS_RX_FIFO_EMPTY_NEXT;\r
+ __I uint32_t STATUS_TX_FIFO_FULL;\r
+ __I uint32_t STATUS_TX_FIFO_FULL_NEXT;\r
+ __I uint32_t STATUS_TX_FIFO_EMPTY;\r
+ __I uint32_t STATUS_TX_FIFO_EMPTY_NEXT;\r
+ __I uint32_t STATUS_RESERVED[20];\r
+ \r
+ __O uint32_t INT_CLEAR_TX_DONE;\r
+ __O uint32_t INT_CLEAR_RX_RDY;\r
+ __O uint32_t INT_CLEAR_RX_OVER;\r
+ __O uint32_t INT_CLEAR_TX_UNDER;\r
+ __O uint32_t INT_CLEAR[28];\r
+ \r
+ __I uint32_t RX_DATA[32];\r
+ __O uint32_t TX_DATA[32];\r
+ __IO uint32_t CLK_GEN[32];\r
+ __IO uint32_t SLAVE_SELECT[32];\r
+ __I uint32_t MIS_TX_DONE;\r
+ __I uint32_t MIS_RX_RDY;\r
+ __I uint32_t MIS_RX_OVER;\r
+ __I uint32_t MIS_TX_UNDER;\r
+ __I uint32_t MIS[28];\r
+ __I uint32_t RIS[32];\r
+} SPI_BitBand_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------------- GPIO -----------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t GPIO_0_CFG;\r
+ __IO uint32_t GPIO_1_CFG;\r
+ __IO uint32_t GPIO_2_CFG;\r
+ __IO uint32_t GPIO_3_CFG;\r
+ __IO uint32_t GPIO_4_CFG;\r
+ __IO uint32_t GPIO_5_CFG;\r
+ __IO uint32_t GPIO_6_CFG;\r
+ __IO uint32_t GPIO_7_CFG;\r
+ __IO uint32_t GPIO_8_CFG;\r
+ __IO uint32_t GPIO_9_CFG;\r
+ __IO uint32_t GPIO_10_CFG;\r
+ __IO uint32_t GPIO_11_CFG;\r
+ __IO uint32_t GPIO_12_CFG;\r
+ __IO uint32_t GPIO_13_CFG;\r
+ __IO uint32_t GPIO_14_CFG;\r
+ __IO uint32_t GPIO_15_CFG;\r
+ __IO uint32_t GPIO_16_CFG;\r
+ __IO uint32_t GPIO_17_CFG;\r
+ __IO uint32_t GPIO_18_CFG;\r
+ __IO uint32_t GPIO_19_CFG;\r
+ __IO uint32_t GPIO_20_CFG;\r
+ __IO uint32_t GPIO_21_CFG;\r
+ __IO uint32_t GPIO_22_CFG;\r
+ __IO uint32_t GPIO_23_CFG;\r
+ __IO uint32_t GPIO_24_CFG;\r
+ __IO uint32_t GPIO_25_CFG;\r
+ __IO uint32_t GPIO_26_CFG;\r
+ __IO uint32_t GPIO_27_CFG;\r
+ __IO uint32_t GPIO_28_CFG;\r
+ __IO uint32_t GPIO_29_CFG;\r
+ __IO uint32_t GPIO_30_CFG;\r
+ __IO uint32_t GPIO_31_CFG;\r
+ __IO uint32_t GPIO_IRQ;\r
+ __I uint32_t GPIO_IN;\r
+ __IO uint32_t GPIO_OUT;\r
+} GPIO_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t GPIO_0_CFG[32];\r
+ __IO uint32_t GPIO_1_CFG[32];\r
+ __IO uint32_t GPIO_2_CFG[32];\r
+ __IO uint32_t GPIO_3_CFG[32];\r
+ __IO uint32_t GPIO_4_CFG[32];\r
+ __IO uint32_t GPIO_5_CFG[32];\r
+ __IO uint32_t GPIO_6_CFG[32];\r
+ __IO uint32_t GPIO_7_CFG[32];\r
+ __IO uint32_t GPIO_8_CFG[32];\r
+ __IO uint32_t GPIO_9_CFG[32];\r
+ __IO uint32_t GPIO_10_CFG[32];\r
+ __IO uint32_t GPIO_11_CFG[32];\r
+ __IO uint32_t GPIO_12_CFG[32];\r
+ __IO uint32_t GPIO_13_CFG[32];\r
+ __IO uint32_t GPIO_14_CFG[32];\r
+ __IO uint32_t GPIO_15_CFG[32];\r
+ __IO uint32_t GPIO_16_CFG[32];\r
+ __IO uint32_t GPIO_17_CFG[32];\r
+ __IO uint32_t GPIO_18_CFG[32];\r
+ __IO uint32_t GPIO_19_CFG[32];\r
+ __IO uint32_t GPIO_20_CFG[32];\r
+ __IO uint32_t GPIO_21_CFG[32];\r
+ __IO uint32_t GPIO_22_CFG[32];\r
+ __IO uint32_t GPIO_23_CFG[32];\r
+ __IO uint32_t GPIO_24_CFG[32];\r
+ __IO uint32_t GPIO_25_CFG[32];\r
+ __IO uint32_t GPIO_26_CFG[32];\r
+ __IO uint32_t GPIO_27_CFG[32];\r
+ __IO uint32_t GPIO_28_CFG[32];\r
+ __IO uint32_t GPIO_29_CFG[32];\r
+ __IO uint32_t GPIO_30_CFG[32];\r
+ __IO uint32_t GPIO_31_CFG[32];\r
+ __IO uint32_t GPIO_IRQ[32];\r
+ __I uint32_t GPIO_IN[32];\r
+ __IO uint32_t GPIO_OUT[32];\r
+} GPIO_BitBand_TypeDef;\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------------- RTC ------------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t COUNTER0_REG;\r
+ __IO uint32_t COUNTER1_REG;\r
+ __IO uint32_t COUNTER2_REG;\r
+ __IO uint32_t COUNTER3_REG;\r
+ __IO uint32_t COUNTER4_REG;\r
+\r
+ __IO uint32_t RESERVED0[3];\r
+ \r
+ __IO uint32_t MATCHREG0_REG;\r
+ __IO uint32_t MATCHREG1_REG;\r
+ __IO uint32_t MATCHREG2_REG;\r
+ __IO uint32_t MATCHREG3_REG;\r
+ __IO uint32_t MATCHREG4_REG;\r
+\r
+ __IO uint32_t RESERVED1[3];\r
+ \r
+ __IO uint32_t MATCHBITS0_REG;\r
+ __IO uint32_t MATCHBITS1_REG;\r
+ __IO uint32_t MATCHBITS2_REG;\r
+ __IO uint32_t MATCHBITS3_REG;\r
+ __IO uint32_t MATCHBITS4_REG;\r
+\r
+ __IO uint32_t RESERVED2[3];\r
+ \r
+ __IO uint32_t CTRL_STAT_REG;\r
+} RTC_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*---------------------------------- Timer -----------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __I uint32_t TIM1_VAL;\r
+ __IO uint32_t TIM1_LOADVAL;\r
+ __IO uint32_t TIM1_BGLOADVAL;\r
+ __IO uint32_t TIM1_CTRL;\r
+ __IO uint32_t TIM1_RIS;\r
+ __I uint32_t TIM1_MIS;\r
+ \r
+ __I uint32_t TIM2_VAL;\r
+ __IO uint32_t TIM2_LOADVAL;\r
+ __IO uint32_t TIM2_BGLOADVAL;\r
+ __IO uint32_t TIM2_CTRL;\r
+ __IO uint32_t TIM2_RIS;\r
+ __I uint32_t TIM2_MIS;\r
+ \r
+ __I uint32_t TIM64_VAL_U;\r
+ __I uint32_t TIM64_VAL_L;\r
+ __IO uint32_t TIM64_LOADVAL_U;\r
+ __IO uint32_t TIM64_LOADVAL_L;\r
+ __IO uint32_t TIM64_BGLOADVAL_U;\r
+ __IO uint32_t TIM64_BGLOADVAL_L;\r
+ __IO uint32_t TIM64_CTRL;\r
+ __IO uint32_t TIM64_RIS;\r
+ __I uint32_t TIM64_MIS;\r
+ __IO uint32_t TIM64_MODE;\r
+} TIMER_TypeDef;\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Timer bit band\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TIM1_VALUE_BIT[32];\r
+ __IO uint32_t TIM1_LOADVAL[32];\r
+ __IO uint32_t TIM1_BGLOADVAL[32];\r
+ \r
+ __IO uint32_t TIM1ENABLE;\r
+ __IO uint32_t TIM1MODE;\r
+ __IO uint32_t TIM1INTEN;\r
+ __IO uint32_t TIM1_CTRL_RESERVED[29];\r
+ __IO uint32_t TIM1_RIS[32];\r
+ __I uint32_t TIM1_MIS[32];\r
+ \r
+ __I uint32_t TIM2_VALUE[32];\r
+ __IO uint32_t TIM2_LOADVAL[32];\r
+ __IO uint32_t TIM2_BGLOADVAL[32];\r
+ \r
+ __IO uint32_t TIM2ENABLE;\r
+ __IO uint32_t TIM2MODE;\r
+ __IO uint32_t TIM2INTEN;\r
+ __IO uint32_t TIM2_CTRL[29];\r
+ __IO uint32_t TIM2_RIS[32];\r
+ __I uint32_t TIM2_MIS[32];\r
+ \r
+ __I uint32_t TIM64VALUEU[32];\r
+ __I uint32_t TIM64VALUEL[32];\r
+ __IO uint32_t TIM64LOADVALUEU[32];\r
+ __IO uint32_t TIM64LOADVALUEL[32];\r
+ __IO uint32_t TIM64BGLOADVALUEU[32];\r
+ __IO uint32_t TIM64BGLOADVALUEL[32];\r
+ __IO uint32_t TIM64ENABLE;\r
+ __IO uint32_t TIM64MODE;\r
+ __IO uint32_t TIM64INTEN;\r
+ __IO uint32_t TIM64_CTRL[29];\r
+ __IO uint32_t TIM64_RIS[32];\r
+ __I uint32_t TIM64_MIS[32];\r
+ __IO uint32_t TIM64_MODE[32];\r
+} TIMER_BitBand_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*--------------------------------- Watchdog ---------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __I uint32_t WDOGVALUE;\r
+ __IO uint32_t WDOGLOAD;\r
+ __IO uint32_t WDOGMVRP;\r
+ __O uint32_t WDOGREFRESH;\r
+ __IO uint32_t WDOGENABLE;\r
+ __IO uint32_t WDOGCONTROL;\r
+ __I uint32_t WDOGSTATUS;\r
+ __IO uint32_t WDOGRIS;\r
+ __I uint32_t WDOGMIS;\r
+} WATCHDOG_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------- Real Time Clock ------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------- Peripherals DMA ------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t CRTL;\r
+ __IO uint32_t STATUS;\r
+ __IO uint32_t BUFFER_A_SRC_ADDR;\r
+ __IO uint32_t BUFFER_A_DEST_ADDR;\r
+ __IO uint32_t BUFFER_A_TRANSFER_COUNT;\r
+ __IO uint32_t BUFFER_B_SRC_ADDR;\r
+ __IO uint32_t BUFFER_B_DEST_ADDR;\r
+ __IO uint32_t BUFFER_B_TRANSFER_COUNT;\r
+} PDMA_Channel_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t RATIO_HIGH_LOW;\r
+ __IO uint32_t BUFFER_STATUS;\r
+ uint32_t RESERVED[6];\r
+ PDMA_Channel_TypeDef CHANNEL[8];\r
+} PDMA_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*------------------------------ Ethernet MAC --------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR0;\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t CSR1;\r
+ uint32_t RESERVED1;\r
+ __IO uint32_t CSR2;\r
+ uint32_t RESERVED2;\r
+ __IO uint32_t CSR3;\r
+ uint32_t RESERVED3;\r
+ __IO uint32_t CSR4;\r
+ uint32_t RESERVED4;\r
+ __IO uint32_t CSR5;\r
+ uint32_t RESERVED5;\r
+ __IO uint32_t CSR6;\r
+ uint32_t RESERVED6;\r
+ __IO uint32_t CSR7;\r
+ uint32_t RESERVED7;\r
+ __IO uint32_t CSR8;\r
+ uint32_t RESERVED8;\r
+ __IO uint32_t CSR9;\r
+ uint32_t RESERVED9;\r
+ uint32_t RESERVED10;\r
+ uint32_t RESERVED11;\r
+ __IO uint32_t CSR11;\r
+} MAC_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*---------------------- Analog Conversion Engine (ACE) ----------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+/* Analog quad configuration */\r
+typedef struct\r
+{\r
+ __IO uint8_t b0;\r
+ uint8_t reserved0_0;\r
+ uint16_t reserved0_1;\r
+ __IO uint8_t b1;\r
+ uint8_t reserved1_0;\r
+ uint16_t reserved1_1;\r
+ __IO uint8_t b2;\r
+ uint8_t reserved2_0;\r
+ uint16_t reserved2_1;\r
+ __IO uint8_t b3;\r
+ uint8_t reserved3_0;\r
+ uint16_t reserved3_1;\r
+ __IO uint8_t b4;\r
+ uint8_t reserved4_0;\r
+ uint16_t reserved4_1;\r
+ __IO uint8_t b5;\r
+ uint8_t reserved5_0;\r
+ uint16_t reserved5_1;\r
+ __IO uint8_t b6;\r
+ uint8_t reserved6_0;\r
+ uint16_t reserved6_1;\r
+ __IO uint8_t b7;\r
+ uint8_t reserved7_0;\r
+ uint16_t reserved7_1;\r
+ __IO uint8_t b8;\r
+ uint8_t reserved8_0;\r
+ uint16_t reserved8_1;\r
+ __IO uint8_t b9;\r
+ uint8_t reserved9_0;\r
+ uint16_t reserved9_1;\r
+ __IO uint8_t b10;\r
+ uint8_t reserved10_0;\r
+ uint16_t reserved10_1;\r
+ __IO uint8_t b11;\r
+ uint8_t reserved11_0;\r
+ uint16_t reserved11_1;\r
+} AQ_config_t;\r
+\r
+/* ACE memory map layout */\r
+typedef struct\r
+{\r
+ __O uint32_t NOP;\r
+ __IO uint32_t SSE_TS_CTRL;\r
+ __IO uint32_t ADC_SYNC_CONV;\r
+ __IO uint32_t ANA_COMM_CTRL;\r
+ __IO uint32_t DAC_SYNC_CTRL;\r
+ __IO uint32_t PDMA_REQUEST;\r
+ uint32_t RESERVED0[10];\r
+ __O uint32_t PC0_LO;\r
+ __O uint32_t PC0_HI;\r
+ __IO uint32_t PC0_CTRL;\r
+ __IO uint32_t PC0_DLY;\r
+ __IO uint32_t ADC0_CONV_CTRL;\r
+ __IO uint32_t ADC0_STC;\r
+ __IO uint32_t ADC0_TVC;\r
+ __IO uint32_t ADC0_MISC_CTRL;\r
+ __IO uint32_t DAC0_CTRL;\r
+ __IO uint32_t DAC0_BYTE0;\r
+ __IO uint32_t DAC0_BYTE1;\r
+ __IO uint32_t DAC0_BYTE2;\r
+ __IO uint32_t LC0;\r
+ __O uint32_t LC0_JMP_LO;\r
+ __O uint32_t LC0_JMP_HI;\r
+ __O uint32_t PC0_FLAGS;\r
+ __O uint32_t PC1_LO;\r
+ __O uint32_t PC1_HI;\r
+ __IO uint32_t PC1_CTRL;\r
+ __IO uint32_t PC1_DLY;\r
+ __IO uint32_t ADC1_CONV_CTRL;\r
+ __IO uint32_t ADC1_STC;\r
+ __IO uint32_t ADC1_TVC;\r
+ __IO uint32_t ADC1_MISC_CTRL;\r
+ __IO uint32_t DAC1_CTRL;\r
+ __IO uint32_t DAC1_BYTE0;\r
+ __IO uint32_t DAC1_BYTE1;\r
+ __IO uint32_t DAC1_BYTE2;\r
+ __IO uint32_t LC1;\r
+ __O uint32_t LC1_JMP_LO;\r
+ __O uint32_t LC1_JMP_HI;\r
+ __O uint32_t PC1_FLAGS;\r
+ __O uint32_t PC2_LO;\r
+ __O uint32_t PC2_HI;\r
+ __IO uint32_t PC2_CTRL;\r
+ __IO uint32_t PC2_DLY;\r
+ __IO uint32_t ADC2_CONV_CTRL;\r
+ __IO uint32_t ADC2_STC;\r
+ __IO uint32_t ADC2_TVC;\r
+ __IO uint32_t ADC2_MISC_CTRL;\r
+ __IO uint32_t DAC2_CTRL;\r
+ __IO uint32_t DAC2_BYTE0;\r
+ __IO uint32_t DAC2_BYTE1;\r
+ __IO uint32_t DAC2_BYTE2;\r
+ __IO uint32_t LC2;\r
+ __O uint32_t LC2_JMP_LO;\r
+ __O uint32_t LC2_JMP_HI;\r
+ __O uint32_t PC2_FLAGS;\r
+ uint32_t RESERVED1;\r
+ uint32_t RESERVED2;\r
+ __IO uint32_t SSE_RAM_LO_IDATA;\r
+ __IO uint32_t SSE_RAM_HI_IDATA;\r
+ uint32_t RESERVED3[61];\r
+ AQ_config_t ACB_DATA[6]; \r
+ uint32_t RESERVED4[59];\r
+ __IO uint32_t SSE_PC0;\r
+ __IO uint32_t SSE_PC1;\r
+ __IO uint32_t SSE_PC2;\r
+ uint32_t RESERVED5[57];\r
+ __IO uint32_t SSE_DAC0_BYTES01;\r
+ __IO uint32_t SSE_DAC1_BYTES01;\r
+ __IO uint32_t SSE_DAC2_BYTES01;\r
+ uint32_t RESERVED6[61];\r
+ __O uint32_t SSE_ADC0_RESULTS;\r
+ __O uint32_t SSE_ADC1_RESULTS;\r
+ __O uint32_t SSE_ADC2_RESULTS;\r
+ uint32_t RESERVED7[61];\r
+ __O uint32_t SSE_PDMA_DATAIN;\r
+ uint32_t RESERVED8[63];\r
+ __IO uint32_t SSE_RAM_DATA[512];\r
+ __I uint32_t ADC0_STATUS;\r
+ __I uint32_t ADC1_STATUS;\r
+ __I uint32_t ADC2_STATUS;\r
+ __I uint32_t COMPARATOR_STATUS;\r
+ uint32_t RESERVED9[124];\r
+ __IO uint32_t SSE_IRQ_EN;\r
+ __I uint32_t SSE_IRQ;\r
+ __O uint32_t SSE_IRQ_CLR;\r
+ __IO uint32_t COMP_IRQ_EN;\r
+ __I uint32_t COMP_IRQ;\r
+ __O uint32_t COMP_IRQ_CLR;\r
+ __IO uint32_t PPE_FIFO_IRQ_EN;\r
+ __I uint32_t PPE_FIFO_IRQ;\r
+ __O uint32_t PPE_FIFO_IRQ_CLR;\r
+ __IO uint32_t PPE_FLAGS0_IRQ_EN;\r
+ __I uint32_t PPE_FLAGS0_IRQ;\r
+ __O uint32_t PPE_FLAGS0_IRQ_CLR;\r
+ __IO uint32_t PPE_FLAGS1_IRQ_EN;\r
+ __I uint32_t PPE_FLAGS1_IRQ;\r
+ __O uint32_t PPE_FLAGS1_IRQ_CLR;\r
+ __IO uint32_t PPE_FLAGS2_IRQ_EN;\r
+ __I uint32_t PPE_FLAGS2_IRQ;\r
+ __O uint32_t PPE_FLAGS2_IRQ_CLR;\r
+ __IO uint32_t PPE_FLAGS3_IRQ_EN;\r
+ __I uint32_t PPE_FLAGS3_IRQ;\r
+ __O uint32_t PPE_FLAGS3_IRQ_CLR;\r
+ __IO uint32_t PPE_SFFLAGS_IRQ_EN;\r
+ __I uint32_t PPE_SFFLAGS_IRQ;\r
+ __O uint32_t PPE_SFFLAGS_IRQ_CLR;\r
+ __IO uint32_t FPGA_FLAGS_SEL;\r
+ uint32_t RESERVED10[39];\r
+ __IO uint32_t PPE_PDMA_CTRL;\r
+ __I uint32_t PDMA_STATUS;\r
+ __IO uint32_t PPE_PDMA_DATAOUT;\r
+ uint32_t RESERVED11[61];\r
+ __I uint32_t PPE_NOP;\r
+ __IO uint32_t PPE_CTRL;\r
+ __IO uint32_t PPE_PC_ETC;\r
+ __IO uint32_t PPE_SF;\r
+ __IO uint32_t PPE_SCRATCH;\r
+ uint32_t RESERVED12;\r
+ __IO uint32_t ALU_CTRL;\r
+ __I uint32_t ALU_STATUS;\r
+ __IO uint32_t ALU_A;\r
+ uint32_t RESERVED50;\r
+ __IO uint32_t ALU_B;\r
+ uint32_t RESERVED53;\r
+ __IO uint32_t ALU_C;\r
+ uint32_t RESERVED51;\r
+ __IO uint32_t ALU_D;\r
+ uint32_t RESERVED52;\r
+ __IO uint32_t ALU_E;\r
+ uint32_t RESERVED54;\r
+ __IO uint32_t PPE_FPTR;\r
+ uint32_t RESERVED55;\r
+ __IO uint32_t PPE_FLAGS0;\r
+ __IO uint32_t PPE_FLAGS1;\r
+ __IO uint32_t PPE_FLAGS2;\r
+ __IO uint32_t PPE_FLAGS3;\r
+ __IO uint32_t PPE_SFFLAGS;\r
+ uint32_t RESERVED13[11];\r
+ __IO uint32_t ADC0_FIFO_CTRL;\r
+ __I uint32_t ADC0_FIFO_STATUS;\r
+ __IO uint32_t ADC0_FIFO_DATA;\r
+ __IO uint32_t ADC1_FIFO_CTRL;\r
+ __I uint32_t ADC1_FIFO_STATUS;\r
+ __IO uint32_t ADC1_FIFO_DATA;\r
+ __IO uint32_t ADC2_FIFO_CTRL;\r
+ __I uint32_t ADC2_FIFO_STATUS;\r
+ __IO uint32_t ADC2_FIFO_DATA;\r
+ uint32_t RESERVED14[19];\r
+ __I uint32_t ADC0_FIFO_DATA_PEEK;\r
+ __I uint32_t ADC0_FIFO_DATA0;\r
+ __I uint32_t ADC0_FIFO_DATA1;\r
+ __I uint32_t ADC0_FIFO_DATA2;\r
+ __I uint32_t ADC0_FIFO_DATA3;\r
+ __I uint32_t ADC1_FIFO_DATA_PEEK;\r
+ __I uint32_t ADC1_FIFO_DATA0;\r
+ __I uint32_t ADC1_FIFO_DATA1;\r
+ __I uint32_t ADC1_FIFO_DATA2;\r
+ __I uint32_t ADC1_FIFO_DATA3;\r
+ __I uint32_t ADC2_FIFO_DATA_PEEK;\r
+ __I uint32_t ADC2_FIFO_DATA0;\r
+ __I uint32_t ADC2_FIFO_DATA1;\r
+ __I uint32_t ADC2_FIFO_DATA2;\r
+ __I uint32_t ADC2_FIFO_DATA3;\r
+ uint32_t RESERVED15[177]; \r
+ __IO uint32_t PPE_RAM_DATA[512];\r
+} ACE_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*------------------------ In Application Programming ------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t IAP_IR;\r
+ __IO uint32_t IAP_DR2;\r
+ __IO uint32_t IAP_DR3;\r
+ __IO uint32_t IAP_DR5;\r
+ __IO uint32_t IAP_DR26;\r
+ __IO uint32_t IAP_DR32;\r
+ __IO uint32_t IAP_DR;\r
+ __IO uint32_t IAP_DR_LENGTH;\r
+ __IO uint32_t IAP_TAP_NEW_STATE;\r
+ __IO uint32_t IAP_TAP_CONTROL;\r
+ __I uint32_t IAP_STATUS;\r
+} IAP_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*---------------------- eNVM Special Function Registers ---------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t STATUS;\r
+ __IO uint32_t CONTROL;\r
+ __IO uint32_t ENABLE;\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t CONFIG_0;\r
+ __IO uint32_t CONFIG_1;\r
+ __IO uint32_t PAGE_STATUS_0;\r
+ __IO uint32_t PAGE_STATUS_1;\r
+ __IO uint32_t SEGMENT;\r
+ __IO uint32_t ENVM_SELECT;\r
+} NVM_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*---------------------- eNVM Special Function Registers ---------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t MSSIRQ_EN0;\r
+ __IO uint32_t MSSIRQ_EN1;\r
+ __IO uint32_t MSSIRQ_EN2;\r
+ __IO uint32_t MSSIRQ_EN3;\r
+ __IO uint32_t MSSIRQ_EN4;\r
+ __IO uint32_t MSSIRQ_EN5;\r
+ __IO uint32_t MSSIRQ_EN6;\r
+ __IO uint32_t MSSIRQ_EN7;\r
+ __I uint32_t MSSIRQ_SRC0;\r
+ __I uint32_t MSSIRQ_SRC1;\r
+ __I uint32_t MSSIRQ_SRC2;\r
+ __I uint32_t MSSIRQ_SRC3;\r
+ __I uint32_t MSSIRQ_SRC4;\r
+ __I uint32_t MSSIRQ_SRC5;\r
+ __I uint32_t MSSIRQ_SRC6;\r
+ __I uint32_t MSSIRQ_SRC7;\r
+ __IO uint32_t FIIC_MR;\r
+} MSS_IRQ_CTRL_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*------------------------------ System Registers ----------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t ESRAM_CR;\r
+ __IO uint32_t ENVM_CR;\r
+ __IO uint32_t ENVM_REMAP_SYS_CR;\r
+ __IO uint32_t ENVM_REMAP_FAB_CR;\r
+ __IO uint32_t FAB_PROT_SIZE_CR;\r
+ __IO uint32_t FAB_PROT_BASE_CR;\r
+ __IO uint32_t AHB_MATRIX_CR;\r
+ __IO uint32_t MSS_SR;\r
+ __IO uint32_t CLR_MSS_SR;\r
+ __IO uint32_t EFROM_CR;\r
+ __IO uint32_t IAP_CR;\r
+ __IO uint32_t SOFT_IRQ_CR;\r
+ __IO uint32_t SOFT_RST_CR;\r
+ __IO uint32_t DEVICE_SR;\r
+ __IO uint32_t SYSTICK_CR;\r
+ __IO uint32_t EMC_MUX_CR;\r
+ __IO uint32_t EMC_CS_0_CR;\r
+ __IO uint32_t EMC_CS_1_CR;\r
+ __IO uint32_t MSS_CLK_CR;\r
+ __IO uint32_t MSS_CCC_DIV_CR;\r
+ __IO uint32_t MSS_CCC_MUX_CR;\r
+ __IO uint32_t MSS_CCC_PLL_CR;\r
+ __IO uint32_t MSS_CCC_DLY_CR;\r
+ __IO uint32_t MSS_CCC_SR;\r
+ __IO uint32_t MSS_RCOSC_CR;\r
+ __IO uint32_t VRPSM_CR;\r
+ __IO uint32_t RESERVED;\r
+ __IO uint32_t FAB_IF_CR;\r
+ __IO uint32_t FAB_APB_HIWORD_DR;\r
+ __IO uint32_t LOOPBACK_CR;\r
+ __IO uint32_t MSS_IO_BANK_CR;\r
+ __IO uint32_t GPIN_SOURCE_CR;\r
+ __IO uint32_t TEST_SR;\r
+ __IO uint32_t RED_REP_ADDR0;\r
+ __I uint32_t RED_REP_LOW_LOCS0;\r
+ __I uint32_t RED_REP_HIGH_LOCS0;\r
+ __IO uint32_t RED_REP_ADDR1;\r
+ __I uint32_t RED_REP_LOW_LOCS1;\r
+ __I uint32_t RED_REP_HIGH_LOCS1;\r
+ __IO uint32_t FABRIC_CR;\r
+ uint32_t RESERVED1[24];\r
+ __IO uint32_t IOMUX_CR[83];\r
+} SYSREG_TypeDef;\r
+\r
+#define SYSREG_ENVM_SOFTRESET_MASK (uint32_t)0x00000001\r
+#define SYSREG_ESRAM0_SOFTRESET_MASK (uint32_t)0x00000002\r
+#define SYSREG_ESRAM1_SOFTRESET_MASK (uint32_t)0x00000004\r
+#define SYSREG_EMC_SOFTRESET_MASK (uint32_t)0x00000008\r
+#define SYSREG_MAC_SOFTRESET_MASK (uint32_t)0x00000010\r
+#define SYSREG_PDMA_SOFTRESET_MASK (uint32_t)0x00000020\r
+#define SYSREG_TIMER_SOFTRESET_MASK (uint32_t)0x00000040\r
+#define SYSREG_UART0_SOFTRESET_MASK (uint32_t)0x00000080\r
+#define SYSREG_UART1_SOFTRESET_MASK (uint32_t)0x00000100\r
+#define SYSREG_SPI0_SOFTRESET_MASK (uint32_t)0x00000200\r
+#define SYSREG_SPI1_SOFTRESET_MASK (uint32_t)0x00000400\r
+#define SYSREG_I2C0_SOFTRESET_MASK (uint32_t)0x00000800\r
+#define SYSREG_I2C1_SOFTRESET_MASK (uint32_t)0x00001000\r
+#define SYSREG_ACE_SOFTRESET_MASK (uint32_t)0x00002000\r
+#define SYSREG_GPIO_SOFTRESET_MASK (uint32_t)0x00004000\r
+#define SYSREG_IAP_SOFTRESET_MASK (uint32_t)0x00008000\r
+#define SYSREG_EXT_SOFTRESET_MASK (uint32_t)0x00010000\r
+#define SYSREG_FPGA_SOFTRESET_MASK (uint32_t)0x00020000\r
+#define SYSREG_F2M_RESET_ENABLE_MASK (uint32_t)0x00040000 \r
+#define SYSREG_PADRESET_ENABLE_MASK (uint32_t)0x00080000\r
+\r
+/******************************************************************************/\r
+/* Peripheral memory map */\r
+/******************************************************************************/\r
+#define UART0_BASE 0x40000000U\r
+#define SPI0_BASE 0x40001000U\r
+#define I2C0_BASE 0x40002000U\r
+#define MAC_BASE 0x40003000U\r
+#define PDMA_BASE 0x40004000U\r
+#define TIMER_BASE 0x40005000U\r
+#define WATCHDOG_BASE 0x40006000U\r
+#define H2F_IRQ_CTRL_BASE 0x40007000U\r
+#define UART1_BASE 0x40010000U\r
+#define SPI1_BASE 0x40011000U\r
+#define I2C1_BASE 0x40012000U\r
+#define GPIO_BASE 0x40013000U\r
+#define RTC_BASE 0x40014100U\r
+#define FROM_BASE 0x40015000U\r
+#define IAP_BASE 0x40016000U\r
+#define ACE_BASE 0x40020000U\r
+#define FPGA_FABRIC_RAM_BASE 0x40040000U\r
+#define FPGA_FABRIC_BASE 0x40050000U\r
+#define ENVM_BASE 0x60000000U\r
+#define ENVM_REGS_BASE 0x60100000U\r
+#define SYSREG_BASE 0xE0042000U\r
+\r
+/******************************************************************************/\r
+/* bitband address calcualtion macro */\r
+/******************************************************************************/\r
+#define BITBAND_ADDRESS(X) ((X & 0xF0000000U) + 0x02000000U + ((X & 0xFFFFFU) << 5))\r
+\r
+/******************************************************************************/\r
+/* Peripheral declaration */\r
+/******************************************************************************/\r
+#define UART0 ((UART_TypeDef *) UART0_BASE)\r
+#define UART0_BITBAND ((UART_BitBand_TypeDef *) BITBAND_ADDRESS(UART0_BASE))\r
+#define SPI0 ((SPI_TypeDef *) SPI0_BASE)\r
+#define SPI0_BITBAND ((SPI_BitBand_TypeDef *) BITBAND_ADDRESS(SPI0_BASE))\r
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE)\r
+#define I2C0_BITBAND ((I2C_BitBand_TypeDef *) BITBAND_ADDRESS(I2C0_BASE))\r
+#define MAC ((MAC_TypeDef *) MAC_BASE)\r
+#define PDMA ((PDMA_TypeDef *) PDMA_BASE)\r
+#define TIMER ((TIMER_TypeDef *) TIMER_BASE)\r
+#define TIMER_BITBAND ((TIMER_BitBand_TypeDef *) BITBAND_ADDRESS(TIMER_BASE))\r
+#define WATCHDOG ((WATCHDOG_TypeDef *) WATCHDOG_BASE)\r
+#define MSS_IRQ_CTRL ((MSS_IRQ_CTRL_TypeDef *) H2F_IRQ_CTRL_BASE)\r
+#define UART1 ((UART_TypeDef *) UART1_BASE)\r
+#define UART1_BITBAND ((UART_BitBand_TypeDef *) BITBAND_ADDRESS(UART1_BASE))\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
+#define SPI1_BITBAND ((SPI_BitBand_TypeDef *) BITBAND_ADDRESS(SPI1_BASE))\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C1_BITBAND ((I2C_BitBand_TypeDef *) BITBAND_ADDRESS(I2C1_BASE))\r
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE)\r
+#define GPIO_BITBAND ((GPIO_BitBand_TypeDef *) BITBAND_ADDRESS(GPIO_BASE))\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define FROM ((void *) FROM_BASE)\r
+#define IAP ((IAP_TypeDef *) IAP_BASE)\r
+#define ACE ((ACE_TypeDef *) ACE_BASE)\r
+#define FPGA_FABRIC_RAM ((void *) FPGA_FABRIC_RAM_BASE)\r
+#define FPGA_FABRIC ((void *) FPGA_FABRIC_BASE)\r
+#define ENVM ((void *) ENVM_BASE)\r
+#define ENVM_REGS ((NVM_TypeDef *) ENVM_REGS_BASE)\r
+#define SYSREG ((SYSREG_TypeDef *) SYSREG_BASE)\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __A2FXXXM3_H__ */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.c\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
+ * @version V1.30\r
+ * @date 30. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <stdint.h>\r
+\r
+/* define compiler specific symbols */\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+__ASM uint32_t __get_PSP(void)\r
+{\r
+ mrs r0, psp\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ msr psp, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+__ASM uint32_t __get_MSP(void)\r
+{\r
+ mrs r0, msp\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_MSP(uint32_t mainStackPointer)\r
+{\r
+ msr msp, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+__ASM uint32_t __REV16(uint16_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+__ASM int32_t __REVSH(int16_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+__ASM void __CLREX(void)\r
+{\r
+ clrex\r
+}\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+__ASM uint32_t __get_BASEPRI(void)\r
+{\r
+ mrs r0, basepri\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+__ASM void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ msr basepri, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+__ASM uint32_t __get_PRIMASK(void)\r
+{\r
+ mrs r0, primask\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+__ASM void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ msr primask, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+__ASM uint32_t __get_FAULTMASK(void)\r
+{\r
+ mrs r0, faultmask\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+__ASM void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ msr faultmask, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+__ASM uint32_t __get_CONTROL(void)\r
+{\r
+ mrs r0, control\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+__ASM void __set_CONTROL(uint32_t control)\r
+{\r
+ msr control, r0\r
+ bx lr\r
+}\r
+\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+#pragma diag_suppress=Pe940\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void)\r
+{\r
+ __ASM("mrs r0, psp");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM("msr psp, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void)\r
+{\r
+ __ASM("mrs r0, msp");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM("msr msp, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+ __ASM("rev16 r0, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+ __ASM("rbit r0, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit values)\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+ __ASM("ldrexb r0, [r0]");\r
+ __ASM("bx lr"); \r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+ __ASM("ldrexh r0, [r0]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+ __ASM("ldrex r0, [r0]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+ __ASM("strexb r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+ __ASM("strexh r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+ __ASM("strex r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+#pragma diag_default=Pe940\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_PSP(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, psp\n\t" \r
+ "MOV r0, %0 \n\t"\r
+ "BX lr \n\t" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n\t"\r
+ "BX lr \n\t" : : "r" (topOfProcStack) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_MSP(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, msp\n\t" \r
+ "MOV r0, %0 \n\t"\r
+ "BX lr \n\t" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n\t"\r
+ "BX lr \n\t" : : "r" (topOfMainStack) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+* \r
+* @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+\r
+/**\r
+ * @brief Reverse byte order in integer value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+uint32_t __REV(uint32_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+int32_t __REVSH(int16_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit value\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+ uint8_t result=0;\r
+ \r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+ uint16_t result=0;\r
+ \r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V1.30\r
+ * @date 30. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CM3_CORE_H__\r
+#define __CM3_CORE_H__\r
+\r
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
+ *\r
+ * List of Lint messages which will be suppressed and not shown:\r
+ * - Error 10: \n\r
+ * register uint32_t __regBasePri __asm("basepri"); \n\r
+ * Error 10: Expecting ';'\r
+ * .\r
+ * - Error 530: \n\r
+ * return(__regBasePri); \n\r
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized\r
+ * . \r
+ * - Error 550: \n\r
+ * __regBasePri = (basePri & 0x1ff); \n\r
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed\r
+ * .\r
+ * - Error 754: \n\r
+ * uint32_t RESERVED0[24]; \n\r
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 750: \n\r
+ * #define __CM3_CORE_H__ \n\r
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 528: \n\r
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 751: \n\r
+ * } InterruptType_Type; \n\r
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced\r
+ * .\r
+ * Note: To re-enable a Message, insert a space before 'lint' *\r
+ *\r
+ */\r
+\r
+/*lint -save */\r
+/*lint -e10 */\r
+/*lint -e530 */\r
+/*lint -e550 */\r
+/*lint -e754 */\r
+/*lint -e750 */\r
+/*lint -e528 */\r
+/*lint -e751 */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
+ This file defines all structures and symbols for CMSIS core:\r
+ - CMSIS version number\r
+ - Cortex-M core registers and bitfields\r
+ - Cortex-M core peripheral base address\r
+ @{\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex core */\r
+\r
+#include <stdint.h> /* Include standard types */\r
+\r
+#if defined (__ICCARM__)\r
+ #include <intrinsics.h> /* IAR Intrinsics */\r
+#endif\r
+\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+\r
+\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
+ memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24]; \r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24]; \r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24]; \r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24]; \r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56]; \r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644]; \r
+ __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */\r
+} NVIC_Type; \r
+/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
+ memory mapped structure for System Control Block (SCB)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */\r
+} SCB_Type; \r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+ \r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SCB */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
+ memory mapped structure for SysTick\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
+ memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __O union \r
+ {\r
+ __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864]; \r
+ __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15]; \r
+ __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15]; \r
+ __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */\r
+ uint32_t RESERVED3[29]; \r
+ __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */\r
+ __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43]; \r
+ __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */\r
+ __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */\r
+ uint32_t RESERVED5[6]; \r
+ __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */\r
+} ITM_Type; \r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_ITM */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
+ memory mapped structure for Interrupt Type\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0;\r
+ __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1;\r
+#endif\r
+} InterruptType_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */\r
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */\r
+#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */\r
+\r
+#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
+\r
+#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */\r
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
+ memory mapped structure for Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type; \r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */\r
+#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */\r
+#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */\r
+#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */\r
+#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */\r
+#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */\r
+#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_MPU */\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
+ memory mapped structure for Core Debug Register\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
+\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
+\r
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_register */\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#define __enable_fault_irq __enable_fiq\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+#define __NOP __nop\r
+#define __WFI __wfi\r
+#define __WFE __wfe\r
+#define __SEV __sev\r
+#define __ISB() __isb(0)\r
+#define __DSB() __dsb(0)\r
+#define __DMB() __dmb(0)\r
+#define __REV __rev\r
+#define __RBIT __rbit\r
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+extern void __CLREX(void);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & 1);\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
+\r
+static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
+\r
+#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ \r
+static __INLINE void __WFI() { __ASM ("wfi"); }\r
+static __INLINE void __WFE() { __ASM ("wfe"); }\r
+static __INLINE void __SEV() { __ASM ("sev"); }\r
+static __INLINE void __CLREX() { __ASM ("clrex"); }\r
+\r
+/* intrinsic void __ISB(void) */\r
+/* intrinsic void __DSB(void) */\r
+/* intrinsic void __DMB(void) */\r
+/* intrinsic void __set_PRIMASK(); */\r
+/* intrinsic void __get_PRIMASK(); */\r
+/* intrinsic void __set_FAULTMASK(); */\r
+/* intrinsic void __get_FAULTMASK(); */\r
+/* intrinsic uint32_t __REV(uint32_t value); */\r
+/* intrinsic uint32_t __REVSH(uint32_t value); */\r
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
+/* intrinsic unsigned long __LDREX(unsigned long *); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit values)\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); }\r
+static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); }\r
+\r
+static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); }\r
+\r
+static __INLINE void __NOP(void) { __ASM volatile ("nop"); }\r
+static __INLINE void __WFI(void) { __ASM volatile ("wfi"); }\r
+static __INLINE void __WFE(void) { __ASM volatile ("wfe"); }\r
+static __INLINE void __SEV(void) { __ASM volatile ("sev"); }\r
+static __INLINE void __ISB(void) { __ASM volatile ("isb"); }\r
+static __INLINE void __DSB(void) { __ASM volatile ("dsb"); }\r
+static __INLINE void __DMB(void) { __ASM volatile ("dmb"); }\r
+static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); }\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+* \r
+* @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+/**\r
+ * @brief Reverse byte order in integer value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+extern uint32_t __REV(uint32_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit value\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface\r
+ Core Function Interface containing:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Reset Functions\r
+*/\r
+/*@{*/\r
+\r
+/* ########################## NVIC functions #################################### */\r
+\r
+/**\r
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
+ *\r
+ * @param PriorityGroup is priority grouping field\r
+ *\r
+ * Set the priority grouping field using the required unlock sequence.\r
+ * The parameter priority_grouping is assigned to the field \r
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ \r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ (0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+/**\r
+ * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
+ *\r
+ * @return priority grouping field \r
+ *\r
+ * Get the priority grouping from NVIC Interrupt Controller.\r
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+/**\r
+ * @brief Enable Interrupt in NVIC Interrupt Controller\r
+ *\r
+ * @param IRQn The positive number of the external interrupt to enable\r
+ *\r
+ * Enable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Disable the interrupt line for external interrupt specified\r
+ * \r
+ * @param IRQn The positive number of the external interrupt to disable\r
+ * \r
+ * Disable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the interrupt pending bit for a device specific interrupt source\r
+ * \r
+ * @param IRQn The number of the device specifc interrupt\r
+ * @return 1 = interrupt pending, 0 = interrupt not pending\r
+ *\r
+ * Read the pending register in NVIC and return 1 if its status is pending, \r
+ * otherwise it returns 0\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the pending bit for an external interrupt\r
+ * \r
+ * @param IRQn The number of the interrupt for set pending\r
+ *\r
+ * Set the pending bit for the specified interrupt.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+/**\r
+ * @brief Clear the pending bit for an external interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for clear pending\r
+ *\r
+ * Clear the pending bit for the specified interrupt. \r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the active bit for an external interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for read active bit\r
+ * @return 1 = interrupt active, 0 = interrupt not active\r
+ *\r
+ * Read the active register in NVIC and returns 1 if its status is active, \r
+ * otherwise it returns 0.\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the priority for an interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for set priority\r
+ * @param priority The priority to set\r
+ *\r
+ * Set the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+/**\r
+ * @brief Read the priority for an interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for get priority\r
+ * @return The priority for the interrupt\r
+ *\r
+ * Read the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * The returned priority value is automatically aligned to the implemented\r
+ * priority bits of the microcontroller.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Encode the priority for an interrupt\r
+ *\r
+ * @param PriorityGroup The used priority group\r
+ * @param PreemptPriority The preemptive priority value (starting from 0)\r
+ * @param SubPriority The sub priority value (starting from 0)\r
+ * @return The encoded priority for the interrupt\r
+ *\r
+ * Encode the priority for an interrupt with the given priority group,\r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The returned priority value can be used for NVIC_SetPriority(...) function\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ * @brief Decode the priority of an interrupt\r
+ *\r
+ * @param Priority The priority for the interrupt\r
+ * @param PriorityGroup The used priority group\r
+ * @param pPreemptPriority The preemptive priority value (starting from 0)\r
+ * @param pSubPriority The sub priority value (starting from 0)\r
+ *\r
+ * Decode an interrupt priority value with the given priority group to \r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The priority value can be retrieved with NVIC_GetPriority(...) function\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+\r
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
+\r
+/**\r
+ * @brief Initialize and start the SysTick counter and its interrupt.\r
+ *\r
+ * @param ticks number of ticks between two interrupts\r
+ * @return 1 = failed, 0 = successful\r
+ *\r
+ * Initialise the system tick timer and its interrupt and start the\r
+ * system tick timer / counter in free running mode to generate \r
+ * periodical interrupts.\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{ \r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ \r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | \r
+ SysTick_CTRL_TICKINT_Msk | \r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+/* ################################## Reset function ############################################ */\r
+\r
+/**\r
+ * @brief Initiate a system reset request.\r
+ *\r
+ * Initiate a system reset request to reset the MCU\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | \r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */ \r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface\r
+ Core Debug Interface containing:\r
+ - Core Debug Receive / Transmit Functions\r
+ - Core Debug Defines\r
+ - Core Debug Variables\r
+*/\r
+/*@{*/\r
+\r
+extern volatile int ITM_RxBuffer; /*!< variable to receive characters */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
+\r
+\r
+/**\r
+ * @brief Outputs a character via the ITM channel 0\r
+ *\r
+ * @param ch character to output\r
+ * @return character to output\r
+ *\r
+ * The function outputs a character via the ITM channel 0. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ } \r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Inputs a character via variable ITM_RxBuffer\r
+ *\r
+ * @return received character, -1 = no character received\r
+ *\r
+ * The function inputs a character via variable ITM_RxBuffer. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE int ITM_ReceiveChar (void) {\r
+ int ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+ \r
+ return (ch); \r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if a character via variable ITM_RxBuffer is available\r
+ *\r
+ * @return 1 = character available, 0 = no character available\r
+ *\r
+ * The function checks variable ITM_RxBuffer whether a character is available or not. \r
+ * The function returns '1' if a character is available and '0' if no character is available. \r
+ */\r
+static __INLINE int ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_definitions */\r
+\r
+#endif /* __CM3_CORE_H__ */\r
+\r
+/*lint -restore */\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * Assertion implementation.\r
+ *\r
+ * This file provides the implementation of the ASSERT macro. This file can be\r
+ * modified to cater for project specific requirements regarding the way\r
+ * assertions are handled.\r
+ *\r
+ * SVN $Revision: 1676 $\r
+ * SVN $Date: 2009-12-02 16:47:03 +0000 (Wed, 02 Dec 2009) $\r
+ */\r
+#ifndef __MSS_ASSERT_H_\r
+#define __MSS_ASSERT_H_\r
+\r
+#include <assert.h>\r
+\r
+#if defined ( __GNUC__ )\r
+\r
+#if defined(NDEBUG)\r
+\r
+#define ASSERT(CHECK)\r
+\r
+#else /* NDEBUG */\r
+/*\r
+ * SoftConsole assertion handling\r
+ */\r
+#define ASSERT(CHECK) \\r
+ do { \\r
+ if (!(CHECK)) \\r
+ { \\r
+ __asm volatile ("BKPT\n\t"); \\r
+ } \\r
+ } while (0);\r
+ \r
+#endif /* NDEBUG */\r
+\r
+#else\r
+/*\r
+ * IAR Embedded Workbench or Keil assertion handling.\r
+ * Call C library assert function which should result in error message\r
+ * displayed in debugger.\r
+ */\r
+#define ASSERT(X) assert(X)\r
+\r
+#endif\r
+\r
+#endif /* __MSS_ASSERT_H_ */\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ *\r
+ * Startup code for SmartFusion A2FM3Fxxx\r
+ *\r
+ * SVN $Revision: 2068 $\r
+ * SVN $Date: 2010-01-27 17:27:41 +0000 (Wed, 27 Jan 2010) $\r
+ */\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+ SECTION .intvec:CODE:NOROOT(2)\r
+ \r
+ EXTERN __iar_program_start\r
+; EXTERN SystemInit\r
+ PUBLIC __vector_table\r
+\r
+ DATA\r
+__vector_table\r
+ DCD sfe(CSTACK)\r
+ DCD Reset_Handler\r
+\r
+ DCD NMI_Handler\r
+ DCD HardFault_Handler\r
+ DCD MemManage_Handler\r
+ DCD BusFault_Handler\r
+ DCD UsageFault_Handler\r
+ DCD 0\r
+ DCD 0\r
+ DCD 0\r
+ DCD 0\r
+ DCD SVC_Handler\r
+ DCD DebugMon_Handler\r
+ DCD 0\r
+ DCD PendSV_Handler\r
+ DCD SysTick_Handler\r
+\r
+ ; External Interrupts\r
+ DCD WdogWakeup_IRQHandler\r
+ DCD BrownOut_1_5V_IRQHandler\r
+ DCD BrownOut_3_3V_IRQHandler\r
+ DCD RTC_Match_IRQHandler\r
+ DCD RTCIF_Pub_IRQHandler\r
+ DCD EthernetMAC_IRQHandler\r
+ DCD IAP_IRQHandler\r
+ DCD ENVM0_IRQHandler\r
+ DCD ENVM1_IRQHandler\r
+ DCD DMA_IRQHandler\r
+ DCD UART0_IRQHandler\r
+ DCD UART1_IRQHandler\r
+ DCD SPI0_IRQHandler\r
+ DCD SPI1_IRQHandler\r
+ DCD I2C0_IRQHandler\r
+ DCD I2C0_SMBAlert_IRQHandler\r
+ DCD I2C0_SMBus_IRQHandler\r
+ DCD I2C1_IRQHandler\r
+ DCD I2C1_SMBAlert_IRQHandler\r
+ DCD I2C1_SMBus_IRQHandler\r
+ DCD Timer1_IRQHandler\r
+ DCD Timer2_IRQHandler\r
+ DCD PLL_Lock_IRQHandler\r
+ DCD PLL_LockLost_IRQHandler\r
+ DCD CommError_IRQHandler\r
+ DCD 0\r
+ DCD 0\r
+ DCD 0\r
+ DCD 0\r
+ DCD 0\r
+ DCD 0\r
+ DCD Fabric_IRQHandler\r
+ DCD GPIO0_IRQHandler\r
+ DCD GPIO1_IRQHandler\r
+ DCD GPIO2_IRQHandler\r
+ DCD GPIO3_IRQHandler\r
+ DCD GPIO4_IRQHandler\r
+ DCD GPIO5_IRQHandler\r
+ DCD GPIO6_IRQHandler\r
+ DCD GPIO7_IRQHandler\r
+ DCD GPIO8_IRQHandler\r
+ DCD GPIO9_IRQHandler\r
+ DCD GPIO10_IRQHandler\r
+ DCD GPIO11_IRQHandler\r
+ DCD GPIO12_IRQHandler\r
+ DCD GPIO13_IRQHandler\r
+ DCD GPIO14_IRQHandler\r
+ DCD GPIO15_IRQHandler\r
+ DCD GPIO16_IRQHandler\r
+ DCD GPIO17_IRQHandler\r
+ DCD GPIO18_IRQHandler\r
+ DCD GPIO19_IRQHandler\r
+ DCD GPIO20_IRQHandler\r
+ DCD GPIO21_IRQHandler\r
+ DCD GPIO22_IRQHandler\r
+ DCD GPIO23_IRQHandler\r
+ DCD GPIO24_IRQHandler\r
+ DCD GPIO25_IRQHandler\r
+ DCD GPIO26_IRQHandler\r
+ DCD GPIO27_IRQHandler\r
+ DCD GPIO28_IRQHandler\r
+ DCD GPIO29_IRQHandler\r
+ DCD GPIO30_IRQHandler\r
+ DCD GPIO31_IRQHandler\r
+ DCD ACE_PC0_Flag0_IRQHandler\r
+ DCD ACE_PC0_Flag1_IRQHandler\r
+ DCD ACE_PC0_Flag2_IRQHandler\r
+ DCD ACE_PC0_Flag3_IRQHandler\r
+ DCD ACE_PC1_Flag0_IRQHandler\r
+ DCD ACE_PC1_Flag1_IRQHandler\r
+ DCD ACE_PC1_Flag2_IRQHandler\r
+ DCD ACE_PC1_Flag3_IRQHandler\r
+ DCD ACE_PC2_Flag0_IRQHandler\r
+ DCD ACE_PC2_Flag1_IRQHandler\r
+ DCD ACE_PC2_Flag2_IRQHandler\r
+ DCD ACE_PC2_Flag3_IRQHandler\r
+ DCD ACE_ADC0_DataValid_IRQHandler\r
+ DCD ACE_ADC1_DataValid_IRQHandler\r
+ DCD ACE_ADC2_DataValid_IRQHandler\r
+ DCD ACE_ADC0_CalDone_IRQHandler\r
+ DCD ACE_ADC1_CalDone_IRQHandler\r
+ DCD ACE_ADC2_CalDone_IRQHandler\r
+ DCD ACE_ADC0_CalStart_IRQHandler\r
+ DCD ACE_ADC1_CalStart_IRQHandler\r
+ DCD ACE_ADC2_CalStart_IRQHandler\r
+ DCD ACE_Comp0_Fall_IRQHandler\r
+ DCD ACE_Comp1_Fall_IRQHandler\r
+ DCD ACE_Comp2_Fall_IRQHandler\r
+ DCD ACE_Comp3_Fall_IRQHandler\r
+ DCD ACE_Comp4_Fall_IRQHandler\r
+ DCD ACE_Comp5_Fall_IRQHandler\r
+ DCD ACE_Comp6_Fall_IRQHandler\r
+ DCD ACE_Comp7_Fall_IRQHandler\r
+ DCD ACE_Comp8_Fall_IRQHandler\r
+ DCD ACE_Comp9_Fall_IRQHandler\r
+ DCD ACE_Comp10_Fall_IRQHandler\r
+ DCD ACE_Comp11_Fall_IRQHandler\r
+ DCD ACE_Comp0_Rise_IRQHandler\r
+ DCD ACE_Comp1_Rise_IRQHandler\r
+ DCD ACE_Comp2_Rise_IRQHandler\r
+ DCD ACE_Comp3_Rise_IRQHandler\r
+ DCD ACE_Comp4_Rise_IRQHandler\r
+ DCD ACE_Comp5_Rise_IRQHandler\r
+ DCD ACE_Comp6_Rise_IRQHandler\r
+ DCD ACE_Comp7_Rise_IRQHandler\r
+ DCD ACE_Comp8_Rise_IRQHandler\r
+ DCD ACE_Comp9_Rise_IRQHandler\r
+ DCD ACE_Comp10_Rise_IRQHandler\r
+ DCD ACE_Comp11_Rise_IRQHandler\r
+ DCD ACE_ADC0_FifoFull_IRQHandler\r
+ DCD ACE_ADC0_FifoAFull_IRQHandler\r
+ DCD ACE_ADC0_FifoEmpty_IRQHandler\r
+ DCD ACE_ADC1_FifoFull_IRQHandler\r
+ DCD ACE_ADC1_FifoAFull_IRQHandler\r
+ DCD ACE_ADC1_FifoEmpty_IRQHandler\r
+ DCD ACE_ADC2_FifoFull_IRQHandler\r
+ DCD ACE_ADC2_FifoAFull_IRQHandler\r
+ DCD ACE_ADC2_FifoEmpty_IRQHandler\r
+ DCD ACE_PPE_Flag0_IRQHandler\r
+ DCD ACE_PPE_Flag1_IRQHandler\r
+ DCD ACE_PPE_Flag2_IRQHandler\r
+ DCD ACE_PPE_Flag3_IRQHandler\r
+ DCD ACE_PPE_Flag4_IRQHandler\r
+ DCD ACE_PPE_Flag5_IRQHandler\r
+ DCD ACE_PPE_Flag6_IRQHandler\r
+ DCD ACE_PPE_Flag7_IRQHandler\r
+ DCD ACE_PPE_Flag8_IRQHandler\r
+ DCD ACE_PPE_Flag9_IRQHandler\r
+ DCD ACE_PPE_Flag10_IRQHandler\r
+ DCD ACE_PPE_Flag11_IRQHandler\r
+ DCD ACE_PPE_Flag12_IRQHandler\r
+ DCD ACE_PPE_Flag13_IRQHandler\r
+ DCD ACE_PPE_Flag14_IRQHandler\r
+ DCD ACE_PPE_Flag15_IRQHandler\r
+ DCD ACE_PPE_Flag16_IRQHandler\r
+ DCD ACE_PPE_Flag17_IRQHandler\r
+ DCD ACE_PPE_Flag18_IRQHandler\r
+ DCD ACE_PPE_Flag19_IRQHandler\r
+ DCD ACE_PPE_Flag20_IRQHandler\r
+ DCD ACE_PPE_Flag21_IRQHandler\r
+ DCD ACE_PPE_Flag22_IRQHandler\r
+ DCD ACE_PPE_Flag23_IRQHandler\r
+ DCD ACE_PPE_Flag24_IRQHandler\r
+ DCD ACE_PPE_Flag25_IRQHandler\r
+ DCD ACE_PPE_Flag26_IRQHandler\r
+ DCD ACE_PPE_Flag27_IRQHandler\r
+ DCD ACE_PPE_Flag28_IRQHandler\r
+ DCD ACE_PPE_Flag29_IRQHandler\r
+ DCD ACE_PPE_Flag30_IRQHandler\r
+ DCD ACE_PPE_Flag31_IRQHandler\r
+\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+ THUMB\r
+\r
+ PUBWEAK Reset_Handler\r
+ SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+; LDR R0, =SystemInit\r
+; BLX R0\r
+ LDR R0, =__iar_program_start\r
+ BX R0\r
+\r
+ PUBWEAK NMI_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+NMI_Handler\r
+ B NMI_Handler\r
+ \r
+ PUBWEAK HardFault_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+HardFault_Handler\r
+ B HardFault_Handler\r
+ \r
+ PUBWEAK MemManage_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+MemManage_Handler\r
+ B MemManage_Handler\r
+ \r
+ PUBWEAK BusFault_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+BusFault_Handler\r
+ B BusFault_Handler\r
+ \r
+ PUBWEAK UsageFault_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+UsageFault_Handler\r
+ B UsageFault_Handler\r
+ \r
+ PUBWEAK SVC_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+SVC_Handler\r
+ B SVC_Handler\r
+ \r
+ PUBWEAK DebugMon_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+DebugMon_Handler\r
+ B DebugMon_Handler\r
+ \r
+ PUBWEAK PendSV_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+PendSV_Handler\r
+ B PendSV_Handler\r
+ \r
+ PUBWEAK SysTick_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+SysTick_Handler\r
+ B SysTick_Handler\r
+\r
+ PUBWEAK WdogWakeup_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+WdogWakeup_IRQHandler\r
+ B WdogWakeup_IRQHandler\r
+ \r
+ PUBWEAK BrownOut_1_5V_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+BrownOut_1_5V_IRQHandler\r
+ B BrownOut_1_5V_IRQHandler\r
+ \r
+ PUBWEAK BrownOut_3_3V_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+BrownOut_3_3V_IRQHandler\r
+ B BrownOut_3_3V_IRQHandler\r
+ \r
+ PUBWEAK RTC_Match_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+RTC_Match_IRQHandler\r
+ B RTC_Match_IRQHandler\r
+ \r
+ PUBWEAK RTCIF_Pub_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+RTCIF_Pub_IRQHandler\r
+ B RTCIF_Pub_IRQHandler\r
+ \r
+ PUBWEAK EthernetMAC_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EthernetMAC_IRQHandler\r
+ B EthernetMAC_IRQHandler\r
+ \r
+ PUBWEAK IAP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+IAP_IRQHandler\r
+ B IAP_IRQHandler\r
+ \r
+ PUBWEAK ENVM0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ENVM0_IRQHandler\r
+ B ENVM0_IRQHandler\r
+ \r
+ PUBWEAK ENVM1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ENVM1_IRQHandler\r
+ B ENVM1_IRQHandler\r
+ \r
+ PUBWEAK DMA_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+DMA_IRQHandler\r
+ B DMA_IRQHandler\r
+ \r
+ PUBWEAK UART0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+UART0_IRQHandler\r
+ B UART0_IRQHandler\r
+ \r
+ PUBWEAK UART1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+UART1_IRQHandler\r
+ B UART1_IRQHandler\r
+ \r
+ PUBWEAK SPI0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+SPI0_IRQHandler\r
+ B SPI0_IRQHandler\r
+ \r
+ PUBWEAK SPI1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+SPI1_IRQHandler\r
+ B SPI1_IRQHandler\r
+ \r
+ PUBWEAK I2C0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+I2C0_IRQHandler\r
+ B I2C0_IRQHandler\r
+ \r
+ PUBWEAK I2C0_SMBAlert_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+I2C0_SMBAlert_IRQHandler\r
+ B I2C0_SMBAlert_IRQHandler\r
+\r
+ PUBWEAK I2C0_SMBus_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+I2C0_SMBus_IRQHandler\r
+ B I2C0_SMBus_IRQHandler\r
+ \r
+ PUBWEAK I2C1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+I2C1_IRQHandler\r
+ B I2C1_IRQHandler\r
+ \r
+ PUBWEAK I2C1_SMBAlert_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+I2C1_SMBAlert_IRQHandler\r
+ B I2C1_SMBAlert_IRQHandler\r
+ \r
+ PUBWEAK I2C1_SMBus_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+I2C1_SMBus_IRQHandler\r
+ B I2C1_SMBus_IRQHandler\r
+ \r
+ PUBWEAK Timer1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+Timer1_IRQHandler\r
+ B Timer1_IRQHandler\r
+ \r
+ PUBWEAK Timer2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+Timer2_IRQHandler\r
+ B Timer2_IRQHandler\r
+ \r
+ PUBWEAK PLL_Lock_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+PLL_Lock_IRQHandler\r
+ B PLL_Lock_IRQHandler\r
+ \r
+ PUBWEAK PLL_LockLost_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+PLL_LockLost_IRQHandler\r
+ B PLL_LockLost_IRQHandler\r
+ \r
+ PUBWEAK CommError_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+CommError_IRQHandler\r
+ B CommError_IRQHandler\r
+ \r
+ PUBWEAK Fabric_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+Fabric_IRQHandler\r
+ B Fabric_IRQHandler\r
+ \r
+ PUBWEAK GPIO0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO0_IRQHandler\r
+ B GPIO0_IRQHandler\r
+ \r
+ PUBWEAK GPIO1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO1_IRQHandler\r
+ B GPIO1_IRQHandler\r
+ \r
+ PUBWEAK GPIO2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO2_IRQHandler\r
+ B GPIO2_IRQHandler\r
+ \r
+ PUBWEAK GPIO3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO3_IRQHandler\r
+ B GPIO3_IRQHandler\r
+ \r
+ PUBWEAK GPIO4_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO4_IRQHandler\r
+ B GPIO4_IRQHandler\r
+ \r
+ PUBWEAK GPIO5_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO5_IRQHandler\r
+ B GPIO5_IRQHandler\r
+ \r
+ PUBWEAK GPIO6_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO6_IRQHandler\r
+ B GPIO6_IRQHandler\r
+ \r
+ PUBWEAK GPIO7_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO7_IRQHandler\r
+ B GPIO7_IRQHandler\r
+ \r
+ PUBWEAK GPIO8_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO8_IRQHandler\r
+ B GPIO8_IRQHandler\r
+ \r
+ PUBWEAK GPIO9_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO9_IRQHandler\r
+ B GPIO9_IRQHandler\r
+ \r
+ PUBWEAK GPIO10_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO10_IRQHandler\r
+ B GPIO10_IRQHandler\r
+ \r
+ PUBWEAK GPIO11_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO11_IRQHandler\r
+ B GPIO11_IRQHandler\r
+ \r
+ PUBWEAK GPIO12_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO12_IRQHandler\r
+ B GPIO12_IRQHandler\r
+ \r
+ PUBWEAK GPIO13_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO13_IRQHandler\r
+ B GPIO13_IRQHandler\r
+ \r
+ PUBWEAK GPIO14_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO14_IRQHandler\r
+ B GPIO14_IRQHandler\r
+ \r
+ PUBWEAK GPIO15_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO15_IRQHandler\r
+ B GPIO15_IRQHandler\r
+ \r
+ PUBWEAK GPIO16_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO16_IRQHandler\r
+ B GPIO16_IRQHandler\r
+ \r
+ PUBWEAK GPIO17_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO17_IRQHandler\r
+ B GPIO17_IRQHandler\r
+ \r
+ PUBWEAK GPIO18_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO18_IRQHandler\r
+ B GPIO18_IRQHandler\r
+ \r
+ PUBWEAK GPIO19_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO19_IRQHandler\r
+ B GPIO19_IRQHandler\r
+ \r
+ PUBWEAK GPIO20_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO20_IRQHandler\r
+ B GPIO20_IRQHandler\r
+ \r
+ PUBWEAK GPIO21_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO21_IRQHandler\r
+ B GPIO21_IRQHandler\r
+ \r
+ PUBWEAK GPIO22_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO22_IRQHandler\r
+ B GPIO22_IRQHandler\r
+ \r
+ PUBWEAK GPIO23_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO23_IRQHandler\r
+ B GPIO23_IRQHandler\r
+ \r
+ PUBWEAK GPIO24_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO24_IRQHandler\r
+ B GPIO24_IRQHandler\r
+ \r
+ PUBWEAK GPIO25_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO25_IRQHandler\r
+ B GPIO25_IRQHandler\r
+ \r
+ PUBWEAK GPIO26_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO26_IRQHandler\r
+ B GPIO26_IRQHandler\r
+ \r
+ PUBWEAK GPIO27_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO27_IRQHandler\r
+ B GPIO27_IRQHandler\r
+ \r
+ PUBWEAK GPIO28_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO28_IRQHandler\r
+ B GPIO28_IRQHandler\r
+ \r
+ PUBWEAK GPIO29_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO29_IRQHandler\r
+ B GPIO29_IRQHandler\r
+ \r
+ PUBWEAK GPIO30_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO30_IRQHandler\r
+ B GPIO30_IRQHandler\r
+ \r
+ PUBWEAK GPIO31_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+GPIO31_IRQHandler\r
+ B GPIO31_IRQHandler\r
+\r
+ PUBWEAK ACE_PC0_Flag0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PC0_Flag0_IRQHandler\r
+ B ACE_PC0_Flag0_IRQHandler\r
+\r
+ PUBWEAK ACE_PC0_Flag1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PC0_Flag1_IRQHandler\r
+ B ACE_PC0_Flag1_IRQHandler\r
+\r
+ PUBWEAK ACE_PC0_Flag2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PC0_Flag2_IRQHandler\r
+ B ACE_PC0_Flag2_IRQHandler\r
+\r
+ PUBWEAK ACE_PC0_Flag3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PC0_Flag3_IRQHandler\r
+ B ACE_PC0_Flag3_IRQHandler\r
+\r
+ PUBWEAK ACE_PC1_Flag0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PC1_Flag0_IRQHandler\r
+ B ACE_PC1_Flag0_IRQHandler\r
+\r
+ PUBWEAK ACE_PC1_Flag1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PC1_Flag1_IRQHandler\r
+ B ACE_PC1_Flag1_IRQHandler\r
+\r
+ PUBWEAK ACE_PC1_Flag2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PC1_Flag2_IRQHandler\r
+ B ACE_PC1_Flag2_IRQHandler\r
+\r
+ PUBWEAK ACE_PC1_Flag3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PC1_Flag3_IRQHandler\r
+ B ACE_PC1_Flag3_IRQHandler\r
+\r
+ PUBWEAK ACE_PC2_Flag0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PC2_Flag0_IRQHandler\r
+ B ACE_PC2_Flag0_IRQHandler\r
+\r
+ PUBWEAK ACE_PC2_Flag1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PC2_Flag1_IRQHandler\r
+ B ACE_PC2_Flag1_IRQHandler\r
+\r
+ PUBWEAK ACE_PC2_Flag2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PC2_Flag2_IRQHandler\r
+ B ACE_PC2_Flag2_IRQHandler\r
+\r
+ PUBWEAK ACE_PC2_Flag3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PC2_Flag3_IRQHandler\r
+ B ACE_PC2_Flag3_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC0_DataValid_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC0_DataValid_IRQHandler\r
+ B ACE_ADC0_DataValid_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC1_DataValid_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC1_DataValid_IRQHandler\r
+ B ACE_ADC1_DataValid_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC2_DataValid_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC2_DataValid_IRQHandler\r
+ B ACE_ADC2_DataValid_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC0_CalDone_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC0_CalDone_IRQHandler\r
+ B ACE_ADC0_CalDone_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC1_CalDone_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC1_CalDone_IRQHandler\r
+ B ACE_ADC1_CalDone_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC2_CalDone_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC2_CalDone_IRQHandler\r
+ B ACE_ADC2_CalDone_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC0_CalStart_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC0_CalStart_IRQHandler\r
+ B ACE_ADC0_CalStart_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC1_CalStart_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC1_CalStart_IRQHandler\r
+ B ACE_ADC1_CalStart_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC2_CalStart_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC2_CalStart_IRQHandler\r
+ B ACE_ADC2_CalStart_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp0_Fall_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp0_Fall_IRQHandler\r
+ B ACE_Comp0_Fall_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp1_Fall_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp1_Fall_IRQHandler\r
+ B ACE_Comp1_Fall_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp2_Fall_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp2_Fall_IRQHandler\r
+ B ACE_Comp2_Fall_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp3_Fall_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp3_Fall_IRQHandler\r
+ B ACE_Comp3_Fall_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp4_Fall_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp4_Fall_IRQHandler\r
+ B ACE_Comp4_Fall_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp5_Fall_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp5_Fall_IRQHandler\r
+ B ACE_Comp5_Fall_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp6_Fall_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp6_Fall_IRQHandler\r
+ B ACE_Comp6_Fall_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp7_Fall_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp7_Fall_IRQHandler\r
+ B ACE_Comp7_Fall_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp8_Fall_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp8_Fall_IRQHandler\r
+ B ACE_Comp8_Fall_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp9_Fall_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp9_Fall_IRQHandler\r
+ B ACE_Comp9_Fall_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp10_Fall_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp10_Fall_IRQHandler\r
+ B ACE_Comp10_Fall_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp11_Fall_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp11_Fall_IRQHandler\r
+ B ACE_Comp11_Fall_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp0_Rise_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp0_Rise_IRQHandler\r
+ B ACE_Comp0_Rise_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp1_Rise_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp1_Rise_IRQHandler\r
+ B ACE_Comp1_Rise_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp2_Rise_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp2_Rise_IRQHandler\r
+ B ACE_Comp2_Rise_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp3_Rise_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp3_Rise_IRQHandler\r
+ B ACE_Comp3_Rise_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp4_Rise_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp4_Rise_IRQHandler\r
+ B ACE_Comp4_Rise_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp5_Rise_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp5_Rise_IRQHandler\r
+ B ACE_Comp5_Rise_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp6_Rise_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp6_Rise_IRQHandler\r
+ B ACE_Comp6_Rise_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp7_Rise_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp7_Rise_IRQHandler\r
+ B ACE_Comp7_Rise_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp8_Rise_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp8_Rise_IRQHandler\r
+ B ACE_Comp8_Rise_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp9_Rise_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp9_Rise_IRQHandler\r
+ B ACE_Comp9_Rise_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp10_Rise_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp10_Rise_IRQHandler\r
+ B ACE_Comp10_Rise_IRQHandler\r
+\r
+ PUBWEAK ACE_Comp11_Rise_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_Comp11_Rise_IRQHandler\r
+ B ACE_Comp11_Rise_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC0_FifoFull_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC0_FifoFull_IRQHandler\r
+ B ACE_ADC0_FifoFull_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC0_FifoAFull_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC0_FifoAFull_IRQHandler\r
+ B ACE_ADC0_FifoAFull_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC0_FifoEmpty_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC0_FifoEmpty_IRQHandler\r
+ B ACE_ADC0_FifoEmpty_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC1_FifoFull_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC1_FifoFull_IRQHandler\r
+ B ACE_ADC1_FifoFull_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC1_FifoAFull_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC1_FifoAFull_IRQHandler\r
+ B ACE_ADC1_FifoAFull_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC1_FifoEmpty_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC1_FifoEmpty_IRQHandler\r
+ B ACE_ADC1_FifoEmpty_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC2_FifoFull_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC2_FifoFull_IRQHandler\r
+ B ACE_ADC2_FifoFull_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC2_FifoAFull_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC2_FifoAFull_IRQHandler\r
+ B ACE_ADC2_FifoAFull_IRQHandler\r
+\r
+ PUBWEAK ACE_ADC2_FifoEmpty_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_ADC2_FifoEmpty_IRQHandler\r
+ B ACE_ADC2_FifoEmpty_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag0_IRQHandler\r
+ B ACE_PPE_Flag0_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag1_IRQHandler\r
+ B ACE_PPE_Flag1_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag2_IRQHandler\r
+ B ACE_PPE_Flag2_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag3_IRQHandler\r
+ B ACE_PPE_Flag3_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag4_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag4_IRQHandler\r
+ B ACE_PPE_Flag4_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag5_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag5_IRQHandler\r
+ B ACE_PPE_Flag5_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag6_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag6_IRQHandler\r
+ B ACE_PPE_Flag6_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag7_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag7_IRQHandler\r
+ B ACE_PPE_Flag7_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag8_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag8_IRQHandler\r
+ B ACE_PPE_Flag8_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag9_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag9_IRQHandler\r
+ B ACE_PPE_Flag9_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag10_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag10_IRQHandler\r
+ B ACE_PPE_Flag10_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag11_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag11_IRQHandler\r
+ B ACE_PPE_Flag11_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag12_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag12_IRQHandler\r
+ B ACE_PPE_Flag12_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag13_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag13_IRQHandler\r
+ B ACE_PPE_Flag13_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag14_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag14_IRQHandler\r
+ B ACE_PPE_Flag14_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag15_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag15_IRQHandler\r
+ B ACE_PPE_Flag15_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag16_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag16_IRQHandler\r
+ B ACE_PPE_Flag16_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag17_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag17_IRQHandler\r
+ B ACE_PPE_Flag17_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag18_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag18_IRQHandler\r
+ B ACE_PPE_Flag18_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag19_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag19_IRQHandler\r
+ B ACE_PPE_Flag19_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag20_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag20_IRQHandler\r
+ B ACE_PPE_Flag20_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag21_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag21_IRQHandler\r
+ B ACE_PPE_Flag21_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag22_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag22_IRQHandler\r
+ B ACE_PPE_Flag22_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag23_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag23_IRQHandler\r
+ B ACE_PPE_Flag23_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag24_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag24_IRQHandler\r
+ B ACE_PPE_Flag24_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag25_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag25_IRQHandler\r
+ B ACE_PPE_Flag25_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag26_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag26_IRQHandler\r
+ B ACE_PPE_Flag26_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag27_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag27_IRQHandler\r
+ B ACE_PPE_Flag27_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag28_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag28_IRQHandler\r
+ B ACE_PPE_Flag28_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag29_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag29_IRQHandler\r
+ B ACE_PPE_Flag29_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag30_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag30_IRQHandler\r
+ B ACE_PPE_Flag30_IRQHandler\r
+\r
+ PUBWEAK ACE_PPE_Flag31_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ACE_PPE_Flag31_IRQHandler\r
+ B ACE_PPE_Flag31_IRQHandler\r
+\r
+ END\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * SmartFusion A2FxxxM3 CMSIS system initialization.\r
+ *\r
+ * SVN $Revision: 2069 $\r
+ * SVN $Date: 2010-01-28 00:23:48 +0000 (Thu, 28 Jan 2010) $\r
+ */\r
+#include "a2fxxxm3.h"\r
+#include "mss_assert.h"\r
+\r
+/* System frequency (FCLK) coming out of reset is 25MHz. */\r
+#define RESET_SYSCLCK_FREQ 25000000uL\r
+\r
+/*\r
+ * SmartFusion Microcontroller Subsystem FLCK frequency.\r
+ * The value of SMARTFUSION_FCLK_FREQ is used to report the system's clock\r
+ * frequency in system's which either do not use the Actel System Boot or\r
+ * a version of the Actel System Boot older than 1.3.1. In eitehr of these cases\r
+ * SMARTFUSION_FCLK_FREQ should be defined in the projects settings to reflect\r
+ * the FCLK frequency selected in the Libero MSS configurator.\r
+ * Systems using the Actel System Boot version 1.3.1 or later do not require this\r
+ * define since the system's frequency is retrieved from eNVM spare pages where\r
+ * the MSS Configurator stored the frequency selected during hardware design/configuration.\r
+ */\r
+#ifdef SMARTFUSION_FCLK_FREQ\r
+#define SMARTFUSION_FCLK_FREQ_DEFINED 1\r
+#else\r
+#define SMARTFUSION_FCLK_FREQ_DEFINED 0\r
+#define SMARTFUSION_FCLK_FREQ RESET_SYSCLCK_FREQ\r
+#endif\r
+\r
+/* Divider values for APB0, APB1 and ACE clocks. */\r
+#define RESET_PCLK0_DIV 4uL\r
+#define RESET_PCLK1_DIV 4uL\r
+#define RESET_ACE_DIV 4uL\r
+#define RESET_FPGA_CLK_DIV 4uL\r
+\r
+/* System register clock control mask and shift for PCLK dividers. */\r
+#define PCLK_DIV_MASK 0x00000003uL\r
+#define PCLK0_DIV_SHIFT 2uL\r
+#define PCLK1_DIV_SHIFT 4uL\r
+#define ACE_DIV_SHIFT 6uL\r
+\r
+/* System register MSS_CCC_DIV_CR mask and shift for GLB (FPGA fabric clock). */\r
+#define OBDIV_SHIFT 8uL\r
+#define OBDIV_MASK 0x0000001FuL\r
+#define OBDIVHALF_SHIFT 13uL\r
+#define OBDIVHALF_MASK 0x00000001uL\r
+\r
+/*\r
+ * Actel system boot version defines used to extract the system clock from eNVM\r
+ * spare pages.\r
+ * These defines allow detecting the presence of Actel system boot in eNVM spare\r
+ * pages and the version of that system boot executable and associated\r
+ * configuration data.\r
+ */\r
+#define SYSBOOT_KEY_ADDR (uint32_t *)0x6008081C\r
+#define SYSBOOT_KEY_VALUE 0x4C544341uL\r
+#define SYSBOOT_VERSION_ADDR (uint32_t *)0x60080840\r
+#define SYSBOOT_1_3_FCLK_ADDR (uint32_t *)0x6008162C\r
+#define SYSBOOT_2_x_FCLK_ADDR (uint32_t *)0x60081EAC\r
+\r
+/*\r
+ * The system boot version is stored in the least significant 24 bits of a word.\r
+ * The FCLK is stored in eNVM from version 1.3.1 of the system boot. We expect\r
+ * that the major version number of the system boot version will change if the\r
+ * system boot configuration data layout needs to change. \r
+ */\r
+#define SYSBOOT_VERSION_MASK 0x00FFFFFFuL\r
+#define MIN_SYSBOOT_VERSION 0x00010301uL\r
+#define SYSBOOT_VERSION_2_X 0x00020000uL\r
+#define MAX_SYSBOOT_VERSION 0x00030000uL\r
+\r
+/* Standard CMSIS global variables. */\r
+uint32_t SystemFrequency = SMARTFUSION_FCLK_FREQ; /*!< System Clock Frequency (Core Clock) */\r
+uint32_t SystemCoreClock = SMARTFUSION_FCLK_FREQ; /*!< System Clock Frequency (Core Clock) */\r
+\r
+/* SmartFusion specific clocks. */\r
+uint32_t g_FrequencyPCLK0 = (SMARTFUSION_FCLK_FREQ / RESET_PCLK0_DIV); /*!< Clock frequency of APB bus 0. */ \r
+uint32_t g_FrequencyPCLK1 = (SMARTFUSION_FCLK_FREQ / RESET_PCLK1_DIV); /*!< Clock frequency of APB bus 1. */\r
+uint32_t g_FrequencyACE = (SMARTFUSION_FCLK_FREQ / RESET_ACE_DIV); /*!< Clock frequency of Analog Compute Engine. */\r
+uint32_t g_FrequencyFPGA = (SMARTFUSION_FCLK_FREQ / RESET_FPGA_CLK_DIV); /*!< Clock frequecny of FPGA fabric */\r
+\r
+/* Local functions */\r
+static uint32_t GetSystemClock( void );\r
+\r
+/***************************************************************************//**\r
+ * See system_a2fm3fxxx.h for details.\r
+ */\r
+void SystemInit(void)\r
+{\r
+}\r
+\r
+/***************************************************************************//**\r
+ *\r
+ */\r
+void SystemCoreClockUpdate (void)\r
+{\r
+ uint32_t PclkDiv0;\r
+ uint32_t PclkDiv1;\r
+ uint32_t AceDiv;\r
+ uint32_t FabDiv;\r
+\r
+ const uint32_t pclk_div_lut[4] = { 1uL, 2uL, 4uL, 1uL };\r
+\r
+ /* Read PCLK dividers from system registers. Multiply the value read from\r
+ * system register by two to get actual divider value. */\r
+ PclkDiv0 = pclk_div_lut[((SYSREG->MSS_CLK_CR >> PCLK0_DIV_SHIFT) & PCLK_DIV_MASK)];\r
+ PclkDiv1 = pclk_div_lut[((SYSREG->MSS_CLK_CR >> PCLK1_DIV_SHIFT) & PCLK_DIV_MASK)];\r
+ AceDiv = pclk_div_lut[((SYSREG->MSS_CLK_CR >> ACE_DIV_SHIFT) & PCLK_DIV_MASK)];\r
+ {\r
+ /* Compute the FPGA fabric frequency divider. */\r
+ uint32_t obdiv;\r
+ uint32_t obdivhalf;\r
+ \r
+ obdiv = (SYSREG->MSS_CCC_DIV_CR >> OBDIV_SHIFT) & OBDIV_MASK;\r
+ obdivhalf = (SYSREG->MSS_CCC_DIV_CR >> OBDIVHALF_SHIFT) & OBDIVHALF_MASK;\r
+ FabDiv = obdiv + 1uL;\r
+ if ( obdivhalf != 0uL )\r
+ {\r
+ FabDiv = FabDiv * 2uL;\r
+ }\r
+ }\r
+ \r
+ /* Retrieve FCLK from eNVM spare pages if Actel system boot programmed as part of the system. */\r
+ \r
+ /* Read system clock from eNVM spare pages. */\r
+ SystemCoreClock = GetSystemClock();\r
+ g_FrequencyPCLK0 = SystemCoreClock / PclkDiv0;\r
+ g_FrequencyPCLK1 = SystemCoreClock / PclkDiv1;\r
+ g_FrequencyACE = SystemCoreClock / AceDiv;\r
+ g_FrequencyFPGA = SystemCoreClock / FabDiv;\r
+ \r
+ /* Keep SystemFrequency as well as SystemCoreClock for legacy reasons. */\r
+ SystemFrequency = SystemCoreClock;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * Retrieve the system clock frequency from eNVM spare page if available.\r
+ * Returns the frequency defined through SMARTFUSION_FCLK_FREQ if FCLK cannot be\r
+ * retrieved from eNVM spare pages.\r
+ * The FCLK frequency value selected in the MSS Configurator software tool is\r
+ * stored in eNVM spare pages as part of the Actel system boot configuration data.\r
+ */\r
+uint32_t GetSystemClock( void )\r
+{\r
+ uint32_t fclk = 0uL;\r
+ \r
+ uint32_t * p_sysboot_key = SYSBOOT_KEY_ADDR;\r
+ \r
+ if ( SYSBOOT_KEY_VALUE == *p_sysboot_key )\r
+ {\r
+ /* Actel system boot programmed, check if it has the FCLK value stored. */\r
+ uint32_t *p_sysboot_version = SYSBOOT_VERSION_ADDR;\r
+ uint32_t sysboot_version = *p_sysboot_version;\r
+ \r
+ sysboot_version &= SYSBOOT_VERSION_MASK;\r
+ \r
+ if ( sysboot_version >= MIN_SYSBOOT_VERSION )\r
+ {\r
+ /* Handle change of eNVM location of FCLK between 1.3.x and 2.x.x versions of the system boot. */\r
+ if ( sysboot_version < SYSBOOT_VERSION_2_X )\r
+ {\r
+ /* Read FCLK value from MSS configurator generated configuration\r
+ * data stored in eNVM spare pages as part of system boot version 1.3.x\r
+ * configuration tables. */\r
+ uint32_t *p_fclk = SYSBOOT_1_3_FCLK_ADDR;\r
+ fclk = *p_fclk;\r
+ }\r
+ else if ( sysboot_version < MAX_SYSBOOT_VERSION )\r
+ {\r
+ /* Read FCLK value from MSS configurator generated configuration\r
+ * data stored in eNVM spare pages as part of system boot version 2.x.x\r
+ * configuration tables. */\r
+ uint32_t *p_fclk = SYSBOOT_2_x_FCLK_ADDR;\r
+ fclk = *p_fclk;\r
+ }\r
+ else\r
+ {\r
+ fclk = 0uL;\r
+ }\r
+ }\r
+ }\r
+ \r
+ if ( 0uL == fclk )\r
+ {\r
+ /* \r
+ * Could not retrieve FCLK from system boot configuration data. Fall back\r
+ * to using SMARTFUSION_FCLK_FREQ which must then be defined as part of\r
+ * project settings.\r
+ */\r
+ ASSERT( SMARTFUSION_FCLK_FREQ_DEFINED );\r
+ fclk = SMARTFUSION_FCLK_FREQ;\r
+ }\r
+ \r
+ return fclk;\r
+}\r
+\r
--- /dev/null
+/*******************************************************************************\r
+ * (c) Copyright 2009 Actel Corporation. All rights reserved.\r
+ * \r
+ * SmartFusion A2FxxxM3 CMSIS system initialization.\r
+ *\r
+ * SVN $Revision: 2064 $\r
+ * SVN $Date: 2010-01-27 15:05:58 +0000 (Wed, 27 Jan 2010) $\r
+ */\r
+\r
+#ifndef __SYSTEM_A2FM3FXX_H__\r
+#define __SYSTEM_A2FM3FXX_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/* Standard CMSIS global variables. */\r
+extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+/* SmartFusion specific clocks. */\r
+extern uint32_t g_FrequencyPCLK0; /*!< Clock frequency of APB bus 0. */ \r
+extern uint32_t g_FrequencyPCLK1; /*!< Clock frequency of APB bus 1. */\r
+extern uint32_t g_FrequencyACE; /*!< Clock frequency of Analog Compute Engine. */\r
+extern uint32_t g_FrequencyFPGA; /*!< Clock frequecny of FPGA fabric */\r
+\r
+/***************************************************************************//**\r
+ * The SystemInit() is a standard CMSIS function called during system startup.\r
+ * It is meant to perform low level hardware setup such as configuring PLLs. In\r
+ * the case of SmartFusion these hardware setup operations are performed by the\r
+ * chip boot which executed before the application started. Therefore this\r
+ * function does not need to perform any hardware setup.\r
+ */\r
+void SystemInit(void);\r
+\r
+/***************************************************************************//**\r
+ * The SystemCoreClockUpdate() is a standard CMSIS function which can be called\r
+ * by the application in order to ensure that the SystemCoreClock global\r
+ * variable contains the up to date Cortex-M3 core frequency. Calling this\r
+ * function also updates the global variables containing the frequencies of the\r
+ * APB busses connecting the peripherals and the ACE frequency.\r
+ */\r
+void SystemCoreClockUpdate(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
projects / freertos / commitdiff