--- /dev/null
+This version supports only the cortex-M4F core. Future versions will also support the Cortex-M0 core.
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include "LPC43xx.h"\r
+#include "core_cm4.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 1\r
+#define configCPU_CLOCK_HZ ( 120000000UL )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 75 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. This example uses I2C to write to the LEDs. As\r
+this takes a finite time, and because a timer callback writes to an LED, the\r
+priority of the timer task is kept to a minimum to ensure it does not disrupt\r
+test tasks that check their own execution times. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 0 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 5 /* 32 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x1f\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+ \r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } \r
+ \r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/******************************************************************************/\r
+/* LPC43XX-FLASH-DEBUG.INI: External Memory Interface initialization for */\r
+/* LPC43xx first revision (Sept 2011). */\r
+/* The purpose is to be able to debug a program */\r
+/* located in the external flash. */\r
+/******************************************************************************/\r
+FUNC void Pre_Setup (void) {\r
+\r
+ /* configure M0 for infinite loop */\r
+ _WDWORD(0x10080000,0x00001F00); /* dummy stack pointer */\r
+ _WDWORD(0x10080004,0x000000D5); /* reset handler */\r
+ _WDWORD(0x100800D4,0xE7FEE7FE); /* jump to itself instruction for M0a */\r
+ _WDWORD(0x40043404,0x10080000); /* M0 shadow pointer. */\r
+ \r
+ /* release M0 from reset to allow Jtag access */\r
+ _WDWORD(0x40053104,(~(_RDWORD(0x40053154))) & (~(1<<24)));\r
+\r
+ // u32Val = (~(u32REG) & (~(1 << 24))); // clear the control bit \r
+ // LPC_RGU->RESET_CTRL1 = (~( LPC_RGU->RESET_ACTIVE_STATUS1 )) & (0 << 24); //Release M0\r
+\r
+}\r
+ \r
+ \r
+FUNC void Setup (void) \r
+{\r
+ // With the values used here, the program had to be linked to CS0 memory\r
+ // located at 0x1C000000 in the LPC43xx.\r
+\r
+/* This would be used in case there is a 16-byte header in the image */\r
+\r
+/*\r
+\r
+ SP = _RDWORD(0x1c000100); // Setup Stack Pointer\r
+ PC = _RDWORD(0x1C000104); // Setup Program Counter\r
+\r
+ _WDWORD(0xE000ED08, 0x1C000100); // Setup Vector Table Offset Register \r
+\r
+*/\r
+\r
+\r
+/* This is used for plain images, without a 16-byte header */\r
+\r
+ SP = _RDWORD(0x1C000000); // Setup Stack Pointer\r
+ PC = _RDWORD(0x1C000004); // Setup Program Counter\r
+\r
+ _WDWORD(0xE000ED08, 0x1C000000); // Setup Vector Table Offset Register \r
+\r
+} \r
+ \r
+ \r
+FUNC void emc_setup (void) \r
+{\r
+ // bus signals for external memory\r
+ _WDWORD(0x4008609C, 0x000000F3); /* P1_7: D0 (function 3) */\r
+ _WDWORD(0x400860A0, 0x000000F3); /* P1_8: D1 (function 3) */\r
+ _WDWORD(0x400860A4, 0x000000F3); /* P1_9: D2 (function 3) */\r
+ _WDWORD(0x400860A8, 0x000000F3); /* P1_10: D3 (function 3) */\r
+ _WDWORD(0x400860AC, 0x000000F3); /* P1_11: D4 (function 3) */\r
+ _WDWORD(0x400860B0, 0x000000F3); /* P1_12: D5 (function 3) */\r
+ _WDWORD(0x400860B4, 0x000000F3); /* P1_13: D6 (function 3) */\r
+ _WDWORD(0x400860B8, 0x000000F3); /* P1_14: D7 (function 3) */\r
+ _WDWORD(0x40086280, 0x000000F2); /* P5_0: D12 (function 2) */\r
+ _WDWORD(0x40086284, 0x000000F2); /* P5_1: D13 (function 2) */\r
+ _WDWORD(0x40086288, 0x000000F2); /* P5_2: D14 (function 2) */\r
+ _WDWORD(0x4008628C, 0x000000F2); /* P5_3: D15 (function 2) */\r
+ _WDWORD(0x40086290, 0x000000F2); /* P5_4: D8 (function 2) */\r
+ _WDWORD(0x40086294, 0x000000F2); /* P5_5: D9 (function 2) */\r
+ _WDWORD(0x40086298, 0x000000F2); /* P5_6: D10 (function 2) */\r
+ _WDWORD(0x4008629C, 0x000000F2); /* P5_7: D11 (function 2) */\r
+ _WDWORD(0x40086688, 0x000000F2); /* PD_2: D16 (function 2) */\r
+ _WDWORD(0x4008668C, 0x000000F2); /* PD_3: D17 (function 2) */\r
+ _WDWORD(0x40086690, 0x000000F2); /* PD_4: D18 (function 2) */\r
+ _WDWORD(0x40086694, 0x000000F2); /* PD_5: D19 (function 2) */\r
+ _WDWORD(0x40086698, 0x000000F2); /* PD_6: D20 (function 2) */\r
+ _WDWORD(0x4008669C, 0x000000F2); /* PD_7: D21 (function 2) */\r
+ _WDWORD(0x400866A0, 0x000000F2); /* PD_8: D22 (function 2) */\r
+ _WDWORD(0x400866A4, 0x000000F2); /* PD_9: D23 (function 2) */\r
+ _WDWORD(0x40086714, 0x000000F3); /* PE_5: D24 (function 3) */\r
+ _WDWORD(0x40086718, 0x000000F3); /* PE_6: D25 (function 3) */\r
+ _WDWORD(0x4008671C, 0x000000F3); /* PE_7: D26 (function 3) */\r
+ _WDWORD(0x40086720, 0x000000F3); /* PE_8: D27 (function 3) */\r
+ _WDWORD(0x40086724, 0x000000F3); /* PE_9: D28 (function 3) */\r
+ _WDWORD(0x40086728, 0x000000F3); /* PE_10: D29 (function 3) */\r
+ _WDWORD(0x4008672C, 0x000000F3); /* PE_11: D30 (function 3) */\r
+ _WDWORD(0x40086730, 0x000000F3); /* PE_12: D31 (function 3) */\r
+ \r
+ _WDWORD(0x40086124, 0x000000F3); /* P2_9: A0 (function 3) */\r
+ _WDWORD(0x40086128, 0x000000F3); /* P2_10: A1 (function 3) */\r
+ _WDWORD(0x4008612C, 0x000000F3); /* P2_11: A2 (function 3) */\r
+ _WDWORD(0x40086130, 0x000000F3); /* P2_12: A3 (function 3) */\r
+ _WDWORD(0x40086134, 0x000000F3); /* P2_13: A4 (function 3) */\r
+ _WDWORD(0x40086080, 0x000000F2); /* P1_0: A5 (function 2) */\r
+ _WDWORD(0x40086084, 0x000000F2); /* P1_1: A6 (function 2) */\r
+ _WDWORD(0x40086088, 0x000000F2); /* P1_2: A7 (function 2) */ \r
+ _WDWORD(0x40086120, 0x000000F3); /* P2_8: A8 (function 3) */\r
+ _WDWORD(0x4008611C, 0x000000F3); /* P2_7: A9 (function 3) */\r
+ _WDWORD(0x40086118, 0x000000F2); /* P2_6: A10 (function 2) */\r
+ _WDWORD(0x40086108, 0x000000F2); /* P2_2: A11 (function 2) */\r
+ _WDWORD(0x40086104, 0x000000F2); /* P2_1: A12 (function 2) */\r
+ _WDWORD(0x40086100, 0x000000F2); /* P2_0: A13 (function 2) */\r
+ _WDWORD(0x40086320, 0x000000F1); /* P6_8: A14 (function 1) */\r
+ _WDWORD(0x4008631C, 0x000000F1); /* P6_7: A15 (function 1) */\r
+ _WDWORD(0x400866C0, 0x000000F2); /* PD_16: A16 (function 2) */\r
+ _WDWORD(0x400866BC, 0x000000F2); /* PD_15: A17 (function 2) */\r
+ _WDWORD(0x40086700, 0x000000F3); /* PE_0: A18 (function 3) */\r
+ _WDWORD(0x40086704, 0x000000F3); /* PE_1: A19 (function 3) */\r
+ _WDWORD(0x40086708, 0x000000F3); /* PE_2: A20 (function 3) */\r
+ _WDWORD(0x4008670C, 0x000000F3); /* PE_3: A21 (function 3) */\r
+ _WDWORD(0x40086710, 0x000000F3); /* PE_4: A22 (function 3) */\r
+\r
+ // control signals for static memory\r
+ _WDWORD(0x40086094, 0x000000F3); /* P1_5: CS0 (function 3) */\r
+ _WDWORD(0x400866B0, 0x000000F2); /* PD_12: CS2 (function 2) */\r
+ _WDWORD(0x40086098, 0x000000F3); /* P1_6: WE (function 3) */\r
+ _WDWORD(0x4008608C, 0x000000F3); /* P1_3: OE (function 3) */\r
+ _WDWORD(0x40086090, 0x000000F3); /* P1_4: BLS0 (function 3) */\r
+ _WDWORD(0x40086318, 0x000000F1); /* P6_6: BLS1 (function 1) */\r
+\r
+ // configure EMC static memory registers\r
+ _WDWORD(0x40005000, 0x00000001); /* Enable the EMC block */\r
+\r
+ _WDWORD(0x40005200, 0x00000081); /* CS0: 16 bit, WE */\r
+ _WDWORD(0x40005208, 0x00000000); /* CS0: WAITOEN = 0 */\r
+ _WDWORD(0x4000520C, 0x00000008); /* CS0: WAITRD = 8 @120MHz for 70ns flash */\r
+\r
+ _WDWORD(0x40005240, 0x00000081); /* CS2: 16 bit, WE */\r
+ _WDWORD(0x40005248, 0x00000000); /* CS2: WAITOEN = 0 */\r
+ _WDWORD(0x4000524C, 0x00000007); /* CS2: WAITRD = 7 */\r
+}\r
+\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* */\r
+/* */\r
+/******************************************************************************/ \r
+\r
+_sleep_(100);\r
+\r
+//Pre_setup();\r
+\r
+// Just set up the memory interface to enable the correct access to the external\r
+// flash memory on CS0.\r
+emc_setup();\r
+\r
+\r
+// Download the image. This is not a physical download as the image is \r
+// (already) in the flash.\r
+// If working with ULINK devices an alternative is to check the checkbox "Load Application at Startup" in the \r
+// debug settings of µVision (comment the LOAD instruction out).\r
+// This mechanism is not used here, because somehow it does not work with the JLINK devices.\r
+LOAD Flash\LPC43xx_M4_FLASH.axf INCREMENTAL\r
+\r
+\r
+\r
+\r
+\r
+// Setup for running from a specific memory location\r
+Setup();\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/******************************************************************************/\r
+/* LPC43XX-FLASH-PROGRAM.INI: External Memory Interface initialization for */\r
+/* LPC43xx first revision (Sept 2011). */\r
+/* The purpose is to be able to program the */ \r
+/* external flash using the KEIL µVision utility. */\r
+/******************************************************************************/\r
+ \r
+ \r
+ \r
+FUNC void emc_setup (void) \r
+{\r
+ // bus signals for external memory\r
+ _WDWORD(0x4008609C, 0x000000F3); /* P1_7: D0 (function 3) */\r
+ _WDWORD(0x400860A0, 0x000000F3); /* P1_8: D1 (function 3) */\r
+ _WDWORD(0x400860A4, 0x000000F3); /* P1_9: D2 (function 3) */\r
+ _WDWORD(0x400860A8, 0x000000F3); /* P1_10: D3 (function 3) */\r
+ _WDWORD(0x400860AC, 0x000000F3); /* P1_11: D4 (function 3) */\r
+ _WDWORD(0x400860B0, 0x000000F3); /* P1_12: D5 (function 3) */\r
+ _WDWORD(0x400860B4, 0x000000F3); /* P1_13: D6 (function 3) */\r
+ _WDWORD(0x400860B8, 0x000000F3); /* P1_14: D7 (function 3) */\r
+ _WDWORD(0x40086280, 0x000000F2); /* P5_0: D12 (function 2) */\r
+ _WDWORD(0x40086284, 0x000000F2); /* P5_1: D13 (function 2) */\r
+ _WDWORD(0x40086288, 0x000000F2); /* P5_2: D14 (function 2) */\r
+ _WDWORD(0x4008628C, 0x000000F2); /* P5_3: D15 (function 2) */\r
+ _WDWORD(0x40086290, 0x000000F2); /* P5_4: D8 (function 2) */\r
+ _WDWORD(0x40086294, 0x000000F2); /* P5_5: D9 (function 2) */\r
+ _WDWORD(0x40086298, 0x000000F2); /* P5_6: D10 (function 2) */\r
+ _WDWORD(0x4008629C, 0x000000F2); /* P5_7: D11 (function 2) */\r
+ _WDWORD(0x40086688, 0x000000F2); /* PD_2: D16 (function 2) */\r
+ _WDWORD(0x4008668C, 0x000000F2); /* PD_3: D17 (function 2) */\r
+ _WDWORD(0x40086690, 0x000000F2); /* PD_4: D18 (function 2) */\r
+ _WDWORD(0x40086694, 0x000000F2); /* PD_5: D19 (function 2) */\r
+ _WDWORD(0x40086698, 0x000000F2); /* PD_6: D20 (function 2) */\r
+ _WDWORD(0x4008669C, 0x000000F2); /* PD_7: D21 (function 2) */\r
+ _WDWORD(0x400866A0, 0x000000F2); /* PD_8: D22 (function 2) */\r
+ _WDWORD(0x400866A4, 0x000000F2); /* PD_9: D23 (function 2) */\r
+ _WDWORD(0x40086714, 0x000000F3); /* PE_5: D24 (function 3) */\r
+ _WDWORD(0x40086718, 0x000000F3); /* PE_6: D25 (function 3) */\r
+ _WDWORD(0x4008671C, 0x000000F3); /* PE_7: D26 (function 3) */\r
+ _WDWORD(0x40086720, 0x000000F3); /* PE_8: D27 (function 3) */\r
+ _WDWORD(0x40086724, 0x000000F3); /* PE_9: D28 (function 3) */\r
+ _WDWORD(0x40086728, 0x000000F3); /* PE_10: D29 (function 3) */\r
+ _WDWORD(0x4008672C, 0x000000F3); /* PE_11: D30 (function 3) */\r
+ _WDWORD(0x40086730, 0x000000F3); /* PE_12: D31 (function 3) */\r
+ \r
+ _WDWORD(0x40086124, 0x000000F3); /* P2_9: A0 (function 3) */\r
+ _WDWORD(0x40086128, 0x000000F3); /* P2_10: A1 (function 3) */\r
+ _WDWORD(0x4008612C, 0x000000F3); /* P2_11: A2 (function 3) */\r
+ _WDWORD(0x40086130, 0x000000F3); /* P2_12: A3 (function 3) */\r
+ _WDWORD(0x40086134, 0x000000F3); /* P2_13: A4 (function 3) */\r
+ _WDWORD(0x40086080, 0x000000F2); /* P1_0: A5 (function 2) */\r
+ _WDWORD(0x40086084, 0x000000F2); /* P1_1: A6 (function 2) */\r
+ _WDWORD(0x40086088, 0x000000F2); /* P1_2: A7 (function 2) */ \r
+ _WDWORD(0x40086120, 0x000000F3); /* P2_8: A8 (function 3) */\r
+ _WDWORD(0x4008611C, 0x000000F3); /* P2_7: A9 (function 3) */\r
+ _WDWORD(0x40086118, 0x000000F2); /* P2_6: A10 (function 2) */\r
+ _WDWORD(0x40086108, 0x000000F2); /* P2_2: A11 (function 2) */\r
+ _WDWORD(0x40086104, 0x000000F2); /* P2_1: A12 (function 2) */\r
+ _WDWORD(0x40086100, 0x000000F2); /* P2_0: A13 (function 2) */\r
+ _WDWORD(0x40086320, 0x000000F1); /* P6_8: A14 (function 1) */\r
+ _WDWORD(0x4008631C, 0x000000F1); /* P6_7: A15 (function 1) */\r
+ _WDWORD(0x400866C0, 0x000000F2); /* PD_16: A16 (function 2) */\r
+ _WDWORD(0x400866BC, 0x000000F2); /* PD_15: A17 (function 2) */\r
+ _WDWORD(0x40086700, 0x000000F3); /* PE_0: A18 (function 3) */\r
+ _WDWORD(0x40086704, 0x000000F3); /* PE_1: A19 (function 3) */\r
+ _WDWORD(0x40086708, 0x000000F3); /* PE_2: A20 (function 3) */\r
+ _WDWORD(0x4008670C, 0x000000F3); /* PE_3: A21 (function 3) */\r
+ _WDWORD(0x40086710, 0x000000F3); /* PE_4: A22 (function 3) */\r
+\r
+ // signals for static memory\r
+ _WDWORD(0x40086094, 0x000000F3); /* P1_5: CS0 (function 3) */\r
+ _WDWORD(0x400866B0, 0x000000F2); /* PD_12: CS2 (function 2) */\r
+ _WDWORD(0x40086098, 0x000000F3); /* P1_6: WE (function 3) */\r
+ _WDWORD(0x4008608C, 0x000000F3); /* P1_3: OE (function 3) */\r
+ _WDWORD(0x40086090, 0x000000F3); /* P1_4: BLS0 (function 3) */\r
+ _WDWORD(0x40086318, 0x000000F1); /* P6_6: BLS1 (function 1) */\r
+\r
+\r
+ // configure EMC static memory registers\r
+ _WDWORD(0x40005000, 0x00000001); /* Enable */\r
+\r
+ _WDWORD(0x40005200, 0x00000081); /* CS0: 16 bit, WE */\r
+ _WDWORD(0x40005208, 0x00000000); /* CS0: WAITOEN = 0 */\r
+ _WDWORD(0x4000520C, 0x00000008); /* CS0: WAITRD = 8 */\r
+\r
+ _WDWORD(0x40005240, 0x00000081); /* CS2: 16 bit, WE */\r
+ _WDWORD(0x40005248, 0x00000000); /* CS2: WAITOEN = 0 */\r
+ _WDWORD(0x4000524C, 0x00000007); /* CS2: WAITRD = 7 */\r
+}\r
+\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* */\r
+/* */\r
+/******************************************************************************/ \r
+\r
+_sleep_(100);\r
+\r
+\r
+// Just set up the memory interface to enable the correct access to the external\r
+// flash memory on CS0.\r
+emc_setup();\r
+\r
+\r
+\r
+\r
+\r
+
\ No newline at end of file
--- /dev/null
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+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\Common\Minimal\semtest.c</PathWithFileName>
+ <FilenameWithoutPath>semtest.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Peripheral_Library</GroupName>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>0</GroupNumber>
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+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
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+ <PathWithFileName>..\platform\M4_PeripheralLibraryFiles\lpc43xx_i2c.c</PathWithFileName>
+ <FilenameWithoutPath>lpc43xx_i2c.c</FilenameWithoutPath>
+ </File>
+ <File>
+ <GroupNumber>0</GroupNumber>
+ <FileNumber>0</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
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+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\platform\M4_PeripheralLibraryFiles\lpc43xx_cgu.c</PathWithFileName>
+ <FilenameWithoutPath>lpc43xx_cgu.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <MDIGroups>
+ <Orientation>1</Orientation>
+ <ActiveMDIGroup>0</ActiveMDIGroup>
+ <MDIGroup>
+ <Size>100</Size>
+ <ActiveTab>0</ActiveTab>
+ <Documents>
+ <Doc>
+ <Name>.\main.c</Name>
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+ <TopLine>52</TopLine>
+ <CurrentLine>52</CurrentLine>
+ </Doc>
+ </Documents>
+ </MDIGroup>
+ </MDIGroups>
+
+</ProjectOpt>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>LPC43xx_M4_FLASH</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M4 FPU</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>5237</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath>NXP\LPC17xx\</RegisterFilePath>
+ <DBRegisterFilePath>NXP\LPC17xx\</DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\FLASH\</OutputDirectory>
+ <OutputName>LPC43xx_M4_FLASH</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>1</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\FLASH\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>1</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>fromelf --bin -o "$L@L.bin" "$L@L.axf"</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DLM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pEMBER</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TLM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments></TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>0</RestoreWatchpoints>
+ <RestoreMemoryDisplay>0</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>0</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile>.\LPC43XX-M4-FLASH-DEBUG.ini</InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4096</DriverSelection>
+ </Flash1>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4>.\LPC43XX-M4-FLASH-PROGRAM.ini</Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>0</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M4"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>0</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>0</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>0</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x10000000</StartAddress>
+ <Size>0x8000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x80000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls>--no_allow_fpreg_for_nonfpdata</MiscControls>
+ <Define>CORE_M4</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\system;..\platform;..\..\Common\include;..\M4;..\..\..\Source\include;..\..\..\Source\portable\RVDS\ARM_CM4F;..\platform\M4_PeripheralLibraryFiles</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>1</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>NO_CRP EXT_FLASH</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x10000000</TextAddressRange>
+ <DataAddressRange>0x10004000</DataAddressRange>
+ <ScatterFile>..\platform\M4_Flash.sct</ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc>--debug --pad=0xFF</Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings>6312</DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>System Code</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_LPC43xx.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\platform\startup_LPC43xx.s</FilePath>
+ </File>
+ <File>
+ <FileName>system_LPC43xx.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\system\system_LPC43xx.c</FilePath>
+ </File>
+ <File>
+ <FileName>core_cm4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\system\core_cm4.c</FilePath>
+ </File>
+ <File>
+ <FileName>emc_LPC43xx.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\system\emc_LPC43xx.c</FilePath>
+ </File>
+ <File>
+ <FileName>scu.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\system\scu.c</FilePath>
+ </File>
+ <File>
+ <FileName>fpu_init.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\system\fpu_init.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Platform</GroupName>
+ <Files>
+ <File>
+ <FileName>platform_config.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\platform\platform_config.h</FilePath>
+ </File>
+ <File>
+ <FileName>platform_config.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\platform\platform_config.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Application_Source</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ <File>
+ <FileName>ParTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\ParTest.c</FilePath>
+ </File>
+ <File>
+ <FileName>RegTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\RegTest.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>FreeRTOS_Source</GroupName>
+ <Files>
+ <File>
+ <FileName>port.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath>
+ </File>
+ <File>
+ <FileName>heap_2.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\MemMang\heap_2.c</FilePath>
+ </File>
+ <File>
+ <FileName>timers.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\timers.c</FilePath>
+ </File>
+ <File>
+ <FileName>list.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\list.c</FilePath>
+ </File>
+ <File>
+ <FileName>queue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\queue.c</FilePath>
+ </File>
+ <File>
+ <FileName>tasks.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\tasks.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Common_Demo_Source</GroupName>
+ <Files>
+ <File>
+ <FileName>sp_flop.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\sp_flop.c</FilePath>
+ </File>
+ <File>
+ <FileName>BlockQ.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\BlockQ.c</FilePath>
+ </File>
+ <File>
+ <FileName>blocktim.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\blocktim.c</FilePath>
+ </File>
+ <File>
+ <FileName>countsem.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\countsem.c</FilePath>
+ </File>
+ <File>
+ <FileName>death.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\death.c</FilePath>
+ </File>
+ <File>
+ <FileName>dynamic.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\dynamic.c</FilePath>
+ </File>
+ <File>
+ <FileName>flash.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\flash.c</FilePath>
+ </File>
+ <File>
+ <FileName>GenQTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\GenQTest.c</FilePath>
+ </File>
+ <File>
+ <FileName>integer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\integer.c</FilePath>
+ </File>
+ <File>
+ <FileName>PollQ.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\PollQ.c</FilePath>
+ </File>
+ <File>
+ <FileName>recmutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\recmutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>semtest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\semtest.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Peripheral_Library</GroupName>
+ <Files>
+ <File>
+ <FileName>lpc43xx_i2c.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\platform\M4_PeripheralLibraryFiles\lpc43xx_i2c.c</FilePath>
+ </File>
+ <File>
+ <FileName>lpc43xx_cgu.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\platform\M4_PeripheralLibraryFiles\lpc43xx_cgu.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Normally, a demo application would define ParTest (parallel port test) \r
+ * functions to write to an LED. In this case, four '*' symbols that are\r
+ * output to the debug printf() port are used to simulate LED outputs.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+/* Library includes. */\r
+#include "lpc43xx_i2c.h"\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Standard demo include. */\r
+#include "partest.h"\r
+\r
+/* The number of LED outputs. */\r
+#define partstMAX_LEDS 4\r
+\r
+/* Commands written to the PCA9502. */\r
+#define partstIO_WRITE_COMMAND ( ( unsigned char ) ( 0x0BU << 3U ) )\r
+#define partstIO_DIR_COMMAND ( ( unsigned char ) ( 0x0AU << 3U ) )\r
+#define partstSLAVE_ADDRESS ( ( unsigned char ) ( 0x9AU >> 1U ) )\r
+\r
+/* Just defines the length of the queue used to pass toggle commands to the I2C\r
+gatekeeper task. */\r
+#define partstLED_COMMAND_QUEUE_LENGTH ( 6 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The LEDs are connected to an I2C port expander. Therefore, writing to an\r
+ * LED takes longer than might be expected if the LED was connected directly\r
+ * to a GPIO pin. As several tasks, and a timer, toggle LEDs, it is convenient\r
+ * to use a gatekeeper task to ensure access is both mutually exclusive and\r
+ * serialised. Tasks other than this gatekeeper task must not access the I2C\r
+ * port directly.\r
+ */\r
+static void prvI2CGateKeeperTask( void *pvParameters );\r
+\r
+/* The queue used to communicate toggle commands with the I2C gatekeeper \r
+task. */\r
+static xQueueHandle xI2CCommandQueue = NULL;\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+unsigned char ucBuffer[ 2 ];\r
+I2C_M_SETUP_Type xI2CMessage;\r
+\r
+ /* The LEDs are on an I2C IO expander. Initialise the I2C interface. */\r
+ I2C_Init( LPC_I2C0, 300000 );\r
+ I2C_Cmd( LPC_I2C0, ENABLE );\r
+\r
+ /* GPIO0-GPIO2 to output. */\r
+ ucBuffer[ 0 ] = partstIO_DIR_COMMAND;\r
+ ucBuffer[ 1 ] = 0x0f;\r
+ xI2CMessage.sl_addr7bit = partstSLAVE_ADDRESS;\r
+ xI2CMessage.tx_data = ucBuffer ;\r
+ xI2CMessage.tx_length = sizeof( ucBuffer );\r
+ xI2CMessage.rx_data = NULL;\r
+ xI2CMessage.rx_length = 0;\r
+ xI2CMessage.retransmissions_max = 3;\r
+ I2C_MasterTransferData( LPC_I2C0, &xI2CMessage, I2C_TRANSFER_POLLING );\r
+\r
+ /* Create the mutex used to guard access to the I2C bus. */\r
+ xI2CCommandQueue = xQueueCreate( partstLED_COMMAND_QUEUE_LENGTH, sizeof( unsigned char ) );\r
+ configASSERT( xI2CCommandQueue );\r
+\r
+ /* Create the I2C gatekeeper task itself. */\r
+ xTaskCreate( prvI2CGateKeeperTask, ( signed char * ) "I2C", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned long ulLED )\r
+{\r
+unsigned char ucLED = ( unsigned char ) ulLED;\r
+\r
+ /* Only the gatekeeper task will actually access the I2C port, so send the\r
+ toggle request to the gatekeeper task. A block time of zero is used as\r
+ this function is called by a software timer callback. */\r
+ xQueueSend( xI2CCommandQueue, &ucLED, 0UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvI2CGateKeeperTask( void *pvParameters )\r
+{\r
+unsigned char ucBuffer[ 2 ], ucLED;\r
+static unsigned char ucLEDState = 0xffU;\r
+static I2C_M_SETUP_Type xI2CMessage; /* Static so it is not on the stack as this is called from task code. */\r
+\r
+ /* Just to remove compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for the next command. */\r
+ xQueueReceive( xI2CCommandQueue, &ucLED, portMAX_DELAY );\r
+\r
+ /* Only this task is allowed to touch the I2C port, so there is no need\r
+ for additional mutual exclusion. */\r
+ if( ucLED < partstMAX_LEDS )\r
+ {\r
+ /* Which bit is being manipulated? */\r
+ ucLED = 0x01 << ucLED;\r
+ \r
+ /* Is the bit currently set or clear? */\r
+ if( ( ucLEDState & ucLED ) == 0U )\r
+ {\r
+ ucLEDState |= ucLED;\r
+ }\r
+ else\r
+ {\r
+ ucLEDState &= ~ucLED;\r
+ }\r
+ \r
+ ucBuffer[ 0 ] = partstIO_WRITE_COMMAND;\r
+ ucBuffer[ 1 ] = ucLEDState;\r
+ \r
+ xI2CMessage.sl_addr7bit = partstSLAVE_ADDRESS;\r
+ xI2CMessage.tx_data = ucBuffer ;\r
+ xI2CMessage.tx_length = sizeof( ucBuffer );\r
+ xI2CMessage.rx_data = NULL;\r
+ xI2CMessage.rx_length = 0;\r
+ xI2CMessage.retransmissions_max = 3;\r
+ I2C_MasterTransferData( LPC_I2C0, &xI2CMessage, I2C_TRANSFER_POLLING );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+__asm vRegTest1Task( void )\r
+{\r
+ PRESERVE8\r
+ IMPORT ulRegTest1LoopCounter\r
+\r
+ /* Fill the core registers with known values. */\r
+ mov r0, #100\r
+ mov r1, #101\r
+ mov r2, #102\r
+ mov r3, #103\r
+ mov r4, #104\r
+ mov r5, #105\r
+ mov r6, #106\r
+ mov r7, #107\r
+ mov r8, #108\r
+ mov r9, #109\r
+ mov r10, #110\r
+ mov r11, #111\r
+ mov r12, #112\r
+\r
+ /* Fill the VFP registers with known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg1_loop\r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+ \r
+ vmov r0, r1, d0\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ \r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+ \r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg1_loopf_pass\r
+\r
+reg1_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg1_error_loopf\r
+\r
+reg1_loopf_pass\r
+\r
+ cmp r0, #100\r
+ bne reg1_error_loop\r
+ cmp r1, #101\r
+ bne reg1_error_loop\r
+ cmp r2, #102\r
+ bne reg1_error_loop\r
+ cmp r3, #103\r
+ bne reg1_error_loop\r
+ cmp r4, #104\r
+ bne reg1_error_loop\r
+ cmp r5, #105\r
+ bne reg1_error_loop\r
+ cmp r6, #106\r
+ bne reg1_error_loop\r
+ cmp r7, #107\r
+ bne reg1_error_loop\r
+ cmp r8, #108\r
+ bne reg1_error_loop\r
+ cmp r9, #109\r
+ bne reg1_error_loop\r
+ cmp r10, #110\r
+ bne reg1_error_loop\r
+ cmp r11, #111\r
+ bne reg1_error_loop\r
+ cmp r12, #112\r
+ bne reg1_error_loop\r
+ \r
+ /* Everything passed, increment the loop counter. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest1LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+ \r
+ /* Start again. */\r
+ b reg1_loop\r
+\r
+reg1_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ b reg1_error_loop\r
+ nop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm vRegTest2Task( void )\r
+{\r
+ PRESERVE8\r
+ IMPORT ulRegTest2LoopCounter\r
+\r
+ /* Set all the core registers to known values. */\r
+ mov r0, #-1\r
+ mov r1, #1\r
+ mov r2, #2\r
+ mov r3, #3\r
+ mov r4, #4\r
+ mov r5, #5\r
+ mov r6, #6\r
+ mov r7, #7\r
+ mov r8, #8\r
+ mov r9, #9\r
+ mov r10, #10\r
+ mov r11, #11\r
+ mov r12, #12\r
+\r
+ /* Set all the VFP to known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg2_loop\r
+ \r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+ \r
+ vmov r0, r1, d0\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ \r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+ \r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg2_loopf_pass\r
+\r
+reg2_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg2_error_loopf\r
+\r
+reg2_loopf_pass\r
+\r
+ cmp r0, #-1\r
+ bne reg2_error_loop\r
+ cmp r1, #1\r
+ bne reg2_error_loop\r
+ cmp r2, #2\r
+ bne reg2_error_loop\r
+ cmp r3, #3\r
+ bne reg2_error_loop\r
+ cmp r4, #4\r
+ bne reg2_error_loop\r
+ cmp r5, #5\r
+ bne reg2_error_loop\r
+ cmp r6, #6\r
+ bne reg2_error_loop\r
+ cmp r7, #7\r
+ bne reg2_error_loop\r
+ cmp r8, #8\r
+ bne reg2_error_loop\r
+ cmp r9, #9\r
+ bne reg2_error_loop\r
+ cmp r10, #10\r
+ bne reg2_error_loop\r
+ cmp r11, #11\r
+ bne reg2_error_loop\r
+ cmp r12, #12\r
+ bne reg2_error_loop\r
+ \r
+ /* Increment the loop counter to indicate this test is still functioning\r
+ correctly. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest2LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+ \r
+ /* Start again. */\r
+ b reg2_loop\r
+\r
+reg2_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ This loop ensures the loop counter variable stops incrementing. */\r
+ b reg2_error_loop\r
+ nop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue )\r
+{\r
+ PRESERVE8\r
+\r
+ /* Clobber the auto saved registers. */\r
+ vmov d0, r0, r0\r
+ vmov d1, r0, r0\r
+ vmov d2, r0, r0\r
+ vmov d3, r0, r0\r
+ vmov d4, r0, r0\r
+ vmov d5, r0, r0\r
+ vmov d6, r0, r0\r
+ vmov d7, r0, r0\r
+ bx lr\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue )\r
+{\r
+ PRESERVE8\r
+\r
+ vmov r1, s0\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s1\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s2\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s3\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s4\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s5\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s6\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s7\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s8\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s9\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s10\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s11\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s12\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s13\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s14\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s15\r
+ cmp r0, r1\r
+ bne return_error\r
+ \r
+return_pass\r
+ mov r0, #1\r
+ bx lr\r
+\r
+return_error\r
+ mov r0, #0\r
+ bx lr\r
+}\r
+\r
+ \r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/******************************************************************************\r
+ * >>>>>> NOTE 1: <<<<<<\r
+ *\r
+ * main() can be configured to create either a very simple LED flasher demo, or\r
+ * a more comprehensive test/demo application.\r
+ *\r
+ * To create a very simple LED flasher example, set the\r
+ * mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY constant (defined below) to 1. When\r
+ * this is done, only the standard demo flash tasks are created. The standard\r
+ * demo flash example creates three tasks, each of which toggle an LED at a\r
+ * fixed but different frequency.\r
+ *\r
+ * To create a more comprehensive test and demo application, set\r
+ * mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 0.\r
+ ******************************************************************************\r
+ *\r
+ * main() creates all the demo application tasks and software timers, then starts\r
+ * the scheduler. The web documentation provides more details of the standard\r
+ * demo application tasks, which provide no particular functionality, but do\r
+ * provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill both the core and floating point registers with\r
+ * known values, then check that each register maintains its expected value for\r
+ * the lifetime of the task. Each task uses a different set of values. The reg\r
+ * test tasks execute with a very low priority, so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ * "Check" timer - The check software timer period is initially set to three\r
+ * seconds. The callback function associated with the check software timer\r
+ * checks that all the standard demo tasks, and the register check tasks, are\r
+ * not only still executing, but are executing without reporting any errors. If\r
+ * the check software timer discovers that a task has either stalled, or\r
+ * reported an error, then it changes its own execution period from the initial\r
+ * three seconds, to just 200ms. The check software timer callback function\r
+ * also toggles an LED each time it is called. This provides a visual\r
+ * indication of the system status: If the LED toggles every three seconds,\r
+ * then no issues have been discovered. If the LED toggles every 200ms, then\r
+ * an issue has been discovered with at least one task.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "flop.h"\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+\r
+/* Hardware includes. */\r
+#include "platform_config.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The LED used by the check timer. */\r
+#define mainCHECK_LED ( 3UL )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The period after which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_RATE_MS constant. */\r
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_RATE_MS constant. */\r
+#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )\r
+\r
+/* Set mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 1 to create a simple demo.\r
+Set mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 0 to create a much more\r
+comprehensive test application. See the comments at the top of this file, and\r
+the documentation page on the http://www.FreeRTOS.org web site for more\r
+information. */\r
+#define mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY 0\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Set up the hardware ready to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * The check timer callback function, as described at the top of this file.\r
+ */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer );\r
+\r
+/*\r
+ * Register check tasks, and the tasks used to write over and check the contents\r
+ * of the FPU registers, as described at the top of this file. The nature of\r
+ * these files necessitates that they are written in an assembly file.\r
+ */\r
+extern void vRegTest1Task( void *pvParameters );\r
+extern void vRegTest2Task( void *pvParameters );\r
+extern void vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue );\r
+extern unsigned long ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue );\r
+\r
+/*\r
+ * This file can be used to create either a simple LED flasher example, or a\r
+ * comprehensive test/demo application - depending on the setting of the\r
+ * mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY constant defined above. If\r
+ * mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 1, then the following\r
+ * function will create a lot of additional tasks and a software timer. If\r
+ * mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 0, then the following\r
+ * function will do nothing.\r
+ */\r
+static void prvOptionallyCreateComprehensveTestApplication( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The following two variables are used to communicate the status of the\r
+register check tasks to the check software timer. If the variables keep\r
+incrementing, then the register check tasks has not discovered any errors. If\r
+a variable stops incrementing, then an error has been found. */\r
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main(void)\r
+{\r
+ /* Configure the hardware ready to run the test. */\r
+ prvSetupHardware();\r
+\r
+ /* Start standard demo/test application flash tasks. See the comments at\r
+ the top of this file. The LED flash tasks are always created. The other\r
+ tasks are only created if mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to\r
+ 0 (at the top of this file). See the comments at the top of this file for\r
+ more information. */\r
+ vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );\r
+\r
+ /* The following function will only create more tasks and timers if\r
+ mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 0 (at the top of this\r
+ file). See the comments at the top of this file for more information. */\r
+ prvOptionallyCreateComprehensveTestApplication();\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+ \r
+ /* Infinite loop */\r
+ for( ;; ); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTimerCallback( xTimerHandle xTimer )\r
+{\r
+static long lChangedTimerPeriodAlready = pdFALSE;\r
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none have detected an error. */\r
+\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 0x01UL << 0UL;\r
+ }\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 0x01UL << 1UL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 0x01UL << 2UL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 0x01UL << 3UL;\r
+ }\r
+\r
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 0x01UL << 4UL;\r
+ }\r
+\r
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 0x01UL << 5UL;\r
+ }\r
+\r
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 0x01UL << 6UL;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 0x01UL << 7UL;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 0x01UL << 8UL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 0x01UL << 9UL;\r
+ }\r
+ \r
+ /* Check that the register test 1 task is still running. */\r
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
+ {\r
+ ulErrorFound |= 0x01UL << 10UL;\r
+ }\r
+ ulLastRegTest1Value = ulRegTest1LoopCounter;\r
+\r
+ /* Check that the register test 2 task is still running. */\r
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
+ {\r
+ ulErrorFound |= 0x01UL << 11UL;\r
+ }\r
+ ulLastRegTest2Value = ulRegTest2LoopCounter;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ vParTestToggleLED( mainCHECK_LED ); \r
+ \r
+ /* Have any errors been latch in ulErrorFound? If so, shorten the\r
+ period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.\r
+ This will result in an increase in the rate at which mainCHECK_LED\r
+ toggles. */\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ if( lChangedTimerPeriodAlready == pdFALSE )\r
+ {\r
+ lChangedTimerPeriodAlready = pdTRUE;\r
+ \r
+ /* This call to xTimerChangePeriod() uses a zero block time.\r
+ Functions called from inside of a timer callback function must\r
+ *never* attempt to block. */\r
+ xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup system (clock, PLL and Flash configuration) */\r
+ platformInit();\r
+ \r
+ /* Ensure all priority bits are assigned as preemption priority bits. */\r
+ NVIC_SetPriorityGrouping( 0 );\r
+ \r
+ /* Setup the LED outputs. */\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvOptionallyCreateComprehensveTestApplication( void )\r
+{\r
+ #if ( mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY == 0 )\r
+ {\r
+ xTimerHandle xCheckTimer = NULL;\r
+\r
+ /* Start all the other standard demo/test tasks. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+\r
+ /* Most importantly, start the tasks that use the FPU. */\r
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
+ \r
+ /* Create the register check tasks, as described at the top of this\r
+ file */\r
+ xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the software timer that performs the 'check' functionality,\r
+ as described at the top of this file. */\r
+ xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
+ ); \r
+ \r
+ if( xCheckTimer != NULL )\r
+ {\r
+ xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
+ }\r
+\r
+ /* This task has to be created last as it keeps account of the number of\r
+ tasks it expects to see running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+ }\r
+ #else /* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY */\r
+ {\r
+ /* Just to prevent compiler warnings when the configuration options are\r
+ set such that these static functions are not used. */\r
+ ( void ) vRegTest1Task;\r
+ ( void ) vRegTest2Task;\r
+ ( void ) prvCheckTimerCallback;\r
+ ( void ) prvSetupNestedFPUInterruptsTest;\r
+ }\r
+ #endif /* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* vApplicationMallocFailedHook() will only be called if\r
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ function that will get called if a call to pvPortMalloc() fails.\r
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+ timer or semaphore is created. It is also called by various parts of the\r
+ demo application. If heap_1.c or heap_2.c are used, then the size of the\r
+ heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+ FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+ to query the size of free heap space that remains (although it does not\r
+ provide information on how the remaining heap might be fragmented). */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
+ task. It is essential that code added to this hook function never attempts\r
+ to block in any way (for example, call xQueueReceive() with a block time\r
+ specified, or call vTaskDelay()). If the application makes use of the\r
+ vTaskDelete() API function (as this demo application does) then it is also\r
+ important that vApplicationIdleHook() is permitted to return to its calling\r
+ function, because it is the responsibility of the idle task to clean up\r
+ memory allocated by the kernel to any task that has since been deleted. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ /* This function will be called by each tick interrupt if \r
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
+ added here, but the tick hook is called from an interrupt context, so\r
+ code must not attempt to block, and only the interrupt safe FreeRTOS API\r
+ functions can be used (those that end in FromISR()). */\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <WorkspaceName>WorkSpace</WorkspaceName>
+
+ <project>
+ <PathAndName>.\M4\M4.uvproj</PathAndName>
+ <NodeIsActive>1</NodeIsActive>
+ <NodeIsExpanded>1</NodeIsExpanded>
+ </project>
+
+</ProjectWorkspace>
--- /dev/null
+IPC demo program based on mailbox\r
+-----------------------------------------\r
+\r
+- within the file platform_config.h the user needs to specify the system configuration. \r
+\r
+\r
+The user can specifiy:\r
+\r
+* which mailboxes are required (host, slave, or both)\r
+\r
+* if the M0 memory has to be initialized to a specific value before download\r
+\r
+* the usage of an optional 32-bit parameter for the mailboxes\r
+\r
+* the availability of a callback function for the mailboxes \r
+\r
+* the priority of the interrupt associated with the IPC communication\r
+\r
+* the memory locations of the M0 code/data, buffers for M0 and M4, location of the mailboxes\r
+ \r
+* if the M4 shall download the M0 and start it via INITIALIZE_M0_IMAGE (YES/NO)\r
+\r
+The linker scatter file needs to be consistent with the provided ROM/RAM addresses in case of changes. \r
+\r
+Set it to NO if you want to debug the M0 application separately. \r
+\r
+Set to YES means the M4 will reset, download, and release the M0. In this case, the debug connection could be lost.\r
+\r
+For debugging, in this scenario the .ini file shall be modified, not to download the application but just to connect to the processor.\r
+\r
+\r
+- according to the number of mailbox desired, if callbacks are enabled, the user has to provide a callback table within the Mx_usr_mbx_callbacks.c file. \r
+\r
+In Mx_usr_mbx_callbacks.h file the mailbox numbering is defined. Within the callback table, each callback gets associated to the related mailbox number.\r
+\r
+The order in the table is not important, since the callback function addresses are plugged-in at runtime by the IPC initialization routines. \r
+\r
+\r
+- The mailbox table defined in ipc_buffer.c needs also to be updated accordingly to accomodate the desired number of mailboxes. There can be \r
+\r
+\r
+- since the callbacks are executed within the ISR, their usage is meant for quick operations that need to be performed in reaction to the mailbox event\r
+\r
+For normal application processing, message pending flags are provided and shall rather be used, to avoid increasing unnecessarily interrupt latency\r
+\r
+\r
+- the type of logical messages for the mailboxes are defined within the Mx_ipc_msg.h file \r
+\r
+\r
+- the application runs completely from RAM and exchanges messages between the processors, showing how to post and read from the mailboxes.\r
+\r
+\r
+
\ No newline at end of file
--- /dev/null
+; memory map assignment\r
+; check with platform_config.h header\r
+; check the ranges\r
+\r
+; #define M4_ROM_START 0x1C000000\r
+; #define M4_ROM_LEN 0x400000 /* 4 Mbytes */\r
+LR_IROM1 0x1C000000 0x400000 { ; load region size_region\r
+\r
+ ER_IROM1 0x1C000000 0x400000 { ; load address = execution address\r
+\r
+ *.o (RESET, +First)\r
+ *(InRoot$$Sections)\r
+ .ANY (+RO)\r
+ }\r
+\r
+; #define M4_RAM_START 0x10000000 /* 96 Kbytes */\r
+; #define M4_RAM_LEN 0x18000\r
+ \r
+ ; this region includes just the relocated vector table\r
+ ; not used by anything else\r
+ ER_RELOCIRQ 0x10000000 0xC0 {\r
+ }\r
+ \r
+ RW_IRAM1 +0 (0x18000 - 0xC0) { ; RW data\r
+\r
+ .ANY (+RW +ZI)\r
+ }\r
+\r
+; #define M4_BUF_START 0x20000000\r
+; #define M4_BUF_LEN 0x4000\r
+ RW_IRAM_BUFFERS 0x20000000 0x4000 { ; rw buffers\r
+\r
+ }\r
+\r
+; #define M4_MBX_START 0x20008000\r
+; #define M4_MBX_LEN 0x2000\r
+ RW_IRAM_MBX 0x20008000 0x2000 {\r
+\r
+\r
+ }\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/**********************************************************************\r
+* $Id$ lpc43xx_cgu.c 2011-06-02\r
+*//**\r
+* @file lpc43xx_cgu.c\r
+* @brief Contains all functions support for Clock Generation and Control\r
+* firmware library on lpc43xx\r
+* @version 1.0\r
+* @date 02. June. 2011\r
+* @author NXP MCU SW Application Team\r
+*\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+***********************************************************************\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+\r
+/* Peripheral group ----------------------------------------------------------- */\r
+/** @addtogroup CGU\r
+ * @{\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------- */\r
+#include "lpc_types.h"\r
+#include "lpc43xx_scu.h"\r
+#include "lpc43xx_cgu.h"\r
+\r
+/** This define used to fix mistake when run with IAR compiler */\r
+#ifdef __ICCARM__\r
+#define CGU_BRANCH_STATUS_ENABLE_MASK 0x80000001\r
+#else\r
+#define CGU_BRANCH_STATUS_ENABLE_MASK 0x01\r
+#endif\r
+\r
+/*TODO List:\r
+ * SET PLL0\r
+ * UPDATE Clock from PLL0\r
+ * SetDIV uncheck value\r
+ * GetBaseStatus BASE_SAFE\r
+ * */\r
+/* Local definition */\r
+#define CGU_ADDRESS32(x,y) (*(uint32_t*)((uint32_t)x+y))\r
+\r
+/* Local Variable */\r
+const int16_t CGU_Entity_ControlReg_Offset[CGU_ENTITY_NUM] = {\r
+ -1, //CGU_CLKSRC_32KHZ_OSC,\r
+ -1, //CGU_CLKSRC_IRC,\r
+ -1, //CGU_CLKSRC_ENET_RX_CLK,\r
+ -1, //CGU_CLKSRC_ENET_TX_CLK,\r
+ -1, //CGU_CLKSRC_GP_CLKIN,\r
+ -1, //CGU_CLKSRC_TCK,\r
+ 0x18, //CGU_CLKSRC_XTAL_OSC,\r
+ 0x20, //CGU_CLKSRC_PLL0,\r
+ 0x30, //CGU_CLKSRC_PLL0_AUDIO **REV A**\r
+ 0x44, //CGU_CLKSRC_PLL1,\r
+ -1, //CGU_CLKSRC_RESERVE,\r
+ -1, //CGU_CLKSRC_RESERVE,\r
+ 0x48, //CGU_CLKSRC_IDIVA,,\r
+ 0x4C, //CGU_CLKSRC_IDIVB,\r
+ 0x50, //CGU_CLKSRC_IDIVC,\r
+ 0x54, //CGU_CLKSRC_IDIVD,\r
+ 0x58, //CGU_CLKSRC_IDIVE,\r
+\r
+ 0x5C, //CGU_BASE_SAFE,\r
+ 0x60, //CGU_BASE_USB0,\r
+ -1, //CGU_BASE_RESERVE,\r
+ 0x68, //CGU_BASE_USB1,\r
+ 0x6C, //CGU_BASE_M3,\r
+ 0x70, //CGU_BASE_SPIFI,\r
+ -1, //CGU_BASE_RESERVE,\r
+ 0x78, //CGU_BASE_PHY_RX,\r
+ 0x7C, //CGU_BASE_PHY_TX,\r
+ 0x80, //CGU_BASE_APB1,\r
+ 0x84, //CGU_BASE_APB3,\r
+ 0x88, //CGU_BASE_LCD,\r
+ 0X8C, //CGU_BASE_ENET_CSR, **REV A**\r
+ 0x90, //CGU_BASE_SDIO,\r
+ 0x94, //CGU_BASE_SSP0,\r
+ 0x98, //CGU_BASE_SSP1,\r
+ 0x9C, //CGU_BASE_UART0,\r
+ 0xA0, //CGU_BASE_UART1,\r
+ 0xA4, //CGU_BASE_UART2,\r
+ 0xA8, //CGU_BASE_UART3,\r
+ 0xAC, //CGU_BASE_CLKOUT\r
+ -1,\r
+ -1,\r
+ -1,\r
+ -1,\r
+ 0xC0, //CGU_BASE_APLL\r
+ 0xC4, //CGU_BASE_OUT0\r
+ 0xC8 //CGU_BASE_OUT1\r
+};\r
+\r
+const uint8_t CGU_ConnectAlloc_Tbl[CGU_CLKSRC_NUM][CGU_ENTITY_NUM] = {\r
+// 3 I E E G T X P P P x x D D D D D S U x U M S x P P A A L E S S S U U U U C x x x x A O O\r
+// 2 R R T P C T L L L I I I I I A S S 3 P H H P P C N D S S R R R R O P U U\r
+// C X X I K A 0 A 1 A B C D E F B B F RxTx1 3 D T I 0 1 0 1 2 3 L T T\r
+ {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_32KHZ_OSC = 0,*/\r
+ {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,1,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IRC,*/\r
+ {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_ENET_RX_CLK,*/\r
+ {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_ENET_TX_CLK,*/\r
+ {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_GP_CLKIN,*/\r
+ {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0},/*CGU_CLKSRC_TCK,*/\r
+ {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_XTAL_OSC,*/\r
+ {0,0,0,0,0,0,0,0,0,1,0,0,1,0,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,1,1},/*CGU_CLKSRC_PLL0,*/\r
+ {0,0,0,0,0,0,0,0,0,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_PLL0_AUDIO,*/\r
+ {0,0,0,0,0,0,0,1,1,0,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_PLL1,*/\r
+ {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},\r
+ {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},\r
+ {0,0,0,0,0,0,0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3,*/\r
+ {0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVB,*/\r
+ {0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVC,*/\r
+ {0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVD,*/\r
+ {0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1}/*CGU_CLKSRC_IDIVE,*/\r
+};\r
+\r
+const CGU_PERIPHERAL_S CGU_PERIPHERAL_Info[CGU_PERIPHERAL_NUM] = {\r
+ /* Register Clock | Peripheral Clock\r
+ | BASE | BRANCH | BASE | BRANCH */\r
+ {CGU_BASE_APB3, 0x1118, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC0,\r
+ {CGU_BASE_APB3, 0x1120, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC1,\r
+ {CGU_BASE_M3, 0x1460, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_AES,\r
+ //// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,\r
+ {CGU_BASE_APB1, 0x1200, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB1_BUS,\r
+ {CGU_BASE_APB3, 0x1100, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB3_BUS,\r
+ {CGU_BASE_APB3, 0x1128, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CAN0,\r
+ {CGU_BASE_M3, 0x1538, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CREG,\r
+ {CGU_BASE_APB3, 0x1110, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DAC,\r
+ {CGU_BASE_M3, 0x1440, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DMA,\r
+ {CGU_BASE_M3, 0x1430, CGU_BASE_M3, 0x1478, 0},//CGU_PERIPHERAL_EMC,\r
+ {CGU_BASE_M3, 0x1420, CGU_BASE_PHY_RX, 0x0000, CGU_PERIPHERAL_ETHERNET_TX},//CGU_PERIPHERAL_ETHERNET,\r
+ {CGU_ENTITY_NONE,0x0000, CGU_BASE_PHY_TX, 0x0000, 0},//CGU_PERIPHERAL_ETHERNET_TX\r
+ {CGU_BASE_M3, 0x1410, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_GPIO,\r
+ {CGU_BASE_APB1, 0x1210, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C0,\r
+ {CGU_BASE_APB3, 0x1108, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C1,\r
+ {CGU_BASE_APB1, 0x1218, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2S,\r
+ {CGU_BASE_M3, 0x1418, CGU_BASE_LCD, 0x0000, 0},//CGU_PERIPHERAL_LCD,\r
+ {CGU_BASE_M3, 0x1448, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3CORE,\r
+ {CGU_BASE_M3, 0x1400, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3_BUS,\r
+ {CGU_BASE_APB1, 0x1208, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_MOTOCON,\r
+ {CGU_BASE_M3, 0x1630, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_QEI,\r
+ {CGU_BASE_M3, 0x1600, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_RITIMER,\r
+ {CGU_BASE_M3, 0x1468, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCT,\r
+ {CGU_BASE_M3, 0x1530, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCU,\r
+ {CGU_BASE_M3, 0x1438, CGU_BASE_SDIO, 0x2800, 0},//CGU_PERIPHERAL_SDIO,\r
+ {CGU_BASE_M3, 0x1408, CGU_BASE_SPIFI, 0x1300, 0},//CGU_PERIPHERAL_SPIFI,\r
+ {CGU_BASE_M3, 0x1518, CGU_BASE_SSP0, 0x2700, 0},//CGU_PERIPHERAL_SSP0,\r
+ {CGU_BASE_M3, 0x1628, CGU_BASE_SSP1, 0x2600, 0},//CGU_PERIPHERAL_SSP1,\r
+ {CGU_BASE_M3, 0x1520, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER0,\r
+ {CGU_BASE_M3, 0x1528, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER1,\r
+ {CGU_BASE_M3, 0x1618, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER2,\r
+ {CGU_BASE_M3, 0x1620, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER3,\r
+ {CGU_BASE_M3, 0x1508, CGU_BASE_UART0, 0x2500, 0},//CGU_PERIPHERAL_UART0,\r
+ {CGU_BASE_M3, 0x1510, CGU_BASE_UART1, 0x2400, 0},//CGU_PERIPHERAL_UART1,\r
+ {CGU_BASE_M3, 0x1608, CGU_BASE_UART2, 0x2300, 0},//CGU_PERIPHERAL_UART2,\r
+ {CGU_BASE_M3, 0x1610, CGU_BASE_UART3, 0x2200, 0},//CGU_PERIPHERAL_UART3,\r
+ {CGU_BASE_M3, 0x1428, CGU_BASE_USB0, 0x1800, 0},//CGU_PERIPHERAL_USB0,\r
+ {CGU_BASE_M3, 0x1470, CGU_BASE_USB1, 0x1900, 0},//CGU_PERIPHERAL_USB1,\r
+ {CGU_BASE_M3, 0x1500, CGU_BASE_SAFE, 0x0000, 0},//CGU_PERIPHERAL_WWDT,\r
+};\r
+\r
+uint32_t CGU_ClockSourceFrequency[CGU_CLKSRC_NUM] = {0,12000000,0,0,0,0, 0, 480000000,0,0,0,0,0,0,0,0,0};\r
+\r
+#define CGU_CGU_ADDR ((uint32_t)LPC_CGU)\r
+#define CGU_REG_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].RegBaseEntity]))\r
+#define CGU_REG_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset))\r
+#define CGU_REG_BRANCH_STATUS(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset+4))\r
+\r
+#define CGU_PER_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].PerBaseEntity]))\r
+#define CGU_PER_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset))\r
+#define CGU_PER_BRANCH_STATUS(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset+4))\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Initialize default clock for LPC4300 Eval board\r
+ * @param[in] None\r
+ * @return Initialize status, could be:\r
+ * - CGU_ERROR_SUCCESS: successful\r
+ * - Other: error\r
+ **********************************************************************/\r
+uint32_t CGU_Init(void){\r
+ CGU_SetXTALOSC(12000000);\r
+ CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);\r
+ CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);\r
+ // Disable PLL1 CPU hang???\r
+ //CGU_EnableEntity(CGU_CLKSRC_PLL1, DISABLE);\r
+ CGU_SetPLL1(6);\r
+ CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);\r
+ CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);\r
+ CGU_UpdateClock();\r
+ return 0;\r
+}\r
+\r
+/*********************************************************************//**\r
+ * @brief Configure power for individual peripheral\r
+ * @param[in] PPType peripheral type, should be:\r
+ * - CGU_PERIPHERAL_ADC0 :ADC0\r
+ * - CGU_PERIPHERAL_ADC1 :ADC1\r
+ * - CGU_PERIPHERAL_AES :AES\r
+ * - CGU_PERIPHERAL_APB1_BUS :APB1 bus\r
+ * - CGU_PERIPHERAL_APB3_BUS :APB3 bus\r
+ * - CGU_PERIPHERAL_CAN :CAN\r
+ * - CGU_PERIPHERAL_CREG :CREG\r
+ * - CGU_PERIPHERAL_DAC :DAC\r
+ * - CGU_PERIPHERAL_DMA :DMA\r
+ * - CGU_PERIPHERAL_EMC :EMC\r
+ * - CGU_PERIPHERAL_ETHERNET :ETHERNET\r
+ * - CGU_PERIPHERAL_GPIO :GPIO\r
+ * - CGU_PERIPHERAL_I2C0 :I2C0\r
+ * - CGU_PERIPHERAL_I2C1 :I2C1\r
+ * - CGU_PERIPHERAL_I2S :I2S\r
+ * - CGU_PERIPHERAL_LCD :LCD\r
+ * - CGU_PERIPHERAL_M3CORE :M3 core\r
+ * - CGU_PERIPHERAL_M3_BUS :M3 bus\r
+ * - CGU_PERIPHERAL_MOTOCON :Motor control\r
+ * - CGU_PERIPHERAL_QEI :QEI\r
+ * - CGU_PERIPHERAL_RITIMER :RIT timer\r
+ * - CGU_PERIPHERAL_SCT :SCT\r
+ * - CGU_PERIPHERAL_SCU :SCU\r
+ * - CGU_PERIPHERAL_SDIO :SDIO\r
+ * - CGU_PERIPHERAL_SPIFI :SPIFI\r
+ * - CGU_PERIPHERAL_SSP0 :SSP0\r
+ * - CGU_PERIPHERAL_SSP1 :SSP1\r
+ * - CGU_PERIPHERAL_TIMER0 :TIMER0\r
+ * - CGU_PERIPHERAL_TIMER1 :TIMER1\r
+ * - CGU_PERIPHERAL_TIMER2 :TIMER2\r
+ * - CGU_PERIPHERAL_TIMER3 :TIMER3\r
+ * - CGU_PERIPHERAL_UART0 :UART0\r
+ * - CGU_PERIPHERAL_UART1 :UART1\r
+ * - CGU_PERIPHERAL_UART2 :UART2\r
+ * - CGU_PERIPHERAL_UART3 :UART3\r
+ * - CGU_PERIPHERAL_USB0 :USB0\r
+ * - CGU_PERIPHERAL_USB1 :USB1\r
+ * - CGU_PERIPHERAL_WWDT :WWDT\r
+ * @param[in] en status, should be:\r
+ * - ENABLE: Enable power\r
+ * - DISABLE: Disable power\r
+ * @return Configure status, could be:\r
+ * - CGU_ERROR_SUCCESS: successful\r
+ * - Other: error\r
+ **********************************************************************/\r
+uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en){\r
+ if(PPType >= CGU_PERIPHERAL_WWDT && PPType <= CGU_PERIPHERAL_ADC0)\r
+ return CGU_ERROR_INVALID_PARAM;\r
+ if(en == DISABLE){/* Going to disable clock */\r
+ /*Get Reg branch status */\r
+ if(CGU_PERIPHERAL_Info[PPType].RegBranchOffset!= 0 &&\r
+ CGU_REG_BRANCH_STATUS(PPType) & 1){\r
+ CGU_REG_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */\r
+ while(CGU_REG_BRANCH_STATUS(PPType) & 1);\r
+ }\r
+ /* GetBase Status*/\r
+ if((CGU_PERIPHERAL_Info[PPType].RegBaseEntity!=CGU_ENTITY_NONE) &&\r
+ CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity) == 0){\r
+ /* Disable Base */\r
+ CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity,0);\r
+ }\r
+\r
+ /* Same for Peripheral */\r
+ if((CGU_PERIPHERAL_Info[PPType].PerBranchOffset!= 0) && (CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){\r
+ CGU_PER_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */\r
+ while(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK);\r
+ }\r
+ /* GetBase Status*/\r
+ if((CGU_PERIPHERAL_Info[PPType].PerBaseEntity!=CGU_ENTITY_NONE) &&\r
+ CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity) == 0){\r
+ /* Disable Base */\r
+ CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity,0);\r
+ }\r
+ }else{\r
+ /* enable */\r
+ /* GetBase Status*/\r
+ if((CGU_PERIPHERAL_Info[PPType].RegBaseEntity!=CGU_ENTITY_NONE) && CGU_REG_BASE_CTRL(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK){\r
+ /* Enable Base */\r
+ CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity, 1);\r
+ }\r
+ /*Get Reg branch status */\r
+ if((CGU_PERIPHERAL_Info[PPType].RegBranchOffset!= 0) && !(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){\r
+ CGU_REG_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */\r
+ while(!(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK));\r
+ }\r
+\r
+ /* Same for Peripheral */\r
+ /* GetBase Status*/\r
+ if((CGU_PERIPHERAL_Info[PPType].PerBaseEntity != CGU_ENTITY_NONE) &&\r
+ (CGU_PER_BASE_CTRL(PPType) & 1)){\r
+ /* Enable Base */\r
+ CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity, 1);\r
+ }\r
+ /*Get Reg branch status */\r
+ if((CGU_PERIPHERAL_Info[PPType].PerBranchOffset!= 0) && !(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){\r
+ CGU_PER_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */\r
+ while(!(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK));\r
+ }\r
+\r
+ }\r
+\r
+ if(CGU_PERIPHERAL_Info[PPType].next){\r
+ return CGU_ConfigPWR((CGU_PERIPHERAL_T)CGU_PERIPHERAL_Info[PPType].next, en);\r
+ }\r
+ return CGU_ERROR_SUCCESS;\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Get peripheral clock frequency\r
+ * @param[in] Clock Peripheral type, should be:\r
+ * - CGU_PERIPHERAL_ADC0 :ADC0\r
+ * - CGU_PERIPHERAL_ADC1 :ADC1\r
+ * - CGU_PERIPHERAL_AES :AES\r
+ * - CGU_PERIPHERAL_APB1_BUS :APB1 bus\r
+ * - CGU_PERIPHERAL_APB3_BUS :APB3 bus\r
+ * - CGU_PERIPHERAL_CAN :CAN\r
+ * - CGU_PERIPHERAL_CREG :CREG\r
+ * - CGU_PERIPHERAL_DAC :DAC\r
+ * - CGU_PERIPHERAL_DMA :DMA\r
+ * - CGU_PERIPHERAL_EMC :EMC\r
+ * - CGU_PERIPHERAL_ETHERNET :ETHERNET\r
+ * - CGU_PERIPHERAL_GPIO :GPIO\r
+ * - CGU_PERIPHERAL_I2C0 :I2C0\r
+ * - CGU_PERIPHERAL_I2C1 :I2C1\r
+ * - CGU_PERIPHERAL_I2S :I2S\r
+ * - CGU_PERIPHERAL_LCD :LCD\r
+ * - CGU_PERIPHERAL_M3CORE :M3 core\r
+ * - CGU_PERIPHERAL_M3_BUS :M3 bus\r
+ * - CGU_PERIPHERAL_MOTOCON :Motor control\r
+ * - CGU_PERIPHERAL_QEI :QEI\r
+ * - CGU_PERIPHERAL_RITIMER :RIT timer\r
+ * - CGU_PERIPHERAL_SCT :SCT\r
+ * - CGU_PERIPHERAL_SCU :SCU\r
+ * - CGU_PERIPHERAL_SDIO :SDIO\r
+ * - CGU_PERIPHERAL_SPIFI :SPIFI\r
+ * - CGU_PERIPHERAL_SSP0 :SSP0\r
+ * - CGU_PERIPHERAL_SSP1 :SSP1\r
+ * - CGU_PERIPHERAL_TIMER0 :TIMER0\r
+ * - CGU_PERIPHERAL_TIMER1 :TIMER1\r
+ * - CGU_PERIPHERAL_TIMER2 :TIMER2\r
+ * - CGU_PERIPHERAL_TIMER3 :TIMER3\r
+ * - CGU_PERIPHERAL_UART0 :UART0\r
+ * - CGU_PERIPHERAL_UART1 :UART1\r
+ * - CGU_PERIPHERAL_UART2 :UART2\r
+ * - CGU_PERIPHERAL_UART3 :UART3\r
+ * - CGU_PERIPHERAL_USB0 :USB0\r
+ * - CGU_PERIPHERAL_USB1 :USB1\r
+ * - CGU_PERIPHERAL_WWDT :WWDT\r
+ * @return Return frequently value\r
+ **********************************************************************/\r
+uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock){\r
+ uint32_t ClkSrc;\r
+ if(Clock >= CGU_PERIPHERAL_WWDT && Clock <= CGU_PERIPHERAL_ADC0)\r
+ return CGU_ERROR_INVALID_PARAM;\r
+\r
+ if(CGU_PERIPHERAL_Info[Clock].PerBaseEntity != CGU_ENTITY_NONE){\r
+ /* Get Base Clock Source */\r
+ ClkSrc = (CGU_PER_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24;\r
+ /* GetBase Status*/\r
+ if(CGU_PER_BASE_CTRL(Clock) & 1)\r
+ return 0;\r
+ /* check Branch if it is enabled */\r
+ if((CGU_PERIPHERAL_Info[Clock].PerBranchOffset!= 0) && !(CGU_PER_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) return 0;\r
+ }else{\r
+ if(CGU_REG_BASE_CTRL(Clock) & 1) return 0;\r
+ ClkSrc = (CGU_REG_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24;\r
+ /* check Branch if it is enabled */\r
+ if((CGU_PERIPHERAL_Info[Clock].RegBranchOffset!= 0) && !(CGU_REG_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) return 0;\r
+ }\r
+ return CGU_ClockSourceFrequency[ClkSrc];\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Update clock\r
+ * @param[in] None\r
+ * @return None\r
+ **********************************************************************/\r
+void CGU_UpdateClock(void){\r
+ uint32_t ClkSrc;\r
+ uint32_t div;\r
+ uint32_t divisor;\r
+ int32_t RegOffset;\r
+ /* 32OSC */\r
+ if(ISBITSET(LPC_CREG->CREG0,1) && ISBITCLR(LPC_CREG->CREG0,3))\r
+ CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 32768;\r
+ else\r
+ CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 0;\r
+ /*PLL0*/\r
+ /* PLL1 */\r
+ if(ISBITCLR(LPC_CGU->PLL1_CTRL,1) /* Enabled */\r
+ && (LPC_CGU->PLL1_STAT&1)){ /* Locked? */\r
+ ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK)>>24;\r
+ CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = CGU_ClockSourceFrequency[ClkSrc] *\r
+ (((LPC_CGU->PLL1_CTRL>>16)&0xFF)+1);\r
+ }else\r
+ CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = 0;\r
+\r
+ /* DIV */\r
+ for(div = CGU_CLKSRC_IDIVA; div <= CGU_CLKSRC_IDIVE; div++){\r
+ RegOffset = CGU_Entity_ControlReg_Offset[div];\r
+ if(ISBITCLR(CGU_ADDRESS32(LPC_CGU,RegOffset),1)){\r
+ ClkSrc = (CGU_ADDRESS32(LPC_CGU,RegOffset) & CGU_CTRL_SRC_MASK) >> 24;\r
+ divisor = (CGU_ADDRESS32(LPC_CGU,RegOffset)>>2) & 0xFF;\r
+ divisor ++;\r
+ CGU_ClockSourceFrequency[div] = CGU_ClockSourceFrequency[ClkSrc] / divisor;\r
+ }else\r
+ CGU_ClockSourceFrequency[div] = 0;\r
+ }\r
+}\r
+\r
+/*********************************************************************//**\r
+ * @brief Set XTAL oscillator value\r
+ * @param[in] ClockFrequency XTAL Frequency value\r
+ * @return Setting status, could be:\r
+ * - CGU_ERROR_SUCCESS: successful\r
+ * - CGU_ERROR_FREQ_OUTOF_RANGE: XTAL value set is out of range\r
+ **********************************************************************/\r
+uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency){\r
+ if(ClockFrequency < 15000000){\r
+ LPC_CGU->XTAL_OSC_CTRL &= ~(1<<2);\r
+ }else if(ClockFrequency < 25000000){\r
+ LPC_CGU->XTAL_OSC_CTRL |= (1<<2);\r
+ }else\r
+ return CGU_ERROR_FREQ_OUTOF_RANGE;\r
+\r
+ CGU_ClockSourceFrequency[CGU_CLKSRC_XTAL_OSC] = ClockFrequency;\r
+ return CGU_ERROR_SUCCESS;\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Set clock divider\r
+ * @param[in] SelectDivider Clock source, should be:\r
+ * - CGU_CLKSRC_IDIVA :Integer divider register A\r
+ * - CGU_CLKSRC_IDIVB :Integer divider register B\r
+ * - CGU_CLKSRC_IDIVC :Integer divider register C\r
+ * - CGU_CLKSRC_IDIVD :Integer divider register D\r
+ * - CGU_CLKSRC_IDIVE :Integer divider register E\r
+ * @param[in] divisor Divisor value, should be: 0..255\r
+ * @return Setting status, could be:\r
+ * - CGU_ERROR_SUCCESS: successful\r
+ * - CGU_ERROR_INVALID_ENTITY: Invalid entity\r
+ **********************************************************************/\r
+/* divisor number must >=1*/\r
+uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor){\r
+ int32_t RegOffset;\r
+ uint32_t tempReg;\r
+ if(SelectDivider>=CGU_CLKSRC_IDIVA && SelectDivider<=CGU_CLKSRC_IDIVE){\r
+ RegOffset = CGU_Entity_ControlReg_Offset[SelectDivider];\r
+ if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY;\r
+ tempReg = CGU_ADDRESS32(LPC_CGU,RegOffset);\r
+ tempReg &= ~(0xFF<<2);\r
+ tempReg |= ((divisor-1)&0xFF)<<2;\r
+ CGU_ADDRESS32(LPC_CGU,RegOffset) = tempReg;\r
+ return CGU_ERROR_SUCCESS;\r
+ }\r
+ return CGU_ERROR_INVALID_ENTITY;\r
+}\r
+\r
+/*********************************************************************//**\r
+ * @brief Enable clock entity\r
+ * @param[in] ClockEntity Clock entity, should be:\r
+ * - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator\r
+ * - CGU_CLKSRC_IRC :IRC clock\r
+ * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock\r
+ * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock\r
+ * - CGU_CLKSRC_GP_CLKIN :General purpose input clock\r
+ * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator\r
+ * - CGU_CLKSRC_PLL0 :PLL0 clock\r
+ * - CGU_CLKSRC_PLL1 :PLL1 clock\r
+ * - CGU_CLKSRC_IDIVA :Integer divider register A\r
+ * - CGU_CLKSRC_IDIVB :Integer divider register B\r
+ * - CGU_CLKSRC_IDIVC :Integer divider register C\r
+ * - CGU_CLKSRC_IDIVD :Integer divider register D\r
+ * - CGU_CLKSRC_IDIVE :Integer divider register E\r
+ * - CGU_BASE_SAFE :Base safe clock (always on)for WDT\r
+ * - CGU_BASE_USB0 :Base clock for USB0\r
+ * - CGU_BASE_USB1 :Base clock for USB1\r
+ * - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core\r
+ * and APB peripheral blocks #0 and #2\r
+ * - CGU_BASE_SPIFI :Base clock for SPIFI\r
+ * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx\r
+ * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx\r
+ * - CGU_BASE_APB1 :Base clock for APB peripheral block #1\r
+ * - CGU_BASE_APB3 :Base clock for APB peripheral block #3\r
+ * - CGU_BASE_LCD :Base clock for LCD\r
+ * - CGU_BASE_SDIO :Base clock for SDIO card reader\r
+ * - CGU_BASE_SSP0 :Base clock for SSP0\r
+ * - CGU_BASE_SSP1 :Base clock for SSP1\r
+ * - CGU_BASE_UART0 :Base clock for UART0\r
+ * - CGU_BASE_UART1 :Base clock for UART1\r
+ * - CGU_BASE_UART2 :Base clock for UART2\r
+ * - CGU_BASE_UART3 :Base clock for UART3\r
+ * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin\r
+ * @param[in] en status, should be:\r
+ * - ENABLE: Enable power\r
+ * - DISABLE: Disable power\r
+ * @return Setting status, could be:\r
+ * - CGU_ERROR_SUCCESS: successful\r
+ * - CGU_ERROR_INVALID_ENTITY: Invalid entity\r
+ **********************************************************************/\r
+uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en){\r
+ int32_t RegOffset;\r
+ int32_t i;\r
+ if(ClockEntity == CGU_CLKSRC_32KHZ_OSC){\r
+ if(en){\r
+ LPC_CREG->CREG0 &= ~((1<<3)|(1<<2));\r
+ LPC_CREG->CREG0 |= (1<<1)|(1<<0);\r
+ }else{\r
+ LPC_CREG->CREG0 &= ~((1<<1)|(1<<0));\r
+ LPC_CREG->CREG0 |= (1<<3);\r
+ }\r
+ for(i = 0;i<1000000;i++);\r
+\r
+ }else if(ClockEntity == CGU_CLKSRC_ENET_RX_CLK){\r
+ scu_pinmux(0xC ,0 , MD_PLN, FUNC3);\r
+\r
+ }else if(ClockEntity == CGU_CLKSRC_ENET_TX_CLK){\r
+ scu_pinmux(0x1 ,19 , MD_PLN, FUNC0);\r
+\r
+ }else if(ClockEntity == CGU_CLKSRC_GP_CLKIN){\r
+\r
+ }else if(ClockEntity == CGU_CLKSRC_TCK){\r
+\r
+ }else if(ClockEntity == CGU_CLKSRC_XTAL_OSC){\r
+ if(!en)\r
+ LPC_CGU->XTAL_OSC_CTRL |= CGU_CTRL_EN_MASK;\r
+ else\r
+ LPC_CGU->XTAL_OSC_CTRL &= ~CGU_CTRL_EN_MASK;\r
+ /*Delay for stable clock*/\r
+ for(i = 0;i<1000000;i++);\r
+\r
+ }else{\r
+ RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity];\r
+ if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY;\r
+ if(!en){\r
+ CGU_ADDRESS32(CGU_CGU_ADDR,RegOffset) |= CGU_CTRL_EN_MASK;\r
+ }else{\r
+ CGU_ADDRESS32(CGU_CGU_ADDR,RegOffset) &= ~CGU_CTRL_EN_MASK;\r
+ /*if PLL is selected check if it is locked */\r
+ if(ClockEntity == CGU_CLKSRC_PLL0){\r
+ while((LPC_CGU->PLL0USB_STAT&1) == 0x0);\r
+ }\r
+ if(ClockEntity == CGU_CLKSRC_PLL1){\r
+ while((LPC_CGU->PLL1_STAT&1) == 0x0);\r
+ /*post check lock status */\r
+ if(!(LPC_CGU->PLL1_STAT&1))\r
+ while(1);\r
+ }\r
+ }\r
+ }\r
+ return CGU_ERROR_SUCCESS;\r
+}\r
+\r
+/*********************************************************************//**\r
+ * @brief Connect entity clock source\r
+ * @param[in] ClockSource Clock source, should be:\r
+ * - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator\r
+ * - CGU_CLKSRC_IRC :IRC clock\r
+ * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock\r
+ * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock\r
+ * - CGU_CLKSRC_GP_CLKIN :General purpose input clock\r
+ * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator\r
+ * - CGU_CLKSRC_PLL0 :PLL0 clock\r
+ * - CGU_CLKSRC_PLL1 :PLL1 clock\r
+ * - CGU_CLKSRC_IDIVA :Integer divider register A\r
+ * - CGU_CLKSRC_IDIVB :Integer divider register B\r
+ * - CGU_CLKSRC_IDIVC :Integer divider register C\r
+ * - CGU_CLKSRC_IDIVD :Integer divider register D\r
+ * - CGU_CLKSRC_IDIVE :Integer divider register E\r
+ * @param[in] ClockEntity Clock entity, should be:\r
+ * - CGU_CLKSRC_PLL0 :PLL0 clock\r
+ * - CGU_CLKSRC_PLL1 :PLL1 clock\r
+ * - CGU_CLKSRC_IDIVA :Integer divider register A\r
+ * - CGU_CLKSRC_IDIVB :Integer divider register B\r
+ * - CGU_CLKSRC_IDIVC :Integer divider register C\r
+ * - CGU_CLKSRC_IDIVD :Integer divider register D\r
+ * - CGU_CLKSRC_IDIVE :Integer divider register E\r
+ * - CGU_BASE_SAFE :Base safe clock (always on)for WDT\r
+ * - CGU_BASE_USB0 :Base clock for USB0\r
+ * - CGU_BASE_USB1 :Base clock for USB1\r
+ * - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core\r
+ * and APB peripheral blocks #0 and #2\r
+ * - CGU_BASE_SPIFI :Base clock for SPIFI\r
+ * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx\r
+ * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx\r
+ * - CGU_BASE_APB1 :Base clock for APB peripheral block #1\r
+ * - CGU_BASE_APB3 :Base clock for APB peripheral block #3\r
+ * - CGU_BASE_LCD :Base clock for LCD\r
+ * - CGU_BASE_SDIO :Base clock for SDIO card reader\r
+ * - CGU_BASE_SSP0 :Base clock for SSP0\r
+ * - CGU_BASE_SSP1 :Base clock for SSP1\r
+ * - CGU_BASE_UART0 :Base clock for UART0\r
+ * - CGU_BASE_UART1 :Base clock for UART1\r
+ * - CGU_BASE_UART2 :Base clock for UART2\r
+ * - CGU_BASE_UART3 :Base clock for UART3\r
+ * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin\r
+ * @return Setting status, could be:\r
+ * - CGU_ERROR_SUCCESS: successful\r
+ * - CGU_ERROR_CONNECT_TOGETHER: Error when 2 clock source connect together\r
+ * - CGU_ERROR_INVALID_CLOCK_SOURCE: Invalid clock source error\r
+ * - CGU_ERROR_INVALID_ENTITY: Invalid entity error\r
+ **********************************************************************/\r
+/* Connect one entity into clock source */\r
+uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity){\r
+ int32_t RegOffset;\r
+ uint32_t tempReg;\r
+\r
+ if(ClockSource > CGU_CLKSRC_IDIVE)\r
+ return CGU_ERROR_INVALID_CLOCK_SOURCE;\r
+\r
+ if(ClockEntity >= CGU_CLKSRC_PLL0 && ClockEntity <= CGU_BASE_CLKOUT){\r
+ if(CGU_ConnectAlloc_Tbl[ClockSource][ClockEntity]){\r
+ RegOffset = CGU_Entity_ControlReg_Offset[ClockSource];\r
+ if(RegOffset != -1){\r
+ if(ClockEntity<=CGU_CLKSRC_IDIVE &&\r
+ ClockEntity>=CGU_CLKSRC_PLL0)\r
+ {\r
+ //RegOffset = (CGU_ADDRESS32(LPC_CGU,RegOffset)>>24)&0xF;\r
+ if(((CGU_ADDRESS32(LPC_CGU,RegOffset)>>24)& 0xF) == ClockEntity)\r
+ return CGU_ERROR_CONNECT_TOGETHER;\r
+ }\r
+ }\r
+ RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity];\r
+ if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY;\r
+ tempReg = CGU_ADDRESS32(LPC_CGU,RegOffset);\r
+ tempReg &= ~CGU_CTRL_SRC_MASK;\r
+ tempReg |= ClockSource<<24 | CGU_CTRL_AUTOBLOCK_MASK;\r
+ CGU_ADDRESS32(LPC_CGU,RegOffset) = tempReg;\r
+ return CGU_ERROR_SUCCESS;\r
+ }else\r
+ return CGU_ERROR_INVALID_CLOCK_SOURCE;\r
+ }else\r
+ return CGU_ERROR_INVALID_ENTITY;\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Get current USB PLL clock from XTAL\r
+ * @param[in] None\r
+ * @return Returned clock value\r
+ **********************************************************************/\r
+uint32_t CGU_SetPLL0(void){\r
+ // Setup PLL550 to generate 480MHz from 12 MHz crystal\r
+ LPC_CGU->PLL0USB_CTRL |= 1; // Power down PLL\r
+ // P N\r
+ LPC_CGU->PLL0USB_NP_DIV = (98<<0) | (514<<12);\r
+ // SELP SELI SELR MDEC\r
+ LPC_CGU->PLL0USB_MDIV = (0xB<<17)|(0x10<<22)|(0<<28)|(0x7FFA<<0);\r
+ LPC_CGU->PLL0USB_CTRL =(CGU_CLKSRC_XTAL_OSC<<24) | (0x3<<2) | (1<<4);\r
+ return CGU_ERROR_SUCCESS;\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Setting PLL1\r
+ * @param[in] mult Multiple value\r
+ * @return Setting status, could be:\r
+ * - CGU_ERROR_SUCCESS: successful\r
+ * - CGU_ERROR_INVALID_PARAM: Invalid parameter error\r
+ **********************************************************************/\r
+uint32_t CGU_SetPLL1(uint32_t mult){\r
+ uint32_t msel=0, nsel=0, psel=0, pval=1;\r
+ uint32_t freq;\r
+ uint32_t ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK)>>24;\r
+ freq = CGU_ClockSourceFrequency[ClkSrc];\r
+ freq *= mult;\r
+ msel = mult-1;\r
+\r
+ LPC_CGU->PLL1_CTRL &= ~(CGU_PLL1_FBSEL_MASK |\r
+ CGU_PLL1_BYPASS_MASK |\r
+ CGU_PLL1_DIRECT_MASK |\r
+ (0x03<<8) | (0xFF<<16) | (0x03<<12));\r
+\r
+ if(freq<156000000){\r
+ //psel is encoded such that 0=1, 1=2, 2=4, 3=8\r
+ while(2*(pval)*freq < 156000000) {\r
+ psel++;\r
+ pval*=2;\r
+ }\r
+// if(2*(pval)*freq > 320000000) {\r
+// //THIS IS OUT OF RANGE!!!\r
+// //HOW DO WE ASSERT IN SAMPLE CODE?\r
+// //__breakpoint(0);\r
+// return CGU_ERROR_INVALID_PARAM;\r
+// }\r
+ LPC_CGU->PLL1_CTRL |= (msel<<16) | (nsel<<12) | (psel<<8) | CGU_PLL1_FBSEL_MASK;\r
+ }else if(freq<320000000){\r
+ LPC_CGU->PLL1_CTRL |= (msel<<16) | (nsel<<12) | (psel<<8) |CGU_PLL1_DIRECT_MASK | CGU_PLL1_FBSEL_MASK;\r
+ }else\r
+ return CGU_ERROR_INVALID_PARAM;\r
+\r
+ return CGU_ERROR_SUCCESS;\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Get current base status\r
+ * @param[in] Base Base type, should be:\r
+ * - CGU_BASE_USB0 :Base clock for USB0\r
+ * - CGU_BASE_USB1 :Base clock for USB1\r
+ * - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core\r
+ * and APB peripheral blocks #0 and #2\r
+ * - CGU_BASE_SPIFI :Base clock for SPIFI\r
+ * - CGU_BASE_APB1 :Base clock for APB peripheral block #1\r
+ * - CGU_BASE_APB3 :Base clock for APB peripheral block #3\r
+ * - CGU_BASE_SDIO :Base clock for SDIO card reader\r
+ * - CGU_BASE_SSP0 :Base clock for SSP0\r
+ * - CGU_BASE_SSP1 :Base clock for SSP1\r
+ * - CGU_BASE_UART0 :Base clock for UART0\r
+ * - CGU_BASE_UART1 :Base clock for UART1\r
+ * - CGU_BASE_UART2 :Base clock for UART2\r
+ * - CGU_BASE_UART3 :Base clock for UART3\r
+ * @return Always return 0\r
+ **********************************************************************/\r
+uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base){\r
+ switch(Base){\r
+ /*CCU1*/\r
+ case CGU_BASE_APB3:\r
+ return LPC_CCU1->BASE_STAT & 1;\r
+\r
+ case CGU_BASE_APB1:\r
+ return (LPC_CCU1->BASE_STAT>>1) & 1;\r
+\r
+ case CGU_BASE_SPIFI:\r
+ return (LPC_CCU1->BASE_STAT>>2) & 1;\r
+\r
+ case CGU_BASE_M3:\r
+ return (LPC_CCU1->BASE_STAT>>3) & 1;\r
+\r
+ case CGU_BASE_USB0:\r
+ return (LPC_CCU1->BASE_STAT>>7) & 1;\r
+\r
+ case CGU_BASE_USB1:\r
+ return (LPC_CCU1->BASE_STAT>>8) & 1;\r
+\r
+ /*CCU2*/\r
+ case CGU_BASE_UART3:\r
+ return (LPC_CCU2->BASE_STAT>>1) & 1;\r
+\r
+ case CGU_BASE_UART2:\r
+ return (LPC_CCU2->BASE_STAT>>2) & 1;\r
+\r
+ case CGU_BASE_UART1:\r
+ return (LPC_CCU2->BASE_STAT>>3) & 1;\r
+\r
+ case CGU_BASE_UART0:\r
+ return (LPC_CCU2->BASE_STAT>>4) & 1;\r
+\r
+ case CGU_BASE_SSP1:\r
+ return (LPC_CCU2->BASE_STAT>>5) & 1;\r
+\r
+ case CGU_BASE_SSP0:\r
+ return (LPC_CCU2->BASE_STAT>>6) & 1;\r
+\r
+ case CGU_BASE_SDIO:\r
+ return (LPC_CCU2->BASE_STAT>>7) & 1;\r
+\r
+ /*BASE SAFE is used by WWDT and RGU*/\r
+ case CGU_BASE_SAFE:\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ return 0;\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Compare one source clock to IRC clock\r
+ * @param[in] Clock Clock entity that will be compared to IRC, should be:\r
+ * - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator\r
+ * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock\r
+ * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock\r
+ * - CGU_CLKSRC_GP_CLKIN :General purpose input clock\r
+ * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator\r
+ * - CGU_CLKSRC_PLL0 :PLL0 clock\r
+ * - CGU_CLKSRC_PLL1 :PLL1 clock\r
+ * - CGU_CLKSRC_IDIVA :Integer divider register A\r
+ * - CGU_CLKSRC_IDIVB :Integer divider register B\r
+ * - CGU_CLKSRC_IDIVC :Integer divider register C\r
+ * - CGU_CLKSRC_IDIVD :Integer divider register D\r
+ * - CGU_CLKSRC_IDIVE :Integer divider register E\r
+ * - CGU_BASE_SAFE :Base safe clock (always on)for WDT\r
+ * - CGU_BASE_USB0 :Base clock for USB0\r
+ * - CGU_BASE_USB1 :Base clock for USB1\r
+ * - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core\r
+ * and APB peripheral blocks #0 and #2\r
+ * - CGU_BASE_SPIFI :Base clock for SPIFI\r
+ * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx\r
+ * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx\r
+ * - CGU_BASE_APB1 :Base clock for APB peripheral block #1\r
+ * - CGU_BASE_APB3 :Base clock for APB peripheral block #3\r
+ * - CGU_BASE_LCD :Base clock for LCD\r
+ * - CGU_BASE_SDIO :Base clock for SDIO card reader\r
+ * - CGU_BASE_SSP0 :Base clock for SSP0\r
+ * - CGU_BASE_SSP1 :Base clock for SSP1\r
+ * - CGU_BASE_UART0 :Base clock for UART0\r
+ * - CGU_BASE_UART1 :Base clock for UART1\r
+ * - CGU_BASE_UART2 :Base clock for UART2\r
+ * - CGU_BASE_UART3 :Base clock for UART3\r
+ * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin\r
+ * @param[in] m Multiple value pointer\r
+ * @param[in] d Divider value pointer\r
+ * @return Compare status, could be:\r
+ * - (-1): fail\r
+ * - 0: successful\r
+ * @note Formula used to compare:\r
+ * FClock = F_IRC* m / d\r
+ **********************************************************************/\r
+int CGU_FrequencyMonitor(CGU_ENTITY_T Clock, uint32_t *m, uint32_t *d){\r
+ uint32_t n,c,temp;\r
+ int i;\r
+\r
+ /* Maximum allow RCOUNT number */\r
+ c= 511;\r
+ /* Check Source Clock Freq is larger or smaller */\r
+ LPC_CGU->FREQ_MON = (Clock<<24) | 1<<23 | c;\r
+ while(LPC_CGU->FREQ_MON & (1 <<23));\r
+ for(i=0;i<10000;i++);\r
+ temp = (LPC_CGU->FREQ_MON >>9) & 0x3FFF;\r
+\r
+ if(temp == 0) /* too low F < 12000000/511*/\r
+ return -1;\r
+ if(temp > 511){ /* larger */\r
+\r
+ c = 511 - (LPC_CGU->FREQ_MON&0x1FF);\r
+ }else{\r
+ do{\r
+ c--;\r
+ LPC_CGU->FREQ_MON = (Clock<<24) | 1<<23 | c;\r
+ while(LPC_CGU->FREQ_MON & (1 <<23));\r
+ for(i=0;i<10000;i++);\r
+ n = (LPC_CGU->FREQ_MON >>9) & 0x3FFF;\r
+ }while(n==temp);\r
+ c++;\r
+ }\r
+ *m = temp;\r
+ *d = c;\r
+ return 0;\r
+}\r
+\r
+/*********************************************************************//**\r
+ * @brief Compare one source clock to another source clock\r
+ * @param[in] Clock Clock entity that will be compared to second source, should be:\r
+ * - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator\r
+ * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock\r
+ * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock\r
+ * - CGU_CLKSRC_GP_CLKIN :General purpose input clock\r
+ * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator\r
+ * - CGU_CLKSRC_PLL0 :PLL0 clock\r
+ * - CGU_CLKSRC_PLL1 :PLL1 clock\r
+ * - CGU_CLKSRC_IDIVA :Integer divider register A\r
+ * - CGU_CLKSRC_IDIVB :Integer divider register B\r
+ * - CGU_CLKSRC_IDIVC :Integer divider register C\r
+ * - CGU_CLKSRC_IDIVD :Integer divider register D\r
+ * - CGU_CLKSRC_IDIVE :Integer divider register E\r
+ * - CGU_BASE_SAFE :Base safe clock (always on)for WDT\r
+ * - CGU_BASE_USB0 :Base clock for USB0\r
+ * - CGU_BASE_USB1 :Base clock for USB1\r
+ * - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core\r
+ * and APB peripheral blocks #0 and #2\r
+ * - CGU_BASE_SPIFI :Base clock for SPIFI\r
+ * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx\r
+ * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx\r
+ * - CGU_BASE_APB1 :Base clock for APB peripheral block #1\r
+ * - CGU_BASE_APB3 :Base clock for APB peripheral block #3\r
+ * - CGU_BASE_LCD :Base clock for LCD\r
+ * - CGU_BASE_SDIO :Base clock for SDIO card reader\r
+ * - CGU_BASE_SSP0 :Base clock for SSP0\r
+ * - CGU_BASE_SSP1 :Base clock for SSP1\r
+ * - CGU_BASE_UART0 :Base clock for UART0\r
+ * - CGU_BASE_UART1 :Base clock for UART1\r
+ * - CGU_BASE_UART2 :Base clock for UART2\r
+ * - CGU_BASE_UART3 :Base clock for UART3\r
+ * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin\r
+ * @param[in] CompareToClock Clock source that to be compared to first source, should be different\r
+ * to first source.\r
+ * @param[in] m Multiple value pointer\r
+ * @param[in] d Divider value pointer\r
+ * @return Compare status, could be:\r
+ * - (-1): fail\r
+ * - 0: successful\r
+ * @note Formula used to compare:\r
+ * FClock = m*FCompareToClock/d\r
+ **********************************************************************/\r
+uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d){\r
+ uint32_t m1,m2,d1,d2;\r
+ /* Check Parameter */\r
+ if((Clock>CGU_CLKSRC_IDIVE) || (CompareToClock>CGU_CLKSRC_IDIVE))\r
+ return CGU_ERROR_INVALID_PARAM;\r
+ /* Check for Clock Enable - Not yet implement\r
+ * The Comparator will hang if Clock has not been set*/\r
+ CGU_FrequencyMonitor(Clock, &m1, &d1);\r
+ CGU_FrequencyMonitor(CompareToClock, &m2, &d2);\r
+ *m= m1*d2;\r
+ *d= d1*m2;\r
+ return 0;\r
+\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* --------------------------------- End Of File ------------------------------ */\r
--- /dev/null
+/**********************************************************************\r
+* $Id$ lpc43xx_cgu.h 2011-06-02\r
+*//**\r
+* @file llpc43xx_cgu.h\r
+* @brief Contains all macro definitions and function prototypes\r
+* support for Clock Generation and Clock Control firmware\r
+* library on lpc43xx\r
+* @version 1.0\r
+* @date 02. June. 2011\r
+* @author NXP MCU SW Application Team\r
+*\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+***********************************************************************\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+\r
+/* Peripheral group ----------------------------------------------------------- */\r
+/** @defgroup CGU CGU (Clock Generation Unit)\r
+ * @ingroup LPC4300CMSIS_FwLib_Drivers\r
+ * @{\r
+ */\r
+\r
+#ifndef lpc43xx_CGU_H_\r
+#define lpc43xx_CGU_H_\r
+\r
+/* Includes ------------------------------------------------------------------- */\r
+#include "lpc43xx.h"\r
+#include "lpc_types.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+/* Private Macros -------------------------------------------------------------- */\r
+/** @defgroup CGU_Private_Macros CGU Private Macros\r
+ * @{\r
+ */\r
+\r
+/** Branch clocks from CGU_BASE_SAFE */\r
+#define CGU_ENTITY_NONE CGU_ENTITY_NUM\r
+\r
+/** Check bit at specific position is clear or not */\r
+#define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))\r
+/** Check bit at specific position is set or not */\r
+#define ISBITSET(x,bit) (x&(1<<bit))\r
+/** Set mask */\r
+#define ISMASKSET(x,mask) (x&mask)\r
+\r
+/** CGU number of clock source */\r
+#define CGU_CLKSRC_NUM (CGU_CLKSRC_IDIVE+1)\r
+\r
+/*********************************************************************//**\r
+ * Macro defines for CGU control mask bit definitions\r
+ **********************************************************************/\r
+/** CGU control enable mask bit */\r
+#define CGU_CTRL_EN_MASK 1\r
+/** CGU control clock-source mask bit */\r
+#define CGU_CTRL_SRC_MASK (0xF<<24)\r
+/** CGU control auto block mask bit */\r
+#define CGU_CTRL_AUTOBLOCK_MASK (1<<11)\r
+\r
+/*********************************************************************//**\r
+ * Macro defines for CGU PLL1 mask bit definitions\r
+ **********************************************************************/\r
+/** CGU PLL1 feedback select mask bit */\r
+#define CGU_PLL1_FBSEL_MASK (1<<6)\r
+/** CGU PLL1 Input clock bypass control mask bit */\r
+#define CGU_PLL1_BYPASS_MASK (1<<1)\r
+/** CGU PLL1 direct CCO output mask bit */\r
+#define CGU_PLL1_DIRECT_MASK (1<<7)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Public Types --------------------------------------------------------------- */\r
+/** @defgroup CGU_Public_Types CGU Public Types\r
+ * @{\r
+ */\r
+\r
+/*********************************************************************//**\r
+ * @brief CGU enumeration\r
+ **********************************************************************/\r
+/*\r
+ * @brief CGU clock source enumerate definition
+ */\r
+typedef enum {\r
+ /* Clock Source */\r
+ CGU_CLKSRC_32KHZ_OSC = 0, /**< 32KHz oscillator clock source */\r
+ CGU_CLKSRC_IRC, /**< IRC 12 Mhz clock source */\r
+ CGU_CLKSRC_ENET_RX_CLK, /**< Ethernet receive clock source */\r
+ CGU_CLKSRC_ENET_TX_CLK, /**< Ethernet transmit clock source */\r
+ CGU_CLKSRC_GP_CLKIN, /**< General purpose clock source */\r
+ CGU_CLKSRC_TCK, /**< TCK clock source */\r
+ CGU_CLKSRC_XTAL_OSC, /**< Crystal oscillator clock source*/\r
+ CGU_CLKSRC_PLL0, /**< PLL0 (USB0) clock source */\r
+ CGU_CLKSRC_PLL0_AUDIO,\r
+ CGU_CLKSRC_PLL1, /**< PLL1 clock source */\r
+ CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3, /**< IDIVA clock source */\r
+ CGU_CLKSRC_IDIVB, /**< IDIVB clock source */\r
+ CGU_CLKSRC_IDIVC, /**< IDIVC clock source */\r
+ CGU_CLKSRC_IDIVD, /**< IDIVD clock source */\r
+ CGU_CLKSRC_IDIVE, /**< IDIVE clock source */\r
+\r
+ /* Base */\r
+ CGU_BASE_SAFE, /**< Base save clock (always on) for WDT */\r
+ CGU_BASE_USB0, /**< USB0 base clock */\r
+ CGU_BASE_USB1 = CGU_BASE_USB0 + 2, /**< USB1 base clock */\r
+ CGU_BASE_M3, /**< ARM Cortex-M3 Core base clock */\r
+ CGU_BASE_SPIFI, /**< SPIFI base clock */\r
+ //CGU_BASE_SPI,\r
+ CGU_BASE_PHY_RX = CGU_BASE_SPIFI + 2, /**< Ethernet PHY Rx base clock */\r
+ CGU_BASE_PHY_TX, /**< Ethernet PHY Tx base clock */\r
+ CGU_BASE_APB1, /**< APB peripheral block #1 base clock */\r
+ CGU_BASE_APB3, /**< APB peripheral block #3 base clock */\r
+ CGU_BASE_LCD, /**< LCD base clock */\r
+ CGU_BASE_ENET_CSR,\r
+ CGU_BASE_SDIO, /**< SDIO base clock */\r
+ CGU_BASE_SSP0, /**< SSP0 base clock */\r
+ CGU_BASE_SSP1, /**< SSP1 base clock */\r
+ CGU_BASE_UART0, /**< UART0 base clock */\r
+ CGU_BASE_UART1, /**< UART1 base clock */\r
+ CGU_BASE_UART2, /**< UART2 base clock */\r
+ CGU_BASE_UART3, /**< UART3 base clock */\r
+ CGU_BASE_CLKOUT, /**< CLKOUT base clock */\r
+ CGU_BASE_APLL = CGU_BASE_CLKOUT + 5,\r
+ CGU_BASE_OUT0,\r
+ CGU_BASE_OUT1,\r
+ CGU_ENTITY_NUM /**< Number or clock source entity */\r
+} CGU_ENTITY_T;\r
+\r
+/*\r
+ * @brief CGU PPL0 mode enumerate definition\r
+ */\r
+typedef enum {\r
+ CGU_PLL0_MODE_1d = 0,\r
+ CGU_PLL0_MODE_1c,\r
+ CGU_PLL0_MODE_1b,\r
+ CGU_PLL0_MODE_1a\r
+}CGU_PLL0_MODE;\r
+\r
+/*\r
+ * @brief CGU peripheral enumerate definition\r
+ */\r
+typedef enum {\r
+ CGU_PERIPHERAL_ADC0 = 0, /**< ADC0 */\r
+ CGU_PERIPHERAL_ADC1, /**< ADC1 */\r
+ CGU_PERIPHERAL_AES, /**< AES */\r
+// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,\r
+ CGU_PERIPHERAL_APB1_BUS, /**< APB1 bus */\r
+ CGU_PERIPHERAL_APB3_BUS, /**< APB3 bus */\r
+ CGU_PERIPHERAL_CAN, /**< CAN */\r
+ CGU_PERIPHERAL_CREG, /**< CREG */\r
+ CGU_PERIPHERAL_DAC, /**< DAC */\r
+ CGU_PERIPHERAL_DMA, /**< DMA */\r
+ CGU_PERIPHERAL_EMC, /**< EMC */\r
+ CGU_PERIPHERAL_ETHERNET, /**< Ethernet */\r
+ CGU_PERIPHERAL_ETHERNET_TX, //HIDE /**< Ethernet transmit */\r
+ CGU_PERIPHERAL_GPIO, /**< GPIO */\r
+ CGU_PERIPHERAL_I2C0, /**< I2C0 */\r
+ CGU_PERIPHERAL_I2C1, /**< I2C1 */\r
+ CGU_PERIPHERAL_I2S, /**< I2S */\r
+ CGU_PERIPHERAL_LCD, /**< LCD */\r
+ CGU_PERIPHERAL_M3CORE, /**< ARM Cortex-M3 Core */\r
+ CGU_PERIPHERAL_M3_BUS, /**< ARM Cortex-M3 Bus */\r
+ CGU_PERIPHERAL_MOTOCON, /**< Motor Control */\r
+ CGU_PERIPHERAL_QEI, /**< QEI */\r
+ CGU_PERIPHERAL_RITIMER, /**< RIT Timer */\r
+ CGU_PERIPHERAL_SCT, /**< SCT */\r
+ CGU_PERIPHERAL_SCU, /**< SCU */\r
+ CGU_PERIPHERAL_SDIO, /**< SDIO */\r
+ CGU_PERIPHERAL_SPIFI, /**< SPIFI */\r
+ CGU_PERIPHERAL_SSP0, /**< SSP0 */\r
+ CGU_PERIPHERAL_SSP1, /**< SSP1 */\r
+ CGU_PERIPHERAL_TIMER0, /**< TIMER 0 */\r
+ CGU_PERIPHERAL_TIMER1, /**< TIMER 1 */\r
+ CGU_PERIPHERAL_TIMER2, /**< TIMER 2 */\r
+ CGU_PERIPHERAL_TIMER3, /**< TIMER 3 */\r
+ CGU_PERIPHERAL_UART0, /**< UART0 */\r
+ CGU_PERIPHERAL_UART1, /**< UART1 */\r
+ CGU_PERIPHERAL_UART2, /**< UART2 */\r
+ CGU_PERIPHERAL_UART3, /**< UART3 */\r
+ CGU_PERIPHERAL_USB0, /**< USB0 */\r
+ CGU_PERIPHERAL_USB1, /**< USB1 */\r
+ CGU_PERIPHERAL_WWDT, /**< WWDT */\r
+ CGU_PERIPHERAL_NUM\r
+} CGU_PERIPHERAL_T;\r
+\r
+/**\r
+ * @brief CGU error status enumerate definition\r
+ */\r
+typedef enum {\r
+ CGU_ERROR_SUCCESS = 0,\r
+ CGU_ERROR_CONNECT_TOGETHER,\r
+ CGU_ERROR_INVALID_ENTITY,\r
+ CGU_ERROR_INVALID_CLOCK_SOURCE,\r
+ CGU_ERROR_INVALID_PARAM,\r
+ CGU_ERROR_FREQ_OUTOF_RANGE\r
+} CGU_ERROR;\r
+\r
+/********************************************************************//**\r
+* @brief CGU structure definitions\r
+**********************************************************************/\r
+/*\r
+ * @brief CGU peripheral clock structure
+ */\r
+typedef struct {\r
+ uint8_t RegBaseEntity; /**< Base register address */\r
+ uint16_t RegBranchOffset; /**< Branch register offset */\r
+ uint8_t PerBaseEntity; /**< Base peripheral address */\r
+ uint16_t PerBranchOffset; /**< Base peripheral offset */\r
+ uint8_t next; /**< Pointer to next structure */\r
+} CGU_PERIPHERAL_S;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Public Functions ----------------------------------------------------------- */\r
+/** @defgroup CGU_Public_Functions CGU Public Functions\r
+ * @{\r
+ */\r
+\r
+/** Clock generate initialize/de-initialize */\r
+uint32_t CGU_Init(void);\r
+uint32_t CGU_DeInit(void);\r
+\r
+/** Clock Generator and Clock Control */\r
+uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en);\r
+uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock);\r
+\r
+/** Clock Source and Base Clock operation */\r
+uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency);\r
+uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor);\r
+uint32_t CGU_SetPLL0(void);\r
+uint32_t CGU_SetPLL1(uint32_t mult);\r
+uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en);\r
+uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity);\r
+uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base);\r
+void CGU_UpdateClock(void);\r
+uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* lpc43xx_CGU_H_ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* --------------------------------- End Of File ------------------------------ */\r
--- /dev/null
+/**********************************************************************\r
+* $Id$ lpc43xx_i2c.c 2011-06-02\r
+*//**\r
+* @file lpc43xx_i2c.c\r
+* @brief Contains all functions support for I2C firmware library\r
+* on lpc43xx\r
+* @version 1.0\r
+* @date 02. June. 2011\r
+* @author NXP MCU SW Application Team\r
+*\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+***********************************************************************\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+\r
+/* Peripheral group ----------------------------------------------------------- */\r
+/** @addtogroup I2C\r
+ * @{\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------- */\r
+#include "lpc43xx_i2c.h"\r
+#include "lpc43xx_cgu.h"\r
+#include "lpc43xx_scu.h"\r
+\r
+#define MD_EZI (0x1<<6)\r
+#define MD_ZI (0x1<<7)\r
+\r
+/* If this source file built with example, the lpc43xx FW library configuration\r
+ * file in each example directory ("lpc43xx_libcfg.h") must be included,\r
+ * otherwise the default FW library configuration file must be included instead\r
+ */\r
+#ifdef __BUILD_WITH_EXAMPLE__\r
+#include "lpc43xx_libcfg.h"\r
+#else\r
+#include "lpc43xx_libcfg_default.h"\r
+#endif /* __BUILD_WITH_EXAMPLE__ */\r
+\r
+\r
+#ifdef _I2C\r
+\r
+\r
+/* Private Types -------------------------------------------------------------- */\r
+/** @defgroup I2C_Private_Types I2C Private Types\r
+ * @{\r
+ */ \r
+#define SFSP2_3_CONFIGURE_I2C1_SDA (0x00000001 | MD_ZI | MD_EZI)\r
+#define SFSP2_4_CONFIGURE_I2C1_SCL (0x00000001 | MD_ZI | MD_EZI)\r
+#define SFSI2C0_CONFIGURE_STANDARD_FAST_MODE (1<<3 | 1<<11)\r
+#define SFSI2C0_CONFIGURE_FASTPLUS_HIGHSPEED_MODE (2<<1 | 1<<3 | 1<<7 | 1<<10 | 1<<11)\r
+\r
+/**\r
+ * @brief I2C device configuration structure type\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t txrx_setup; /* Transmission setup */\r
+ int32_t dir; /* Current direction phase, 0 - write, 1 - read */\r
+} I2C_CFG_T;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private Variables ---------------------------------------------------------- */\r
+/**\r
+ * @brief II2C driver data for I2C0, I2C1\r
+ */\r
+static I2C_CFG_T i2cdat[3];\r
+\r
+static uint32_t I2C_MasterComplete[3];\r
+static uint32_t I2C_SlaveComplete[3];\r
+\r
+static uint32_t I2C_MonitorBufferIndex;\r
+\r
+/* Private Functions ---------------------------------------------------------- */\r
+\r
+/* Get I2C number */\r
+static int32_t I2C_getNum(LPC_I2Cn_Type *I2Cx);\r
+\r
+/* Generate a start condition on I2C bus (in master mode only) */\r
+static uint32_t I2C_Start (LPC_I2Cn_Type *I2Cx);\r
+\r
+/* Generate a stop condition on I2C bus (in master mode only) */\r
+static void I2C_Stop (LPC_I2Cn_Type *I2Cx);\r
+\r
+/* I2C send byte subroutine */\r
+static uint32_t I2C_SendByte (LPC_I2Cn_Type *I2Cx, uint8_t databyte);\r
+\r
+/* I2C get byte subroutine */\r
+static uint32_t I2C_GetByte (LPC_I2Cn_Type *I2Cx, uint8_t *retdat, Bool ack);\r
+\r
+/*--------------------------------------------------------------------------------*/\r
+/********************************************************************//**\r
+ * @brief Convert from I2C peripheral to number\r
+ * @param[in] I2Cx I2C peripheral selected, should be:\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @return I2C number or error code, could be:\r
+ * - 0 :I2C0\r
+ * - 1 :I2C1\r
+ * - (-1) :Error\r
+ *********************************************************************/\r
+static int32_t I2C_getNum(LPC_I2Cn_Type *I2Cx){\r
+ if (I2Cx == LPC_I2C0) {\r
+ return (0);\r
+ } else if (I2Cx == LPC_I2C1) {\r
+ return (1);\r
+ }\r
+ return (-1);\r
+}\r
+\r
+\r
+/********************************************************************//**\r
+ * @brief Generate a start condition on I2C bus (in master mode only)\r
+ * @param[in] I2Cx I2C peripheral selected, should be:\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @return value of I2C status register after generate a start condition\r
+ *********************************************************************/\r
+static uint32_t I2C_Start (LPC_I2Cn_Type *I2Cx)\r
+{\r
+ I2Cx->CONSET = I2C_I2CONSET_STA;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+\r
+ // Wait for complete\r
+ while (!(I2Cx->CONSET & I2C_I2CONSET_SI));\r
+ I2Cx->CONCLR = I2C_I2CONCLR_STAC;\r
+ return (I2Cx->STAT & I2C_STAT_CODE_BITMASK);\r
+}\r
+\r
+\r
+/********************************************************************//**\r
+ * @brief Generate a stop condition on I2C bus (in master mode only)\r
+ * @param[in] I2Cx I2C peripheral selected, should be:\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @return None\r
+ *********************************************************************/\r
+static void I2C_Stop (LPC_I2Cn_Type *I2Cx)\r
+{\r
+\r
+ /* Make sure start bit is not active */\r
+ if (I2Cx->CONSET & I2C_I2CONSET_STA)\r
+ {\r
+ I2Cx->CONCLR = I2C_I2CONCLR_STAC;\r
+ }\r
+ I2Cx->CONSET = I2C_I2CONSET_STO;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+}\r
+\r
+\r
+/********************************************************************//**\r
+ * @brief Send a byte\r
+ * @param[in] I2Cx I2C peripheral selected, should be:\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @param[in] databyte sent data\r
+ * @return value of I2C status register after sending\r
+ *********************************************************************/\r
+static uint32_t I2C_SendByte (LPC_I2Cn_Type *I2Cx, uint8_t databyte)\r
+{\r
+ /* Make sure start bit is not active */\r
+ if (I2Cx->CONSET & I2C_I2CONSET_STA)\r
+ {\r
+ I2Cx->CONCLR = I2C_I2CONCLR_STAC;\r
+ }\r
+ I2Cx->DAT = databyte & I2C_I2DAT_BITMASK;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+\r
+ while (!(I2Cx->CONSET & I2C_I2CONSET_SI));\r
+ return (I2Cx->STAT & I2C_STAT_CODE_BITMASK);\r
+}\r
+\r
+\r
+/********************************************************************//**\r
+ * @brief Get a byte\r
+ * @param[in] I2Cx I2C peripheral selected, should be:\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @param[out] retdat pointer to return data\r
+ * @param[in] ack assert acknowledge or not, should be: TRUE/FALSE\r
+ * @return value of I2C status register after sending\r
+ *********************************************************************/\r
+static uint32_t I2C_GetByte (LPC_I2Cn_Type *I2Cx, uint8_t *retdat, Bool ack)\r
+{\r
+ if (ack == TRUE)\r
+ {\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ }\r
+ else\r
+ {\r
+ I2Cx->CONCLR = I2C_I2CONCLR_AAC;\r
+ }\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+\r
+ while (!(I2Cx->CONSET & I2C_I2CONSET_SI));\r
+ *retdat = (uint8_t) (I2Cx->DAT & I2C_I2DAT_BITMASK);\r
+ return (I2Cx->STAT & I2C_STAT_CODE_BITMASK);\r
+}\r
+\r
+/* End of Private Functions --------------------------------------------------- */\r
+\r
+\r
+/* Public Functions ----------------------------------------------------------- */\r
+/** @addtogroup I2C_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/********************************************************************//**\r
+ * @brief Initializes the I2Cx peripheral with specified parameter.\r
+ * @param[in] I2Cx I2C peripheral selected, should be\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @param[in] clockrate Target clock rate value to initialized I2C\r
+ * peripheral (Hz)\r
+ * @return None\r
+ *********************************************************************/\r
+void I2C_Init(LPC_I2Cn_Type *I2Cx, uint32_t clockrate)\r
+{\r
+ uint32_t tem;\r
+\r
+ CHECK_PARAM(PARAM_I2Cx(I2Cx));\r
+\r
+ if (I2Cx==LPC_I2C0)\r
+ {\r
+ /* Set up clock for I2C0 module */\r
+ //LPC_CGU->BASE_VPB1_CLK = (SRC_PL160M_0<<24) | (1<<11);\r
+ CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_APB1);\r
+ /* Select weather standard, fast, fast plus mode*/\r
+ if(clockrate>=1000000)// Fast mode plus: 1MHz, high speed 3.4MHz\r
+ LPC_SCU->SFSI2C0 = SFSI2C0_CONFIGURE_FASTPLUS_HIGHSPEED_MODE;\r
+ else // standard 100KHz, fast 400KHz\r
+ LPC_SCU->SFSI2C0 = SFSI2C0_CONFIGURE_STANDARD_FAST_MODE;\r
+ }\r
+ else if (I2Cx==LPC_I2C1)\r
+ {\r
+ /* Set up clock for I2C1 module */\r
+ //LPC_CGU->BASE_VPB3_CLK = (SRC_PL160M_0<<24) | (1<<11);\r
+ CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_APB3);\r
+ /* Configure pin function for I2C1*/\r
+ LPC_SCU->SFSP2_3 = SFSP2_3_CONFIGURE_I2C1_SDA; /* SDA */\r
+ LPC_SCU->SFSP2_4 = SFSP2_4_CONFIGURE_I2C1_SCL; /* SCL */\r
+ /* Check if I2C1 run fast mode*/\r
+ if(clockrate != 400000)\r
+ return;\r
+ }\r
+ else {\r
+ // Up-Support this device\r
+ return;\r
+ }\r
+\r
+ /* Set clock rate */\r
+ if(clockrate<1000) //make sure SCLH,SCLL not exceed its 16bit value\r
+ return;\r
+ tem = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE) / clockrate;\r
+ I2Cx->SCLH = (uint32_t)(tem / 2);\r
+ I2Cx->SCLL = (uint32_t)(tem - I2Cx->SCLH);\r
+ /* Set I2C operation to default */\r
+ I2Cx->CONCLR = (I2C_I2CONCLR_AAC |I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_I2ENC);\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief De-initializes the I2C peripheral registers to their\r
+ * default reset values.\r
+ * @param[in] I2Cx I2C peripheral selected, should be\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @return None\r
+ **********************************************************************/\r
+void I2C_DeInit(LPC_I2Cn_Type* I2Cx)\r
+{\r
+ CHECK_PARAM(PARAM_I2Cx(I2Cx));\r
+\r
+ /* Disable I2C control */\r
+ I2Cx->CONCLR = I2C_I2CONCLR_I2ENC;\r
+\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Enable or disable I2C peripheral's operation\r
+ * @param[in] I2Cx I2C peripheral selected, should be\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @param[in] NewState New State of I2Cx peripheral's operation, should be:\r
+ * - ENABLE :enable I2C operation\r
+ * - DISABLE :disable I2C operation\r
+ * @return none\r
+ **********************************************************************/\r
+void I2C_Cmd(LPC_I2Cn_Type* I2Cx, FunctionalState NewState)\r
+{\r
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
+ CHECK_PARAM(PARAM_I2Cx(I2Cx));\r
+\r
+ if (NewState == ENABLE)\r
+ {\r
+ I2Cx->CONSET = I2C_I2CONSET_I2EN;\r
+ }\r
+ else\r
+ {\r
+ I2Cx->CONCLR = I2C_I2CONCLR_I2ENC;\r
+ }\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Enable/Disable interrupt for I2C peripheral\r
+ * @param[in] I2Cx I2C peripheral selected, should be:\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @param[in] NewState New State of I2C peripheral interrupt in NVIC core\r
+ * should be:\r
+ * - ENABLE: enable interrupt for this I2C peripheral\r
+ * - DISABLE: disable interrupt for this I2C peripheral\r
+ * @return None\r
+ **********************************************************************/\r
+void I2C_IntCmd (LPC_I2Cn_Type *I2Cx, Bool NewState)\r
+{\r
+ if (NewState)\r
+ {\r
+ if(I2Cx == LPC_I2C0)\r
+ {\r
+ NVIC_EnableIRQ(I2C0_IRQn);\r
+ }\r
+ else if (I2Cx == LPC_I2C1)\r
+ {\r
+ NVIC_EnableIRQ(I2C1_IRQn);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(I2Cx == LPC_I2C0)\r
+ {\r
+ NVIC_DisableIRQ(I2C0_IRQn);\r
+ }\r
+ else if (I2Cx == LPC_I2C1)\r
+ {\r
+ NVIC_DisableIRQ(I2C1_IRQn);\r
+ }\r
+ }\r
+ return;\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief General Master Interrupt handler for I2C peripheral\r
+ * @param[in] I2Cx I2C peripheral selected, should be:\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @return None\r
+ **********************************************************************/\r
+void I2C_MasterHandler (LPC_I2Cn_Type *I2Cx)\r
+{\r
+ int32_t tmp;\r
+ uint8_t returnCode;\r
+ I2C_M_SETUP_Type *txrx_setup;\r
+\r
+ tmp = I2C_getNum(I2Cx);\r
+ txrx_setup = (I2C_M_SETUP_Type *) i2cdat[tmp].txrx_setup;\r
+\r
+ returnCode = (I2Cx->STAT & I2C_STAT_CODE_BITMASK);\r
+ // Save current status\r
+ txrx_setup->status = returnCode;\r
+ // there's no relevant information\r
+ if (returnCode == I2C_I2STAT_NO_INF){\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ return;\r
+ }\r
+\r
+ /* ----------------------------- TRANSMIT PHASE --------------------------*/\r
+ if (i2cdat[tmp].dir == 0){\r
+ switch (returnCode)\r
+ {\r
+ /* A start/repeat start condition has been transmitted -------------------*/\r
+ case I2C_I2STAT_M_TX_START:\r
+ case I2C_I2STAT_M_TX_RESTART:\r
+ I2Cx->CONCLR = I2C_I2CONCLR_STAC;\r
+ /*\r
+ * If there's any transmit data, then start to\r
+ * send SLA+W right now, otherwise check whether if there's\r
+ * any receive data for next state.\r
+ */\r
+ if ((txrx_setup->tx_data != NULL) && (txrx_setup->tx_length != 0)){\r
+ I2Cx->DAT = (txrx_setup->sl_addr7bit << 1);\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ } else {\r
+ goto next_stage;\r
+ }\r
+ break;\r
+\r
+ /* SLA+W has been transmitted, ACK has been received ----------------------*/\r
+ case I2C_I2STAT_M_TX_SLAW_ACK:\r
+ /* Data has been transmitted, ACK has been received */\r
+ case I2C_I2STAT_M_TX_DAT_ACK:\r
+ /* Send more data */\r
+ if ((txrx_setup->tx_count < txrx_setup->tx_length) \\r
+ && (txrx_setup->tx_data != NULL)){\r
+ I2Cx->DAT = *(uint8_t *)(txrx_setup->tx_data + txrx_setup->tx_count);\r
+ txrx_setup->tx_count++;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ }\r
+ // no more data, switch to next stage\r
+ else {\r
+next_stage:\r
+ // change direction\r
+ i2cdat[tmp].dir = 1;\r
+ // Check if any data to receive\r
+ if ((txrx_setup->rx_length != 0) && (txrx_setup->rx_data != NULL)){\r
+ // check whether if we need to issue an repeat start\r
+ if ((txrx_setup->tx_length != 0) && (txrx_setup->tx_data != NULL)){\r
+ // Send out an repeat start command\r
+ I2Cx->CONSET = I2C_I2CONSET_STA;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC;\r
+ }\r
+ // Don't need issue an repeat start, just goto send SLA+R\r
+ else {\r
+ goto send_slar;\r
+ }\r
+ }\r
+ // no more data send, the go to end stage now\r
+ else {\r
+ // success, goto end stage\r
+ txrx_setup->status |= I2C_SETUP_STATUS_DONE;\r
+ goto end_stage;\r
+ }\r
+ }\r
+ break;\r
+\r
+ /* SLA+W has been transmitted, NACK has been received ----------------------*/\r
+ case I2C_I2STAT_M_TX_SLAW_NACK:\r
+ /* Data has been transmitted, NACK has been received -----------------------*/\r
+ case I2C_I2STAT_M_TX_DAT_NACK:\r
+ // update status\r
+ txrx_setup->status |= I2C_SETUP_STATUS_NOACKF;\r
+ goto retry;\r
+ /* Arbitration lost in SLA+R/W or Data bytes -------------------------------*/\r
+ case I2C_I2STAT_M_TX_ARB_LOST:\r
+ // update status\r
+ txrx_setup->status |= I2C_SETUP_STATUS_ARBF;\r
+ default:\r
+ goto retry;\r
+ }\r
+ }\r
+\r
+ /* ----------------------------- RECEIVE PHASE --------------------------*/\r
+ else if (i2cdat[tmp].dir == 1){\r
+ switch (returnCode){\r
+ /* A start/repeat start condition has been transmitted ---------------------*/\r
+ case I2C_I2STAT_M_RX_START:\r
+ case I2C_I2STAT_M_RX_RESTART:\r
+ I2Cx->CONCLR = I2C_I2CONCLR_STAC;\r
+ /*\r
+ * If there's any receive data, then start to\r
+ * send SLA+R right now, otherwise check whether if there's\r
+ * any receive data for end of state.\r
+ */\r
+ if ((txrx_setup->rx_data != NULL) && (txrx_setup->rx_length != 0)){\r
+send_slar:\r
+ I2Cx->DAT = (txrx_setup->sl_addr7bit << 1) | 0x01;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ } else {\r
+ // Success, goto end stage\r
+ txrx_setup->status |= I2C_SETUP_STATUS_DONE;\r
+ goto end_stage;\r
+ }\r
+ break;\r
+\r
+ /* SLA+R has been transmitted, ACK has been received -----------------*/\r
+ case I2C_I2STAT_M_RX_SLAR_ACK:\r
+ if (txrx_setup->rx_count < (txrx_setup->rx_length - 1)) {\r
+ /*Data will be received, ACK will be return*/\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ }\r
+ else {\r
+ /*Last data will be received, NACK will be return*/\r
+ I2Cx->CONCLR = I2C_I2CONSET_AA;\r
+ }\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ break;\r
+\r
+ /* Data has been received, ACK has been returned ----------------------*/\r
+ case I2C_I2STAT_M_RX_DAT_ACK:\r
+ // Note save data and increase counter first, then check later\r
+ /* Save data */\r
+ if ((txrx_setup->rx_data != NULL) && (txrx_setup->rx_count < txrx_setup->rx_length)){\r
+ *(uint8_t *)(txrx_setup->rx_data + txrx_setup->rx_count) = (I2Cx->DAT & I2C_I2DAT_BITMASK);\r
+ txrx_setup->rx_count++;\r
+ }\r
+ if (txrx_setup->rx_count < (txrx_setup->rx_length - 1)) {\r
+ /*Data will be received, ACK will be return*/\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ }\r
+ else {\r
+ /*Last data will be received, NACK will be return*/\r
+ I2Cx->CONCLR = I2C_I2CONSET_AA;\r
+ }\r
+\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ break;\r
+\r
+ /* Data has been received, NACK has been return -------------------------*/\r
+ case I2C_I2STAT_M_RX_DAT_NACK:\r
+ /* Save the last data */\r
+ if ((txrx_setup->rx_data != NULL) && (txrx_setup->rx_count < txrx_setup->rx_length)){\r
+ *(uint8_t *)(txrx_setup->rx_data + txrx_setup->rx_count) = (I2Cx->DAT & I2C_I2DAT_BITMASK);\r
+ txrx_setup->rx_count++;\r
+ }\r
+ // success, go to end stage\r
+ txrx_setup->status |= I2C_SETUP_STATUS_DONE;\r
+ goto end_stage;\r
+\r
+ /* SLA+R has been transmitted, NACK has been received ------------------*/\r
+ case I2C_I2STAT_M_RX_SLAR_NACK:\r
+ // update status\r
+ txrx_setup->status |= I2C_SETUP_STATUS_NOACKF;\r
+ goto retry;\r
+\r
+ /* Arbitration lost ----------------------------------------------------*/\r
+ case I2C_I2STAT_M_RX_ARB_LOST:\r
+ // update status\r
+ txrx_setup->status |= I2C_SETUP_STATUS_ARBF;\r
+ default:\r
+retry:\r
+ // check if retransmission is available\r
+ if (txrx_setup->retransmissions_count < txrx_setup->retransmissions_max){\r
+ // Clear tx count\r
+ txrx_setup->tx_count = 0;\r
+ I2Cx->CONSET = I2C_I2CONSET_STA;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC;\r
+ txrx_setup->retransmissions_count++;\r
+ }\r
+ // End of stage\r
+ else {\r
+end_stage:\r
+ // Disable interrupt\r
+ I2C_IntCmd(I2Cx, FALSE);\r
+ // Send stop\r
+ I2C_Stop(I2Cx);\r
+\r
+ I2C_MasterComplete[tmp] = TRUE;\r
+ }\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief General Slave Interrupt handler for I2C peripheral\r
+ * @param[in] I2Cx I2C peripheral selected, should be:\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @return None\r
+ **********************************************************************/\r
+void I2C_SlaveHandler (LPC_I2Cn_Type *I2Cx)\r
+{\r
+ int32_t tmp;\r
+ uint8_t returnCode;\r
+ I2C_S_SETUP_Type *txrx_setup;\r
+ uint32_t timeout;\r
+\r
+ tmp = I2C_getNum(I2Cx);\r
+ txrx_setup = (I2C_S_SETUP_Type *) i2cdat[tmp].txrx_setup;\r
+\r
+ returnCode = (I2Cx->STAT & I2C_STAT_CODE_BITMASK);\r
+ // Save current status\r
+ txrx_setup->status = returnCode;\r
+ // there's no relevant information\r
+ if (returnCode == I2C_I2STAT_NO_INF){\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ return;\r
+ }\r
+\r
+\r
+ switch (returnCode)\r
+ {\r
+\r
+ /* No status information */\r
+ case I2C_I2STAT_NO_INF:\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ break;\r
+\r
+ /* Reading phase -------------------------------------------------------- */\r
+ /* Own SLA+R has been received, ACK has been returned */\r
+ case I2C_I2STAT_S_RX_SLAW_ACK:\r
+ /* General call address has been received, ACK has been returned */\r
+ case I2C_I2STAT_S_RX_GENCALL_ACK:\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ break;\r
+\r
+ /* Previously addressed with own SLA;\r
+ * DATA byte has been received;\r
+ * ACK has been returned */\r
+ case I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK:\r
+ /* DATA has been received, ACK hasn been return */\r
+ case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK:\r
+ /*\r
+ * All data bytes that over-flow the specified receive\r
+ * data length, just ignore them.\r
+ */\r
+ if ((txrx_setup->rx_count < txrx_setup->rx_length) \\r
+ && (txrx_setup->rx_data != NULL)){\r
+ *(uint8_t *)(txrx_setup->rx_data + txrx_setup->rx_count) = (uint8_t)I2Cx->DAT;\r
+ txrx_setup->rx_count++;\r
+ }\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ break;\r
+\r
+ /* Previously addressed with own SLA;\r
+ * DATA byte has been received;\r
+ * NOT ACK has been returned */\r
+ case I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK:\r
+ /* DATA has been received, NOT ACK has been returned */\r
+ case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK:\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ break;\r
+\r
+ /*\r
+ * Note that: Return code only let us know a stop condition mixed\r
+ * with a repeat start condition in the same code value.\r
+ * So we should provide a time-out. In case this is really a stop\r
+ * condition, this will return back after time out condition. Otherwise,\r
+ * next session that is slave receive data will be completed.\r
+ */\r
+\r
+ /* A Stop or a repeat start condition */\r
+ case I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX:\r
+ // Temporally lock the interrupt for timeout condition\r
+ I2C_IntCmd(I2Cx, FALSE);\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ // enable time out\r
+ timeout = I2C_SLAVE_TIME_OUT;\r
+ while(1){\r
+ if (I2Cx->CONSET & I2C_I2CONSET_SI){\r
+ // re-Enable interrupt\r
+ I2C_IntCmd(I2Cx, TRUE);\r
+ break;\r
+ } else {\r
+ timeout--;\r
+ if (timeout == 0){\r
+ // timeout occur, it's really a stop condition\r
+ txrx_setup->status |= I2C_SETUP_STATUS_DONE;\r
+ goto s_int_end;\r
+ }\r
+ }\r
+ }\r
+ break;\r
+\r
+ /* Writing phase -------------------------------------------------------- */\r
+ /* Own SLA+R has been received, ACK has been returned */\r
+ case I2C_I2STAT_S_TX_SLAR_ACK:\r
+ /* Data has been transmitted, ACK has been received */\r
+ case I2C_I2STAT_S_TX_DAT_ACK:\r
+ /*\r
+ * All data bytes that over-flow the specified receive\r
+ * data length, just ignore them.\r
+ */\r
+ if ((txrx_setup->tx_count < txrx_setup->tx_length) \\r
+ && (txrx_setup->tx_data != NULL)){\r
+ I2Cx->DAT = *(uint8_t *) (txrx_setup->tx_data + txrx_setup->tx_count);\r
+ txrx_setup->tx_count++;\r
+ }\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ break;\r
+\r
+ /* Data has been transmitted, NACK has been received,\r
+ * that means there's no more data to send, exit now */\r
+ /*\r
+ * Note: Don't wait for stop event since in slave transmit mode,\r
+ * since there no proof lets us know when a stop signal has been received\r
+ * on slave side.\r
+ */\r
+ case I2C_I2STAT_S_TX_DAT_NACK:\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ txrx_setup->status |= I2C_SETUP_STATUS_DONE;\r
+ goto s_int_end;\r
+\r
+ // Other status must be captured\r
+ default:\r
+s_int_end:\r
+ // Disable interrupt\r
+ I2C_IntCmd(I2Cx, FALSE);\r
+ I2Cx->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC;\r
+ I2C_SlaveComplete[tmp] = TRUE;\r
+ break;\r
+ }\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Transmit and Receive data in master mode\r
+ * @param[in] I2Cx I2C peripheral selected, should be:\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @param[in] TransferCfg Pointer to a I2C_M_SETUP_Type structure that\r
+ * contains specified information about the configuration\r
+ * for master transfer.\r
+ * @param[in] Opt a I2C_TRANSFER_OPT_Type type that selected for interrupt\r
+ * or polling mode.\r
+ * @return Transmit/receive status, should be:\r
+ * - SUCCESS\r
+ * - ERROR\r
+ *\r
+ * Note:\r
+ * - In case of using I2C to transmit data only, either transmit length set to 0\r
+ * or transmit data pointer set to NULL.\r
+ * - In case of using I2C to receive data only, either receive length set to 0\r
+ * or receive data pointer set to NULL.\r
+ * - In case of using I2C to transmit followed by receive data, transmit length,\r
+ * transmit data pointer, receive length and receive data pointer should be set\r
+ * corresponding.\r
+ **********************************************************************/\r
+Status I2C_MasterTransferData(LPC_I2Cn_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, \\r
+ I2C_TRANSFER_OPT_Type Opt)\r
+{\r
+ uint8_t *txdat;\r
+ uint8_t *rxdat;\r
+ uint32_t CodeStatus;\r
+ uint8_t tmp;\r
+\r
+ // reset all default state\r
+ txdat = (uint8_t *) TransferCfg->tx_data;\r
+ rxdat = (uint8_t *) TransferCfg->rx_data;\r
+ // Reset I2C setup value to default state\r
+ TransferCfg->tx_count = 0;\r
+ TransferCfg->rx_count = 0;\r
+ TransferCfg->status = 0;\r
+\r
+ if (Opt == I2C_TRANSFER_POLLING){\r
+\r
+ /* First Start condition -------------------------------------------------------------- */\r
+ TransferCfg->retransmissions_count = 0;\r
+retry:\r
+ // reset all default state\r
+ txdat = (uint8_t *) TransferCfg->tx_data;\r
+ rxdat = (uint8_t *) TransferCfg->rx_data;\r
+ // Reset I2C setup value to default state\r
+ TransferCfg->tx_count = 0;\r
+ TransferCfg->rx_count = 0;\r
+ CodeStatus = 0;\r
+\r
+ // Start command\r
+ CodeStatus = I2C_Start(I2Cx);\r
+ if ((CodeStatus != I2C_I2STAT_M_TX_START) \\r
+ && (CodeStatus != I2C_I2STAT_M_TX_RESTART)){\r
+ TransferCfg->retransmissions_count++;\r
+ if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){\r
+ // save status\r
+ TransferCfg->status = CodeStatus;\r
+ goto error;\r
+ } else {\r
+ goto retry;\r
+ }\r
+ }\r
+\r
+ /* In case of sending data first --------------------------------------------------- */\r
+ if ((TransferCfg->tx_length != 0) && (TransferCfg->tx_data != NULL)){\r
+\r
+ /* Send slave address + WR direction bit = 0 ----------------------------------- */\r
+ CodeStatus = I2C_SendByte(I2Cx, (TransferCfg->sl_addr7bit << 1));\r
+ if (CodeStatus != I2C_I2STAT_M_TX_SLAW_ACK){\r
+ TransferCfg->retransmissions_count++;\r
+ if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){\r
+ // save status\r
+ TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_NOACKF;\r
+ goto error;\r
+ } else {\r
+ goto retry;\r
+ }\r
+ }\r
+\r
+ /* Send a number of data bytes ---------------------------------------- */\r
+ while (TransferCfg->tx_count < TransferCfg->tx_length)\r
+ {\r
+ CodeStatus = I2C_SendByte(I2Cx, *txdat);\r
+ if (CodeStatus != I2C_I2STAT_M_TX_DAT_ACK){\r
+ TransferCfg->retransmissions_count++;\r
+ if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){\r
+ // save status\r
+ TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_NOACKF;\r
+ goto error;\r
+ } else {\r
+ goto retry;\r
+ }\r
+ }\r
+\r
+ txdat++;\r
+ TransferCfg->tx_count++;\r
+ }\r
+ }\r
+\r
+ /* Second Start condition (Repeat Start) ------------------------------------------- */\r
+ if ((TransferCfg->tx_length != 0) && (TransferCfg->tx_data != NULL) \\r
+ && (TransferCfg->rx_length != 0) && (TransferCfg->rx_data != NULL)){\r
+\r
+ CodeStatus = I2C_Start(I2Cx);\r
+ if ((CodeStatus != I2C_I2STAT_M_RX_START) \\r
+ && (CodeStatus != I2C_I2STAT_M_RX_RESTART)){\r
+ TransferCfg->retransmissions_count++;\r
+ if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){\r
+ // Update status\r
+ TransferCfg->status = CodeStatus;\r
+ goto error;\r
+ } else {\r
+ goto retry;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Then, start reading after sending data -------------------------------------- */\r
+ if ((TransferCfg->rx_length != 0) && (TransferCfg->rx_data != NULL)){\r
+ /* Send slave address + RD direction bit = 1 ----------------------------------- */\r
+\r
+ CodeStatus = I2C_SendByte(I2Cx, ((TransferCfg->sl_addr7bit << 1) | 0x01));\r
+ if (CodeStatus != I2C_I2STAT_M_RX_SLAR_ACK){\r
+ TransferCfg->retransmissions_count++;\r
+ if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){\r
+ // update status\r
+ TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_NOACKF;\r
+ goto error;\r
+ } else {\r
+ goto retry;\r
+ }\r
+ }\r
+\r
+ /* Receive a number of data bytes ------------------------------------------------- */\r
+ while (TransferCfg->rx_count < TransferCfg->rx_length){\r
+\r
+ /*\r
+ * Note that: if data length is only one, the master should not\r
+ * issue an ACK signal on bus after reading to avoid of next data frame\r
+ * on slave side\r
+ */\r
+ if (TransferCfg->rx_count < (TransferCfg->rx_length - 1)){\r
+ // Issue an ACK signal for next data frame\r
+ CodeStatus = I2C_GetByte(I2Cx, &tmp, TRUE);\r
+ if (CodeStatus != I2C_I2STAT_M_RX_DAT_ACK){\r
+ TransferCfg->retransmissions_count++;\r
+ if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){\r
+ // update status\r
+ TransferCfg->status = CodeStatus;\r
+ goto error;\r
+ } else {\r
+ goto retry;\r
+ }\r
+ }\r
+ } else {\r
+ // Do not issue an ACK signal\r
+ CodeStatus = I2C_GetByte(I2Cx, &tmp, FALSE);\r
+ if (CodeStatus != I2C_I2STAT_M_RX_DAT_NACK){\r
+ TransferCfg->retransmissions_count++;\r
+ if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){\r
+ // update status\r
+ TransferCfg->status = CodeStatus;\r
+ goto error;\r
+ } else {\r
+ goto retry;\r
+ }\r
+ }\r
+ }\r
+ *rxdat++ = tmp;\r
+ TransferCfg->rx_count++;\r
+ }\r
+ }\r
+\r
+ /* Send STOP condition ------------------------------------------------- */\r
+ I2C_Stop(I2Cx);\r
+ return SUCCESS;\r
+\r
+error:\r
+ // Send stop condition\r
+ I2C_Stop(I2Cx);\r
+ return ERROR;\r
+ }\r
+\r
+ else if (Opt == I2C_TRANSFER_INTERRUPT){\r
+ // Setup tx_rx data, callback and interrupt handler\r
+ tmp = I2C_getNum(I2Cx);\r
+ i2cdat[tmp].txrx_setup = (uint32_t) TransferCfg;\r
+ // Set direction phase, write first\r
+ i2cdat[tmp].dir = 0;\r
+\r
+ /* First Start condition -------------------------------------------------------------- */\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ I2Cx->CONSET = I2C_I2CONSET_STA;\r
+ I2C_IntCmd(I2Cx, TRUE);\r
+\r
+ return (SUCCESS);\r
+ }\r
+\r
+ return ERROR;\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Receive and Transmit data in slave mode\r
+ * @param[in] I2Cx I2C peripheral selected, should be\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @param[in] TransferCfg Pointer to a I2C_S_SETUP_Type structure that\r
+ * contains specified information about the configuration for\r
+ * master transfer.\r
+ * @param[in] Opt I2C_TRANSFER_OPT_Type type that selected for interrupt\r
+ * or polling mode.\r
+ * @return Transmit/receive status, could be:\r
+ * - SUCCESS\r
+ * - ERRRO\r
+ *\r
+ * Note:\r
+ * The mode of slave's operation depends on the command sent from master on\r
+ * the I2C bus. If the master send a SLA+W command, this sub-routine will\r
+ * use receive data length and receive data pointer. If the master send a SLA+R\r
+ * command, this sub-routine will use transmit data length and transmit data\r
+ * pointer.\r
+ * If the master issue an repeat start command or a stop command, the slave will\r
+ * enable an time out condition, during time out condition, if there's no activity\r
+ * on I2C bus, the slave will exit, otherwise (i.e. the master send a SLA+R/W),\r
+ * the slave then switch to relevant operation mode. The time out should be used\r
+ * because the return status code can not show difference from stop and repeat\r
+ * start command in slave operation.\r
+ * In case of the expected data length from master is greater than data length\r
+ * that slave can support:\r
+ * - In case of reading operation (from master): slave will return I2C_I2DAT_IDLE_CHAR\r
+ * value.\r
+ * - In case of writing operation (from master): slave will ignore remain data from master.\r
+ **********************************************************************/\r
+Status I2C_SlaveTransferData(LPC_I2Cn_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, \\r
+ I2C_TRANSFER_OPT_Type Opt)\r
+{\r
+ uint8_t *txdat;\r
+ uint8_t *rxdat;\r
+ uint32_t CodeStatus;\r
+ uint32_t timeout;\r
+ int32_t time_en;\r
+ int32_t tmp;\r
+\r
+ // reset all default state\r
+ txdat = (uint8_t *) TransferCfg->tx_data;\r
+ rxdat = (uint8_t *) TransferCfg->rx_data;\r
+ // Reset I2C setup value to default state\r
+ TransferCfg->tx_count = 0;\r
+ TransferCfg->rx_count = 0;\r
+ TransferCfg->status = 0;\r
+\r
+\r
+ // Polling option\r
+ if (Opt == I2C_TRANSFER_POLLING){\r
+\r
+ /* Set AA bit to ACK command on I2C bus */\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ /* Clear SI bit to be ready ... */\r
+ I2Cx->CONCLR = (I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC);\r
+\r
+ time_en = 0;\r
+ timeout = 0;\r
+\r
+ while (1)\r
+ {\r
+ /* Check SI flag ready */\r
+ if (I2Cx->CONSET & I2C_I2CONSET_SI)\r
+ {\r
+ time_en = 0;\r
+\r
+ switch (CodeStatus = (I2Cx->STAT & I2C_STAT_CODE_BITMASK))\r
+ {\r
+\r
+ /* No status information */\r
+ case I2C_I2STAT_NO_INF:\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ break;\r
+\r
+ /* Reading phase -------------------------------------------------------- */\r
+ /* Own SLA+R has been received, ACK has been returned */\r
+ case I2C_I2STAT_S_RX_SLAW_ACK:\r
+ /* General call address has been received, ACK has been returned */\r
+ case I2C_I2STAT_S_RX_GENCALL_ACK:\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ break;\r
+\r
+ /* Previously addressed with own SLA;\r
+ * DATA byte has been received;\r
+ * ACK has been returned */\r
+ case I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK:\r
+ /* DATA has been received, ACK hasn been return */\r
+ case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK:\r
+ /*\r
+ * All data bytes that over-flow the specified receive\r
+ * data length, just ignore them.\r
+ */\r
+ if ((TransferCfg->rx_count < TransferCfg->rx_length) \\r
+ && (TransferCfg->rx_data != NULL)){\r
+ *rxdat++ = (uint8_t)I2Cx->DAT;\r
+ TransferCfg->rx_count++;\r
+ }\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ break;\r
+\r
+ /* Previously addressed with own SLA;\r
+ * DATA byte has been received;\r
+ * NOT ACK has been returned */\r
+ case I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK:\r
+ /* DATA has been received, NOT ACK has been returned */\r
+ case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK:\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ break;\r
+\r
+ /*\r
+ * Note that: Return code only let us know a stop condition mixed\r
+ * with a repeat start condition in the same code value.\r
+ * So we should provide a time-out. In case this is really a stop\r
+ * condition, this will return back after time out condition. Otherwise,\r
+ * next session that is slave receive data will be completed.\r
+ */\r
+\r
+ /* A Stop or a repeat start condition */\r
+ case I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX:\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ // enable time out\r
+ time_en = 1;\r
+ timeout = 0;\r
+ break;\r
+\r
+ /* Writing phase -------------------------------------------------------- */\r
+ /* Own SLA+R has been received, ACK has been returned */\r
+ case I2C_I2STAT_S_TX_SLAR_ACK:\r
+ /* Data has been transmitted, ACK has been received */\r
+ case I2C_I2STAT_S_TX_DAT_ACK:\r
+ /*\r
+ * All data bytes that over-flow the specified receive\r
+ * data length, just ignore them.\r
+ */\r
+ if ((TransferCfg->tx_count < TransferCfg->tx_length) \\r
+ && (TransferCfg->tx_data != NULL)){\r
+ I2Cx->DAT = *txdat++;\r
+ TransferCfg->tx_count++;\r
+ }\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ break;\r
+\r
+ /* Data has been transmitted, NACK has been received,\r
+ * that means there's no more data to send, exit now */\r
+ /*\r
+ * Note: Don't wait for stop event since in slave transmit mode,\r
+ * since there no proof lets us know when a stop signal has been received\r
+ * on slave side.\r
+ */\r
+ case I2C_I2STAT_S_TX_DAT_NACK:\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ // enable time out\r
+ time_en = 1;\r
+ timeout = 0;\r
+ break;\r
+\r
+ // Other status must be captured\r
+ default:\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+ goto s_error;\r
+ }\r
+ } else if (time_en){\r
+ if (timeout++ > I2C_SLAVE_TIME_OUT){\r
+ // it's really a stop condition, goto end stage\r
+ goto s_end_stage;\r
+ }\r
+ }\r
+ }\r
+\r
+s_end_stage:\r
+ /* Clear AA bit to disable ACK on I2C bus */\r
+ I2Cx->CONCLR = I2C_I2CONCLR_AAC;\r
+ // Check if there's no error during operation\r
+ // Update status\r
+ TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_DONE;\r
+ return SUCCESS;\r
+\r
+s_error:\r
+ /* Clear AA bit to disable ACK on I2C bus */\r
+ I2Cx->CONCLR = I2C_I2CONCLR_AAC;\r
+ // Update status\r
+ TransferCfg->status = CodeStatus;\r
+ return ERROR;\r
+ }\r
+\r
+ else if (Opt == I2C_TRANSFER_INTERRUPT){\r
+ // Setup tx_rx data, callback and interrupt handler\r
+ tmp = I2C_getNum(I2Cx);\r
+ i2cdat[tmp].txrx_setup = (uint32_t) TransferCfg;\r
+ // Set direction phase, read first\r
+ i2cdat[tmp].dir = 1;\r
+\r
+ // Enable AA\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC;\r
+ I2C_IntCmd(I2Cx, TRUE);\r
+\r
+ return (SUCCESS);\r
+ }\r
+\r
+ return ERROR;\r
+}\r
+\r
+/*********************************************************************//**\r
+ * @brief Set Own slave address in I2C peripheral corresponding to\r
+ * parameter specified in OwnSlaveAddrConfigStruct.\r
+ * @param[in] I2Cx I2C peripheral selected, should be\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @param[in] OwnSlaveAddrConfigStruct Pointer to a I2C_OWNSLAVEADDR_CFG_Type\r
+ * structure that contains the configuration information for the\r
+ * specified I2C slave address.\r
+ * @return None\r
+ **********************************************************************/\r
+void I2C_SetOwnSlaveAddr(LPC_I2Cn_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct)\r
+{\r
+ uint32_t tmp;\r
+ CHECK_PARAM(PARAM_I2Cx(I2Cx));\r
+ CHECK_PARAM(PARAM_I2C_SLAVEADDR_CH(OwnSlaveAddrConfigStruct->SlaveAddrChannel));\r
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(OwnSlaveAddrConfigStruct->GeneralCallState));\r
+\r
+ tmp = (((uint32_t)(OwnSlaveAddrConfigStruct->SlaveAddr_7bit << 1)) \\r
+ | ((OwnSlaveAddrConfigStruct->GeneralCallState == ENABLE) ? 0x01 : 0x00))& I2C_I2ADR_BITMASK;\r
+ switch (OwnSlaveAddrConfigStruct->SlaveAddrChannel)\r
+ {\r
+ case 0:\r
+ I2Cx->ADR0 = tmp;\r
+ I2Cx->MASK[0] = I2C_I2MASK_MASK((uint32_t) \\r
+ (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));\r
+ break;\r
+ case 1:\r
+ I2Cx->ADR1 = tmp;\r
+ I2Cx->MASK[1] = I2C_I2MASK_MASK((uint32_t) \\r
+ (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));\r
+ break;\r
+ case 2:\r
+ I2Cx->ADR2 = tmp;\r
+ I2Cx->MASK[2] = I2C_I2MASK_MASK((uint32_t) \\r
+ (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));\r
+ break;\r
+ case 3:\r
+ I2Cx->ADR3 = tmp;\r
+ I2Cx->MASK[3] = I2C_I2MASK_MASK((uint32_t) \\r
+ (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));\r
+ break;\r
+ }\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Configures functionality in I2C monitor mode\r
+ * @param[in] I2Cx I2C peripheral selected, should be\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @param[in] MonitorCfgType Monitor Configuration type, should be:\r
+ * - I2C_MONITOR_CFG_SCL_OUTPUT :I2C module can 'stretch'\r
+ * the clock line (hold it low) until it has had time to respond\r
+ * to an I2C interrupt.\r
+ * - I2C_MONITOR_CFG_MATCHALL :When this bit is set to '1'\r
+ * and the I2C is in monitor mode, an interrupt will be generated\r
+ * on ANY address received.\r
+ * @param[in] NewState New State of this function, should be:\r
+ * - ENABLE :Enable this function.\r
+ * - DISABLE :Disable this function.\r
+ * @return None\r
+ **********************************************************************/\r
+void I2C_MonitorModeConfig(LPC_I2Cn_Type *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState)\r
+{\r
+ CHECK_PARAM(PARAM_I2Cx(I2Cx));\r
+ CHECK_PARAM(PARAM_I2C_MONITOR_CFG(MonitorCfgType));\r
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
+\r
+ if (NewState == ENABLE)\r
+ {\r
+ I2Cx->MMCTRL |= MonitorCfgType;\r
+ }\r
+ else\r
+ {\r
+ I2Cx->MMCTRL &= (~MonitorCfgType) & I2C_I2MMCTRL_BITMASK;\r
+ }\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Enable/Disable I2C monitor mode\r
+ * @param[in] I2Cx I2C peripheral selected, should be\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @param[in] NewState New State of this function, should be:\r
+ * - ENABLE :Enable monitor mode.\r
+ * - DISABLE :Disable monitor mode.\r
+ * @return None\r
+ **********************************************************************/\r
+void I2C_MonitorModeCmd(LPC_I2Cn_Type *I2Cx, FunctionalState NewState)\r
+{\r
+ CHECK_PARAM(PARAM_I2Cx(I2Cx));\r
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
+\r
+ if (NewState == ENABLE)\r
+ {\r
+ I2Cx->MMCTRL |= I2C_I2MMCTRL_MM_ENA;\r
+ I2Cx->CONSET = I2C_I2CONSET_AA;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC;\r
+ }\r
+ else\r
+ {\r
+ I2Cx->MMCTRL &= (~I2C_I2MMCTRL_MM_ENA) & I2C_I2MMCTRL_BITMASK;\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_AAC;\r
+ }\r
+ I2C_MonitorBufferIndex = 0;\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Get data from I2C data buffer in monitor mode.\r
+ * @param[in] I2Cx I2C peripheral selected, should be\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @return None\r
+ * Note: In monitor mode, the I2C module may lose the ability to stretch\r
+ * the clock (stall the bus) if the ENA_SCL bit is not set. This means that\r
+ * the processor will have a limited amount of time to read the contents of\r
+ * the data received on the bus. If the processor reads the I2DAT shift\r
+ * register, as it ordinarily would, it could have only one bit-time to\r
+ * respond to the interrupt before the received data is overwritten by\r
+ * new data.\r
+ **********************************************************************/\r
+uint8_t I2C_MonitorGetDatabuffer(LPC_I2Cn_Type *I2Cx)\r
+{\r
+ CHECK_PARAM(PARAM_I2Cx(I2Cx));\r
+ return ((uint8_t)(I2Cx->DATA_BUFFER));\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Get data from I2C data buffer in monitor mode.\r
+ * @param[in] I2Cx I2C peripheral selected, should be\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @return None\r
+ * Note: In monitor mode, the I2C module may lose the ability to stretch\r
+ * the clock (stall the bus) if the ENA_SCL bit is not set. This means that\r
+ * the processor will have a limited amount of time to read the contents of\r
+ * the data received on the bus. If the processor reads the I2DAT shift\r
+ * register, as it ordinarily would, it could have only one bit-time to\r
+ * respond to the interrupt before the received data is overwritten by\r
+ * new data.\r
+ **********************************************************************/\r
+BOOL_8 I2C_MonitorHandler(LPC_I2Cn_Type *I2Cx, uint8_t *buffer, uint32_t size)\r
+{\r
+ BOOL_8 ret=FALSE;\r
+\r
+ I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
+\r
+ buffer[I2C_MonitorBufferIndex] = (uint8_t)(I2Cx->DATA_BUFFER);\r
+ I2C_MonitorBufferIndex++;\r
+ if(I2C_MonitorBufferIndex >= size)\r
+ {\r
+ ret = TRUE;\r
+ }\r
+ return ret;\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Get status of Master Transfer\r
+ * @param[in] I2Cx I2C peripheral selected, should be:\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @return Master transfer status, could be:\r
+ * - TRUE :master transfer completed\r
+ * - FALSE :master transfer have not completed yet\r
+ **********************************************************************/\r
+uint32_t I2C_MasterTransferComplete(LPC_I2Cn_Type *I2Cx)\r
+{\r
+ uint32_t retval, tmp;\r
+ tmp = I2C_getNum(I2Cx);\r
+ retval = I2C_MasterComplete[tmp];\r
+ I2C_MasterComplete[tmp] = FALSE;\r
+ return retval;\r
+}\r
+\r
+\r
+/*********************************************************************//**\r
+ * @brief Get status of Slave Transfer\r
+ * @param[in] I2Cx I2C peripheral selected, should be:\r
+ * - LPC_I2C0 :I2C0 peripheral\r
+ * - LPC_I2C1 :I2C1 peripheral\r
+ * @return Complete status, could be: TRUE/FALSE\r
+ **********************************************************************/\r
+uint32_t I2C_SlaveTransferComplete(LPC_I2Cn_Type *I2Cx)\r
+{\r
+ uint32_t retval, tmp;\r
+ tmp = I2C_getNum(I2Cx);\r
+ retval = I2C_SlaveComplete[tmp];\r
+ I2C_SlaveComplete[tmp] = FALSE;\r
+ return retval;\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* _I2C */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* --------------------------------- End Of File ------------------------------ */\r
--- /dev/null
+/**********************************************************************\r
+* $Id$ lpc43xx_i2c.h 2011-06-02\r
+*//**\r
+* @file lpc43xx_i2c.h\r
+* @brief Contains all macro definitions and function prototypes\r
+* support for I2C firmware library on lpc43xx\r
+* @version 1.0\r
+* @date 02. June. 2011\r
+* @author NXP MCU SW Application Team\r
+*\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+***********************************************************************\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+\r
+/* Peripheral group ----------------------------------------------------------- */\r
+/** @defgroup I2C I2C (Inter-Integrated Circuit)\r
+ * @ingroup LPC4300CMSIS_FwLib_Drivers\r
+ * @{\r
+ */\r
+\r
+#ifndef lpc43xx_I2C_H_\r
+#define lpc43xx_I2C_H_\r
+\r
+/* Includes ------------------------------------------------------------------- */\r
+#include "lpc43xx.h"\r
+#include "lpc_types.h"\r
+\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/* Private Macros ------------------------------------------------------------- */\r
+/** @defgroup I2C_Private_Macros I2C Private Macros\r
+ * @{\r
+ */\r
+\r
+/* --------------------- BIT DEFINITIONS -------------------------------------- */\r
+/*******************************************************************//**\r
+ * I2C Control Set register description\r
+ *********************************************************************/\r
+#define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */\r
+#define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */\r
+#define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */\r
+#define I2C_I2CONSET_STA ((0x20)) /*!< START flag */\r
+#define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */\r
+\r
+/*******************************************************************//**\r
+ * I2C Control Clear register description\r
+ *********************************************************************/\r
+/** Assert acknowledge Clear bit */\r
+#define I2C_I2CONCLR_AAC ((1<<2))\r
+/** I2C interrupt Clear bit */\r
+#define I2C_I2CONCLR_SIC ((1<<3))\r
+/** START flag Clear bit */\r
+#define I2C_I2CONCLR_STAC ((1<<5))\r
+/** I2C interface Disable bit */\r
+#define I2C_I2CONCLR_I2ENC ((1<<6))\r
+\r
+/********************************************************************//**\r
+ * I2C Status Code definition (I2C Status register)\r
+ *********************************************************************/\r
+/* Return Code in I2C status register */\r
+#define I2C_STAT_CODE_BITMASK ((0xF8))\r
+\r
+/* I2C return status code definitions ----------------------------- */\r
+\r
+/** No relevant information */\r
+#define I2C_I2STAT_NO_INF ((0xF8))\r
+\r
+/* Master transmit mode -------------------------------------------- */\r
+/** A start condition has been transmitted */\r
+#define I2C_I2STAT_M_TX_START ((0x08))\r
+/** A repeat start condition has been transmitted */\r
+#define I2C_I2STAT_M_TX_RESTART ((0x10))\r
+/** SLA+W has been transmitted, ACK has been received */\r
+#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))\r
+/** SLA+W has been transmitted, NACK has been received */\r
+#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))\r
+/** Data has been transmitted, ACK has been received */\r
+#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))\r
+/** Data has been transmitted, NACK has been received */\r
+#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))\r
+/** Arbitration lost in SLA+R/W or Data bytes */\r
+#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))\r
+\r
+/* Master receive mode -------------------------------------------- */\r
+/** A start condition has been transmitted */\r
+#define I2C_I2STAT_M_RX_START ((0x08))\r
+/** A repeat start condition has been transmitted */\r
+#define I2C_I2STAT_M_RX_RESTART ((0x10))\r
+/** Arbitration lost */\r
+#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))\r
+/** SLA+R has been transmitted, ACK has been received */\r
+#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))\r
+/** SLA+R has been transmitted, NACK has been received */\r
+#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))\r
+/** Data has been received, ACK has been returned */\r
+#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))\r
+/** Data has been received, NACK has been return */\r
+#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))\r
+\r
+/* Slave receive mode -------------------------------------------- */\r
+/** Own slave address has been received, ACK has been returned */\r
+#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))\r
+\r
+/** Arbitration lost in SLA+R/W as master */\r
+#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))\r
+/** Own SLA+W has been received, ACK returned */\r
+//#define I2C_I2STAT_S_RX_SLAW_ACK ((0x68))\r
+\r
+/** General call address has been received, ACK has been returned */\r
+#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))\r
+\r
+/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */\r
+#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))\r
+/** General call address has been received, ACK has been returned */\r
+//#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78))\r
+\r
+/** Previously addressed with own SLV address;\r
+ * Data has been received, ACK has been return */\r
+#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))\r
+/** Previously addressed with own SLA;\r
+ * Data has been received and NOT ACK has been return */\r
+#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))\r
+/** Previously addressed with General Call;\r
+ * Data has been received and ACK has been return */\r
+#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))\r
+/** Previously addressed with General Call;\r
+ * Data has been received and NOT ACK has been return */\r
+#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))\r
+/** A STOP condition or repeated START condition has\r
+ * been received while still addressed as SLV/REC\r
+ * (Slave Receive) or SLV/TRX (Slave Transmit) */\r
+#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))\r
+\r
+/** Slave transmit mode */\r
+/** Own SLA+R has been received, ACK has been returned */\r
+#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))\r
+\r
+/** Arbitration lost in SLA+R/W as master */\r
+#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))\r
+/** Own SLA+R has been received, ACK has been returned */\r
+//#define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0))\r
+\r
+/** Data has been transmitted, ACK has been received */\r
+#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))\r
+/** Data has been transmitted, NACK has been received */\r
+#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))\r
+/** Last data byte in I2DAT has been transmitted (AA = 0);\r
+ ACK has been received */\r
+#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))\r
+\r
+/** Time out in case of using I2C slave mode */\r
+#define I2C_SLAVE_TIME_OUT 0x10000UL\r
+\r
+/********************************************************************//**\r
+ * I2C Data register definition\r
+ *********************************************************************/\r
+/** Mask for I2DAT register*/\r
+#define I2C_I2DAT_BITMASK ((0xFF))\r
+\r
+/** Idle data value will be send out in slave mode in case of the actual\r
+ * expecting data requested from the master is greater than its sending data\r
+ * length that can be supported */\r
+#define I2C_I2DAT_IDLE_CHAR (0xFF)\r
+\r
+/********************************************************************//**\r
+ * I2C Monitor mode control register description\r
+ *********************************************************************/\r
+#define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */\r
+#define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */\r
+#define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */\r
+#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */\r
+\r
+/********************************************************************//**\r
+ * I2C Data buffer register description\r
+ *********************************************************************/\r
+/** I2C Data buffer register bit mask */\r
+#define I2DATA_BUFFER_BITMASK ((0xFF))\r
+\r
+/********************************************************************//**\r
+ * I2C Slave Address registers definition\r
+ *********************************************************************/\r
+/** General Call enable bit */\r
+#define I2C_I2ADR_GC ((1<<0))\r
+/** I2C Slave Address registers bit mask */\r
+#define I2C_I2ADR_BITMASK ((0xFF))\r
+\r
+/********************************************************************//**\r
+ * I2C Mask Register definition\r
+ *********************************************************************/\r
+/** I2C Mask Register mask field */\r
+#define I2C_I2MASK_MASK(n) ((n&0xFE))\r
+\r
+/********************************************************************//**\r
+ * I2C SCL HIGH duty cycle Register definition\r
+ *********************************************************************/\r
+/** I2C SCL HIGH duty cycle Register bit mask */\r
+#define I2C_I2SCLH_BITMASK ((0xFFFF))\r
+\r
+/********************************************************************//**\r
+ * I2C SCL LOW duty cycle Register definition\r
+ *********************************************************************/\r
+/** I2C SCL LOW duty cycle Register bit mask */\r
+#define I2C_I2SCLL_BITMASK ((0xFFFF))\r
+\r
+/* I2C status values */\r
+#define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */\r
+#define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */\r
+#define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */\r
+\r
+/*********************************************************************//**\r
+ * I2C monitor control configuration defines\r
+ **********************************************************************/\r
+#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */\r
+#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */\r
+\r
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */\r
+/* Macros check I2C slave address */\r
+#define PARAM_I2C_SLAVEADDR_CH(n) (n<=3)\r
+\r
+/** Macro to determine if it is valid SSP port number */\r
+#define PARAM_I2Cx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \\r
+|| (((uint32_t *)n)==((uint32_t *)LPC_I2C1)))\r
+\r
+/* Macros check I2C monitor configuration type */\r
+#define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/* Public Types --------------------------------------------------------------- */\r
+/** @defgroup I2C_Public_Types I2C Public Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief I2C Own slave address setting structure
+ */\r
+typedef struct {\r
+ uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control,\r
+ should be in range from 0..3\r
+ */\r
+ uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */\r
+ uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality\r
+ when I2C control being in Slave mode, should be:\r
+ - ENABLE: Enable General Call function.\r
+ - DISABLE: Disable General Call function.\r
+ */\r
+ uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)\r
+ which is set to '1' will cause an automatic compare on\r
+ the corresponding bit of the received address when it\r
+ is compared to the SlaveAddr_7bit value associated with this\r
+ mask register. In other words, bits in SlaveAddr_7bit value\r
+ which are masked are not taken into account in determining\r
+ an address match\r
+ */\r
+} I2C_OWNSLAVEADDR_CFG_Type;\r
+\r
+\r
+/**\r
+ * @brief Master transfer setup data structure definitions\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t sl_addr7bit; /**< Slave address in 7bit mode */\r
+ uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit\r
+ is not used */\r
+ uint32_t tx_length; /**< Transmit data length - 0 if data transmit\r
+ is not used*/\r
+ uint32_t tx_count; /**< Current Transmit data counter */\r
+ uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive\r
+ is not used */\r
+ uint32_t rx_length; /**< Receive data length - 0 if data receive is\r
+ not used */\r
+ uint32_t rx_count; /**< Current Receive data counter */\r
+ uint32_t retransmissions_max; /**< Max Re-Transmission value */\r
+ uint32_t retransmissions_count; /**< Current Re-Transmission counter */\r
+ uint32_t status; /**< Current status of I2C activity */\r
+ void (*callback)(void); /**< Pointer to Call back function when transmission complete\r
+ used in interrupt transfer mode */\r
+} I2C_M_SETUP_Type;\r
+\r
+\r
+/**\r
+ * @brief Slave transfer setup data structure definitions\r
+ */\r
+typedef struct\r
+{\r
+ uint8_t* tx_data; /**< Pointer to transmit data - NULL if data transmit is not used */\r
+ uint32_t tx_length; /**< Transmit data length - 0 if data transmit is not used */\r
+ uint32_t tx_count; /**< Current transmit data counter */\r
+ uint8_t* rx_data; /**< Pointer to receive data - NULL if data received is not used */\r
+ uint32_t rx_length; /**< Receive data length - 0 if data receive is not used */\r
+ uint32_t rx_count; /**< Current receive data counter */\r
+ uint32_t status; /**< Current status of I2C activity */\r
+ void (*callback)(void); /**< Pointer to call-back function when transmission complete\r
+ used by interrupt transfer mode */\r
+} I2C_S_SETUP_Type;\r
+\r
+/**\r
+ * @brief Transfer option type definitions\r
+ */\r
+typedef enum {\r
+ I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */\r
+ I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */\r
+} I2C_TRANSFER_OPT_Type;\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Public Functions ----------------------------------------------------------- */\r
+/** @defgroup I2C_Public_Functions I2C Public Functions\r
+ * @{\r
+ */\r
+\r
+/* I2C Init/DeInit functions ---------- */\r
+void I2C_Init(LPC_I2Cn_Type *I2Cx, uint32_t clockrate);\r
+void I2C_DeInit(LPC_I2Cn_Type* I2Cx);\r
+//void I2C_SetClock (LPC_I2Cn_Type *I2Cx, uint32_t target_clock);\r
+void I2C_Cmd(LPC_I2Cn_Type* I2Cx, FunctionalState NewState);\r
+\r
+/* I2C transfer data functions -------- */\r
+Status I2C_MasterTransferData(LPC_I2Cn_Type *I2Cx, \\r
+ I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);\r
+Status I2C_SlaveTransferData(LPC_I2Cn_Type *I2Cx, \\r
+ I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);\r
+uint32_t I2C_MasterTransferComplete(LPC_I2Cn_Type *I2Cx);\r
+uint32_t I2C_SlaveTransferComplete(LPC_I2Cn_Type *I2Cx);\r
+\r
+\r
+void I2C_SetOwnSlaveAddr(LPC_I2Cn_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);\r
+uint8_t I2C_GetLastStatusCode(LPC_I2Cn_Type* I2Cx);\r
+\r
+/* I2C Monitor functions ---------------*/\r
+void I2C_MonitorModeConfig(LPC_I2Cn_Type *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);\r
+void I2C_MonitorModeCmd(LPC_I2Cn_Type *I2Cx, FunctionalState NewState);\r
+uint8_t I2C_MonitorGetDatabuffer(LPC_I2Cn_Type *I2Cx);\r
+BOOL_8 I2C_MonitorHandler(LPC_I2Cn_Type *I2Cx, uint8_t *buffer, uint32_t size);\r
+\r
+/* I2C Interrupt handler functions ------*/\r
+void I2C_IntCmd (LPC_I2Cn_Type *I2Cx, Bool NewState);\r
+void I2C_MasterHandler (LPC_I2Cn_Type *I2Cx);\r
+void I2C_SlaveHandler (LPC_I2Cn_Type *I2Cx);\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* lpc43xx_I2C_H_ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* --------------------------------- End Of File ------------------------------ */\r
--- /dev/null
+/**********************************************************************\r
+* $Id$ lpc43xx_libcfg_default.h 2011-06-02\r
+*//**\r
+* @file lpc43xx_libcfg_default.h\r
+* @brief Default Library configuration header file\r
+* @version 1.0\r
+* @date 02. June. 2011\r
+* @author NXP MCU SW Application Team\r
+*\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+***********************************************************************\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+\r
+/* Library Configuration group ----------------------------------------------------------- */\r
+/** @defgroup LIBCFG_DEFAULT LIBCFG_DEFAULT\r
+ * @ingroup LPC4300CMSIS_FwLib_Drivers\r
+ * @{\r
+ */\r
+\r
+#ifndef lpc43xx_LIBCFG_DEFAULT_H_\r
+#define lpc43xx_LIBCFG_DEFAULT_H_\r
+\r
+/* Includes ------------------------------------------------------------------- */\r
+#include "lpc_types.h"\r
+\r
+\r
+/* Public Macros -------------------------------------------------------------- */\r
+/** @defgroup LIBCFG_DEFAULT_Public_Macros LIBCFG_DEFAULT Public Macros\r
+ * @{\r
+ */\r
+\r
+/************************** DEBUG MODE DEFINITIONS *********************************/\r
+/* Un-comment the line below to compile the library in DEBUG mode, this will expanse\r
+ the "CHECK_PARAM" macro in the FW library code */\r
+\r
+//#define DEBUG\r
+\r
+\r
+/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/\r
+\r
+/* Comment the line below to disable the specific peripheral inclusion */\r
+\r
+/* GPIO ------------------------------- */\r
+#define _GPIO\r
+\r
+/* EXTI ------------------------------- */\r
+#define _EXTI\r
+\r
+/* UART ------------------------------- */\r
+#define _UART\r
+#define _UART0\r
+#define _UART1\r
+#define _UART2\r
+#define _UART3\r
+\r
+/* SPI ------------------------------- */\r
+#define _SPI\r
+\r
+/* SYSTICK --------------------------- */\r
+#define _SYSTICK\r
+\r
+/* SSP ------------------------------- */\r
+#define _SSP\r
+#define _SSP0\r
+#define _SSP1\r
+\r
+\r
+/* I2C ------------------------------- */\r
+#define _I2C\r
+#define _I2C0\r
+#define _I2C1\r
+#define _I2C2\r
+\r
+/* TIMER ------------------------------- */\r
+#define _TIM\r
+\r
+/* WWDT ------------------------------- */\r
+#define _WWDT\r
+\r
+\r
+/* GPDMA ------------------------------- */\r
+#define _GPDMA\r
+\r
+\r
+/* DAC ------------------------------- */\r
+#define _DAC\r
+\r
+/* DAC ------------------------------- */\r
+#define _ADC\r
+\r
+\r
+/* PWM ------------------------------- */\r
+#define _PWM\r
+#define _PWM1\r
+\r
+/* RTC ------------------------------- */\r
+#define _RTC\r
+\r
+/* I2S ------------------------------- */\r
+#define _I2S\r
+\r
+/* USB device ------------------------------- */\r
+#define _USBDEV\r
+#define _USB_DMA\r
+\r
+/* QEI ------------------------------- */\r
+#define _QEI\r
+\r
+/* MCPWM ------------------------------- */\r
+#define _MCPWM\r
+\r
+/* CAN--------------------------------*/\r
+#define _C_CAN\r
+\r
+/* RIT ------------------------------- */\r
+#define _RIT\r
+\r
+/* EMAC ------------------------------ */\r
+#define _EMAC\r
+\r
+/* SCT ------------------------------ */\r
+#define _SCT\r
+\r
+/* LCD ------------------------------ */\r
+#define _LCD\r
+\r
+/* ATIMER ------------------------------ */\r
+#define _ATIMER\r
+\r
+/* RGU ------------------------------ */\r
+#define _RGU\r
+\r
+/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/\r
+\r
+#ifdef DEBUG\r
+/*******************************************************************************\r
+* @brief The CHECK_PARAM macro is used for function's parameters check.\r
+* It is used only if the library is compiled in DEBUG mode.\r
+* @param[in] expr - If expr is false, it calls check_failed() function\r
+* which reports the name of the source file and the source\r
+* line number of the call that failed.\r
+* - If expr is true, it returns no value.\r
+* @return None\r
+*******************************************************************************/\r
+#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))\r
+#else\r
+#define CHECK_PARAM(expr)\r
+#endif /* DEBUG */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Public Functions ----------------------------------------------------------- */\r
+/** @defgroup LIBCFG_DEFAULT_Public_Functions LIBCFG_DEFAULT Public Functions\r
+ * @{\r
+ */\r
+\r
+#ifdef DEBUG\r
+void check_failed(uint8_t *file, uint32_t line);\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* lpc43xx_LIBCFG_DEFAULT_H_ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* --------------------------------- End Of File ------------------------------ */\r
--- /dev/null
+/**********************************************************************\r
+* $Id$ lpc43xx_scu.h 2011-06-02\r
+*//**\r
+* @file lpc43xx_scu.h\r
+* @brief Contains all macro definitions and function prototypes\r
+* support for SCU firmware library on lpc43xx\r
+* @version 1.0\r
+* @date 02. June. 2011\r
+* @author NXP MCU SW Application Team\r
+*\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+***********************************************************************\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+\r
+/* Peripheral group ----------------------------------------------------------- */\r
+/** @defgroup SCU SCU (System Control Unit)\r
+ * @ingroup LPC4300CMSIS_FwLib_Drivers\r
+ * @{\r
+ */\r
+\r
+#ifndef __SCU_H\r
+#define __SCU_H\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+/* Private macros ------------------------------------------------------------- */\r
+/** @defgroup SCT_Private_Macros SCT Private Macros\r
+ * @{\r
+ */\r
+\r
+/** Port offset definition */\r
+#define PORT_OFFSET 0x80\r
+/** Pin offset definition */\r
+#define PIN_OFFSET 0x04\r
+\r
+/* Pin modes */\r
+#define MD_PUP (0x0<<3)\r
+#define MD_BUK (0x1<<3)\r
+#define MD_PLN (0x2<<3)\r
+#define MD_PDN (0x3<<3)\r
+#define MD_EHS (0x1<<5)\r
+#define MD_EZI (0x1<<6)\r
+#define MD_ZI (0x1<<7)\r
+#define MD_EHD0 (0x1<<8)\r
+#define MD_EHD1 (0x1<<8)\r
+#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)\r
+// 0xF0\r
+\r
+/* Pin function */\r
+#define FUNC0 0x0 /** Function 0 */\r
+#define FUNC1 0x1 /** Function 1 */\r
+#define FUNC2 0x2 /** Function 2 */\r
+#define FUNC3 0x3 /** Function 3 */\r
+#define FUNC4 0x4\r
+#define FUNC5 0x5\r
+#define FUNC6 0x6\r
+#define FUNC7 0x7\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Public Functions ----------------------------------------------------------- */\r
+/** @defgroup SCU_Public_Functions SCU Public Functions\r
+ * @{\r
+ */\r
+\r
+void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* end __SCU_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* --------------------------------- End Of File ------------------------------ */\r
--- /dev/null
+/**********************************************************************\r
+* $Id$ lpc_types.h 2011-06-02\r
+*//**\r
+* @file lpc_types.h\r
+* @brief Contains the NXP ABL typedefs for C standard types.\r
+* It is intended to be used in ISO C conforming development\r
+* environments and checks for this insofar as it is possible\r
+* to do so.\r
+* @version 1.0\r
+* @date 02. June. 2011\r
+* @author NXP MCU SW Application Team\r
+*\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+***********************************************************************\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+\r
+/* Type group ----------------------------------------------------------- */\r
+/** @defgroup LPC_Types LPC_Types\r
+ * @ingroup LPC4300CMSIS_FwLib_Drivers\r
+ * @{\r
+ */\r
+\r
+#ifndef LPC_TYPES_H\r
+#define LPC_TYPES_H\r
+\r
+/* Includes ------------------------------------------------------------------- */\r
+#include <stdint.h>\r
+\r
+\r
+/* Public Types --------------------------------------------------------------- */\r
+/** @defgroup LPC_Types_Public_Types LPC_Types Public Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Boolean Type definition\r
+ */\r
+typedef enum {FALSE = 0, TRUE = !FALSE} Bool;\r
+\r
+/**\r
+ * @brief Flag Status and Interrupt Flag Status type definition\r
+ */\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;\r
+#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))\r
+\r
+/**\r
+ * @brief Functional State Definition\r
+ */\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))\r
+\r
+/**\r
+ * @ Status type definition\r
+ */\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;\r
+\r
+\r
+/**\r
+ * Read/Write transfer type mode (Block or non-block)\r
+ */\r
+typedef enum\r
+{\r
+ NONE_BLOCKING = 0, /**< None Blocking type */\r
+ BLOCKING, /**< Blocking type */\r
+} TRANSFER_BLOCK_Type;\r
+\r
+\r
+/** Pointer to Function returning Void (any number of parameters) */\r
+typedef void (*PFV)();\r
+\r
+/** Pointer to Function returning int32_t (any number of parameters) */\r
+typedef int32_t(*PFI)();\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Public Macros -------------------------------------------------------------- */\r
+/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros\r
+ * @{\r
+ */\r
+\r
+/* _BIT(n) sets the bit at position "n"\r
+ * _BIT(n) is intended to be used in "OR" and "AND" expressions:\r
+ * e.g., "(_BIT(3) | _BIT(7))".\r
+ */\r
+#undef _BIT\r
+/* Set bit macro */\r
+#define _BIT(n) (1<<(n))\r
+\r
+/* _SBF(f,v) sets the bit field starting at position "f" to value "v".\r
+ * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:\r
+ * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"\r
+ */\r
+#undef _SBF\r
+/* Set bit field macro */\r
+#define _SBF(f,v) ((v)<<(f))\r
+\r
+/* _BITMASK constructs a symbol with 'field_width' least significant\r
+ * bits set.\r
+ * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF\r
+ * The symbol is intended to be used to limit the bit field width\r
+ * thusly:\r
+ * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.\r
+ * If "any_expression" results in a value that is larger than can be\r
+ * contained in 'x' bits, the bits above 'x - 1' are masked off. When\r
+ * used with the _SBF example above, the example would be written:\r
+ * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))\r
+ * This ensures that the value written to a_reg is no wider than\r
+ * 16 bits, and makes the code easier to read and understand.\r
+ */\r
+#undef _BITMASK\r
+/* Bitmask creation macro */\r
+#define _BITMASK(field_width) ( _BIT(field_width) - 1)\r
+\r
+/* NULL pointer */\r
+#ifndef NULL\r
+#define NULL ((void*) 0)\r
+#endif\r
+\r
+/* Number of elements in an array */\r
+#define NELEMENTS(array) (sizeof (array) / sizeof (array[0]))\r
+\r
+/* Static data/function define */\r
+#define STATIC static\r
+/* External data/function define */\r
+#define EXTERN extern\r
+\r
+#if !defined(MAX)\r
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))\r
+#endif\r
+#if !defined(MIN)\r
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Old Type Definition compatibility ------------------------------------------ */\r
+/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types\r
+ * @{\r
+ */\r
+\r
+/** SMA type for character type */\r
+typedef char CHAR;\r
+\r
+/** SMA type for 8 bit unsigned value */\r
+typedef uint8_t UNS_8;\r
+\r
+/** SMA type for 8 bit signed value */\r
+typedef int8_t INT_8;\r
+\r
+/** SMA type for 16 bit unsigned value */\r
+typedef uint16_t UNS_16;\r
+\r
+/** SMA type for 16 bit signed value */\r
+typedef int16_t INT_16;\r
+\r
+/** SMA type for 32 bit unsigned value */\r
+typedef uint32_t UNS_32;\r
+\r
+/** SMA type for 32 bit signed value */\r
+typedef int32_t INT_32;\r
+\r
+/** SMA type for 64 bit signed value */\r
+typedef int64_t INT_64;\r
+\r
+/** SMA type for 64 bit unsigned value */\r
+typedef uint64_t UNS_64;\r
+\r
+/** 32 bit boolean type */\r
+typedef Bool BOOL_32;\r
+\r
+/** 16 bit boolean type */\r
+typedef Bool BOOL_16;\r
+\r
+/** 8 bit boolean type */\r
+typedef Bool BOOL_8;\r
+\r
+#ifdef __CC_ARM\r
+#define INLINE __inline\r
+#else\r
+#define INLINE inline\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+#endif /* LPC_TYPES_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* --------------------------------- End Of File ------------------------------ */\r
--- /dev/null
+#ifndef __PLATFORM_CHECK_H\r
+#define __PLATFORM_CHECK_H\r
+\r
+#warning "************ PLATFORM CONFIG ************"\r
+\r
+/* this is used to check the build platform */\r
+#if (PLATFORM == NXP_VALIDATION_BOARD) \r
+ #warning "*** Building for NXP VALIDATION BOARD ***" \r
+#elif (PLATFORM == HITEX_A2_BOARD)\r
+ #warning "Building for HITEX LPC4350EVA-2 platform" \r
+#else\r
+ #error "Platform not supported, check platform_config.h"\r
+#endif\r
+\r
+/* this is to ensure memory ranges are defined */\r
+#ifndef M4_ROM_START\r
+ #error "M4_ROM_START not defined, check platform_config.h"\r
+#endif\r
+#ifndef M4_ROM_LEN\r
+ #error "M4_ROM_LEN not defined, check platform_config.h"\r
+#endif\r
+#ifndef M4_RAM_START\r
+ #error "M4_RAM_START not defined, check platform_config.h"\r
+#endif\r
+#ifndef M4_RAM_LEN\r
+ #error "M4_RAM_LEN not defined, check platform_config.h"\r
+#endif\r
+\r
+#ifndef M0_ROM_START\r
+ #error "M0_ROM_START not defined, check platform_config.h"\r
+#endif\r
+#ifndef M0_ROM_LEN\r
+ #error "M0_ROM_LEN not defined, check platform_config.h"\r
+#endif\r
+#ifndef M0_RAM_START\r
+ #error "M0_RAM_START not defined, check platform_config.h"\r
+#endif\r
+#ifndef M0_RAM_LEN\r
+ #error "M0_RAM_LEN not defined, check platform_config.h"\r
+#endif\r
+\r
+/* feedback for mailboxes usage */\r
+\r
+/* configuration checks for M0 */\r
+#ifdef CORE_M4\r
+\r
+#if (USE_M4_MAILBOX == YES)\r
+\r
+ #warning "*** M4 mailbox: YES ***"\r
+\r
+ #if (USE_MAILBOX_PARAMETER == YES)\r
+ #warning "*** M4 mailbox parameter: YES ***"\r
+ #elif (USE_MAILBOX_PARAMETER == NO)\r
+ #warning "*** M4 mailbox parameter: NO ***"\r
+ #else \r
+ #error "*** Specify if M4 mailbox parameter is required (YES/NO) ***"\r
+ #endif\r
+ \r
+ #if (USE_MAILBOX_CALLBACK == YES)\r
+ #warning "*** M4 mailbox callback: YES ***"\r
+ #elif (USE_MAILBOX_CALLBACK == NO)\r
+ #warning "*** M4 mailbox callback: NO ***"\r
+ #else \r
+ #error "*** Specify if M4 mailbox callback is required (YES/NO) ***"\r
+ #endif\r
+\r
+#elif (USE_M4_MAILBOX == NO)\r
+ #warning "*** M4 mailbox: NO ***"\r
+#else \r
+ #error "*** Specify if M4 mailbox is required (YES/NO) ***"\r
+#endif\r
+\r
+#if (INITIALIZE_M0_IMAGE == YES) \r
+ #warning "*** M4 should download the M0 image: YES ***"\r
+#elif (INITIALIZE_M0_IMAGE == NO)\r
+ #warning "*** M4 should download the M0 image: NO ***"\r
+#else\r
+ #error "*** Specify if M4 should initialize the M0 image (YES/NO) ***"\r
+#endif\r
+\r
+/* check the build rules */\r
+#if (USE_EXT_FLASH == YES)\r
+ #warning "*** Building with external flash support: YES ***"\r
+#elif (USE_EXT_FLASH == NO)\r
+ #warning "*** Building with external flash support: NO ***"\r
+#endif\r
+\r
+#if (USE_EXT_STATIC_MEM == YES)\r
+ #warning "*** Building with external static memory support: YES ***"\r
+#elif (USE_EXT_STATIC_MEM == NO)\r
+ #warning "*** Building with external static memory support: NO ***"\r
+#endif\r
+\r
+#if (USE_EXT_DYNAMIC_MEM == YES)\r
+ #warning "*** Building for external dynamic memory support: YES ***"\r
+#elif (USE_EXT_DYNAMIC_MEM == NO)\r
+ #warning "*** Building for external dynamic memory support: NO ***"\r
+#endif\r
+ \r
+#endif /* CORE_M4 */\r
+\r
+/* configuration checks for M0 */\r
+#ifdef CORE_M0\r
+\r
+#if (USE_M0_MAILBOX == YES)\r
+ \r
+ #warning "*** M0 mailbox: YES ***"\r
+\r
+ #if (USE_MAILBOX_PARAMETER == YES)\r
+ #warning "*** M0 mailbox parameter: YES ***"\r
+ #elif (USE_MAILBOX_PARAMETER == NO)\r
+ #warning "*** M0 mailbox parameter: NO ***"\r
+ #else \r
+ #error "*** Specify if M0 mailbox parameter is required (YES/NO) ***"\r
+ #endif\r
+ \r
+ #if (USE_MAILBOX_CALLBACK == YES)\r
+ #warning "*** M0 mailbox callback: YES ***"\r
+ #elif (USE_MAILBOX_CALLBACK == NO)\r
+ #warning "*** M0 mailbox callback: NO ***"\r
+ #else \r
+ #error "*** Specify if M0 mailbox callback is required (YES/NO) ***"\r
+ #endif\r
+\r
+#elif (USE_M0_MAILBOX == NO)\r
+ #warning "*** M0 mailbox: NO ***"\r
+#else \r
+ #error "*** Specify if M0 mailbox is required (YES/NO) ***"\r
+#endif\r
+\r
+\r
+\r
+#endif /* CORE_M0 */\r
+\r
+#warning "************ PLATFORM CONFIG ************"\r
+\r
+#endif /* platform check */\r
+\r
+\r
+\r
--- /dev/null
+#include "LPC43xx.h"\r
+#include "platform_config.h"\r
+\r
+#include "scu.h"\r
+#include "type.h"\r
+#include "emc_LPC43xx.h"\r
+#include "fpu_init.h"\r
+\r
+\r
+/**********************************************************************\r
+ ** Function prototypes\r
+ **********************************************************************/\r
+void vIOInit(void);\r
+void clockInit(void);\r
+\r
+\r
+\r
+/* this function initializes the platform with system level settings */\r
+void platformInit(void) {\r
+\r
+ SystemInit();\r
+ \r
+ fpuInit(); \r
+ \r
+ clockInit();\r
+\r
+ vIOInit();\r
+\r
+ #if (USE_EXT_STATIC_MEM == YES) || (USE_EXT_DYNAMIC_MEM == YES)\r
+ \r
+ EMC_Init();\r
+ \r
+ #endif\r
+\r
+ #if (USE_EXT_FLASH == YES)\r
+ \r
+ // relocate vector table to internal ram\r
+ // updates also VTOR\r
+ relocIrqTable(); \r
+ \r
+ #endif\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ Initialize board specific IO\r
+ *----------------------------------------------------------------------------*/\r
+void vIOInit(void)\r
+{ \r
+ #if (PLATFORM == NXP_VALIDATION_BOARD)\r
+ // P9.2 : GPIO4_14: LD11 (LED)\r
+ scu_pinmux(0x9 ,2 , PDN_ENABLE, FUNC0); \r
+ LPC_GPIO4->DIR |= (1UL << 14);\r
+ #endif\r
+ #if (PLATFORM == HITEX_A2_BOARD)\r
+ // P9.3 : GPIO4_15\r
+ scu_pinmux(0x9 , 3 , PDN_ENABLE, FUNC0); \r
+ LPC_GPIO4->DIR |= (1UL << 15);\r
+ #endif \r
+}\r
+ \r
+/*----------------------------------------------------------------------------\r
+ Initialize clocks\r
+ *----------------------------------------------------------------------------*/\r
+void clockInit(void)\r
+{\r
+ /* Set PL160M @ 10*12=120 MHz */\r
+ SetPL160M(SRC_XTAL, 10); \r
+ /* Run base M4 clock from PL160M, no division */\r
+ SetClock(BASE_M4_CLK, SRC_PL160M_0, DIV1); \r
+ /* Show base out clock on output */\r
+ SetClock(BASE_OUT_CLK, SRC_XTAL, DIV1); \r
+ \r
+ // clock to UART 1\r
+ SetClock(BASE_UART1_CLK, SRC_PL160M_0, DIV1);\r
+\r
+ // clock to CAN1 > 15 MHz\r
+ // SetClock(BASE_VPB1_CLK, SRC_PL160M_0, DIV8); \r
+}\r
+\r
+\r
--- /dev/null
+#ifndef __PLATFORM_CONFIG_H \r
+#define __PLATFORM_CONFIG_H\r
+\r
+#include "stdint.h"\r
+\r
+/****************************************************/\r
+/* supported platforms list */\r
+/* DO NOT CHANGE THESE DEFINITIONS */\r
+#define NXP_VALIDATION_BOARD (1)\r
+#define HITEX_A2_BOARD (3)\r
+/****************************************************/\r
+\r
+/****************************************************/\r
+/* used for the configuration checks */\r
+/* DO NOT CHANGE THESE DEFINITIONS */\r
+/****************************************************/\r
+#define YES (1)\r
+#define NO (2)\r
+\r
+/****************************************************/\r
+/* USER CONFIGURATION SECTION */\r
+/****************************************************/\r
+\r
+/* choose the platform you want to build against */\r
+// #define PLATFORM NXP_VALIDATION_BOARD \r
+#define PLATFORM HITEX_A2_BOARD\r
+\r
+/* these definitions are being taken from the build rule */\r
+#ifdef EXT_FLASH\r
+#define USE_EXT_FLASH (YES)\r
+#else \r
+#define USE_EXT_FLASH (NO)\r
+#endif\r
+\r
+#ifdef EXT_STAT_MEM\r
+#define USE_EXT_STATIC_MEM (YES)\r
+#else\r
+#define USE_EXT_STATIC_MEM (NO)\r
+#endif\r
+\r
+#ifdef EXT_DYN_MEM\r
+#define USE_EXT_DYNAMIC_MEM (YES)\r
+#else\r
+#define USE_EXT_DYNAMIC_MEM (NO)\r
+#endif\r
+\r
+/* define if the M4 should download and start the M0 application */\r
+/* set to YES if M4 should initialize M0 application */\r
+/* set to NO if the debugger is downloading the M0 image, used for */\r
+/* dual core debugging sessions */\r
+#define INITIALIZE_M0_IMAGE (NO)\r
+\r
+/* specify if need to prefill the M0 memory before download */\r
+#define FILL_ROM_BEFORE_DOWNLOAD (NO)\r
+#define FILL_RAM_BEFORE_DOWNLOAD (NO)\r
+\r
+/* define if the M4 provides a mailbox system to the M0 */\r
+/* M0 ---> M4 */\r
+#define USE_M4_MAILBOX (NO)\r
+/* configure which priority the mailbox interrupt should have on the M4 side */\r
+/* cmsis definition, priority from 0 to 7 */\r
+#define M4_MAILBOX_PRIORITY (0)\r
+\r
+/* define if the M0 provides a mailbox system to the M4 */\r
+/* M4 ---> M0 */\r
+#define USE_M0_MAILBOX (NO)\r
+/* configure which priority the mailbox interrupt should have on the M0 side */\r
+/* cmsis definition, priority from 0 to 3 */\r
+#define M0_MAILBOX_PRIORITY (0)\r
+\r
+\r
+/* define if the system needs to exchange a parameter */\r
+#define USE_MAILBOX_PARAMETER (NO)\r
+\r
+/* define if the system needs to hook a callback, or just notify */\r
+#define USE_MAILBOX_CALLBACK (NO)\r
+\r
+\r
+/* memory map for the application */\r
+/* !!! needs to be consistent with the scatter file !!! */\r
+#ifdef EXT_FLASH\r
+\r
+/************************************/\r
+/* this is for the FLASH version */\r
+/************************************/\r
+/* 0x1C000000 M4 ROM 4Mbytes */\r
+/* 0x1C3FFFFF */\r
+/* 0x10000000 M4 RAM 96K */\r
+/* 0x10017FFF */\r
+#define M4_ROM_START 0x1C000000\r
+#define M4_ROM_LEN 0x400000 /* 4 Mbytes */\r
+\r
+#define M4_RAM_START 0x10000000 /* 96 Kbytes */\r
+#define M4_RAM_LEN 0x18000\r
+\r
+/* 0x10080000 M0 ROM 32K */\r
+/* 0x10087FFF */\r
+/* 0x10088000 M0 RAM 8K */\r
+/* 0x10089FFF */\r
+#define M0_ROM_START 0x10080000\r
+#define M0_ROM_LEN 0x8000\r
+\r
+#define M0_RAM_START 0x10088000\r
+#define M0_RAM_LEN 0x2000\r
+\r
+/* 0x20000000 M4 BUF 16K */\r
+/* 0x20003FFF */\r
+/* 0x20004000 M0 BUF 16K */\r
+/* 0x20007FFF */\r
+#define M4_BUF_START 0x20000000\r
+#define M4_BUF_LEN 0x4000\r
+\r
+#define M0_BUF_START 0x20004000\r
+#define M0_BUF_LEN 0x4000\r
+\r
+/* 0x20008000 M4 MBX 8K */\r
+/* 0x20009FFF */\r
+/* 0x2000A000 M0 MBX 8K */\r
+/* 0x2000BFFF */\r
+#define M4_MBX_START 0x20008000\r
+#define M4_MBX_LEN 0x2000\r
+\r
+#define M0_MBX_START 0x2000A000\r
+#define M0_MBX_LEN 0x2000\r
+\r
+#else \r
+\r
+/*******************************/\r
+/* this is for the ram version */\r
+/*******************************/\r
+/* 0x10000000 M4 ROM 64K */\r
+/* 0x1000FFFF */\r
+/* 0x10010000 M4 RAM 32K */\r
+/* 0x10017FFF */\r
+#define M4_ROM_START 0x10000000\r
+#define M4_ROM_LEN 0x10000\r
+\r
+#define M4_RAM_START 0x10010000\r
+#define M4_RAM_LEN 0x8000\r
+\r
+/* 0x10080000 M0 ROM 32K */\r
+/* 0x10087FFF */\r
+/* 0x10088000 M0 RAM 8K */\r
+/* 0x10089FFF */\r
+#define M0_ROM_START 0x10080000\r
+#define M0_ROM_LEN 0x8000\r
+\r
+#define M0_RAM_START 0x10088000\r
+#define M0_RAM_LEN 0x2000\r
+\r
+/* 0x20000000 M4 BUF 16K */\r
+/* 0x20003FFF */\r
+/* 0x20004000 M0 BUF 16K */\r
+/* 0x20007FFF */\r
+#define M4_BUF_START 0x20000000\r
+#define M4_BUF_LEN 0x4000\r
+\r
+#define M0_BUF_START 0x20004000\r
+#define M0_BUF_LEN 0x4000\r
+\r
+/* 0x20008000 M4 MBX 8K */\r
+/* 0x20009FFF */\r
+/* 0x2000A000 M0 MBX 8K */\r
+/* 0x2000BFFF */\r
+#define M4_MBX_START 0x20008000\r
+#define M4_MBX_LEN 0x2000\r
+\r
+#define M0_MBX_START 0x2000A000\r
+#define M0_MBX_LEN 0x2000\r
+\r
+#endif /* ifdef EXT_FLASH */\r
+\r
+/****************************************************/\r
+/* END OF USER CONFIGURATION */\r
+/* DO NOT EDIT BELOW THIS LINE */\r
+/****************************************************/\r
+\r
+#define M4_IPC_TABLE M4_MBX_START\r
+#define M0_IPC_TABLE M0_MBX_START\r
+\r
+/* configure defines for local mailbox */\r
+#if defined (CORE_M0) && (USE_M0_MAILBOX == YES)\r
+ #define PROVIDE_M0_LOCAL_MBX (1)\r
+#endif\r
+\r
+#if defined (CORE_M4) && (USE_M4_MAILBOX == YES)\r
+ #define PROVIDE_M4_LOCAL_MBX (1)\r
+#endif\r
+\r
+#if defined PROVIDE_M0_LOCAL_MBX || PROVIDE_M4_LOCAL_MBX\r
+ #define LOCAL_MAILBOX_ENABLED (1)\r
+#endif\r
+\r
+\r
+#if defined (CORE_M0) && (USE_M4_MAILBOX == YES)\r
+ #define PROVIDE_M0_REMOTE_MBX (1)\r
+#endif\r
+\r
+#if defined (CORE_M4) && (USE_M0_MAILBOX == YES)\r
+ #define PROVIDE_M4_REMOTE_MBX (1)\r
+#endif\r
+\r
+#if defined PROVIDE_M0_REMOTE_MBX || PROVIDE_M4_REMOTE_MBX\r
+ #define REMOTE_MAILBOX_ENABLED (1)\r
+#endif\r
+\r
+\r
+#if(USE_MAILBOX_PARAMETER == YES)\r
+ #define MBX_PARAM_DEFAULT ,0x0\r
+#else\r
+ #define MBX_PARAM_DEFAULT \r
+#endif\r
+\r
+#define DUMMY_CALLBACK ,(mbxCallback_t) &dummyCallback\r
+\r
+#if (USE_MAILBOX_CALLBACK == YES) \r
+ #define MBX_CALLBACK_DEFAULT DUMMY_CALLBACK\r
+#else\r
+ #define MBX_CALLBACK_DEFAULT\r
+#endif\r
+\r
+/****************************************************/\r
+/* platform wise initialization functions */\r
+/****************************************************/\r
+void platformInit(void);\r
+\r
+\r
+\r
+#endif /* __PLATFORM_CONFIG_H */\r
+\r
--- /dev/null
+;/***********************************************************************\r
+; * $Id: startup_LPC43xx.s 8389 2011-10-19 13:53:14Z nxp28536 $\r
+; *\r
+; * Project: LPC43xx CMSIS Package\r
+; *\r
+; * Description: Cortex-M4 Core Device Startup File for the NXP LPC18xx \r
+; * Device Series.\r
+; *\r
+; * Copyright(C) 2011, NXP Semiconductor\r
+; * All rights reserved.\r
+; *\r
+; ***********************************************************************\r
+; * Software that is described herein is for illustrative purposes only\r
+; * which provides customers with programming information regarding the\r
+; * products. This software is supplied "AS IS" without any warranties.\r
+; * NXP Semiconductors assumes no responsibility or liability for the\r
+; * use of the software, conveys no license or title under any patent,\r
+; * copyright, or mask work right to the product. NXP Semiconductors\r
+; * reserves the right to make changes in the software without\r
+; * notification. NXP Semiconductors also make no representation or\r
+; * warranty that such application will be suitable for the specified\r
+; * use without further testing or modification.\r
+; **********************************************************************/\r
+\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000400\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000000\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __endVectors\r
+\r
+Sign_Value EQU 0x5A5A5A5A\r
+\r
+; this might be meaningful only for images which require a header\r
+; IF :DEF:EXT_FLASH\r
+;\r
+;Signature_Size EQU 0x10\r
+; DCD 0x000200DA\r
+; DCD 0x00000000\r
+; DCD 0x00000000\r
+; DCD 0x00000000\r
+; SPACE Signature_Size \r
+; DCD __initial_sp\r
+; DCD Reset_Handler ; 1 Reset Handler\r
+; FILL 256 - 8 - 16\r
+; ENDIF\r
+\r
+\r
+__Vectors DCD __initial_sp ; 0 Top of Stack\r
+ DCD Reset_Handler ; 1 Reset Handler\r
+ DCD NMI_Handler ; 2 NMI Handler\r
+ DCD HardFault_Handler ; 3 Hard Fault Handler\r
+ DCD MemManage_Handler ; 4 MPU Fault Handler\r
+ DCD BusFault_Handler ; 5 Bus Fault Handler\r
+ DCD UsageFault_Handler ; 6 Usage Fault Handler\r
+ DCD Sign_Value ; 7 Reserved\r
+ DCD 0 ; 8 Reserved\r
+ DCD 0 ; 9 Reserved\r
+ DCD 0 ; 10 Reserved\r
+ DCD SVC_Handler ; 11 SVCall Handler \r
+ DCD DebugMon_Handler ; 12 Debug Monitor Handler\r
+ DCD 0 ; 13 Reserved\r
+ DCD PendSV_Handler ; 14 PendSV Handler \r
+ DCD SysTick_Handler ; 15 SysTick Handler \r
+\r
+ ; External Interrupts \r
+ DCD DAC_IRQHandler ; 16 D/A Converter\r
+ DCD M0_IRQHandler ; 17 M0 \r
+ DCD DMA_IRQHandler ; 18 General Purpose DMA\r
+ DCD 0 ; 19 Reserved\r
+ DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon\r
+ DCD ETH_IRQHandler ; 21 Ethernet\r
+ DCD SDIO_IRQHandler ; 22 SD/MMC\r
+ DCD LCD_IRQHandler ; 23 LCD\r
+ DCD USB0_IRQHandler ; 24 USB0\r
+ DCD USB1_IRQHandler ; 25 USB1\r
+ DCD SCT_IRQHandler ; 26 State Configurable Timer\r
+ DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer\r
+ DCD TIMER0_IRQHandler ; 28 Timer0\r
+ DCD TIMER1_IRQHandler ; 29 Timer1\r
+ DCD TIMER2_IRQHandler ; 30 Timer2\r
+ DCD TIMER3_IRQHandler ; 31 Timer3\r
+ DCD MCPWM_IRQHandler ; 32 Motor Control PWM\r
+ DCD ADC0_IRQHandler ; 33 A/D Converter 0\r
+ DCD I2C0_IRQHandler ; 34 I2C0\r
+ DCD I2C1_IRQHandler ; 35 I2C1\r
+ DCD SPI_IRQHandler ; 36 SPI\r
+ DCD ADC1_IRQHandler ; 37 A/D Converter 1\r
+ DCD SSP0_IRQHandler ; 38 SSP0\r
+ DCD SSP1_IRQHandler ; 39 SSP1\r
+ DCD UART0_IRQHandler ; 40 UART0\r
+ DCD UART1_IRQHandler ; 41 UART1\r
+ DCD UART2_IRQHandler ; 42 UART2\r
+ DCD UART3_IRQHandler ; 43 UART3\r
+ DCD I2S0_IRQHandler ; 44 I2S0\r
+ DCD I2S1_IRQHandler ; 45 I2S1\r
+ DCD SPIFI_IRQHandler ; 46 SPI Flash Interface\r
+ DCD SGPIO_IRQHandler ; 47 SGPIO\r
+ DCD GPIO0_IRQHandler ; 48 GPIO0\r
+ DCD GPIO1_IRQHandler ; 49 GPIO1\r
+ DCD GPIO2_IRQHandler ; 50 GPIO2\r
+ DCD GPIO3_IRQHandler ; 51 GPIO3\r
+ DCD GPIO4_IRQHandler ; 52 GPIO4\r
+ DCD GPIO5_IRQHandler ; 53 GPIO5\r
+ DCD GPIO6_IRQHandler ; 54 GPIO6\r
+ DCD GPIO7_IRQHandler ; 55 GPIO7\r
+ DCD GINT0_IRQHandler ; 56 GINT0\r
+ DCD GINT1_IRQHandler ; 57 GINT1\r
+ DCD EVRT_IRQHandler ; 58 Event Router\r
+ DCD CAN1_IRQHandler ; 59 C_CAN1\r
+ DCD 0 ; 60 Reserved\r
+ DCD VADC_IRQHandler ; 61 VADC\r
+ DCD ATIMER_IRQHandler ; 62 ATIMER\r
+ DCD RTC_IRQHandler ; 63 RTC\r
+ DCD 0 ; 64 Reserved\r
+ DCD WDT_IRQHandler ; 65 WDT\r
+ DCD 0 ; 66 Reserved\r
+ DCD CAN0_IRQHandler ; 67 C_CAN0\r
+ DCD QEI_IRQHandler ; 68 QEI\r
+\r
+__endVectors\r
+ \r
+ IF :LNOT::DEF:NO_CRP\r
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY\r
+CRP_Key DCD 0xFFFFFFFF\r
+ ENDIF\r
+\r
+ AREA |.text|, CODE, READONLY\r
+\r
+; Reset Handler\r
+\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT __main\r
+\r
+ IF :DEF:EXT_FLASH\r
+\r
+ ; Extend the address bus, as the bootloader configured only [A13:0]\r
+ ; *(uint32_t*)(0x40086320) = 0x000000F1; \r
+ ; P6_8: A14 (function 1) \r
+ LDR R0, =0x40086320\r
+ LDR R1, =0x000000F1\r
+ STR R1, [R0,#0]\r
+ ; *(uint32_t*)(0x4008631C) = 0x000000F1; \r
+ ; P6_7: A15 (function 1) \r
+ LDR R0, =0x4008631C\r
+ LDR R1, =0x000000F1\r
+ STR R1, [R0,#0] \r
+ ; *(uint32_t*)(0x400866C0) = 0x000000F2; \r
+ ; PD_16: A16 (function 2) \r
+ LDR R0, =0x400866C0\r
+ LDR R1, =0x000000F2\r
+ STR R1, [R0,#0] \r
+ ; *(uint32_t*)(0x400866BC) = 0x000000F2; \r
+ ; PD_15: A17 (function 2) \r
+ LDR R0, =0x400866BC\r
+ LDR R1, =0x000000F2\r
+ STR R1, [R0,#0] \r
+ ; *(uint32_t*)(0x40086700) = 0x000000F3; \r
+ ; PE_0: A18 (function 3) \r
+ LDR R0, =0x40086700\r
+ LDR R1, =0x000000F3\r
+ STR R1, [R0,#0] \r
+ ; *(uint32_t*)(0x40086704) = 0x000000F3; \r
+ ; PE_1: A19 (function 3) \r
+ LDR R0, =0x40086704\r
+ LDR R1, =0x000000F3\r
+ STR R1, [R0,#0] \r
+ ; *(uint32_t*)(0x40086708) = 0x000000F3; \r
+ ; PE_2: A20 (function 3) \r
+ LDR R0, =0x40086708\r
+ LDR R1, =0x000000F3\r
+ STR R1, [R0,#0] \r
+ ; *(uint32_t*)(0x4008670C) = 0x000000F3; \r
+ ; PE_3: A21 (function 3) \r
+ LDR R0, =0x4008670C\r
+ LDR R1, =0x000000F3\r
+ STR R1, [R0,#0] \r
+ ; *(uint32_t*)(0x40086710) = 0x000000F3; \r
+ ; PE_4: A22 (function 3) \r
+ LDR R0, =0x40086710\r
+ LDR R1, =0x000000F3\r
+ STR R1, [R0,#0]\r
+\r
+ ENDIF\r
+\r
+ LDR R0, =__main\r
+ BX R0\r
+ ENDP\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified) \r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+MemManage_Handler\\r
+ PROC\r
+ EXPORT MemManage_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+BusFault_Handler\\r
+ PROC\r
+ EXPORT BusFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+UsageFault_Handler\\r
+ PROC\r
+ EXPORT UsageFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+; FreeRTOS handler\r
+vPortSVCHandler\\r
+ PROC\r
+ EXPORT vPortSVCHandler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+SVC_Handler PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+DebugMon_Handler\\r
+ PROC\r
+ EXPORT DebugMon_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+; FreeRTOS handler\r
+xPortPendSVHandler\\r
+ PROC\r
+ EXPORT xPortPendSVHandler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+PendSV_Handler PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+; FreeRTOS handler\r
+xPortSysTickHandler\\r
+ PROC\r
+ EXPORT xPortSysTickHandler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+SysTick_Handler PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+Default_Handler PROC\r
+\r
+ EXPORT DAC_IRQHandler [WEAK]\r
+ EXPORT M0_IRQHandler [WEAK]\r
+ EXPORT DMA_IRQHandler [WEAK]\r
+ EXPORT FLASH_EEPROM_IRQHandler [WEAK]\r
+ EXPORT ETH_IRQHandler [WEAK]\r
+ EXPORT SDIO_IRQHandler [WEAK]\r
+ EXPORT LCD_IRQHandler [WEAK]\r
+ EXPORT USB0_IRQHandler [WEAK]\r
+ EXPORT USB1_IRQHandler [WEAK]\r
+ EXPORT SCT_IRQHandler [WEAK]\r
+ EXPORT RIT_IRQHandler [WEAK]\r
+ EXPORT TIMER0_IRQHandler [WEAK]\r
+ EXPORT TIMER1_IRQHandler [WEAK]\r
+ EXPORT TIMER2_IRQHandler [WEAK]\r
+ EXPORT TIMER3_IRQHandler [WEAK]\r
+ EXPORT MCPWM_IRQHandler [WEAK]\r
+ EXPORT ADC0_IRQHandler [WEAK]\r
+ EXPORT I2C0_IRQHandler [WEAK]\r
+ EXPORT I2C1_IRQHandler [WEAK]\r
+ EXPORT SPI_IRQHandler [WEAK]\r
+ EXPORT ADC1_IRQHandler [WEAK]\r
+ EXPORT SSP0_IRQHandler [WEAK]\r
+ EXPORT SSP1_IRQHandler [WEAK]\r
+ EXPORT UART0_IRQHandler [WEAK]\r
+ EXPORT UART1_IRQHandler [WEAK]\r
+ EXPORT UART2_IRQHandler [WEAK]\r
+ EXPORT UART3_IRQHandler [WEAK]\r
+ EXPORT I2S0_IRQHandler [WEAK]\r
+ EXPORT I2S1_IRQHandler [WEAK]\r
+ EXPORT SPIFI_IRQHandler [WEAK]\r
+ EXPORT SGPIO_IRQHandler [WEAK]\r
+ EXPORT GPIO0_IRQHandler [WEAK]\r
+ EXPORT GPIO1_IRQHandler [WEAK]\r
+ EXPORT GPIO2_IRQHandler [WEAK]\r
+ EXPORT GPIO3_IRQHandler [WEAK]\r
+ EXPORT GPIO4_IRQHandler [WEAK]\r
+ EXPORT GPIO5_IRQHandler [WEAK]\r
+ EXPORT GPIO6_IRQHandler [WEAK]\r
+ EXPORT GPIO7_IRQHandler [WEAK]\r
+ EXPORT GINT0_IRQHandler [WEAK]\r
+ EXPORT GINT1_IRQHandler [WEAK]\r
+ EXPORT EVRT_IRQHandler [WEAK]\r
+ EXPORT CAN1_IRQHandler [WEAK]\r
+ EXPORT VADC_IRQHandler [WEAK]\r
+ EXPORT ATIMER_IRQHandler [WEAK]\r
+ EXPORT RTC_IRQHandler [WEAK]\r
+ EXPORT WDT_IRQHandler [WEAK]\r
+ EXPORT CAN0_IRQHandler [WEAK]\r
+ EXPORT QEI_IRQHandler [WEAK]\r
+\r
+\r
+\r
+\r
+DAC_IRQHandler\r
+M0_IRQHandler\r
+DMA_IRQHandler\r
+FLASH_EEPROM_IRQHandler\r
+ETH_IRQHandler\r
+SDIO_IRQHandler\r
+LCD_IRQHandler\r
+USB0_IRQHandler\r
+USB1_IRQHandler\r
+SCT_IRQHandler\r
+RIT_IRQHandler\r
+TIMER0_IRQHandler\r
+TIMER1_IRQHandler\r
+TIMER2_IRQHandler\r
+TIMER3_IRQHandler\r
+MCPWM_IRQHandler\r
+ADC0_IRQHandler\r
+I2C0_IRQHandler\r
+I2C1_IRQHandler\r
+SPI_IRQHandler\r
+ADC1_IRQHandler\r
+SSP0_IRQHandler\r
+SSP1_IRQHandler\r
+UART0_IRQHandler\r
+UART1_IRQHandler\r
+UART2_IRQHandler\r
+UART3_IRQHandler\r
+I2S0_IRQHandler\r
+I2S1_IRQHandler\r
+SPIFI_IRQHandler\r
+SGPIO_IRQHandler\r
+GPIO0_IRQHandler\r
+GPIO1_IRQHandler\r
+GPIO2_IRQHandler\r
+GPIO3_IRQHandler\r
+GPIO4_IRQHandler\r
+GPIO5_IRQHandler\r
+GPIO6_IRQHandler\r
+GPIO7_IRQHandler\r
+GINT0_IRQHandler\r
+GINT1_IRQHandler\r
+EVRT_IRQHandler\r
+CAN1_IRQHandler\r
+VADC_IRQHandler\r
+ATIMER_IRQHandler\r
+RTC_IRQHandler\r
+WDT_IRQHandler\r
+CAN0_IRQHandler\r
+QEI_IRQHandler\r
+\r
+ B .\r
+\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+; User Initial Stack & Heap\r
+\r
+ IF :DEF:__MICROLIB\r
+ \r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+ \r
+ ELSE\r
+ \r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+ END\r
--- /dev/null
+ \r
+/****************************************************************************************************//**\r
+ * @file LPC43xx.h\r
+ *\r
+ * @status EXPERIMENTAL\r
+ *\r
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for\r
+ * default LPC43xx Device Series\r
+ *\r
+ * @version V0.10\r
+ * @date 10. June 2011\r
+ *\r
+ * @note Generated with SFDGen V2.6 Build 4f on Friday, 10.06.2011 14:32:01\r
+ *\r
+ *\r
+ *******************************************************************************************************/\r
+\r
+\r
+\r
+/** @addtogroup (null)\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup LPC43xx\r
+ * @{\r
+ */\r
+\r
+#ifndef __LPC43XX_H__\r
+#define __LPC43XX_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #pragma anon_unions\r
+#endif\r
+\r
+ /* Interrupt Number Definition */\r
+\r
+#if defined CORE_M4\r
+\r
+typedef enum {\r
+// ------------------------- Cortex-M4 Processor Exceptions Numbers -----------------------------\r
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */\r
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */\r
+ BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */\r
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */\r
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */\r
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */\r
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */\r
+// --------------------------- LPC43xx Specific Interrupt Numbers -------------------------------\r
+ DAC_IRQn = 0, /*!< 0 DAC */\r
+ M0_IRQn = 1, /*!< 1 M0 */\r
+ DMA_IRQn = 2, /*!< 2 DMA */\r
+ RESERVED0_IRQn = 3, \r
+ RESERVED1_IRQn = 4,\r
+ ETH_IRQn = 5, /*!< 5 ETHERNET */\r
+ SDIO_IRQn = 6, /*!< 6 SDIO */\r
+ LCD_IRQn = 7, /*!< 7 LCD */\r
+ USB0_IRQn = 8, /*!< 8 USB0 */\r
+ USB1_IRQn = 9, /*!< 9 USB1 */\r
+ SCT_IRQn = 10, /*!< 10 SCT */\r
+ RITIMER_IRQn = 11, /*!< 11 RITIMER */\r
+ TIMER0_IRQn = 12, /*!< 12 TIMER0 */\r
+ TIMER1_IRQn = 13, /*!< 13 TIMER1_INT */\r
+ TIMER2_IRQn = 14, /*!< 14 TIMER2_INT */\r
+ TIMER3_IRQn = 15, /*!< 15 TIMER3_INT */\r
+ MCPWM_IRQn = 16, /*!< 16 MCPWM */\r
+ ADC0_IRQn = 17, /*!< 17 ADC0 */\r
+ I2C0_IRQn = 18, /*!< 18 I2C0 */\r
+ I2C1_IRQn = 19, /*!< 19 I2C1 */\r
+ SPI_IRQn = 20, /*!< 20 SPI */\r
+ ADC1_IRQn = 21, /*!< 21 ADC1 */\r
+ SSP0_IRQn = 22, /*!< 22 SSP0 */\r
+ SSP1_IRQn = 23, /*!< 23 SSP1 */\r
+ USART0_IRQn = 24, /*!< 24 USART0 */\r
+ UART1_IRQn = 25, /*!< 25 UART1 */\r
+ USART2_IRQn = 26, /*!< 26 USART2 */\r
+ USART3_IRQn = 27, /*!< 27 USART3 */\r
+ I2S0_IRQn = 28, /*!< 28 I2S0 */\r
+ I2S1_IRQn = 29, /*!< 29 I2S1 */\r
+ SPIFI_IRQn = 30, /*!< 30 SPIFI */\r
+ SGPIO_IRQn = 31, /*!< 31 SGPIO */\r
+ PIN_INT0_IRQn = 32, /*!< 32 PIN_INT0 */\r
+ PIN_INT1_IRQn = 33, /*!< 33 PIN_INT1 */\r
+ PIN_INT2_IRQn = 34, /*!< 34 PIN_INT2 */\r
+ PIN_INT3_IRQn = 35, /*!< 35 PIN_INT3 */\r
+ PIN_INT4_IRQn = 36, /*!< 36 PIN_INT4 */\r
+ PIN_INT5_IRQn = 37, /*!< 37 PIN_INT5 */\r
+ PIN_INT6_IRQn = 38, /*!< 38 PIN_INT6 */\r
+ PIN_INT7_IRQn = 39, /*!< 39 PIN_INT7 */\r
+ GINT0_IRQn = 40, /*!< 40 GINT0 */\r
+ GINT1_IRQn = 41, /*!< 41 GINT1 */\r
+ EVENTROUTER_INT_IRQn = 42, /*!< 42 EVENTROUTER_INT */\r
+ C_CAN1_IRQn = 43, /*!< 43 C_CAN1 */\r
+ RESERVED3_IRQn = 44,\r
+ VADC_IRQn = 45, /*!< 45 VADC */\r
+ ATIMER_IRQn = 46, /*!< 46 ATIMER */\r
+ RTC_IRQn = 47, /*!< 47 RTC */\r
+ RESERVED4_IRQn = 48,\r
+ WWDT_IRQn = 49, /*!< 49 WDT */\r
+ RESERVED5_IRQn = 50, \r
+ C_CAN0_IRQn = 51, /*!< 51 C_CAN0 */\r
+ QEI_IRQn = 52, /*!< 52 QEI */\r
+} IRQn_Type;\r
+\r
+#endif\r
+\r
+#if defined CORE_M0\r
+#include "LPC43xx_M0.h"\r
+#endif\r
+\r
+ /* Event Router Input (ERI) Number Definitions */\r
+typedef enum {\r
+ WAKEUP0_ERIn = 0,\r
+ WAKEUP1_ERIn = 1,\r
+ WAKEUP2_ERIn = 2,\r
+ WAKEUP3_ERIn = 3,\r
+ ATIMER_ERIn = 4,\r
+ RTC_ERIn = 5,\r
+ BOD1_ERIn = 6, /* Bod trip 1 */\r
+ WWDT_ERIn = 7,\r
+ ETH_ERIn = 8,\r
+ USB0_ERIn = 9,\r
+ USB1_ERIn = 10,\r
+ SDIO_ERIn = 11,\r
+ CAN_ERIn = 12, /* CAN0/1 or'ed */\r
+ TIM2_ERIn = 13,\r
+ TIM6_ERIn = 14,\r
+ QEI_ERIn = 15,\r
+ TIM14_ERIn = 16,\r
+ RESERVED1_ERI = 17, \r
+ M4_ERIn = 18, /* M4 */ \r
+ RESET_ERIn = 19,\r
+ BOD2_ERIn = 20, /* Bod trip 2 */\r
+ PMC_ERIn = 21, /* Vd1_rst_req */\r
+ REG_VD1_OK_ERIn = 22,\r
+ REG_VD2_OK_ERIn = 23,\r
+ REG_VD3_OK_ERIn = 24,\r
+ REG_VD8_OK_ERIn = 25\r
+}ERIn_Type;\r
+\r
+\r
+/** @addtogroup Configuration_of_CMSIS\r
+ * @{\r
+ */\r
+\r
+/* Processor and Core Peripheral Section */ \r
+/* Configuration of the Cortex-M4 Processor and Core Peripherals */\r
+\r
+#if defined CORE_M0\r
+#define __CM0_REV 0x0101 /*!< Cortex-M0 Core Revision */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+#endif\r
+\r
+#ifdef CORE_M4\r
+#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+#endif\r
+\r
+/** @} */ /* End of group Configuration_of_CMSIS */\r
+\r
+#ifdef CORE_M0\r
+#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */\r
+#include "system_LPC43xx_M0.h" /*!< LPC43xx System */\r
+#endif\r
+\r
+#ifdef CORE_M4\r
+#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */\r
+#include "system_LPC43xx.h" /*!< LPC43xx System */\r
+#endif\r
+\r
+/** @addtogroup Device_Peripheral_Registers\r
+ * @{\r
+ */\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- SCT -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)\r
+ */\r
+\r
+#define CONFIG_SCT_nEV (16) /* Number of events */\r
+#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */\r
+#define CONFIG_SCT_nOU (16) /* Number of outputs */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CONFIG; /* 0x000 Configuration Register */\r
+ union {\r
+ __IO uint32_t CTRL_U; /* 0x004 Control Register */\r
+ struct {\r
+ __IO uint16_t CTRL_L; /* 0x004 low control register */\r
+ __IO uint16_t CTRL_H; /* 0x006 high control register */\r
+ };\r
+ };\r
+ __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */\r
+ __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */\r
+ __IO uint16_t HALT_L; /* 0x00C halt register for counter L */\r
+ __IO uint16_t HALT_H; /* 0x00E halt register for counter H */\r
+ __IO uint16_t STOP_L; /* 0x010 stop register for counter L */\r
+ __IO uint16_t STOP_H; /* 0x012 stop register for counter H */\r
+ __IO uint16_t START_L; /* 0x014 start register for counter L */\r
+ __IO uint16_t START_H; /* 0x016 start register for counter H */\r
+ uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */\r
+ union {\r
+ __IO uint32_t COUNT_U; /* 0x040 counter register */\r
+ struct {\r
+ __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */\r
+ __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */\r
+ };\r
+ };\r
+ __IO uint16_t STATE_L; /* 0x044 state register for counter L */\r
+ __IO uint16_t STATE_H; /* 0x046 state register for counter H */\r
+ __I uint32_t INPUT; /* 0x048 input register */\r
+ __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */\r
+ __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */\r
+ __IO uint32_t OUTPUT; /* 0x050 output register */\r
+ __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */\r
+ __IO uint32_t RES; /* 0x058 conflict resolution register */\r
+ __IO uint32_t DMA0REQUEST; /* 0x05C DMA0 Request Register */\r
+ __IO uint32_t DMA1REQUEST; /* 0x060 DMA1 Request Register */\r
+ uint32_t RESERVED2[35]; /* 0x064-0x0EC reserved */\r
+ __IO uint32_t EVEN; /* 0x0F0 event enable register */\r
+ __IO uint32_t EVFLAG; /* 0x0F4 event flag register */\r
+ __IO uint32_t CONEN; /* 0x0F8 conflict enable register */\r
+ __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */\r
+\r
+ union {\r
+ __IO union { /* 0x100-... Match / Capture value */\r
+ uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */\r
+ struct {\r
+ uint16_t L; /* SCTMATCH[i].L Access to L value */\r
+ uint16_t H; /* SCTMATCH[i].H Access to H value */\r
+ };\r
+ } MATCH[CONFIG_SCT_nRG];\r
+ __I union {\r
+ uint32_t U; /* SCTCAP[i].U Unified 32-bit register */\r
+ struct {\r
+ uint16_t L; /* SCTCAP[i].L Access to H value */\r
+ uint16_t H; /* SCTCAP[i].H Access to H value */\r
+ };\r
+ } CAP[CONFIG_SCT_nRG];\r
+ };\r
+\r
+ uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */\r
+\r
+ union {\r
+ __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */\r
+ __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */\r
+ };\r
+ uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */\r
+ union {\r
+ __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */\r
+ __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */\r
+ };\r
+ uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */\r
+\r
+ union {\r
+ __IO union { /* 0x200-... Match Reload / Capture Control value */\r
+ uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */\r
+ struct {\r
+ uint16_t L; /* SCTMATCHREL[i].L Access to L value */\r
+ uint16_t H; /* SCTMATCHREL[i].H Access to H value */\r
+ };\r
+ } MATCHREL[CONFIG_SCT_nRG];\r
+ __IO union {\r
+ uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */\r
+ struct {\r
+ uint16_t L; /* SCTCAPCTRL[i].L Access to H value */\r
+ uint16_t H; /* SCTCAPCTRL[i].H Access to H value */\r
+ };\r
+ } CAPCTRL[CONFIG_SCT_nRG];\r
+ };\r
+\r
+ uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */\r
+\r
+ union {\r
+ __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */\r
+ __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */\r
+ };\r
+ uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */\r
+ union {\r
+ __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */\r
+ __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */\r
+ };\r
+ uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */\r
+\r
+ __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/\r
+ uint32_t STATE; /* Event State Register */\r
+ uint32_t CTRL; /* Event Control Register */\r
+ } EVENT[CONFIG_SCT_nEV];\r
+\r
+ uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */\r
+\r
+ __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */\r
+ uint32_t SET; /* Output n Set Register */\r
+ uint32_t CLR; /* Output n Clear Register */\r
+ } OUT[CONFIG_SCT_nOU];\r
+\r
+ uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */\r
+\r
+ __I uint32_t MODULECONTENT; /* 0x7FC Module Content */\r
+\r
+} LPC_SCT_Type;\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- GPDMA -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx General Purpose DMA (GPDMA) controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (GPDMA)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40002000) GPDMA Structure */\r
+ __I uint32_t INTSTAT; /*!< (@ 0x40002000) DMA Interrupt Status Register */\r
+ __I uint32_t INTTCSTAT; /*!< (@ 0x40002004) DMA Interrupt Terminal Count Request Status Register */\r
+ __O uint32_t INTTCCLEAR; /*!< (@ 0x40002008) DMA Interrupt Terminal Count Request Clear Register */\r
+ __I uint32_t INTERRSTAT; /*!< (@ 0x4000200C) DMA Interrupt Error Status Register */\r
+ __O uint32_t INTERRCLR; /*!< (@ 0x40002010) DMA Interrupt Error Clear Register */\r
+ __I uint32_t RAWINTTCSTAT; /*!< (@ 0x40002014) DMA Raw Interrupt Terminal Count Status Register */\r
+ __I uint32_t RAWINTERRSTAT; /*!< (@ 0x40002018) DMA Raw Error Interrupt Status Register */\r
+ __I uint32_t ENBLDCHNS; /*!< (@ 0x4000201C) DMA Enabled Channel Register */\r
+ __IO uint32_t SOFTBREQ; /*!< (@ 0x40002020) DMA Software Burst Request Register */\r
+ __IO uint32_t SOFTSREQ; /*!< (@ 0x40002024) DMA Software Single Request Register */\r
+ __IO uint32_t SOFTLBREQ; /*!< (@ 0x40002028) DMA Software Last Burst Request Register */\r
+ __IO uint32_t SOFTLSREQ; /*!< (@ 0x4000202C) DMA Software Last Single Request Register */\r
+ __IO uint32_t CONFIG; /*!< (@ 0x40002030) DMA Configuration Register */\r
+ __IO uint32_t SYNC; /*!< (@ 0x40002034) DMA Synchronization Register */\r
+ __I uint32_t RESERVED0[50];\r
+ __IO uint32_t C0SRCADDR; /*!< (@ 0x40002100) DMA Channel Source Address Register */\r
+ __IO uint32_t C0DESTADDR; /*!< (@ 0x40002104) DMA Channel Destination Address Register */\r
+ __IO uint32_t C0LLI; /*!< (@ 0x40002108) DMA Channel Linked List Item Register */\r
+ __IO uint32_t C0CONTROL; /*!< (@ 0x4000210C) DMA Channel Control Register */\r
+ __IO uint32_t C0CONFIG; /*!< (@ 0x40002110) DMA Channel Configuration Register */\r
+ __I uint32_t RESERVED1[3];\r
+ __IO uint32_t C1SRCADDR; /*!< (@ 0x40002120) DMA Channel Source Address Register */\r
+ __IO uint32_t C1DESTADDR; /*!< (@ 0x40002124) DMA Channel Destination Address Register */\r
+ __IO uint32_t C1LLI; /*!< (@ 0x40002128) DMA Channel Linked List Item Register */\r
+ __IO uint32_t C1CONTROL; /*!< (@ 0x4000212C) DMA Channel Control Register */\r
+ __IO uint32_t C1CONFIG; /*!< (@ 0x40002130) DMA Channel Configuration Register */\r
+ __I uint32_t RESERVED2[3];\r
+ __IO uint32_t C2SRCADDR; /*!< (@ 0x40002140) DMA Channel Source Address Register */\r
+ __IO uint32_t C2DESTADDR; /*!< (@ 0x40002144) DMA Channel Destination Address Register */\r
+ __IO uint32_t C2LLI; /*!< (@ 0x40002148) DMA Channel Linked List Item Register */\r
+ __IO uint32_t C2CONTROL; /*!< (@ 0x4000214C) DMA Channel Control Register */\r
+ __IO uint32_t C2CONFIG; /*!< (@ 0x40002150) DMA Channel Configuration Register */\r
+ __I uint32_t RESERVED3[3];\r
+ __IO uint32_t C3SRCADDR; /*!< (@ 0x40002160) DMA Channel Source Address Register */\r
+ __IO uint32_t C3DESTADDR; /*!< (@ 0x40002164) DMA Channel Destination Address Register */\r
+ __IO uint32_t C3LLI; /*!< (@ 0x40002168) DMA Channel Linked List Item Register */\r
+ __IO uint32_t C3CONTROL; /*!< (@ 0x4000216C) DMA Channel Control Register */\r
+ __IO uint32_t C3CONFIG; /*!< (@ 0x40002170) DMA Channel Configuration Register */\r
+ __I uint32_t RESERVED4[3];\r
+ __IO uint32_t C4SRCADDR; /*!< (@ 0x40002180) DMA Channel Source Address Register */\r
+ __IO uint32_t C4DESTADDR; /*!< (@ 0x40002184) DMA Channel Destination Address Register */\r
+ __IO uint32_t C4LLI; /*!< (@ 0x40002188) DMA Channel Linked List Item Register */\r
+ __IO uint32_t C4CONTROL; /*!< (@ 0x4000218C) DMA Channel Control Register */\r
+ __IO uint32_t C4CONFIG; /*!< (@ 0x40002190) DMA Channel Configuration Register */\r
+ __I uint32_t RESERVED5[3];\r
+ __IO uint32_t C5SRCADDR; /*!< (@ 0x400021A0) DMA Channel Source Address Register */\r
+ __IO uint32_t C5DESTADDR; /*!< (@ 0x400021A4) DMA Channel Destination Address Register */\r
+ __IO uint32_t C5LLI; /*!< (@ 0x400021A8) DMA Channel Linked List Item Register */\r
+ __IO uint32_t C5CONTROL; /*!< (@ 0x400021AC) DMA Channel Control Register */\r
+ __IO uint32_t C5CONFIG; /*!< (@ 0x400021B0) DMA Channel Configuration Register */\r
+ __I uint32_t RESERVED6[3];\r
+ __IO uint32_t C6SRCADDR; /*!< (@ 0x400021C0) DMA Channel Source Address Register */\r
+ __IO uint32_t C6DESTADDR; /*!< (@ 0x400021C4) DMA Channel Destination Address Register */\r
+ __IO uint32_t C6LLI; /*!< (@ 0x400021C8) DMA Channel Linked List Item Register */\r
+ __IO uint32_t C6CONTROL; /*!< (@ 0x400021CC) DMA Channel Control Register */\r
+ __IO uint32_t C6CONFIG; /*!< (@ 0x400021D0) DMA Channel Configuration Register */\r
+ __I uint32_t RESERVED7[3];\r
+ __IO uint32_t C7SRCADDR; /*!< (@ 0x400021E0) DMA Channel Source Address Register */\r
+ __IO uint32_t C7DESTADDR; /*!< (@ 0x400021E4) DMA Channel Destination Address Register */\r
+ __IO uint32_t C7LLI; /*!< (@ 0x400021E8) DMA Channel Linked List Item Register */\r
+ __IO uint32_t C7CONTROL; /*!< (@ 0x400021EC) DMA Channel Control Register */\r
+ __IO uint32_t C7CONFIG; /*!< (@ 0x400021F0) DMA Channel Configuration Register */\r
+} LPC_GPDMA_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- SPIFI -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx SPI Flash Interface (SPIFI) Modification date=1/19/2011 Major revision=0 Minor revision=7 (SPIFI)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40003000) SPIFI Structure */\r
+ __IO uint32_t CTRL; /*!< (@ 0x40003000) SPIFI control register */\r
+ __IO uint32_t CMD; /*!< (@ 0x40003004) SPIFI command register */\r
+ __IO uint32_t ADDR; /*!< (@ 0x40003008) SPIFI address register */\r
+ __IO uint32_t DATINTM; /*!< (@ 0x4000300C) SPIFI intermediate data register */\r
+ __IO uint32_t ADDRINTM; /*!< (@ 0x40003010) SPIFI address and intermediate data register */\r
+ __IO uint32_t DAT; /*!< (@ 0x40003014) SPIFI data register */\r
+ __IO uint32_t MEMCMD; /*!< (@ 0x40003018) SPIFI memory command register */\r
+ __I uint32_t STAT; /*!< (@ 0x4000301C) SPIFI status register */\r
+} LPC_SPIFI_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- SDMMC -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC43xx SD/MMC Modification date=n/a Major revision=n/a Minor revision=n/a (SDMMC)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40004000) SDMMC Structure */\r
+ __IO uint32_t CTRL; /*!< (@ 0x40004000) Control Register */\r
+ __IO uint32_t PWREN; /*!< (@ 0x40004004) Power Enable Register */\r
+ __IO uint32_t CLKDIV; /*!< (@ 0x40004008) Clock Divider Register */\r
+ __IO uint32_t CLKSRC; /*!< (@ 0x4000400C) SD Clock Source Register */\r
+ __IO uint32_t CLKENA; /*!< (@ 0x40004010) Clock Enable Register */\r
+ __IO uint32_t TMOUT; /*!< (@ 0x40004014) Timeout Register */\r
+ __IO uint32_t CTYPE; /*!< (@ 0x40004018) Card Type Register */\r
+ __IO uint32_t BLKSIZ; /*!< (@ 0x4000401C) Block Size Register */\r
+ __IO uint32_t BYTCNT; /*!< (@ 0x40004020) Byte Count Register */\r
+ __IO uint32_t INTMASK; /*!< (@ 0x40004024) Interrupt Mask Register */\r
+ __IO uint32_t CMDARG; /*!< (@ 0x40004028) Command Argument Register */\r
+ __IO uint32_t CMD; /*!< (@ 0x4000402C) Command Register */\r
+ __I uint32_t RESP0; /*!< (@ 0x40004030) Response Register 0 */\r
+ __I uint32_t RESP1; /*!< (@ 0x40004034) Response Register 1 */\r
+ __I uint32_t RESP2; /*!< (@ 0x40004038) Response Register 2 */\r
+ __I uint32_t RESP3; /*!< (@ 0x4000403C) Response Register 3 */\r
+ __I uint32_t MINTSTS; /*!< (@ 0x40004040) Masked Interrupt Status Register */\r
+ __IO uint32_t RINTSTS; /*!< (@ 0x40004044) Raw Interrupt Status Register */\r
+ __I uint32_t STATUS; /*!< (@ 0x40004048) Status Register */\r
+ __IO uint32_t FIFOTH; /*!< (@ 0x4000404C) FIFO Threshold Watermark Register */\r
+ __I uint32_t CDETECT; /*!< (@ 0x40004050) Card Detect Register */\r
+ __I uint32_t WRTPRT; /*!< (@ 0x40004054) Write Protect Register */\r
+ __IO uint32_t GPIO; /*!< (@ 0x40004058) General Purpose Input/Output Register */\r
+ __I uint32_t TCBCNT; /*!< (@ 0x4000405C) Transferred CIU Card Byte Count Register */\r
+ __I uint32_t TBBCNT; /*!< (@ 0x40004060) Transferred Host to BIU-FIFO Byte Count Register */\r
+ __IO uint32_t DEBNCE; /*!< (@ 0x40004064) Debounce Count Register */\r
+ __IO uint32_t USRID; /*!< (@ 0x40004068) User ID Register */\r
+ __I uint32_t VERID; /*!< (@ 0x4000406C) Version ID Register */\r
+ __I uint32_t RESERVED0;\r
+ __IO uint32_t UHS_REG; /*!< (@ 0x40004074) UHS-1 Register */\r
+ __IO uint32_t RST_N; /*!< (@ 0x40004078) Hardware Reset */\r
+ __I uint32_t RESERVED1;\r
+ __IO uint32_t BMOD; /*!< (@ 0x40004080) Bus Mode Register */\r
+ __O uint32_t PLDMND; /*!< (@ 0x40004084) Poll Demand Register */\r
+ __IO uint32_t DBADDR; /*!< (@ 0x40004088) Descriptor List Base Address Register */\r
+ __IO uint32_t IDSTS; /*!< (@ 0x4000408C) Internal DMAC Status Register */\r
+ __IO uint32_t IDINTEN; /*!< (@ 0x40004090) Internal DMAC Interrupt Enable Register */\r
+ __I uint32_t DSCADDR; /*!< (@ 0x40004094) Current Host Descriptor Address Register */\r
+ __I uint32_t BUFADDR; /*!< (@ 0x40004098) Current Buffer Descriptor Address Register */\r
+} LPC_SDMMC_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- EMC -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx External Memory Controller (EMC) Modification date=1/19/2011 Major revision=0 Minor revision=7 (EMC)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40005000) EMC Structure */\r
+ __IO uint32_t CONTROL; /*!< (@ 0x40005000) Controls operation of the memory controller. */\r
+ __I uint32_t STATUS; /*!< (@ 0x40005004) Provides EMC status information. */\r
+ __IO uint32_t CONFIG; /*!< (@ 0x40005008) Configures operation of the memory controller. */\r
+ __I uint32_t RESERVED0[5];\r
+ __IO uint32_t DYNAMICCONTROL; /*!< (@ 0x40005020) Controls dynamic memory operation. */\r
+ __IO uint32_t DYNAMICREFRESH; /*!< (@ 0x40005024) Configures dynamic memory refresh operation. */\r
+ __IO uint32_t DYNAMICREADCONFIG; /*!< (@ 0x40005028) Configures the dynamic memory read strategy. */\r
+ __I uint32_t RESERVED1;\r
+ __IO uint32_t DYNAMICRP; /*!< (@ 0x40005030) Selects the precharge command period. */\r
+ __IO uint32_t DYNAMICRAS; /*!< (@ 0x40005034) Selects the active to precharge command period. */\r
+ __IO uint32_t DYNAMICSREX; /*!< (@ 0x40005038) Selects the self-refresh exit time. */\r
+ __IO uint32_t DYNAMICAPR; /*!< (@ 0x4000503C) Selects the last-data-out to active command time. */\r
+ __IO uint32_t DYNAMICDAL; /*!< (@ 0x40005040) Selects the data-in to active command time. */\r
+ __IO uint32_t DYNAMICWR; /*!< (@ 0x40005044) Selects the write recovery time. */\r
+ __IO uint32_t DYNAMICRC; /*!< (@ 0x40005048) Selects the active to active command period. */\r
+ __IO uint32_t DYNAMICRFC; /*!< (@ 0x4000504C) Selects the auto-refresh period. */\r
+ __IO uint32_t DYNAMICXSR; /*!< (@ 0x40005050) Selects the exit self-refresh to active command time. */\r
+ __IO uint32_t DYNAMICRRD; /*!< (@ 0x40005054) Selects the active bank A to active bank B latency. */\r
+ __IO uint32_t DYNAMICMRD; /*!< (@ 0x40005058) Selects the load mode register to active command time. */\r
+ __I uint32_t RESERVED2[9];\r
+ __IO uint32_t STATICEXTENDEDWAIT; /*!< (@ 0x40005080) Selects time for long static memory read and write transfers. */\r
+ __I uint32_t RESERVED3[31];\r
+ __IO uint32_t DYNAMICCONFIG0; /*!< (@ 0x40005100) Selects the configuration information for dynamic memory chip select n. */\r
+ __IO uint32_t DYNAMICRASCAS0; /*!< (@ 0x40005104) Selects the RAS and CAS latencies for dynamic memory chip select n. */\r
+ __I uint32_t RESERVED4[6];\r
+ __IO uint32_t DYNAMICCONFIG1; /*!< (@ 0x40005120) Selects the configuration information for dynamic memory chip select n. */\r
+ __IO uint32_t DYNAMICRASCAS1; /*!< (@ 0x40005124) Selects the RAS and CAS latencies for dynamic memory chip select n. */\r
+ __I uint32_t RESERVED5[6];\r
+ __IO uint32_t DYNAMICCONFIG2; /*!< (@ 0x40005140) Selects the configuration information for dynamic memory chip select n. */\r
+ __IO uint32_t DYNAMICRASCAS2; /*!< (@ 0x40005144) Selects the RAS and CAS latencies for dynamic memory chip select n. */\r
+ __I uint32_t RESERVED6[6];\r
+ __IO uint32_t DYNAMICCONFIG3; /*!< (@ 0x40005160) Selects the configuration information for dynamic memory chip select n. */\r
+ __IO uint32_t DYNAMICRASCAS3; /*!< (@ 0x40005164) Selects the RAS and CAS latencies for dynamic memory chip select n. */\r
+ __I uint32_t RESERVED7[38];\r
+ __IO uint32_t STATICCONFIG0; /*!< (@ 0x40005200) Selects the memory configuration for static chip select n. */\r
+ __IO uint32_t STATICWAITWEN0; /*!< (@ 0x40005204) Selects the delay from chip select n to write enable. */\r
+ __IO uint32_t STATICWAITOEN0; /*!< (@ 0x40005208) Selects the delay from chip select n or address change, whichever is later, to output enable. */\r
+ __IO uint32_t STATICWAITRD0; /*!< (@ 0x4000520C) Selects the delay from chip select n to a read access. */\r
+ __IO uint32_t STATICWAITPAG0; /*!< (@ 0x40005210) Selects the delay for asynchronous page mode sequential accesses for chip select n. */\r
+ __IO uint32_t STATICWAITWR0; /*!< (@ 0x40005214) Selects the delay from chip select n to a write access. */\r
+ __IO uint32_t STATICWAITTURN0; /*!< (@ 0x40005218) Selects bus turnaround cycles */\r
+ __I uint32_t RESERVED8[1];\r
+ __IO uint32_t STATICCONFIG1; /*!< (@ 0x40005220) Selects the memory configuration for static chip select n. */\r
+ __IO uint32_t STATICWAITWEN1; /*!< (@ 0x40005224) Selects the delay from chip select n to write enable. */\r
+ __IO uint32_t STATICWAITOEN1; /*!< (@ 0x40005228) Selects the delay from chip select n or address change, whichever is later, to output enable. */\r
+ __IO uint32_t STATICWAITRD1; /*!< (@ 0x4000522C) Selects the delay from chip select n to a read access. */\r
+ __IO uint32_t STATICWAITPAG1; /*!< (@ 0x40005230) Selects the delay for asynchronous page mode sequential accesses for chip select n. */\r
+ __IO uint32_t STATICWAITWR1; /*!< (@ 0x40005234) Selects the delay from chip select n to a write access. */\r
+ __I uint32_t STATICWAITTURN1; /*!< (@ 0x40005238) read-write */\r
+ __I uint32_t RESERVED9[1];\r
+ __IO uint32_t STATICCONFIG2; /*!< (@ 0x40005240) Selects the memory configuration for static chip select n. */\r
+ __IO uint32_t STATICWAITWEN2; /*!< (@ 0x40005244) Selects the delay from chip select n to write enable. */\r
+ __IO uint32_t STATICWAITOEN2; /*!< (@ 0x40005248) Selects the delay from chip select n or address change, whichever is later, to output enable. */\r
+ __IO uint32_t STATICWAITRD2; /*!< (@ 0x4000524C) Selects the delay from chip select n to a read access. */\r
+ __IO uint32_t STATICWAITPAG2; /*!< (@ 0x40005250) Selects the delay for asynchronous page mode sequential accesses for chip select n. */\r
+ __IO uint32_t STATICWAITWR2; /*!< (@ 0x40005254) Selects the delay from chip select n to a write access. */\r
+ __I uint32_t STATICWAITTURN2; /*!< (@ 0x40005258) read-write */\r
+ __I uint32_t RESERVED10[1];\r
+ __IO uint32_t STATICCONFIG3; /*!< (@ 0x40005260) Selects the memory configuration for static chip select n. */\r
+ __IO uint32_t STATICWAITWEN3; /*!< (@ 0x40005264) Selects the delay from chip select n to write enable. */\r
+ __IO uint32_t STATICWAITOEN3; /*!< (@ 0x40005268) Selects the delay from chip select n or address change, whichever is later, to output enable. */\r
+ __IO uint32_t STATICWAITRD3; /*!< (@ 0x4000526C) Selects the delay from chip select n to a read access. */\r
+ __IO uint32_t STATICWAITPAG3; /*!< (@ 0x40005270) Selects the delay for asynchronous page mode sequential accesses for chip select n. */\r
+ __IO uint32_t STATICWAITWR3; /*!< (@ 0x40005274) Selects the delay from chip select n to a write access. */\r
+ __I uint32_t STATICWAITTURN3; /*!< (@ 0x40005278) read-write */\r
+} LPC_EMC_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- USB0 -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx USB0 Host/Device/OTG controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (USB0)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40006000) USB0 Structure */\r
+ __I uint32_t RESERVED0[64];\r
+ __I uint32_t CAPLENGTH; /*!< (@ 0x40006100) Capability register length */\r
+ __I uint32_t HCSPARAMS; /*!< (@ 0x40006104) Host controller structural parameters */\r
+ __I uint32_t HCCPARAMS; /*!< (@ 0x40006108) Host controller capability parameters */\r
+ __I uint32_t RESERVED1[5];\r
+ __I uint32_t DCIVERSION; /*!< (@ 0x40006120) Device interface version number */\r
+ __I uint32_t RESERVED2[7];\r
+ \r
+ union {\r
+ __IO uint32_t USBCMD_H; /*!< (@ 0x40006140) USB command (host mode) */\r
+ __IO uint32_t USBCMD_D; /*!< (@ 0x40006140) USB command (device mode) */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t USBSTS_H; /*!< (@ 0x40006144) USB status (host mode) */\r
+ __IO uint32_t USBSTS_D; /*!< (@ 0x40006144) USB status (device mode) */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t USBINTR_H; /*!< (@ 0x40006148) USB interrupt enable (host mode) */\r
+ __IO uint32_t USBINTR_D; /*!< (@ 0x40006148) USB interrupt enable (device mode) */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t FRINDEX_H; /*!< (@ 0x4000614C) USB frame index (host mode) */\r
+ __IO uint32_t FRINDEX_D; /*!< (@ 0x4000614C) USB frame index (device mode) */\r
+ };\r
+ __I uint32_t RESERVED3;\r
+ \r
+ union {\r
+ __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40006154) Frame list base address (host mode) */\r
+ __IO uint32_t DEVICEADDR; /*!< (@ 0x40006154) USB device address (device mode) */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */\r
+ __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */\r
+ };\r
+ __IO uint32_t TTCTRL; /*!< (@ 0x4000615C) Asynchronous buffer status for embedded TT (host mode) */\r
+ __IO uint32_t BURSTSIZE; /*!< (@ 0x40006160) Programmable burst size */\r
+ __IO uint32_t TXFILLTUNING; /*!< (@ 0x40006164) Host transmit pre-buffer packet tuning (host mode) */\r
+ __I uint32_t RESERVED4[3];\r
+ __IO uint32_t BINTERVAL; /*!< (@ 0x40006174) Length of virtual frame */\r
+ __IO uint32_t ENDPTNAK; /*!< (@ 0x40006178) Endpoint NAK (device mode) */\r
+ __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000617C) Endpoint NAK Enable (device mode) */\r
+ __I uint32_t RESERVED5;\r
+ \r
+ union {\r
+ __IO uint32_t PORTSC1_H; /*!< (@ 0x40006184) Port 1 status/control (host mode) */\r
+ __IO uint32_t PORTSC1_D; /*!< (@ 0x40006184) Port 1 status/control (device mode) */\r
+ };\r
+ __I uint32_t RESERVED6[7];\r
+ __IO uint32_t OTGSC; /*!< (@ 0x400061A4) OTG status and control */\r
+ \r
+ union {\r
+ __IO uint32_t USBMODE_H; /*!< (@ 0x400061A8) USB mode (host mode) */\r
+ __IO uint32_t USBMODE_D; /*!< (@ 0x400061A8) USB device mode (device mode) */\r
+ };\r
+ __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400061AC) Endpoint setup status */\r
+ __IO uint32_t ENDPTPRIME; /*!< (@ 0x400061B0) Endpoint initialization */\r
+ __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400061B4) Endpoint de-initialization */\r
+ __I uint32_t ENDPTSTAT; /*!< (@ 0x400061B8) Endpoint status */\r
+ __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400061BC) Endpoint complete */\r
+ __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400061C0) Endpoint control 0 */\r
+ __IO uint32_t ENDPTCTRL[5]; /*!< (@ 0x400061C4) Endpoint control */\r
+} LPC_USB0_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- USB1 -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx USB1 Host/Device controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (USB1)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40007000) USB1 Structure */\r
+ __I uint32_t RESERVED0[64];\r
+ __I uint32_t CAPLENGTH; /*!< (@ 0x40007100) Capability register length */\r
+ __I uint32_t HCSPARAMS; /*!< (@ 0x40007104) Host controller structural parameters */\r
+ __I uint32_t HCCPARAMS; /*!< (@ 0x40007108) Host controller capability parameters */\r
+ __I uint32_t RESERVED1[5];\r
+ __I uint32_t DCIVERSION; /*!< (@ 0x40007120) Device interface version number */\r
+ __I uint32_t RESERVED2[7];\r
+ \r
+ union {\r
+ __IO uint32_t USBCMD_H; /*!< (@ 0x40007140) USB command (host mode) */\r
+ __IO uint32_t USBCMD_D; /*!< (@ 0x40007140) USB command (device mode) */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t USBSTS_H; /*!< (@ 0x40007144) USB status (host mode) */\r
+ __IO uint32_t USBSTS_D; /*!< (@ 0x40007144) USB status (device mode) */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t USBINTR_H; /*!< (@ 0x40007148) USB interrupt enable (host mode) */\r
+ __IO uint32_t USBINTR_D; /*!< (@ 0x40007148) USB interrupt enable (device mode) */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t FRINDEX_H; /*!< (@ 0x4000714C) USB frame index (host mode) */\r
+ __I uint32_t FRINDEX_D; /*!< (@ 0x4000714C) USB frame index (device mode) */\r
+ };\r
+ __I uint32_t RESERVED3;\r
+ \r
+ union {\r
+ __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40007154) Frame list base address */\r
+ __IO uint32_t DEVICEADDR; /*!< (@ 0x40007154) USB device address */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (host mode) */\r
+ __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (device mode) */\r
+ };\r
+ __IO uint32_t TTCTRL; /*!< (@ 0x4000715C) Asynchronous buffer status for embedded TT (host mode) */\r
+ __IO uint32_t BURSTSIZE; /*!< (@ 0x40007160) Programmable burst size */\r
+ __IO uint32_t TXFILLTUNING; /*!< (@ 0x40007164) Host transmit pre-buffer packet tuning (host mode) */\r
+ __I uint32_t RESERVED4[2];\r
+ __IO uint32_t ULPIVIEWPORT; /*!< (@ 0x40007170) ULPI viewport */\r
+ __IO uint32_t BINTERVAL; /*!< (@ 0x40007174) Length of virtual frame */\r
+ __IO uint32_t ENDPTNAK; /*!< (@ 0x40007178) Endpoint NAK (device mode) */\r
+ __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000717C) Endpoint NAK Enable (device mode) */\r
+ __I uint32_t RESERVED5;\r
+ \r
+ union {\r
+ __IO uint32_t PORTSC1_H; /*!< (@ 0x40007184) Port 1 status/control (host mode) */\r
+ __IO uint32_t PORTSC1_D; /*!< (@ 0x40007184) Port 1 status/control (device mode) */\r
+ };\r
+ __I uint32_t RESERVED6[8];\r
+ \r
+ union {\r
+ __IO uint32_t USBMODE_H; /*!< (@ 0x400071A8) USB mode (host mode) */\r
+ __IO uint32_t USBMODE_D; /*!< (@ 0x400071A8) USB mode (device mode) */\r
+ };\r
+ __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400071AC) Endpoint setup status */\r
+ __IO uint32_t ENDPTPRIME; /*!< (@ 0x400071B0) Endpoint initialization */\r
+ __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400071B4) Endpoint de-initialization */\r
+ __I uint32_t ENDPTSTAT; /*!< (@ 0x400071B8) Endpoint status */\r
+ __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400071BC) Endpoint complete */\r
+ __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400071C0) Endpoint control 0 */\r
+ __IO uint32_t ENDPTCTRL[3]; /*!< (@ 0x400071C4) Endpoint control */\r
+} LPC_USB1_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- LCD -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx LCD Modification date=1/19/2011 Major revision=0 Minor revision=7 (LCD)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40008000) LCD Structure */\r
+ __IO uint32_t TIMH; /*!< (@ 0x40008000) Horizontal Timing Control register */\r
+ __IO uint32_t TIMV; /*!< (@ 0x40008004) Vertical Timing Control register */\r
+ __IO uint32_t POL; /*!< (@ 0x40008008) Clock and Signal Polarity Control register */\r
+ __IO uint32_t LE; /*!< (@ 0x4000800C) Line End Control register */\r
+ __IO uint32_t UPBASE; /*!< (@ 0x40008010) Upper Panel Frame Base Address register */\r
+ __IO uint32_t LPBASE; /*!< (@ 0x40008014) Lower Panel Frame Base Address register */\r
+ __IO uint32_t CTRL; /*!< (@ 0x40008018) LCD Control register */\r
+ __IO uint32_t INTMSK; /*!< (@ 0x4000801C) Interrupt Mask register */\r
+ __I uint32_t INTRAW; /*!< (@ 0x40008020) Raw Interrupt Status register */\r
+ __I uint32_t INTSTAT; /*!< (@ 0x40008024) Masked Interrupt Status register */\r
+ __O uint32_t INTCLR; /*!< (@ 0x40008028) Interrupt Clear register */\r
+ __I uint32_t UPCURR; /*!< (@ 0x4000802C) Upper Panel Current Address Value register */\r
+ __I uint32_t LPCURR; /*!< (@ 0x40008030) Lower Panel Current Address Value register */\r
+ __I uint32_t RESERVED0[115];\r
+ __IO uint32_t PAL[256]; /*!< (@ 0x40008200) 256x16-bit Color Palette registers */\r
+ __I uint32_t RESERVED1[128];\r
+ __IO uint32_t CRSR_IMG[256]; /*!< (@ 0x40008800) Cursor Image registers */\r
+ __IO uint32_t CRSR_CTRL; /*!< (@ 0x40008C00) Cursor Control register */\r
+ __IO uint32_t CRSR_CFG; /*!< (@ 0x40008C04) Cursor Configuration register */\r
+ __IO uint32_t CRSR_PAL0; /*!< (@ 0x40008C08) Cursor Palette register 0 */\r
+ __IO uint32_t CRSR_PAL1; /*!< (@ 0x40008C0C) Cursor Palette register 1 */\r
+ __IO uint32_t CRSR_XY; /*!< (@ 0x40008C10) Cursor XY Position register */\r
+ __IO uint32_t CRSR_CLIP; /*!< (@ 0x40008C14) Cursor Clip Position register */\r
+ __I uint32_t RESERVED2[2];\r
+ __IO uint32_t CRSR_INTMSK; /*!< (@ 0x40008C20) Cursor Interrupt Mask register */\r
+ __O uint32_t CRSR_INTCLR; /*!< (@ 0x40008C24) Cursor Interrupt Clear register */\r
+ __I uint32_t CRSR_INTRAW; /*!< (@ 0x40008C28) Cursor Raw Interrupt Status register */\r
+ __I uint32_t CRSR_INTSTAT; /*!< (@ 0x40008C2C) Cursor Masked Interrupt Status register */\r
+} LPC_LCD_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- ETHERNET -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx Ethernet Modification date=1/20/2011 Major revision=0 Minor revision=7 (ETHERNET)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40010000) ETHERNET Structure */\r
+ __IO uint32_t MAC_CONFIG; /*!< (@ 0x40010000) MAC configuration register */\r
+ __IO uint32_t MAC_FRAME_FILTER; /*!< (@ 0x40010004) MAC frame filter */\r
+ __IO uint32_t MAC_HASHTABLE_HIGH; /*!< (@ 0x40010008) Hash table high register */\r
+ __IO uint32_t MAC_HASHTABLE_LOW; /*!< (@ 0x4001000C) Hash table low register */\r
+ __IO uint32_t MAC_MII_ADDR; /*!< (@ 0x40010010) MII address register */\r
+ __IO uint32_t MAC_MII_DATA; /*!< (@ 0x40010014) MII data register */\r
+ __IO uint32_t MAC_FLOW_CTRL; /*!< (@ 0x40010018) Flow control register */\r
+ __IO uint32_t MAC_VLAN_TAG; /*!< (@ 0x4001001C) VLAN tag register */\r
+ __I uint32_t RESERVED0;\r
+ __IO uint32_t MAC_DEBUG; /*!< (@ 0x40010024) Debug register */\r
+ __IO uint32_t MAC_RWAKE_FRFLT; /*!< (@ 0x40010028) Remote wake-up frame filter */\r
+ __IO uint32_t MAC_PMT_CTRL_STAT; /*!< (@ 0x4001002C) PMT control and status */\r
+ __I uint32_t RESERVED1[2];\r
+ __IO uint32_t MAC_INTR; /*!< (@ 0x40010038) Interrupt status register */\r
+ __IO uint32_t MAC_INTR_MASK; /*!< (@ 0x4001003C) Interrupt mask register */\r
+ __IO uint32_t MAC_ADDR0_HIGH; /*!< (@ 0x40010040) MAC address 0 high register */\r
+ __IO uint32_t MAC_ADDR0_LOW; /*!< (@ 0x40010044) MAC address 0 low register */\r
+ __I uint32_t RESERVED2[430];\r
+ __IO uint32_t MAC_TIMESTP_CTRL; /*!< (@ 0x40010700) Time stamp control register */\r
+ __I uint32_t RESERVED3[575];\r
+ __IO uint32_t DMA_BUS_MODE; /*!< (@ 0x40011000) Bus Mode Register */\r
+ __IO uint32_t DMA_TRANS_POLL_DEMAND; /*!< (@ 0x40011004) Transmit poll demand register */\r
+ __IO uint32_t DMA_REC_POLL_DEMAND; /*!< (@ 0x40011008) Receive poll demand register */\r
+ __IO uint32_t DMA_REC_DES_ADDR; /*!< (@ 0x4001100C) Receive descriptor list address register */\r
+ __IO uint32_t DMA_TRANS_DES_ADDR; /*!< (@ 0x40011010) Transmit descriptor list address register */\r
+ __IO uint32_t DMA_STAT; /*!< (@ 0x40011014) Status register */\r
+ __IO uint32_t DMA_OP_MODE; /*!< (@ 0x40011018) Operation mode register */\r
+ __IO uint32_t DMA_INT_EN; /*!< (@ 0x4001101C) Interrupt enable register */\r
+ __IO uint32_t DMA_MFRM_BUFOF; /*!< (@ 0x40011020) Missed frame and buffer overflow register */\r
+ __IO uint32_t DMA_REC_INT_WDT; /*!< (@ 0x40011024) Receive interrupt watchdog timer register */\r
+ __I uint32_t RESERVED4[8];\r
+ __IO uint32_t DMA_CURHOST_TRANS_DES; /*!< (@ 0x40011048) Current host transmit descriptor register */\r
+ __IO uint32_t DMA_CURHOST_REC_DES; /*!< (@ 0x4001104C) Current host receive descriptor register */\r
+ __IO uint32_t DMA_CURHOST_TRANS_BUF; /*!< (@ 0x40011050) Current host transmit buffer address register */\r
+ __IO uint32_t DMA_CURHOST_REC_BUF; /*!< (@ 0x40011054) Current host receive buffer address register */\r
+} LPC_ETHERNET_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- ATIMER -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx Alarm timer Modification date=1/7/2011 Major revision=0 Minor revision=6 (ATIMER)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40040000) ATIMER Structure */\r
+ __IO uint32_t DOWNCOUNTER; /*!< (@ 0x40040000) Downcounter register */\r
+ __IO uint32_t PRESET; /*!< (@ 0x40040004) Preset value register */\r
+ __I uint32_t RESERVED0[1012];\r
+ __O uint32_t CLR_EN; /*!< (@ 0x40040FD8) Interrupt clear enable register */\r
+ __O uint32_t SET_EN; /*!< (@ 0x40040FDC) Interrupt set enable register */\r
+ __I uint32_t STATUS; /*!< (@ 0x40040FE0) Status register */\r
+ __I uint32_t ENABLE; /*!< (@ 0x40040FE4) Enable register */\r
+ __O uint32_t CLR_STAT; /*!< (@ 0x40040FE8) Clear register */\r
+ __O uint32_t SET_STAT; /*!< (@ 0x40040FEC) Set register */\r
+} LPC_ATIMER_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- REGFILE -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx rtc/REGFILE date=1/20/2011 Major revision=0 Minor revision=7 (REGFILE)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40041000) REGFILE Structure */\r
+ __IO uint32_t REGFILE[64]; /*!< (@ 0x40041000) General purpose storage register */\r
+} LPC_REGFILE_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- PMC -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx Power Management Controller (PMC) Modification date=1/20/2011 Major revision=0 Minor revision=7 (PMC)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40042000) PMC Structure */\r
+ __IO uint32_t PD0_SLEEP0_HW_ENA; /*!< (@ 0x40042000) Hardware sleep event enable register */\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t PD0_SLEEP0_HW_EDG_LVL; /* 0x008 */\r
+ uint32_t RESERVED1[3];\r
+ __IO uint32_t PD0_SLEEP0_CONFIG; /* 0x018 */\r
+ __IO uint32_t PD0_SLEEP0_MODE; /*!< (@ 0x4004201C) Sleep power mode register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t PD0_WAKE0_HW_ENA; /* 0x080 */\r
+ uint32_t RESERVED3;\r
+ __IO uint32_t PD0_WAKE0_HW_EDG_LVL; /* 0x088 */\r
+ uint32_t RESERVED4[67];\r
+ __IO uint32_t PD0_PSU_OPT; /* 0x198 */\r
+ uint32_t RESERVED5[2];\r
+ __IO uint32_t PD0_PSU_DELAY; /* 0x1A4 */\r
+ uint32_t RESERVED6;\r
+ __IO uint32_t PD0_POST_PSU_DELAY; /* 0x1AC */\r
+} LPC_PMC_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- CREG -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx Configuration Registers (CREG) Modification date=1/20/2011 Major revision=0 Minor revision=7 (CREG)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40043000) CREG Structure */\r
+ __IO uint32_t IRCTRM; /*!< (@ 0x40043000) IRC trim register */\r
+ __IO uint32_t CREG0; /*!< (@ 0x40043004) Chip configuration register 32 kHz oscillator output and BOD control register. */\r
+ __IO uint32_t PMUCON; /*!< (@ 0x40043008) Power mode control register. */\r
+ __I uint32_t RESERVED0[61];\r
+ __IO uint32_t M4MEMMAP; /*!< (@ 0x40043100) ARM Cortex-M4 memory mapping */\r
+ __I uint32_t RESERVED1[5];\r
+ __IO uint32_t CREG5; /*!< (@ 0x40043118) Chip configuration register 5. Controls JTAG access. */\r
+ __IO uint32_t DMAMUX; /*!< (@ 0x4004311C) DMA muxing control */\r
+ __I uint32_t RESERVED2[2];\r
+ __IO uint32_t ETBCFG; /*!< (@ 0x40043128) ETB RAM configuration */\r
+ __IO uint32_t CREG6; /*!< (@ 0x4004312C) tbd. */\r
+ __I uint32_t RESERVED3[52];\r
+ __I uint32_t CHIPID; /*!< (@ 0x40043200) Part ID */\r
+} LPC_CREG_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- EVENTROUTER -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx Event router Modification date=1/20/2011 Major revision=0 Minor revision=7 (EVENTROUTER)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40044000) EVENTROUTER Structure */\r
+ __IO uint32_t HILO; /*!< (@ 0x40044000) Level configuration register */\r
+ __IO uint32_t EDGE; /*!< (@ 0x40044004) Edge configuration */\r
+ __I uint32_t RESERVED0[1012];\r
+ __O uint32_t CLR_EN; /*!< (@ 0x40044FD8) Event clear enable register */\r
+ __O uint32_t SET_EN; /*!< (@ 0x40044FDC) Event set enable register */\r
+ __I uint32_t STATUS; /*!< (@ 0x40044FE0) Status register */\r
+ __I uint32_t ENABLE; /*!< (@ 0x40044FE4) Enable register */\r
+ __O uint32_t CLR_STAT; /*!< (@ 0x40044FE8) Clear register */\r
+ __O uint32_t SET_STAT; /*!< (@ 0x40044FEC) Set register */\r
+} LPC_EVENTROUTER_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- RTC -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx Real-Time Clock (RTC) Modification date=1/20/2011 Major revision=0 Minor revision=7 (RTC)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40046000) RTC Structure */\r
+ __O uint32_t ILR; /*!< (@ 0x40046000) Interrupt Location Register */\r
+ __I uint32_t RESERVED0;\r
+ __IO uint32_t CCR; /*!< (@ 0x40046008) Clock Control Register */\r
+ __IO uint32_t CIIR; /*!< (@ 0x4004600C) Counter Increment Interrupt Register */\r
+ __IO uint32_t AMR; /*!< (@ 0x40046010) Alarm Mask Register */\r
+ __I uint32_t CTIME0; /*!< (@ 0x40046014) Consolidated Time Register 0 */\r
+ __I uint32_t CTIME1; /*!< (@ 0x40046018) Consolidated Time Register 1 */\r
+ __I uint32_t CTIME2; /*!< (@ 0x4004601C) Consolidated Time Register 2 */\r
+ __IO uint32_t SEC; /*!< (@ 0x40046020) Seconds Register */\r
+ __IO uint32_t MIN; /*!< (@ 0x40046024) Minutes Register */\r
+ __IO uint32_t HRS; /*!< (@ 0x40046028) Hours Register */\r
+ __IO uint32_t DOM; /*!< (@ 0x4004602C) Day of Month Register */\r
+ __IO uint32_t DOW; /*!< (@ 0x40046030) Day of Week Register */\r
+ __IO uint32_t DOY; /*!< (@ 0x40046034) Day of Year Register */\r
+ __IO uint32_t MONTH; /*!< (@ 0x40046038) Months Register */\r
+ __IO uint32_t YEAR; /*!< (@ 0x4004603C) Years Register */\r
+ __IO uint32_t CALIBRATION; /*!< (@ 0x40046040) Calibration Value Register */\r
+ __I uint32_t RESERVED1[7];\r
+ __IO uint32_t ASEC; /*!< (@ 0x40046060) Alarm value for Seconds */\r
+ __IO uint32_t AMIN; /*!< (@ 0x40046064) Alarm value for Minutes */\r
+ __IO uint32_t AHRS; /*!< (@ 0x40046068) Alarm value for Hours */\r
+ __IO uint32_t ADOM; /*!< (@ 0x4004606C) Alarm value for Day of Month */\r
+ __IO uint32_t ADOW; /*!< (@ 0x40046070) Alarm value for Day of Week */\r
+ __IO uint32_t ADOY; /*!< (@ 0x40046074) Alarm value for Day of Year */\r
+ __IO uint32_t AMON; /*!< (@ 0x40046078) Alarm value for Months */\r
+ __IO uint32_t AYRS; /*!< (@ 0x4004607C) Alarm value for Year */\r
+} LPC_RTC_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- CGU -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC43xx Clock Generation Unit (CGU) Modification date=6/1/2011 Major revision=0 Minor revision=1 (CGU)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40050000) CGU Structure */\r
+ __I uint32_t RESERVED0[5];\r
+ __IO uint32_t FREQ_MON; /*!< (@ 0x40050014) Frequency monitor register */\r
+ __IO uint32_t XTAL_OSC_CTRL; /*!< (@ 0x40050018) Crystal oscillator control register */\r
+ __I uint32_t PLL0USB_STAT; /*!< (@ 0x4005001C) PLL0 (USB) status register */\r
+ __IO uint32_t PLL0USB_CTRL; /*!< (@ 0x40050020) PLL0 (USB) control register */\r
+ __IO uint32_t PLL0USB_MDIV; /*!< (@ 0x40050024) PLL0 (USB) M-divider register */\r
+ __IO uint32_t PLL0USB_NP_DIV; /*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */\r
+ __I uint32_t PLL0AUDIO_STAT; /*!< (@ 0x4005002C) PLL0 (audio) status register */\r
+ __IO uint32_t PLL0AUDIO_CTRL; /*!< (@ 0x40050030) PLL0 (audio) control register */\r
+ __IO uint32_t PLL0AUDIO_MDIV; /*!< (@ 0x40050034) PLL0 (audio) M-divider register */\r
+ __IO uint32_t PLL0AUDIO_NP_DIV; /*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */\r
+ __IO uint32_t PLL0AUDIO_FRAC; /*!< (@ 0x4005003C) PLL0 (audio) */\r
+ __I uint32_t PLL1_STAT; /*!< (@ 0x40050040) PLL1 status register */\r
+ __IO uint32_t PLL1_CTRL; /*!< (@ 0x40050044) PLL1 control register */\r
+ __IO uint32_t IDIVA_CTRL; /*!< (@ 0x40050048) Integer divider A control register */\r
+ __IO uint32_t IDIVB_CTRL; /*!< (@ 0x4005004C) Integer divider B control register */\r
+ __IO uint32_t IDIVC_CTRL; /*!< (@ 0x40050050) Integer divider C control register */\r
+ __IO uint32_t IDIVD_CTRL; /*!< (@ 0x40050054) Integer divider D control register */\r
+ __IO uint32_t IDIVE_CTRL; /*!< (@ 0x40050058) Integer divider E control register */\r
+ __IO uint32_t BASE_SAFE_CLK; /*!< (@ 0x4005005C) Output stage 0 control register for base clock BASE_SAFE_CLK */\r
+ __IO uint32_t BASE_USB0_CLK; /*!< (@ 0x40050060) Output stage 1 control register for base clock BASE_USB0_CLK */\r
+ __IO uint32_t BASE_M0_CLK; /*!< (@ 0x40050064) */\r
+ __IO uint32_t BASE_USB1_CLK; /*!< (@ 0x40050068) Output stage 3 control register for base clock BASE_USB1_CLK */\r
+ __IO uint32_t BASE_M4_CLK; /*!< (@ 0x4005006C) Output stage control register */\r
+ __IO uint32_t BASE_SPIFI0_CLK; /*!< (@ 0x40050070) Output stage control register */\r
+ __IO uint32_t BASE_SPI_CLK; /*!< (@ 0x40050074) Output stage control register */\r
+ __IO uint32_t BASE_PHY_RX_CLK; /*!< (@ 0x40050078) Output stage control register */\r
+ __IO uint32_t BASE_PHY_TX_CLK; /*!< (@ 0x4005007C) Output stage control register */\r
+ __IO uint32_t BASE_APB1_CLK; /*!< (@ 0x40050080) Output stage control register */\r
+ __IO uint32_t BASE_APB3_CLK; /*!< (@ 0x40050084) Output stage control register */\r
+ __IO uint32_t BASE_LCD_CLK; /*!< (@ 0x40050088) Output stage control register */\r
+ __IO uint32_t BASE_VADC_CLK; /*!< (@ 0x4005008C) Output stage control register */\r
+ __IO uint32_t BASE_SDIO_CLK; /*!< (@ 0x40050090) Output stage control register */\r
+ __IO uint32_t BASE_SSP0_CLK; /*!< (@ 0x40050094) Output stage control register */\r
+ __IO uint32_t BASE_SSP1_CLK; /*!< (@ 0x40050098) Output stage control register */\r
+ __IO uint32_t BASE_UART0_CLK; /*!< (@ 0x4005009C) Output stage control register */\r
+ __IO uint32_t BASE_UART1_CLK; /*!< (@ 0x400500A0) Output stage control register */\r
+ __IO uint32_t BASE_UART2_CLK; /*!< (@ 0x400500A4) Output stage control register */\r
+ __IO uint32_t BASE_UART3_CLK; /*!< (@ 0x400500A8) Output stage control register */\r
+ __IO uint32_t BASE_OUT_CLK; /*!< (@ 0x400500AC) Output stage 20 control register for base clock BASE_OUT_CLK */\r
+ __IO uint32_t BASE_AOTEST_CLK; /*!< (@ 0x400500B0) */\r
+ __IO uint32_t BASE_ISO_TCK; /*!< (@ 0x400500B4) */\r
+ __IO uint32_t BASE_BSR_TCK; /*!< (@ 0x400500B8) */\r
+ __IO uint32_t BASE_CLK_TESTSHELL; /*!< (@ 0x400500BC) */\r
+ __IO uint32_t BASE_APLL_CLK; /*!< (@ 0x400500C0) Output stage 25 control register for base clock BASE_APLL_CLK */\r
+ __IO uint32_t BASE_CGU_OUT0_CLK; /*!< (@ 0x400500C4) Output stage 26 control register for base clock BASE_CGU_OUT0_CLK */\r
+ __IO uint32_t BASE_CGU_OUT1_CLK; /*!< (@ 0x400500C8) Output stage 27 control register for base clock BASE_CGU_OUT1_CLK */\r
+} LPC_CGU_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- CCU1 -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx Clock Control Unit (CCU) Modification date=1/21/2011 Major revision=0 Minor revision=7 (CCU1)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40051000) CCU1 Structure */\r
+ __IO uint32_t PM; /*!< (@ 0x40051000) CCU1 power mode register */\r
+ __I uint32_t BASE_STAT; /*!< (@ 0x40051004) CCU1 base clocks status register */\r
+ __I uint32_t RESERVED0[62];\r
+ __IO uint32_t CLK_APB3_BUS_CFG; /*!< (@ 0x40051100) CLK_APB3_BUS clock configuration register */\r
+ __I uint32_t CLK_APB3_BUS_STAT; /*!< (@ 0x40051104) CLK_APB3_BUS clock status register */\r
+ __IO uint32_t CLK_APB3_I2C1_CFG; /*!< (@ 0x40051108) CLK_APB3_I2C1 clock configuration register */\r
+ __I uint32_t CLK_APB3_I2C1_STAT; /*!< (@ 0x4005110C) CLK_APB3_I2C1 clock status register */\r
+ __IO uint32_t CLK_APB3_DAC_CFG; /*!< (@ 0x40051110) CLK_APB3_DAC clock configuration register */\r
+ __I uint32_t CLK_APB3_DAC_STAT; /*!< (@ 0x40051114) CLK_APB3_DAC clock status register */\r
+ __IO uint32_t CLK_APB3_ADC0_CFG; /*!< (@ 0x40051118) CLK_APB3_ADC0 clock configuration register */\r
+ __I uint32_t CLK_APB3_ADC0_STAT; /*!< (@ 0x4005111C) CLK_APB3_ADC0 clock status register */\r
+ __IO uint32_t CLK_APB3_ADC1_CFG; /*!< (@ 0x40051120) CLK_APB3_ADC1 clock configuration register */\r
+ __I uint32_t CLK_APB3_ADC1_STAT; /*!< (@ 0x40051124) CLK_APB3_ADC1 clock status register */\r
+ __IO uint32_t CLK_APB3_CAN0_CFG; /*!< (@ 0x40051128) CLK_APB3_CAN0 clock configuration register */\r
+ __I uint32_t CLK_APB3_CAN0_STAT; /*!< (@ 0x4005112C) CLK_APB3_CAN0 clock status register */\r
+ __IO uint32_t CLK_APB3_SPARE0_CFG; /*!< (@ 0x40051130) */\r
+ __I uint32_t CLK_APB3_SPARE0_STAT; /*!< (@ 0x40051134) */\r
+ __I uint32_t RESERVED1[52-2];\r
+ __IO uint32_t CLK_APB1_BUS_CFG; /*!< (@ 0x40051200) CLK_APB1_BUS clock configuration register */\r
+ __I uint32_t CLK_APB1_BUS_STAT; /*!< (@ 0x40051204) CLK_APB1_BUS clock status register */\r
+ __IO uint32_t CLK_APB1_MOTOCONPWM_CFG; /*!< (@ 0x40051208) CLK_APB1_MOTOCONPWM clock configuration register */\r
+ __I uint32_t CLK_APB1_MOTOCONPWM_STAT; /*!< (@ 0x4005120C) CLK_APB1_MOTOCONPWM clock status register */\r
+ __IO uint32_t CLK_ABP1_I2C0_CFG; /*!< (@ 0x40051210) CLK_ABP1_I2C0 clock configuration register */\r
+ __I uint32_t CLK_APB1_I2C0_STAT; /*!< (@ 0x40051214) CLK_APB1_I2C0 clock status register */\r
+ __IO uint32_t CLK_APB1_I2S_CFG; /*!< (@ 0x40051218) CLK_APB1_I2S clock configuration register */\r
+ __I uint32_t CLK_APB1_I2S_STAT; /*!< (@ 0x4005121C) CLK_APB1_I2S clock status register */\r
+ __IO uint32_t CLK_APB1_CAN1_CFG; /*!< (@ 0x40051220) CLK_APB1_CAN1 clock configuration register */\r
+ __I uint32_t CLK_APB1_CAN1_STAT; /*!< (@ 0x40051224) CLK_APB1_CAN1 clock status register */\r
+ __IO uint32_t CLK_APB1_SPARE0_CFG; /*!< (@ 0x40051228) */\r
+ __I uint32_t CLK_APB1_SPARE0_STAT; /*!< (@ 0x4005122C) */\r
+ __I uint32_t RESERVED2[54-2];\r
+ __IO uint32_t CLK_SPIFI_CFG; /*!< (@ 0x40051300) CLK_SPIFI clock configuration register */\r
+ __I uint32_t CLK_SPIFI_STAT; /*!< (@ 0x40051304) CLK_APB1_SPIFI clock status register */\r
+ __I uint32_t RESERVED3[62];\r
+ __IO uint32_t CLK_M4_BUS_CFG; /*!< (@ 0x40051400) CLK_M4_BUS clock configuration register */\r
+ __I uint32_t CLK_M4_BUS_STAT; /*!< (@ 0x40051404) CLK_M4_BUSclock status register */\r
+ __IO uint32_t CLK_M4_SPIFI_CFG; /*!< (@ 0x40051408) CLK_M4_SPIFI clock configuration register */\r
+ __I uint32_t CLK_M4_SPIFI_STAT; /*!< (@ 0x4005140C) CLK_M4_SPIFI clock status register */\r
+ __IO uint32_t CLK_M4_GPIO_CFG; /*!< (@ 0x40051410) CLK_M4_GPIO clock configuration register */\r
+ __I uint32_t CLK_M4_GPIO_STAT; /*!< (@ 0x40051414) CLK_M4_GPIO clock status register */\r
+ __IO uint32_t CLK_M4_LCD_CFG; /*!< (@ 0x40051418) CLK_M4_LCD clock configuration register */\r
+ __I uint32_t CLK_M4_LCD_STAT; /*!< (@ 0x4005141C) CLK_M4_LCD clock status register */\r
+ __IO uint32_t CLK_M4_ETHERNET_CFG; /*!< (@ 0x40051420) CLK_M4_ETHERNET clock configuration register */\r
+ __I uint32_t CLK_M4_ETHERNET_STAT; /*!< (@ 0x40051424) CLK_M4_ETHERNET clock status register */\r
+ __IO uint32_t CLK_M4_USB0_CFG; /*!< (@ 0x40051428) CLK_M4_USB0 clock configuration register */\r
+ __I uint32_t CLK_M4_USB0_STAT; /*!< (@ 0x4005142C) CLK_M4_USB0 clock status register */\r
+ __IO uint32_t CLK_M4_EMC_CFG; /*!< (@ 0x40051430) CLK_M4_EMC clock configuration register */\r
+ __I uint32_t CLK_M4_EMC_STAT; /*!< (@ 0x40051434) CLK_M4_EMC clock status register */\r
+ __IO uint32_t CLK_M4_SDIO_CFG; /*!< (@ 0x40051438) CLK_M4_SDIO clock configuration register */\r
+ __I uint32_t CLK_M4_SDIO_STAT; /*!< (@ 0x4005143C) CLK_M4_SDIO clock status register */\r
+ __IO uint32_t CLK_M4_DMA_CFG; /*!< (@ 0x40051440) CLK_M4_DMA clock configuration register */\r
+ __I uint32_t CLK_M4_DMA_STAT; /*!< (@ 0x40051444) CLK_M4_DMA clock status register */\r
+ __IO uint32_t CLK_M4_M4CORE_CFG; /*!< (@ 0x40051448) CLK_M4_M4CORE clock configuration register */\r
+ __I uint32_t CLK_M4_M4CORE_STAT; /*!< (@ 0x4005144C) CLK_M4_M4CORE clock status register */\r
+ __IO uint32_t CLK_M4_USART_CFG; /*!< (@ 0x40051450) Reserved for Eagle */\r
+ __I uint32_t CLK_M4_USART_STAT; /*!< (@ 0x40051454) Reserved for Eagle */\r
+ __IO uint32_t CLK_M4_EVENTHANDLER_CFG; /*!< (@ 0x40051458) Reserved for Eagle */\r
+ __I uint32_t CLK_M4_EVENTHANDLER_STAT; /*!< (@ 0x4005145C) Reserved for Eagle */\r
+// __I uint32_t RESERVED4[4];\r
+ __IO uint32_t CLK_M4_AES_CFG; /*!< (@ 0x40051460) CLK_M4_AES clock configuration register */\r
+ __I uint32_t CLK_M4_AES_STAT; /*!< (@ 0x40051464) CLK_M4_AES clock status register */\r
+ __IO uint32_t CLK_M4_SCT_CFG; /*!< (@ 0x40051468) CLK_M4_SCT clock configuration register */\r
+ __I uint32_t CLK_M4_SCT_STAT; /*!< (@ 0x4005146C) CLK_M4_SCT clock status register */\r
+ __IO uint32_t CLK_M4_USB1_CFG; /*!< (@ 0x40051470) CLK_M4_USB1 clock configuration register */\r
+ __I uint32_t CLK_M4_USB1_STAT; /*!< (@ 0x40051474) CLK_M4_USB1 clock status register */\r
+ __IO uint32_t CLK_M4_EMCDIV_CFG; /*!< (@ 0x40051478) CLK_M4_EMCDIV clock configuration register */\r
+ __I uint32_t CLK_M4_EMCDIV_STAT; /*!< (@ 0x4005147C) CLK_M4_EMCDIV clock status register */\r
+ __IO uint32_t CLK_M4_FLASH0_CFG; /*!< (@ 0x40051480) */\r
+ __I uint32_t CLK_M4_FLASH0_STAT; /*!< (@ 0x40051484) */\r
+ __IO uint32_t CLK_M4_FLASH1_CFG; /*!< (@ 0x40051488) */\r
+ __I uint32_t CLK_M4_FLASH1_STAT; /*!< (@ 0x4005148C) */\r
+ __IO uint32_t CLK_M4_M0ACORE_CFG; /*!< (@ 0x40051490) */\r
+ __I uint32_t CLK_M4_M0ACORE_STAT; /*!< (@ 0x40051494) */\r
+ __IO uint32_t CLK_M4_VADC_CFG; /*!< (@ 0x40051498) */\r
+ __I uint32_t CLK_M4_VADC_STAT; /*!< (@ 0x4005149C) */\r
+ __IO uint32_t CLK_M4_EEPROM_CFG; /*!< (@ 0x400514A0) */\r
+ __I uint32_t CLK_M4_EEPROM_STAT; /*!< (@ 0x400514A4) */\r
+ __IO uint32_t CLK_M4_SPARE0_CFG; /*!< (@ 0x400514A8) */\r
+ __I uint32_t CLK_M4_SPARE0_STAT; /*!< (@ 0x400514AC) */\r
+ __IO uint32_t CLK_M4_SPARE1_CFG; /*!< (@ 0x400514B0) */\r
+ __I uint32_t CLK_M4_SPARE1_STAT; /*!< (@ 0x400514B4) */\r
+ __I uint32_t RESERVED5[32-14];\r
+ __IO uint32_t CLK_M4_WWDT_CFG; /*!< (@ 0x40051500) CLK_M4_WWDT clock configuration register */\r
+ __I uint32_t CLK_M4_WWDT_STAT; /*!< (@ 0x40051504) CLK_M4_WWDT clock status register */\r
+ __IO uint32_t CLK_M4_USART0_CFG; /*!< (@ 0x40051508) CLK_M4_USART0 clock configuration register */\r
+ __I uint32_t CLK_M4_USART0_STAT; /*!< (@ 0x4005150C) CLK_M4_USART0 clock status register */\r
+ __IO uint32_t CLK_M4_UART1_CFG; /*!< (@ 0x40051510) CLK_M4_UART1 clock configuration register */\r
+ __I uint32_t CLK_M4_UART1_STAT; /*!< (@ 0x40051514) CLK_M4_UART1 clock status register */\r
+ __IO uint32_t CLK_M4_SSP0_CFG; /*!< (@ 0x40051518) CLK_M4_SSP0 clock configuration register */\r
+ __I uint32_t CLK_M4_SSP0_STAT; /*!< (@ 0x4005151C) CLK_M4_SSP0 clock status register */\r
+ __IO uint32_t CLK_M4_TIMER0_CFG; /*!< (@ 0x40051520) CLK_M4_TIMER0 clock configuration register */\r
+ __I uint32_t CLK_M4_TIMER0_STAT; /*!< (@ 0x40051524) CLK_M4_TIMER0 clock status register */\r
+ __IO uint32_t CLK_M4_TIMER1_CFG; /*!< (@ 0x40051528) CLK_M4_TIMER1clock configuration register */\r
+ __I uint32_t CLK_M4_TIMER1_STAT; /*!< (@ 0x4005152C) CLK_M4_TIMER1 clock status register */\r
+ __IO uint32_t CLK_M4_SCU_CFG; /*!< (@ 0x40051530) CLK_M4_SCU clock configuration register */\r
+ __I uint32_t CLK_M4_SCU_STAT; /*!< (@ 0x40051534) CLK_SCU_XXX clock status register */\r
+ __IO uint32_t CLK_M4_CREG_CFG; /*!< (@ 0x40051538) CLK_M4_CREGclock configuration register */\r
+ __I uint32_t CLK_M4_CREG_STAT; /*!< (@ 0x4005153C) CLK_M4_CREG clock status register */\r
+ __IO uint32_t CLK_APB0_SPARE1_CFG; /*!< (@ 0x40051540) */\r
+ __I uint32_t CLK_APB0_SPARE1_STAT; /*!< (@ 0x40051544) */\r
+ __I uint32_t RESERVED6[48-2];\r
+ __IO uint32_t CLK_M4_RITIMER_CFG; /*!< (@ 0x40051600) CLK_M4_RITIMER clock configuration register */\r
+ __I uint32_t CLK_M4_RITIMER_STAT; /*!< (@ 0x40051604) CLK_M4_RITIMER clock status register */\r
+ __IO uint32_t CLK_M4_USART2_CFG; /*!< (@ 0x40051608) CLK_M4_USART2 clock configuration register */\r
+ __I uint32_t CLK_M4_USART2_STAT; /*!< (@ 0x4005160C) CLK_M4_USART2 clock status register */\r
+ __IO uint32_t CLK_M4_USART3_CFG; /*!< (@ 0x40051610) CLK_M4_USART3 clock configuration register */\r
+ __I uint32_t CLK_M4_USART3_STAT; /*!< (@ 0x40051614) CLK_M4_USART3 clock status register */\r
+ __IO uint32_t CLK_M4_TIMER2_CFG; /*!< (@ 0x40051618) CLK_M4_TIMER2 clock configuration register */\r
+ __I uint32_t CLK_M4_TIMER2_STAT; /*!< (@ 0x4005161C) CLK_M4_TIMER2 clock status register */\r
+ __IO uint32_t CLK_M4_TIMER3_CFG; /*!< (@ 0x40051620) CLK_M4_TIMER3 clock configuration register */\r
+ __I uint32_t CLK_M4_TIMER3_STAT; /*!< (@ 0x40051624) CLK_M4_TIMER3 clock status register */\r
+ __IO uint32_t CLK_M4_SSP1_CFG; /*!< (@ 0x40051628) CLK_M4_SSP1 clock configuration register */\r
+ __I uint32_t CLK_M4_SSP1_STAT; /*!< (@ 0x4005162C) CLK_M4_SSP1 clock status register */\r
+ __IO uint32_t CLK_M4_QEI_CFG; /*!< (@ 0x40051630) CLK_M4_QEIclock configuration register */\r
+ __I uint32_t CLK_M4_QEI_STAT; /*!< (@ 0x40051634) CLK_M4_QEI clock status register */\r
+ __IO uint32_t CLK_APB2_SPARE1_CFG; /*!< (@ 0x40051638) */\r
+ __I uint32_t CLK_APB2_SPARE1_STAT; /*!< (@ 0x4005163C) */\r
+ __I uint32_t RESERVED7[48];\r
+ __IO uint32_t CLK_M0_BUS_CFG; /*!< (@ 0x40051700) */\r
+ __I uint32_t CLK_M0_BUS_STAT; /*!< (@ 0x40051704) */\r
+ __IO uint32_t CLK_M0_GPIO_CFG; /*!< (@ 0x40051708) */\r
+ __I uint32_t CLK_M0_GPIO_STAT; /*!< (@ 0x4005170C) */\r
+ __IO uint32_t CLK_M0_M0SCORE_CFG; /*!< (@ 0x40051710) */\r
+ __I uint32_t CLK_M0_M0SCORE_STAT; /*!< (@ 0x40051714) */\r
+ __IO uint32_t CLK_M0_SGPIO_CFG; /*!< (@ 0x40051718) */\r
+ __I uint32_t CLK_M0_SGPIO_STAT; /*!< (@ 0x4005171C) */\r
+ __IO uint32_t CLK_M0_EDM_CFG; /*!< (@ 0x40051720) */\r
+ __I uint32_t CLK_M0_EDM_STAT; /*!< (@ 0x40051724) */\r
+ __I uint32_t RESERVED72[54];\r
+ __IO uint32_t CLK_USB0_CFG; /*!< (@ 0x40051800) CLK_M4_USB0 clock configuration register */\r
+ __I uint32_t CLK_USB0_STAT; /*!< (@ 0x40051804) CLK_USB0 clock status register */\r
+ __I uint32_t RESERVED8[62];\r
+ __IO uint32_t CLK_USB1_CFG; /*!< (@ 0x40051900) CLK_USB1 clock configuration register */\r
+ __I uint32_t CLK_USB1_STAT; /*!< (@ 0x40051904) CLK_USB1 clock status register */\r
+ __I uint32_t RESERVED9[126];\r
+ __IO uint32_t CLK_VADC_CFG; /*!< (@ 0x40051B00) CLK_VADC clock configuration register */\r
+ __I uint32_t CLK_VADC_STAT; /*!< (@ 0x40051B04) CLK_VADC clock status register */\r
+} LPC_CCU1_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- CCU2 -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx Clock Control Unit (CCU) Modification date=1/21/2011 Major revision=0 Minor revision=7 (CCU2)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40052000) CCU2 Structure */\r
+ __IO uint32_t PM; /*!< (@ 0x40052000) Power mode register */\r
+ __I uint32_t BASE_STAT; /*!< (@ 0x40052004) CCU base clocks status register */\r
+ __I uint32_t RESERVED0[62];\r
+ __IO uint32_t CLK_APLL_CFG; /*!< (@ 0x40052100) CLK_APLL clock configuration register */\r
+ __I uint32_t CLK_APLL_STAT; /*!< (@ 0x40052104) CLK_APLL clock status register */\r
+ __I uint32_t RESERVED1[62];\r
+ __IO uint32_t CLK_APB2_USART3_CFG; /*!< (@ 0x40052200) CLK_APB2_USART3 clock configuration register */\r
+ __I uint32_t CLK_APB2_USART3_STAT; /*!< (@ 0x40052204) CLK_APB2_USART3 clock status register */\r
+ __I uint32_t RESERVED2[62];\r
+ __IO uint32_t CLK_APB2_USART2_CFG; /*!< (@ 0x40052300) CLK_APB2_USART2 clock configuration register */\r
+ __I uint32_t CLK_APB2_USART2_STAT; /*!< (@ 0x40052304) CLK_APB2_USART clock status register */\r
+ __I uint32_t RESERVED3[62];\r
+ __IO uint32_t CLK_APB0_UART1_CFG; /*!< (@ 0x40052400) CLK_APB2_UART1 clock configuration register */\r
+ __I uint32_t CLK_APB0_UART1_STAT; /*!< (@ 0x40052404) CLK_APB0_UART1 clock status register */\r
+ __I uint32_t RESERVED4[62];\r
+ __IO uint32_t CLK_APB0_USART0_CFG; /*!< (@ 0x40052500) CLK_APB2_USART0 clock configuration register */\r
+ __I uint32_t CLK_APB0_USART0_STAT; /*!< (@ 0x40052504) CLK_APB0_USART0 clock status register */\r
+ __I uint32_t RESERVED5[62];\r
+ __IO uint32_t CLK_APB2_SSP1_CFG; /*!< (@ 0x40052600) CLK_APB2_SSP1 clock configuration register */\r
+ __I uint32_t CLK_APB2_SSP1_STAT; /*!< (@ 0x40052604) CLK_APB2_SSP1 clock status register */\r
+ __I uint32_t RESERVED6[62];\r
+ __IO uint32_t CLK_APB0_SSP0_CFG; /*!< (@ 0x40052700) CLK_APB0_SSP0 clock configuration register */\r
+ __I uint32_t CLK_APB0_SSP0_STAT; /*!< (@ 0x40052704) CLK_APB0_SSP0 clock status register */\r
+ __I uint32_t RESERVED7[62];\r
+ __IO uint32_t CLK_SDIO_CFG; /*!< (@ 0x40052800) CLK_SDIO clock configuration register */\r
+ __I uint32_t CLK_SDIO_STAT; /*!< (@ 0x40052804) CLK_SDIO clock status register */\r
+} LPC_CCU2_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- RGU -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx Reset Generation Unit (RGU) Modification date=1/21/2011 Major revision=0 Minor revision=7 (RGU)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40053000) RGU Structure */\r
+ __I uint32_t RESERVED0[64];\r
+ __O uint32_t RESET_CTRL0; /*!< (@ 0x40053100) Reset control register 0 */\r
+ __O uint32_t RESET_CTRL1; /*!< (@ 0x40053104) Reset control register 1 */\r
+ __I uint32_t RESERVED1[2];\r
+ __IO uint32_t RESET_STATUS0; /*!< (@ 0x40053110) Reset status register 0 */\r
+ __IO uint32_t RESET_STATUS1; /*!< (@ 0x40053114) Reset status register 1 */\r
+ __IO uint32_t RESET_STATUS2; /*!< (@ 0x40053118) Reset status register 2 */\r
+ __IO uint32_t RESET_STATUS3; /*!< (@ 0x4005311C) Reset status register 3 */\r
+ __I uint32_t RESERVED2[12];\r
+ __I uint32_t RESET_ACTIVE_STATUS0; /*!< (@ 0x40053150) Reset active status register 0 */\r
+ __I uint32_t RESET_ACTIVE_STATUS1; /*!< (@ 0x40053154) Reset active status register 1 */\r
+ __I uint32_t RESERVED3[170];\r
+ __IO uint32_t RESET_EXT_STAT0; /*!< (@ 0x40053400) Reset external status register 0 for CORE_RST */\r
+ __IO uint32_t RESET_EXT_STAT1; /*!< (@ 0x40053404) Reset external status register 1 for PERIPH_RST */\r
+ __IO uint32_t RESET_EXT_STAT2; /*!< (@ 0x40053408) Reset external status register 2 for MASTER_RST */\r
+ __I uint32_t RESERVED4;\r
+ __IO uint32_t RESET_EXT_STAT4; /*!< (@ 0x40053410) Reset external status register 4 for WWDT_RST */\r
+ __IO uint32_t RESET_EXT_STAT5; /*!< (@ 0x40053414) Reset external status register 5 for CREG_RST */\r
+ __I uint32_t RESERVED5[2];\r
+ __IO uint32_t RESET_EXT_STAT8; /*!< (@ 0x40053420) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT9; /*!< (@ 0x40053424) Reset external status register */\r
+ __I uint32_t RESERVED6[3];\r
+ __IO uint32_t RESET_EXT_STAT13; /*!< (@ 0x40053434) Reset external status register */\r
+ __I uint32_t RESERVED7[2];\r
+ __IO uint32_t RESET_EXT_STAT16; /*!< (@ 0x40053440) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT17; /*!< (@ 0x40053444) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT18; /*!< (@ 0x40053448) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT19; /*!< (@ 0x4005344C) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT20; /*!< (@ 0x40053450) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT21; /*!< (@ 0x40053454) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT22; /*!< (@ 0x40053458) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT23; /*!< (@ 0x4005345C) Reset external status register */\r
+ __I uint32_t RESERVED8[4];\r
+ __IO uint32_t RESET_EXT_STAT28; /*!< (@ 0x40053470) Reset external status register */\r
+ __I uint32_t RESERVED9[3];\r
+ __IO uint32_t RESET_EXT_STAT32; /*!< (@ 0x40053480) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT33; /*!< (@ 0x40053484) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT34; /*!< (@ 0x40053488) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT35; /*!< (@ 0x4005348C) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT36; /*!< (@ 0x40053490) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT37; /*!< (@ 0x40053494) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT38; /*!< (@ 0x40053498) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT39; /*!< (@ 0x4005349C) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT40; /*!< (@ 0x400534A0) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT41; /*!< (@ 0x400534A4) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT42; /*!< (@ 0x400534A8) Reset external status register */\r
+ __I uint32_t RESERVED10;\r
+ __IO uint32_t RESET_EXT_STAT44; /*!< (@ 0x400534B0) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT45; /*!< (@ 0x400534B4) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT46; /*!< (@ 0x400534B8) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT47; /*!< (@ 0x400534BC) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT48; /*!< (@ 0x400534C0) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT49; /*!< (@ 0x400534C4) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT50; /*!< (@ 0x400534C8) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT51; /*!< (@ 0x400534CC) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT52; /*!< (@ 0x400534D0) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT53; /*!< (@ 0x400534D4) Reset external status register */\r
+ __I uint32_t RESERVED11;\r
+ __IO uint32_t RESET_EXT_STAT55; /*!< (@ 0x400534DC) Reset external status register */\r
+ __IO uint32_t RESET_EXT_STAT56; /*!< (@ 0x400534E0) Reset external status register */\r
+} LPC_RGU_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- WWDT -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx Windowed Watchdog timer (WWDT) Modification date=1/14/2011 Major revision=0 Minor revision=7 (WWDT)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40080000) WWDT Structure */\r
+ __IO uint32_t MOD; /*!< (@ 0x40080000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */\r
+ __IO uint32_t TC; /*!< (@ 0x40080004) Watchdog timer constant register. This register determines the time-out value. */\r
+ __O uint32_t FEED; /*!< (@ 0x40080008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */\r
+ __I uint32_t TV; /*!< (@ 0x4008000C) Watchdog timer value register. This register reads out the current value of the Watchdog timer. */\r
+ __I uint32_t RESERVED0;\r
+ __IO uint32_t WARNINT; /*!< (@ 0x40080014) Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */\r
+ __IO uint32_t WINDOW; /*!< (@ 0x40080018) Watchdog timer window register. This register contains the Watchdog window value. */\r
+} LPC_WWDT_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- USARTn -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx USART0_2_3 Modification date=1/14/2011 Major revision=0 Minor revision=7 (USARTn)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x400xx000) USARTn Structure */\r
+\r
+ union {\r
+ __IO uint32_t DLL; /*!< (@ 0x400xx000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */\r
+ __O uint32_t THR; /*!< (@ 0x400xx000) Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */\r
+ __I uint32_t RBR; /*!< (@ 0x400xx000) Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */\r
+ };\r
+\r
+ union {\r
+ __IO uint32_t IER; /*!< (@ 0x400xx004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */\r
+ __IO uint32_t DLM; /*!< (@ 0x400xx004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */\r
+ };\r
+\r
+ union {\r
+ __O uint32_t FCR; /*!< (@ 0x400xx008) FIFO Control Register. Controls UART FIFO usage and modes. */\r
+ __I uint32_t IIR; /*!< (@ 0x400xx008) Interrupt ID Register. Identifies which interrupt(s) are pending. */\r
+ };\r
+ __IO uint32_t LCR; /*!< (@ 0x400xx00C) Line Control Register. Contains controls for frame formatting and break generation. */\r
+ __I uint32_t RESERVED0[1];\r
+ __I uint32_t LSR; /*!< (@ 0x400xx014) Line Status Register. Contains flags for transmit and receive status, including line errors. */\r
+ __I uint32_t RESERVED1[1];\r
+ __IO uint32_t SCR; /*!< (@ 0x400xx01C) Scratch Pad Register. Eight-bit temporary storage for software. */\r
+ __IO uint32_t ACR; /*!< (@ 0x400xx020) Auto-baud Control Register. Contains controls for the auto-baud feature. */\r
+ __IO uint32_t ICR; /*!< (@ 0x400xx024) IrDA control register (UART3 only) */\r
+ __IO uint32_t FDR; /*!< (@ 0x400xx028) Fractional Divider Register. Generates a clock input for the baud rate divider. */\r
+ __I uint32_t RESERVED2[4];\r
+ __IO uint32_t HDEN; /*!< (@ 0x400xx03C) Half-duplex enable Register */\r
+ __I uint32_t RESERVED3[2];\r
+ __IO uint32_t SCICTRL; /*!< (@ 0x400xx048) Smart card interface control register */\r
+ __IO uint32_t RS485CTRL; /*!< (@ 0x400xx04C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */\r
+ __IO uint32_t RS485ADRMATCH; /*!< (@ 0x400xx050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */\r
+ __IO uint32_t RS485DLY; /*!< (@ 0x400xx054) RS-485/EIA-485 direction control delay. */\r
+ __IO uint32_t SYNCCTRL; /*!< (@ 0x400xx058) Synchronous mode control register. */\r
+ __IO uint32_t TER; /*!< (@ 0x400xx05C) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */\r
+} LPC_USARTn_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- UART1 -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx UART1 Modification date=1/14/2011 Major revision=0 Minor revision=7 (UART1)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40082000) UART1 Structure */\r
+\r
+ union {\r
+ __IO uint32_t DLL; /*!< (@ 0x40082000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */\r
+ __O uint32_t THR; /*!< (@ 0x40082000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */\r
+ __I uint32_t RBR; /*!< (@ 0x40082000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */\r
+ };\r
+\r
+ union {\r
+ __IO uint32_t IER; /*!< (@ 0x40082004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0) */\r
+ __IO uint32_t DLM; /*!< (@ 0x40082004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1) */\r
+ };\r
+\r
+ union {\r
+ __O uint32_t FCR; /*!< (@ 0x40082008) FIFO Control Register. Controls UART1 FIFO usage and modes. */\r
+ __I uint32_t IIR; /*!< (@ 0x40082008) Interrupt ID Register. Identifies which interrupt(s) are pending. */\r
+ };\r
+ __IO uint32_t LCR; /*!< (@ 0x4008200C) Line Control Register. Contains controls for frame formatting and break generation. */\r
+ __IO uint32_t MCR; /*!< (@ 0x40082010) Modem Control Register. Contains controls for flow control handshaking and loopback mode. */\r
+ __I uint32_t LSR; /*!< (@ 0x40082014) Line Status Register. Contains flags for transmit and receive status, including line errors. */\r
+ __I uint32_t MSR; /*!< (@ 0x40082018) Modem Status Register. Contains handshake signal status flags. */\r
+ __IO uint32_t SCR; /*!< (@ 0x4008201C) Scratch Pad Register. 8-bit temporary storage for software. */\r
+ __IO uint32_t ACR; /*!< (@ 0x40082020) Auto-baud Control Register. Contains controls for the auto-baud feature. */\r
+ __I uint32_t RESERVED0[1];\r
+ __IO uint32_t FDR; /*!< (@ 0x40082028) Fractional Divider Register. Generates a clock input for the baud rate divider. */\r
+ __I uint32_t RESERVED1[1];\r
+ __IO uint32_t TER; /*!< (@ 0x40082030) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */\r
+ __I uint32_t RESERVED2[6];\r
+ __IO uint32_t RS485CTRL; /*!< (@ 0x4008204C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */\r
+ __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40082050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */\r
+ __IO uint32_t RS485DLY; /*!< (@ 0x40082054) RS-485/EIA-485 direction control delay. */\r
+ __I uint32_t FIFOLVL; /*!< (@ 0x40082058) FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */\r
+} LPC_UART1_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- SSPn -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx SSP0/1 Modification date=1/14/2011 Major revision=0 Minor revision=7 (SSP0)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x400xx000) SSPn Structure */\r
+ __IO uint32_t CR0; /*!< (@ 0x400xx000) Control Register 0. Selects the serial clock rate, bus type, and data size. */\r
+ __IO uint32_t CR1; /*!< (@ 0x400xx004) Control Register 1. Selects master/slave and other modes. */\r
+ __IO uint32_t DR; /*!< (@ 0x400xx008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */\r
+ __I uint32_t SR; /*!< (@ 0x400xx00C) Status Register */\r
+ __IO uint32_t CPSR; /*!< (@ 0x400xx010) Clock Prescale Register */\r
+ __IO uint32_t IMSC; /*!< (@ 0x400xx014) Interrupt Mask Set and Clear Register */\r
+ __I uint32_t RIS; /*!< (@ 0x400xx018) Raw Interrupt Status Register */\r
+ __I uint32_t MIS; /*!< (@ 0x400xx01C) Masked Interrupt Status Register */\r
+ __O uint32_t ICR; /*!< (@ 0x400xx020) SSPICR Interrupt Clear Register */\r
+ __IO uint32_t DMACR; /*!< (@ 0x400xx024) SSPn DMA control register */\r
+} LPC_SSPn_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- TIMERn -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx Timer0/1/2/3 Modification date=1/14/2011 Major revision=0 Minor revision=7 (TIMERn)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x400xx000) TIMERn Structure */\r
+ __IO uint32_t IR; /*!< (@ 0x400xx000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */\r
+ __IO uint32_t TCR; /*!< (@ 0x400xx004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */\r
+ __IO uint32_t TC; /*!< (@ 0x400xx008) Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */\r
+ __IO uint32_t PR; /*!< (@ 0x400xx00C) Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */\r
+ __IO uint32_t PC; /*!< (@ 0x400xx010) Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */\r
+ __IO uint32_t MCR; /*!< (@ 0x400xx014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */\r
+ __IO uint32_t MR[4]; /*!< (@ 0x400xx018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */\r
+ __IO uint32_t CCR; /*!< (@ 0x400xx028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */\r
+ __IO uint32_t CR[4]; /*!< (@ 0x400xx02C) Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */\r
+ __IO uint32_t EMR; /*!< (@ 0x400xx03C) External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */\r
+ __I uint32_t RESERVED0[12];\r
+ __IO uint32_t CTCR; /*!< (@ 0x400xx070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */\r
+} LPC_TIMERn_Type;\r
+\r
+\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- SCU -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx System Control Unit (SCU) Modification date=6/8/2011 Major revision=0 Minor revision=10 (SCU)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40086000) SCU Structure */\r
+ __IO uint32_t SFSP0_0; /*!< (@ 0x40086000) Pin configuration register for pins P0 */\r
+ __IO uint32_t SFSP0_1; /*!< (@ 0x40086004) Pin configuration register for pins P0 */\r
+ __I uint32_t RESERVED0[30];\r
+ __IO uint32_t SFSP1_0; /*!< (@ 0x40086080) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_1; /*!< (@ 0x40086084) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_2; /*!< (@ 0x40086088) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_3; /*!< (@ 0x4008608C) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_4; /*!< (@ 0x40086090) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_5; /*!< (@ 0x40086094) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_6; /*!< (@ 0x40086098) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_7; /*!< (@ 0x4008609C) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_8; /*!< (@ 0x400860A0) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_9; /*!< (@ 0x400860A4) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_10; /*!< (@ 0x400860A8) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_11; /*!< (@ 0x400860AC) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_12; /*!< (@ 0x400860B0) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_13; /*!< (@ 0x400860B4) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_14; /*!< (@ 0x400860B8) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_15; /*!< (@ 0x400860BC) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_16; /*!< (@ 0x400860C0) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_17; /*!< (@ 0x400860C4) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_18; /*!< (@ 0x400860C8) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_19; /*!< (@ 0x400860CC) Pin configuration register for pins P1 */\r
+ __IO uint32_t SFSP1_20; /*!< (@ 0x400860D0) Pin configuration register for pins P1 */\r
+ __I uint32_t RESERVED1[11];\r
+ __IO uint32_t SFSP2_0; /*!< (@ 0x40086100) Pin configuration register for pins P2 */\r
+ __IO uint32_t SFSP2_1; /*!< (@ 0x40086104) Pin configuration register for pins P2 */\r
+ __IO uint32_t SFSP2_2; /*!< (@ 0x40086108) Pin configuration register for pins P2 */\r
+ __IO uint32_t SFSP2_3; /*!< (@ 0x4008610C) Pin configuration register for pins P2 */\r
+ __IO uint32_t SFSP2_4; /*!< (@ 0x40086110) Pin configuration register for pins P2 */\r
+ __IO uint32_t SFSP2_5; /*!< (@ 0x40086114) Pin configuration register for pins P2 */\r
+ __IO uint32_t SFSP2_6; /*!< (@ 0x40086118) Pin configuration register for pins P2 */\r
+ __IO uint32_t SFSP2_7; /*!< (@ 0x4008611C) Pin configuration register for pins P2 */\r
+ __IO uint32_t SFSP2_8; /*!< (@ 0x40086120) Pin configuration register for pins P2 */\r
+ __IO uint32_t SFSP2_9; /*!< (@ 0x40086124) Pin configuration register for pins P2 */\r
+ __IO uint32_t SFSP2_10; /*!< (@ 0x40086128) Pin configuration register for pins P2 */\r
+ __IO uint32_t SFSP2_11; /*!< (@ 0x4008612C) Pin configuration register for pins P2 */\r
+ __IO uint32_t SFSP2_12; /*!< (@ 0x40086130) Pin configuration register for pins P2 */\r
+ __IO uint32_t SFSP2_13; /*!< (@ 0x40086134) Pin configuration register for pins P2 */\r
+ __I uint32_t RESERVED2[18];\r
+ __IO uint32_t SFSP3_0; /*!< (@ 0x40086180) Pin configuration register for pins P3 */\r
+ __IO uint32_t SFSP3_1; /*!< (@ 0x40086184) Pin configuration register for pins P3 */\r
+ __IO uint32_t SFSP3_2; /*!< (@ 0x40086188) Pin configuration register for pins P3 */\r
+ __IO uint32_t SFSP3_3; /*!< (@ 0x4008618C) Pin configuration register for pins P3 */\r
+ __IO uint32_t SFSP3_4; /*!< (@ 0x40086190) Pin configuration register for pins P3 */\r
+ __IO uint32_t SFSP3_5; /*!< (@ 0x40086194) Pin configuration register for pins P3 */\r
+ __IO uint32_t SFSP3_6; /*!< (@ 0x40086198) Pin configuration register for pins P3 */\r
+ __IO uint32_t SFSP3_7; /*!< (@ 0x4008619C) Pin configuration register for pins P3 */\r
+ __IO uint32_t SFSP3_8; /*!< (@ 0x400861A0) Pin configuration register for pins P3 */\r
+ __I uint32_t RESERVED3[23];\r
+ __IO uint32_t SFSP4_0; /*!< (@ 0x40086200) Pin configuration register for pins P4 */\r
+ __IO uint32_t SFSP4_1; /*!< (@ 0x40086204) Pin configuration register for pins P4 */\r
+ __IO uint32_t SFSP4_2; /*!< (@ 0x40086208) Pin configuration register for pins P4 */\r
+ __IO uint32_t SFSP4_3; /*!< (@ 0x4008620C) Pin configuration register for pins P4 */\r
+ __IO uint32_t SFSP4_4; /*!< (@ 0x40086210) Pin configuration register for pins P4 */\r
+ __IO uint32_t SFSP4_5; /*!< (@ 0x40086214) Pin configuration register for pins P4 */\r
+ __IO uint32_t SFSP4_6; /*!< (@ 0x40086218) Pin configuration register for pins P4 */\r
+ __IO uint32_t SFSP4_7; /*!< (@ 0x4008621C) Pin configuration register for pins P4 */\r
+ __IO uint32_t SFSP4_8; /*!< (@ 0x40086220) Pin configuration register for pins P4 */\r
+ __IO uint32_t SFSP4_9; /*!< (@ 0x40086224) Pin configuration register for pins P4 */\r
+ __IO uint32_t SFSP4_10; /*!< (@ 0x40086228) Pin configuration register for pins P4 */\r
+ __I uint32_t RESERVED4[21];\r
+ __IO uint32_t SFSP5_0; /*!< (@ 0x40086280) Pin configuration register for pins P5 */\r
+ __IO uint32_t SFSP5_1; /*!< (@ 0x40086284) Pin configuration register for pins P5 */\r
+ __IO uint32_t SFSP5_2; /*!< (@ 0x40086288) Pin configuration register for pins P5 */\r
+ __IO uint32_t SFSP5_3; /*!< (@ 0x4008628C) Pin configuration register for pins P5 */\r
+ __IO uint32_t SFSP5_4; /*!< (@ 0x40086290) Pin configuration register for pins P5 */\r
+ __IO uint32_t SFSP5_5; /*!< (@ 0x40086294) Pin configuration register for pins P5 */\r
+ __IO uint32_t SFSP5_6; /*!< (@ 0x40086298) Pin configuration register for pins P5 */\r
+ __IO uint32_t SFSP5_7; /*!< (@ 0x4008629C) Pin configuration register for pins P5 */\r
+ __I uint32_t RESERVED5[24];\r
+ __IO uint32_t SFSP6_0; /*!< (@ 0x40086300) Pin configuration register for pins P6 */\r
+ __IO uint32_t SFSP6_1; /*!< (@ 0x40086304) Pin configuration register for pins P6 */\r
+ __IO uint32_t SFSP6_2; /*!< (@ 0x40086308) Pin configuration register for pins P6 */\r
+ __IO uint32_t SFSP6_3; /*!< (@ 0x4008630C) Pin configuration register for pins P6 */\r
+ __IO uint32_t SFSP6_4; /*!< (@ 0x40086310) Pin configuration register for pins P6 */\r
+ __IO uint32_t SFSP6_5; /*!< (@ 0x40086314) Pin configuration register for pins P6 */\r
+ __IO uint32_t SFSP6_6; /*!< (@ 0x40086318) Pin configuration register for pins P6 */\r
+ __IO uint32_t SFSP6_7; /*!< (@ 0x4008631C) Pin configuration register for pins P6 */\r
+ __IO uint32_t SFSP6_8; /*!< (@ 0x40086320) Pin configuration register for pins P6 */\r
+ __IO uint32_t SFSP6_9; /*!< (@ 0x40086324) Pin configuration register for pins P6 */\r
+ __IO uint32_t SFSP6_10; /*!< (@ 0x40086328) Pin configuration register for pins P6 */\r
+ __IO uint32_t SFSP6_11; /*!< (@ 0x4008632C) Pin configuration register for pins P6 */\r
+ __IO uint32_t SFSP6_12; /*!< (@ 0x40086330) Pin configuration register for pins P6 */\r
+ __I uint32_t RESERVED6[19];\r
+ __IO uint32_t SFSP7_0; /*!< (@ 0x40086380) Pin configuration register for pins P7 */\r
+ __IO uint32_t SFSP7_1; /*!< (@ 0x40086384) Pin configuration register for pins P7 */\r
+ __IO uint32_t SFSP7_2; /*!< (@ 0x40086388) Pin configuration register for pins P7 */\r
+ __IO uint32_t SFSP7_3; /*!< (@ 0x4008638C) Pin configuration register for pins P7 */\r
+ __IO uint32_t SFSP7_4; /*!< (@ 0x40086390) Pin configuration register for pins P7 */\r
+ __IO uint32_t SFSP7_5; /*!< (@ 0x40086394) Pin configuration register for pins P7 */\r
+ __IO uint32_t SFSP7_6; /*!< (@ 0x40086398) Pin configuration register for pins P7 */\r
+ __IO uint32_t SFSP7_7; /*!< (@ 0x4008639C) Pin configuration register for pins P7 */\r
+ __I uint32_t RESERVED7[24];\r
+ __IO uint32_t SFSP8_0; /*!< (@ 0x40086400) Pin configuration register for pins P8 */\r
+ __IO uint32_t SFSP8_1; /*!< (@ 0x40086404) Pin configuration register for pins P8 */\r
+ __IO uint32_t SFSP8_2; /*!< (@ 0x40086408) Pin configuration register for pins P8 */\r
+ __IO uint32_t SFSP8_3; /*!< (@ 0x4008640C) Pin configuration register for pins P8 */\r
+ __IO uint32_t SFSP8_4; /*!< (@ 0x40086410) Pin configuration register for pins P8 */\r
+ __IO uint32_t SFSP8_5; /*!< (@ 0x40086414) Pin configuration register for pins P8 */\r
+ __IO uint32_t SFSP8_6; /*!< (@ 0x40086418) Pin configuration register for pins P8 */\r
+ __IO uint32_t SFSP8_7; /*!< (@ 0x4008641C) Pin configuration register for pins P8 */\r
+ __IO uint32_t SFSP8_8; /*!< (@ 0x40086420) Pin configuration register for pins P8 */\r
+ __I uint32_t RESERVED8[23];\r
+ __IO uint32_t SFSP9_0; /*!< (@ 0x40086480) Pin configuration register for pins P9 */\r
+ __IO uint32_t SFSP9_1; /*!< (@ 0x40086484) Pin configuration register for pins P9 */\r
+ __IO uint32_t SFSP9_2; /*!< (@ 0x40086488) Pin configuration register for pins P9 */\r
+ __IO uint32_t SFSP9_3; /*!< (@ 0x4008648C) Pin configuration register for pins P9 */\r
+ __IO uint32_t SFSP9_4; /*!< (@ 0x40086490) Pin configuration register for pins P9 */\r
+ __IO uint32_t SFSP9_5; /*!< (@ 0x40086494) Pin configuration register for pins P9 */\r
+ __IO uint32_t SFSP9_6; /*!< (@ 0x40086498) Pin configuration register for pins P9 */\r
+ __I uint32_t RESERVED9[25];\r
+ __IO uint32_t SFSPA_0; /*!< (@ 0x40086500) Pin configuration register for pins PA */\r
+ __IO uint32_t SFSPA_1; /*!< (@ 0x40086504) Pin configuration register for pins PA */\r
+ __IO uint32_t SFSPA_2; /*!< (@ 0x40086508) Pin configuration register for pins PA */\r
+ __IO uint32_t SFSPA_3; /*!< (@ 0x4008650C) Pin configuration register for pins PA */\r
+ __IO uint32_t SFSPA_4; /*!< (@ 0x40086510) Pin configuration register for pins PA */\r
+ __I uint32_t RESERVED10[27];\r
+ __IO uint32_t SFSPB_0; /*!< (@ 0x40086580) Pin configuration register for pins PB */\r
+ __IO uint32_t SFSPB_1; /*!< (@ 0x40086584) Pin configuration register for pins PB */\r
+ __IO uint32_t SFSPB_2; /*!< (@ 0x40086588) Pin configuration register for pins PB */\r
+ __IO uint32_t SFSPB_3; /*!< (@ 0x4008658C) Pin configuration register for pins PB */\r
+ __IO uint32_t SFSPB_4; /*!< (@ 0x40086590) Pin configuration register for pins PB */\r
+ __IO uint32_t SFSPB_5; /*!< (@ 0x40086594) Pin configuration register for pins PB */\r
+ __IO uint32_t SFSPB_6; /*!< (@ 0x40086598) Pin configuration register for pins PB */\r
+ __I uint32_t RESERVED11[25];\r
+ __IO uint32_t SFSPC_0; /*!< (@ 0x40086600) Pin configuration register for pins PC */\r
+ __IO uint32_t SFSPC_1; /*!< (@ 0x40086604) Pin configuration register for pins PC */\r
+ __IO uint32_t SFSPC_2; /*!< (@ 0x40086608) Pin configuration register for pins PC */\r
+ __IO uint32_t SFSPC_3; /*!< (@ 0x4008660C) Pin configuration register for pins PC */\r
+ __IO uint32_t SFSPC_4; /*!< (@ 0x40086610) Pin configuration register for pins PC */\r
+ __IO uint32_t SFSPC_5; /*!< (@ 0x40086614) Pin configuration register for pins PC */\r
+ __IO uint32_t SFSPC_6; /*!< (@ 0x40086618) Pin configuration register for pins PC */\r
+ __IO uint32_t SFSPC_7; /*!< (@ 0x4008661C) Pin configuration register for pins PC */\r
+ __IO uint32_t SFSPC_8; /*!< (@ 0x40086620) Pin configuration register for pins PC */\r
+ __IO uint32_t SFSPC_9; /*!< (@ 0x40086624) Pin configuration register for pins PC */\r
+ __IO uint32_t SFSPC_10; /*!< (@ 0x40086628) Pin configuration register for pins PC */\r
+ __IO uint32_t SFSPC_11; /*!< (@ 0x4008662C) Pin configuration register for pins PC */\r
+ __IO uint32_t SFSPC_12; /*!< (@ 0x40086630) Pin configuration register for pins PC */\r
+ __IO uint32_t SFSPC_13; /*!< (@ 0x40086634) Pin configuration register for pins PC */\r
+ __IO uint32_t SFSPC_14; /*!< (@ 0x40086638) Pin configuration register for pins PC */\r
+ __I uint32_t RESERVED12[17];\r
+ __IO uint32_t SFSPD_0; /*!< (@ 0x40086680) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_1; /*!< (@ 0x40086684) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_2; /*!< (@ 0x40086688) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_3; /*!< (@ 0x4008668C) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_4; /*!< (@ 0x40086690) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_5; /*!< (@ 0x40086694) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_6; /*!< (@ 0x40086698) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_7; /*!< (@ 0x4008669C) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_8; /*!< (@ 0x400866A0) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_9; /*!< (@ 0x400866A4) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_10; /*!< (@ 0x400866A8) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_11; /*!< (@ 0x400866AC) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_12; /*!< (@ 0x400866B0) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_13; /*!< (@ 0x400866B4) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_14; /*!< (@ 0x400866B8) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_15; /*!< (@ 0x400866BC) Pin configuration register for pins PD */\r
+ __IO uint32_t SFSPD_16; /*!< (@ 0x400866C0) Pin configuration register for pins PD */\r
+ __I uint32_t RESERVED13[15];\r
+ __IO uint32_t SFSPE_0; /*!< (@ 0x40086700) Pin configuration register for pins PE */\r
+ __IO uint32_t SFSPE_1; /*!< (@ 0x40086704) Pin configuration register for pins PE */\r
+ __IO uint32_t SFSPE_2; /*!< (@ 0x40086708) Pin configuration register for pins PE */\r
+ __IO uint32_t SFSPE_3; /*!< (@ 0x4008670C) Pin configuration register for pins PE */\r
+ __IO uint32_t SFSPE_4; /*!< (@ 0x40086710) Pin configuration register for pins PE */\r
+ __IO uint32_t SFSPE_5; /*!< (@ 0x40086714) Pin configuration register for pins PE */\r
+ __IO uint32_t SFSPE_6; /*!< (@ 0x40086718) Pin configuration register for pins PE */\r
+ __IO uint32_t SFSPE_7; /*!< (@ 0x4008671C) Pin configuration register for pins PE */\r
+ __IO uint32_t SFSPE_8; /*!< (@ 0x40086720) Pin configuration register for pins PE */\r
+ __IO uint32_t SFSPE_9; /*!< (@ 0x40086724) Pin configuration register for pins PE */\r
+ __IO uint32_t SFSPE_10; /*!< (@ 0x40086728) Pin configuration register for pins PE */\r
+ __IO uint32_t SFSPE_11; /*!< (@ 0x4008672C) Pin configuration register for pins PE */\r
+ __IO uint32_t SFSPE_12; /*!< (@ 0x40086730) Pin configuration register for pins PE */\r
+ __IO uint32_t SFSPE_13; /*!< (@ 0x40086734) Pin configuration register for pins PE */\r
+ __IO uint32_t SFSPE_14; /*!< (@ 0x40086738) Pin configuration register for pins PE */\r
+ __IO uint32_t SFSPE_15; /*!< (@ 0x4008673C) Pin configuration register for pins PE */\r
+ __I uint32_t RESERVED14[16];\r
+ __IO uint32_t SFSPF_0; /*!< (@ 0x40086780) Pin configuration register for pins PF */\r
+ __IO uint32_t SFSPF_1; /*!< (@ 0x40086784) Pin configuration register for pins PF */\r
+ __IO uint32_t SFSPF_2; /*!< (@ 0x40086788) Pin configuration register for pins PF */\r
+ __IO uint32_t SFSPF_3; /*!< (@ 0x4008678C) Pin configuration register for pins PF */\r
+ __IO uint32_t SFSPF_4; /*!< (@ 0x40086790) Pin configuration register for pins PF */\r
+ __IO uint32_t SFSPF_5; /*!< (@ 0x40086794) Pin configuration register for pins PF */\r
+ __IO uint32_t SFSPF_6; /*!< (@ 0x40086798) Pin configuration register for pins PF */\r
+ __IO uint32_t SFSPF_7; /*!< (@ 0x4008679C) Pin configuration register for pins PF */\r
+ __IO uint32_t SFSPF_8; /*!< (@ 0x400867A0) Pin configuration register for pins PF */\r
+ __IO uint32_t SFSPF_9; /*!< (@ 0x400867A4) Pin configuration register for pins PF */\r
+ __IO uint32_t SFSPF_10; /*!< (@ 0x400867A8) Pin configuration register for pins PF */\r
+ __IO uint32_t SFSPF_11; /*!< (@ 0x400867AC) Pin configuration register for pins PF */\r
+ __I uint32_t RESERVED15[276];\r
+ __IO uint32_t SFSCLK_0; /*!< (@ 0x40086C00) Pin configuration register for pin CLK0 */\r
+ __IO uint32_t SFSCLK_1; /*!< (@ 0x40086C04) Pin configuration register for pin CLK1 */\r
+ __IO uint32_t SFSCLK_2; /*!< (@ 0x40086C08) Pin configuration register for pin CLK2 */\r
+ __IO uint32_t SFSCLK_3; /*!< (@ 0x40086C0C) Pin configuration register for pin CLK3 */\r
+ __I uint32_t RESERVED16[28];\r
+ __IO uint32_t SFSUSB; /*!< (@ 0x40086C80) Pin configuration register for */\r
+ __IO uint32_t SFSI2C0; /*!< (@ 0x40086C84) Pin configuration register for I 2C0-bus pins */\r
+ __IO uint32_t ENAIO0; /*!< (@ 0x40086C88) ADC0 function select register */\r
+ __IO uint32_t ENAIO1; /*!< (@ 0x40086C8C) ADC1 function select register */\r
+ __IO uint32_t ENAIO2; /*!< (@ 0x40086C90) Analog function select register */\r
+ __I uint32_t RESERVED17[27];\r
+ __IO uint32_t EMCCLKDELAY; /*!< (@ 0x40086D00) EMC clock delay register */\r
+ __IO uint32_t EMCCTRLDELAY; /*!< (@ 0x40086D04) EMC control delay register */\r
+ __IO uint32_t EMCCSDELAY; /*!< (@ 0x40086D08) EMC chip select delay register */\r
+ __IO uint32_t EMCDOUTDELAY; /*!< (@ 0x40086D0C) EMC data out delay register */\r
+ __IO uint32_t EMCFBCLKDELAY; /*!< (@ 0x40086D10) EMC FBCLK delay register */\r
+ __IO uint32_t EMCADDRDELAY0; /*!< (@ 0x40086D14) EMC address line delay register 0 */\r
+ __IO uint32_t EMCADDRDELAY1; /*!< (@ 0x40086D18) EMC address line delay register 1 */\r
+ __IO uint32_t EMCADDRDELAY2; /*!< (@ 0x40086D1C) EMC address line delay register 2 */\r
+ __I uint32_t RESERVED18;\r
+ __IO uint32_t EMCDINDELAY; /*!< (@ 0x40086D24) EMC data delay register */\r
+ __I uint32_t RESERVED19[54];\r
+ __IO uint32_t PINTSEL0; /*!< (@ 0x40086E00) Pin interrupt select register for pin interrupts 0 to 3. */\r
+ __IO uint32_t PINTSEL1; /*!< (@ 0x40086E04) Pin interrupt select register for pin interrupts 4 to 7. */\r
+} LPC_SCU_Type;\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- MCPWM -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx Motor Control PWM (MOTOCONPWM) Modification date=1/14/2011 Major revision=0 Minor revision=7 (MCPWM)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x400A0000) MCPWM Structure */\r
+ __I uint32_t CON; /*!< (@ 0x400A0000) PWM Control read address */\r
+ __O uint32_t CON_SET; /*!< (@ 0x400A0004) PWM Control set address */\r
+ __O uint32_t CON_CLR; /*!< (@ 0x400A0008) PWM Control clear address */\r
+ __I uint32_t CAPCON; /*!< (@ 0x400A000C) Capture Control read address */\r
+ __O uint32_t CAPCON_SET; /*!< (@ 0x400A0010) Capture Control set address */\r
+ __O uint32_t CAPCON_CLR; /*!< (@ 0x400A0014) Event Control clear address */\r
+ __IO uint32_t TC[3]; /*!< (@ 0x400A0018) Timer Counter register */\r
+ __IO uint32_t LIM[3]; /*!< (@ 0x400A0024) Limit register */\r
+ __IO uint32_t MAT[3]; /*!< (@ 0x400A0030) Match register */\r
+ __IO uint32_t DT; /*!< (@ 0x400A003C) Dead time register */\r
+ __IO uint32_t CCP; /*!< (@ 0x400A0040) Communication Pattern register */\r
+ __I uint32_t CAP[3]; /*!< (@ 0x400A0044) Capture register */\r
+ __I uint32_t INTEN; /*!< (@ 0x400A0050) Interrupt Enable read address */\r
+ __O uint32_t INTEN_SET; /*!< (@ 0x400A0054) Interrupt Enable set address */\r
+ __O uint32_t INTEN_CLR; /*!< (@ 0x400A0058) Interrupt Enable clear address */\r
+ __I uint32_t CNTCON; /*!< (@ 0x400A005C) Count Control read address */\r
+ __O uint32_t CNTCON_SET; /*!< (@ 0x400A0060) Count Control set address */\r
+ __O uint32_t CNTCON_CLR; /*!< (@ 0x400A0064) Count Control clear address */\r
+ __I uint32_t INTF; /*!< (@ 0x400A0068) Interrupt flags read address */\r
+ __O uint32_t INTF_SET; /*!< (@ 0x400A006C) Interrupt flags set address */\r
+ __O uint32_t INTF_CLR; /*!< (@ 0x400A0070) Interrupt flags clear address */\r
+ __O uint32_t CAP_CLR; /*!< (@ 0x400A0074) Capture clear address */\r
+} LPC_MCPWM_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- I2Cn -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx I2C0/1-bus interface Modification date=1/14/2011 Major revision=0 Minor revision=7 (I2Cn)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x400xx000) I2C0 Structure */\r
+ __IO uint32_t CONSET; /*!< (@ 0x400xx000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */\r
+ __I uint32_t STAT; /*!< (@ 0x400xx004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */\r
+ __IO uint32_t DAT; /*!< (@ 0x400xx008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */\r
+ __IO uint32_t ADR0; /*!< (@ 0x400xx00C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */\r
+ __IO uint32_t SCLH; /*!< (@ 0x400xx010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */\r
+ __IO uint32_t SCLL; /*!< (@ 0x400xx014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */\r
+ __O uint32_t CONCLR; /*!< (@ 0x400xx018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */\r
+ __IO uint32_t MMCTRL; /*!< (@ 0x400xx01C) Monitor mode control register. */\r
+ __IO uint32_t ADR1; /*!< (@ 0x400xx020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */\r
+ __IO uint32_t ADR2; /*!< (@ 0x400xx024) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */\r
+ __IO uint32_t ADR3; /*!< (@ 0x400xx028) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */\r
+ __I uint32_t DATA_BUFFER; /*!< (@ 0x400xx02C) Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */\r
+ __IO uint32_t MASK[4]; /*!< (@ 0x400xx030) I2C Slave address mask register */\r
+} LPC_I2Cn_Type;\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- I2Sn -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx I2S interface Modification date=1/14/2011 Major revision=0 Minor revision=7 (I2Sn)\r
+ 0x400A2000 / 0x400A3000\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x400Ax000) I2S Structure */\r
+ __IO uint32_t DAO; /*!< (@ 0x400Ax000) I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. */\r
+ __IO uint32_t DAI; /*!< (@ 0x400Ax004) I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. */\r
+ __O uint32_t TXFIFO; /*!< (@ 0x400Ax008) I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. */\r
+ __I uint32_t RXFIFO; /*!< (@ 0x400Ax00C) I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. */\r
+ __I uint32_t STATE; /*!< (@ 0x400Ax010) I2S Status Feedback Register. Contains status information about the I2S interface. */\r
+ __IO uint32_t DMA1; /*!< (@ 0x400Ax014) I2S DMA Configuration Register 1. Contains control information for DMA request 1. */\r
+ __IO uint32_t DMA2; /*!< (@ 0x400Ax018) I2S DMA Configuration Register 2. Contains control information for DMA request 2. */\r
+ __IO uint32_t IRQ; /*!< (@ 0x400Ax01C) I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. */\r
+ __IO uint32_t TXRATE; /*!< (@ 0x400Ax020) I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */\r
+ __IO uint32_t RXRATE; /*!< (@ 0x400Ax024) I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */\r
+ __IO uint32_t TXBITRATE; /*!< (@ 0x400Ax028) I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. */\r
+ __IO uint32_t RXBITRATE; /*!< (@ 0x400Ax02C) I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. */\r
+ __IO uint32_t TXMODE; /*!< (@ 0x400Ax030) I2S Transmit mode control. */\r
+ __IO uint32_t RXMODE; /*!< (@ 0x400Ax034) I2S Receive mode control. */\r
+} LPC_I2Sn_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- RITIMER -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx Repetitive Interrupt Timer (RIT) Modification date=1/14/2011 Major revision=0 Minor revision=7 (RITIMER)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x400C0000) RITIMER Structure */\r
+ __IO uint32_t COMPVAL; /*!< (@ 0x400C0000) Compare register */\r
+ __IO uint32_t MASK; /*!< (@ 0x400C0004) Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */\r
+ __IO uint32_t CTRL; /*!< (@ 0x400C0008) Control register. */\r
+ __IO uint32_t COUNTER; /*!< (@ 0x400C000C) 32-bit counter */\r
+} LPC_RITIMER_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- QEI -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx Quadrature Encoder Interface (QEI) Modification date=1/18/2011 Major revision=0 Minor revision=7 (QEI)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x400C6000) QEI Structure */\r
+ __O uint32_t CON; /*!< (@ 0x400C6000) Control register */\r
+ __I uint32_t STAT; /*!< (@ 0x400C6004) Encoder status register */\r
+ __IO uint32_t CONF; /*!< (@ 0x400C6008) Configuration register */\r
+ __I uint32_t POS; /*!< (@ 0x400C600C) Position register */\r
+ __IO uint32_t MAXPOS; /*!< (@ 0x400C6010) Maximum position register */\r
+ __IO uint32_t CMPOS0; /*!< (@ 0x400C6014) position compare register 0 */\r
+ __IO uint32_t CMPOS1; /*!< (@ 0x400C6018) position compare register 1 */\r
+ __IO uint32_t CMPOS2; /*!< (@ 0x400C601C) position compare register 2 */\r
+ __I uint32_t INXCNT; /*!< (@ 0x400C6020) Index count register */\r
+ __IO uint32_t INXCMP0; /*!< (@ 0x400C6024) Index compare register 0 */\r
+ __IO uint32_t LOAD; /*!< (@ 0x400C6028) Velocity timer reload register */\r
+ __I uint32_t TIME; /*!< (@ 0x400C602C) Velocity timer register */\r
+ __I uint32_t VEL; /*!< (@ 0x400C6030) Velocity counter register */\r
+ __I uint32_t CAP; /*!< (@ 0x400C6034) Velocity capture register */\r
+ __IO uint32_t VELCOMP; /*!< (@ 0x400C6038) Velocity compare register */\r
+ __IO uint32_t FILTERPHA; /*!< (@ 0x400C603C) Digital filter register on input phase A (QEI_A) */\r
+ __IO uint32_t FILTERPHB; /*!< (@ 0x400C6040) Digital filter register on input phase B (QEI_B) */\r
+ __IO uint32_t FILTERINX; /*!< (@ 0x400C6044) Digital filter register on input index (QEI_IDX) */\r
+ __IO uint32_t WINDOW; /*!< (@ 0x400C6048) Index acceptance window register */\r
+ __IO uint32_t INXCMP1; /*!< (@ 0x400C604C) Index compare register 1 */\r
+ __IO uint32_t INXCMP2; /*!< (@ 0x400C6050) Index compare register 2 */\r
+ __I uint32_t RESERVED0[993];\r
+ __O uint32_t IEC; /*!< (@ 0x400C6FD8) Interrupt enable clear register */\r
+ __O uint32_t IES; /*!< (@ 0x400C6FDC) Interrupt enable set register */\r
+ __I uint32_t INTSTAT; /*!< (@ 0x400C6FE0) Interrupt status register */\r
+ __I uint32_t IE; /*!< (@ 0x400C6FE4) Interrupt enable register */\r
+ __O uint32_t CLR; /*!< (@ 0x400C6FE8) Interrupt status clear register */\r
+ __O uint32_t SET; /*!< (@ 0x400C6FEC) Interrupt status set register */\r
+} LPC_QEI_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- GIMA -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=Falcon Chapter title=Global Input Multiplexer Array (GIMA) Modification date=3/25/2011 Major revision=0 Minor revision=4 (GIMA)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x400C7000) GIMA Structure */\r
+ __IO uint32_t CAP0_0_IN; /*!< (@ 0x400C7000) Timer 0 CAP0_0 capture input multiplexer */\r
+ __IO uint32_t CAP0_1_IN; /*!< (@ 0x400C7004) Timer 0 CAP0_1 capture input multiplexer */\r
+ __IO uint32_t CAP0_2_IN; /*!< (@ 0x400C7008) Timer 0 CAP0_2 capture input multiplexer */\r
+ __IO uint32_t CAP0_3_IN; /*!< (@ 0x400C700C) Timer 0 CAP0_3 capture input multiplexer */\r
+ __IO uint32_t CAP1_0_IN; /*!< (@ 0x400C7010) Timer 1 CAP1_0 capture input multiplexer */\r
+ __IO uint32_t CAP1_1_IN; /*!< (@ 0x400C7014) Timer 1 CAP1_1 capture input multiplexer */\r
+ __IO uint32_t CAP1_2_IN; /*!< (@ 0x400C7018) Timer 1 CAP1_2 capture input multiplexer */\r
+ __IO uint32_t CAP1_3_IN; /*!< (@ 0x400C701C) Timer 1 CAP1_3 capture input multiplexer */\r
+ __IO uint32_t CAP2_0_IN; /*!< (@ 0x400C7020) Timer 2 CAP2_0 capture input multiplexer */\r
+ __IO uint32_t CAP2_1_IN; /*!< (@ 0x400C7024) Timer 2 CAP2_1 capture input multiplexer */\r
+ __IO uint32_t CAP2_2_IN; /*!< (@ 0x400C7028) Timer 2 CAP2_2 capture input multiplexer */\r
+ __IO uint32_t CAP2_3_IN; /*!< (@ 0x400C702C) Timer 2 CAP2_3 capture input multiplexer */\r
+ __IO uint32_t CAP3_0_IN; /*!< (@ 0x400C7030) Timer 3 CAP3_0 capture input multiplexer */\r
+ __IO uint32_t CAP3_1_IN; /*!< (@ 0x400C7034) Timer 3 CAP3_1 capture input multiplexer */\r
+ __IO uint32_t CAP3_2_IN; /*!< (@ 0x400C7038) Timer 3 CAP3_2 capture input multiplexer */\r
+ __IO uint32_t CAP3_3_IN; /*!< (@ 0x400C703C) Timer 3 CAP3_3 capture input multiplexer */\r
+ __IO uint32_t CTIN_0_IN; /*!< (@ 0x400C7040) SCT CTIN_0 capture input multiplexer */\r
+ __IO uint32_t CTIN_1_IN; /*!< (@ 0x400C7044) SCT CTIN_1 capture input multiplexer */\r
+ __IO uint32_t CTIN_2_IN; /*!< (@ 0x400C7048) SCT CTIN_2 capture input multiplexer */\r
+ __IO uint32_t CTIN_3_IN; /*!< (@ 0x400C704C) SCT CTIN_3 capture input multiplexer */\r
+ __IO uint32_t CTIN_4_IN; /*!< (@ 0x400C7050) SCT CTIN_4 capture input multiplexer */\r
+ __IO uint32_t CTIN_5_IN; /*!< (@ 0x400C7054) SCT CTIN_5 capture input multiplexer */\r
+ __IO uint32_t CTIN_6_IN; /*!< (@ 0x400C7058) SCT CTIN_6 capture input multiplexer */\r
+ __IO uint32_t CTIN_7_IN; /*!< (@ 0x400C705C) SCT CTIN_7 capture input multiplexer */\r
+ __IO uint32_t VADC_TRIGGER_IN; /*!< (@ 0x400C7060) ADC trigger input multiplexer */\r
+ __IO uint32_t EVENTROUTER_13_IN; /*!< (@ 0x400C7064) Event router input 13 multiplexer */\r
+ __IO uint32_t EVENTROUTER_14_IN; /*!< (@ 0x400C7068) Event router input 14 multiplexer */\r
+ __IO uint32_t EVENTROUTER_16_IN; /*!< (@ 0x400C706C) Event router input 16 multiplexer */\r
+ __IO uint32_t ADCSTART0_IN; /*!< (@ 0x400C7070) ADC start0 input multiplexer */\r
+ __IO uint32_t ADCSTART1_IN; /*!< (@ 0x400C7074) ADC start1 input multiplexer */\r
+} LPC_GIMA_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- DAC -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx DAC Modification date=1/18/2011 Major revision=0 Minor revision=7 (DAC)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x400E1000) DAC Structure */\r
+ __IO uint32_t CR; /*!< (@ 0x400E1000) DAC register. Holds the conversion data. */\r
+ __IO uint32_t CTRL; /*!< (@ 0x400E1004) DAC control register. */\r
+ __IO uint32_t CNTVAL; /*!< (@ 0x400E1008) DAC counter value register. */\r
+} LPC_DAC_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- C_CANn -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx C_CAN Modification date=1/18/2011 Major revision=0 Minor revision=7 (C_CANn)\r
+ 0x400A4000 / 0x400E2000\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x400E2000) C_CAN Structure */\r
+ __IO uint32_t CNTL; /*!< (@ 0x400E2000) CAN control */\r
+ __IO uint32_t STAT; /*!< (@ 0x400E2004) Status register */\r
+ __I uint32_t EC; /*!< (@ 0x400E2008) Error counter */\r
+ __IO uint32_t BT; /*!< (@ 0x400E200C) Bit timing register */\r
+ __I uint32_t INT; /*!< (@ 0x400E2010) Interrupt register */\r
+ __IO uint32_t TEST; /*!< (@ 0x400E2014) Test register */\r
+ __IO uint32_t BRPE; /*!< (@ 0x400E2018) Baud rate prescaler extension register */\r
+ __I uint32_t RESERVED0;\r
+ __IO uint32_t IF1_CMDREQ; /*!< (@ 0x400E2020) Message interface command request */\r
+ \r
+ union {\r
+ __IO uint32_t IF1_CMDMSK_R; /*!< (@ 0x400E2024) Message interface command mask (read direction) */\r
+ __IO uint32_t IF1_CMDMSK_W; /*!< (@ 0x400E2024) Message interface command mask (write direction) */\r
+ };\r
+ __IO uint32_t IF1_MSK1; /*!< (@ 0x400E2028) Message interface mask 1 */\r
+ __IO uint32_t IF1_MSK2; /*!< (@ 0x400E202C) Message interface 1 mask 2 */\r
+ __IO uint32_t IF1_ARB1; /*!< (@ 0x400E2030) Message interface 1 arbitration 1 */\r
+ __IO uint32_t IF1_ARB2; /*!< (@ 0x400E2034) Message interface 1 arbitration 2 */\r
+ __IO uint32_t IF1_MCTRL; /*!< (@ 0x400E2038) Message interface 1 message control */\r
+ __IO uint32_t IF1_DA1; /*!< (@ 0x400E203C) Message interface data A1 */\r
+ __IO uint32_t IF1_DA2; /*!< (@ 0x400E2040) Message interface 1 data A2 */\r
+ __IO uint32_t IF1_DB1; /*!< (@ 0x400E2044) Message interface 1 data B1 */\r
+ __IO uint32_t IF1_DB2; /*!< (@ 0x400E2048) Message interface 1 data B2 */\r
+ __I uint32_t RESERVED1[13];\r
+ __IO uint32_t IF2_CMDREQ; /*!< (@ 0x400E2080) Message interface command request */\r
+\r
+ union {\r
+ __IO uint32_t IF2_CMDMSK_R; /*!< (@ 0x400E2084) Message interface command mask (read direction) */\r
+ __IO uint32_t IF2_CMDMSK_W; /*!< (@ 0x400E2084) Message interface command mask (write direction) */\r
+ };\r
+ __IO uint32_t IF2_MSK1; /*!< (@ 0x400E2088) Message interface mask 1 */\r
+ __IO uint32_t IF2_MSK2; /*!< (@ 0x400E208C) Message interface 1 mask 2 */\r
+ __IO uint32_t IF2_ARB1; /*!< (@ 0x400E2090) Message interface 1 arbitration 1 */\r
+ __IO uint32_t IF2_ARB2; /*!< (@ 0x400E2094) Message interface 1 arbitration 2 */\r
+ __IO uint32_t IF2_MCTRL; /*!< (@ 0x400E2098) Message interface 1 message control */\r
+ __IO uint32_t IF2_DA1; /*!< (@ 0x400E209C) Message interface data A1 */\r
+ __IO uint32_t IF2_DA2; /*!< (@ 0x400E20A0) Message interface 1 data A2 */\r
+ __IO uint32_t IF2_DB1; /*!< (@ 0x400E20A4) Message interface 1 data B1 */\r
+ __IO uint32_t IF2_DB2; /*!< (@ 0x400E20A8) Message interface 1 data B2 */\r
+ __I uint32_t RESERVED6[21];\r
+ __I uint32_t TXREQ1; /*!< (@ 0x400E2100) Transmission request 1 */\r
+ __I uint32_t TXREQ2; /*!< (@ 0x400E2104) Transmission request 2 */\r
+ __I uint32_t RESERVED2[6];\r
+ __I uint32_t ND1; /*!< (@ 0x400E2120) New data 1 */\r
+ __I uint32_t ND2; /*!< (@ 0x400E2124) New data 2 */\r
+ __I uint32_t RESERVED3[6];\r
+ __I uint32_t IR1; /*!< (@ 0x400E2140) Interrupt pending 1 */\r
+ __I uint32_t IR2; /*!< (@ 0x400E2144) Interrupt pending 2 */\r
+ __I uint32_t RESERVED4[6];\r
+ __I uint32_t MSGV1; /*!< (@ 0x400E2160) Message valid 1 */\r
+ __I uint32_t MSGV2; /*!< (@ 0x400E2164) Message valid 2 */\r
+ __I uint32_t RESERVED5[6];\r
+ __IO uint32_t CLKDIV; /*!< (@ 0x400E2180) CAN clock divider register */\r
+} LPC_C_CANn_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- ADCn -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10430 Chapter title=LPC43xx 10-bit ADC0/1 Modification date=1/18/2011 Major revision=0 Minor revision=7 (ADCn)\r
+ 0x400E3000 / 0x400E4000\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x400Ex000) ADCn Structure */\r
+ __IO uint32_t CR; /*!< (@ 0x400Ex000) A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */\r
+ __I uint32_t GDR; /*!< (@ 0x400Ex004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */\r
+ __I uint32_t RESERVED0;\r
+ __IO uint32_t INTEN; /*!< (@ 0x400Ex00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */\r
+ __I uint32_t DR[8]; /*!< (@ 0x400Ex010) A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */\r
+ __I uint32_t STAT; /*!< (@ 0x400Ex030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */\r
+} LPC_ADCn_Type;\r
+\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- Video ADC -----\r
+// ------------------------------------------------------------------------------------------------\r
+/**\r
+ * \r
+ 0x400F0000\r
+ */\r
+\r
+typedef struct { \r
+ __O uint32_t FLUSH; /*!< (@ 0x400F0000) A/D Flush FIFO */\r
+ __IO uint32_t DMA_REQ; /*!< (@ 0x400F0004) A/D DMA request a DMA write to load a descriptor table from memory */\r
+ __I uint32_t FIFO_STS; /*!< (@ 0x400F0008) A/D Full / count / empty status */\r
+ __IO uint32_t FIFO_CFG; /*!< (@ 0x400F000C) A/D FIFO configuration - regular or packed samples */\r
+ __O uint32_t TRIGGER; /*!< (@ 0x400F0010) A/D Trigger to initiate timer and descriptor table processing */\r
+ __IO uint32_t DSCR_STS; /*!< (@ 0x400F0014) A/D Descriptor processing status register */\r
+ __IO uint32_t POWER_DOWN; /*!< (@ 0x400F0018) A/D ADC power down control */\r
+ __IO uint32_t CONFIG; /*!< (@ 0x400F001C) A/D ADC configuration register */\r
+ __IO uint32_t THR_A; /*!< (@ 0x400F0020) A/D Threshold register A */\r
+ __IO uint32_t THR_B; /*!< (@ 0x400F0024) A/D Threshold register B */\r
+ __I uint32_t LAST_SAMPLE[6]; /*!< (@ 0x400F0028 to 0x400F003C) A/D Last sample registers - sample data and results of window comparator */\r
+ __I uint32_t RESERVED0[48]; \r
+ __IO uint32_t ADC_DEBUG; /*!< (@ 0x400F0100) A/D Debug Register*/\r
+ __IO uint32_t ADC_SPEED; /*!< (@ 0x400F0104) A/D Speed setting register */\r
+ __IO uint32_t POWER_CONTROL; /*!< (@ 0x400F0108) A/D Power control register*/\r
+ __I uint32_t RESERVED1[61];\r
+ __I uint32_t FIFO_OUTPUT[16]; /*!< (@ 0x400F0200) A/D FIFO output results */\r
+ __I uint32_t RESERVED2[48];\r
+ __IO uint32_t DESCRIPTOR_0[8]; /*!< (@ 0x400F0300) A/D Descriptor entries table 0 */\r
+ __IO uint32_t DESCRIPTOR_1[8]; /*!< (@ 0x400F0320) A/D Descriptor entries table 1 */\r
+ __I uint32_t RESERVED3[752];\r
+ __O uint32_t CLR_EN0; /*!< (@ 0x400F0F00) A/D Interupt 0 bit mask fields Clear enable */\r
+ __O uint32_t SET_EN0; /*!< (@ 0x400F0F04) A/D Interrupt 0 bit mask fields Set enable */\r
+ __I uint32_t MASK0; /*!< (@ 0x400F0F08) A/D Interrupt 0 enable register */\r
+ __I uint32_t STATUS0; /*!< (@ 0x400F0F0C) A/D Interrtpt 0 status register */\r
+ __O uint32_t CLR_STAT0; /*!< (@ 0x400F0F10) A/D Interrupt 0 Clear Status */\r
+ __O uint32_t SET_STAT0; /*!< (@ 0x400F0F14) A/D Interrupt 0 set status */\r
+ __I uint32_t RESERVED4[2];\r
+ __O uint32_t CLR_EN1; /*!< (@ 0x400F0F20) A/D Interrupt 1 clear mask */\r
+ __O uint32_t SET_EN1; /*!< (@ 0x400F0F24) A/D Interrupt 1 bit mask fields Set enable */\r
+ __I uint32_t MASK1; /*!< (@ 0x400F0F28) A/D Interrupt 1 enable register */\r
+ __I uint32_t STATUS1; /*!< (@ 0x400F0F2C) A/D Interrtpt 1 status register */\r
+ __O uint32_t CLR_STAT1; /*!< (@ 0x400F0F30) A/D Interrupt 1 Clear Status */\r
+ __O uint32_t SET_STAT1; /*!< (@ 0x400F0F34) A/D Interrupt 1 set status */\r
+} LPC_VADC_Type;\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- GPIO_PORT -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief GPIO port (GPIO_PORT)\r
+ Note: it is not a generic gpio but a high speed gpio (hs gpio)!\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x400F4000) GPIO_PORT Structure */\r
+ __IO uint8_t B[256]; /*!< (@ 0x400F4000) Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31 */\r
+ __I uint32_t RESERVED0[960];\r
+ __IO uint32_t W[256]; /*!< (@ 0x400F5000) Word pin registers port 0 to 5 */\r
+ __I uint32_t RESERVED1[768];\r
+ __IO uint32_t DIR[8]; /*!< (@ 0x400F6000) Direction registers port n */\r
+ __I uint32_t RESERVED2[24];\r
+ __IO uint32_t MASK[8]; /*!< (@ 0x400F6080) Mask register port n */\r
+ __I uint32_t RESERVED3[24];\r
+ __IO uint32_t PIN[8]; /*!< (@ 0x400F6100) Portpin register port n */\r
+ __I uint32_t RESERVED4[24];\r
+ __IO uint32_t MPIN[8]; /*!< (@ 0x400F6180) Masked port register port n */\r
+ __I uint32_t RESERVED5[24];\r
+ __IO uint32_t SET[8]; /*!< (@ 0x400F6200) Write: Set register for port n Read: output bits for port n */\r
+ __I uint32_t RESERVED6[24];\r
+ __O uint32_t CLR[8]; /*!< (@ 0x400F6280) Clear port n */\r
+ __I uint32_t RESERVED7[24];\r
+ __O uint32_t NOT[8]; /*!< (@ 0x400F6300) Toggle port n */\r
+} LPC_GPIO_PORT_Type;\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- GPIOn (same as GPIO_PORT, backward compatibility) -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+// Is a backward compatibility for struct members important: DIR/MASK/PIN/SET/CLR??? NOT is new.\r
+\r
+typedef struct {\r
+ __IO uint32_t RESERVED1[2048]; //reserved for Byte pin (PB) and Word pin (PW) registers\r
+ __IO uint32_t DIR; /*!< (@ 0x400F6000) Direction registers port n */\r
+ __IO uint32_t RESERVED2[31]; //reserved for port 1 ..7 (tricky)\r
+ __IO uint32_t MASK; /*!< (@ 0x400F6080) Mask register port n */\r
+ __IO uint32_t RESERVED3[31]; //reserved for port 1 ..7 (tricky)\r
+ __IO uint32_t RESERVED4[32]; //Do not use GPIO port register due to non-masking\r
+ __IO uint32_t PIN; /*!< (@ 0x400F6180) Masked port register port n */\r
+ __IO uint32_t RESERVED5[31]; //reserved for port 1 ..7 (tricky)\r
+ __IO uint32_t SET; /*!< (@ 0x400F6200) Write: Set register for port n Read: output bits for port n */\r
+ __IO uint32_t RESERVED6[31]; //reserved for port 1 ..7 (tricky)\r
+ __O uint32_t CLR; /*!< (@ 0x400F6280) Clear port n */\r
+ __IO uint32_t RESERVED7[31]; //reserved for port 1 ..7 (tricky)\r
+ __O uint32_t NOT; /*!< (@ 0x400F6300) Toggle port n */\r
+ __IO uint32_t RESERVED8[31]; //reserved for port 1 ..7 (tricky)\r
+ //to be expanded\r
+} LPC_GPIOn_Type;\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- GPIO_PIN_INT -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief GPIO pin interrupt (GPIO_PIN_INT)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40087000) GPIO_PIN_INT Structure */\r
+ __IO uint32_t ISEL; /*!< (@ 0x40087000) Pin Interrupt Mode register */\r
+ __IO uint32_t IENR; /*!< (@ 0x40087004) Pin Interrupt Enable (Rising) register */\r
+ __O uint32_t SIENR; /*!< (@ 0x40087008) Set Pin Interrupt Enable (Rising) register */\r
+ __O uint32_t CIENR; /*!< (@ 0x4008700C) Clear Pin Interrupt Enable (Rising) register */\r
+ __IO uint32_t IENF; /*!< (@ 0x40087010) Pin Interrupt Enable Falling Edge / Active Level register */\r
+ __O uint32_t SIENF; /*!< (@ 0x40087014) Set Pin Interrupt Enable Falling Edge / Active Level register */\r
+ __O uint32_t CIENF; /*!< (@ 0x40087018) Clear Pin Interrupt Enable Falling Edge / Active Level address */\r
+ __IO uint32_t RISE; /*!< (@ 0x4008701C) Pin Interrupt Rising Edge register */\r
+ __IO uint32_t FALL; /*!< (@ 0x40087020) Pin Interrupt Falling Edge register */\r
+ __IO uint32_t IST; /*!< (@ 0x40087024) Pin Interrupt Status register */\r
+} LPC_GPIO_PIN_INT_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- GPIO_GROUP_INTn -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief GPIO group interrupt 0/1 (GPIO_GROUP_INTn) \r
+ 0x40088000/0x40089000\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x4008x000) GPIO_GROUP_INT0 Structure */\r
+ __IO uint32_t CTRL; /*!< (@ 0x4008x000) GPIO grouped interrupt control register */\r
+ __I uint32_t RESERVED0[7];\r
+ __IO uint32_t PORT_POL[8]; /*!< (@ 0x4008x020) GPIO grouped interrupt port polarity register */\r
+ __IO uint32_t PORT_ENA[8]; /*!< (@ 0x4008x040) GPIO grouped interrupt port 0/1 enable register */\r
+} LPC_GPIO_GROUP_INTn_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- Random number generation (RNG) -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+typedef struct\r
+{\r
+ __I uint32_t RANDOM_NUMBER; /*!< (@ 0x40054000) Random number */\r
+ __I uint32_t STATISTIC; /*!< (@ 0x40054004) Statistic */\r
+ __IO uint32_t COUNTER_SEL_RNG; /*!< (@ 0x40054008) Select for statistics */\r
+ __I uint32_t RESERVED0[(0xFF4-0x008-0x04)/4];\r
+ __IO uint32_t POWERDOWN; /*!< (@ 0x40054FF4) Powerdown mode */\r
+} LPC_RNG_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- Serial GPIO (SGPIO) -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t OUT_MUX_CFG[16]; /*!< (@ 0x40101000) Pin output multiplexer configuration */\r
+ __IO uint32_t SGPIO_MUX_CFG[16]; /*!< (@ 0x40101040) SGPIO input multiplexer configuration */\r
+ __IO uint32_t SLICE_MUX_CFG[16]; /*!< (@ 0x40101080) Slice multiplexer configuration */\r
+ __IO uint32_t REG[16]; /*!< (@ 0x401010C0) Register */\r
+ __IO uint32_t REG_SS[16]; /*!< (@ 0x40101100) Shadow register */\r
+ __IO uint32_t PRESET[16]; /*!< (@ 0x40101140) Reload value of COUNT0, loaded when COUNT0 reaches 0x0 */\r
+ __IO uint32_t COUNT[16]; /*!< (@ 0x40101180) Down counter, counts down each clock cycle */\r
+ __IO uint32_t POS[16]; /*!< (@ 0x401011C0) Each time COUNT0 reaches 0x0 POS counts down */\r
+ __IO uint32_t MASK_A; /*!< (@ 0x40101200) Mask for pattern match function of slice A */\r
+ __IO uint32_t MASK_H; /*!< (@ 0x40101204) Mask for pattern match function of slice H */\r
+ __IO uint32_t MASK_I; /*!< (@ 0x40101208) Mask for pattern match function of slice I */\r
+ __IO uint32_t MASK_P; /*!< (@ 0x4010120C) Mask for pattern match function of slice P */\r
+ __I uint32_t GPIO_INREG; /*!< (@ 0x40101210) GPIO input status register */\r
+ __IO uint32_t GPIO_OUTREG; /*!< (@ 0x40101214) GPIO output control register */\r
+ __IO uint32_t GPIO_OEREG; /*!< (@ 0x40101218) GPIO OE control register */\r
+ __IO uint32_t CTRL_ENABLE; /*!< (@ 0x4010121C) Enables the slice COUNT counter */\r
+ __IO uint32_t CTRL_DISABLE; /*!< (@ 0x40101220) Disables the slice COUNT counter */\r
+ __I uint32_t RESERVED0[(0xF00-0x220-0x04)/4];\r
+ __IO uint32_t CLR_EN0; /*!< (@ 0x40101F00) Shift clock interrupt clear mask */\r
+ __IO uint32_t SET_EN0; /*!< (@ 0x40101F04) Shift clock interrupt set mask */\r
+ __I uint32_t ENABLE0; /*!< (@ 0x40101F08) Shift clock interrupt enable */\r
+ __I uint32_t STATUS0; /*!< (@ 0x40101F0C) Shift clock interrupt status */\r
+ __IO uint32_t CTR_STAT0; /*!< (@ 0x40101F10) Shift clock interrupt clear status */\r
+ __IO uint32_t SET_STAT0; /*!< (@ 0x40101F14) Shift clock interrupt set status */\r
+ __I uint32_t RESERVED1[2];\r
+ __IO uint32_t CLR_EN1; /*!< (@ 0x40101F20) Capture clock interrupt clear mask */\r
+ __IO uint32_t SET_EN1; /*!< (@ 0x40101F24) Capture clock interrupt set mask */\r
+ __I uint32_t ENABLE1; /*!< (@ 0x40101F28) Capture clock interrupt enable */\r
+ __I uint32_t STATUS1; /*!< (@ 0x40101F2C) Capture clock interrupt status */\r
+ __IO uint32_t CTR_STAT1; /*!< (@ 0x40101F30) Capture clock interrupt clear status */\r
+ __IO uint32_t SET_STAT1; /*!< (@ 0x40101F34) Capture clock interrupt set status */\r
+ __I uint32_t RESERVED2[2];\r
+ __IO uint32_t CLR_EN2; /*!< (@ 0x40101F40) Pattern match interrupt clear mask */\r
+ __IO uint32_t SET_EN2; /*!< (@ 0x40101F44) Pattern match interrupt set mask */\r
+ __I uint32_t ENABLE2; /*!< (@ 0x40101F48) Pattern match interrupt enable */\r
+ __I uint32_t STATUS2; /*!< (@ 0x40101F4C) Pattern match interrupt status */\r
+ __IO uint32_t CTR_STAT2; /*!< (@ 0x40101F50) Pattern match interrupt clear status */\r
+ __IO uint32_t SET_STAT2; /*!< (@ 0x40101F54) Pattern match interrupt set status */\r
+ __I uint32_t RESERVED3[2];\r
+ __IO uint32_t CLR_EN3; /*!< (@ 0x40101F60) Input interrupt clear mask */\r
+ __IO uint32_t SET_EN3; /*!< (@ 0x40101F64) Input bit match interrupt set mask */\r
+ __I uint32_t ENABLE3; /*!< (@ 0x40101F68) Input bit match interrupt enable */\r
+ __I uint32_t STATUS3; /*!< (@ 0x40101F6C) Input bit match interrupt status */\r
+ __IO uint32_t CTR_STAT3; /*!< (@ 0x40101F70) Input bit match interrupt clear status */\r
+ __IO uint32_t SET_STAT3; /*!< (@ 0x40101F74) Input bit match interrupt set status */\r
+} LPC_SGPIO_Type;\r
+\r
+#if defined ( __CC_ARM )\r
+ #pragma no_anon_unions\r
+#endif\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- Peripheral memory map -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+#define LPC_SCT_BASE (0x40000000)\r
+#define LPC_GPDMA_BASE (0x40002000)\r
+#define LPC_SPIFI_BASE (0x40003000)\r
+#define LPC_SDMMC_BASE (0x40004000)\r
+#define LPC_EMC_BASE (0x40005000)\r
+#define LPC_USB0_BASE (0x40006000)\r
+#define LPC_USB1_BASE (0x40007000)\r
+#define LPC_LCD_BASE (0x40008000)\r
+#define LPC_ETHERNET_BASE (0x40010000)\r
+#define LPC_ATIMER_BASE (0x40040000)\r
+#define LPC_REGFILE_BASE (0x40041000)\r
+#define LPC_PMC_BASE (0x40042000)\r
+#define LPC_CREG_BASE (0x40043000)\r
+#define LPC_EVENTROUTER_BASE (0x40044000)\r
+#define LPC_RTC_BASE (0x40046000)\r
+#define LPC_CGU_BASE (0x40050000)\r
+#define LPC_CCU1_BASE (0x40051000)\r
+#define LPC_CCU2_BASE (0x40052000)\r
+#define LPC_RGU_BASE (0x40053000)\r
+#define LPC_WWDT_BASE (0x40080000)\r
+#define LPC_USART0_BASE (0x40081000)\r
+#define LPC_USART2_BASE (0x400C1000)\r
+#define LPC_USART3_BASE (0x400C2000)\r
+#define LPC_UART1_BASE (0x40082000)\r
+#define LPC_SSP0_BASE (0x40083000)\r
+#define LPC_SSP1_BASE (0x400C5000)\r
+#define LPC_TIMER0_BASE (0x40084000)\r
+#define LPC_TIMER1_BASE (0x40085000)\r
+#define LPC_TIMER2_BASE (0x400C3000)\r
+#define LPC_TIMER3_BASE (0x400C4000)\r
+#define LPC_SCU_BASE (0x40086000)\r
+#define LPC_GPIO_PIN_INT_BASE (0x40087000)\r
+#define LPC_GPIO_GROUP_INT0_BASE (0x40088000)\r
+#define LPC_GPIO_GROUP_INT1_BASE (0x40089000)\r
+#define LPC_MCPWM_BASE (0x400A0000)\r
+#define LPC_I2C0_BASE (0x400A1000)\r
+#define LPC_I2C1_BASE (0x400E0000)\r
+#define LPC_I2S0_BASE (0x400A2000)\r
+#define LPC_I2S1_BASE (0x400A3000)\r
+#define LPC_C_CAN1_BASE (0x400A4000)\r
+#define LPC_RITIMER_BASE (0x400C0000)\r
+#define LPC_QEI_BASE (0x400C6000)\r
+#define LPC_GIMA_BASE (0x400C7000)\r
+#define LPC_DAC_BASE (0x400E1000)\r
+#define LPC_C_CAN0_BASE (0x400E2000)\r
+#define LPC_ADC0_BASE (0x400E3000)\r
+#define LPC_ADC1_BASE (0x400E4000)\r
+#define LPC_GPIO_PORT_BASE (0x400F4000)\r
+//The following are applied to have a backward compitability with existing Eagle/Raptor GPIOs\r
+#define LPC_GPIO0_BASE (0x400F4000)\r
+#define LPC_GPIO1_BASE (0x400F4004)\r
+#define LPC_GPIO2_BASE (0x400F4008)\r
+#define LPC_GPIO3_BASE (0x400F400C)\r
+#define LPC_GPIO4_BASE (0x400F4010)\r
+#define LPC_GPIO5_BASE (0x400F4014)\r
+#define LPC_GPIO6_BASE (0x400F4018)\r
+#define LPC_GPIO7_BASE (0x400F401C)\r
+#define LPC_RNG_BASE (0x40054000)\r
+#define LPC_SGPIO_BASE (0x40101000)\r
+#define LPC_VADC_BASE (0x400F0000)\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- Peripheral declaration -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+#define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE)\r
+#define LPC_GPDMA ((LPC_GPDMA_Type *) LPC_GPDMA_BASE)\r
+#define LPC_SPIFI ((LPC_SPIFI_Type *) LPC_SPIFI_BASE)\r
+#define LPC_SDMMC ((LPC_SDMMC_Type *) LPC_SDMMC_BASE)\r
+#define LPC_EMC ((LPC_EMC_Type *) LPC_EMC_BASE)\r
+#define LPC_USB0 ((LPC_USB0_Type *) LPC_USB0_BASE)\r
+#define LPC_USB1 ((LPC_USB1_Type *) LPC_USB1_BASE)\r
+#define LPC_LCD ((LPC_LCD_Type *) LPC_LCD_BASE)\r
+#define LPC_ETHERNET ((LPC_ETHERNET_Type *) LPC_ETHERNET_BASE)\r
+#define LPC_ATIMER ((LPC_ATIMER_Type *) LPC_ATIMER_BASE)\r
+#define LPC_REGFILE ((LPC_REGFILE_Type *) LPC_REGFILE_BASE)\r
+#define LPC_PMC ((LPC_PMC_Type *) LPC_PMC_BASE)\r
+#define LPC_CREG ((LPC_CREG_Type *) LPC_CREG_BASE)\r
+#define LPC_EVENTROUTER ((LPC_EVENTROUTER_Type *) LPC_EVENTROUTER_BASE)\r
+#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)\r
+#define LPC_CGU ((LPC_CGU_Type *) LPC_CGU_BASE)\r
+#define LPC_CCU1 ((LPC_CCU1_Type *) LPC_CCU1_BASE)\r
+#define LPC_CCU2 ((LPC_CCU2_Type *) LPC_CCU2_BASE)\r
+#define LPC_RGU ((LPC_RGU_Type *) LPC_RGU_BASE)\r
+#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)\r
+#define LPC_USART0 ((LPC_USARTn_Type *) LPC_USART0_BASE)\r
+#define LPC_USART2 ((LPC_USARTn_Type *) LPC_USART2_BASE)\r
+#define LPC_USART3 ((LPC_USARTn_Type *) LPC_USART3_BASE)\r
+#define LPC_UART1 ((LPC_UART1_Type *) LPC_UART1_BASE)\r
+#define LPC_SSP0 ((LPC_SSPn_Type *) LPC_SSP0_BASE)\r
+#define LPC_SSP1 ((LPC_SSPn_Type *) LPC_SSP1_BASE)\r
+#define LPC_TIMER0 ((LPC_TIMERn_Type *) LPC_TIMER0_BASE)\r
+#define LPC_TIMER1 ((LPC_TIMERn_Type *) LPC_TIMER1_BASE)\r
+#define LPC_TIMER2 ((LPC_TIMERn_Type *) LPC_TIMER2_BASE)\r
+#define LPC_TIMER3 ((LPC_TIMERn_Type *) LPC_TIMER3_BASE)\r
+#define LPC_SCU ((LPC_SCU_Type *) LPC_SCU_BASE)\r
+#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)\r
+#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)\r
+#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)\r
+#define LPC_MCPWM ((LPC_MCPWM_Type *) LPC_MCPWM_BASE)\r
+#define LPC_I2C0 ((LPC_I2Cn_Type *) LPC_I2C0_BASE)\r
+#define LPC_I2C1 ((LPC_I2Cn_Type *) LPC_I2C1_BASE)\r
+#define LPC_I2S0 ((LPC_I2Sn_Type *) LPC_I2S0_BASE)\r
+#define LPC_I2S1 ((LPC_I2Sn_Type *) LPC_I2S1_BASE)\r
+#define LPC_C_CAN1 ((LPC_C_CANn_Type *) LPC_C_CAN1_BASE)\r
+#define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)\r
+#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)\r
+#define LPC_GIMA ((LPC_GIMA_Type *) LPC_GIMA_BASE)\r
+#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)\r
+#define LPC_C_CAN0 ((LPC_C_CANn_Type *) LPC_C_CAN0_BASE)\r
+#define LPC_ADC0 ((LPC_ADCn_Type *) LPC_ADC0_BASE)\r
+#define LPC_ADC1 ((LPC_ADCn_Type *) LPC_ADC1_BASE)\r
+#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE) //Short name: HSGPIO???\r
+#define LPC_GPIO0 ((LPC_GPIOn_Type *) LPC_GPIO0_BASE) //Backward compitable for all GPIOs\r
+#define LPC_GPIO1 ((LPC_GPIOn_Type *) LPC_GPIO1_BASE)\r
+#define LPC_GPIO2 ((LPC_GPIOn_Type *) LPC_GPIO2_BASE)\r
+#define LPC_GPIO3 ((LPC_GPIOn_Type *) LPC_GPIO3_BASE)\r
+#define LPC_GPIO4 ((LPC_GPIOn_Type *) LPC_GPIO4_BASE)\r
+#define LPC_GPIO5 ((LPC_GPIOn_Type *) LPC_GPIO5_BASE)\r
+#define LPC_GPIO6 ((LPC_GPIOn_Type *) LPC_GPIO6_BASE)\r
+#define LPC_GPIO7 ((LPC_GPIOn_Type *) LPC_GPIO7_BASE)\r
+#define LPC_SGPIO ((LPC_SGPIO_Type *) LPC_SGPIO_BASE)\r
+#define LPC_RNG ((LPC_RNG_Type *) LPC_RNG_BASE)\r
+#define LPC_VADC ((LPC_VADC_Type *) LPC_VADC_BASE)\r
+\r
+/** @} */ /* End of group Device_Peripheral_Registers */\r
+/** @} */ /* End of group (null) */\r
+/** @} */ /* End of group LPC43xx */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif \r
+\r
+\r
+#endif // __LPC43XX_A_H__\r
--- /dev/null
+/*****************************************************************************\r
+ * config.h: Header file for NXP LPC43xx Family Microprocessors\r
+ *\r
+ * Copyright(C) 2011, NXP Semiconductor\r
+ * All rights reserved.\r
+ *\r
+ * History\r
+ * 2011.6.22 ver 1.00 Preliminary version, first Release\r
+ *\r
+******************************************************************************/\r
+#ifndef __CONFIG_H \r
+#define __CONFIG_H\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ Define clocks\r
+ *----------------------------------------------------------------------------*/\r
+#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */\r
+#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */\r
+#define IRC_TRIM_VAL 0x34A /* IRC trim value for 12MHz output */\r
+#define XTAL_FREQ (12000000UL) /* Frequency of external xtal */\r
+#define EXT_FREQ (12000000UL) /* Frequency of external clock on EXT_TCK, ENET_RX_CLK or ENET_TX_CLK */\r
+\r
+/*----------------------------------------------------------------------------\r
+ Retarget selection\r
+ *----------------------------------------------------------------------------*/\r
+\r
+typedef enum {\r
+ RETARGET_USART0 = 0,\r
+ RETARGET_UART1 = 1,\r
+ RETARGET_USART2 = 2,\r
+ RETARGET_USART3 = 3\r
+} RETARGET_Type;\r
+\r
+#define RETARGET_UART_BUFSIZE 0x40\r
+extern volatile uint32_t UART0Count;\r
+extern volatile uint8_t UART0Buffer[RETARGET_UART_BUFSIZE];\r
+extern volatile uint32_t UART1Count;\r
+extern volatile uint8_t UART1Buffer[RETARGET_UART_BUFSIZE];\r
+extern volatile uint32_t UART2Count;\r
+extern volatile uint8_t UART2Buffer[RETARGET_UART_BUFSIZE];\r
+extern volatile uint32_t UART3Count;\r
+extern volatile uint8_t UART3Buffer[RETARGET_UART_BUFSIZE];\r
+extern void RetargetInit(RETARGET_Type retarget, uint32_t baudrate);\r
+\r
+/*----------------------------------------------------------------------------\r
+ Board selection\r
+ *----------------------------------------------------------------------------*/\r
+//NXP LPC4300 validation board\r
+//#define NXP_VALIDATION_BOARD\r
+\r
+//Hitex LPC4350 evaluation board\r
+//#define USE_HITEX_LPC4350_EVAL\r
+\r
+#endif /* end __CONFIG_H */\r
+/*****************************************************************************\r
+** End Of File\r
+******************************************************************************/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4.c\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
+ * @version V2.01\r
+ * @date 06. December 2010\r
+ *\r
+ * @note\r
+ * Copyright (C) 2010 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+\r
+#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4.h\r
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
+ * @version V2.01\r
+ * @date 06. December 2010\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+#if defined ( __ICCARM__ ) \r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#ifndef __CORE_CM4_H_GENERIC\r
+#define __CORE_CM4_H_GENERIC\r
+\r
+\r
+/** \mainpage CMSIS Cortex-M4\r
+ \r
+ This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.\r
+ It consists of:\r
+ \r
+ - Cortex-M Core Register Definitions\r
+ - Cortex-M functions\r
+ - Cortex-M instructions\r
+ - Cortex-M SIMD instructions\r
+ \r
+ The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease \r
+ access to the Cortex-M Core\r
+ */ \r
+\r
+/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration\r
+ List of Lint messages which will be suppressed and not shown:\r
+ - not yet checked\r
+ .\r
+ Note: To re-enable a Message, insert a space before 'lint' *\r
+ \r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions\r
+ This file defines all structures and symbols for CMSIS core:\r
+ - CMSIS version number\r
+ - Cortex-M core \r
+ - Cortex-M core Revision Number\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM4 definitions */\r
+#define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x04) /*!< Cortex core */\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3 /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+#include <stdint.h> /*!< standard types definitions */\r
+#include "core_cmInstr.h" /*!< Core Instruction Access */\r
+#include "core_cmFunc.h" /*!< Core Function Access */\r
+#include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */\r
+\r
+#endif /* __CORE_CM4_H_GENERIC */\r
+\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM4_H_DEPENDANT\r
+#define __CORE_CM4_H_DEPENDANT\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+/*@} end of group CMSIS_core_definitions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register CMSIS Core Register\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register \r
+ \defgroup CMSIS_CORE CMSIS Core\r
+ Type definitions for the Cortex-M Core Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */ \r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register \r
+ \defgroup CMSIS_NVIC CMSIS NVIC\r
+ Type definitions for the Cortex-M NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24]; \r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24]; \r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24]; \r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24]; \r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56]; \r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644]; \r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type; \r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register \r
+ \defgroup CMSIS_SCB CMSIS SCB\r
+ Type definitions for the Cortex-M System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) Hard Fault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) Mem Manage Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) Bus Fault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) ISA Feature Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x880 (R/W) Coprocessor access register */\r
+} SCB_Type; \r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+ \r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register \r
+ \defgroup CMSIS_SysTick CMSIS SysTick\r
+ Type definitions for the Cortex-M System Timer Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register \r
+ \defgroup CMSIS_ITM CMSIS ITM\r
+ Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union \r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864]; \r
+ __IO uint32_t TER; /*!< Offset: (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15]; \r
+ __IO uint32_t TPR; /*!< Offset: (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15]; \r
+ __IO uint32_t TCR; /*!< Offset: (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29]; \r
+ __IO uint32_t IWR; /*!< Offset: (R/W) ITM Integration Write Register */\r
+ __IO uint32_t IRR; /*!< Offset: (R/W) ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43]; \r
+ __IO uint32_t LAR; /*!< Offset: (R/W) ITM Lock Access Register */\r
+ __IO uint32_t LSR; /*!< Offset: (R/W) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6]; \r
+ __I uint32_t PID4; /*!< Offset: (R/ ) ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: (R/ ) ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: (R/ ) ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: (R/ ) ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: (R/ ) ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: (R/ ) ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: (R/ ) ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: (R/ ) ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: (R/ ) ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: (R/ ) ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: (R/ ) ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type; \r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_ATBID_Msk (0x7FUL << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/** \ingroup CMSIS_core_register \r
+ \defgroup CMSIS_InterruptType CMSIS Interrupt Type\r
+ Type definitions for the Cortex-M Interrupt Type Register\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Interrupt Type Register.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0;\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Control Type Register */\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} InterruptType_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define IntType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */\r
+#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define IntType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */\r
+#define IntType_ACTLR_DISFOLD_Msk (1UL << IntType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */\r
+\r
+#define IntType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
+#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
+\r
+#define IntType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */\r
+#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_InterruptType */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register \r
+ \defgroup CMSIS_MPU CMSIS MPU\r
+ Type definitions for the Cortex-M Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type; \r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */\r
+#define MPU_RASR_AP_Msk (7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */\r
+#define MPU_RASR_TEX_Msk (7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENA_Msk (0x1UL << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if (__FPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register \r
+ \defgroup CMSIS_FPU CMSIS FPU\r
+ Type definitions for the Cortex-M Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1]; \r
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating point context control register */\r
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating point context address register */\r
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating point default status control register */\r
+ __IO uint32_t MVFR0; /*!< Offset: 0x010 (R/W) Media and VFP feature register 0 */\r
+ __IO uint32_t MVFR1; /*!< Offset: 0x014 (R/W) Media and VFP feature register 1 */\r
+} FPU_Type; \r
+\r
+/*@} end of group CMSIS_FPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register \r
+ \defgroup CMSIS_CoreDebug CMSIS Core Debug\r
+ Type definitions for the Cortex-M Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register \r
+ @{\r
+ */\r
+ \r
+/* Memory mapping of Cortex-M4 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#if (__FPU_PRESENT == 1)\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type*) FPU_BASE) /*!< Floating Point Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface \r
+ \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ This function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ \r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ (0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ This function gets the priority grouping from NVIC Interrupt Controller.\r
+ Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+\r
+ \return Priority grouping field\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ This function enables a device specific interupt in the NVIC interrupt controller.\r
+ The interrupt number cannot be a negative value. \r
+\r
+ \param [in] IRQn Number of the external interrupt to enable\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ This function disables a device specific interupt in the NVIC interrupt controller.\r
+ The interrupt number cannot be a negative value. \r
+\r
+ \param [in] IRQn Number of the external interrupt to disable\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ This function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt. \r
+\r
+ \param [in] IRQn Number of the interrupt for get pending\r
+ \return 0 Interrupt status is not pending\r
+ \return 1 Interrupt status is pending\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ This function sets the pending bit for the specified interrupt. \r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the interrupt for set pending\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ This function clears the pending bit for the specified interrupt. \r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the interrupt for clear pending\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ This function reads the active register in NVIC and returns the active bit. \r
+ \param [in] IRQn Number of the interrupt for get active\r
+ \return 0 Interrupt status is not active\r
+ \return 1 Interrupt status is active\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ This function sets the priority for the specified interrupt. The interrupt \r
+ number can be positive to specify an external (device specific) \r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+ Note: The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Number of the interrupt for set priority\r
+ \param [in] priority Priority to set\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ This function reads the priority for the specified interrupt. The interrupt \r
+ number can be positive to specify an external (device specific) \r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+ The returned priority value is automatically aligned to the implemented\r
+ priority bits of the microcontroller.\r
+\r
+ \param [in] IRQn Number of the interrupt for get priority\r
+ \return Interrupt Priority\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ This function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value and sub priority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ \r
+ The returned priority value can be used for NVIC_SetPriority(...) function\r
+\r
+ \param [in] PriorityGroup Used priority group\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0)\r
+ \param [in] SubPriority Sub priority value (starting from 0)\r
+ \return Encoded priority for the interrupt\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ This function decodes an interrupt priority value with the given priority group to \r
+ preemptive priority value and sub priority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ \r
+ The priority value can be retrieved with NVIC_GetPriority(...) function\r
+ \r
+ \param [in] Priority Priority value\r
+ \param [in] PriorityGroup Used priority group\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0)\r
+ \param [out] pSubPriority Sub priority value (starting from 0)\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ This function initiate a system reset request to reset the MCU.\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */ \r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | \r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */ \r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface \r
+ \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ This function initialises the system tick timer and its interrupt and start the system tick timer.\r
+ Counter is in free running mode to generate periodical interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{ \r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ \r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | \r
+ SysTick_CTRL_TICKINT_Msk | \r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface \r
+ \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ This function transmits a character via the ITM channel 0. \r
+ It just returns when no debugger is connected that has booked the output. \r
+ It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+\r
+ \param [in] ch Character to transmit\r
+ \return Character to transmit\r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ } \r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ This function inputs a character via external variable ITM_RxBuffer. \r
+ It just returns when no debugger is connected that has booked the output. \r
+ It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+\r
+ \return Received character\r
+ \return -1 No character received\r
+ */\r
+static __INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+ \r
+ return (ch); \r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ This function checks external variable ITM_RxBuffer whether a character is available or not. \r
+ It returns '1' if a character is available and '0' if no character is available. \r
+\r
+ \return 0 No character available\r
+ \return 1 Character available\r
+ */\r
+static __INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+#endif /* __CORE_CM4_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*lint -restore */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V2.01\r
+ * @date 06. December 2010\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMFUNC_H__\r
+#define __CORE_CMFUNC_H__\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface \r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern uint32_t __get_CONTROL(void);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern void __set_CONTROL(uint32_t control);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+/** \brief Get ISPR Register\r
+\r
+ This function returns the content of the ISPR Register.\r
+\r
+ \return ISPR Register value\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern uint32_t __get_IPSR(void);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+static __INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern uint32_t __get_APSR(void);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+static __INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern uint32_t __get_xPSR(void);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+static __INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern uint32_t __get_PSP(void);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+static __INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+static __INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern uint32_t __get_MSP(void);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+static __INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+static __INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern uint32_t __get_PRIMASK(void);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+ \r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern uint32_t __get_BASEPRI(void);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+ \r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern uint32_t __get_FAULTMASK(void);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & 1);\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+static __INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+static __INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+ #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#if defined (__ICCARM__)\r
+ #include <intrinsics.h> /* IAR Intrinsics */\r
+#endif\r
+\r
+#pragma diag_suppress=Pe940\r
+\r
+/** \brief Enable IRQ Interrupts\r
+\r
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_irq __enable_interrupt\r
+\r
+\r
+/** \brief Disable IRQ Interrupts\r
+\r
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_irq __disable_interrupt\r
+\r
+\r
+/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */\r
+/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */\r
+\r
+\r
+/** \brief Get ISPR Register\r
+\r
+ This function returns the content of the ISPR Register.\r
+\r
+ \return ISPR Register value\r
+ */\r
+static uint32_t __get_IPSR(void)\r
+{\r
+ __ASM("mrs r0, ipsr");\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+static uint32_t __get_APSR(void)\r
+{\r
+ __ASM("mrs r0, apsr");\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+static uint32_t __get_xPSR(void)\r
+{\r
+ __ASM("mrs r0, psr"); // assembler does not know "xpsr"\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+static uint32_t __get_PSP(void)\r
+{\r
+ __ASM("mrs r0, psp");\r
+}\r
+ \r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+static void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM("msr psp, r0");\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+static uint32_t __get_MSP(void)\r
+{\r
+ __ASM("mrs r0, msp");\r
+}\r
+ \r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+static void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM("msr msp, r0");\r
+}\r
+ \r
+\r
+/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */\r
+/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */\r
+ \r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+static __INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM ("cpsie f");\r
+}\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+static __INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM ("cpsid f");\r
+}\r
+\r
+\r
+/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */\r
+/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */\r
+/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */\r
+/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+static uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1)\r
+ __ASM("vmrs r0, fpscr"); \r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+static void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1)\r
+ __ASM("vmsr fpscr, r0");\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+#pragma diag_default=Pe940\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief Enable IRQ Interrupts\r
+\r
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i");\r
+}\r
+\r
+\r
+/** \brief Disable IRQ Interrupts\r
+\r
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i");\r
+}\r
+\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+\r
+/** \brief Get ISPR Register\r
+\r
+ This function returns the content of the ISPR Register.\r
+\r
+ \return ISPR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+ \r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+ \r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+ \r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f");\r
+}\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f");\r
+}\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1)\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, fpscr" : "=r" (result) );\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1)\r
+ __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+#endif /* __CORE_CMFUNC_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V2.01\r
+ * @date 06. December 2010\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMINSTR_H__\r
+#define __CORE_CMINSTR_H__\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor, \r
+ so that all instructions following the ISB are fetched from cache or \r
+ memory, after the instruction has been completed.\r
+ */\r
+#define __ISB() __isb(0xF)\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier. \r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __dsb(0xF)\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before \r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __dmb(0xF)\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#if (__ARMCC_VERSION < 400677)\r
+extern uint32_t __REV16(uint32_t value);\r
+#else /* (__ARMCC_VERSION >= 400677) */\r
+static __INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#if (__ARMCC_VERSION < 400677)\r
+extern int32_t __REVSH(int32_t value);\r
+#else /* (__ARMCC_VERSION >= 400677) */\r
+static __INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __rbit\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+extern void __CLREX(void);\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+#define __CLREX __clrex\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz \r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <intrinsics.h> /* IAR Intrinsics */\r
+\r
+#pragma diag_suppress=Pe940\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __no_operation\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+static __INLINE void __WFI(void)\r
+{\r
+ __ASM ("wfi");\r
+}\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+static __INLINE void __WFE(void)\r
+{\r
+ __ASM ("wfe");\r
+}\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+static __INLINE void __SEV(void)\r
+{\r
+ __ASM ("sev");\r
+}\r
+\r
+\r
+/* intrinsic void __ISB(void) (see intrinsics.h) */\r
+/* intrinsic void __DSB(void) (see intrinsics.h) */\r
+/* intrinsic void __DMB(void) (see intrinsics.h) */\r
+/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */\r
+/* intrinsic __SSAT (see intrinsics.h) */\r
+/* intrinsic __USAT (see intrinsics.h) */\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+static uint32_t __REV16(uint32_t value)\r
+{\r
+ __ASM("rev16 r0, r0");\r
+}\r
+\r
+\r
+/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+static uint32_t __RBIT(uint32_t value)\r
+{\r
+ __ASM("rbit r0, r0");\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+static uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ __ASM("ldrexb r0, [r0]");\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+static uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ __ASM("ldrexh r0, [r0]");\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */\r
+static uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ __ASM("ldrex r0, [r0]");\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ __ASM("strexb r0, r0, [r1]");\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ __ASM("strexh r0, r0, [r1]");\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/\r
+static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ __ASM("strex r0, r0, [r1]");\r
+}\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+static __INLINE void __CLREX(void)\r
+{\r
+ __ASM ("clrex");\r
+}\r
+\r
+/* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+#pragma diag_default=Pe940\r
+\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor, \r
+ so that all instructions following the ISB are fetched from cache or \r
+ memory, after the instruction has been completed.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb");\r
+}\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier. \r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb");\r
+}\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before \r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb");\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint8_t result;\r
+ \r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint16_t result;\r
+ \r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex");\r
+}\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ uint8_t result;\r
+ \r
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+\r
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H__ */\r
--- /dev/null
+/*********************************************************************** \r
+ * $Id: dma.h 8242 2011-10-11 15:15:25Z nxp28536 $\r
+ * \r
+ * Project: LPC43xx Validation\r
+ * \r
+ * Description: DMA Test\r
+ * \r
+ * Copyright(C) 2010, NXP Semiconductor\r
+ * All rights reserved.\r
+ * \r
+ ***********************************************************************\r
+ * Software that is described herein is for illustrative purposes only \r
+ * which provides customers with programming information regarding the \r
+ * products. This software is supplied "AS IS" without any warranties. \r
+ * NXP Semiconductors assumes no responsibility or liability for the \r
+ * use of the software, conveys no license or title under any patent, \r
+ * copyright, or mask work right to the product. NXP Semiconductors \r
+ * reserves the right to make changes in the software without \r
+ * notification. NXP Semiconductors also make no representation or \r
+ * warranty that such application will be suitable for the specified \r
+ * use without further testing or modification. \r
+ **********************************************************************/\r
+#ifndef __DMA_H \r
+#define __DMA_H\r
+\r
+#define DMA_SIZE 0x1000\r
+\r
+#define M2M 0x00\r
+#define M2P 0x01\r
+#define P2M 0x02\r
+#define P2P 0x03\r
+\r
+extern void DMA_IRQHandler (void);\r
+extern uint32_t DMA_Init_Matrix( uint32_t u32SrcAddr );\r
+\r
+typedef struct _LinkedList {\r
+ DWORD SRC;\r
+ DWORD DST; \r
+ DWORD LLI;\r
+ DWORD CTRL;\r
+}LinkedList;\r
+\r
+#endif /* end __DMA_H */\r
+/****************************************************************************\r
+** End Of File\r
+****************************************************************************/\r
--- /dev/null
+/***********************************************************************\r
+ * $Id: emc_LPC43xx.c 8389 2011-10-19 13:53:14Z nxp28536 $ emc_LPC43xx.c\r
+ *\r
+ * Project: NXP LPC43xx Common\r
+ *\r
+ * Description: Initialisation of the external memory interface and\r
+ * configuration for the specific memories connected to\r
+ * the LPC43xx\r
+ *\r
+ * Copyright(C) 2011, NXP Semiconductor\r
+ * All rights reserved.\r
+ *\r
+ ***********************************************************************\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * products. This software is supplied "AS IS" without any warranties.\r
+ * NXP Semiconductors assumes no responsibility or liability for the\r
+ * use of the software, conveys no license or title under any patent,\r
+ * copyright, or mask work right to the product. NXP Semiconductors\r
+ * reserves the right to make changes in the software without\r
+ * notification. NXP Semiconductors also make no representation or\r
+ * warranty that such application will be suitable for the specified\r
+ * use without further testing or modification.\r
+ **********************************************************************/\r
+\r
+#include "LPC43xx.h"\r
+#include "system_LPC43xx.h"\r
+#include "scu.h"\r
+#include "config.h"\r
+#include "platform_config.h"\r
+\r
+#include "emc_LPC43xx.h"\r
+\r
+\r
+/**********************************************************************\r
+ ** Function prototypes\r
+**********************************************************************/\r
+#define DELAY_1usFreq (1000000) // 1MHz equivalent to 1usec\r
+static uint32_t delayBase1us; // calculated depending on M4/EMI frequency\r
+static void vDelay(uint32_t u32Delay); // delay function\r
+\r
+\r
+\r
+/****************************************************************************************\r
+* Call the required memory setup functions from here\r
+*\r
+*\r
+****************************************************************************************/\r
+void EMC_Init( void )\r
+{\r
+ // The address/data pins for the memory interface are required for the static and for\r
+ // dynamic memories\r
+ EMC_Config_Pinmux();\r
+\r
+ // Initialise the control signals for static memories\r
+#if (USE_EXT_STATIC_MEM == YES)\r
+\r
+ // Initialise the control signals for static memories\r
+ EMC_Config_Static();\r
+\r
+// #if (USE_EXT_DYNAMIC_MEM == NO)\r
+// LPC_EMC->CONTROL = 0x00000001; // Enable the external memory controller \r
+// LPC_EMC->CONFIG = 0; \r
+// // Buffers for the static memories are enabled as well. If there is SDRAM as well,\r
+// // then this is done after the initialisation for the dynamic memory interface.\r
+// LPC_EMC->STATICCONFIG0 = 0x00080081; \r
+// #endif\r
+\r
+#endif\r
+\r
+#if (USE_EXT_DYNAMIC_MEM == YES)\r
+\r
+ // The setup for dynamic memories (SDRAM)\r
+ EMC_Init_SRDRAM(SDRAM_BASE, PART_WIDTH, PART_SIZE, EXT_WIDTH, COL_ADDR_BITS);\r
+\r
+#elif (USE_EXT_DYNAMIC_MEM == NO)\r
+\r
+ LPC_EMC->CONTROL = 0x00000001; // Enable the external memory controller \r
+ LPC_EMC->CONFIG = 0; \r
+\r
+#endif\r
+ \r
+ // Buffers for the static memories can now be enabled as well. In a system with static and dynamic memory\r
+ // this should only been done after the SDRAM initialisation --> here\r
+ LPC_EMC->STATICCONFIG0 = 0x00080081;\r
+\r
+}\r
+\r
+\r
+/****************************************************************************************\r
+* Set up the address/data pins for external memory interface in LP43xx\r
+*\r
+* Modify this function in case not all of the address/data pins are needed.\r
+****************************************************************************************/\r
+void EMC_Config_Pinmux(void)\r
+{\r
+ \r
+ // Disable the external memory controller before changing pin control configuration\r
+ LPC_EMC->CONTROL = 0x00000000;\r
+\r
+// EMC_OUT (PUP_CLEAR | SLEWRATE_FAST | FILTER_DISABLE) \r
+// EMC_IO (PUP_CLEAR | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)\r
+\r
+ // Data line configuration\r
+ scu_pinmux(0x1, 7, EMC_IO, FUNC3); // P1_7: D0\r
+ scu_pinmux(0x1, 8, EMC_IO, FUNC3); // P1_8: D1\r
+ scu_pinmux(0x1, 9, EMC_IO, FUNC3); // P1_9: D2\r
+ scu_pinmux(0x1, 10, EMC_IO, FUNC3); // P1_10: D3\r
+ scu_pinmux(0x1, 11, EMC_IO, FUNC3); // P1_11: D4\r
+ scu_pinmux(0x1, 12, EMC_IO, FUNC3); // P1_12: D5\r
+ scu_pinmux(0x1, 13, EMC_IO, FUNC3); // P1_13: D6\r
+ scu_pinmux(0x1, 14, EMC_IO, FUNC3); // P1_14: D7\r
+ scu_pinmux(0x5, 4, EMC_IO, FUNC2); // P5_4: D8\r
+ scu_pinmux(0x5, 5, EMC_IO, FUNC2); // P5_5: D9\r
+ scu_pinmux(0x5, 6, EMC_IO, FUNC2); // P5_6: D10\r
+ scu_pinmux(0x5, 7, EMC_IO, FUNC2); // P5_7: D11\r
+ scu_pinmux(0x5, 0, EMC_IO, FUNC2); // P5_0: D12\r
+ scu_pinmux(0x5, 1, EMC_IO, FUNC2); // P5_1: D13\r
+ scu_pinmux(0x5, 2, EMC_IO, FUNC2); // P5_2: D14\r
+ scu_pinmux(0x5, 3, EMC_IO, FUNC2); // P5_3: D15\r
+ scu_pinmux(0xD, 2, EMC_IO, FUNC2); // PD_2: D16\r
+ scu_pinmux(0xD, 3, EMC_IO, FUNC2); // PD_3: D17\r
+ scu_pinmux(0xD, 4, EMC_IO, FUNC2); // PD_4: D18\r
+ scu_pinmux(0xD, 5, EMC_IO, FUNC2); // PD_5: D19\r
+ scu_pinmux(0xD, 6, EMC_IO, FUNC2); // PD_6: D20\r
+ scu_pinmux(0xD, 7, EMC_IO, FUNC2); // PD_7: D21\r
+ scu_pinmux(0xD, 8, EMC_IO, FUNC2); // PD_8: D22\r
+ scu_pinmux(0xD, 9, EMC_IO, FUNC2); // PD_9: D23\r
+ scu_pinmux(0xE, 5, EMC_IO, FUNC3); // PE_5: D24\r
+ scu_pinmux(0xE, 6, EMC_IO, FUNC3); // PE_6: D25\r
+ scu_pinmux(0xE, 7, EMC_IO, FUNC3); // PE_7: D26\r
+ scu_pinmux(0xE, 8, EMC_IO, FUNC3); // PE_8: D27\r
+ scu_pinmux(0xE, 9, EMC_IO, FUNC3); // PE_9: D28\r
+ scu_pinmux(0xE, 10, EMC_IO, FUNC3); // PE_10: D29\r
+ scu_pinmux(0xE, 11, EMC_IO, FUNC3); // PE_11: D30\r
+ scu_pinmux(0xE, 12, EMC_IO, FUNC3); // PE_12: D31\r
+\r
+ // Address line configuration\r
+ scu_pinmux(0x2, 9, EMC_IO, FUNC3); // P2_9: A0\r
+ scu_pinmux(0x2, 10, EMC_IO, FUNC3); // P2_10: A1\r
+ scu_pinmux(0x2, 11, EMC_IO, FUNC3); // P2_11: A2\r
+ scu_pinmux(0x2, 12, EMC_IO, FUNC3); // P2_12: A3\r
+ scu_pinmux(0x2, 13, EMC_IO, FUNC3); // P2_13: A4\r
+ scu_pinmux(0x1, 0, EMC_IO, FUNC2); // P1_0: A5\r
+ scu_pinmux(0x1, 1, EMC_IO, FUNC2); // P1_1: A6\r
+ scu_pinmux(0x1, 2, EMC_IO, FUNC2); // P1_2: A7\r
+ scu_pinmux(0x2, 8, EMC_IO, FUNC3); // P2_8: A8\r
+ scu_pinmux(0x2, 7, EMC_IO, FUNC3); // P2_7: A9\r
+ scu_pinmux(0x2, 6, EMC_IO, FUNC2); // P2_6: A10\r
+ scu_pinmux(0x2, 2, EMC_IO, FUNC2); // P2_2: A11\r
+ scu_pinmux(0x2, 1, EMC_IO, FUNC2); // P2_0: A12\r
+ scu_pinmux(0x2, 0, EMC_IO, FUNC2); // P2_0: A13\r
+ scu_pinmux(0x6, 8, EMC_IO, FUNC1); // P6_8: A14\r
+ scu_pinmux(0x6, 7, EMC_IO, FUNC1); // P6_7: A15\r
+ scu_pinmux(0xD, 16, EMC_IO, FUNC2); // PD_16: A16\r
+ scu_pinmux(0xD, 15, EMC_IO, FUNC2); // PD_15: A17\r
+ scu_pinmux(0xE, 0, EMC_IO, FUNC3); // PE_0: A18\r
+ scu_pinmux(0xE, 1, EMC_IO, FUNC3); // PE_1: A19\r
+ scu_pinmux(0xE, 2, EMC_IO, FUNC3); // PE_2: A20\r
+ scu_pinmux(0xE, 3, EMC_IO, FUNC3); // PE_3: A21\r
+ scu_pinmux(0xE, 4, EMC_IO, FUNC3); // PE_4: A22\r
+\r
+ // Control signals for static memory\r
+ scu_pinmux(0x1, 6, EMC_IO, FUNC3); // P1_6: WE\r
+ scu_pinmux(0x1, 5, EMC_IO, FUNC3); // P1_5: CS0\r
+ scu_pinmux(0x1, 3, EMC_IO, FUNC3); // P1_6: OE\r
+ scu_pinmux(0x1, 4, EMC_IO, FUNC3); // P1_5: BLS0\r
+ scu_pinmux(0x6, 6, EMC_IO, FUNC1); // P1_6: BLS1\r
+ scu_pinmux(0xD, 12, EMC_IO, FUNC2); // PD_12: CS2\r
+\r
+ #if (USE_EXT_DYNAMIC_MEM == YES)\r
+ // Control signals for dynamic memory\r
+ scu_pinmux(0x6, 9, EMC_IO, FUNC3); // P6_9: DYCS0\r
+ scu_pinmux(0x6, 4, EMC_IO, FUNC3); // P6_4: CAS\r
+ scu_pinmux(0x6, 5, EMC_IO, FUNC3); // P6_5: RAS\r
+ scu_pinmux(0x6, 11, EMC_IO, FUNC3); // P6_11: CKEOUT0\r
+ scu_pinmux(0x6, 12, EMC_IO, FUNC3); // P6_12: DQMOUT0\r
+ scu_pinmux(0x6, 10, EMC_IO, FUNC3); // P6_10: DQMOUT1\r
+\r
+ LPC_SCU_CLK(0) = 0 + EMC_IO; // EMC_CLK0 signal on pin CLK0 (needed for SDRAM)\r
+ LPC_SCU_CLK(1) = 0 + EMC_IO;\r
+ LPC_SCU_CLK(2) = 0 + EMC_IO;\r
+ LPC_SCU_CLK(3) = 0 + EMC_IO;\r
+ #endif\r
+\r
+}\r
+\r
+\r
+/****************************************************************************************\r
+* Configure CS0 for 70ns 16-bit flash memory on the Hitex board\r
+* Configure CS2 for 55ns 16-bit SRAM on the Hitex board\r
+*\r
+****************************************************************************************/\r
+void EMC_Config_Static(void)\r
+{\r
+\r
+ // Configure CS0 for flash memory\r
+ // @120MHz there should be 8 or 9 waitstates for the 70ns flash, apparently it works with 7\r
+ LPC_EMC->STATICCONFIG0 = 0x00000081; // CS0: 16 bit = WE\r
+ LPC_EMC->STATICWAITOEN0 = 0; // CS0: WAITOEN = 0\r
+\r
+ #if (PLATFORM == HITEX_A2_BOARD)\r
+\r
+ LPC_EMC->STATICWAITRD0 = 7; // CS0: WAITRD = 7 \r
+\r
+ // The Hitex board has external SRAM on CS2\r
+ // @120MHz there should be 7 waitstates for the 55ns SRAM, it should work with 6\r
+ LPC_EMC->STATICCONFIG0 = 0x00000081; // CS2: 16 bit = WE\r
+ LPC_EMC->STATICWAITOEN2 = 0; // CS2: WAITOEN = 0\r
+ LPC_EMC->STATICWAITRD2 = 7; // CS2: WAITRD = 6\r
+\r
+ #elif (PLATFORM == NXP_VALIDATION_BOARD)\r
+\r
+ LPC_EMC->STATICWAITRD0 = check 9; // CS0: WAITRD = 8 \r
+ // to be added\r
+\r
+ LPC_EMC->STATICCONFIG0 = check 0x00000081; // CS2: 16 bit = WE\r
+ LPC_EMC->STATICWAITOEN2 = check 0; // CS2: WAITOEN = 0\r
+ LPC_EMC->STATICWAITRD2 = check 7; // CS2: WAITRD = 6\r
+\r
+ #endif\r
+ \r
+}\r
+\r
+\r
+// Defines for EMC signal delay settings\r
+#define EMC_B_ENABLE (1 << 19)\r
+#define EMC_ENABLE (1 << 0)\r
+#define EMC_CE_ENABLE (1 << 0)\r
+#define EMC_CS_ENABLE (1 << 1)\r
+#define EMC_CLOCK_DELAYED_STRATEGY (0 << 0)\r
+#define EMC_COMMAND_DELAYED_STRATEGY (1 << 0)\r
+#define EMC_COMMAND_DELAYED_STRATEGY2 (2 << 0)\r
+#define EMC_COMMAND_DELAYED_STRATEGY3 (3 << 0)\r
+#define EMC_INIT(i) ((i) << 7)\r
+#define EMC_NORMAL (0)\r
+#define EMC_MODE (1)\r
+#define EMC_PRECHARGE_ALL (2)\r
+#define EMC_NOP (3)\r
+\r
+/****************************************************************************************\r
+* Configure the delays for the SDRAM\r
+*\r
+* - on the Hitex board (IS42S16400D-7TL)\r
+* - on the NXP evaluation board (MT48LC4M32B2)\r
+* - on the NXP validation board (MT48LC4M32B2)\r
+*\r
+****************************************************************************************/\r
+#if (PLATFORM == HITEX_A2_BOARD) || (PLATFORM == NXP_VALIDATION_BOARD)\r
+\r
+// Defines for SDRAM devices\r
+#define DOUT_DELAY 0\r
+#define CLK0_DELAY 5\r
+#define CLKE0_DELAY 5\r
+#define RAS_DELAY 0\r
+#define CAS_DELAY 0\r
+#define WE_DELAY 0\r
+#define DYCS0_DELAY 0\r
+#define DQM0_DELAY 0\r
+#define FBCLK0_DELAY 0\r
+#define CCLK_DELAY 0\r
+#define ADDR_DELAY 0\r
+#define DIN_DELAY 0\r
+#define DEN_DELAY 0\r
+\r
+#endif\r
+\r
+void initEmiDelays(void)\r
+{\r
+ // eventually configure delays, defaults are zero\r
+\r
+ // CLK & CLKE0 delay\r
+ *(uint32_t*)(LPC_SCU_BASE + 0xD00) = ((CLK0_DELAY << 16) | (CLKE0_DELAY << 0) );\r
+\r
+ // EMCCTRLDELAY, address 0x4008 6D04\r
+ *(uint32_t*)(LPC_SCU_BASE + 0xD04) = ((WE_DELAY << 12)| (CAS_DELAY << 4) | (RAS_DELAY << 0) );\r
+\r
+ // DYCS0_DELAY, address 0x4008 6D08\r
+ *(uint32_t*)(LPC_SCU_BASE + 0xD08) = ((DYCS0_DELAY << 0));\r
+\r
+ // data out delay for D0 to D31 EMCDOUTDELAY\r
+ *(uint32_t*)(LPC_SCU_BASE + 0xD0C) = ((DOUT_DELAY << 28) | (DOUT_DELAY << 24) | (DOUT_DELAY << 20) | (DOUT_DELAY << 16)|(DQM0_DELAY << 12) | (DQM0_DELAY << 8) | (DQM0_DELAY << 4) | (DQM0_DELAY << 0)) ;\r
+\r
+ // EMCFBCLKDELAY, address 0x4008 6D10\r
+ *(uint32_t*)(LPC_SCU_BASE + 0xD10) = ((CCLK_DELAY << 16)|(FBCLK0_DELAY << 12) | (FBCLK0_DELAY << 8) | (FBCLK0_DELAY << 4) | (FBCLK0_DELAY << 0)) ;\r
+\r
+ // EMCADDRDELAY, address 0x4008 6D14, 0x4008 6D18, 0x4008 6D1C)\r
+ *(uint32_t*)(LPC_SCU_BASE + 0xD14) = ((ADDR_DELAY << 28)|(ADDR_DELAY << 24)|(ADDR_DELAY << 20)|(ADDR_DELAY << 16)|(ADDR_DELAY << 12) | (ADDR_DELAY << 8) | (ADDR_DELAY << 4) | (ADDR_DELAY << 0)) ;\r
+ *(uint32_t*)(LPC_SCU_BASE + 0xD18) = ((ADDR_DELAY << 28)|(ADDR_DELAY << 24)|(ADDR_DELAY << 20)|(ADDR_DELAY << 16)|(ADDR_DELAY << 12) | (ADDR_DELAY << 8) | (ADDR_DELAY << 4) | (ADDR_DELAY << 0)) ;\r
+ *(uint32_t*)(LPC_SCU_BASE + 0xD1C) = ((ADDR_DELAY << 28)|(ADDR_DELAY << 24)|(ADDR_DELAY << 20)|(ADDR_DELAY << 16)|(ADDR_DELAY << 12) | (ADDR_DELAY << 8) | (ADDR_DELAY << 4) | (ADDR_DELAY << 0)) ;\r
+\r
+ // data in delay for D0 to D31 EMCDINDELAY\r
+ *(uint32_t*)(LPC_SCU_BASE + 0xD24) = ((DEN_DELAY << 28)|(DEN_DELAY << 24)|(DEN_DELAY << 20)|(DEN_DELAY << 16)|(DIN_DELAY << 12)|(DIN_DELAY << 8)|(DIN_DELAY << 4)|(DIN_DELAY << 0));\r
+}\r
+\r
+\r
+\r
+\r
+/****************************************************************************************\r
+* Configure the EMI for the SDRAM\r
+*\r
+* - on the Hitex board (IS42S16400D-7TL)\r
+* - on the NXP validation board (MT48LC4M32B2)\r
+*\r
+****************************************************************************************/\r
+void EMC_Init_SRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits)\r
+{\r
+\r
+ // calculate a 1 usec delay base \r
+ delayBase1us = M4Frequency / DELAY_1usFreq;\r
+\r
+ // eventually adjust the CCU delays for EMI (default to zero)\r
+ initEmiDelays();\r
+\r
+ // Initialize EMC to interface with SDRAM. The EMC needs to run for this.\r
+ LPC_EMC->CONTROL = 0x00000001; // (Re-)enable the external memory controller \r
+ LPC_EMC->CONFIG = 0;\r
+\r
+#if (PLATFORM == HITEX_A2_BOARD)\r
+\r
+ LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (u32DataBus << 14)); // Selects the configuration information for dynamic memory chip select 0.\r
+ LPC_EMC->DYNAMICRASCAS0 = (2UL << 0) | (2UL << 8); // Selects the RAS and CAS latencies for dynamic memory chip select 0. \r
+ LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY; // Configures the dynamic memory read strategy.\r
+ LPC_EMC->DYNAMICRP = 1; // Selects the precharge command period\r
+ LPC_EMC->DYNAMICRAS = 3; // Selects the active to precharge command period\r
+ LPC_EMC->DYNAMICSREX = 5; // Selects the self-refresh exit time\r
+ LPC_EMC->DYNAMICAPR = 0; // Selects the last-data-out to active command time\r
+ LPC_EMC->DYNAMICDAL = 4; // Selects the data-in to active command time.\r
+ LPC_EMC->DYNAMICWR = 1; // Selects the write recovery time\r
+ LPC_EMC->DYNAMICRC = 5; // Selects the active to active command period\r
+ LPC_EMC->DYNAMICRFC = 5; // Selects the auto-refresh period\r
+ LPC_EMC->DYNAMICXSR = 5; // Selects the exit self-refresh to active command time\r
+ LPC_EMC->DYNAMICRRD = 0; // Selects the active bank A to active bank B latency\r
+ LPC_EMC->DYNAMICMRD = 0; // Selects the load mode register to active command time\r
+ \r
+ LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);\r
+ vDelay(100);\r
+ \r
+ LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);\r
+\r
+ LPC_EMC->DYNAMICREFRESH = 2; // Configures dynamic memory refresh operation\r
+ vDelay(100);\r
+ \r
+ LPC_EMC->DYNAMICREFRESH = 83; // Configures dynamic memory refresh operation\r
+ \r
+ LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);\r
+ \r
+ // Write configuration data to SDRAM device\r
+ if(u32DataBus == 0) // 16-bit data bus, the EMC enforces a burst size 8\r
+ {\r
+ *((volatile uint32_t *)(u32BaseAddr | ((3UL | (2UL << 4)) << (u32ColAddrBits + 2 + 1))));\r
+ }\r
+ else // burst size 4 (which is not an option for 16-bit data bus anyway)\r
+ {\r
+ *((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2 + 2))));\r
+ }\r
+#endif // HITEX_BOARD\r
+\r
+\r
+#if (PLATFORM == NXP_VALIDATION_BOARD) \r
+\r
+ LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (u32DataBus << 14));\r
+ LPC_EMC->DYNAMICRASCAS0 = (2UL << 0) | (2UL << 8); \r
+ LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY; \r
+ LPC_EMC->DYNAMICRP = 1; // calculated from xls sheet\r
+ LPC_EMC->DYNAMICRAS = 2;\r
+ LPC_EMC->DYNAMICSREX = 5;\r
+ LPC_EMC->DYNAMICAPR = 0;\r
+ LPC_EMC->DYNAMICDAL = 4;\r
+ LPC_EMC->DYNAMICWR = 1;\r
+ LPC_EMC->DYNAMICRC = 5;\r
+ LPC_EMC->DYNAMICRFC = 5;\r
+ LPC_EMC->DYNAMICXSR = 5;\r
+ LPC_EMC->DYNAMICRRD = 0;\r
+ LPC_EMC->DYNAMICMRD = 0;\r
+ \r
+ LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);\r
+ vDelay(100);\r
+ \r
+ LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);\r
+\r
+ LPC_EMC->DYNAMICREFRESH = 2;\r
+ vDelay(100);\r
+ \r
+ LPC_EMC->DYNAMICREFRESH = 83;\r
+ \r
+ LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);\r
+ \r
+ // Write configuration data to SDRAM device\r
+ if(u32DataBus == 0) // burst size 8\r
+ {\r
+ *((volatile uint32_t *)(u32BaseAddr | ((3UL | (2UL << 4)) << (u32ColAddrBits + 2 + 1))));\r
+ }\r
+ else // burst size 4\r
+ {\r
+ *((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2 + 2))));\r
+ }\r
+#endif // Validation board\r
+\r
+ LPC_EMC->DYNAMICCONTROL = 0;\r
+ LPC_EMC->DYNAMICCONFIG0 |= EMC_B_ENABLE; // Enable the buffers\r
+\r
+}\r
+\r
+\r
+/**********************************************************************\r
+ ** Function name:\r
+ **\r
+ ** Description:\r
+ **\r
+ ** Parameters:\r
+ **\r
+ ** Returned value:\r
+ **********************************************************************/\r
+static void vDelay(uint32_t u32Delay)\r
+{\r
+ volatile uint32_t i;\r
+ \r
+ for(i = 0; i < (u32Delay * delayBase1us); i++);\r
+}\r
+\r
--- /dev/null
+//BF: take over the whole file\r
+\r
+/***********************************************************************\r
+ * $Id: emc_LPC43xx.h 8389 2011-10-19 13:53:14Z nxp28536 $ emc_LPC18xx_43xx.h\r
+ *\r
+ * Project: NXP LPC18xx/LPC43xx Common\r
+ *\r
+ * Description: Header file for emc_LPC18xx_43xx.c\r
+ *\r
+ * Copyright(C) 2011, NXP Semiconductor\r
+ * All rights reserved.\r
+ *\r
+ ***********************************************************************\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * products. This software is supplied "AS IS" without any warranties.\r
+ * NXP Semiconductors assumes no responsibility or liability for the\r
+ * use of the software, conveys no license or title under any patent,\r
+ * copyright, or mask work right to the product. NXP Semiconductors\r
+ * reserves the right to make changes in the software without\r
+ * notification. NXP Semiconductors also make no representation or\r
+ * warranty that such application will be suitable for the specified\r
+ * use without further testing or modification.\r
+ **********************************************************************/\r
+\r
+#ifndef EMC_LPC43XX_H_\r
+#define EMC_LPC43XX_H_\r
+\r
+\r
+enum {\r
+ PART_WIDTH_8 = 0,\r
+ PART_WIDTH_16 = 1,\r
+ PART_WIDTH_32 = 2\r
+};\r
+\r
+enum {\r
+ PART_SIZE_16 = 0,\r
+ PART_SIZE_64 = 1,\r
+ PART_SIZE_128 = 2,\r
+ PART_SIZE_256 = 3,\r
+ PART_SIZE_512 = 4\r
+};\r
+\r
+enum {\r
+ EXT_WIDTH_16 = 0,\r
+ EXT_WIDTH_32 = 1\r
+};\r
+\r
+\r
+#if (PLATFORM == HITEX_A2_BOARD) //defined USE_HITEX_A2\r
+\r
+ #define SDRAM_SIZE 0x00800000 // 8 MByte SDRAM IS42S16400D-7TL\r
+ #define SDRAM_BASE 0x28000000 // base address for DYCS0\r
+\r
+ // We have 16 data lines connected to the SDRAM\r
+ #define PART_WIDTH (PART_WIDTH_16) // part width (possibly smaller than EXT_WIDTH, e.g. two 8-bit chips cascaded as 16-bit memory.\r
+ #define PART_SIZE (PART_SIZE_64)\r
+ #define EXT_WIDTH (EXT_WIDTH_16) // external memory bus width\r
+ #define COL_ADDR_BITS (8) // for calculating how to write mode bits\r
+\r
+#endif\r
+\r
+#if (PLATFORM == NXP_VALIDATION_BOARD)\r
+\r
+ #define SDRAM_SIZE 0x01000000 // 16 MByte SDRAM MT48LC4M32\r
+ #define SDRAM_BASE 0x28000000 // base address for DYCS0\r
+\r
+ // We have 32 data lines connected to the SDRAM\r
+ #define PART_WIDTH (PART_WIDTH_32) // part width (possibly smaller than EXT_WIDTH, e.g. two 8-bit chips cascaded as 16-bit memory.\r
+ #define PART_SIZE (PART_SIZE_128)\r
+ #define EXT_WIDTH (EXT_WIDTH_32) // external memory bus width\r
+ #define COL_ADDR_BITS (8) // for calculating how to write mode bits\r
+\r
+#endif\r
+\r
+\r
+\r
+// Function prototypes\r
+void EMC_Init( void );\r
+void EMC_Config_Pinmux( void );\r
+void EMC_Config_Static( void );\r
+void initEmiDelays( void );\r
+void EMC_Init_SRDRAM( uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits );\r
+\r
+\r
+#endif /* EMC_LPC43XX_H_ */\r
+\r
+\r
+\r
--- /dev/null
+/*********************************************************************** \r
+ * $Id: fpu_init.c \r
+ * \r
+ * Project: LPC43xx \r
+ * \r
+ * Description: fpu initialization routine\r
+ * \r
+ * Copyright(C) 2011, NXP Semiconductor\r
+ * All rights reserved.\r
+ * \r
+ ***********************************************************************\r
+ * Software that is described herein is for illustrative purposes only \r
+ * which provides customers with programming information regarding the \r
+ * products. This software is supplied "AS IS" without any warranties. \r
+ * NXP Semiconductors assumes no responsibility or liability for the \r
+ * use of the software, conveys no license or title under any patent, \r
+ * copyright, or mask work right to the product. NXP Semiconductors \r
+ * reserves the right to make changes in the software without \r
+ * notification. NXP Semiconductors also make no representation or \r
+ * warranty that such application will be suitable for the specified \r
+ * use without further testing or modification. \r
+ **********************************************************************/\r
+\r
+#define LPC_CPACR 0xE000ED88 \r
+\r
+#define SCB_MVFR0 0xE000EF40\r
+#define SCB_MVFR0_RESET 0x10110021\r
+\r
+#define SCB_MVFR1 0xE000EF44\r
+#define SCB_MVFR1_RESET 0x11000011\r
+\r
+#include "stdint.h"\r
+\r
+void fpuInit(void)\r
+{\r
+// from arm trm manual:\r
+// ; CPACR is located at address 0xE000ED88\r
+// LDR.W R0, =0xE000ED88\r
+// ; Read CPACR\r
+// LDR R1, [R0]\r
+// ; Set bits 20-23 to enable CP10 and CP11 coprocessors\r
+// ORR R1, R1, #(0xF << 20)\r
+// ; Write back the modified value to the CPACR\r
+// STR R1, [R0]\r
+\r
+ \r
+ volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR;\r
+ volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0;\r
+ volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1;\r
+ volatile uint32_t Cpacr;\r
+ volatile uint32_t Mvfr0;\r
+ volatile uint32_t Mvfr1; \r
+ char vfpPresent = 0;\r
+\r
+ Mvfr0 = *regMvfr0;\r
+ Mvfr1 = *regMvfr1;\r
+\r
+ vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));\r
+ \r
+ if(vfpPresent)\r
+ {\r
+ Cpacr = *regCpacr;\r
+ Cpacr |= (0xF << 20);\r
+ *regCpacr = Cpacr; // enable CP10 and CP11 for full access\r
+ }\r
+\r
+}\r
+\r
+\r
--- /dev/null
+/*********************************************************************** \r
+ * $Id: fpu_init.h \r
+ * \r
+ * Project: LPC43xx \r
+ * \r
+ * Description: fpu initialization routine header\r
+ * \r
+ * Copyright(C) 2011, NXP Semiconductor\r
+ * All rights reserved.\r
+ * \r
+ ***********************************************************************\r
+ * Software that is described herein is for illustrative purposes only \r
+ * which provides customers with programming information regarding the \r
+ * products. This software is supplied "AS IS" without any warranties. \r
+ * NXP Semiconductors assumes no responsibility or liability for the \r
+ * use of the software, conveys no license or title under any patent, \r
+ * copyright, or mask work right to the product. NXP Semiconductors \r
+ * reserves the right to make changes in the software without \r
+ * notification. NXP Semiconductors also make no representation or \r
+ * warranty that such application will be suitable for the specified \r
+ * use without further testing or modification. \r
+ **********************************************************************/\r
+\r
+#ifndef __FPU_INIT_H \r
+#define __FPU_INIT_H \r
+\r
+void fpuInit(void);\r
+\r
+#endif /* __FPU_INIT_H */\r
--- /dev/null
+/***********************************************************************\r
+ * $Id: scu.c 8242 2011-10-11 15:15:25Z nxp28536 $\r
+ *\r
+ * Project: LPC43xx Common\r
+ *\r
+ * Description:\r
+ * This file contains code to configure the PINMUX\r
+ *\r
+ ***********************************************************************\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * products. This software is supplied "AS IS" without any warranties.\r
+ * NXP Semiconductors assumes no responsibility or liability for the\r
+ * use of the software, conveys no license or title under any patent,\r
+ * copyright, or mask work right to the product. NXP Semiconductors\r
+ * reserves the right to make changes in the software without\r
+ * notification. NXP Semiconductors also make no representation or\r
+ * warranty that such application will be suitable for the specified\r
+ * use without further testing or modification.\r
+ **********************************************************************/\r
+\r
+#if defined CORE_M4\r
+#include "LPC43xx.h" /* LPC43xx definitions */\r
+#endif\r
+\r
+#ifdef CORE_M0\r
+#include "LPC43xx_M0.h" /* LPC43xx definitions */\r
+#endif\r
+\r
+#include "type.h"\r
+#include "scu.h"\r
+\r
+void scu_pinmux(unsigned port, unsigned pin, unsigned mode, unsigned func)\r
+{\r
+ volatile unsigned int * const scu_base=(unsigned int*)(LPC_SCU_BASE);\r
+ scu_base[(PORT_OFFSET*port+PIN_OFFSET*pin)/4]=mode+func;\r
+} /* scu_pinmux */\r
--- /dev/null
+/***********************************************************************\r
+ * $Id: scu.h 8389 2011-10-19 13:53:14Z nxp28536 $\r
+ *\r
+ * Project: LPC43xx Common\r
+ *\r
+ * Description:\r
+ * Header file for PINMUX configuration\r
+ *\r
+ ***********************************************************************\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * products. This software is supplied "AS IS" without any warranties.\r
+ * NXP Semiconductors assumes no responsibility or liability for the\r
+ * use of the software, conveys no license or title under any patent,\r
+ * copyright, or mask work right to the product. NXP Semiconductors\r
+ * reserves the right to make changes in the software without\r
+ * notification. NXP Semiconductors also make no representation or\r
+ * warranty that such application will be suitable for the specified\r
+ * use without further testing or modification.\r
+ **********************************************************************/\r
+#ifndef __SCU_H \r
+#define __SCU_H\r
+\r
+#define PORT_OFFSET 0x80\r
+#define PIN_OFFSET 0x04\r
+\r
+/* Pin modes */\r
+//#define MD_PUP (0x0<<3)\r
+//#define MD_BUK (0x1<<3)\r
+//#define MD_PLN (0x2<<3)\r
+//#define MD_PDN (0x3<<3)\r
+//#define MD_EHS (0x1<<5)\r
+//#define MD_EZI (0x1<<6)\r
+//#define MD_ZI (0x1<<7)\r
+//#define MD_EHD0 (0x1<<8)\r
+//#define MD_EHD1 (0x1<<8)\r
+\r
+/* Pin modes\r
+* ========= \r
+* The EPUN and EPD bits in the SFS registers allow the selection of weak on-chip\r
+* pull-up or pull-down resistors with a typical value of 50 kOhm for each pin or the\r
+* selection of the repeater mode.\r
+* The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no\r
+* pull-up/pull-down. The default value is pull-up enabled.\r
+*\r
+* The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables\r
+* the pull-down resistor if the pin is at a logic LOW. This causes the pin to retain its last\r
+* known state if it is configured as an input and is not driven externally. Repeater mode may\r
+* typically be used to prevent a pin from floating (and potentially using significant power if it\r
+* floats to an indeterminate state) if it is temporarily not driven.\r
+* \r
+* To be able to receive a digital signal, the input buffer must be enabled through bit EZI in\r
+* the pin configuration registers. By default, the input buffer is disabled.\r
+* For pads that support both a digital and an analog function, the input buffer must be\r
+* disabled before enabling the analog function\r
+* \r
+* All digital pins support a programmable glitch filter (bit ZIF), which can be switched on or\r
+* off. By default, the glitch filter is on. The glitch filter should be disabled for\r
+* clocking signals with frequencies higher than 30 MHz.\r
+* \r
+* Normal-drive and high-speed pins support a programmable slew rate (bit EHS) to select\r
+* between lower noise and low speed or higher noise and high speed . The typical\r
+* frequencies supported are 50 MHz/80 MHz for normal-drive pins and 75 MHz/180 MHz for\r
+* high-speed pins.\r
+*/\r
+\r
+/* these definitions allow to set or clear single configuration bits */\r
+#define PDN_SET (1 << 3)\r
+#define PDN_CLR (0)\r
+#define PUP_SET (0)\r
+#define PUP_CLR (1 << 4)\r
+\r
+/* these definitions allow to configure the port in one specific mode */\r
+/* within scu_pinmux() function */\r
+#define PDN_ENABLE (0x3 << 3) /* pull down */\r
+#define PUP_ENABLE (0x0 << 3) /* pull up */\r
+#define REPEATER_ENABLE (0x1 << 3) /* repeater */\r
+#define PLAIN_ENABLE (0x2 << 3) /* no pull up, no pull down (plain) */\r
+\r
+#define SLEWRATE_SLOW (0)\r
+#define SLEWRATE_FAST (1 << 5)\r
+\r
+/* enable / disable the input buffer */\r
+#define INBUF_ENABLE (1 << 6)\r
+#define INBUF_DISABLE (0)\r
+\r
+/* enable / disable the filter */\r
+#define FILTER_ENABLE (0)\r
+#define FILTER_DISABLE (1 << 7)\r
+\r
+/* define the drive strenght */\r
+#define DRIVE_8MA (0x1 << 8) // Drive strength of 8mA\r
+#define DRIVE_14MA (0x1 << 9) // Drive strength of 14mA\r
+#define DRIVE_20MA (0x3 << 8) // Drive strength of 20mA\r
+\r
+\r
+\r
+// Configuration examples for external memory bus pins\r
+#define EMC_OUT (PUP_CLR | SLEWRATE_FAST | FILTER_DISABLE) \r
+#define EMC_IO (PUP_CLR | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)\r
+\r
+// Configuration examples \r
+#define CLK_OUT (PUP_CLR | SLEWRATE_FAST | FILTER_DISABLE) \r
+#define CLK_IN (PUP_CLR | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)\r
+\r
+/* Pin functions */\r
+#define FUNC0 0x0\r
+#define FUNC1 0x1\r
+#define FUNC2 0x2\r
+#define FUNC3 0x3\r
+#define FUNC4 0x4\r
+#define FUNC5 0x5\r
+#define FUNC6 0x6\r
+#define FUNC7 0x7\r
+\r
+extern void scu_pinmux(unsigned port, unsigned pin, unsigned mode, unsigned func);\r
+\r
+#define LPC_SCU_PIN(po, pi) (*(volatile int *) (LPC_SCU_BASE + ((po) * 0x80) + ((pi) * 0x4)) )\r
+#define LPC_SCU_CLK(c) (*(volatile int *) (LPC_SCU_BASE + 0xC00 + ((c) * 0x4)) )\r
+\r
+\r
+#endif /* end __SCU_H */\r
+/*****************************************************************************\r
+** End Of File\r
+******************************************************************************/\r
--- /dev/null
+;/***********************************************************************\r
+; * $Id: startup_LPC43xx.s 8389 2011-10-19 13:53:14Z nxp28536 $\r
+; *\r
+; * Project: LPC43xx CMSIS Package\r
+; *\r
+; * Description: Cortex-M4 Core Device Startup File for the NXP LPC18xx \r
+; * Device Series.\r
+; *\r
+; * Copyright(C) 2011, NXP Semiconductor\r
+; * All rights reserved.\r
+; *\r
+; ***********************************************************************\r
+; * Software that is described herein is for illustrative purposes only\r
+; * which provides customers with programming information regarding the\r
+; * products. This software is supplied "AS IS" without any warranties.\r
+; * NXP Semiconductors assumes no responsibility or liability for the\r
+; * use of the software, conveys no license or title under any patent,\r
+; * copyright, or mask work right to the product. NXP Semiconductors\r
+; * reserves the right to make changes in the software without\r
+; * notification. NXP Semiconductors also make no representation or\r
+; * warranty that such application will be suitable for the specified\r
+; * use without further testing or modification.\r
+; **********************************************************************/\r
+\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000400\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000000\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __endVectors\r
+\r
+Sign_Value EQU 0x5A5A5A5A\r
+\r
+; IF :DEF:EXT_FLASH\r
+;\r
+;Signature_Size EQU 0x10\r
+; DCD 0x000200DA\r
+; DCD 0x00000000\r
+; DCD 0x00000000\r
+; DCD 0x00000000\r
+; SPACE Signature_Size \r
+; DCD __initial_sp\r
+; DCD Reset_Handler ; 1 Reset Handler\r
+; FILL 256 - 8 - 16\r
+; ENDIF\r
+\r
+\r
+__Vectors DCD __initial_sp ; 0 Top of Stack\r
+ DCD Reset_Handler ; 1 Reset Handler\r
+ DCD NMI_Handler ; 2 NMI Handler\r
+ DCD HardFault_Handler ; 3 Hard Fault Handler\r
+ DCD MemManage_Handler ; 4 MPU Fault Handler\r
+ DCD BusFault_Handler ; 5 Bus Fault Handler\r
+ DCD UsageFault_Handler ; 6 Usage Fault Handler\r
+ DCD Sign_Value ; 7 Reserved\r
+ DCD 0 ; 8 Reserved\r
+ DCD 0 ; 9 Reserved\r
+ DCD 0 ; 10 Reserved\r
+ DCD SVC_Handler ; 11 SVCall Handler \r
+ DCD DebugMon_Handler ; 12 Debug Monitor Handler\r
+ DCD 0 ; 13 Reserved\r
+ DCD PendSV_Handler ; 14 PendSV Handler \r
+ DCD SysTick_Handler ; 15 SysTick Handler \r
+\r
+ ; External Interrupts \r
+ DCD DAC_IRQHandler ; 16 D/A Converter\r
+ DCD M0_IRQHandler ; 17 M0 \r
+ DCD DMA_IRQHandler ; 18 General Purpose DMA\r
+ DCD 0 ; 19 Reserved\r
+ DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon\r
+ DCD ETH_IRQHandler ; 21 Ethernet\r
+ DCD SDIO_IRQHandler ; 22 SD/MMC\r
+ DCD LCD_IRQHandler ; 23 LCD\r
+ DCD USB0_IRQHandler ; 24 USB0\r
+ DCD USB1_IRQHandler ; 25 USB1\r
+ DCD SCT_IRQHandler ; 26 State Configurable Timer\r
+ DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer\r
+ DCD TIMER0_IRQHandler ; 28 Timer0\r
+ DCD TIMER1_IRQHandler ; 29 Timer1\r
+ DCD TIMER2_IRQHandler ; 30 Timer2\r
+ DCD TIMER3_IRQHandler ; 31 Timer3\r
+ DCD MCPWM_IRQHandler ; 32 Motor Control PWM\r
+ DCD ADC0_IRQHandler ; 33 A/D Converter 0\r
+ DCD I2C0_IRQHandler ; 34 I2C0\r
+ DCD I2C1_IRQHandler ; 35 I2C1\r
+ DCD SPI_IRQHandler ; 36 SPI\r
+ DCD ADC1_IRQHandler ; 37 A/D Converter 1\r
+ DCD SSP0_IRQHandler ; 38 SSP0\r
+ DCD SSP1_IRQHandler ; 39 SSP1\r
+ DCD UART0_IRQHandler ; 40 UART0\r
+ DCD UART1_IRQHandler ; 41 UART1\r
+ DCD UART2_IRQHandler ; 42 UART2\r
+ DCD UART3_IRQHandler ; 43 UART3\r
+ DCD I2S0_IRQHandler ; 44 I2S0\r
+ DCD I2S1_IRQHandler ; 45 I2S1\r
+ DCD SPIFI_IRQHandler ; 46 SPI Flash Interface\r
+ DCD SGPIO_IRQHandler ; 47 SGPIO\r
+ DCD GPIO0_IRQHandler ; 48 GPIO0\r
+ DCD GPIO1_IRQHandler ; 49 GPIO1\r
+ DCD GPIO2_IRQHandler ; 50 GPIO2\r
+ DCD GPIO3_IRQHandler ; 51 GPIO3\r
+ DCD GPIO4_IRQHandler ; 52 GPIO4\r
+ DCD GPIO5_IRQHandler ; 53 GPIO5\r
+ DCD GPIO6_IRQHandler ; 54 GPIO6\r
+ DCD GPIO7_IRQHandler ; 55 GPIO7\r
+ DCD GINT0_IRQHandler ; 56 GINT0\r
+ DCD GINT1_IRQHandler ; 57 GINT1\r
+ DCD EVRT_IRQHandler ; 58 Event Router\r
+ DCD CAN1_IRQHandler ; 59 C_CAN1\r
+ DCD 0 ; 60 Reserved\r
+ DCD VADC_IRQHandler ; 61 VADC\r
+ DCD ATIMER_IRQHandler ; 62 ATIMER\r
+ DCD RTC_IRQHandler ; 63 RTC\r
+ DCD 0 ; 64 Reserved\r
+ DCD WDT_IRQHandler ; 65 WDT\r
+ DCD 0 ; 66 Reserved\r
+ DCD CAN0_IRQHandler ; 67 C_CAN0\r
+ DCD QEI_IRQHandler ; 68 QEI\r
+\r
+__endVectors\r
+ \r
+ IF :LNOT::DEF:NO_CRP\r
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY\r
+CRP_Key DCD 0xFFFFFFFF\r
+ ENDIF\r
+\r
+ AREA |.text|, CODE, READONLY\r
+\r
+; Reset Handler\r
+\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT __main\r
+\r
+ IF :DEF:EXT_FLASH\r
+\r
+ ; Extend the address bus, as the bootloader configured only [A13:0]\r
+ ; *(uint32_t*)(0x40086320) = 0x000000F1; \r
+ ; P6_8: A14 (function 1) \r
+ LDR R0, =0x40086320\r
+ LDR R1, =0x000000F1\r
+ STR R1, [R0,#0]\r
+ ; *(uint32_t*)(0x4008631C) = 0x000000F1; \r
+ ; P6_7: A15 (function 1) \r
+ LDR R0, =0x4008631C\r
+ LDR R1, =0x000000F1\r
+ STR R1, [R0,#0] \r
+ ; *(uint32_t*)(0x400866C0) = 0x000000F2; \r
+ ; PD_16: A16 (function 2) \r
+ LDR R0, =0x400866C0\r
+ LDR R1, =0x000000F2\r
+ STR R1, [R0,#0] \r
+ ; *(uint32_t*)(0x400866BC) = 0x000000F2; \r
+ ; PD_15: A17 (function 2) \r
+ LDR R0, =0x400866BC\r
+ LDR R1, =0x000000F2\r
+ STR R1, [R0,#0] \r
+ ; *(uint32_t*)(0x40086700) = 0x000000F3; \r
+ ; PE_0: A18 (function 3) \r
+ LDR R0, =0x40086700\r
+ LDR R1, =0x000000F3\r
+ STR R1, [R0,#0] \r
+ ; *(uint32_t*)(0x40086704) = 0x000000F3; \r
+ ; PE_1: A19 (function 3) \r
+ LDR R0, =0x40086704\r
+ LDR R1, =0x000000F3\r
+ STR R1, [R0,#0] \r
+ ; *(uint32_t*)(0x40086708) = 0x000000F3; \r
+ ; PE_2: A20 (function 3) \r
+ LDR R0, =0x40086708\r
+ LDR R1, =0x000000F3\r
+ STR R1, [R0,#0] \r
+ ; *(uint32_t*)(0x4008670C) = 0x000000F3; \r
+ ; PE_3: A21 (function 3) \r
+ LDR R0, =0x4008670C\r
+ LDR R1, =0x000000F3\r
+ STR R1, [R0,#0] \r
+ ; *(uint32_t*)(0x40086710) = 0x000000F3; \r
+ ; PE_4: A22 (function 3) \r
+ LDR R0, =0x40086710\r
+ LDR R1, =0x000000F3\r
+ STR R1, [R0,#0]\r
+\r
+; IMPORT _startup_configureFlash\r
+; LDR R0, =_startup_configureFlash\r
+; NOP\r
+; NOP\r
+; NOP\r
+; BLX R0\r
+\r
+ ENDIF\r
+\r
+ LDR R0, =__main\r
+ BX R0\r
+ ENDP\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified) \r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+MemManage_Handler\\r
+ PROC\r
+ EXPORT MemManage_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+BusFault_Handler\\r
+ PROC\r
+ EXPORT BusFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+UsageFault_Handler\\r
+ PROC\r
+ EXPORT UsageFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+; FreeRTOS handler\r
+vPortSVCHandler\\r
+ PROC\r
+ EXPORT vPortSVCHandler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+SVC_Handler PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+DebugMon_Handler\\r
+ PROC\r
+ EXPORT DebugMon_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+; FreeRTOS handler\r
+xPortPendSVHandler\\r
+ PROC\r
+ EXPORT xPortPendSVHandler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+PendSV_Handler PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+; FreeRTOS handler\r
+xPortSysTickHandler\\r
+ PROC\r
+ EXPORT xPortSysTickHandler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+SysTick_Handler PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+Default_Handler PROC\r
+\r
+ EXPORT DAC_IRQHandler [WEAK]\r
+ EXPORT M0_IRQHandler [WEAK]\r
+ EXPORT DMA_IRQHandler [WEAK]\r
+ EXPORT FLASH_EEPROM_IRQHandler [WEAK]\r
+ EXPORT ETH_IRQHandler [WEAK]\r
+ EXPORT SDIO_IRQHandler [WEAK]\r
+ EXPORT LCD_IRQHandler [WEAK]\r
+ EXPORT USB0_IRQHandler [WEAK]\r
+ EXPORT USB1_IRQHandler [WEAK]\r
+ EXPORT SCT_IRQHandler [WEAK]\r
+ EXPORT RIT_IRQHandler [WEAK]\r
+ EXPORT TIMER0_IRQHandler [WEAK]\r
+ EXPORT TIMER1_IRQHandler [WEAK]\r
+ EXPORT TIMER2_IRQHandler [WEAK]\r
+ EXPORT TIMER3_IRQHandler [WEAK]\r
+ EXPORT MCPWM_IRQHandler [WEAK]\r
+ EXPORT ADC0_IRQHandler [WEAK]\r
+ EXPORT I2C0_IRQHandler [WEAK]\r
+ EXPORT I2C1_IRQHandler [WEAK]\r
+ EXPORT SPI_IRQHandler [WEAK]\r
+ EXPORT ADC1_IRQHandler [WEAK]\r
+ EXPORT SSP0_IRQHandler [WEAK]\r
+ EXPORT SSP1_IRQHandler [WEAK]\r
+ EXPORT UART0_IRQHandler [WEAK]\r
+ EXPORT UART1_IRQHandler [WEAK]\r
+ EXPORT UART2_IRQHandler [WEAK]\r
+ EXPORT UART3_IRQHandler [WEAK]\r
+ EXPORT I2S0_IRQHandler [WEAK]\r
+ EXPORT I2S1_IRQHandler [WEAK]\r
+ EXPORT SPIFI_IRQHandler [WEAK]\r
+ EXPORT SGPIO_IRQHandler [WEAK]\r
+ EXPORT GPIO0_IRQHandler [WEAK]\r
+ EXPORT GPIO1_IRQHandler [WEAK]\r
+ EXPORT GPIO2_IRQHandler [WEAK]\r
+ EXPORT GPIO3_IRQHandler [WEAK]\r
+ EXPORT GPIO4_IRQHandler [WEAK]\r
+ EXPORT GPIO5_IRQHandler [WEAK]\r
+ EXPORT GPIO6_IRQHandler [WEAK]\r
+ EXPORT GPIO7_IRQHandler [WEAK]\r
+ EXPORT GINT0_IRQHandler [WEAK]\r
+ EXPORT GINT1_IRQHandler [WEAK]\r
+ EXPORT EVRT_IRQHandler [WEAK]\r
+ EXPORT CAN1_IRQHandler [WEAK]\r
+ EXPORT VADC_IRQHandler [WEAK]\r
+ EXPORT ATIMER_IRQHandler [WEAK]\r
+ EXPORT RTC_IRQHandler [WEAK]\r
+ EXPORT WDT_IRQHandler [WEAK]\r
+ EXPORT CAN0_IRQHandler [WEAK]\r
+ EXPORT QEI_IRQHandler [WEAK]\r
+\r
+\r
+\r
+\r
+DAC_IRQHandler\r
+M0_IRQHandler\r
+DMA_IRQHandler\r
+FLASH_EEPROM_IRQHandler\r
+ETH_IRQHandler\r
+SDIO_IRQHandler\r
+LCD_IRQHandler\r
+USB0_IRQHandler\r
+USB1_IRQHandler\r
+SCT_IRQHandler\r
+RIT_IRQHandler\r
+TIMER0_IRQHandler\r
+TIMER1_IRQHandler\r
+TIMER2_IRQHandler\r
+TIMER3_IRQHandler\r
+MCPWM_IRQHandler\r
+ADC0_IRQHandler\r
+I2C0_IRQHandler\r
+I2C1_IRQHandler\r
+SPI_IRQHandler\r
+ADC1_IRQHandler\r
+SSP0_IRQHandler\r
+SSP1_IRQHandler\r
+UART0_IRQHandler\r
+UART1_IRQHandler\r
+UART2_IRQHandler\r
+UART3_IRQHandler\r
+I2S0_IRQHandler\r
+I2S1_IRQHandler\r
+SPIFI_IRQHandler\r
+SGPIO_IRQHandler\r
+GPIO0_IRQHandler\r
+GPIO1_IRQHandler\r
+GPIO2_IRQHandler\r
+GPIO3_IRQHandler\r
+GPIO4_IRQHandler\r
+GPIO5_IRQHandler\r
+GPIO6_IRQHandler\r
+GPIO7_IRQHandler\r
+GINT0_IRQHandler\r
+GINT1_IRQHandler\r
+EVRT_IRQHandler\r
+CAN1_IRQHandler\r
+VADC_IRQHandler\r
+ATIMER_IRQHandler\r
+RTC_IRQHandler\r
+WDT_IRQHandler\r
+CAN0_IRQHandler\r
+QEI_IRQHandler\r
+\r
+ B .\r
+\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+; User Initial Stack & Heap\r
+\r
+ IF :DEF:__MICROLIB\r
+ \r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+ \r
+ ELSE\r
+ \r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+ END\r
--- /dev/null
+/***********************************************************************\r
+ * $Id: system_LPC43xx.c 8389 2011-10-19 13:53:14Z nxp28536 $\r
+ *\r
+ * Project: LPC43xx Common\r
+ *\r
+ * Description:\r
+ * CMSIS Cortex-M4 Device Peripheral Access Layer Source File\r
+ * for the NXP LPC43xx Device Series \r
+ *\r
+ ***********************************************************************\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * products. This software is supplied "AS IS" without any warranties.\r
+ * NXP Semiconductors assumes no responsibility or liability for the\r
+ * use of the software, conveys no license or title under any patent,\r
+ * copyright, or mask work right to the product. NXP Semiconductors\r
+ * reserves the right to make changes in the software without\r
+ * notification. NXP Semiconductors also make no representation or\r
+ * warranty that such application will be suitable for the specified\r
+ * use without further testing or modification.\r
+ **********************************************************************/\r
+\r
+#include <stdint.h>\r
+#if defined CORE_M4\r
+#include "LPC43xx.h" /* LPC18xx definitions */\r
+#endif\r
+\r
+#ifdef CORE_M0\r
+#include "LPC43xx_M0.h" /* LPC18xx definitions */\r
+#endif\r
+\r
+#include "scu.h"\r
+#include "type.h"\r
+#include "config.h"\r
+\r
+\r
+/*--------------------- Clock Configuration ----------------------------------*/\r
+//#define OTP\r
+#define FLASH_SETUP 0\r
+#define FLASHCFG_Val 0x0000303A\r
+\r
+/*----------------------------------------------------------------------------\r
+ Check the register settings\r
+ *----------------------------------------------------------------------------*/\r
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))\r
+#define CHECK_RSVD(val, mask) (val & mask)\r
+\r
+/* Clock Configuration -------------------------------------------------------*/\r
+#if (CHECK_RSVD((SCS_Val), ~0x00000030))\r
+ #error "SCS: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))\r
+ #error "CLKSRCSEL: Value out of range!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))\r
+ #error "PLL0CFG: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))\r
+ #error "PLL1CFG: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))\r
+ #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))\r
+ #error "USBCLKCFG: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))\r
+ #error "PCLKSEL0: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))\r
+ #error "PCLKSEL1: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((PCONP_Val), 0x10100821))\r
+ #error "PCONP: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))\r
+ #error "CLKOUTCFG: Invalid values of reserved bits!"\r
+#endif\r
+\r
+/* Flash Accelerator Configuration -------------------------------------------*/\r
+#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))\r
+ #error "FLASHCFG: Invalid values of reserved bits!"\r
+#endif\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ DEFINES\r
+ *----------------------------------------------------------------------------*/\r
+uint32_t XtalFrequency = 0; \r
+uint32_t PL160M_0Frequency = 0; \r
+uint32_t PL160M_1Frequency = 0; \r
+uint32_t PL160M_2Frequency = 0; \r
+uint32_t PL550Frequency = 0; \r
+uint32_t PL550FracFrequency = 0; //New in Falcon\r
+uint32_t IDIVAFrequency = 0;\r
+uint32_t IDIVBFrequency = 0;\r
+uint32_t IDIVCFrequency = 0;\r
+uint32_t IDIVDFrequency = 0;\r
+uint32_t IDIVEFrequency = 0;\r
+uint32_t USB1Frequency = 0;\r
+uint32_t M4Frequency = 0;\r
+uint32_t SPIFIFrequency = 0;\r
+uint32_t SPIFrequency = 0;\r
+uint32_t EnetRxFrequency = 0;\r
+uint32_t EnetTxFrequency = 0;\r
+uint32_t EXTFrequency = 0;\r
+uint32_t VPB1Frequency = 0;\r
+uint32_t VPB3Frequency = 0;\r
+uint32_t LCDFrequency = 0;\r
+uint32_t SCIFrequency = 0;\r
+uint32_t VADCFrequency = 0; \r
+uint32_t SDIOFrequency = 0;\r
+uint32_t SSP0Frequency = 0;\r
+uint32_t SSP1Frequency = 0;\r
+uint32_t UART0Frequency = 0;\r
+uint32_t UART1Frequency = 0;\r
+uint32_t UART2Frequency = 0;\r
+uint32_t UART3Frequency = 0;\r
+uint32_t OUTFrequency = 0;\r
+uint32_t AOTESTFrequency = 0;\r
+uint32_t ISOFrequency = 0;\r
+uint32_t BSRFrequency = 0;\r
+uint32_t CLK_TESTFrequency = 0;\r
+uint32_t APLLFrequency = 0; \r
+uint32_t SPARE0Frequency = 0; \r
+uint32_t SPARE1Frequency = 0; \r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Setup the microcontroller system.\r
+ * \r
+ */\r
+void SystemInit(void)\r
+{\r
+#ifdef OTP \r
+ // Set IRC trim if OTP is not programmed.\r
+ if( *(uint32_t *)LPC_OTP_CTRL_BASE == 0x00FF || \r
+ *(uint32_t *)(LPC_OTP_CTRL_BASE+4) == 0x0000)\r
+ {\r
+ LPC_CREG->IRCTRM = IRC_TRIM_VAL;\r
+ }\r
+#else\r
+ LPC_CREG->IRCTRM = IRC_TRIM_VAL;\r
+#endif\r
+\r
+ // Set all GPIO as input.\r
+ LPC_GPIO0->DIR = 0x0000;\r
+ LPC_GPIO1->DIR = 0x0000;\r
+ LPC_GPIO2->DIR = 0x0000;\r
+ LPC_GPIO3->DIR = 0x0000;\r
+ LPC_GPIO4->DIR = 0x0000;\r
+ LPC_GPIO5->DIR = 0x0000;\r
+ LPC_GPIO6->DIR = 0x0000;\r
+ LPC_GPIO7->DIR = 0x0000;\r
+\r
+ // M4 runs on IRC by default\r
+ M4Frequency = IRC_OSC; \r
+ XtalFrequency = XTAL_FREQ;\r
+ EXTFrequency = EXT_FREQ;\r
+}\r
+\r
+/**\r
+ * Set Clock\r
+ *\r
+ * @param target PLL, source clock, division\r
+ * @return none\r
+ *\r
+ * @brief Setup a clock \r
+ */\r
+void SetClock(CLKBASE_Type target_clk, CLKSRC_Type src_clk, CLKDIV_Type div)\r
+{\r
+ volatile uint32_t target_clk_adr;\r
+ volatile uint8_t auto_block=TRUE;\r
+ uint32_t src_freq;\r
+\r
+ EnableSourceClk(src_clk);\r
+\r
+ switch(div)\r
+ {\r
+ case(DIV1): // Divide by 1 == no division\r
+ break;\r
+ case(DIV2): \r
+ LPC_CGU->IDIVA_CTRL = (src_clk<<24) | (1<<2) | AUTO_BLOCK; \r
+ IDIVAFrequency = GetClockFrequency(src_clk)/2;\r
+ src_clk = SRC_IDIV_0; // Set new src_clk for target_clk\r
+ break;\r
+ case(DIV4): \r
+ LPC_CGU->IDIVB_CTRL = (src_clk<<24) | (3<<2) |AUTO_BLOCK; \r
+ IDIVBFrequency = GetClockFrequency(src_clk)/4;\r
+ src_clk = SRC_IDIV_1; // Set new src_clk for target_clk\r
+ break;\r
+ case(DIV8): \r
+ LPC_CGU->IDIVC_CTRL = (src_clk<<24) | (7<<2) |AUTO_BLOCK; \r
+ IDIVCFrequency = GetClockFrequency(src_clk)/8;\r
+ src_clk = SRC_IDIV_2; // Set new src_clk for target_clk\r
+ break;\r
+ case(DIV16): \r
+ LPC_CGU->IDIVD_CTRL = (src_clk<<24) | (15<<2) |AUTO_BLOCK; \r
+ IDIVDFrequency = GetClockFrequency(src_clk)/16;\r
+ src_clk = SRC_IDIV_3; // Set new src_clk for target_clk\r
+ break;\r
+ case(DIV256):\r
+ LPC_CGU->IDIVE_CTRL = (src_clk<<24) | (255<<2) |AUTO_BLOCK; // MAX 128? IDIV bit 2:9 = 7 bits = 127 max\r
+ IDIVEFrequency = GetClockFrequency(src_clk)/256;\r
+ src_clk = SRC_IDIV_4; // Set new src_clk for target_clk\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ src_freq = GetClockFrequency(src_clk);\r
+\r
+ switch(target_clk)\r
+ {\r
+ case(BASE_OUT_CLK):\r
+ {\r
+ LPC_SCU->SFSCLK_0 = 1; // function 1; CGU clk out, diable pull down, disable pull-up\r
+ auto_block = FALSE;\r
+ break;\r
+ }\r
+ case(XTAL):\r
+ {\r
+ XtalFrequency = (uint32_t) src_clk; // convert target clock directly to frequency\r
+ break;\r
+ }\r
+ case(ENET_RX):\r
+ {\r
+ EnetRxFrequency = (uint32_t) src_clk; // convert target clock directly to frequency\r
+ break;\r
+ }\r
+ case(ENET_TX):\r
+ {\r
+ EnetTxFrequency = (uint32_t) src_clk; // convert target clock directly to frequency\r
+ break;\r
+ }\r
+ case(BASE_USB1_CLK):\r
+ {\r
+ USB1Frequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_M4_CLK):\r
+ {\r
+ M4Frequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_SPIFI_CLK):\r
+ {\r
+ SPIFIFrequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_SPI_CLK):\r
+ {\r
+ SPIFrequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_PHY_RX_CLK):\r
+ {\r
+ EnetRxFrequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_PHY_TX_CLK):\r
+ {\r
+ EnetTxFrequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_VPB1_CLK):\r
+ {\r
+ VPB1Frequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_VPB3_CLK):\r
+ {\r
+ VPB3Frequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_LCD_CLK):\r
+ {\r
+ LCDFrequency = src_freq;\r
+ break;\r
+ }\r
+ case (BASE_VADC_CLK) :\r
+ {\r
+ VADCFrequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_SDIO_CLK):\r
+ {\r
+ SDIOFrequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_SSP0_CLK):\r
+ {\r
+ SSP0Frequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_SSP1_CLK):\r
+ {\r
+ SSP1Frequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_UART0_CLK):\r
+ {\r
+ UART0Frequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_UART1_CLK):\r
+ {\r
+ UART1Frequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_UART2_CLK):\r
+ {\r
+ UART2Frequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_UART3_CLK):\r
+ {\r
+ UART3Frequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_AOTEST_CLK):\r
+ {\r
+ AOTESTFrequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_ISO_TCK):\r
+ {\r
+ ISOFrequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_BSR_TCK):\r
+ {\r
+ BSRFrequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_CLK_TEST):\r
+ {\r
+ CLK_TESTFrequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_APLL_CLK): //New in Falcon\r
+ {\r
+ APLLFrequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_SPARE0_CLK): //New in Falcon\r
+ {\r
+ SPARE0Frequency = src_freq;\r
+ break;\r
+ }\r
+ case(BASE_SPARE1_CLK): //New in Falcon\r
+ {\r
+ SPARE1Frequency = src_freq;\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ if(target_clk<200)\r
+ {\r
+ target_clk_adr = (uint32_t) &LPC_CGU->IDIVA_CTRL + (target_clk-2)*4; \r
+ *(uint32_t *)target_clk_adr = (src_clk<<24) | (auto_block<<11); \r
+ }\r
+}\r
+\r
+/**\r
+ * Get Clock Frequency\r
+ *\r
+ * @param source clock\r
+ * @return frequency\r
+ *\r
+ * @brief returns the current frequency of a base clock\r
+ */\r
+uint32_t GetClockFrequency(CLKSRC_Type src_clk)\r
+{\r
+ switch(src_clk)\r
+ {\r
+ case(SRC_OSC32K):\r
+ return RTC_CLK;\r
+ case(SRC_IRC):\r
+ return IRC_OSC;\r
+ case(SRC_ENET_RX_CLK):\r
+ return EnetRxFrequency;\r
+ case(SRC_ENET_TX_CLK):\r
+ return EnetTxFrequency;\r
+ case(SRC_EXT_TCK):\r
+ return EXTFrequency;\r
+ case(SRC_XTAL):\r
+ return XtalFrequency;\r
+ case(SRC_PL550M_0):\r
+ return PL550Frequency;\r
+ case(SRC_PL550M_FRAC): //New in Falcon\r
+ return PL550FracFrequency;\r
+ case(SRC_PL160M_0):\r
+ return PL160M_0Frequency;\r
+ case(SRC_PL160M_1):\r
+ return PL160M_1Frequency;\r
+ case(SRC_PL160M_2):\r
+ return PL160M_2Frequency;\r
+ case(SRC_IDIV_0):\r
+ return IDIVAFrequency;\r
+ case(SRC_IDIV_1):\r
+ return IDIVBFrequency;\r
+ case(SRC_IDIV_2):\r
+ return IDIVCFrequency;\r
+ case(SRC_IDIV_3):\r
+ return IDIVDFrequency;\r
+ case(SRC_IDIV_4):\r
+ return IDIVEFrequency;\r
+ default:\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * Set PL160M\r
+ *\r
+ * @param source clock, desired frequency \r
+ * @return none\r
+ *\r
+ * @brief Setup the PL160M PLL \r
+ * If frequency equals 0 then disable PLL\r
+ * Integer mode only (fbsel=1, direct=0) \r
+ * Fclkout = M * Fclkin/N \r
+ * Fcc0 = 2 * P * Fclkout = 2 * P * M * Fclkin/N \r
+ * msel+1 = feedback-divider value M (1 to 2^15) \r
+ * nsel+1 = pre-divider value N (1 to 2^8) \r
+ * psel+1 = post-divider value P(x2) (1 to 2^5) \r
+ */\r
+void SetPL160M(CLKSRC_Type src_clk, uint32_t mult) \r
+{\r
+ uint32_t msel=0, nsel=0, psel=0, pval=1; \r
+\r
+// EnableSourceClk(src_clk);\r
+\r
+ if(mult==0)\r
+ {\r
+ LPC_CGU->PLL1_CTRL |= PD_ENABLE; // Power down PLL\r
+ DisableSourceClk(src_clk);\r
+ }\r
+ else\r
+ {\r
+ EnableSourceClk(src_clk);\r
+ \r
+ switch(src_clk)\r
+ {\r
+ case(SRC_OSC32K):\r
+ PL160M_0Frequency = mult * RTC_CLK;\r
+ break;\r
+ case(SRC_IRC):\r
+ PL160M_0Frequency = mult * IRC_OSC;\r
+ break;\r
+ case(SRC_ENET_RX_CLK):\r
+ PL160M_0Frequency = mult * EnetRxFrequency;\r
+ break;\r
+ case(SRC_ENET_TX_CLK):\r
+ PL160M_0Frequency = mult * EnetTxFrequency;\r
+ break;\r
+ case(SRC_EXT_TCK):\r
+ PL160M_0Frequency = mult * EXTFrequency;\r
+ break;\r
+ case(SRC_XTAL):\r
+ PL160M_0Frequency = mult * XtalFrequency;\r
+ break;\r
+ default:\r
+ PL160M_0Frequency = mult * IRC_OSC;\r
+ break;\r
+ }\r
+ \r
+ // CCO must be in range of 156 - 320 MHz\r
+ // Increase P if FCCO is too low. \r
+ msel = mult-1;\r
+ //psel is encoded such that 0=1, 1=2, 2=4, 3=8\r
+ while(2*(pval)*PL160M_0Frequency < 156000000) {\r
+ psel++; \r
+ pval*=2;\r
+ }\r
+// if(2*(pval)*PL160M_0Frequency > 320000000) {\r
+// THIS IS OUT OF RANGE!!!\r
+// HOW DO WE ASSERT IN SAMPLE CODE?\r
+// __breakpoint(0);\r
+// }\r
+ LPC_CGU->PLL1_CTRL = (src_clk<<24) | (msel<<16) | (nsel<<12) | (psel<<8) | FBSEL;\r
+ while((LPC_CGU->PLL1_STAT&1) == 0x0); // Wait for PLL lock\r
+ }\r
+}\r
+\r
+/**\r
+ * Set PLL USB (PL550M)\r
+ *\r
+ * @param enable\r
+ * @return none\r
+ *\r
+ * @brief Setup the USB PLL to 480 MHz \r
+ * If enable equals 0 then disable PLL\r
+ * Only clock sources IRC and XTAL are valid\r
+ * Mode1a only: Normal operating mode without post- and pre-divider \r
+ * Fclkout = 2 * M * Fclkin\r
+ * msel+1 = feedback-divider value M (1 to 2^15) \r
+ */\r
+void SetPLLUSB(CLKSRC_Type src_clk, uint8_t enable)\r
+{\r
+ if(!enable)\r
+ {\r
+ LPC_CGU->PLL0USB_CTRL |= PD_ENABLE; // Power down PLL\r
+ }\r
+ else\r
+ {\r
+ // Setup PLL550 to generate 480MHz from 12 MHz crystal\r
+ LPC_CGU->PLL0USB_CTRL |= PD_ENABLE; // Power down PLL\r
+ // P N\r
+ LPC_CGU->PLL0USB_NP_DIV = (98<<0) | (514<<12);\r
+ // SELP SELI SELR MDEC \r
+ LPC_CGU->PLL0USB_MDIV = (0xB<<17)|(0x10<<22)|(0<<28)|(0x7FFA<<0); \r
+ LPC_CGU->PLL0USB_CTRL =(SRC_XTAL<<24) | (0x3<<2) | CLKEN; \r
+ \r
+ // Set the USB0 clock source to PLL550 (480MHz)\r
+ LPC_CGU->BASE_USB0_CLK = (0<<0) | (1<<11) | (SRC_PL550M_0<<24); \r
+ \r
+ while((LPC_CGU->PLL0USB_STAT&1) == 0x0); // Wait for PLL lock \r
+ }\r
+\r
+ PL550Frequency = 480000000UL;\r
+}\r
+\r
+/**\r
+ * Enable source clock pheripheral\r
+ *\r
+ * @param clock source\r
+ * @return none\r
+ *\r
+ * @brief Enable clock specific peripherals\r
+ */\r
+void EnableSourceClk(CLKSRC_Type src_clk)\r
+{\r
+ uint32_t i=0;\r
+\r
+ if(src_clk == SRC_OSC32K)\r
+ {\r
+ LPC_CREG->CREG0 &= ~((1<<3)|(1<<2)); // Active mode of 32 KHz osc and release reset\r
+ LPC_CREG->CREG0 |= (1<<1)|(1<<0); // Enable 32 kHz & 1 kHz on osc32k\r
+ }\r
+ if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PLAIN_ENABLE, FUNC3); // enet_rx_clk on PC_0 func 3\r
+ if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PLAIN_ENABLE, FUNC0); // enet_tx_clk on P1_19 func 0\r
+ if(src_clk == SRC_XTAL && (LPC_CGU->XTAL_OSC_CTRL&0x1))\r
+ {\r
+ LPC_CGU->XTAL_OSC_CTRL &= ~(1<<0); // Enable Xo50M\r
+ for(i=0;i<0xFFFF;i++);\r
+ }\r
+}\r
+\r
+/**\r
+ * Disable source clock pheripheral\r
+ *\r
+ * @param clock source\r
+ * @return none\r
+ *\r
+ * @brief Disable clock specific peripherals\r
+ */\r
+void DisableSourceClk(CLKSRC_Type src_clk)\r
+{\r
+ uint32_t i=0;\r
+\r
+ if(src_clk == SRC_OSC32K)\r
+ {\r
+ LPC_CREG->CREG0 &= ~((1<<1)|(1<<0)); // Disable 32 kHz & 1 kHz on osc32k\r
+ LPC_CREG->CREG0 |= ((1<<3)|(1<<2)); // osc32k in power down and in reset mode\r
+ }\r
+ if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PLAIN_ENABLE, FUNC0); // nc on PC_0 func 0\r
+ if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PLAIN_ENABLE, FUNC2); // nc on P1_19 func 2\r
+ if(src_clk == SRC_XTAL)\r
+ {\r
+ LPC_CGU->XTAL_OSC_CTRL = (1<<0); // Disable Xo50M\r
+ for(i=0;i<0xFFFF;i++);\r
+ }\r
+}\r
--- /dev/null
+/***********************************************************************\r
+ * $Id: system_LPC43xx.h 8242 2011-10-11 15:15:25Z nxp28536 $\r
+ *\r
+ * Project: LPC43xx Common\r
+ *\r
+ * Description:\r
+ * CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
+ * for the NXP LPC43xx Device Series\r
+ *\r
+ ***********************************************************************\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * products. This software is supplied "AS IS" without any warranties.\r
+ * NXP Semiconductors assumes no responsibility or liability for the\r
+ * use of the software, conveys no license or title under any patent,\r
+ * copyright, or mask work right to the product. NXP Semiconductors\r
+ * reserves the right to make changes in the software without\r
+ * notification. NXP Semiconductors also make no representation or\r
+ * warranty that such application will be suitable for the specified\r
+ * use without further testing or modification.\r
+ **********************************************************************/\r
+\r
+\r
+#ifndef __SYSTEM_LPC18xx_H\r
+#define __SYSTEM_LPC18xx_H\r
+\r
+#include <stdint.h>\r
+#include "scu.h"\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define BUTTON0 !((LPC_GPIO3->PIN>>6)&1) // P6.10\r
+#define BUTTON1 !((LPC_GPIO2->PIN>>0)&1) // P4.0\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ DO NOT SET MANUALLY, SET WITH SetClock AND SetPL160M\r
+ *----------------------------------------------------------------------------*/\r
+extern uint32_t XtalFrequency; \r
+extern uint32_t PL160M_0Frequency; \r
+extern uint32_t PL160M_1Frequency; \r
+extern uint32_t PL160M_2Frequency; \r
+extern uint32_t PL550Frequency; \r
+extern uint32_t PL550FracFrequency; //New in Falcon\r
+extern uint32_t IDIVAFrequency;\r
+extern uint32_t IDIVBFrequency;\r
+extern uint32_t IDIVCFrequency;\r
+extern uint32_t IDIVDFrequency;\r
+extern uint32_t IDIVEFrequency;\r
+extern uint32_t M0Frequency;\r
+extern uint32_t USB1Frequency;\r
+extern uint32_t M4Frequency;\r
+extern uint32_t SPIFIFrequency;\r
+extern uint32_t SPIFrequency;\r
+extern uint32_t EnetRxFrequency;\r
+extern uint32_t EnetTxFrequency;\r
+extern uint32_t EXTFrequency;\r
+extern uint32_t VPB1Frequency;\r
+extern uint32_t VPB3Frequency;\r
+extern uint32_t LCDFrequency;\r
+extern uint32_t SCIFrequency;\r
+extern uint32_t SDIOFrequency;\r
+extern uint32_t SSP0Frequency;\r
+extern uint32_t SSP1Frequency;\r
+extern uint32_t UART0Frequency;\r
+extern uint32_t UART1Frequency;\r
+extern uint32_t UART2Frequency;\r
+extern uint32_t UART3Frequency;\r
+extern uint32_t OUTFrequency;\r
+extern uint32_t AOTESTFrequency;\r
+extern uint32_t ISOFrequency;\r
+extern uint32_t BSRFrequency;\r
+extern uint32_t CLK_TESTFrequency;\r
+extern uint32_t APLLFrequency;\r
+extern uint32_t SPARE0Frequency;\r
+extern uint32_t SPARE1Frequency;\r
+\r
+\r
+typedef enum CLKDIV\r
+{\r
+ DIV1 = 1,\r
+ DIV2 = 2,\r
+ DIV4 = 4,\r
+ DIV8 = 8,\r
+ DIV16 = 16,\r
+ DIV256 = 256,\r
+} CLKDIV_Type;\r
+\r
+typedef enum CLKSRC\r
+{\r
+ SRC_OSC32K = 0,\r
+ SRC_IRC = 1,\r
+ SRC_ENET_RX_CLK = 2,\r
+ SRC_ENET_TX_CLK = 3,\r
+ SRC_EXT_TCK = 4,\r
+ RESERVED = 5, // Do NOT use\r
+ SRC_XTAL = 6,\r
+ SRC_PL550M_0 = 7,\r
+ SRC_PL550M_FRAC = 8, //New in Falcon\r
+ SRC_PL160M_0 = 9,\r
+ SRC_PL160M_1 = 10,\r
+ SRC_PL160M_2 = 11,\r
+ SRC_IDIV_0 = 12,\r
+ SRC_IDIV_1 = 13,\r
+ SRC_IDIV_2 = 14,\r
+ SRC_IDIV_3 = 15,\r
+ SRC_IDIV_4 = 16,\r
+ NOT_DEFINED = 0xFFFFFFF, // Force a signed int enum, so every possible frequency can be entered\r
+} CLKSRC_Type;\r
+\r
+typedef enum CLKBASE\r
+{\r
+ PL550M = 0, //PL550Frac is new, should be added???\r
+ PL160M = 1,\r
+ IDIVA_4 = 2,\r
+ IDIVB_16 = 3,\r
+ IDIVC_16 = 4,\r
+ IDIVD_16 = 5,\r
+ IDIVE_256 = 6,\r
+ BASE_SAFE_CLK = 7,\r
+ BASE_USB0_CLK = 8,\r
+ BASE_M0_CLK = 9,\r
+ BASE_USB1_CLK = 10,\r
+ BASE_M4_CLK = 11,\r
+ BASE_SPIFI_CLK = 12,\r
+ BASE_SPI_CLK = 13,\r
+ BASE_PHY_RX_CLK = 14,\r
+ BASE_PHY_TX_CLK = 15,\r
+ BASE_VPB1_CLK = 16,\r
+ BASE_VPB3_CLK = 17,\r
+ BASE_LCD_CLK = 18,\r
+ BASE_VADC_CLK = 19, //New\r
+ BASE_SDIO_CLK = 20,\r
+ BASE_SSP0_CLK = 21,\r
+ BASE_SSP1_CLK = 22,\r
+ BASE_UART0_CLK = 23,\r
+ BASE_UART1_CLK = 24,\r
+ BASE_UART2_CLK = 25,\r
+ BASE_UART3_CLK = 26,\r
+ BASE_OUT_CLK = 27,\r
+ BASE_AOTEST_CLK = 28,\r
+ BASE_ISO_TCK = 29,\r
+ BASE_BSR_TCK = 30,\r
+ BASE_CLK_TEST = 31,\r
+ BASE_APLL_CLK = 32, //New in Falcon\r
+ BASE_SPARE0_CLK = 33, //New in Falcon\r
+ BASE_SPARE1_CLK = 34, //New in Falcon\r
+ XTAL = 253,\r
+ ENET_RX = 254,\r
+ ENET_TX = 255,\r
+}CLKBASE_Type; \r
+\r
+// PL550M\r
+#define MODE1A (0x3<<2) // Normal operating mode without post-divider and without pre-divider \r
+#define MODE1B (0x2<<2) // Normal operating mode with post-divider and without pre-divider\r
+#define MODE1C (0x1<<2) // Normal operating mode without post-divider and with pre-divider\r
+#define MODE1D (0x0<<2) // Normal operating mode with post-divider and with pre-divider.\r
+#define BYPASSOFF (0<<1)\r
+#define CLKEN (1<<4)\r
+\r
+// PL160M\r
+#define FBSEL (1<<6)\r
+#define MSEL_FBDIV(n) (n<<16) // MSEL = feedback-divider value 2*M (1 to 2^15)\r
+#define NSEL_PREDIV(n) (n<<12) // NSEL = pre-divider value N (1 to 2^8) \r
+#define PSEL_POSTDIV(n) (n<<8) // PSEL = post-divider value P*2 (1 to 2^5)\r
+\r
+// Generic clock properties\r
+#define AUTO_BLOCK (1<<11)\r
+#define PD_ENABLE (1<<0)\r
+\r
+extern void SystemInit(void);\r
+extern void SetClock(CLKBASE_Type target_clk, CLKSRC_Type src_clk, CLKDIV_Type div);\r
+extern void SetPL160M(CLKSRC_Type src_clk, uint32_t mult);\r
+extern void SetPLLUSB(CLKSRC_Type src_clk, uint8_t enable);\r
+extern void EnableSourceClk(CLKSRC_Type src_clk);\r
+extern void DisableSourceClk(CLKSRC_Type src_clk);\r
+extern void IOInit(void);\r
+extern uint32_t GetClockFrequency(CLKSRC_Type src_clk);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SYSTEM_LPC43xx_H */\r
--- /dev/null
+/***********************************************************************\r
+ * $Id: type.h 8242 2011-10-11 15:15:25Z nxp28536 $\r
+ *\r
+ * Project: LPC43xx Common\r
+ *\r
+ * Description:\r
+ * Type definition Header file for NXP LPC4300 Family\r
+ * Microprocessors\r
+ *\r
+ ***********************************************************************\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * products. This software is supplied "AS IS" without any warranties.\r
+ * NXP Semiconductors assumes no responsibility or liability for the\r
+ * use of the software, conveys no license or title under any patent,\r
+ * copyright, or mask work right to the product. NXP Semiconductors\r
+ * reserves the right to make changes in the software without\r
+ * notification. NXP Semiconductors also make no representation or\r
+ * warranty that such application will be suitable for the specified\r
+ * use without further testing or modification.\r
+ **********************************************************************/\r
+\r
+#ifndef __TYPE_H__\r
+#define __TYPE_H__\r
+\r
+#ifndef NULL\r
+#define NULL ((void *)0)\r
+#endif\r
+\r
+#ifndef FALSE\r
+#define FALSE (0)\r
+#endif\r
+\r
+#ifndef TRUE\r
+#define TRUE (1)\r
+#endif\r
+\r
+#define ABS(value) (value<0 ? -value : value)\r
+\r
+/**\r
+ * @brief Flag Status and Interrupt Flag Status type definition\r
+ */\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;\r
+#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))\r
+\r
+/**\r
+ * @brief Functional State Definition\r
+ */\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))\r
+\r
+/**\r
+ * @ Status type definition\r
+ */\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;\r
+\r
+typedef unsigned char BYTE;\r
+typedef unsigned short WORD;\r
+typedef unsigned long DWORD;\r
+typedef unsigned int BOOL;\r
+\r
+typedef union _BITS\r
+{\r
+ unsigned char value;\r
+ struct _bits\r
+ {\r
+ unsigned char bit0:1;\r
+ unsigned char bit1:1;\r
+ unsigned char bit2:1;\r
+ unsigned char bit3:1;\r
+ unsigned char bit4:1;\r
+ unsigned char bit5:1;\r
+ unsigned char bit6:1;\r
+ unsigned char bit7:1;\r
+ }bits;\r
+}BITS;\r
+\r
+#endif /* __TYPE_H__ */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Ensure stdint is only used by the compiler, and not the assembler. */\r
+#ifdef __ICCARM__\r
+ #include <stdint.h>\r
+ extern uint32_t SystemCoreClock;\r
+#endif\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 1\r
+#define configCPU_CLOCK_HZ ( SystemCoreClock )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 75 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 10\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 4 /* 15 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+ \r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } \r
+ \r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. \r
+ * This file contains all the peripheral register's definitions, bits \r
+ * definitions and memory mapping for STM32F4xx devices.\r
+ * \r
+ * The file is the unique include file that the application programmer\r
+ * is using in the C source code, usually in main.c. This file contains:\r
+ * - Configuration section that allows to select:\r
+ * - The device used in the target application\r
+ * - To use or not the peripheral\92s drivers in application code(i.e. \r
+ * code will be based on direct access to peripheral\92s registers \r
+ * rather than drivers API), this option is controlled by \r
+ * "#define USE_STDPERIPH_DRIVER"\r
+ * - To change few application-specific parameters such as the HSE \r
+ * crystal frequency\r
+ * - Data structures and the address mapping for all peripherals\r
+ * - Peripheral's registers declarations and bits definition\r
+ * - Macros to access peripheral\92s registers hardware\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f4xx\r
+ * @{\r
+ */\r
+ \r
+#ifndef __STM32F4xx_H\r
+#define __STM32F4xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+ \r
+/** @addtogroup Library_configuration_section\r
+ * @{\r
+ */\r
+ \r
+/* Uncomment the line below according to the target STM32 device used in your\r
+ application \r
+ */\r
+\r
+#if !defined (STM32F4XX) \r
+ #define STM32F4XX\r
+#endif\r
+\r
+/* Tip: To avoid modifying this file each time you need to switch between these\r
+ devices, you can define the device in your toolchain compiler preprocessor.\r
+ */\r
+\r
+#if !defined (STM32F4XX)\r
+ #error "Please select first the target STM32F4XX device used in your application (in stm32f4xx.h file)"\r
+#endif\r
+\r
+#if !defined (USE_STDPERIPH_DRIVER)\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+ In this case, these drivers will not be included and the application code will \r
+ be based on direct access to peripherals registers \r
+ */\r
+ /*#define USE_STDPERIPH_DRIVER*/\r
+#endif /* USE_STDPERIPH_DRIVER */\r
+\r
+/**\r
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)\r
+ used in your application \r
+ \r
+ Tip: To avoid modifying this file each time you need to use different HSE, you\r
+ can define the HSE value in your toolchain compiler preprocessor.\r
+ */ \r
+\r
+#if !defined (HSE_VALUE) \r
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r
+#endif /* HSE_VALUE */\r
+\r
+/**\r
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup \r
+ Timeout value \r
+ */\r
+#if !defined (HSE_STARTUP_TIMEOUT) \r
+ #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */\r
+#endif /* HSE_STARTUP_TIMEOUT */ \r
+\r
+#if !defined (HSI_VALUE) \r
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */ \r
+\r
+/**\r
+ * @brief STM32F4XX Standard Peripherals Library version number V1.0.0\r
+ */\r
+#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ \r
+#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */\r
+#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
+#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ \r
+#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\\r
+ |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\\r
+ |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\\r
+ |(__STM32F4XX_STDPERIPH_VERSION_RC))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Configuration_section_for_CMSIS\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals \r
+ */\r
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */\r
+#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+#define __FPU_PRESENT 1 /*!< FPU present */\r
+\r
+/**\r
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device \r
+ * in @ref Library_configuration_section \r
+ */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */\r
+/****** STM32 specific Interrupt Numbers **********************************************************************/\r
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */\r
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */\r
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
+ RCC_IRQn = 5, /*!< RCC global Interrupt */\r
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */\r
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */\r
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */\r
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */\r
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */\r
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */\r
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */\r
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */\r
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */\r
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */\r
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */\r
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ \r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */\r
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ \r
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */\r
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */\r
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */\r
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */\r
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */\r
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */\r
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */\r
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */\r
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */\r
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */\r
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */\r
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */\r
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */\r
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */\r
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */\r
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */\r
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */\r
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */\r
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */\r
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */\r
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */\r
+ USART6_IRQn = 71, /*!< USART6 global interrupt */ \r
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */\r
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */\r
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */\r
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */\r
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */\r
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */\r
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */\r
+ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */\r
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */\r
+ FPU_IRQn = 81 /*!< FPU global interrupt */\r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */\r
+#include "system_stm32f4xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Exported_types\r
+ * @{\r
+ */ \r
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */\r
+typedef int32_t s32;\r
+typedef int16_t s16;\r
+typedef int8_t s8;\r
+\r
+typedef const int32_t sc32; /*!< Read Only */\r
+typedef const int16_t sc16; /*!< Read Only */\r
+typedef const int8_t sc8; /*!< Read Only */\r
+\r
+typedef __IO int32_t vs32;\r
+typedef __IO int16_t vs16;\r
+typedef __IO int8_t vs8;\r
+\r
+typedef __I int32_t vsc32; /*!< Read Only */\r
+typedef __I int16_t vsc16; /*!< Read Only */\r
+typedef __I int8_t vsc8; /*!< Read Only */\r
+\r
+typedef uint32_t u32;\r
+typedef uint16_t u16;\r
+typedef uint8_t u8;\r
+\r
+typedef const uint32_t uc32; /*!< Read Only */\r
+typedef const uint16_t uc16; /*!< Read Only */\r
+typedef const uint8_t uc8; /*!< Read Only */\r
+\r
+typedef __IO uint32_t vu32;\r
+typedef __IO uint16_t vu16;\r
+typedef __IO uint8_t vu8;\r
+\r
+typedef __I uint32_t vuc32; /*!< Read Only */\r
+typedef __I uint16_t vuc16; /*!< Read Only */\r
+typedef __I uint8_t vuc8; /*!< Read Only */\r
+\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
+\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief Analog to Digital Converter \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */\r
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ \r
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */\r
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */\r
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */\r
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\r
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\r
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\r
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\r
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */\r
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */\r
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */\r
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */\r
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */\r
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/\r
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */\r
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */\r
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */\r
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */\r
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */\r
+} ADC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */\r
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */\r
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual\r
+ AND triple modes, Address offset: ADC1 base address + 0x308 */\r
+} ADC_Common_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Controller Area Network TxMailBox \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */\r
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\r
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */\r
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */\r
+} CAN_TxMailBox_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network FIFOMailBox \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */\r
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\r
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\r
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\r
+} CAN_FIFOMailBox_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network FilterRegister \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\r
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\r
+} CAN_FilterRegister_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */\r
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */\r
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */\r
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */\r
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */\r
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */\r
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */\r
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */\r
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */\r
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */\r
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */\r
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */\r
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */\r
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */\r
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */\r
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */\r
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */\r
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */\r
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */\r
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ \r
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */\r
+} CAN_TypeDef;\r
+\r
+/** \r
+ * @brief CRC calculation unit \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\r
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\r
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */\r
+} CRC_TypeDef;\r
+\r
+/** \r
+ * @brief Digital to Analog Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\r
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\r
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\r
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\r
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */\r
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */\r
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */\r
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */\r
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */\r
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\r
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */\r
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\r
+} DAC_TypeDef;\r
+\r
+/** \r
+ * @brief Debug MCU\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\r
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\r
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */\r
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */\r
+}DBGMCU_TypeDef;\r
+\r
+/** \r
+ * @brief DCMI\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */\r
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */\r
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */\r
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */\r
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */\r
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */\r
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\r
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */\r
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */\r
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */\r
+} DCMI_TypeDef;\r
+\r
+/** \r
+ * @brief DMA Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DMA stream x configuration register */\r
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */\r
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */\r
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */\r
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */\r
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */\r
+} DMA_Stream_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */\r
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */\r
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */\r
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\r
+} DMA_TypeDef;\r
+\r
+/** \r
+ * @brief Ethernet MAC\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MACCR;\r
+ __IO uint32_t MACFFR;\r
+ __IO uint32_t MACHTHR;\r
+ __IO uint32_t MACHTLR;\r
+ __IO uint32_t MACMIIAR;\r
+ __IO uint32_t MACMIIDR;\r
+ __IO uint32_t MACFCR;\r
+ __IO uint32_t MACVLANTR; /* 8 */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t MACRWUFFR; /* 11 */\r
+ __IO uint32_t MACPMTCSR;\r
+ uint32_t RESERVED1[2];\r
+ __IO uint32_t MACSR; /* 15 */\r
+ __IO uint32_t MACIMR;\r
+ __IO uint32_t MACA0HR;\r
+ __IO uint32_t MACA0LR;\r
+ __IO uint32_t MACA1HR;\r
+ __IO uint32_t MACA1LR;\r
+ __IO uint32_t MACA2HR;\r
+ __IO uint32_t MACA2LR;\r
+ __IO uint32_t MACA3HR;\r
+ __IO uint32_t MACA3LR; /* 24 */\r
+ uint32_t RESERVED2[40];\r
+ __IO uint32_t MMCCR; /* 65 */\r
+ __IO uint32_t MMCRIR;\r
+ __IO uint32_t MMCTIR;\r
+ __IO uint32_t MMCRIMR;\r
+ __IO uint32_t MMCTIMR; /* 69 */\r
+ uint32_t RESERVED3[14];\r
+ __IO uint32_t MMCTGFSCCR; /* 84 */\r
+ __IO uint32_t MMCTGFMSCCR;\r
+ uint32_t RESERVED4[5];\r
+ __IO uint32_t MMCTGFCR;\r
+ uint32_t RESERVED5[10];\r
+ __IO uint32_t MMCRFCECR;\r
+ __IO uint32_t MMCRFAECR;\r
+ uint32_t RESERVED6[10];\r
+ __IO uint32_t MMCRGUFCR;\r
+ uint32_t RESERVED7[334];\r
+ __IO uint32_t PTPTSCR;\r
+ __IO uint32_t PTPSSIR;\r
+ __IO uint32_t PTPTSHR;\r
+ __IO uint32_t PTPTSLR;\r
+ __IO uint32_t PTPTSHUR;\r
+ __IO uint32_t PTPTSLUR;\r
+ __IO uint32_t PTPTSAR;\r
+ __IO uint32_t PTPTTHR;\r
+ __IO uint32_t PTPTTLR;\r
+ __IO uint32_t RESERVED8;\r
+ __IO uint32_t PTPTSSR;\r
+ uint32_t RESERVED9[565];\r
+ __IO uint32_t DMABMR;\r
+ __IO uint32_t DMATPDR;\r
+ __IO uint32_t DMARPDR;\r
+ __IO uint32_t DMARDLAR;\r
+ __IO uint32_t DMATDLAR;\r
+ __IO uint32_t DMASR;\r
+ __IO uint32_t DMAOMR;\r
+ __IO uint32_t DMAIER;\r
+ __IO uint32_t DMAMFBOCR;\r
+ __IO uint32_t DMARSWTR;\r
+ uint32_t RESERVED10[8];\r
+ __IO uint32_t DMACHTDR;\r
+ __IO uint32_t DMACHRDR;\r
+ __IO uint32_t DMACHTBAR;\r
+ __IO uint32_t DMACHRBAR;\r
+} ETH_TypeDef;\r
+\r
+/** \r
+ * @brief External Interrupt/Event Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */\r
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */\r
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */\r
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\r
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */\r
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */\r
+} EXTI_TypeDef;\r
+\r
+/** \r
+ * @brief FLASH Registers\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */\r
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */\r
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */\r
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */\r
+ __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */\r
+} FLASH_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ \r
+} FSMC_Bank1_TypeDef; \r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller Bank1E\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
+} FSMC_Bank1E_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller Bank2\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */\r
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */\r
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */\r
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */\r
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */\r
+} FSMC_Bank2_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller Bank3\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */\r
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */\r
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */\r
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x90 */\r
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */\r
+} FSMC_Bank3_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller Bank4\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */\r
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */\r
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */\r
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */\r
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */\r
+} FSMC_Bank4_TypeDef; \r
+\r
+/** \r
+ * @brief General Purpose I/O\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\r
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\r
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\r
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\r
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\r
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\r
+ __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */\r
+ __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */\r
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\r
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */\r
+} GPIO_TypeDef;\r
+\r
+/** \r
+ * @brief System configuration controller\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */\r
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */\r
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ \r
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */\r
+} SYSCFG_TypeDef;\r
+\r
+/** \r
+ * @brief Inter-integrated Circuit Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
+ __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
+ __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
+ __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */\r
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
+ __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */\r
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
+ __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */\r
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
+ __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */\r
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */\r
+ __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */\r
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */\r
+} I2C_TypeDef;\r
+\r
+/** \r
+ * @brief Independent WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */\r
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */\r
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */\r
+} IWDG_TypeDef;\r
+\r
+/** \r
+ * @brief Power Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */\r
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */\r
+} PWR_TypeDef;\r
+\r
+/** \r
+ * @brief Reset and Clock Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\r
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */\r
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */\r
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */\r
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */\r
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */\r
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */\r
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */\r
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */\r
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */\r
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */\r
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */\r
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */\r
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */\r
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */\r
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */\r
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\r
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\r
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\r
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */\r
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\r
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\r
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */\r
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */\r
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */\r
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */\r
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */\r
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */\r
+} RCC_TypeDef;\r
+\r
+/** \r
+ * @brief Real-Time Clock\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\r
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\r
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */\r
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */\r
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */\r
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */\r
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */\r
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */\r
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\r
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */\r
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\r
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\r
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\r
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\r
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */\r
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\r
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */\r
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */\r
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */\r
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */\r
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */\r
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */\r
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */\r
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */\r
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */\r
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */\r
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */\r
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */\r
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */\r
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */\r
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */\r
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */\r
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */\r
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */\r
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */\r
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */\r
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */\r
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */\r
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */\r
+} RTC_TypeDef;\r
+\r
+/** \r
+ * @brief SD host Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */\r
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */\r
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */\r
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */\r
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */\r
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */\r
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */\r
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */\r
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */\r
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */\r
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */\r
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */\r
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */\r
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */\r
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */\r
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */\r
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */\r
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */\r
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */\r
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */\r
+} SDIO_TypeDef;\r
+\r
+/** \r
+ * @brief Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
+ __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
+ __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
+ __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\r
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
+ __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */\r
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
+ __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */\r
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
+ __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */\r
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */\r
+ __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */\r
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */\r
+} SPI_TypeDef;\r
+\r
+/** \r
+ * @brief TIM\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
+ __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
+ __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
+ __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */\r
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
+ __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\r
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
+ __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
+ __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */\r
+ __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\r
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */\r
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\r
+ __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */\r
+ uint16_t RESERVED9; /*!< Reserved, 0x2A */\r
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\r
+ __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\r
+ uint16_t RESERVED10; /*!< Reserved, 0x32 */\r
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\r
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\r
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\r
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\r
+ __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\r
+ uint16_t RESERVED11; /*!< Reserved, 0x46 */\r
+ __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */\r
+ uint16_t RESERVED12; /*!< Reserved, 0x4A */\r
+ __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */\r
+ uint16_t RESERVED13; /*!< Reserved, 0x4E */\r
+ __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */\r
+ uint16_t RESERVED14; /*!< Reserved, 0x52 */\r
+} TIM_TypeDef;\r
+\r
+/** \r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
+ __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
+ __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
+ __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */\r
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
+ __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */\r
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
+ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */\r
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
+} USART_TypeDef;\r
+\r
+/** \r
+ * @brief Window WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\r
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\r
+} WWDG_TypeDef;\r
+\r
+/** \r
+ * @brief Crypto Processor\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */\r
+ __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */\r
+ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */\r
+ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */\r
+ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */\r
+ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */\r
+ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */\r
+ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */\r
+ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */\r
+ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */\r
+ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */\r
+ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */\r
+ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */\r
+ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */\r
+ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */\r
+ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */\r
+ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */\r
+ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */\r
+ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */\r
+} CRYP_TypeDef;\r
+\r
+/** \r
+ * @brief HASH\r
+ */\r
+ \r
+typedef struct \r
+{\r
+ __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */\r
+ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */\r
+ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */\r
+ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */\r
+ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */\r
+ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */\r
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */\r
+ __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ \r
+} HASH_TypeDef;\r
+\r
+/** \r
+ * @brief HASH\r
+ */\r
+ \r
+typedef struct \r
+{\r
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */\r
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */\r
+} RNG_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_memory_map\r
+ * @{\r
+ */\r
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */\r
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */\r
+#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */\r
+#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */\r
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */\r
+#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */\r
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */\r
+\r
+#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */\r
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */\r
+#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */\r
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */\r
+#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */\r
+\r
+/* Legacy defines */\r
+#define SRAM_BASE SRAM1_BASE\r
+#define SRAM_BB_BASE SRAM1_BB_BASE\r
+\r
+\r
+/*!< Peripheral memory map */\r
+#define APB1PERIPH_BASE PERIPH_BASE\r
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)\r
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)\r
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)\r
+\r
+/*!< APB1 peripherals */\r
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)\r
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)\r
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)\r
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)\r
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)\r
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)\r
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)\r
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)\r
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)\r
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)\r
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)\r
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)\r
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)\r
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)\r
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)\r
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)\r
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)\r
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)\r
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)\r
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)\r
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)\r
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)\r
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)\r
+\r
+/*!< APB2 peripherals */\r
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)\r
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)\r
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)\r
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)\r
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)\r
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)\r
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)\r
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)\r
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)\r
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)\r
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)\r
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)\r
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)\r
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)\r
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)\r
+\r
+/*!< AHB1 peripherals */\r
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)\r
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)\r
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)\r
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)\r
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)\r
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)\r
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)\r
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)\r
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)\r
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)\r
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)\r
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)\r
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)\r
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)\r
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)\r
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)\r
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)\r
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)\r
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)\r
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)\r
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)\r
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)\r
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)\r
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)\r
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)\r
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)\r
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)\r
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)\r
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)\r
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)\r
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)\r
+#define ETH_MAC_BASE (ETH_BASE)\r
+#define ETH_MMC_BASE (ETH_BASE + 0x0100)\r
+#define ETH_PTP_BASE (ETH_BASE + 0x0700)\r
+#define ETH_DMA_BASE (ETH_BASE + 0x1000)\r
+\r
+/*!< AHB2 peripherals */\r
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)\r
+#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)\r
+#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)\r
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)\r
+\r
+/*!< FSMC Bankx registers base address */\r
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)\r
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)\r
+#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)\r
+#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)\r
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)\r
+\r
+/* Debug MCU registers base address */\r
+#define DBGMCU_BASE ((uint32_t )0xE0042000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_declaration\r
+ * @{\r
+ */ \r
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)\r
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)\r
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)\r
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\r
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)\r
+#define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#define USART3 ((USART_TypeDef *) USART3_BASE)\r
+#define UART4 ((USART_TypeDef *) UART4_BASE)\r
+#define UART5 ((USART_TypeDef *) UART5_BASE)\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)\r
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)\r
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)\r
+#define PWR ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC ((DAC_TypeDef *) DAC_BASE)\r
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\r
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\r
+#define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#define USART6 ((USART_TypeDef *) USART6_BASE)\r
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)\r
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)\r
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)\r
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\r
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)\r
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)\r
+#define CRC ((CRC_TypeDef *) CRC_BASE)\r
+#define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\r
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\r
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\r
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\r
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\r
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\r
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\r
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\r
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\r
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\r
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\r
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\r
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\r
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\r
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\r
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\r
+#define ETH ((ETH_TypeDef *) ETH_BASE) \r
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)\r
+#define CRYP ((CRYP_TypeDef *) CRYP_BASE)\r
+#define HASH ((HASH_TypeDef *) HASH_BASE)\r
+#define RNG ((RNG_TypeDef *) RNG_BASE)\r
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\r
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\r
+#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)\r
+#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)\r
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)\r
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_constants\r
+ * @{\r
+ */\r
+ \r
+ /** @addtogroup Peripheral_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+ \r
+/******************************************************************************/\r
+/* Peripheral Registers_Bits_Definition */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Analog to Digital Converter */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for ADC_SR register ********************/\r
+#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */\r
+#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */\r
+#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */\r
+#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */\r
+#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */\r
+#define ADC_SR_OVR ((uint8_t)0x20) /*!<Overrun flag */\r
+\r
+/******************* Bit definition for ADC_CR1 register ********************/\r
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */\r
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */\r
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */\r
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */\r
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */\r
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */\r
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */\r
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */\r
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */\r
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */\r
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */\r
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */\r
+ \r
+/******************* Bit definition for ADC_CR2 register ********************/\r
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */\r
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */\r
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */\r
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */\r
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */\r
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */\r
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */\r
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\r
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */\r
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\r
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\r
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */\r
+\r
+/****************** Bit definition for ADC_SMPR1 register *******************/\r
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\r
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\r
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\r
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\r
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\r
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\r
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\r
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\r
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\r
+#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for ADC_SMPR2 register *******************/\r
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\r
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\r
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\r
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\r
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\r
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\r
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\r
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\r
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\r
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\r
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR1 register *******************/\r
+#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */\r
+\r
+/****************** Bit definition for ADC_JOFR2 register *******************/\r
+#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR3 register *******************/\r
+#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */\r
+\r
+/****************** Bit definition for ADC_JOFR4 register *******************/\r
+#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */\r
+\r
+/******************* Bit definition for ADC_HTR register ********************/\r
+#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */\r
+\r
+/******************* Bit definition for ADC_LTR register ********************/\r
+#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */\r
+\r
+/******************* Bit definition for ADC_SQR1 register *******************/\r
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */\r
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for ADC_SQR2 register *******************/\r
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR3 register *******************/\r
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for ADC_JSQR register *******************/\r
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ \r
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */\r
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for ADC_JDR1 register *******************/\r
+#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR2 register *******************/\r
+#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR3 register *******************/\r
+#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR4 register *******************/\r
+#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************** Bit definition for ADC_DR register ********************/\r
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */\r
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */\r
+\r
+/******************* Bit definition for ADC_CSR register ********************/\r
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */\r
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */\r
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */\r
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */\r
+#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */\r
+#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */\r
+#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */\r
+#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */\r
+#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */\r
+#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */\r
+#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */\r
+#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */\r
+#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */\r
+#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */\r
+#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */\r
+\r
+/******************* Bit definition for ADC_CCR register ********************/\r
+#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ \r
+#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ \r
+#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */\r
+#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ \r
+#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */\r
+#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */\r
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */ \r
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */\r
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */\r
+\r
+/******************* Bit definition for ADC_CDR register ********************/\r
+#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */\r
+#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Controller Area Network */\r
+/* */\r
+/******************************************************************************/\r
+/*!<CAN control and status registers */\r
+/******************* Bit definition for CAN_MCR register ********************/\r
+#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */\r
+#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */\r
+#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */\r
+#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */\r
+#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */\r
+#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */\r
+#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */\r
+#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */\r
+#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */\r
+\r
+/******************* Bit definition for CAN_MSR register ********************/\r
+#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */\r
+#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */\r
+#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */\r
+#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */\r
+#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */\r
+#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */\r
+#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */\r
+#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */\r
+#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */\r
+\r
+/******************* Bit definition for CAN_TSR register ********************/\r
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */\r
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */\r
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */\r
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */\r
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */\r
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */\r
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */\r
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */\r
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */\r
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */\r
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */\r
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */\r
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */\r
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */\r
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */\r
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */\r
+\r
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */\r
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */\r
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */\r
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */\r
+\r
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */\r
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */\r
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */\r
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */\r
+\r
+/******************* Bit definition for CAN_RF0R register *******************/\r
+#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */\r
+#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */\r
+#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */\r
+#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */\r
+\r
+/******************* Bit definition for CAN_RF1R register *******************/\r
+#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */\r
+#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */\r
+#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */\r
+#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */\r
+\r
+/******************** Bit definition for CAN_IER register *******************/\r
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */\r
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */\r
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */\r
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */\r
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */\r
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */\r
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */\r
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */\r
+\r
+/******************** Bit definition for CAN_ESR register *******************/\r
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */\r
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */\r
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */\r
+\r
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */\r
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+\r
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */\r
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */\r
+\r
+/******************* Bit definition for CAN_BTR register ********************/\r
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */\r
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */\r
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */\r
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */\r
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */\r
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */\r
+\r
+/*!<Mailbox registers */\r
+/****************** Bit definition for CAN_TI0R register ********************/\r
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/****************** Bit definition for CAN_TDT0R register *******************/\r
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/****************** Bit definition for CAN_TDL0R register *******************/\r
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/****************** Bit definition for CAN_TDH0R register *******************/\r
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI1R register *******************/\r
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT1R register ******************/\r
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL1R register ******************/\r
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH1R register ******************/\r
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI2R register *******************/\r
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */\r
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT2R register ******************/ \r
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL2R register ******************/\r
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH2R register ******************/\r
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI0R register *******************/\r
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT0R register ******************/\r
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */\r
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL0R register ******************/\r
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH0R register ******************/\r
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI1R register *******************/\r
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */\r
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT1R register ******************/\r
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */\r
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL1R register ******************/\r
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH1R register ******************/\r
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/*!<CAN filter registers */\r
+/******************* Bit definition for CAN_FMR register ********************/\r
+#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */\r
+\r
+/******************* Bit definition for CAN_FM1R register *******************/\r
+#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */\r
+#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */\r
+#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */\r
+#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */\r
+#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */\r
+#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */\r
+#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */\r
+#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */\r
+#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */\r
+#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */\r
+#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */\r
+#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */\r
+#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */\r
+#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */\r
+#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */\r
+\r
+/******************* Bit definition for CAN_FS1R register *******************/\r
+#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */\r
+#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */\r
+#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */\r
+#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */\r
+#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */\r
+#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */\r
+#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */\r
+#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */\r
+#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */\r
+#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */\r
+#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */\r
+#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */\r
+#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */\r
+#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */\r
+#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */\r
+\r
+/****************** Bit definition for CAN_FFA1R register *******************/\r
+#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */\r
+#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */\r
+#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */\r
+#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */\r
+#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */\r
+#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */\r
+#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */\r
+#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */\r
+#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */\r
+#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */\r
+#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */\r
+#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */\r
+#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */\r
+#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */\r
+#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */\r
+\r
+/******************* Bit definition for CAN_FA1R register *******************/\r
+#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */\r
+#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */\r
+#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */\r
+#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */\r
+#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */\r
+#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */\r
+#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */\r
+#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */\r
+#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */\r
+#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */\r
+#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */\r
+#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */\r
+#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */\r
+#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */\r
+#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */\r
+\r
+/******************* Bit definition for CAN_F0R1 register *******************/\r
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R1 register *******************/\r
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R1 register *******************/\r
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R1 register *******************/\r
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R1 register *******************/\r
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R1 register *******************/\r
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R1 register *******************/\r
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R1 register *******************/\r
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R1 register *******************/\r
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R1 register *******************/\r
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R1 register ******************/\r
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R1 register ******************/\r
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R1 register ******************/\r
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R1 register ******************/\r
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F0R2 register *******************/\r
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R2 register *******************/\r
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R2 register *******************/\r
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R2 register *******************/\r
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R2 register *******************/\r
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R2 register *******************/\r
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R2 register *******************/\r
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R2 register *******************/\r
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R2 register *******************/\r
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R2 register *******************/\r
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R2 register ******************/\r
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R2 register ******************/\r
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R2 register ******************/\r
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R2 register ******************/\r
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CRC calculation unit */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for CRC_DR register *********************/\r
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\r
+\r
+\r
+/******************* Bit definition for CRC_IDR register ********************/\r
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */\r
+\r
+\r
+/******************** Bit definition for CRC_CR register ********************/\r
+#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Crypto Processor */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bits definition for CRYP_CR register ********************/\r
+#define CRYP_CR_ALGODIR ((uint32_t)0x00000004)\r
+\r
+#define CRYP_CR_ALGOMODE ((uint32_t)0x00000038)\r
+#define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)\r
+#define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)\r
+#define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)\r
+#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)\r
+#define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)\r
+#define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)\r
+#define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)\r
+#define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)\r
+#define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)\r
+#define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)\r
+#define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)\r
+\r
+#define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)\r
+#define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)\r
+#define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)\r
+#define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)\r
+#define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)\r
+#define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)\r
+#define CRYP_CR_FFLUSH ((uint32_t)0x00004000)\r
+#define CRYP_CR_CRYPEN ((uint32_t)0x00008000)\r
+/****************** Bits definition for CRYP_SR register *********************/\r
+#define CRYP_SR_IFEM ((uint32_t)0x00000001)\r
+#define CRYP_SR_IFNF ((uint32_t)0x00000002)\r
+#define CRYP_SR_OFNE ((uint32_t)0x00000004)\r
+#define CRYP_SR_OFFU ((uint32_t)0x00000008)\r
+#define CRYP_SR_BUSY ((uint32_t)0x00000010)\r
+/****************** Bits definition for CRYP_DMACR register ******************/\r
+#define CRYP_DMACR_DIEN ((uint32_t)0x00000001)\r
+#define CRYP_DMACR_DOEN ((uint32_t)0x00000002)\r
+/***************** Bits definition for CRYP_IMSCR register ******************/\r
+#define CRYP_IMSCR_INIM ((uint32_t)0x00000001)\r
+#define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)\r
+/****************** Bits definition for CRYP_RISR register *******************/\r
+#define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)\r
+#define CRYP_RISR_INRIS ((uint32_t)0x00000002)\r
+/****************** Bits definition for CRYP_MISR register *******************/\r
+#define CRYP_MISR_INMIS ((uint32_t)0x00000001)\r
+#define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital to Analog Converter */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DAC_CR register ********************/\r
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */\r
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */\r
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */\r
+\r
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */\r
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */\r
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */\r
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */\r
+\r
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */\r
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */\r
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */\r
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */\r
+\r
+/***************** Bit definition for DAC_SWTRIGR register ******************/\r
+#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */\r
+#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */\r
+\r
+/***************** Bit definition for DAC_DHR12R1 register ******************/\r
+#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L1 register ******************/\r
+#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R1 register ******************/\r
+#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12R2 register ******************/\r
+#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L2 register ******************/\r
+#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R2 register ******************/\r
+#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12RD register ******************/\r
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12LD register ******************/\r
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8RD register ******************/\r
+#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */\r
+#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/******************* Bit definition for DAC_DOR1 register *******************/\r
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */\r
+\r
+/******************* Bit definition for DAC_DOR2 register *******************/\r
+#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */\r
+\r
+/******************** Bit definition for DAC_SR register ********************/\r
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */\r
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Debug MCU */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DCMI */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DCMI_CR register ******************/\r
+#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)\r
+#define DCMI_CR_CM ((uint32_t)0x00000002)\r
+#define DCMI_CR_CROP ((uint32_t)0x00000004)\r
+#define DCMI_CR_JPEG ((uint32_t)0x00000008)\r
+#define DCMI_CR_ESS ((uint32_t)0x00000010)\r
+#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)\r
+#define DCMI_CR_HSPOL ((uint32_t)0x00000040)\r
+#define DCMI_CR_VSPOL ((uint32_t)0x00000080)\r
+#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)\r
+#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)\r
+#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)\r
+#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)\r
+#define DCMI_CR_CRE ((uint32_t)0x00001000)\r
+#define DCMI_CR_ENABLE ((uint32_t)0x00004000)\r
+\r
+/******************** Bits definition for DCMI_SR register ******************/\r
+#define DCMI_SR_HSYNC ((uint32_t)0x00000001)\r
+#define DCMI_SR_VSYNC ((uint32_t)0x00000002)\r
+#define DCMI_SR_FNE ((uint32_t)0x00000004)\r
+\r
+/******************** Bits definition for DCMI_RISR register ****************/\r
+#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)\r
+#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)\r
+#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)\r
+#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)\r
+#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)\r
+\r
+/******************** Bits definition for DCMI_IER register *****************/\r
+#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)\r
+#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)\r
+#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)\r
+#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)\r
+#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)\r
+\r
+/******************** Bits definition for DCMI_MISR register ****************/\r
+#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)\r
+#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)\r
+#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)\r
+#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)\r
+#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)\r
+\r
+/******************** Bits definition for DCMI_ICR register *****************/\r
+#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)\r
+#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)\r
+#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)\r
+#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)\r
+#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DMA Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DMA_SxCR register *****************/ \r
+#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)\r
+#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)\r
+#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)\r
+#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) \r
+#define DMA_SxCR_MBURST ((uint32_t)0x01800000)\r
+#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)\r
+#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)\r
+#define DMA_SxCR_PBURST ((uint32_t)0x00600000)\r
+#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)\r
+#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)\r
+#define DMA_SxCR_ACK ((uint32_t)0x00100000)\r
+#define DMA_SxCR_CT ((uint32_t)0x00080000) \r
+#define DMA_SxCR_DBM ((uint32_t)0x00040000)\r
+#define DMA_SxCR_PL ((uint32_t)0x00030000)\r
+#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)\r
+#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)\r
+#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)\r
+#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)\r
+#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)\r
+#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)\r
+#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)\r
+#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)\r
+#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)\r
+#define DMA_SxCR_MINC ((uint32_t)0x00000400)\r
+#define DMA_SxCR_PINC ((uint32_t)0x00000200)\r
+#define DMA_SxCR_CIRC ((uint32_t)0x00000100)\r
+#define DMA_SxCR_DIR ((uint32_t)0x000000C0)\r
+#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)\r
+#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)\r
+#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)\r
+#define DMA_SxCR_TCIE ((uint32_t)0x00000010)\r
+#define DMA_SxCR_HTIE ((uint32_t)0x00000008)\r
+#define DMA_SxCR_TEIE ((uint32_t)0x00000004)\r
+#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)\r
+#define DMA_SxCR_EN ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_SxCNDTR register **************/\r
+#define DMA_SxNDT ((uint32_t)0x0000FFFF)\r
+#define DMA_SxNDT_0 ((uint32_t)0x00000001)\r
+#define DMA_SxNDT_1 ((uint32_t)0x00000002)\r
+#define DMA_SxNDT_2 ((uint32_t)0x00000004)\r
+#define DMA_SxNDT_3 ((uint32_t)0x00000008)\r
+#define DMA_SxNDT_4 ((uint32_t)0x00000010)\r
+#define DMA_SxNDT_5 ((uint32_t)0x00000020)\r
+#define DMA_SxNDT_6 ((uint32_t)0x00000040)\r
+#define DMA_SxNDT_7 ((uint32_t)0x00000080)\r
+#define DMA_SxNDT_8 ((uint32_t)0x00000100)\r
+#define DMA_SxNDT_9 ((uint32_t)0x00000200)\r
+#define DMA_SxNDT_10 ((uint32_t)0x00000400)\r
+#define DMA_SxNDT_11 ((uint32_t)0x00000800)\r
+#define DMA_SxNDT_12 ((uint32_t)0x00001000)\r
+#define DMA_SxNDT_13 ((uint32_t)0x00002000)\r
+#define DMA_SxNDT_14 ((uint32_t)0x00004000)\r
+#define DMA_SxNDT_15 ((uint32_t)0x00008000)\r
+\r
+/******************** Bits definition for DMA_SxFCR register ****************/ \r
+#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)\r
+#define DMA_SxFCR_FS ((uint32_t)0x00000038)\r
+#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)\r
+#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)\r
+#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)\r
+#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)\r
+#define DMA_SxFCR_FTH ((uint32_t)0x00000003)\r
+#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)\r
+#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)\r
+\r
+/******************** Bits definition for DMA_LISR register *****************/ \r
+#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)\r
+#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)\r
+#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)\r
+#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)\r
+#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)\r
+#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)\r
+#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)\r
+#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)\r
+#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)\r
+#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)\r
+#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)\r
+#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)\r
+#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)\r
+#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)\r
+#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)\r
+#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)\r
+#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)\r
+#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)\r
+#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)\r
+#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_HISR register *****************/ \r
+#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)\r
+#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)\r
+#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)\r
+#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)\r
+#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)\r
+#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)\r
+#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)\r
+#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)\r
+#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)\r
+#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)\r
+#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)\r
+#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)\r
+#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)\r
+#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)\r
+#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)\r
+#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)\r
+#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)\r
+#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)\r
+#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)\r
+#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_LIFCR register ****************/ \r
+#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)\r
+#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)\r
+#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)\r
+#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)\r
+#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)\r
+#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)\r
+#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)\r
+#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)\r
+#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)\r
+#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)\r
+#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)\r
+#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)\r
+#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)\r
+#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)\r
+#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)\r
+#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)\r
+#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)\r
+#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)\r
+#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)\r
+#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_HIFCR register ****************/ \r
+#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)\r
+#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)\r
+#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)\r
+#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)\r
+#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)\r
+#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)\r
+#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)\r
+#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)\r
+#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)\r
+#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)\r
+#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)\r
+#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)\r
+#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)\r
+#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)\r
+#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)\r
+#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)\r
+#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)\r
+#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)\r
+#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)\r
+#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* External Interrupt/Event Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for EXTI_IMR register *******************/\r
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */\r
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */\r
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */\r
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */\r
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */\r
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */\r
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */\r
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */\r
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */\r
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */\r
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */\r
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */\r
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */\r
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */\r
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */\r
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */\r
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */\r
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */\r
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */\r
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */\r
+\r
+/******************* Bit definition for EXTI_EMR register *******************/\r
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */\r
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */\r
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */\r
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */\r
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */\r
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */\r
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */\r
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */\r
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */\r
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */\r
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */\r
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */\r
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */\r
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */\r
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */\r
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */\r
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */\r
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */\r
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */\r
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */\r
+\r
+/****************** Bit definition for EXTI_RTSR register *******************/\r
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */\r
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */\r
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */\r
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */\r
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */\r
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */\r
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */\r
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */\r
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */\r
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */\r
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */\r
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */\r
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */\r
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */\r
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */\r
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */\r
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */\r
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */\r
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */\r
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */\r
+\r
+/****************** Bit definition for EXTI_FTSR register *******************/\r
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */\r
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */\r
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */\r
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */\r
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */\r
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */\r
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */\r
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */\r
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */\r
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */\r
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */\r
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */\r
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */\r
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */\r
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */\r
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */\r
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */\r
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */\r
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */\r
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */\r
+\r
+/****************** Bit definition for EXTI_SWIER register ******************/\r
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */\r
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */\r
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */\r
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */\r
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */\r
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */\r
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */\r
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */\r
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */\r
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */\r
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */\r
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */\r
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */\r
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */\r
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */\r
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */\r
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */\r
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */\r
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */\r
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */\r
+\r
+/******************* Bit definition for EXTI_PR register ********************/\r
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */\r
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */\r
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */\r
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */\r
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */\r
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */\r
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */\r
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */\r
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */\r
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */\r
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */\r
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */\r
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */\r
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */\r
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */\r
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */\r
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */\r
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */\r
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */\r
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* FLASH */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bits definition for FLASH_ACR register *****************/\r
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000007)\r
+#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)\r
+#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)\r
+#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)\r
+#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)\r
+#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)\r
+#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)\r
+#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)\r
+#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)\r
+\r
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)\r
+#define FLASH_ACR_ICEN ((uint32_t)0x00000200)\r
+#define FLASH_ACR_DCEN ((uint32_t)0x00000400)\r
+#define FLASH_ACR_ICRST ((uint32_t)0x00000800)\r
+#define FLASH_ACR_DCRST ((uint32_t)0x00001000)\r
+#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)\r
+#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)\r
+\r
+/******************* Bits definition for FLASH_SR register ******************/\r
+#define FLASH_SR_EOP ((uint32_t)0x00000001)\r
+#define FLASH_SR_SOP ((uint32_t)0x00000002)\r
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010)\r
+#define FLASH_SR_PGAERR ((uint32_t)0x00000020)\r
+#define FLASH_SR_PGPERR ((uint32_t)0x00000040)\r
+#define FLASH_SR_PGSERR ((uint32_t)0x00000080)\r
+#define FLASH_SR_BSY ((uint32_t)0x00010000)\r
+\r
+/******************* Bits definition for FLASH_CR register ******************/\r
+#define FLASH_CR_PG ((uint32_t)0x00000001)\r
+#define FLASH_CR_SER ((uint32_t)0x00000002)\r
+#define FLASH_CR_MER ((uint32_t)0x00000004)\r
+#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)\r
+#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)\r
+#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)\r
+#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)\r
+#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)\r
+#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)\r
+#define FLASH_CR_STRT ((uint32_t)0x00010000)\r
+#define FLASH_CR_EOPIE ((uint32_t)0x01000000)\r
+#define FLASH_CR_LOCK ((uint32_t)0x80000000)\r
+\r
+/******************* Bits definition for FLASH_OPTCR register ***************/\r
+#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)\r
+#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)\r
+#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)\r
+#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)\r
+#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)\r
+#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)\r
+#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)\r
+#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)\r
+#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)\r
+#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)\r
+#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)\r
+#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)\r
+#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)\r
+#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)\r
+#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)\r
+#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)\r
+#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)\r
+#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)\r
+#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)\r
+#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)\r
+#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)\r
+#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)\r
+#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)\r
+#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)\r
+#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)\r
+#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)\r
+#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)\r
+#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Flexible Static Memory Controller */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for FSMC_BCR1 register *******************/\r
+#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BCR2 register *******************/\r
+#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BCR3 register *******************/\r
+#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit. */\r
+#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BCR4 register *******************/\r
+#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BTR1 register ******************/\r
+#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BTR2 register *******************/\r
+#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for FSMC_BTR3 register *******************/\r
+#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BTR4 register *******************/\r
+#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR1 register ******************/\r
+#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR2 register ******************/\r
+#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/\r
+#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR3 register ******************/\r
+#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR4 register ******************/\r
+#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_PCR2 register *******************/\r
+#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
+#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
+\r
+#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
+\r
+#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */\r
+#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FSMC_PCR3 register *******************/\r
+#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
+#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
+\r
+#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
+\r
+#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
+#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FSMC_PCR4 register *******************/\r
+#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
+#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
+\r
+#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
+\r
+#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
+#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+\r
+/******************* Bit definition for FSMC_SR2 register *******************/\r
+#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
+#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
+#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
+#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
+#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
+\r
+/******************* Bit definition for FSMC_SR3 register *******************/\r
+#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
+#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
+#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
+#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
+#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
+\r
+/******************* Bit definition for FSMC_SR4 register *******************/\r
+#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
+#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
+#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
+#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
+#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
+\r
+/****************** Bit definition for FSMC_PMEM2 register ******************/\r
+#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\r
+#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\r
+#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\r
+#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\r
+#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PMEM3 register ******************/\r
+#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r
+#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r
+#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r
+#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r
+#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PMEM4 register ******************/\r
+#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */\r
+#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */\r
+#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */\r
+#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */\r
+#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PATT2 register ******************/\r
+#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\r
+#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\r
+#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\r
+#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\r
+#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PATT3 register ******************/\r
+#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r
+#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r
+#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r
+#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r
+#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PATT4 register ******************/\r
+#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */\r
+#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */\r
+#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */\r
+#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */\r
+#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PIO4 register *******************/\r
+#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */\r
+#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */\r
+#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */\r
+#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\r
+#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_ECCR2 register ******************/\r
+#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
+\r
+/****************** Bit definition for FSMC_ECCR3 register ******************/\r
+#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* General Purpose I/O */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bits definition for GPIO_MODER register *****************/\r
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)\r
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)\r
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)\r
+\r
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)\r
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)\r
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)\r
+\r
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)\r
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)\r
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)\r
+\r
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)\r
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)\r
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)\r
+\r
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)\r
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)\r
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)\r
+\r
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)\r
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)\r
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)\r
+\r
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)\r
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)\r
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)\r
+\r
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)\r
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)\r
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)\r
+\r
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)\r
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)\r
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)\r
+\r
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)\r
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)\r
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)\r
+\r
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)\r
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)\r
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)\r
+\r
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)\r
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)\r
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)\r
+\r
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)\r
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)\r
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)\r
+\r
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)\r
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)\r
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)\r
+\r
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)\r
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)\r
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)\r
+\r
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)\r
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)\r
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)\r
+\r
+/****************** Bits definition for GPIO_OTYPER register ****************/\r
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)\r
+\r
+/****************** Bits definition for GPIO_OSPEEDR register ***************/\r
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)\r
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)\r
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)\r
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)\r
+\r
+/****************** Bits definition for GPIO_PUPDR register *****************/\r
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)\r
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)\r
+\r
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)\r
+\r
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)\r
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)\r
+\r
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)\r
+\r
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)\r
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)\r
+\r
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)\r
+\r
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)\r
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)\r
+\r
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)\r
+\r
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)\r
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)\r
+\r
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)\r
+\r
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)\r
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)\r
+\r
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)\r
+\r
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)\r
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)\r
+\r
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)\r
+\r
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)\r
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)\r
+\r
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)\r
+\r
+/****************** Bits definition for GPIO_IDR register *******************/\r
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)\r
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)\r
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)\r
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)\r
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)\r
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)\r
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)\r
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)\r
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)\r
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)\r
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)\r
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)\r
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)\r
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)\r
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)\r
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)\r
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */\r
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0\r
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1\r
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2\r
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3\r
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4\r
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5\r
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6\r
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7\r
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8\r
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9\r
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10\r
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11\r
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12\r
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13\r
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14\r
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15\r
+\r
+/****************** Bits definition for GPIO_ODR register *******************/\r
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)\r
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)\r
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)\r
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)\r
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)\r
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)\r
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)\r
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)\r
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)\r
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)\r
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)\r
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)\r
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)\r
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)\r
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)\r
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)\r
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */\r
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0\r
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1\r
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2\r
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3\r
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4\r
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5\r
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6\r
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7\r
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8\r
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9\r
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10\r
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11\r
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12\r
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13\r
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14\r
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15\r
+\r
+/****************** Bits definition for GPIO_BSRR register ******************/\r
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)\r
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)\r
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)\r
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)\r
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)\r
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)\r
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)\r
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)\r
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)\r
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)\r
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)\r
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)\r
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)\r
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)\r
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)\r
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)\r
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)\r
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)\r
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)\r
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)\r
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)\r
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)\r
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)\r
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)\r
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)\r
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)\r
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)\r
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)\r
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)\r
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)\r
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)\r
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* HASH */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bits definition for HASH_CR register ********************/\r
+#define HASH_CR_INIT ((uint32_t)0x00000004)\r
+#define HASH_CR_DMAE ((uint32_t)0x00000008)\r
+#define HASH_CR_DATATYPE ((uint32_t)0x00000030)\r
+#define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)\r
+#define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)\r
+#define HASH_CR_MODE ((uint32_t)0x00000040)\r
+#define HASH_CR_ALGO ((uint32_t)0x00000080)\r
+#define HASH_CR_NBW ((uint32_t)0x00000F00)\r
+#define HASH_CR_NBW_0 ((uint32_t)0x00000100)\r
+#define HASH_CR_NBW_1 ((uint32_t)0x00000200)\r
+#define HASH_CR_NBW_2 ((uint32_t)0x00000400)\r
+#define HASH_CR_NBW_3 ((uint32_t)0x00000800)\r
+#define HASH_CR_DINNE ((uint32_t)0x00001000)\r
+#define HASH_CR_LKEY ((uint32_t)0x00010000)\r
+\r
+/****************** Bits definition for HASH_STR register *******************/\r
+#define HASH_STR_NBW ((uint32_t)0x0000001F)\r
+#define HASH_STR_NBW_0 ((uint32_t)0x00000001)\r
+#define HASH_STR_NBW_1 ((uint32_t)0x00000002)\r
+#define HASH_STR_NBW_2 ((uint32_t)0x00000004)\r
+#define HASH_STR_NBW_3 ((uint32_t)0x00000008)\r
+#define HASH_STR_NBW_4 ((uint32_t)0x00000010)\r
+#define HASH_STR_DCAL ((uint32_t)0x00000100)\r
+\r
+/****************** Bits definition for HASH_IMR register *******************/\r
+#define HASH_IMR_DINIM ((uint32_t)0x00000001)\r
+#define HASH_IMR_DCIM ((uint32_t)0x00000002)\r
+\r
+/****************** Bits definition for HASH_SR register ********************/\r
+#define HASH_SR_DINIS ((uint32_t)0x00000001)\r
+#define HASH_SR_DCIS ((uint32_t)0x00000002)\r
+#define HASH_SR_DMAS ((uint32_t)0x00000004)\r
+#define HASH_SR_BUSY ((uint32_t)0x00000008)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Inter-integrated Circuit Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for I2C_CR1 register ********************/\r
+#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */\r
+#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */\r
+#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */\r
+#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */\r
+#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */\r
+#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */\r
+#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */\r
+#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */\r
+#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */\r
+#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */\r
+#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */\r
+#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */\r
+#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */\r
+#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */\r
+\r
+/******************* Bit definition for I2C_CR2 register ********************/\r
+#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */\r
+#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+\r
+#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */\r
+#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */\r
+#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */\r
+#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */\r
+#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */\r
+\r
+/******************* Bit definition for I2C_OAR1 register *******************/\r
+#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */\r
+#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */\r
+\r
+#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */\r
+#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */\r
+#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */\r
+#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */\r
+\r
+#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */\r
+\r
+/******************* Bit definition for I2C_OAR2 register *******************/\r
+#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */\r
+#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */\r
+\r
+/******************** Bit definition for I2C_DR register ********************/\r
+#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */\r
+\r
+/******************* Bit definition for I2C_SR1 register ********************/\r
+#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */\r
+#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */\r
+#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */\r
+#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */\r
+#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */\r
+#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */\r
+#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */\r
+#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */\r
+#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */\r
+#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */\r
+#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */\r
+#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */\r
+#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */\r
+#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */\r
+\r
+/******************* Bit definition for I2C_SR2 register ********************/\r
+#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */\r
+#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */\r
+#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */\r
+#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */\r
+#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */\r
+#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */\r
+#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */\r
+#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */\r
+\r
+/******************* Bit definition for I2C_CCR register ********************/\r
+#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */\r
+#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */\r
+#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */\r
+\r
+/****************** Bit definition for I2C_TRISE register *******************/\r
+#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Independent WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */\r
+\r
+/******************* Bit definition for IWDG_PR register ********************/\r
+#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */\r
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */\r
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */\r
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */\r
+\r
+/******************* Bit definition for IWDG_RLR register *******************/\r
+#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */\r
+\r
+/******************* Bit definition for IWDG_SR register ********************/\r
+#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */\r
+#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Power Control */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for PWR_CR register ********************/\r
+#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */\r
+#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */\r
+#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */\r
+#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */\r
+#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */\r
+\r
+#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */\r
+#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */\r
+#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */\r
+#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */\r
+\r
+\r
+/*!< PVD level configuration */\r
+#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */\r
+#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */\r
+#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */\r
+#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */\r
+#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */\r
+#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */\r
+#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */\r
+#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */\r
+\r
+#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */\r
+#define PWR_CR_FPDS ((uint16_t)0x0200) /*!< Flash power down in Stop mode */\r
+#define PWR_CR_VOS ((uint16_t)0x4000) /*!< Regulator voltage scaling output selection */\r
+/* Legacy define */\r
+#define PWR_CR_PMODE PWR_CR_VOS\r
+\r
+/******************* Bit definition for PWR_CSR register ********************/\r
+#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */\r
+#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */\r
+#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */\r
+#define PWR_CSR_BRR ((uint16_t)0x0008) /*!< Backup regulator ready */\r
+#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */\r
+#define PWR_CSR_BRE ((uint16_t)0x0200) /*!< Backup regulator enable */\r
+#define PWR_CSR_VOSRDY ((uint16_t)0x4000) /*!< Regulator voltage scaling output selection ready */\r
+/* Legacy define */\r
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Reset and Clock Control */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for RCC_CR register ********************/\r
+#define RCC_CR_HSION ((uint32_t)0x00000001)\r
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)\r
+\r
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)\r
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */\r
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */\r
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */\r
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */\r
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */\r
+\r
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)\r
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */\r
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */\r
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */\r
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */\r
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */\r
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */\r
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */\r
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */\r
+\r
+#define RCC_CR_HSEON ((uint32_t)0x00010000)\r
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)\r
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)\r
+#define RCC_CR_CSSON ((uint32_t)0x00080000)\r
+#define RCC_CR_PLLON ((uint32_t)0x01000000)\r
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)\r
+#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)\r
+#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)\r
+\r
+/******************** Bit definition for RCC_PLLCFGR register ***************/\r
+#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)\r
+#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)\r
+#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)\r
+#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)\r
+#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)\r
+#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)\r
+#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)\r
+\r
+#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)\r
+#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)\r
+#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)\r
+#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)\r
+#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)\r
+#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)\r
+#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)\r
+#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)\r
+#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)\r
+#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)\r
+\r
+#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)\r
+#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)\r
+#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)\r
+\r
+#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)\r
+#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)\r
+#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)\r
+\r
+#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)\r
+#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)\r
+#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)\r
+#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)\r
+#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)\r
+\r
+/******************** Bit definition for RCC_CFGR register ******************/\r
+/*!< SW configuration */\r
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */\r
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+\r
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */\r
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */\r
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */\r
+\r
+/*!< SWS configuration */\r
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
+\r
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */\r
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */\r
+\r
+/*!< HPRE configuration */\r
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */\r
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */\r
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */\r
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */\r
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */\r
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */\r
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */\r
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */\r
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */\r
+\r
+/*!< PPRE1 configuration */\r
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */\r
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+\r
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */\r
+\r
+/*!< PPRE2 configuration */\r
+#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */\r
+\r
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */\r
+\r
+/*!< RTCPRE configuration */\r
+#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)\r
+#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)\r
+#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)\r
+#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)\r
+#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)\r
+#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)\r
+\r
+/*!< MCO1 configuration */\r
+#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)\r
+#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)\r
+#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)\r
+\r
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)\r
+\r
+#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)\r
+#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)\r
+#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)\r
+#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)\r
+\r
+#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)\r
+#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)\r
+#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)\r
+#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)\r
+\r
+#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)\r
+#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)\r
+#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_CIR register *******************/\r
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)\r
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)\r
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)\r
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)\r
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)\r
+#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)\r
+#define RCC_CIR_CSSF ((uint32_t)0x00000080)\r
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)\r
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)\r
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)\r
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)\r
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)\r
+#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)\r
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)\r
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)\r
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)\r
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)\r
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)\r
+#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)\r
+#define RCC_CIR_CSSC ((uint32_t)0x00800000)\r
+\r
+/******************** Bit definition for RCC_AHB1RSTR register **************/\r
+#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)\r
+#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)\r
+#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)\r
+#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)\r
+#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)\r
+#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)\r
+#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)\r
+#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)\r
+#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)\r
+#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)\r
+#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)\r
+#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)\r
+#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)\r
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)\r
+\r
+/******************** Bit definition for RCC_AHB2RSTR register **************/\r
+#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)\r
+#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)\r
+#define RCC_AHB2RSTR_HSAHRST ((uint32_t)0x00000020)\r
+#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)\r
+#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)\r
+\r
+/******************** Bit definition for RCC_AHB3RSTR register **************/\r
+#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)\r
+\r
+/******************** Bit definition for RCC_APB1RSTR register **************/\r
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)\r
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)\r
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)\r
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)\r
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)\r
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)\r
+#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)\r
+#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)\r
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)\r
+#define RCC_APB1RSTR_WWDGEN ((uint32_t)0x00000800)\r
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00008000)\r
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00010000)\r
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)\r
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)\r
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)\r
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)\r
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)\r
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)\r
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)\r
+#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)\r
+#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)\r
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)\r
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)\r
+\r
+/******************** Bit definition for RCC_APB2RSTR register **************/\r
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)\r
+#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)\r
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)\r
+#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)\r
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)\r
+#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)\r
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)\r
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)\r
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)\r
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)\r
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)\r
+/* Old SPI1RST bit definition, maintained for legacy purpose */\r
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST\r
+\r
+/******************** Bit definition for RCC_AHB1ENR register ***************/\r
+#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)\r
+#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)\r
+#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)\r
+#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)\r
+#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)\r
+#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)\r
+#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)\r
+#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)\r
+#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)\r
+#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)\r
+#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)\r
+#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)\r
+#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)\r
+#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)\r
+#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)\r
+#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)\r
+#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)\r
+#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)\r
+#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)\r
+#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)\r
+\r
+/******************** Bit definition for RCC_AHB2ENR register ***************/\r
+#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)\r
+#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)\r
+#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)\r
+#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)\r
+#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)\r
+\r
+/******************** Bit definition for RCC_AHB3ENR register ***************/\r
+#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)\r
+\r
+/******************** Bit definition for RCC_APB1ENR register ***************/\r
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)\r
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)\r
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)\r
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)\r
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)\r
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)\r
+#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)\r
+#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)\r
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)\r
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)\r
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)\r
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)\r
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)\r
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)\r
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)\r
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)\r
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)\r
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)\r
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)\r
+#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)\r
+#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)\r
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)\r
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)\r
+\r
+/******************** Bit definition for RCC_APB2ENR register ***************/\r
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)\r
+#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)\r
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)\r
+#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)\r
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)\r
+#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)\r
+#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)\r
+#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)\r
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)\r
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)\r
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)\r
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)\r
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)\r
+\r
+/******************** Bit definition for RCC_AHB1LPENR register *************/\r
+#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)\r
+#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)\r
+#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)\r
+#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)\r
+#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)\r
+#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)\r
+#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)\r
+#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)\r
+#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)\r
+#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)\r
+#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)\r
+#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)\r
+#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)\r
+#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)\r
+#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)\r
+#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)\r
+#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)\r
+#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)\r
+#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)\r
+#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)\r
+#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)\r
+#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)\r
+\r
+/******************** Bit definition for RCC_AHB2LPENR register *************/\r
+#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)\r
+#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)\r
+#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)\r
+#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)\r
+#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)\r
+\r
+/******************** Bit definition for RCC_AHB3LPENR register *************/\r
+#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)\r
+\r
+/******************** Bit definition for RCC_APB1LPENR register *************/\r
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)\r
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)\r
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)\r
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)\r
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)\r
+#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)\r
+#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)\r
+#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)\r
+#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)\r
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)\r
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)\r
+#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)\r
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)\r
+#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)\r
+#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)\r
+#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)\r
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)\r
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)\r
+#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)\r
+#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)\r
+#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)\r
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)\r
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)\r
+\r
+/******************** Bit definition for RCC_APB2LPENR register *************/\r
+#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)\r
+#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)\r
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)\r
+#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)\r
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)\r
+#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)\r
+#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)\r
+#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)\r
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)\r
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)\r
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)\r
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)\r
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)\r
+\r
+/******************** Bit definition for RCC_BDCR register ******************/\r
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001)\r
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)\r
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)\r
+\r
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)\r
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)\r
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)\r
+\r
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)\r
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000)\r
+\r
+/******************** Bit definition for RCC_CSR register *******************/\r
+#define RCC_CSR_LSION ((uint32_t)0x00000001)\r
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)\r
+#define RCC_CSR_RMVF ((uint32_t)0x01000000)\r
+#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)\r
+#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)\r
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)\r
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)\r
+#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)\r
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)\r
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_SSCGR register *****************/\r
+#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)\r
+#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)\r
+#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)\r
+#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/\r
+#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)\r
+#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* RNG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RNG_CR register *******************/\r
+#define RNG_CR_RNGEN ((uint32_t)0x00000004)\r
+#define RNG_CR_IE ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RNG_SR register *******************/\r
+#define RNG_SR_DRDY ((uint32_t)0x00000001)\r
+#define RNG_SR_CECS ((uint32_t)0x00000002)\r
+#define RNG_SR_SECS ((uint32_t)0x00000004)\r
+#define RNG_SR_CEIS ((uint32_t)0x00000020)\r
+#define RNG_SR_SEIS ((uint32_t)0x00000040)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Real-Time Clock (RTC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RTC_TR register *******************/\r
+#define RTC_TR_PM ((uint32_t)0x00400000)\r
+#define RTC_TR_HT ((uint32_t)0x00300000)\r
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_TR_HU ((uint32_t)0x000F0000)\r
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_TR_MNT ((uint32_t)0x00007000)\r
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_TR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_TR_ST ((uint32_t)0x00000070)\r
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_TR_SU ((uint32_t)0x0000000F)\r
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_DR register *******************/\r
+#define RTC_DR_YT ((uint32_t)0x00F00000)\r
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)\r
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)\r
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)\r
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)\r
+#define RTC_DR_YU ((uint32_t)0x000F0000)\r
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)\r
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)\r
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)\r
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)\r
+#define RTC_DR_WDU ((uint32_t)0x0000E000)\r
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)\r
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)\r
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)\r
+#define RTC_DR_MT ((uint32_t)0x00001000)\r
+#define RTC_DR_MU ((uint32_t)0x00000F00)\r
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)\r
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)\r
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)\r
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)\r
+#define RTC_DR_DT ((uint32_t)0x00000030)\r
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)\r
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)\r
+#define RTC_DR_DU ((uint32_t)0x0000000F)\r
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)\r
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)\r
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)\r
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_CR register *******************/\r
+#define RTC_CR_COE ((uint32_t)0x00800000)\r
+#define RTC_CR_OSEL ((uint32_t)0x00600000)\r
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)\r
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)\r
+#define RTC_CR_POL ((uint32_t)0x00100000)\r
+#define RTC_CR_COSEL ((uint32_t)0x00080000)\r
+#define RTC_CR_BCK ((uint32_t)0x00040000)\r
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)\r
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)\r
+#define RTC_CR_TSIE ((uint32_t)0x00008000)\r
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)\r
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)\r
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)\r
+#define RTC_CR_TSE ((uint32_t)0x00000800)\r
+#define RTC_CR_WUTE ((uint32_t)0x00000400)\r
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)\r
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)\r
+#define RTC_CR_DCE ((uint32_t)0x00000080)\r
+#define RTC_CR_FMT ((uint32_t)0x00000040)\r
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)\r
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)\r
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)\r
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)\r
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)\r
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)\r
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)\r
+\r
+/******************** Bits definition for RTC_ISR register ******************/\r
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)\r
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)\r
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)\r
+#define RTC_ISR_TSF ((uint32_t)0x00000800)\r
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)\r
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)\r
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)\r
+#define RTC_ISR_INIT ((uint32_t)0x00000080)\r
+#define RTC_ISR_INITF ((uint32_t)0x00000040)\r
+#define RTC_ISR_RSF ((uint32_t)0x00000020)\r
+#define RTC_ISR_INITS ((uint32_t)0x00000010)\r
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)\r
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)\r
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)\r
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for RTC_PRER register *****************/\r
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)\r
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)\r
+\r
+/******************** Bits definition for RTC_WUTR register *****************/\r
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_CALIBR register ***************/\r
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)\r
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)\r
+\r
+/******************** Bits definition for RTC_ALRMAR register ***************/\r
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)\r
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)\r
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)\r
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)\r
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)\r
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)\r
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)\r
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)\r
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)\r
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)\r
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)\r
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)\r
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)\r
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)\r
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)\r
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_ALRMBR register ***************/\r
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)\r
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)\r
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)\r
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)\r
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)\r
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)\r
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)\r
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)\r
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)\r
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)\r
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)\r
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)\r
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)\r
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)\r
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)\r
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_WPR register ******************/\r
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)\r
+\r
+/******************** Bits definition for RTC_SSR register ******************/\r
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_SHIFTR register ***************/\r
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)\r
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)\r
+\r
+/******************** Bits definition for RTC_TSTR register *****************/\r
+#define RTC_TSTR_PM ((uint32_t)0x00400000)\r
+#define RTC_TSTR_HT ((uint32_t)0x00300000)\r
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)\r
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)\r
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_TSTR_ST ((uint32_t)0x00000070)\r
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)\r
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_TSDR register *****************/\r
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)\r
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)\r
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)\r
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)\r
+#define RTC_TSDR_MT ((uint32_t)0x00001000)\r
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)\r
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)\r
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)\r
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)\r
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)\r
+#define RTC_TSDR_DT ((uint32_t)0x00000030)\r
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)\r
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)\r
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)\r
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)\r
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)\r
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)\r
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_TSSSR register ****************/\r
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_CAL register *****************/\r
+#define RTC_CALR_CALP ((uint32_t)0x00008000)\r
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)\r
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)\r
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)\r
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)\r
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)\r
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)\r
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)\r
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)\r
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)\r
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)\r
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)\r
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)\r
+\r
+/******************** Bits definition for RTC_TAFCR register ****************/\r
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)\r
+#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)\r
+#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)\r
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)\r
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)\r
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)\r
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)\r
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)\r
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)\r
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)\r
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)\r
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)\r
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)\r
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)\r
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)\r
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)\r
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)\r
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for RTC_ALRMASSR register *************/\r
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)\r
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)\r
+\r
+/******************** Bits definition for RTC_ALRMBSSR register *************/\r
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)\r
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)\r
+\r
+/******************** Bits definition for RTC_BKP0R register ****************/\r
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP1R register ****************/\r
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP2R register ****************/\r
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP3R register ****************/\r
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP4R register ****************/\r
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP5R register ****************/\r
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP6R register ****************/\r
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP7R register ****************/\r
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP8R register ****************/\r
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP9R register ****************/\r
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP10R register ***************/\r
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP11R register ***************/\r
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP12R register ***************/\r
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP13R register ***************/\r
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP14R register ***************/\r
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP15R register ***************/\r
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP16R register ***************/\r
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP17R register ***************/\r
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP18R register ***************/\r
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP19R register ***************/\r
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SD host Interface */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for SDIO_POWER register ******************/\r
+#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r
+#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */\r
+#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for SDIO_CLKCR register ******************/\r
+#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */\r
+#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */\r
+#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */\r
+#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */\r
+\r
+#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
+#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */\r
+#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */\r
+\r
+#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */\r
+#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */\r
+\r
+/******************* Bit definition for SDIO_ARG register *******************/\r
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */\r
+\r
+/******************* Bit definition for SDIO_CMD register *******************/\r
+#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */\r
+\r
+#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */\r
+#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */\r
+#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */\r
+\r
+#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */\r
+#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
+#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */\r
+#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */\r
+#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */\r
+#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */\r
+#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */\r
+\r
+/***************** Bit definition for SDIO_RESPCMD register *****************/\r
+#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */\r
+\r
+/****************** Bit definition for SDIO_RESP0 register ******************/\r
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP1 register ******************/\r
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP2 register ******************/\r
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP3 register ******************/\r
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP4 register ******************/\r
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDIO_DTIMER register *****************/\r
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */\r
+\r
+/****************** Bit definition for SDIO_DLEN register *******************/\r
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */\r
+\r
+/****************** Bit definition for SDIO_DCTRL register ******************/\r
+#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */\r
+#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */\r
+#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */\r
+#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */\r
+\r
+#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */\r
+#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */\r
+#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */\r
+#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */\r
+\r
+/****************** Bit definition for SDIO_DCOUNT register *****************/\r
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */\r
+\r
+/****************** Bit definition for SDIO_STA register ********************/\r
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */\r
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */\r
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */\r
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */\r
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */\r
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */\r
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */\r
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */\r
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */\r
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */\r
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */\r
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */\r
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */\r
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */\r
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */\r
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */\r
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */\r
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */\r
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */\r
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */\r
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */\r
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */\r
+\r
+/******************* Bit definition for SDIO_ICR register *******************/\r
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */\r
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */\r
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */\r
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */\r
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */\r
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */\r
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */\r
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */\r
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */\r
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */\r
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */\r
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */\r
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */\r
+\r
+/****************** Bit definition for SDIO_MASK register *******************/\r
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */\r
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */\r
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */\r
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */\r
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */\r
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */\r
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */\r
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */\r
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */\r
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */\r
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */\r
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */\r
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */\r
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */\r
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */\r
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */\r
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */\r
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */\r
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */\r
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */\r
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */\r
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */\r
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */\r
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */\r
+\r
+/***************** Bit definition for SDIO_FIFOCNT register *****************/\r
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */\r
+\r
+/****************** Bit definition for SDIO_FIFO register *******************/\r
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Peripheral Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for SPI_CR1 register ********************/\r
+#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */\r
+#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */\r
+#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */\r
+\r
+#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */\r
+#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */\r
+#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */\r
+#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */\r
+\r
+#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */\r
+#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */\r
+#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */\r
+#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */\r
+#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */\r
+#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */\r
+#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */\r
+#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */\r
+#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */\r
+#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */\r
+\r
+/******************* Bit definition for SPI_CR2 register ********************/\r
+#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */\r
+#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */\r
+#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */\r
+#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */\r
+#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */\r
+#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */\r
+\r
+/******************** Bit definition for SPI_SR register ********************/\r
+#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */\r
+#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */\r
+#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */\r
+#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */\r
+#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */\r
+#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */\r
+#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */\r
+#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */\r
+\r
+/******************** Bit definition for SPI_DR register ********************/\r
+#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */\r
+\r
+/******************* Bit definition for SPI_CRCPR register ******************/\r
+#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */\r
+\r
+/****************** Bit definition for SPI_RXCRCR register ******************/\r
+#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */\r
+\r
+/****************** Bit definition for SPI_TXCRCR register ******************/\r
+#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */\r
+\r
+/****************** Bit definition for SPI_I2SCFGR register *****************/\r
+#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */\r
+\r
+#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */\r
+#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */\r
+\r
+#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */\r
+\r
+#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */\r
+#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */\r
+\r
+#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */\r
+#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */\r
+#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */\r
+\r
+/****************** Bit definition for SPI_I2SPR register *******************/\r
+#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */\r
+#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */\r
+#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SYSCFG */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/ \r
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!<SYSCFG_Memory Remap Config */\r
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)\r
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)\r
+\r
+/****************** Bit definition for SYSCFG_PMC register ******************/\r
+#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */\r
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */\r
+#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/\r
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!<EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!<EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!<EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!<EXTI 3 configuration */\r
+/** \r
+ * @brief EXTI0 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!<PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!<PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!<PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!<PD[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!<PE[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!<PF[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!<PG[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /*!<PH[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /*!<PI[0] pin */\r
+/** \r
+ * @brief EXTI1 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!<PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!<PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!<PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!<PD[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!<PE[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!<PF[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!<PG[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /*!<PH[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /*!<PI[1] pin */\r
+/** \r
+ * @brief EXTI2 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!<PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!<PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!<PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!<PD[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!<PE[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!<PF[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!<PG[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /*!<PH[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /*!<PI[2] pin */\r
+/** \r
+ * @brief EXTI3 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!<PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!<PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!<PC[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!<PD[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!<PE[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!<PF[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!<PG[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /*!<PH[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /*!<PI[3] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/\r
+#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!<EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!<EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!<EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!<EXTI 7 configuration */\r
+/** \r
+ * @brief EXTI4 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!<PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!<PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!<PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!<PD[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!<PE[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!<PF[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!<PG[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /*!<PH[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /*!<PI[4] pin */\r
+/** \r
+ * @brief EXTI5 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!<PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!<PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!<PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!<PD[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!<PE[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!<PF[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!<PG[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /*!<PH[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /*!<PI[5] pin */\r
+/** \r
+ * @brief EXTI6 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!<PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!<PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!<PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!<PD[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!<PE[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!<PF[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!<PG[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /*!<PH[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /*!<PI[6] pin */\r
+/** \r
+ * @brief EXTI7 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!<PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!<PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!<PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!<PD[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!<PE[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!<PF[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!<PG[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /*!<PH[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /*!<PI[7] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/\r
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!<EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!<EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!<EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!<EXTI 11 configuration */\r
+ \r
+/** \r
+ * @brief EXTI8 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!<PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!<PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!<PC[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!<PD[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!<PE[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!<PF[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!<PG[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /*!<PH[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /*!<PI[8] pin */\r
+/** \r
+ * @brief EXTI9 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!<PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!<PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!<PC[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!<PD[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!<PE[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!<PF[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!<PG[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /*!<PH[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /*!<PI[9] pin */\r
+/** \r
+ * @brief EXTI10 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!<PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!<PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!<PC[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!<PD[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!<PE[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!<PF[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!<PG[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /*!<PH[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /*!<PI[10] pin */\r
+/** \r
+ * @brief EXTI11 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!<PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!<PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!<PC[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!<PD[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!<PE[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!<PF[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!<PG[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /*!<PH[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /*!<PI[11] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/\r
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!<EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!<EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!<EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!<EXTI 15 configuration */\r
+/** \r
+ * @brief EXTI12 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!<PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!<PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!<PC[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!<PD[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!<PE[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!<PF[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!<PG[12] pin */\r
+#define SYSCFG_EXTICR3_EXTI12_PH ((uint16_t)0x0007) /*!<PH[12] pin */\r
+/** \r
+ * @brief EXTI13 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!<PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!<PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!<PC[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!<PD[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!<PE[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!<PF[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!<PG[13] pin */\r
+#define SYSCFG_EXTICR3_EXTI13_PH ((uint16_t)0x0070) /*!<PH[13] pin */\r
+/** \r
+ * @brief EXTI14 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!<PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!<PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!<PC[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!<PD[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!<PE[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!<PF[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!<PG[14] pin */\r
+#define SYSCFG_EXTICR3_EXTI14_PH ((uint16_t)0x0700) /*!<PH[14] pin */\r
+/** \r
+ * @brief EXTI15 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!<PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!<PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!<PC[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!<PD[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!<PE[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!<PF[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!<PG[15] pin */\r
+#define SYSCFG_EXTICR3_EXTI15_PH ((uint16_t)0x7000) /*!<PH[15] pin */\r
+\r
+/****************** Bit definition for SYSCFG_CMPCR register ****************/ \r
+#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */\r
+#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* TIM */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for TIM_CR1 register ********************/\r
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */\r
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */\r
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */\r
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */\r
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */\r
+\r
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */\r
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */\r
+\r
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */\r
+\r
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */\r
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for TIM_CR2 register ********************/\r
+#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */\r
+#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */\r
+#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */\r
+\r
+#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */\r
+#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */\r
+#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */\r
+#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */\r
+#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */\r
+#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */\r
+#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */\r
+#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */\r
+\r
+/******************* Bit definition for TIM_SMCR register *******************/\r
+#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */\r
+#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */\r
+\r
+#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */\r
+#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
+#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
+\r
+#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */\r
+#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */\r
+\r
+/******************* Bit definition for TIM_DIER register *******************/\r
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */\r
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */\r
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */\r
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */\r
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */\r
+#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */\r
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */\r
+#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */\r
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */\r
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */\r
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */\r
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */\r
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */\r
+#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */\r
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */\r
+\r
+/******************** Bit definition for TIM_SR register ********************/\r
+#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */\r
+#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */\r
+#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */\r
+#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */\r
+#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */\r
+#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */\r
+#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */\r
+#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */\r
+#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */\r
+#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */\r
+#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */\r
+#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */\r
+\r
+/******************* Bit definition for TIM_EGR register ********************/\r
+#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */\r
+#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */\r
+#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */\r
+#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */\r
+#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */\r
+#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */\r
+#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */\r
+#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */\r
+\r
+/****************** Bit definition for TIM_CCMR1 register *******************/\r
+#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */\r
+#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */\r
+\r
+#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */\r
+\r
+#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */\r
+#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */\r
+\r
+#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
+\r
+/****************** Bit definition for TIM_CCMR2 register *******************/\r
+#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */\r
+#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */\r
+\r
+#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */\r
+\r
+#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for TIM_CCER register *******************/\r
+#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */\r
+#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */\r
+#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */\r
+#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */\r
+#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */\r
+#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */\r
+#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */\r
+#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */\r
+#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */\r
+#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */\r
+#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */\r
+\r
+/******************* Bit definition for TIM_CNT register ********************/\r
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */\r
+\r
+/******************* Bit definition for TIM_PSC register ********************/\r
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */\r
+\r
+/******************* Bit definition for TIM_ARR register ********************/\r
+#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */\r
+\r
+/******************* Bit definition for TIM_RCR register ********************/\r
+#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */\r
+\r
+/******************* Bit definition for TIM_CCR1 register *******************/\r
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */\r
+\r
+/******************* Bit definition for TIM_CCR2 register *******************/\r
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */\r
+\r
+/******************* Bit definition for TIM_CCR3 register *******************/\r
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */\r
+\r
+/******************* Bit definition for TIM_CCR4 register *******************/\r
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */\r
+\r
+/******************* Bit definition for TIM_BDTR register *******************/\r
+#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
+#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */\r
+#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */\r
+\r
+#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */\r
+#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */\r
+#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */\r
+#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */\r
+#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */\r
+#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */\r
+#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */\r
+\r
+/******************* Bit definition for TIM_DCR register ********************/\r
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+\r
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for TIM_DMAR register *******************/\r
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */\r
+\r
+/******************* Bit definition for TIM_OR register *********************/\r
+#define TIM_OR_TI4_RMP ((uint16_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */\r
+#define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */\r
+#define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */\r
+#define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\r
+#define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Synchronous Asynchronous Receiver Transmitter */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for USART_SR register *******************/\r
+#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */\r
+#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */\r
+#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */\r
+#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */\r
+#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */\r
+#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */\r
+#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */\r
+#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */\r
+#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */\r
+#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */\r
+\r
+/******************* Bit definition for USART_DR register *******************/\r
+#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */\r
+\r
+/****************** Bit definition for USART_BRR register *******************/\r
+#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */\r
+#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */\r
+\r
+/****************** Bit definition for USART_CR1 register *******************/\r
+#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */\r
+#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */\r
+#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */\r
+#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */\r
+#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */\r
+#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */\r
+#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */\r
+#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */\r
+#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */\r
+#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */\r
+#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */\r
+#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */\r
+#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */\r
+#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */\r
+#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversampling by 8 enable */\r
+\r
+/****************** Bit definition for USART_CR2 register *******************/\r
+#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */\r
+#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */\r
+#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */\r
+#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */\r
+#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */\r
+#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */\r
+#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */\r
+\r
+#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */\r
+#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */\r
+\r
+/****************** Bit definition for USART_CR3 register *******************/\r
+#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */\r
+#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */\r
+#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */\r
+#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */\r
+#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */\r
+#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */\r
+#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */\r
+#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */\r
+#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */\r
+#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */\r
+#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<USART One bit method enable */\r
+\r
+/****************** Bit definition for USART_GTPR register ******************/\r
+#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */\r
+#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */\r
+#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */\r
+\r
+#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Window WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for WWDG_CR register ********************/\r
+#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */\r
+#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */\r
+#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */\r
+#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */\r
+#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */\r
+#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */\r
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */\r
+\r
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */\r
+\r
+/******************* Bit definition for WWDG_CFR register *******************/\r
+#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */\r
+#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */\r
+\r
+#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */\r
+#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */\r
+#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */\r
+\r
+#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */\r
+\r
+/******************* Bit definition for WWDG_SR register ********************/\r
+#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DBG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DBGMCU_IDCODE register *************/\r
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)\r
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)\r
+\r
+/******************** Bit definition for DBGMCU_CR register *****************/\r
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)\r
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)\r
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)\r
+\r
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)\r
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */\r
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */\r
+\r
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)\r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)\r
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)\r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)\r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)\r
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)\r
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)\r
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)\r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)\r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)\r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)\r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)\r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)\r
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)\r
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)\r
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)\r
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */\r
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP\r
+\r
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/\r
+#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)\r
+#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)\r
+#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)\r
+#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Ethernet MAC Registers bits definitions */\r
+/* */\r
+/******************************************************************************/\r
+/* Bit definition for Ethernet MAC Control Register register */\r
+#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */\r
+#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */\r
+#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */\r
+#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */\r
+ #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */\r
+ #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */\r
+ #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */\r
+ #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ \r
+ #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */\r
+ #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */\r
+ #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ \r
+#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */\r
+#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */\r
+#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */\r
+#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */\r
+#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */\r
+#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */\r
+#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */\r
+#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */\r
+#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling\r
+ a transmission attempt during retries after a collision: 0 =< r <2^k */\r
+ #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */\r
+ #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */\r
+ #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */\r
+ #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ \r
+#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */\r
+#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */\r
+#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */\r
+\r
+/* Bit definition for Ethernet MAC Frame Filter Register */\r
+#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ \r
+#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ \r
+#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ \r
+#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ \r
+#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */\r
+ #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */\r
+ #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */\r
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ \r
+#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ \r
+#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ \r
+#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ \r
+#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ \r
+#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */\r
+#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table High Register */\r
+#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table Low Register */\r
+#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */\r
+\r
+/* Bit definition for Ethernet MAC MII Address Register */\r
+#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ \r
+#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ \r
+#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ \r
+ #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */\r
+ #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */\r
+ #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */\r
+ #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */\r
+ #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ \r
+#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ \r
+#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ \r
+ \r
+/* Bit definition for Ethernet MAC MII Data Register */\r
+#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */\r
+\r
+/* Bit definition for Ethernet MAC Flow Control Register */\r
+#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */\r
+#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */\r
+#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */\r
+ #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */\r
+ #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */\r
+ #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */\r
+ #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ \r
+#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */\r
+#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */\r
+#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */\r
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */\r
+\r
+/* Bit definition for Ethernet MAC VLAN Tag Register */\r
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */\r
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */\r
+\r
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ \r
+#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */\r
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\r
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\r
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\r
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\r
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\r
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\r
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - \r
+ RSVD - Filter1 Command - RSVD - Filter0 Command\r
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\r
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\r
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\r
+\r
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ \r
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */\r
+#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */\r
+#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */\r
+#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */\r
+#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */\r
+#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */\r
+#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */\r
+\r
+/* Bit definition for Ethernet MAC Status Register */\r
+#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */\r
+#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */\r
+#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */\r
+#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */\r
+#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */\r
+\r
+/* Bit definition for Ethernet MAC Interrupt Mask Register */\r
+#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */\r
+#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */\r
+\r
+/* Bit definition for Ethernet MAC Address0 High Register */\r
+#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */\r
+\r
+/* Bit definition for Ethernet MAC Address0 Low Register */\r
+#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */\r
+\r
+/* Bit definition for Ethernet MAC Address1 High Register */\r
+#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */\r
+#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */\r
+#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r
+ #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ \r
+#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address1 Low Register */\r
+#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */\r
+\r
+/* Bit definition for Ethernet MAC Address2 High Register */\r
+#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */\r
+#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */\r
+#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */\r
+ #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address2 Low Register */\r
+#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */\r
+\r
+/* Bit definition for Ethernet MAC Address3 High Register */\r
+#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */\r
+#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */\r
+#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */\r
+ #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */\r
+\r
+/* Bit definition for Ethernet MAC Address3 Low Register */\r
+#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */\r
+\r
+/******************************************************************************/\r
+/* Ethernet MMC Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet MMC Contol Register */\r
+#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */\r
+#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */\r
+#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */\r
+#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */\r
+#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */\r
+#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Register */\r
+#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */\r
+#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\r
+#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\r
+#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\r
+#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\r
+#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\r
+#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\r
+#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\r
+#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */\r
+\r
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\r
+#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */\r
+\r
+/******************************************************************************/\r
+/* Ethernet PTP Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */\r
+#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */\r
+#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */\r
+#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */\r
+#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */\r
+#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */\r
+#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */\r
+#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */\r
+#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */\r
+#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */\r
+\r
+#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */\r
+#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */\r
+#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */\r
+#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */\r
+#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */\r
+#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */\r
+\r
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */\r
+#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Register */\r
+#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Register */\r
+#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */\r
+#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */\r
+#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\r
+#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */\r
+#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */\r
+#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */\r
+\r
+/* Bit definition for Ethernet PTP Target Time High Register */\r
+#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */\r
+\r
+/* Bit definition for Ethernet PTP Target Time Low Register */\r
+#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Status Register */\r
+#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */\r
+#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */\r
+\r
+/******************************************************************************/\r
+/* Ethernet DMA Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet DMA Bus Mode Register */\r
+#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */\r
+#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */\r
+#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */\r
+#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */\r
+ #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+ #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+ #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+ #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+ #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+ #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ \r
+ #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+ #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+ #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+ #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+ #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+ #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ \r
+#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */\r
+#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ \r
+#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */\r
+ #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+ #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+ #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+ #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+ #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+ #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ \r
+ #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+ #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+ #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+ #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+ #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+ #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */\r
+#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */\r
+#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */\r
+#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\r
+#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */\r
+#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\r
+#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\r
+#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */\r
+\r
+/* Bit definition for Ethernet DMA Status Register */\r
+#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */\r
+#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */\r
+#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */\r
+#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */\r
+ /* combination with EBS[2:0] for GetFlagStatus function */\r
+ #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */\r
+ #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */\r
+ #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */\r
+ #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */\r
+ #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */\r
+ #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */\r
+ #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */\r
+ #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */\r
+ #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */\r
+#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */\r
+ #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */\r
+ #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */\r
+ #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */\r
+ #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */\r
+ #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */\r
+ #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */\r
+#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */\r
+#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */\r
+#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */\r
+#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */\r
+#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */\r
+#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */\r
+#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */\r
+#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */\r
+#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */\r
+#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */\r
+#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */\r
+#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */\r
+#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */\r
+#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */\r
+#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */\r
+\r
+/* Bit definition for Ethernet DMA Operation Mode Register */\r
+#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */\r
+#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */\r
+#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */\r
+#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */\r
+#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */\r
+#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */\r
+ #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+ #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+ #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+ #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+ #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+ #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+ #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+ #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */\r
+#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */\r
+#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */\r
+#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */\r
+ #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */\r
+ #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */\r
+ #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */\r
+ #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */\r
+#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */\r
+#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */\r
+\r
+/* Bit definition for Ethernet DMA Interrupt Enable Register */\r
+#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */\r
+#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */\r
+#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */\r
+#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */\r
+#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */\r
+#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */\r
+#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */\r
+#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */\r
+#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */\r
+#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */\r
+#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */\r
+#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */\r
+#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */\r
+\r
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\r
+#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */\r
+#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */\r
+#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */\r
+#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\r
+#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\r
+#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\r
+#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\r
+#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */ \r
+\r
+#ifdef USE_STDPERIPH_DRIVER\r
+ #include "stm32f4xx_conf.h"\r
+#endif /* USE_STDPERIPH_DRIVER */\r
+\r
+/** @addtogroup Exported_macro\r
+ * @{\r
+ */\r
+\r
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
+\r
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
+\r
+#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
+\r
+#define CLEAR_REG(REG) ((REG) = (0x0))\r
+\r
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
+\r
+#define READ_REG(REG) ((REG))\r
+\r
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32F4xx_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f4xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. \r
+ ****************************************************************************** \r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f4xx_system\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @brief Define to prevent recursive inclusion\r
+ */\r
+#ifndef __SYSTEM_STM32F4XX_H\r
+#define __SYSTEM_STM32F4XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/** @addtogroup STM32F4xx_System_Includes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup STM32F4xx_System_Exported_types\r
+ * @{\r
+ */\r
+\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+extern void SystemInit(void);\r
+extern void SystemCoreClockUpdate(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__SYSTEM_STM32F4XX_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
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+ <tr>\r
+ <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../../Release_Notes.html">Back to Release page</a></span></td>\r
+ </tr>\r
+<tr style="">\r
+<td style="padding: 1.5pt;">\r
+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release\r
+Notes for STM32F4xx CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>\r
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>\r
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>\r
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">\r
+<tbody>\r
+<tr>\r
+<td style="padding: 0cm;" valign="top">\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>\r
+<ol style="margin-top: 0cm;" start="1" type="1">\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F4xx CMSIS\r
+update History</a><o:p></o:p></span></li>\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>\r
+</ol>\r
+<span style="font-family: "Times New Roman";"></span>\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F4xx CMSIS\r
+update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 30-September-2011<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+Changes<o:p></o:p></span></u></b></p>\r
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release for </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32F40x/41x</span> devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add startup file for <span style="font-style: italic;">TASKING</span> toolchain</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">system_stm32f4xx.c: driver's comments update</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC2 / 26-September-2011<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+Changes<o:p></o:p></span></u></b></p>\r
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Official version (V1.0.0) Release Candidate2 </span><span style="font-size: 10pt; font-family: Verdana;">for <span style="font-weight: bold; font-style: italic;">STM32F40x/41x</span> devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add define for Cortex-M4 revision <span style="font-style: italic;">__CM4_REV</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Correct <span style="font-style: italic;">RCC_CFGR_PPRE2_DIV16</span> bit (in </span><span style="font-size: 10pt; font-family: Verdana;">RCC_CFGR</span><span style="font-size: 10pt; font-family: Verdana;"> register) value to 0x0000E000</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Correct some bits definition to be in line with naming used in the Reference Manual </span><span style="font-size: 10pt; font-family: Verdana;"> (RM0090)</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_<span style="font-weight: bold;">OTYPER</span>_IDR_x</span> changed to <span style="font-style: italic;">GPIO_<span style="font-weight: bold;">IDR</span>_IDR_x</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_<span style="font-weight: bold;">OTYPER</span>_ODR_x</span> changed to <span style="font-style: italic;">GPIO_<span style="font-weight: bold;">ODR</span>_ODR_x</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SYSCFG_PMC_MII_RMII</span> changed to </span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">SYSCFG_PMC_MII_RMII<span style="font-weight: bold;">_SEL</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">RCC_APB2RSTR_SPI1</span> changed to <span style="font-style: italic;">RCC_APB2RSTR_SPI1<span style="font-weight: bold;">RST</span></span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">DBGMCU_APB1_FZ_DBG_IWD<span style="font-weight: bold;">E</span>G_STOP</span> changed to <span style="font-style: italic;">DBGMCU_APB1_FZ_DBG_IWDG_STOP</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">PWR_CR_PMODE</span> changed to <span style="font-style: italic;">PWR_CR_VOS</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">PWR_CSR_REGRDY</span> changed to <span style="font-style: italic;">PWR_CSR_VOSRDY</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">RCC_AHB1ENR_CCMDATARAMEN</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new defines <span style="font-style: italic;">SRAM2_BASE, CCMDATARAM_BASE </span>and<span style="font-style: italic;"> BKPSRAM_BASE</span></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">GPIO_TypeDef structure: in the comment change AFR[2] address mapping to <span style="font-style: italic;">0x20-0x24</span> instead of <span style="font-style: italic;">0x24-0x28</span></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">system_stm32f4xx.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span>: add code to enable the FPU</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SetSysClock()</span>: change <span style="font-style: italic;">PWR_CR_PMODE</span> by <span style="font-style: italic;">PWR_CR_VOS</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl()</span>: remove commented values</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">startup (for all compilers)</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Delete code used to enable the FPU (moved to system_stm32f4xx.c file)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">File’s header updated</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 176px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC1 / 25-August-2011<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+Changes<o:p></o:p></span></u></b></p>\r
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Official version (V1.0.0) Release Candidate1 for <span style="font-weight: bold; font-style: italic;">STM32F4xx devices</span></span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span><span style="font-weight: bold; font-style: italic;"></span></span>\r
+\r
+<ul style="margin-top: 0in;" type="disc">\r
+</ul>\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>\r
+<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The\r
+enclosed firmware and all the related documentation are not covered by\r
+a License Agreement, if you need such License you can contact your\r
+local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>\r
+<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE\r
+PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO\r
+SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR\r
+ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY\r
+CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY\r
+CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH\r
+THEIR PRODUCTS. <o:p></o:p></span></b></p>\r
+<p class="MsoNormal"><span style="color: black;"><o:p> </o:p></span></p>\r
+<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">\r
+<hr align="center" size="2" width="100%"></span></div>\r
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For\r
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers\r
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+</div>\r
+<p class="MsoNormal"><o:p> </o:p></p>\r
+</div>\r
+</body></html>
\ No newline at end of file
--- /dev/null
+;/******************** (C) COPYRIGHT 2011 STMicroelectronics ********************\r
+;* File Name : startup_stm32f4xx.s\r
+;* Author : MCD Application Team\r
+;* Version : V1.0.0\r
+;* Date : 30-September-2011\r
+;* Description : STM32F4xx devices vector table for EWARM toolchain.\r
+;* This module performs:\r
+;* - Set the initial SP\r
+;* - Set the initial PC == _iar_program_start,\r
+;* - Set the vector table entries with the exceptions ISR \r
+;* address.\r
+;* - Configure the system clock and the external SRAM mounted on \r
+;* STM324xG-EVAL board to be used as data memory (optional, \r
+;* to be enabled by user)\r
+;* - Branches to main in the C library (which eventually\r
+;* calls main()).\r
+;* After Reset the Cortex-M4 processor is in Thread mode,\r
+;* priority is Privileged, and the Stack is set to Main.\r
+;********************************************************************************\r
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+;*******************************************************************************/\r
+;\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; The vector table is normally located at address 0.\r
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
+; The name "__vector_table" has special meaning for C-SPY:\r
+; it is where the SP start value is found, and the NVIC vector\r
+; table register (VTOR) is initialized to this address if != 0.\r
+;\r
+; Cortex-M version\r
+;\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+ SECTION .intvec:CODE:NOROOT(2)\r
+\r
+ EXTERN __iar_program_start\r
+ EXTERN SystemInit\r
+ PUBLIC __vector_table\r
+\r
+ DATA\r
+__vector_table\r
+ DCD sfe(CSTACK)\r
+ DCD Reset_Handler ; Reset Handler\r
+\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ DCD WWDG_IRQHandler ; Window WatchDog \r
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection \r
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line \r
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line \r
+ DCD FLASH_IRQHandler ; FLASH \r
+ DCD RCC_IRQHandler ; RCC \r
+ DCD EXTI0_IRQHandler ; EXTI Line0 \r
+ DCD EXTI1_IRQHandler ; EXTI Line1 \r
+ DCD EXTI2_IRQHandler ; EXTI Line2 \r
+ DCD EXTI3_IRQHandler ; EXTI Line3 \r
+ DCD EXTI4_IRQHandler ; EXTI Line4 \r
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 \r
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 \r
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 \r
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 \r
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 \r
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 \r
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 \r
+ DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s \r
+ DCD CAN1_TX_IRQHandler ; CAN1 TX \r
+ DCD CAN1_RX0_IRQHandler ; CAN1 RX0 \r
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1 \r
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE \r
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s \r
+ DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 \r
+ DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 \r
+ DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11\r
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare \r
+ DCD TIM2_IRQHandler ; TIM2 \r
+ DCD TIM3_IRQHandler ; TIM3 \r
+ DCD TIM4_IRQHandler ; TIM4 \r
+ DCD I2C1_EV_IRQHandler ; I2C1 Event \r
+ DCD I2C1_ER_IRQHandler ; I2C1 Error \r
+ DCD I2C2_EV_IRQHandler ; I2C2 Event \r
+ DCD I2C2_ER_IRQHandler ; I2C2 Error \r
+ DCD SPI1_IRQHandler ; SPI1 \r
+ DCD SPI2_IRQHandler ; SPI2 \r
+ DCD USART1_IRQHandler ; USART1 \r
+ DCD USART2_IRQHandler ; USART2 \r
+ DCD USART3_IRQHandler ; USART3 \r
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s \r
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line \r
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line \r
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 \r
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 \r
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14\r
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare \r
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 \r
+ DCD FSMC_IRQHandler ; FSMC \r
+ DCD SDIO_IRQHandler ; SDIO \r
+ DCD TIM5_IRQHandler ; TIM5 \r
+ DCD SPI3_IRQHandler ; SPI3 \r
+ DCD UART4_IRQHandler ; UART4 \r
+ DCD UART5_IRQHandler ; UART5 \r
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors \r
+ DCD TIM7_IRQHandler ; TIM7 \r
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 \r
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 \r
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 \r
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 \r
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 \r
+ DCD ETH_IRQHandler ; Ethernet \r
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line \r
+ DCD CAN2_TX_IRQHandler ; CAN2 TX \r
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0 \r
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1 \r
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE \r
+ DCD OTG_FS_IRQHandler ; USB OTG FS \r
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 \r
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 \r
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 \r
+ DCD USART6_IRQHandler ; USART6 \r
+ DCD I2C3_EV_IRQHandler ; I2C3 event \r
+ DCD I2C3_ER_IRQHandler ; I2C3 error \r
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out \r
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In \r
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI \r
+ DCD OTG_HS_IRQHandler ; USB OTG HS \r
+ DCD DCMI_IRQHandler ; DCMI \r
+ DCD CRYP_IRQHandler ; CRYP crypto \r
+ DCD HASH_RNG_IRQHandler ; Hash and Rng\r
+ DCD FPU_IRQHandler ; FPU\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+ THUMB\r
+ PUBWEAK Reset_Handler\r
+ SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__iar_program_start\r
+ BX R0\r
+\r
+ PUBWEAK NMI_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+NMI_Handler\r
+ B NMI_Handler\r
+\r
+ PUBWEAK HardFault_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+HardFault_Handler\r
+ B HardFault_Handler\r
+\r
+ PUBWEAK MemManage_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+MemManage_Handler\r
+ B MemManage_Handler\r
+\r
+ PUBWEAK BusFault_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+BusFault_Handler\r
+ B BusFault_Handler\r
+\r
+ PUBWEAK UsageFault_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+UsageFault_Handler\r
+ B UsageFault_Handler\r
+\r
+ PUBWEAK SVC_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+SVC_Handler\r
+ B SVC_Handler\r
+\r
+ PUBWEAK DebugMon_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+DebugMon_Handler\r
+ B DebugMon_Handler\r
+\r
+ PUBWEAK PendSV_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+PendSV_Handler\r
+ B PendSV_Handler\r
+\r
+ PUBWEAK SysTick_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+SysTick_Handler\r
+ B SysTick_Handler\r
+\r
+ PUBWEAK WWDG_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+WWDG_IRQHandler \r
+ B WWDG_IRQHandler\r
+\r
+ PUBWEAK PVD_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+PVD_IRQHandler \r
+ B PVD_IRQHandler\r
+\r
+ PUBWEAK TAMP_STAMP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TAMP_STAMP_IRQHandler \r
+ B TAMP_STAMP_IRQHandler\r
+\r
+ PUBWEAK RTC_WKUP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+RTC_WKUP_IRQHandler \r
+ B RTC_WKUP_IRQHandler\r
+\r
+ PUBWEAK FLASH_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+FLASH_IRQHandler \r
+ B FLASH_IRQHandler\r
+\r
+ PUBWEAK RCC_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+RCC_IRQHandler \r
+ B RCC_IRQHandler\r
+\r
+ PUBWEAK EXTI0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EXTI0_IRQHandler \r
+ B EXTI0_IRQHandler\r
+\r
+ PUBWEAK EXTI1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EXTI1_IRQHandler \r
+ B EXTI1_IRQHandler\r
+\r
+ PUBWEAK EXTI2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EXTI2_IRQHandler \r
+ B EXTI2_IRQHandler\r
+\r
+ PUBWEAK EXTI3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EXTI3_IRQHandler\r
+ B EXTI3_IRQHandler\r
+\r
+ PUBWEAK EXTI4_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+EXTI4_IRQHandler \r
+ B EXTI4_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream0_IRQHandler \r
+ B DMA1_Stream0_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream1_IRQHandler \r
+ B DMA1_Stream1_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream2_IRQHandler \r
+ B DMA1_Stream2_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream3_IRQHandler \r
+ B DMA1_Stream3_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream4_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream4_IRQHandler \r
+ B DMA1_Stream4_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream5_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream5_IRQHandler \r
+ B DMA1_Stream5_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream6_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream6_IRQHandler \r
+ B DMA1_Stream6_IRQHandler\r
+\r
+ PUBWEAK ADC_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ADC_IRQHandler \r
+ B ADC_IRQHandler\r
+\r
+ PUBWEAK CAN1_TX_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN1_TX_IRQHandler \r
+ B CAN1_TX_IRQHandler\r
+\r
+ PUBWEAK CAN1_RX0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN1_RX0_IRQHandler \r
+ B CAN1_RX0_IRQHandler\r
+\r
+ PUBWEAK CAN1_RX1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN1_RX1_IRQHandler \r
+ B CAN1_RX1_IRQHandler\r
+\r
+ PUBWEAK CAN1_SCE_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN1_SCE_IRQHandler \r
+ B CAN1_SCE_IRQHandler\r
+\r
+ PUBWEAK EXTI9_5_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+EXTI9_5_IRQHandler \r
+ B EXTI9_5_IRQHandler\r
+\r
+ PUBWEAK TIM1_BRK_TIM9_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM1_BRK_TIM9_IRQHandler \r
+ B TIM1_BRK_TIM9_IRQHandler\r
+\r
+ PUBWEAK TIM1_UP_TIM10_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM1_UP_TIM10_IRQHandler \r
+ B TIM1_UP_TIM10_IRQHandler\r
+\r
+ PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM1_TRG_COM_TIM11_IRQHandler \r
+ B TIM1_TRG_COM_TIM11_IRQHandler\r
+ \r
+ PUBWEAK TIM1_CC_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM1_CC_IRQHandler \r
+ B TIM1_CC_IRQHandler\r
+\r
+ PUBWEAK TIM2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM2_IRQHandler \r
+ B TIM2_IRQHandler\r
+\r
+ PUBWEAK TIM3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM3_IRQHandler \r
+ B TIM3_IRQHandler\r
+\r
+ PUBWEAK TIM4_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM4_IRQHandler \r
+ B TIM4_IRQHandler\r
+\r
+ PUBWEAK I2C1_EV_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+I2C1_EV_IRQHandler \r
+ B I2C1_EV_IRQHandler\r
+\r
+ PUBWEAK I2C1_ER_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+I2C1_ER_IRQHandler \r
+ B I2C1_ER_IRQHandler\r
+\r
+ PUBWEAK I2C2_EV_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+I2C2_EV_IRQHandler \r
+ B I2C2_EV_IRQHandler\r
+\r
+ PUBWEAK I2C2_ER_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+I2C2_ER_IRQHandler \r
+ B I2C2_ER_IRQHandler\r
+\r
+ PUBWEAK SPI1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+SPI1_IRQHandler \r
+ B SPI1_IRQHandler\r
+\r
+ PUBWEAK SPI2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+SPI2_IRQHandler \r
+ B SPI2_IRQHandler\r
+\r
+ PUBWEAK USART1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+USART1_IRQHandler \r
+ B USART1_IRQHandler\r
+\r
+ PUBWEAK USART2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+USART2_IRQHandler \r
+ B USART2_IRQHandler\r
+\r
+ PUBWEAK USART3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+USART3_IRQHandler \r
+ B USART3_IRQHandler\r
+\r
+ PUBWEAK EXTI15_10_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+EXTI15_10_IRQHandler \r
+ B EXTI15_10_IRQHandler\r
+\r
+ PUBWEAK RTC_Alarm_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+RTC_Alarm_IRQHandler \r
+ B RTC_Alarm_IRQHandler\r
+\r
+ PUBWEAK OTG_FS_WKUP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+OTG_FS_WKUP_IRQHandler \r
+ B OTG_FS_WKUP_IRQHandler\r
+ \r
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM8_BRK_TIM12_IRQHandler \r
+ B TIM8_BRK_TIM12_IRQHandler\r
+\r
+ PUBWEAK TIM8_UP_TIM13_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM8_UP_TIM13_IRQHandler \r
+ B TIM8_UP_TIM13_IRQHandler\r
+\r
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM8_TRG_COM_TIM14_IRQHandler \r
+ B TIM8_TRG_COM_TIM14_IRQHandler\r
+\r
+ PUBWEAK TIM8_CC_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM8_CC_IRQHandler \r
+ B TIM8_CC_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream7_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream7_IRQHandler \r
+ B DMA1_Stream7_IRQHandler\r
+\r
+ PUBWEAK FSMC_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+FSMC_IRQHandler \r
+ B FSMC_IRQHandler\r
+\r
+ PUBWEAK SDIO_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+SDIO_IRQHandler \r
+ B SDIO_IRQHandler\r
+\r
+ PUBWEAK TIM5_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM5_IRQHandler \r
+ B TIM5_IRQHandler\r
+\r
+ PUBWEAK SPI3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+SPI3_IRQHandler \r
+ B SPI3_IRQHandler\r
+\r
+ PUBWEAK UART4_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+UART4_IRQHandler \r
+ B UART4_IRQHandler\r
+\r
+ PUBWEAK UART5_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+UART5_IRQHandler \r
+ B UART5_IRQHandler\r
+\r
+ PUBWEAK TIM6_DAC_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM6_DAC_IRQHandler \r
+ B TIM6_DAC_IRQHandler\r
+\r
+ PUBWEAK TIM7_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM7_IRQHandler \r
+ B TIM7_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream0_IRQHandler \r
+ B DMA2_Stream0_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream1_IRQHandler \r
+ B DMA2_Stream1_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream2_IRQHandler \r
+ B DMA2_Stream2_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream3_IRQHandler \r
+ B DMA2_Stream3_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream4_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream4_IRQHandler \r
+ B DMA2_Stream4_IRQHandler\r
+\r
+ PUBWEAK ETH_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ETH_IRQHandler \r
+ B ETH_IRQHandler\r
+\r
+ PUBWEAK ETH_WKUP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+ETH_WKUP_IRQHandler \r
+ B ETH_WKUP_IRQHandler\r
+\r
+ PUBWEAK CAN2_TX_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN2_TX_IRQHandler \r
+ B CAN2_TX_IRQHandler\r
+\r
+ PUBWEAK CAN2_RX0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN2_RX0_IRQHandler \r
+ B CAN2_RX0_IRQHandler\r
+\r
+ PUBWEAK CAN2_RX1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN2_RX1_IRQHandler \r
+ B CAN2_RX1_IRQHandler\r
+\r
+ PUBWEAK CAN2_SCE_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN2_SCE_IRQHandler \r
+ B CAN2_SCE_IRQHandler\r
+\r
+ PUBWEAK OTG_FS_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+OTG_FS_IRQHandler \r
+ B OTG_FS_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream5_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream5_IRQHandler \r
+ B DMA2_Stream5_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream6_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream6_IRQHandler \r
+ B DMA2_Stream6_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream7_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream7_IRQHandler \r
+ B DMA2_Stream7_IRQHandler\r
+\r
+ PUBWEAK USART6_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+USART6_IRQHandler \r
+ B USART6_IRQHandler\r
+\r
+ PUBWEAK I2C3_EV_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+I2C3_EV_IRQHandler \r
+ B I2C3_EV_IRQHandler\r
+\r
+ PUBWEAK I2C3_ER_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+I2C3_ER_IRQHandler \r
+ B I2C3_ER_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+OTG_HS_EP1_OUT_IRQHandler \r
+ B OTG_HS_EP1_OUT_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+OTG_HS_EP1_IN_IRQHandler \r
+ B OTG_HS_EP1_IN_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_WKUP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+OTG_HS_WKUP_IRQHandler \r
+ B OTG_HS_WKUP_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+OTG_HS_IRQHandler \r
+ B OTG_HS_IRQHandler\r
+\r
+ PUBWEAK DCMI_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+DCMI_IRQHandler \r
+ B DCMI_IRQHandler\r
+\r
+ PUBWEAK CRYP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+CRYP_IRQHandler \r
+ B CRYP_IRQHandler\r
+\r
+ PUBWEAK HASH_RNG_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+HASH_RNG_IRQHandler \r
+ B HASH_RNG_IRQHandler\r
+\r
+ PUBWEAK FPU_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+FPU_IRQHandler \r
+ B FPU_IRQHandler\r
+\r
+ END\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f4xx.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.\r
+ * This file contains the system clock configuration for STM32F4xx devices,\r
+ * and is generated by the clock configuration tool\r
+ * stm32f4xx_Clock_Configuration_V1.0.0.xls\r
+ * \r
+ * 1. This file provides two functions and one global variable to be called from \r
+ * user application:\r
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier\r
+ * and Divider factors, AHB/APBx prescalers and Flash settings),\r
+ * depending on the configuration made in the clock xls tool. \r
+ * This function is called at startup just after reset and \r
+ * before branch to main program. This call is made inside\r
+ * the "startup_stm32f4xx.s" file.\r
+ *\r
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+ * by the user application to setup the SysTick \r
+ * timer or configure other parameters.\r
+ * \r
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+ * be called whenever the core clock is changed\r
+ * during program execution.\r
+ *\r
+ * 2. After each device reset the HSI (16 MHz) is used as system clock source.\r
+ * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to\r
+ * configure the system clock before to branch to main program.\r
+ *\r
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()\r
+ * function will do nothing and HSI still used as system clock source. User can \r
+ * add some code to deal with this issue inside the SetSysClock() function.\r
+ *\r
+ * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define\r
+ * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or\r
+ * through PLL, and you are using different crystal you have to adapt the HSE\r
+ * value to your own configuration.\r
+ *\r
+ * 5. This file configures the system clock as follows:\r
+ *=============================================================================\r
+ *=============================================================================\r
+ * Supported STM32F4xx device revision | Rev A\r
+ *-----------------------------------------------------------------------------\r
+ * System Clock source | PLL (HSE)\r
+ *-----------------------------------------------------------------------------\r
+ * SYSCLK(Hz) | 168000000\r
+ *-----------------------------------------------------------------------------\r
+ * HCLK(Hz) | 168000000\r
+ *-----------------------------------------------------------------------------\r
+ * AHB Prescaler | 1\r
+ *-----------------------------------------------------------------------------\r
+ * APB1 Prescaler | 4\r
+ *-----------------------------------------------------------------------------\r
+ * APB2 Prescaler | 2\r
+ *-----------------------------------------------------------------------------\r
+ * HSE Frequency(Hz) | 25000000\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_M | 25\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_N | 336\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_P | 2\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_Q | 7\r
+ *-----------------------------------------------------------------------------\r
+ * PLLI2S_N | NA\r
+ *-----------------------------------------------------------------------------\r
+ * PLLI2S_R | NA\r
+ *-----------------------------------------------------------------------------\r
+ * I2S input clock | NA\r
+ *-----------------------------------------------------------------------------\r
+ * VDD(V) | 3.3\r
+ *-----------------------------------------------------------------------------\r
+ * Main regulator output voltage | Scale1 mode\r
+ *-----------------------------------------------------------------------------\r
+ * Flash Latency(WS) | 5\r
+ *-----------------------------------------------------------------------------\r
+ * Prefetch Buffer | OFF\r
+ *-----------------------------------------------------------------------------\r
+ * Instruction cache | ON\r
+ *-----------------------------------------------------------------------------\r
+ * Data cache | ON\r
+ *-----------------------------------------------------------------------------\r
+ * Require 48MHz for USB OTG FS, | Enabled\r
+ * SDIO and RNG clock |\r
+ *-----------------------------------------------------------------------------\r
+ *=============================================================================\r
+ ****************************************************************************** \r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f4xx_system\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup STM32F4xx_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32f4xx.h"\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/************************* Miscellaneous Configuration ************************/\r
+/*!< Uncomment the following line if you need to use external SRAM mounted\r
+ on STM324xG_EVAL board as data memory */\r
+/* #define DATA_IN_ExtSRAM */\r
+\r
+/*!< Uncomment the following line if you need to relocate your vector Table in\r
+ Internal SRAM. */\r
+/* #define VECT_TAB_SRAM */\r
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. \r
+ This value must be a multiple of 0x200. */\r
+/******************************************************************************/\r
+\r
+/************************* PLL Parameters *************************************/\r
+/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */\r
+#define PLL_M 25\r
+#define PLL_N 336\r
+\r
+/* SYSCLK = PLL_VCO / PLL_P */\r
+#define PLL_P 2\r
+\r
+/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */\r
+#define PLL_Q 7\r
+\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Variables\r
+ * @{\r
+ */\r
+\r
+ uint32_t SystemCoreClock = 168000000;\r
+\r
+ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+static void SetSysClock(void);\r
+#ifdef DATA_IN_ExtSRAM\r
+ static void SystemInit_ExtMemCtl(void); \r
+#endif /* DATA_IN_ExtSRAM */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system\r
+ * Initialize the Embedded Flash Interface, the PLL and update the \r
+ * SystemFrequency variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+ /* FPU settings ------------------------------------------------------------*/\r
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */\r
+ #endif\r
+\r
+ /* Reset the RCC clock configuration to the default reset state ------------*/\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset CFGR register */\r
+ RCC->CFGR = 0x00000000;\r
+\r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset PLLCFGR register */\r
+ RCC->PLLCFGR = 0x24003010;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+\r
+#ifdef DATA_IN_ExtSRAM\r
+ SystemInit_ExtMemCtl(); \r
+#endif /* DATA_IN_ExtSRAM */\r
+ \r
+ /* Configure the System clock source, PLL Multiplier and Divider factors, \r
+ AHB/APBx prescalers and Flash settings ----------------------------------*/\r
+ SetSysClock();\r
+\r
+ /* Configure the Vector Table location add offset address ------------------*/\r
+#ifdef VECT_TAB_SRAM\r
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r
+#else\r
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock variable according to Clock Register Values.\r
+ * The SystemCoreClock variable contains the core clock (HCLK), it can\r
+ * be used by the user application to setup the SysTick timer or configure\r
+ * other parameters.\r
+ * \r
+ * @note Each time the core clock (HCLK) changes, this function must be called\r
+ * to update SystemCoreClock variable value. Otherwise, any configuration\r
+ * based on this variable will be incorrect. \r
+ * \r
+ * @note - The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ * \r
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
+ * \r
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
+ * \r
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature. \r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value\r
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ * \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\r
+ \r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+\r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock source */\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ case 0x04: /* HSE used as system clock source */\r
+ SystemCoreClock = HSE_VALUE;\r
+ break;\r
+ case 0x08: /* PLL used as system clock source */\r
+\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\r
+ SYSCLK = PLL_VCO / PLL_P\r
+ */ \r
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\r
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r
+ \r
+ if (pllsource != 0)\r
+ {\r
+ /* HSE used as PLL clock source */\r
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r
+ }\r
+ else\r
+ {\r
+ /* HSI used as PLL clock source */\r
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); \r
+ }\r
+\r
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\r
+ SystemCoreClock = pllvco/pllp;\r
+ break;\r
+ default:\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ }\r
+ /* Compute HCLK frequency --------------------------------------------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+ /* HCLK frequency */\r
+ SystemCoreClock >>= tmp;\r
+}\r
+\r
+/**\r
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors, \r
+ * AHB/APBx prescalers and Flash settings\r
+ * @Note This function should be called only once the RCC clock configuration \r
+ * is reset to the default reset state (done in SystemInit() function). \r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClock(void)\r
+{\r
+/******************************************************************************/\r
+/* PLL (clocked by HSE) used as System clock source */\r
+/******************************************************************************/\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* Enable HSE */\r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++;\r
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ }\r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */\r
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+ PWR->CR |= PWR_CR_VOS;\r
+\r
+ /* HCLK = SYSCLK / 1*/\r
+ RCC->CFGR |= RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK2 = HCLK / 2*/\r
+ RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;\r
+ \r
+ /* PCLK1 = HCLK / 4*/\r
+ RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;\r
+\r
+ /* Configure the main PLL */\r
+ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |\r
+ (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);\r
+\r
+ /* Enable the main PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till the main PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+ \r
+ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */\r
+ FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;\r
+\r
+ /* Select the main PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= RCC_CFGR_SW_PLL;\r
+\r
+ /* Wait till the main PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock\r
+ configuration. User can add here some code to deal with this error */\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Setup the external memory controller. Called in startup_stm32f4xx.s \r
+ * before jump to __main\r
+ * @param None\r
+ * @retval None\r
+ */ \r
+#ifdef DATA_IN_ExtSRAM\r
+/**\r
+ * @brief Setup the external memory controller.\r
+ * Called in startup_stm32f4xx.s before jump to main.\r
+ * This function configures the external SRAM mounted on STM324xG_EVAL board\r
+ * This SRAM will be used as program data memory (including heap and stack).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit_ExtMemCtl(void)\r
+{\r
+/*-- GPIOs Configuration -----------------------------------------------------*/\r
+/*\r
+ +-------------------+--------------------+------------------+------------------+\r
+ + SRAM pins assignment +\r
+ +-------------------+--------------------+------------------+------------------+\r
+ | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | \r
+ | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | \r
+ | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | \r
+ | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | \r
+ | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | \r
+ | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | \r
+ | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | \r
+ | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+\r
+ | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 | \r
+ | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 | \r
+ | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+\r
+ | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |\r
+ | | PE15 <-> FSMC_D12 |\r
+ +-------------------+--------------------+\r
+*/\r
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */\r
+ RCC->AHB1ENR = 0x00000078;\r
+ \r
+ /* Connect PDx pins to FSMC Alternate function */\r
+ GPIOD->AFR[0] = 0x00cc00cc;\r
+ GPIOD->AFR[1] = 0xcc0ccccc;\r
+ /* Configure PDx pins in Alternate function mode */ \r
+ GPIOD->MODER = 0xaaaa0a0a;\r
+ /* Configure PDx pins speed to 100 MHz */ \r
+ GPIOD->OSPEEDR = 0xffff0f0f;\r
+ /* Configure PDx pins Output type to push-pull */ \r
+ GPIOD->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PDx pins */ \r
+ GPIOD->PUPDR = 0x00000000;\r
+\r
+ /* Connect PEx pins to FSMC Alternate function */\r
+ GPIOE->AFR[0] = 0xc00cc0cc;\r
+ GPIOE->AFR[1] = 0xcccccccc;\r
+ /* Configure PEx pins in Alternate function mode */ \r
+ GPIOE->MODER = 0xaaaa828a;\r
+ /* Configure PEx pins speed to 100 MHz */ \r
+ GPIOE->OSPEEDR = 0xffffc3cf;\r
+ /* Configure PEx pins Output type to push-pull */ \r
+ GPIOE->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PEx pins */ \r
+ GPIOE->PUPDR = 0x00000000;\r
+\r
+ /* Connect PFx pins to FSMC Alternate function */\r
+ GPIOF->AFR[0] = 0x00cccccc;\r
+ GPIOF->AFR[1] = 0xcccc0000;\r
+ /* Configure PFx pins in Alternate function mode */ \r
+ GPIOF->MODER = 0xaa000aaa;\r
+ /* Configure PFx pins speed to 100 MHz */ \r
+ GPIOF->OSPEEDR = 0xff000fff;\r
+ /* Configure PFx pins Output type to push-pull */ \r
+ GPIOF->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PFx pins */ \r
+ GPIOF->PUPDR = 0x00000000;\r
+\r
+ /* Connect PGx pins to FSMC Alternate function */\r
+ GPIOG->AFR[0] = 0x00cccccc;\r
+ GPIOG->AFR[1] = 0x000000c0;\r
+ /* Configure PGx pins in Alternate function mode */ \r
+ GPIOG->MODER = 0x00080aaa;\r
+ /* Configure PGx pins speed to 100 MHz */ \r
+ GPIOG->OSPEEDR = 0x000c0fff;\r
+ /* Configure PGx pins Output type to push-pull */ \r
+ GPIOG->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PGx pins */ \r
+ GPIOG->PUPDR = 0x00000000;\r
+ \r
+/*-- FSMC Configuration ------------------------------------------------------*/\r
+ /* Enable the FSMC interface clock */\r
+ RCC->AHB3ENR = 0x00000001;\r
+\r
+ /* Configure and enable Bank1_SRAM2 */\r
+ FSMC_Bank1->BTCR[2] = 0x00001015;\r
+ FSMC_Bank1->BTCR[3] = 0x00010603;\r
+ FSMC_Bank1E->BWTR[2] = 0x0fffffff;\r
+/*\r
+ Bank1_SRAM2 is configured as follow:\r
+\r
+ p.FSMC_AddressSetupTime = 3;\r
+ p.FSMC_AddressHoldTime = 0;\r
+ p.FSMC_DataSetupTime = 6;\r
+ p.FSMC_BusTurnAroundDuration = 1;\r
+ p.FSMC_CLKDivision = 0;\r
+ p.FSMC_DataLatency = 0;\r
+ p.FSMC_AccessMode = FSMC_AccessMode_A;\r
+\r
+ FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;\r
+ FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;\r
+ FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;\r
+ FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; \r
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
+ FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
+ FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;\r
+ FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;\r
+*/\r
+ \r
+}\r
+#endif /* DATA_IN_ExtSRAM */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
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+ <o:LastAuthor>Raouf Hosni</o:LastAuthor>\r
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+ <tbody><tr style="">\r
+ <td style="padding: 0in 5.4pt;" valign="top">\r
+ <p class="MsoNormal"><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
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+ <h1 style="margin-bottom: 0.25in; text-align: center;" align="center"><span style="font-size: 20pt; font-family: "Verdana","sans-serif"; color: rgb(51, 102, 255);">Release Notes for STM32F4xx Standard\r
+ Peripherals Library Drivers (StdPeriph_Driver)</span><span style="font-size: 20pt; font-family: "Verdana","sans-serif";"><o:p></o:p></span></h1>\r
+ <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;">Copyright\r
+ 2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>\r
+ <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;"><img id="_x0000_i1026" src="../../_htmresc/logo.bmp" border="0" height="65" width="86"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+ </td>\r
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+ <tbody><tr style="">\r
+ <td style="padding: 0in;" valign="top">\r
+ <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>\r
+ <ol style="margin-top: 0in;" start="1" type="1">\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><a href="#History">STM32F4xx Standard Peripherals Library Drivers\r
+ update History</a><o:p></o:p></span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><a href="#License">License</a><o:p></o:p></span></li>\r
+ </ol>\r
+ <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F4xx\r
+ Standard Peripherals Library Drivers update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 198px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 30-September-2011</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+Changes<o:p></o:p></span></u></b></p>\r
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release for </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32F40x/41x</span> devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx_rtc.c: remove useless code from <span style="font-style: italic;">RTC_GetDate()</span> function<br></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx_rcc.c, stm32f4xx_spi.c, stm32f4xx_wwdg.c and stm32f4xx_syscfg.c: </span><span style="font-size: 10pt; font-family: Verdana;">driver's comments update</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 198px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC2 / 26-September-2011</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+Changes<o:p></o:p></span></u></b></p>\r
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Official version (V1.0.0) Release Candidate1<span style="font-weight: bold; font-style: italic;"> </span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"> </span><span style="font-style: italic;">for</span><span style="font-weight: bold; font-style: italic;"> STM32F40x/</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32F41x</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"> devices</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx_usart.h/.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update procedure to check on overrun error interrupt pending bit, defines for the following flag are added:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">USART_IT_ORE_RX:</span> this flag is set if </span><span style="font-size: 10pt; font-family: Verdana;">overrun error interrupt</span><span style="font-size: 10pt; font-family: Verdana;"> occurs and RXNEIE bit is set</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">USART_IT_ORE_ER:</span> </span><span style="font-size: 10pt; font-family: Verdana;">this flag is set if </span><span style="font-size: 10pt; font-family: Verdana;">overrun error interrupt</span><span style="font-size: 10pt; font-family: Verdana;"> occurs and EIE bit is set</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx_tim.c</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">TIM_UpdateRequestConfig(): </span>correct function header's comment </span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">TIM_ICInit(): </span>add assert macros to test if the passed TIM parameter has channel 2, 3 or 4</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx_pwr.h/.c</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">PWR_FLAG_REGRDY</span> constant to <span style="font-style: italic;">PWR_CSR_REGRDY</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">PWR_FLAG_VOSRDY </span></span><span style="font-size: 10pt; font-family: Verdana;">constant </span><span style="font-size: 10pt; font-family: Verdana;">to <span style="font-style: italic;">PWR_CSR_VOSRDY</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename<span style="font-style: italic;"> PWR_HighPerformanceModeCmd(FunctionalState NewState) </span>function to<span style="font-style: italic;"> PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)<br></span></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx_rcc.h/.c</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">RCC_AHB1PeriphClockCmd(): add new constant <span style="font-style: italic;">RCC_AHB1Periph_CCMDATARAMEN </span>as value for<span style="font-style: italic;"> RCC_AHB1Periph </span>parameter</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx_spi.h</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">IS_I2S_EXT_PERIPH(): add check on <span style="font-style: italic;">I2S3ext</span> peripheral</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC1 / 25-August-2011<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+Changes<o:p></o:p></span></u></b></p>\r
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Official version (V1.0.0) Release Candidate1<span style="font-weight: bold; font-style: italic;"> for STM32F4xx devices</span></span></li></ul>\r
+ <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>\r
+ <p class="MsoNormal" style="margin: 4.5pt 0in;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">The enclosed firmware and all the related documentation are\r
+ not covered by a License Agreement, if you need such License you can\r
+ contact your local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>\r
+ <p class="MsoNormal"><b><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING\r
+ CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR\r
+ THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE\r
+ FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY\r
+ CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY\r
+ CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH\r
+ THEIR PRODUCTS. <o:p></o:p></span></b></p>\r
+ <p class="MsoNormal"><span style="color: black;"><o:p> </o:p></span></p>\r
+ <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">\r
+ <hr align="center" size="2" width="100%">\r
+ </span></div>\r
+ <p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">For\r
+ complete documentation on </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32(<span style="color: black;">CORTEX M3) 32-Bit\r
+ Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>\r
+ </td>\r
+ </tr>\r
+ </tbody></table>\r
+ <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+ </td>\r
+ </tr>\r
+</tbody></table>\r
+\r
+</div>\r
+\r
+<p class="MsoNormal"><o:p> </o:p></p>\r
+\r
+</div>\r
+\r
+</body></html>
\ No newline at end of file
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file misc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the miscellaneous\r
+ * firmware library functions (add-on to CMSIS functions).\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __MISC_H\r
+#define __MISC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup MISC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief NVIC Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.\r
+ This parameter can be an enumerator of @ref IRQn_Type \r
+ enumeration (For the complete STM32 Devices IRQ Channels\r
+ list, please refer to stm32f4xx.h file) */\r
+\r
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel\r
+ specified in NVIC_IRQChannel. This parameter can be a value\r
+ between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table\r
+ A lower priority value indicates a higher priority */\r
+\r
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified\r
+ in NVIC_IRQChannel. This parameter can be a value\r
+ between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table\r
+ A lower priority value indicates a higher priority */\r
+\r
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel\r
+ will be enabled or disabled. \r
+ This parameter can be set either to ENABLE or DISABLE */ \r
+} NVIC_InitTypeDef;\r
+ \r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup MISC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MISC_Vector_Table_Base \r
+ * @{\r
+ */\r
+\r
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)\r
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)\r
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \\r
+ ((VECTTAB) == NVIC_VectTab_FLASH))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_System_Low_Power \r
+ * @{\r
+ */\r
+\r
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)\r
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)\r
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)\r
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\r
+ ((LP) == NVIC_LP_SLEEPDEEP) || \\r
+ ((LP) == NVIC_LP_SLEEPONEXIT))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Preemption_Priority_Group \r
+ * @{\r
+ */\r
+\r
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority\r
+ 4 bits for subpriority */\r
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority\r
+ 3 bits for subpriority */\r
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority\r
+ 2 bits for subpriority */\r
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority\r
+ 1 bits for subpriority */\r
+#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority\r
+ 0 bits for subpriority */\r
+\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \\r
+ ((GROUP) == NVIC_PriorityGroup_1) || \\r
+ ((GROUP) == NVIC_PriorityGroup_2) || \\r
+ ((GROUP) == NVIC_PriorityGroup_3) || \\r
+ ((GROUP) == NVIC_PriorityGroup_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_SysTick_clock_source \r
+ * @{\r
+ */\r
+\r
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)\r
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\r
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MISC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_adc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the ADC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_ADC_H\r
+#define __STM32F4xx_ADC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ADC\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief ADC Init structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. \r
+ This parameter can be a value of @ref ADC_resolution */ \r
+ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion \r
+ is performed in Scan (multichannels) \r
+ or Single (one channel) mode.\r
+ This parameter can be set to ENABLE or DISABLE */ \r
+ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion \r
+ is performed in Continuous or Single mode.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+ uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and\r
+ enable the trigger of a regular group. \r
+ This parameter can be a value of \r
+ @ref ADC_external_trigger_edge_for_regular_channels_conversion */\r
+ uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger \r
+ the start of conversion of a regular group.\r
+ This parameter can be a value of \r
+ @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */\r
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment\r
+ is left or right. This parameter can be \r
+ a value of @ref ADC_data_align */\r
+ uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions\r
+ that will be done using the sequencer for\r
+ regular channel group.\r
+ This parameter must range from 1 to 16. */\r
+}ADC_InitTypeDef;\r
+ \r
+/** \r
+ * @brief ADC Common Init structure definition \r
+ */ \r
+typedef struct \r
+{\r
+ uint32_t ADC_Mode; /*!< Configures the ADC to operate in \r
+ independent or multi mode. \r
+ This parameter can be a value of @ref ADC_Common_mode */ \r
+ uint32_t ADC_Prescaler; /*!< Select the frequency of the clock \r
+ to the ADC. The clock is common for all the ADCs.\r
+ This parameter can be a value of @ref ADC_Prescaler */\r
+ uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access \r
+ mode for multi ADC mode.\r
+ This parameter can be a value of \r
+ @ref ADC_Direct_memory_access_mode_for_multi_mode */\r
+ uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.\r
+ This parameter can be a value of \r
+ @ref ADC_delay_between_2_sampling_phases */\r
+ \r
+}ADC_CommonInitTypeDef;\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Exported_Constants\r
+ * @{\r
+ */ \r
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \\r
+ ((PERIPH) == ADC2) || \\r
+ ((PERIPH) == ADC3)) \r
+\r
+/** @defgroup ADC_Common_mode \r
+ * @{\r
+ */ \r
+#define ADC_Mode_Independent ((uint32_t)0x00000000) \r
+#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001)\r
+#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002)\r
+#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005)\r
+#define ADC_DualMode_RegSimult ((uint32_t)0x00000006)\r
+#define ADC_DualMode_Interl ((uint32_t)0x00000007)\r
+#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009)\r
+#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011)\r
+#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012)\r
+#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015)\r
+#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016)\r
+#define ADC_TripleMode_Interl ((uint32_t)0x00000017)\r
+#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019)\r
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \\r
+ ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \\r
+ ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \\r
+ ((MODE) == ADC_DualMode_InjecSimult) || \\r
+ ((MODE) == ADC_DualMode_RegSimult) || \\r
+ ((MODE) == ADC_DualMode_Interl) || \\r
+ ((MODE) == ADC_DualMode_AlterTrig) || \\r
+ ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \\r
+ ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \\r
+ ((MODE) == ADC_TripleMode_InjecSimult) || \\r
+ ((MODE) == ADC_TripleMode_RegSimult) || \\r
+ ((MODE) == ADC_TripleMode_Interl) || \\r
+ ((MODE) == ADC_TripleMode_AlterTrig))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_Prescaler \r
+ * @{\r
+ */ \r
+#define ADC_Prescaler_Div2 ((uint32_t)0x00000000)\r
+#define ADC_Prescaler_Div4 ((uint32_t)0x00010000)\r
+#define ADC_Prescaler_Div6 ((uint32_t)0x00020000)\r
+#define ADC_Prescaler_Div8 ((uint32_t)0x00030000)\r
+#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \\r
+ ((PRESCALER) == ADC_Prescaler_Div4) || \\r
+ ((PRESCALER) == ADC_Prescaler_Div6) || \\r
+ ((PRESCALER) == ADC_Prescaler_Div8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode \r
+ * @{\r
+ */ \r
+#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */\r
+#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/\r
+#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/\r
+#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */\r
+#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \\r
+ ((MODE) == ADC_DMAAccessMode_1) || \\r
+ ((MODE) == ADC_DMAAccessMode_2) || \\r
+ ((MODE) == ADC_DMAAccessMode_3))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_delay_between_2_sampling_phases \r
+ * @{\r
+ */ \r
+#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000)\r
+#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100)\r
+#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200)\r
+#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300)\r
+#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400)\r
+#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500)\r
+#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600)\r
+#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700)\r
+#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800)\r
+#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900)\r
+#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00)\r
+#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00)\r
+#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00)\r
+#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00)\r
+#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00)\r
+#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00)\r
+#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \\r
+ ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \\r
+ ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \\r
+ ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \\r
+ ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \\r
+ ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \\r
+ ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \\r
+ ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \\r
+ ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \\r
+ ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \\r
+ ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \\r
+ ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \\r
+ ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \\r
+ ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \\r
+ ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \\r
+ ((DELAY) == ADC_TwoSamplingDelay_20Cycles))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_resolution \r
+ * @{\r
+ */ \r
+#define ADC_Resolution_12b ((uint32_t)0x00000000)\r
+#define ADC_Resolution_10b ((uint32_t)0x01000000)\r
+#define ADC_Resolution_8b ((uint32_t)0x02000000)\r
+#define ADC_Resolution_6b ((uint32_t)0x03000000)\r
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \\r
+ ((RESOLUTION) == ADC_Resolution_10b) || \\r
+ ((RESOLUTION) == ADC_Resolution_8b) || \\r
+ ((RESOLUTION) == ADC_Resolution_6b))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion \r
+ * @{\r
+ */ \r
+#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)\r
+#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)\r
+#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)\r
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion \r
+ * @{\r
+ */ \r
+#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000)\r
+#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000)\r
+#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)\r
+#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000)\r
+#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000)\r
+#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)\r
+#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)\r
+#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000)\r
+#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000)\r
+#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000)\r
+#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000)\r
+#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000)\r
+#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000)\r
+#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000)\r
+#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)\r
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_data_align \r
+ * @{\r
+ */ \r
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)\r
+#define ADC_DataAlign_Left ((uint32_t)0x00000800)\r
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \\r
+ ((ALIGN) == ADC_DataAlign_Left))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_channels \r
+ * @{\r
+ */ \r
+#define ADC_Channel_0 ((uint8_t)0x00)\r
+#define ADC_Channel_1 ((uint8_t)0x01)\r
+#define ADC_Channel_2 ((uint8_t)0x02)\r
+#define ADC_Channel_3 ((uint8_t)0x03)\r
+#define ADC_Channel_4 ((uint8_t)0x04)\r
+#define ADC_Channel_5 ((uint8_t)0x05)\r
+#define ADC_Channel_6 ((uint8_t)0x06)\r
+#define ADC_Channel_7 ((uint8_t)0x07)\r
+#define ADC_Channel_8 ((uint8_t)0x08)\r
+#define ADC_Channel_9 ((uint8_t)0x09)\r
+#define ADC_Channel_10 ((uint8_t)0x0A)\r
+#define ADC_Channel_11 ((uint8_t)0x0B)\r
+#define ADC_Channel_12 ((uint8_t)0x0C)\r
+#define ADC_Channel_13 ((uint8_t)0x0D)\r
+#define ADC_Channel_14 ((uint8_t)0x0E)\r
+#define ADC_Channel_15 ((uint8_t)0x0F)\r
+#define ADC_Channel_16 ((uint8_t)0x10)\r
+#define ADC_Channel_17 ((uint8_t)0x11)\r
+#define ADC_Channel_18 ((uint8_t)0x12)\r
+\r
+#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)\r
+#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)\r
+#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18)\r
+\r
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \\r
+ ((CHANNEL) == ADC_Channel_1) || \\r
+ ((CHANNEL) == ADC_Channel_2) || \\r
+ ((CHANNEL) == ADC_Channel_3) || \\r
+ ((CHANNEL) == ADC_Channel_4) || \\r
+ ((CHANNEL) == ADC_Channel_5) || \\r
+ ((CHANNEL) == ADC_Channel_6) || \\r
+ ((CHANNEL) == ADC_Channel_7) || \\r
+ ((CHANNEL) == ADC_Channel_8) || \\r
+ ((CHANNEL) == ADC_Channel_9) || \\r
+ ((CHANNEL) == ADC_Channel_10) || \\r
+ ((CHANNEL) == ADC_Channel_11) || \\r
+ ((CHANNEL) == ADC_Channel_12) || \\r
+ ((CHANNEL) == ADC_Channel_13) || \\r
+ ((CHANNEL) == ADC_Channel_14) || \\r
+ ((CHANNEL) == ADC_Channel_15) || \\r
+ ((CHANNEL) == ADC_Channel_16) || \\r
+ ((CHANNEL) == ADC_Channel_17) || \\r
+ ((CHANNEL) == ADC_Channel_18))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_sampling_times \r
+ * @{\r
+ */ \r
+#define ADC_SampleTime_3Cycles ((uint8_t)0x00)\r
+#define ADC_SampleTime_15Cycles ((uint8_t)0x01)\r
+#define ADC_SampleTime_28Cycles ((uint8_t)0x02)\r
+#define ADC_SampleTime_56Cycles ((uint8_t)0x03)\r
+#define ADC_SampleTime_84Cycles ((uint8_t)0x04)\r
+#define ADC_SampleTime_112Cycles ((uint8_t)0x05)\r
+#define ADC_SampleTime_144Cycles ((uint8_t)0x06)\r
+#define ADC_SampleTime_480Cycles ((uint8_t)0x07)\r
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \\r
+ ((TIME) == ADC_SampleTime_15Cycles) || \\r
+ ((TIME) == ADC_SampleTime_28Cycles) || \\r
+ ((TIME) == ADC_SampleTime_56Cycles) || \\r
+ ((TIME) == ADC_SampleTime_84Cycles) || \\r
+ ((TIME) == ADC_SampleTime_112Cycles) || \\r
+ ((TIME) == ADC_SampleTime_144Cycles) || \\r
+ ((TIME) == ADC_SampleTime_480Cycles))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion \r
+ * @{\r
+ */ \r
+#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)\r
+#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)\r
+#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)\r
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \\r
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \\r
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \\r
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion \r
+ * @{\r
+ */ \r
+#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000)\r
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000)\r
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000)\r
+#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000)\r
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000)\r
+#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)\r
+#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)\r
+#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)\r
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000)\r
+#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000)\r
+#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000)\r
+#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000)\r
+#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000)\r
+#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000)\r
+#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)\r
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_injected_channel_selection \r
+ * @{\r
+ */ \r
+#define ADC_InjectedChannel_1 ((uint8_t)0x14)\r
+#define ADC_InjectedChannel_2 ((uint8_t)0x18)\r
+#define ADC_InjectedChannel_3 ((uint8_t)0x1C)\r
+#define ADC_InjectedChannel_4 ((uint8_t)0x20)\r
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_2) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_3) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_4))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_analog_watchdog_selection \r
+ * @{\r
+ */ \r
+#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)\r
+#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)\r
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)\r
+#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)\r
+#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)\r
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)\r
+#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)\r
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_None))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_interrupts_definition \r
+ * @{\r
+ */ \r
+#define ADC_IT_EOC ((uint16_t)0x0205) \r
+#define ADC_IT_AWD ((uint16_t)0x0106) \r
+#define ADC_IT_JEOC ((uint16_t)0x0407) \r
+#define ADC_IT_OVR ((uint16_t)0x201A) \r
+#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \\r
+ ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_flags_definition \r
+ * @{\r
+ */ \r
+#define ADC_FLAG_AWD ((uint8_t)0x01)\r
+#define ADC_FLAG_EOC ((uint8_t)0x02)\r
+#define ADC_FLAG_JEOC ((uint8_t)0x04)\r
+#define ADC_FLAG_JSTRT ((uint8_t)0x08)\r
+#define ADC_FLAG_STRT ((uint8_t)0x10)\r
+#define ADC_FLAG_OVR ((uint8_t)0x20) \r
+ \r
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) \r
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \\r
+ ((FLAG) == ADC_FLAG_EOC) || \\r
+ ((FLAG) == ADC_FLAG_JEOC) || \\r
+ ((FLAG)== ADC_FLAG_JSTRT) || \\r
+ ((FLAG) == ADC_FLAG_STRT) || \\r
+ ((FLAG)== ADC_FLAG_OVR)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_thresholds \r
+ * @{\r
+ */ \r
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_injected_offset \r
+ * @{\r
+ */ \r
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_injected_length \r
+ * @{\r
+ */ \r
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_injected_rank \r
+ * @{\r
+ */ \r
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_regular_length \r
+ * @{\r
+ */ \r
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_regular_rank \r
+ * @{\r
+ */ \r
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_regular_discontinuous_mode_number \r
+ * @{\r
+ */ \r
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+/* Function used to set the ADC configuration to the default reset state *****/ \r
+void ADC_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+\r
+/* Analog Watchdog configuration functions ************************************/\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);\r
+\r
+/* Temperature Sensor, Vrefint and VBAT management functions ******************/\r
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);\r
+void ADC_VBATCmd(FunctionalState NewState);\r
+\r
+/* Regular Channels Configuration functions ***********************************/\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);\r
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);\r
+uint32_t ADC_GetMultiModeConversionValue(void);\r
+\r
+/* Regular Channels DMA Configuration functions *******************************/\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);\r
+\r
+/* Injected channels Configuration functions **********************************/\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);\r
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);\r
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F4xx_ADC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_can.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the CAN firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_CAN_H\r
+#define __STM32F4xx_CAN_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CAN\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \\r
+ ((PERIPH) == CAN2))\r
+\r
+/** \r
+ * @brief CAN init structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. \r
+ It ranges from 1 to 1024. */\r
+ \r
+ uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.\r
+ This parameter can be a value of @ref CAN_operating_mode */\r
+\r
+ uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta \r
+ the CAN hardware is allowed to lengthen or \r
+ shorten a bit to perform resynchronization.\r
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */\r
+\r
+ uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit \r
+ Segment 1. This parameter can be a value of \r
+ @ref CAN_time_quantum_in_bit_segment_1 */\r
+\r
+ uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.\r
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */\r
+ \r
+ FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+ \r
+ FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+\r
+ FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. \r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+\r
+ FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+\r
+ FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+\r
+ FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+} CAN_InitTypeDef;\r
+\r
+/** \r
+ * @brief CAN filter init structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit\r
+ configuration, first one for a 16-bit configuration).\r
+ This parameter can be a value between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit\r
+ configuration, second one for a 16-bit configuration).\r
+ This parameter can be a value between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,\r
+ according to the mode (MSBs for a 32-bit configuration,\r
+ first one for a 16-bit configuration).\r
+ This parameter can be a value between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,\r
+ according to the mode (LSBs for a 32-bit configuration,\r
+ second one for a 16-bit configuration).\r
+ This parameter can be a value between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.\r
+ This parameter can be a value of @ref CAN_filter_FIFO */\r
+ \r
+ uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */\r
+\r
+ uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.\r
+ This parameter can be a value of @ref CAN_filter_mode */\r
+\r
+ uint8_t CAN_FilterScale; /*!< Specifies the filter scale.\r
+ This parameter can be a value of @ref CAN_filter_scale */\r
+\r
+ FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+} CAN_FilterInitTypeDef;\r
+\r
+/** \r
+ * @brief CAN Tx message structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t StdId; /*!< Specifies the standard identifier.\r
+ This parameter can be a value between 0 to 0x7FF. */\r
+\r
+ uint32_t ExtId; /*!< Specifies the extended identifier.\r
+ This parameter can be a value between 0 to 0x1FFFFFFF. */\r
+\r
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that \r
+ will be transmitted. This parameter can be a value \r
+ of @ref CAN_identifier_type */\r
+\r
+ uint8_t RTR; /*!< Specifies the type of frame for the message that will \r
+ be transmitted. This parameter can be a value of \r
+ @ref CAN_remote_transmission_request */\r
+\r
+ uint8_t DLC; /*!< Specifies the length of the frame that will be \r
+ transmitted. This parameter can be a value between \r
+ 0 to 8 */\r
+\r
+ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 \r
+ to 0xFF. */\r
+} CanTxMsg;\r
+\r
+/** \r
+ * @brief CAN Rx message structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t StdId; /*!< Specifies the standard identifier.\r
+ This parameter can be a value between 0 to 0x7FF. */\r
+\r
+ uint32_t ExtId; /*!< Specifies the extended identifier.\r
+ This parameter can be a value between 0 to 0x1FFFFFFF. */\r
+\r
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that \r
+ will be received. This parameter can be a value of \r
+ @ref CAN_identifier_type */\r
+\r
+ uint8_t RTR; /*!< Specifies the type of frame for the received message.\r
+ This parameter can be a value of \r
+ @ref CAN_remote_transmission_request */\r
+\r
+ uint8_t DLC; /*!< Specifies the length of the frame that will be received.\r
+ This parameter can be a value between 0 to 8 */\r
+\r
+ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to \r
+ 0xFF. */\r
+\r
+ uint8_t FMI; /*!< Specifies the index of the filter the message stored in \r
+ the mailbox passes through. This parameter can be a \r
+ value between 0 to 0xFF */\r
+} CanRxMsg;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup CAN_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CAN_InitStatus \r
+ * @{\r
+ */\r
+\r
+#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */\r
+#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */\r
+\r
+\r
+/* Legacy defines */\r
+#define CANINITFAILED CAN_InitStatus_Failed\r
+#define CANINITOK CAN_InitStatus_Success\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_operating_mode \r
+ * @{\r
+ */\r
+\r
+#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */\r
+#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */\r
+#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */\r
+#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */\r
+\r
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \\r
+ ((MODE) == CAN_Mode_LoopBack)|| \\r
+ ((MODE) == CAN_Mode_Silent) || \\r
+ ((MODE) == CAN_Mode_Silent_LoopBack))\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup CAN_operating_mode \r
+ * @{\r
+ */ \r
+#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */\r
+#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */\r
+#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */\r
+\r
+\r
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\\r
+ ((MODE) == CAN_OperatingMode_Normal)|| \\r
+ ((MODE) == CAN_OperatingMode_Sleep))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @defgroup CAN_operating_mode_status\r
+ * @{\r
+ */ \r
+\r
+#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */\r
+#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_synchronisation_jump_width \r
+ * @{\r
+ */\r
+#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r
+#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r
+#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r
+#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r
+\r
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \\r
+ ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_time_quantum_in_bit_segment_1 \r
+ * @{\r
+ */\r
+#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r
+#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r
+#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r
+#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r
+#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */\r
+#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */\r
+#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */\r
+#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */\r
+#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */\r
+#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */\r
+#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */\r
+#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */\r
+#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */\r
+#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */\r
+#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */\r
+#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */\r
+\r
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_time_quantum_in_bit_segment_2 \r
+ * @{\r
+ */\r
+#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r
+#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r
+#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r
+#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r
+#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */\r
+#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */\r
+#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */\r
+#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */\r
+\r
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_clock_prescaler \r
+ * @{\r
+ */\r
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_filter_number \r
+ * @{\r
+ */\r
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_filter_mode \r
+ * @{\r
+ */\r
+#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */\r
+#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */\r
+\r
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \\r
+ ((MODE) == CAN_FilterMode_IdList))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_filter_scale \r
+ * @{\r
+ */\r
+#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */\r
+#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */\r
+\r
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \\r
+ ((SCALE) == CAN_FilterScale_32bit))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_filter_FIFO\r
+ * @{\r
+ */\r
+#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */\r
+#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */\r
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \\r
+ ((FIFO) == CAN_FilterFIFO1))\r
+\r
+/* Legacy defines */\r
+#define CAN_FilterFIFO0 CAN_Filter_FIFO0\r
+#define CAN_FilterFIFO1 CAN_Filter_FIFO1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Start_bank_filter_for_slave_CAN \r
+ * @{\r
+ */\r
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Tx \r
+ * @{\r
+ */\r
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))\r
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))\r
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))\r
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_identifier_type \r
+ * @{\r
+ */\r
+#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */\r
+#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */\r
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \\r
+ ((IDTYPE) == CAN_Id_Extended))\r
+\r
+/* Legacy defines */\r
+#define CAN_ID_STD CAN_Id_Standard \r
+#define CAN_ID_EXT CAN_Id_Extended\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_remote_transmission_request \r
+ * @{\r
+ */\r
+#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */\r
+#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */\r
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))\r
+\r
+/* Legacy defines */\r
+#define CAN_RTR_DATA CAN_RTR_Data \r
+#define CAN_RTR_REMOTE CAN_RTR_Remote\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_transmit_constants \r
+ * @{\r
+ */\r
+#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */\r
+#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */\r
+#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */\r
+#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide \r
+ an empty mailbox */\r
+/* Legacy defines */ \r
+#define CANTXFAILED CAN_TxStatus_Failed\r
+#define CANTXOK CAN_TxStatus_Ok\r
+#define CANTXPENDING CAN_TxStatus_Pending\r
+#define CAN_NO_MB CAN_TxStatus_NoMailBox\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_receive_FIFO_number_constants \r
+ * @{\r
+ */\r
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */\r
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */\r
+\r
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_sleep_constants \r
+ * @{\r
+ */\r
+#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */\r
+#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */\r
+\r
+/* Legacy defines */ \r
+#define CANSLEEPFAILED CAN_Sleep_Failed\r
+#define CANSLEEPOK CAN_Sleep_Ok\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_wake_up_constants \r
+ * @{\r
+ */\r
+#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */\r
+#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */\r
+\r
+/* Legacy defines */\r
+#define CANWAKEUPFAILED CAN_WakeUp_Failed \r
+#define CANWAKEUPOK CAN_WakeUp_Ok \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @defgroup CAN_Error_Code_constants\r
+ * @{\r
+ */ \r
+#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ \r
+#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ \r
+#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ \r
+#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ \r
+#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ \r
+#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ \r
+#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ \r
+#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_flags \r
+ * @{\r
+ */\r
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()\r
+ and CAN_ClearFlag() functions. */\r
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with \r
+ CAN_GetFlagStatus() function. */\r
+\r
+/* Transmit Flags */\r
+#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */\r
+#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */\r
+#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */\r
+\r
+/* Receive Flags */\r
+#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */\r
+#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */\r
+#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */\r
+#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */\r
+#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */\r
+#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */\r
+\r
+/* Operating Mode Flags */\r
+#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */\r
+#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */\r
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. \r
+ In this case the SLAK bit can be polled.*/\r
+\r
+/* Error Flags */\r
+#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */\r
+#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */\r
+#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */\r
+#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */\r
+\r
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \\r
+ ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \\r
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \\r
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \\r
+ ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \\r
+ ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \\r
+ ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \\r
+ ((FLAG) == CAN_FLAG_SLAK ))\r
+\r
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \\r
+ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \\r
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\\r
+ ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \\r
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup CAN_interrupts \r
+ * @{\r
+ */ \r
+#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/\r
+\r
+/* Receive Interrupts */\r
+#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/\r
+#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/\r
+#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/\r
+#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/\r
+#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/\r
+#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/\r
+\r
+/* Operating Mode Interrupts */\r
+#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/\r
+#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/\r
+\r
+/* Error Interrupts */\r
+#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/\r
+#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/\r
+#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/\r
+#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/\r
+#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/\r
+\r
+/* Flags named as Interrupts : kept only for FW compatibility */\r
+#define CAN_IT_RQCP0 CAN_IT_TME\r
+#define CAN_IT_RQCP1 CAN_IT_TME\r
+#define CAN_IT_RQCP2 CAN_IT_TME\r
+\r
+\r
+#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\\r
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\\r
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\\r
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\\r
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\r
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
+\r
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\\r
+ ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\\r
+ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\\r
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\r
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+/* Function used to set the CAN configuration to the default reset state *****/ \r
+void CAN_DeInit(CAN_TypeDef* CANx);\r
+\r
+/* Initialization and Configuration functions *********************************/ \r
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);\r
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);\r
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);\r
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber); \r
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);\r
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);\r
+\r
+/* CAN Frames Transmission functions ******************************************/\r
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);\r
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);\r
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);\r
+\r
+/* CAN Frames Reception functions *********************************************/\r
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);\r
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);\r
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);\r
+\r
+/* Operation modes functions **************************************************/\r
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);\r
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);\r
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);\r
+\r
+/* CAN Bus Error management functions *****************************************/\r
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);\r
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);\r
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);\r
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);\r
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);\r
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);\r
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F4xx_CAN_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_crc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the CRC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_CRC_H\r
+#define __STM32F4xx_CRC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup CRC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+void CRC_ResetDR(void);\r
+uint32_t CRC_CalcCRC(uint32_t Data);\r
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);\r
+uint32_t CRC_GetCRC(void);\r
+void CRC_SetIDRegister(uint8_t IDValue);\r
+uint8_t CRC_GetIDRegister(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F4xx_CRC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_cryp.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the Cryptographic\r
+ * processor(CRYP) firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_CRYP_H\r
+#define __STM32F4xx_CRYP_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRYP\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief CRYP Init structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint16_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a \r
+ value of @ref CRYP_Algorithm_Direction */\r
+ uint16_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, \r
+ AES-CBC, AES-CTR, AES-Key. This parameter can be\r
+ a value of @ref CRYP_Algorithm_Mode */\r
+ uint16_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit-string.\r
+ This parameter can be a value of @ref CRYP_Data_Type */ \r
+ uint16_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit \r
+ key length. This parameter can be a value of \r
+ @ref CRYP_Key_Size_for_AES_only */\r
+}CRYP_InitTypeDef;\r
+\r
+/** \r
+ * @brief CRYP Key(s) structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t CRYP_Key0Left; /*!< Key 0 Left */\r
+ uint32_t CRYP_Key0Right; /*!< Key 0 Right */\r
+ uint32_t CRYP_Key1Left; /*!< Key 1 left */\r
+ uint32_t CRYP_Key1Right; /*!< Key 1 Right */\r
+ uint32_t CRYP_Key2Left; /*!< Key 2 left */\r
+ uint32_t CRYP_Key2Right; /*!< Key 2 Right */\r
+ uint32_t CRYP_Key3Left; /*!< Key 3 left */\r
+ uint32_t CRYP_Key3Right; /*!< Key 3 Right */\r
+}CRYP_KeyInitTypeDef;\r
+/** \r
+ * @brief CRYP Initialization Vectors (IV) structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t CRYP_IV0Left; /*!< Init Vector 0 Left */\r
+ uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */\r
+ uint32_t CRYP_IV1Left; /*!< Init Vector 1 left */\r
+ uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */\r
+}CRYP_IVInitTypeDef;\r
+\r
+/** \r
+ * @brief CRYP context swapping structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ /*!< Configuration */\r
+ uint32_t CR_bits9to2;\r
+ /*!< KEY */\r
+ uint32_t CRYP_IV0LR;\r
+ uint32_t CRYP_IV0RR;\r
+ uint32_t CRYP_IV1LR;\r
+ uint32_t CRYP_IV1RR;\r
+ /*!< IV */\r
+ uint32_t CRYP_K0LR;\r
+ uint32_t CRYP_K0RR;\r
+ uint32_t CRYP_K1LR;\r
+ uint32_t CRYP_K1RR;\r
+ uint32_t CRYP_K2LR;\r
+ uint32_t CRYP_K2RR;\r
+ uint32_t CRYP_K3LR;\r
+ uint32_t CRYP_K3RR;\r
+}CRYP_Context;\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup CRYP_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRYP_Algorithm_Direction \r
+ * @{\r
+ */\r
+#define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000)\r
+#define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004)\r
+#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \\r
+ ((ALGODIR) == CRYP_AlgoDir_Decrypt))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup CRYP_Algorithm_Mode \r
+ * @{\r
+ */\r
+\r
+/*!< TDES Modes */\r
+#define CRYP_AlgoMode_TDES_ECB ((uint16_t)0x0000)\r
+#define CRYP_AlgoMode_TDES_CBC ((uint16_t)0x0008)\r
+\r
+/*!< DES Modes */\r
+#define CRYP_AlgoMode_DES_ECB ((uint16_t)0x0010)\r
+#define CRYP_AlgoMode_DES_CBC ((uint16_t)0x0018)\r
+\r
+/*!< AES Modes */\r
+#define CRYP_AlgoMode_AES_ECB ((uint16_t)0x0020)\r
+#define CRYP_AlgoMode_AES_CBC ((uint16_t)0x0028)\r
+#define CRYP_AlgoMode_AES_CTR ((uint16_t)0x0030)\r
+#define CRYP_AlgoMode_AES_Key ((uint16_t)0x0038)\r
+\r
+#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \\r
+ ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \\r
+ ((ALGOMODE) == CRYP_AlgoMode_DES_ECB)|| \\r
+ ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \\r
+ ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \\r
+ ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \\r
+ ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \\r
+ ((ALGOMODE) == CRYP_AlgoMode_AES_Key))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup CRYP_Data_Type \r
+ * @{\r
+ */\r
+#define CRYP_DataType_32b ((uint16_t)0x0000)\r
+#define CRYP_DataType_16b ((uint16_t)0x0040)\r
+#define CRYP_DataType_8b ((uint16_t)0x0080)\r
+#define CRYP_DataType_1b ((uint16_t)0x00C0)\r
+#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \\r
+ ((DATATYPE) == CRYP_DataType_16b)|| \\r
+ ((DATATYPE) == CRYP_DataType_8b)|| \\r
+ ((DATATYPE) == CRYP_DataType_1b)) \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CRYP_Key_Size_for_AES_only \r
+ * @{\r
+ */\r
+#define CRYP_KeySize_128b ((uint16_t)0x0000)\r
+#define CRYP_KeySize_192b ((uint16_t)0x0100)\r
+#define CRYP_KeySize_256b ((uint16_t)0x0200)\r
+#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \\r
+ ((KEYSIZE) == CRYP_KeySize_192b)|| \\r
+ ((KEYSIZE) == CRYP_KeySize_256b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_flags_definition \r
+ * @{\r
+ */\r
+#define CRYP_FLAG_BUSY ((uint8_t)0x10) /*!< The CRYP core is currently \r
+ processing a block of data \r
+ or a key preparation (for \r
+ AES decryption). */\r
+#define CRYP_FLAG_IFEM ((uint8_t)0x01) /*!< Input Fifo Empty */\r
+#define CRYP_FLAG_IFNF ((uint8_t)0x02) /*!< Input Fifo is Not Full */\r
+#define CRYP_FLAG_INRIS ((uint8_t)0x22) /*!< Raw interrupt pending */\r
+#define CRYP_FLAG_OFNE ((uint8_t)0x04) /*!< Input Fifo service raw \r
+ interrupt status */\r
+#define CRYP_FLAG_OFFU ((uint8_t)0x08) /*!< Output Fifo is Full */\r
+#define CRYP_FLAG_OUTRIS ((uint8_t)0x21) /*!< Output Fifo service raw \r
+ interrupt status */\r
+\r
+#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \\r
+ ((FLAG) == CRYP_FLAG_IFNF) || \\r
+ ((FLAG) == CRYP_FLAG_OFNE) || \\r
+ ((FLAG) == CRYP_FLAG_OFFU) || \\r
+ ((FLAG) == CRYP_FLAG_BUSY) || \\r
+ ((FLAG) == CRYP_FLAG_OUTRIS)|| \\r
+ ((FLAG) == CRYP_FLAG_INRIS))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_interrupts_definition \r
+ * @{\r
+ */\r
+#define CRYP_IT_INI ((uint8_t)0x01) /*!< IN Fifo Interrupt */\r
+#define CRYP_IT_OUTI ((uint8_t)0x02) /*!< OUT Fifo Interrupt */\r
+#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))\r
+#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_Encryption_Decryption_modes_definition \r
+ * @{\r
+ */\r
+#define MODE_ENCRYPT ((uint8_t)0x01)\r
+#define MODE_DECRYPT ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_DMA_transfer_requests \r
+ * @{\r
+ */\r
+#define CRYP_DMAReq_DataIN ((uint8_t)0x01)\r
+#define CRYP_DMAReq_DataOUT ((uint8_t)0x02)\r
+#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/* Function used to set the CRYP configuration to the default reset state ****/\r
+void CRYP_DeInit(void);\r
+\r
+/* CRYP Initialization and Configuration functions ****************************/\r
+void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct);\r
+void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct);\r
+void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);\r
+void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);\r
+void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);\r
+void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);\r
+void CRYP_Cmd(FunctionalState NewState);\r
+\r
+/* CRYP Data processing functions *********************************************/\r
+void CRYP_DataIn(uint32_t Data);\r
+uint32_t CRYP_DataOut(void);\r
+void CRYP_FIFOFlush(void);\r
+\r
+/* CRYP Context swapping functions ********************************************/\r
+ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,\r
+ CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);\r
+void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore);\r
+\r
+/* CRYP's DMA interface function **********************************************/\r
+void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState);\r
+ITStatus CRYP_GetITStatus(uint8_t CRYP_IT);\r
+FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG);\r
+\r
+/* High Level AES functions **************************************************/\r
+ErrorStatus CRYP_AES_ECB(uint8_t Mode,\r
+ uint8_t *Key, uint16_t Keysize,\r
+ uint8_t *Input, uint32_t Ilength,\r
+ uint8_t *Output);\r
+\r
+ErrorStatus CRYP_AES_CBC(uint8_t Mode,\r
+ uint8_t InitVectors[16],\r
+ uint8_t *Key, uint16_t Keysize,\r
+ uint8_t *Input, uint32_t Ilength,\r
+ uint8_t *Output);\r
+\r
+ErrorStatus CRYP_AES_CTR(uint8_t Mode,\r
+ uint8_t InitVectors[16],\r
+ uint8_t *Key, uint16_t Keysize,\r
+ uint8_t *Input, uint32_t Ilength,\r
+ uint8_t *Output);\r
+\r
+/* High Level TDES functions **************************************************/\r
+ErrorStatus CRYP_TDES_ECB(uint8_t Mode,\r
+ uint8_t Key[24], \r
+ uint8_t *Input, uint32_t Ilength,\r
+ uint8_t *Output);\r
+\r
+ErrorStatus CRYP_TDES_CBC(uint8_t Mode,\r
+ uint8_t Key[24],\r
+ uint8_t InitVectors[8],\r
+ uint8_t *Input, uint32_t Ilength,\r
+ uint8_t *Output);\r
+\r
+/* High Level DES functions **************************************************/\r
+ErrorStatus CRYP_DES_ECB(uint8_t Mode,\r
+ uint8_t Key[8],\r
+ uint8_t *Input, uint32_t Ilength,\r
+ uint8_t *Output);\r
+\r
+ErrorStatus CRYP_DES_CBC(uint8_t Mode,\r
+ uint8_t Key[8],\r
+ uint8_t InitVectors[8],\r
+ uint8_t *Input,uint32_t Ilength,\r
+ uint8_t *Output);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F4xx_CRYP_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_dac.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the DAC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_DAC_H\r
+#define __STM32F4xx_DAC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DAC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief DAC Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.\r
+ This parameter can be a value of @ref DAC_trigger_selection */\r
+\r
+ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves\r
+ are generated, or whether no wave is generated.\r
+ This parameter can be a value of @ref DAC_wave_generation */\r
+\r
+ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or\r
+ the maximum amplitude triangle generation for the DAC channel. \r
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */\r
+\r
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.\r
+ This parameter can be a value of @ref DAC_output_buffer */\r
+}DAC_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DAC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC_trigger_selection \r
+ * @{\r
+ */\r
+\r
+#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \r
+ has been loaded, and not by external trigger */\r
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ \r
+\r
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */\r
+\r
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \\r
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T8_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T5_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \\r
+ ((TRIGGER) == DAC_Trigger_Software))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_wave_generation \r
+ * @{\r
+ */\r
+\r
+#define DAC_WaveGeneration_None ((uint32_t)0x00000000)\r
+#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)\r
+#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)\r
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \\r
+ ((WAVE) == DAC_WaveGeneration_Noise) || \\r
+ ((WAVE) == DAC_WaveGeneration_Triangle))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_lfsrunmask_triangleamplitude\r
+ * @{\r
+ */\r
+\r
+#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */\r
+#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */\r
+#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */\r
+#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */\r
+#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */\r
+#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */\r
+#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */\r
+#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */\r
+#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */\r
+#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */\r
+#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */\r
+#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */\r
+#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */\r
+\r
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_3) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_7) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_15) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_31) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_63) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_127) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_255) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_511) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_4095))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_output_buffer \r
+ * @{\r
+ */\r
+\r
+#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)\r
+#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)\r
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \\r
+ ((STATE) == DAC_OutputBuffer_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Channel_selection \r
+ * @{\r
+ */\r
+\r
+#define DAC_Channel_1 ((uint32_t)0x00000000)\r
+#define DAC_Channel_2 ((uint32_t)0x00000010)\r
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \\r
+ ((CHANNEL) == DAC_Channel_2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data_alignement \r
+ * @{\r
+ */\r
+\r
+#define DAC_Align_12b_R ((uint32_t)0x00000000)\r
+#define DAC_Align_12b_L ((uint32_t)0x00000004)\r
+#define DAC_Align_8b_R ((uint32_t)0x00000008)\r
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \\r
+ ((ALIGN) == DAC_Align_12b_L) || \\r
+ ((ALIGN) == DAC_Align_8b_R))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_wave_generation \r
+ * @{\r
+ */\r
+\r
+#define DAC_Wave_Noise ((uint32_t)0x00000040)\r
+#define DAC_Wave_Triangle ((uint32_t)0x00000080)\r
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \\r
+ ((WAVE) == DAC_Wave_Triangle))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data \r
+ * @{\r
+ */\r
+\r
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DAC_interrupts_definition \r
+ * @{\r
+ */ \r
+#define DAC_IT_DMAUDR ((uint32_t)0x00002000) \r
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DAC_flags_definition \r
+ * @{\r
+ */ \r
+ \r
+#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) \r
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+/* Function used to set the DAC configuration to the default reset state *****/ \r
+void DAC_DeInit(void);\r
+\r
+/* DAC channels configuration: trigger, output buffer, data format functions */\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);\r
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);\r
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);\r
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);\r
+\r
+/* DMA management functions ***************************************************/\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);\r
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);\r
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F4xx_DAC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_dbgmcu.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the DBGMCU firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_DBGMCU_H\r
+#define __STM32F4xx_DBGMCU_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DBGMCU\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DBGMCU_Exported_Constants\r
+ * @{\r
+ */ \r
+#define DBGMCU_SLEEP ((uint32_t)0x00000001)\r
+#define DBGMCU_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_STANDBY ((uint32_t)0x00000004)\r
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)\r
+#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)\r
+#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008)\r
+#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)\r
+#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)\r
+#define DBGMCU_TIM12_STOP ((uint32_t)0x00000040)\r
+#define DBGMCU_TIM13_STOP ((uint32_t)0x00000080)\r
+#define DBGMCU_TIM14_STOP ((uint32_t)0x00000100)\r
+#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)\r
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)\r
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)\r
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)\r
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)\r
+#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)\r
+#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)\r
+#define DBGMCU_CAN2_STOP ((uint32_t)0x04000000)\r
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)\r
+#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_TIM9_STOP ((uint32_t)0x00010000)\r
+#define DBGMCU_TIM10_STOP ((uint32_t)0x00020000)\r
+#define DBGMCU_TIM11_STOP ((uint32_t)0x00040000)\r
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+uint32_t DBGMCU_GetREVID(void);\r
+uint32_t DBGMCU_GetDEVID(void);\r
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F4xx_DBGMCU_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_dcmi.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the DCMI firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_DCMI_H\r
+#define __STM32F4xx_DCMI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DCMI\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** \r
+ * @brief DCMI Init structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot.\r
+ This parameter can be a value of @ref DCMI_Capture_Mode */\r
+\r
+ uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.\r
+ This parameter can be a value of @ref DCMI_Synchronization_Mode */\r
+\r
+ uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.\r
+ This parameter can be a value of @ref DCMI_PIXCK_Polarity */\r
+\r
+ uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.\r
+ This parameter can be a value of @ref DCMI_VSYNC_Polarity */\r
+\r
+ uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.\r
+ This parameter can be a value of @ref DCMI_HSYNC_Polarity */\r
+\r
+ uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.\r
+ This parameter can be a value of @ref DCMI_Capture_Rate */\r
+\r
+ uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.\r
+ This parameter can be a value of @ref DCMI_Extended_Data_Mode */\r
+} DCMI_InitTypeDef;\r
+\r
+/** \r
+ * @brief DCMI CROP Init structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture\r
+ will start. This parameter can be a value between 0x00 and 0x1FFF */\r
+\r
+ uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture.\r
+ This parameter can be a value between 0x00 and 0x3FFF */\r
+\r
+ uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point.\r
+ This parameter can be a value between 0x00 and 0x3FFF */\r
+\r
+ uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting\r
+ point on the same line.\r
+ This parameter can be a value between 0x00 and 0x3FFF */\r
+} DCMI_CROPInitTypeDef;\r
+\r
+/** \r
+ * @brief DCMI Embedded Synchronisation CODE Init structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */\r
+ uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */\r
+ uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */\r
+ uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */\r
+} DCMI_CodesInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DCMI_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DCMI_Capture_Mode \r
+ * @{\r
+ */ \r
+#define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously \r
+ into the destination memory through the DMA */\r
+#define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of \r
+ frame and then transfers a single frame through the DMA */\r
+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \\r
+ ((MODE) == DCMI_CaptureMode_SnapShot))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DCMI_Synchronization_Mode\r
+ * @{\r
+ */ \r
+#define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop)\r
+ is synchronized with the HSYNC/VSYNC signals */\r
+#define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with \r
+ synchronization codes embedded in the data flow */\r
+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \\r
+ ((MODE) == DCMI_SynchroMode_Embedded))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DCMI_PIXCK_Polarity \r
+ * @{\r
+ */ \r
+#define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */\r
+#define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */\r
+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \\r
+ ((POLARITY) == DCMI_PCKPolarity_Rising))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DCMI_VSYNC_Polarity \r
+ * @{\r
+ */ \r
+#define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */\r
+#define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */\r
+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \\r
+ ((POLARITY) == DCMI_VSPolarity_High))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DCMI_HSYNC_Polarity \r
+ * @{\r
+ */ \r
+#define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */\r
+#define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */\r
+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \\r
+ ((POLARITY) == DCMI_HSPolarity_High))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DCMI_Capture_Rate \r
+ * @{\r
+ */ \r
+#define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */\r
+#define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */\r
+#define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */\r
+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \\r
+ ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\\r
+ ((RATE) == DCMI_CaptureRate_1of4_Frame))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DCMI_Extended_Data_Mode \r
+ * @{\r
+ */ \r
+#define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */\r
+#define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */\r
+#define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */\r
+#define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */\r
+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \\r
+ ((DATA) == DCMI_ExtendedDataMode_10b) ||\\r
+ ((DATA) == DCMI_ExtendedDataMode_12b) ||\\r
+ ((DATA) == DCMI_ExtendedDataMode_14b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DCMI_interrupt_sources \r
+ * @{\r
+ */ \r
+#define DCMI_IT_FRAME ((uint16_t)0x0001)\r
+#define DCMI_IT_OVF ((uint16_t)0x0002)\r
+#define DCMI_IT_ERR ((uint16_t)0x0004)\r
+#define DCMI_IT_VSYNC ((uint16_t)0x0008)\r
+#define DCMI_IT_LINE ((uint16_t)0x0010)\r
+#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))\r
+#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \\r
+ ((IT) == DCMI_IT_OVF) || \\r
+ ((IT) == DCMI_IT_ERR) || \\r
+ ((IT) == DCMI_IT_VSYNC) || \\r
+ ((IT) == DCMI_IT_LINE))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DCMI_Flags \r
+ * @{\r
+ */ \r
+/** \r
+ * @brief DCMI SR register \r
+ */ \r
+#define DCMI_FLAG_HSYNC ((uint16_t)0x2001)\r
+#define DCMI_FLAG_VSYNC ((uint16_t)0x2002)\r
+#define DCMI_FLAG_FNE ((uint16_t)0x2004)\r
+/** \r
+ * @brief DCMI RISR register \r
+ */ \r
+#define DCMI_FLAG_FRAMERI ((uint16_t)0x0001)\r
+#define DCMI_FLAG_OVFRI ((uint16_t)0x0002)\r
+#define DCMI_FLAG_ERRRI ((uint16_t)0x0004)\r
+#define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008)\r
+#define DCMI_FLAG_LINERI ((uint16_t)0x0010)\r
+/** \r
+ * @brief DCMI MISR register \r
+ */ \r
+#define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001)\r
+#define DCMI_FLAG_OVFMI ((uint16_t)0x1002)\r
+#define DCMI_FLAG_ERRMI ((uint16_t)0x1004)\r
+#define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008)\r
+#define DCMI_FLAG_LINEMI ((uint16_t)0x1010)\r
+#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \\r
+ ((FLAG) == DCMI_FLAG_VSYNC) || \\r
+ ((FLAG) == DCMI_FLAG_FNE) || \\r
+ ((FLAG) == DCMI_FLAG_FRAMERI) || \\r
+ ((FLAG) == DCMI_FLAG_OVFRI) || \\r
+ ((FLAG) == DCMI_FLAG_ERRRI) || \\r
+ ((FLAG) == DCMI_FLAG_VSYNCRI) || \\r
+ ((FLAG) == DCMI_FLAG_LINERI) || \\r
+ ((FLAG) == DCMI_FLAG_FRAMEMI) || \\r
+ ((FLAG) == DCMI_FLAG_OVFMI) || \\r
+ ((FLAG) == DCMI_FLAG_ERRMI) || \\r
+ ((FLAG) == DCMI_FLAG_VSYNCMI) || \\r
+ ((FLAG) == DCMI_FLAG_LINEMI))\r
+ \r
+#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+/* Function used to set the DCMI configuration to the default reset state ****/ \r
+void DCMI_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct);\r
+void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct);\r
+void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct);\r
+void DCMI_CROPCmd(FunctionalState NewState);\r
+void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct);\r
+void DCMI_JPEGCmd(FunctionalState NewState);\r
+\r
+/* Image capture functions ****************************************************/\r
+void DCMI_Cmd(FunctionalState NewState);\r
+void DCMI_CaptureCmd(FunctionalState NewState);\r
+uint32_t DCMI_ReadData(void);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState);\r
+FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG);\r
+void DCMI_ClearFlag(uint16_t DCMI_FLAG);\r
+ITStatus DCMI_GetITStatus(uint16_t DCMI_IT);\r
+void DCMI_ClearITPendingBit(uint16_t DCMI_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F4xx_DCMI_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_dma.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the DMA firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_DMA_H\r
+#define __STM32F4xx_DMA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief DMA Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream. \r
+ This parameter can be a value of @ref DMA_channel */\r
+ \r
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */\r
+\r
+ uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx. \r
+ This memory is the default memory used when double buffer mode is\r
+ not enabled. */\r
+\r
+ uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral, \r
+ from memory to memory or from peripheral to memory.\r
+ This parameter can be a value of @ref DMA_data_transfer_direction */\r
+\r
+ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream. \r
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize\r
+ or DMA_MemoryDataSize members depending in the transfer direction. */\r
+\r
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */\r
+\r
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_memory_incremented_mode */\r
+\r
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.\r
+ This parameter can be a value of @ref DMA_peripheral_data_size */\r
+\r
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.\r
+ This parameter can be a value of @ref DMA_memory_data_size */\r
+\r
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx.\r
+ This parameter can be a value of @ref DMA_circular_normal_mode\r
+ @note The circular buffer mode cannot be used if the memory-to-memory\r
+ data transfer is configured on the selected Stream */\r
+\r
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx.\r
+ This parameter can be a value of @ref DMA_priority_level */\r
+\r
+ uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.\r
+ This parameter can be a value of @ref DMA_fifo_direct_mode\r
+ @note The Direct mode (FIFO mode disabled) cannot be used if the \r
+ memory-to-memory data transfer is configured on the selected Stream */\r
+\r
+ uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level.\r
+ This parameter can be a value of @ref DMA_fifo_threshold_level */\r
+\r
+ uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. \r
+ It specifies the amount of data to be transferred in a single non interruptable \r
+ transaction. This parameter can be a value of @ref DMA_memory_burst \r
+ @note The burst mode is possible only if the address Increment mode is enabled. */\r
+\r
+ uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. \r
+ It specifies the amount of data to be transferred in a single non interruptable \r
+ transaction. This parameter can be a value of @ref DMA_peripheral_burst\r
+ @note The burst mode is possible only if the address Increment mode is enabled. */ \r
+}DMA_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \\r
+ ((PERIPH) == DMA1_Stream1) || \\r
+ ((PERIPH) == DMA1_Stream2) || \\r
+ ((PERIPH) == DMA1_Stream3) || \\r
+ ((PERIPH) == DMA1_Stream4) || \\r
+ ((PERIPH) == DMA1_Stream5) || \\r
+ ((PERIPH) == DMA1_Stream6) || \\r
+ ((PERIPH) == DMA1_Stream7) || \\r
+ ((PERIPH) == DMA2_Stream0) || \\r
+ ((PERIPH) == DMA2_Stream1) || \\r
+ ((PERIPH) == DMA2_Stream2) || \\r
+ ((PERIPH) == DMA2_Stream3) || \\r
+ ((PERIPH) == DMA2_Stream4) || \\r
+ ((PERIPH) == DMA2_Stream5) || \\r
+ ((PERIPH) == DMA2_Stream6) || \\r
+ ((PERIPH) == DMA2_Stream7))\r
+\r
+#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \\r
+ ((CONTROLLER) == DMA2))\r
+\r
+/** @defgroup DMA_channel \r
+ * @{\r
+ */ \r
+#define DMA_Channel_0 ((uint32_t)0x00000000)\r
+#define DMA_Channel_1 ((uint32_t)0x02000000)\r
+#define DMA_Channel_2 ((uint32_t)0x04000000)\r
+#define DMA_Channel_3 ((uint32_t)0x06000000)\r
+#define DMA_Channel_4 ((uint32_t)0x08000000)\r
+#define DMA_Channel_5 ((uint32_t)0x0A000000)\r
+#define DMA_Channel_6 ((uint32_t)0x0C000000)\r
+#define DMA_Channel_7 ((uint32_t)0x0E000000)\r
+\r
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \\r
+ ((CHANNEL) == DMA_Channel_1) || \\r
+ ((CHANNEL) == DMA_Channel_2) || \\r
+ ((CHANNEL) == DMA_Channel_3) || \\r
+ ((CHANNEL) == DMA_Channel_4) || \\r
+ ((CHANNEL) == DMA_Channel_5) || \\r
+ ((CHANNEL) == DMA_Channel_6) || \\r
+ ((CHANNEL) == DMA_Channel_7))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_data_transfer_direction \r
+ * @{\r
+ */ \r
+#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000)\r
+#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) \r
+#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080)\r
+\r
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \\r
+ ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \\r
+ ((DIRECTION) == DMA_DIR_MemoryToMemory)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_data_buffer_size \r
+ * @{\r
+ */ \r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_peripheral_incremented_mode \r
+ * @{\r
+ */ \r
+#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200)\r
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)\r
+\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \\r
+ ((STATE) == DMA_PeripheralInc_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_memory_incremented_mode \r
+ * @{\r
+ */ \r
+#define DMA_MemoryInc_Enable ((uint32_t)0x00000400)\r
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)\r
+\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \\r
+ ((STATE) == DMA_MemoryInc_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_peripheral_data_size \r
+ * @{\r
+ */ \r
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) \r
+#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) \r
+#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000)\r
+\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_Word))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_memory_data_size \r
+ * @{\r
+ */ \r
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) \r
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) \r
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000)\r
+\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \\r
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_MemoryDataSize_Word ))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_circular_normal_mode \r
+ * @{\r
+ */ \r
+#define DMA_Mode_Normal ((uint32_t)0x00000000) \r
+#define DMA_Mode_Circular ((uint32_t)0x00000100)\r
+\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \\r
+ ((MODE) == DMA_Mode_Circular)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_priority_level \r
+ * @{\r
+ */ \r
+#define DMA_Priority_Low ((uint32_t)0x00000000)\r
+#define DMA_Priority_Medium ((uint32_t)0x00010000) \r
+#define DMA_Priority_High ((uint32_t)0x00020000)\r
+#define DMA_Priority_VeryHigh ((uint32_t)0x00030000)\r
+\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \\r
+ ((PRIORITY) == DMA_Priority_Medium) || \\r
+ ((PRIORITY) == DMA_Priority_High) || \\r
+ ((PRIORITY) == DMA_Priority_VeryHigh)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_fifo_direct_mode \r
+ * @{\r
+ */ \r
+#define DMA_FIFOMode_Disable ((uint32_t)0x00000000) \r
+#define DMA_FIFOMode_Enable ((uint32_t)0x00000004)\r
+\r
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \\r
+ ((STATE) == DMA_FIFOMode_Enable)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_fifo_threshold_level \r
+ * @{\r
+ */ \r
+#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000)\r
+#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) \r
+#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002)\r
+#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003)\r
+\r
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \\r
+ ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \\r
+ ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \\r
+ ((THRESHOLD) == DMA_FIFOThreshold_Full)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_memory_burst \r
+ * @{\r
+ */ \r
+#define DMA_MemoryBurst_Single ((uint32_t)0x00000000)\r
+#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) \r
+#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000)\r
+#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000)\r
+\r
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \\r
+ ((BURST) == DMA_MemoryBurst_INC4) || \\r
+ ((BURST) == DMA_MemoryBurst_INC8) || \\r
+ ((BURST) == DMA_MemoryBurst_INC16))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_peripheral_burst \r
+ * @{\r
+ */ \r
+#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000)\r
+#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) \r
+#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000)\r
+#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000)\r
+\r
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \\r
+ ((BURST) == DMA_PeripheralBurst_INC4) || \\r
+ ((BURST) == DMA_PeripheralBurst_INC8) || \\r
+ ((BURST) == DMA_PeripheralBurst_INC16))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_fifo_status_level \r
+ * @{\r
+ */\r
+#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3)\r
+#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3)\r
+#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) \r
+#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3)\r
+#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3)\r
+#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3)\r
+\r
+#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \\r
+ ((STATUS) == DMA_FIFOStatus_HalfFull) || \\r
+ ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \\r
+ ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \\r
+ ((STATUS) == DMA_FIFOStatus_Full) || \\r
+ ((STATUS) == DMA_FIFOStatus_Empty)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_flags_definition \r
+ * @{\r
+ */\r
+#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001)\r
+#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004)\r
+#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008)\r
+#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010)\r
+#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020)\r
+#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040)\r
+#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100)\r
+#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200)\r
+#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400)\r
+#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800)\r
+#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000)\r
+#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000)\r
+#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000)\r
+#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000)\r
+#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000)\r
+#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000)\r
+#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000)\r
+#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000)\r
+#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000)\r
+#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000)\r
+#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001)\r
+#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004)\r
+#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008)\r
+#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010)\r
+#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020)\r
+#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040)\r
+#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100)\r
+#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200)\r
+#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400)\r
+#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800)\r
+#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000)\r
+#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000)\r
+#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000)\r
+#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000)\r
+#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000)\r
+#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000)\r
+#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000)\r
+#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000)\r
+#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000)\r
+#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000)\r
+\r
+#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \\r
+ (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00))\r
+\r
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \\r
+ ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \\r
+ ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \\r
+ ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \\r
+ ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \\r
+ ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \\r
+ ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \\r
+ ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \\r
+ ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \\r
+ ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \\r
+ ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \\r
+ ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \\r
+ ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \\r
+ ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \\r
+ ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \\r
+ ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \\r
+ ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \\r
+ ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \\r
+ ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \\r
+ ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_interrupt_enable_definitions \r
+ * @{\r
+ */ \r
+#define DMA_IT_TC ((uint32_t)0x00000010)\r
+#define DMA_IT_HT ((uint32_t)0x00000008)\r
+#define DMA_IT_TE ((uint32_t)0x00000004)\r
+#define DMA_IT_DME ((uint32_t)0x00000002)\r
+#define DMA_IT_FE ((uint32_t)0x00000080)\r
+\r
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_interrupts_definitions \r
+ * @{\r
+ */ \r
+#define DMA_IT_FEIF0 ((uint32_t)0x90000001)\r
+#define DMA_IT_DMEIF0 ((uint32_t)0x10001004)\r
+#define DMA_IT_TEIF0 ((uint32_t)0x10002008)\r
+#define DMA_IT_HTIF0 ((uint32_t)0x10004010)\r
+#define DMA_IT_TCIF0 ((uint32_t)0x10008020)\r
+#define DMA_IT_FEIF1 ((uint32_t)0x90000040)\r
+#define DMA_IT_DMEIF1 ((uint32_t)0x10001100)\r
+#define DMA_IT_TEIF1 ((uint32_t)0x10002200)\r
+#define DMA_IT_HTIF1 ((uint32_t)0x10004400)\r
+#define DMA_IT_TCIF1 ((uint32_t)0x10008800)\r
+#define DMA_IT_FEIF2 ((uint32_t)0x90010000)\r
+#define DMA_IT_DMEIF2 ((uint32_t)0x10041000)\r
+#define DMA_IT_TEIF2 ((uint32_t)0x10082000)\r
+#define DMA_IT_HTIF2 ((uint32_t)0x10104000)\r
+#define DMA_IT_TCIF2 ((uint32_t)0x10208000)\r
+#define DMA_IT_FEIF3 ((uint32_t)0x90400000)\r
+#define DMA_IT_DMEIF3 ((uint32_t)0x11001000)\r
+#define DMA_IT_TEIF3 ((uint32_t)0x12002000)\r
+#define DMA_IT_HTIF3 ((uint32_t)0x14004000)\r
+#define DMA_IT_TCIF3 ((uint32_t)0x18008000)\r
+#define DMA_IT_FEIF4 ((uint32_t)0xA0000001)\r
+#define DMA_IT_DMEIF4 ((uint32_t)0x20001004)\r
+#define DMA_IT_TEIF4 ((uint32_t)0x20002008)\r
+#define DMA_IT_HTIF4 ((uint32_t)0x20004010)\r
+#define DMA_IT_TCIF4 ((uint32_t)0x20008020)\r
+#define DMA_IT_FEIF5 ((uint32_t)0xA0000040)\r
+#define DMA_IT_DMEIF5 ((uint32_t)0x20001100)\r
+#define DMA_IT_TEIF5 ((uint32_t)0x20002200)\r
+#define DMA_IT_HTIF5 ((uint32_t)0x20004400)\r
+#define DMA_IT_TCIF5 ((uint32_t)0x20008800)\r
+#define DMA_IT_FEIF6 ((uint32_t)0xA0010000)\r
+#define DMA_IT_DMEIF6 ((uint32_t)0x20041000)\r
+#define DMA_IT_TEIF6 ((uint32_t)0x20082000)\r
+#define DMA_IT_HTIF6 ((uint32_t)0x20104000)\r
+#define DMA_IT_TCIF6 ((uint32_t)0x20208000)\r
+#define DMA_IT_FEIF7 ((uint32_t)0xA0400000)\r
+#define DMA_IT_DMEIF7 ((uint32_t)0x21001000)\r
+#define DMA_IT_TEIF7 ((uint32_t)0x22002000)\r
+#define DMA_IT_HTIF7 ((uint32_t)0x24004000)\r
+#define DMA_IT_TCIF7 ((uint32_t)0x28008000)\r
+\r
+#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \\r
+ (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \\r
+ (((IT) & 0x40820082) == 0x00))\r
+\r
+#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \\r
+ ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \\r
+ ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \\r
+ ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \\r
+ ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \\r
+ ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \\r
+ ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \\r
+ ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \\r
+ ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \\r
+ ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \\r
+ ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \\r
+ ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \\r
+ ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \\r
+ ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \\r
+ ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \\r
+ ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \\r
+ ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \\r
+ ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \\r
+ ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \\r
+ ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_peripheral_increment_offset \r
+ * @{\r
+ */ \r
+#define DMA_PINCOS_Psize ((uint32_t)0x00000000)\r
+#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000)\r
+\r
+#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \\r
+ ((SIZE) == DMA_PINCOS_WordAligned))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_flow_controller_definitions \r
+ * @{\r
+ */ \r
+#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000)\r
+#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020)\r
+\r
+#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \\r
+ ((CTRL) == DMA_FlowCtrl_Peripheral))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_memory_targets_definitions \r
+ * @{\r
+ */ \r
+#define DMA_Memory_0 ((uint32_t)0x00000000)\r
+#define DMA_Memory_1 ((uint32_t)0x00080000)\r
+\r
+#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+/* Function used to set the DMA configuration to the default reset state *****/ \r
+void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);\r
+\r
+/* Optional Configuration functions *******************************************/\r
+void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);\r
+void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);\r
+\r
+/* Data Counter functions *****************************************************/\r
+void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);\r
+uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);\r
+\r
+/* Double Buffer mode functions ***********************************************/\r
+void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,\r
+ uint32_t DMA_CurrentMemory);\r
+void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);\r
+void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,\r
+ uint32_t DMA_MemoryTarget);\r
+uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);\r
+uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);\r
+FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);\r
+void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);\r
+void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);\r
+ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);\r
+void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F4xx_DMA_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_exti.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the EXTI firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_EXTI_H\r
+#define __STM32F4xx_EXTI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup EXTI\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief EXTI mode enumeration \r
+ */\r
+\r
+typedef enum\r
+{\r
+ EXTI_Mode_Interrupt = 0x00,\r
+ EXTI_Mode_Event = 0x04\r
+}EXTIMode_TypeDef;\r
+\r
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))\r
+\r
+/** \r
+ * @brief EXTI Trigger enumeration \r
+ */\r
+\r
+typedef enum\r
+{\r
+ EXTI_Trigger_Rising = 0x08,\r
+ EXTI_Trigger_Falling = 0x0C, \r
+ EXTI_Trigger_Rising_Falling = 0x10\r
+}EXTITrigger_TypeDef;\r
+\r
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \\r
+ ((TRIGGER) == EXTI_Trigger_Falling) || \\r
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))\r
+/** \r
+ * @brief EXTI Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.\r
+ This parameter can be any combination value of @ref EXTI_Lines */\r
+ \r
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.\r
+ This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.\r
+ This parameter can be a value of @ref EXTITrigger_TypeDef */\r
+\r
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.\r
+ This parameter can be set either to ENABLE or DISABLE */ \r
+}EXTI_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup EXTI_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Lines \r
+ * @{\r
+ */\r
+\r
+#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */\r
+#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */\r
+#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */\r
+#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */\r
+#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */\r
+#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */\r
+#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */\r
+#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */\r
+#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */\r
+#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */\r
+#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */\r
+#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */\r
+#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */\r
+#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */\r
+#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */\r
+#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */\r
+#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */\r
+#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */\r
+#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ \r
+#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */\r
+#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */\r
+#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ \r
+#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ \r
+ \r
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))\r
+\r
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \\r
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \\r
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \\r
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \\r
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \\r
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \\r
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \\r
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \\r
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \\r
+ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \\r
+ ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\\r
+ ((LINE) == EXTI_Line22))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/* Function used to set the EXTI configuration to the default reset state *****/\r
+void EXTI_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearFlag(uint32_t EXTI_Line);\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F4xx_EXTI_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_flash.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the FLASH \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_FLASH_H\r
+#define __STM32F4xx_FLASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** \r
+ * @brief FLASH Status \r
+ */ \r
+typedef enum\r
+{ \r
+ FLASH_BUSY = 1,\r
+ FLASH_ERROR_PGS,\r
+ FLASH_ERROR_PGP,\r
+ FLASH_ERROR_PGA,\r
+ FLASH_ERROR_WRP,\r
+ FLASH_ERROR_PROGRAM,\r
+ FLASH_ERROR_OPERATION,\r
+ FLASH_COMPLETE\r
+}FLASH_Status;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup FLASH_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup Flash_Latency \r
+ * @{\r
+ */ \r
+#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */\r
+#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */\r
+#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */\r
+#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */\r
+#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */\r
+#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */\r
+#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */\r
+#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */\r
+\r
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \\r
+ ((LATENCY) == FLASH_Latency_1) || \\r
+ ((LATENCY) == FLASH_Latency_2) || \\r
+ ((LATENCY) == FLASH_Latency_3) || \\r
+ ((LATENCY) == FLASH_Latency_4) || \\r
+ ((LATENCY) == FLASH_Latency_5) || \\r
+ ((LATENCY) == FLASH_Latency_6) || \\r
+ ((LATENCY) == FLASH_Latency_7))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Voltage_Range \r
+ * @{\r
+ */ \r
+#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */\r
+#define VoltageRange_2 ((uint8_t)0x01) /*!<Device operating range: 2.1V to 2.7V */\r
+#define VoltageRange_3 ((uint8_t)0x02) /*!<Device operating range: 2.7V to 3.6V */\r
+#define VoltageRange_4 ((uint8_t)0x03) /*!<Device operating range: 2.7V to 3.6V + External Vpp */\r
+\r
+#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \\r
+ ((RANGE) == VoltageRange_2) || \\r
+ ((RANGE) == VoltageRange_3) || \\r
+ ((RANGE) == VoltageRange_4)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Sectors\r
+ * @{\r
+ */ \r
+#define FLASH_Sector_0 ((uint16_t)0x0000) /*!< Sector Number 0 */\r
+#define FLASH_Sector_1 ((uint16_t)0x0008) /*!< Sector Number 1 */\r
+#define FLASH_Sector_2 ((uint16_t)0x0010) /*!< Sector Number 2 */\r
+#define FLASH_Sector_3 ((uint16_t)0x0018) /*!< Sector Number 3 */\r
+#define FLASH_Sector_4 ((uint16_t)0x0020) /*!< Sector Number 4 */\r
+#define FLASH_Sector_5 ((uint16_t)0x0028) /*!< Sector Number 5 */\r
+#define FLASH_Sector_6 ((uint16_t)0x0030) /*!< Sector Number 6 */\r
+#define FLASH_Sector_7 ((uint16_t)0x0038) /*!< Sector Number 7 */\r
+#define FLASH_Sector_8 ((uint16_t)0x0040) /*!< Sector Number 8 */\r
+#define FLASH_Sector_9 ((uint16_t)0x0048) /*!< Sector Number 9 */\r
+#define FLASH_Sector_10 ((uint16_t)0x0050) /*!< Sector Number 10 */\r
+#define FLASH_Sector_11 ((uint16_t)0x0058) /*!< Sector Number 11 */\r
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\\r
+ ((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\\r
+ ((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\\r
+ ((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\\r
+ ((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\\r
+ ((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11))\r
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\\r
+ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Option_Bytes_Write_Protection \r
+ * @{\r
+ */ \r
+#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */\r
+#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */\r
+#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */\r
+#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */\r
+#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */\r
+#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */\r
+#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */\r
+#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */\r
+#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */\r
+#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */\r
+#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */\r
+#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */\r
+#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */\r
+\r
+#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Option_Bytes_Read_Protection \r
+ * @{\r
+ */\r
+#define OB_RDP_Level_0 ((uint8_t)0xAA)\r
+#define OB_RDP_Level_1 ((uint8_t)0x55)\r
+/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 \r
+ it's no more possible to go back to level 1 or 0 */\r
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\\r
+ ((LEVEL) == OB_RDP_Level_1))/*||\\r
+ ((LEVEL) == OB_RDP_Level_2))*/\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Option_Bytes_IWatchdog \r
+ * @{\r
+ */ \r
+#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */\r
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */\r
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Option_Bytes_nRST_STOP \r
+ * @{\r
+ */ \r
+#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */\r
+#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */\r
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup FLASH_Option_Bytes_nRST_STDBY \r
+ * @{\r
+ */ \r
+#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */\r
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */\r
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASH_BOR_Reset_Level \r
+ * @{\r
+ */ \r
+#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */\r
+#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */\r
+#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */\r
+#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */\r
+#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\\r
+ ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Interrupts \r
+ * @{\r
+ */ \r
+#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */\r
+#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */\r
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Flags \r
+ * @{\r
+ */ \r
+#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */\r
+#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */\r
+#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */\r
+#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */\r
+#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */\r
+#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */\r
+#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ \r
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000))\r
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \\r
+ ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \\r
+ ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \\r
+ ((FLAG) == FLASH_FLAG_BSY))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Program_Parallelism \r
+ * @{\r
+ */\r
+#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000)\r
+#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100)\r
+#define FLASH_PSIZE_WORD ((uint32_t)0x00000200)\r
+#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300)\r
+#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Keys \r
+ * @{\r
+ */ \r
+#define RDP_KEY ((uint16_t)0x00A5)\r
+#define FLASH_KEY1 ((uint32_t)0x45670123)\r
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)\r
+#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)\r
+#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** \r
+ * @brief ACR register byte 0 (Bits[8:0]) base address \r
+ */ \r
+#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) \r
+/** \r
+ * @brief OPTCR register byte 3 (Bits[24:16]) base address \r
+ */ \r
+#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)\r
+#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)\r
+#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+ \r
+/* FLASH Interface configuration functions ************************************/\r
+void FLASH_SetLatency(uint32_t FLASH_Latency);\r
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);\r
+void FLASH_InstructionCacheCmd(FunctionalState NewState);\r
+void FLASH_DataCacheCmd(FunctionalState NewState);\r
+void FLASH_InstructionCacheReset(void);\r
+void FLASH_DataCacheReset(void);\r
+\r
+/* FLASH Memory Programming functions *****************************************/ \r
+void FLASH_Unlock(void);\r
+void FLASH_Lock(void);\r
+FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);\r
+FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);\r
+FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);\r
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);\r
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
+FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);\r
+\r
+/* Option Bytes Programming functions *****************************************/ \r
+void FLASH_OB_Unlock(void);\r
+void FLASH_OB_Lock(void);\r
+void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);\r
+void FLASH_OB_RDPConfig(uint8_t OB_RDP);\r
+void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);\r
+void FLASH_OB_BORConfig(uint8_t OB_BOR);\r
+FLASH_Status FLASH_OB_Launch(void);\r
+uint8_t FLASH_OB_GetUser(void);\r
+uint16_t FLASH_OB_GetWRP(void);\r
+FlagStatus FLASH_OB_GetRDP(void);\r
+uint8_t FLASH_OB_GetBOR(void);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);\r
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);\r
+FLASH_Status FLASH_GetStatus(void);\r
+FLASH_Status FLASH_WaitForLastOperation(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F4xx_FLASH_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_fsmc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the FSMC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_FSMC_H\r
+#define __STM32F4xx_FSMC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FSMC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief Timing parameters For NOR/SRAM Banks \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the address setup time. \r
+ This parameter can be a value between 0 and 0xF.\r
+ @note This parameter is not used with synchronous NOR Flash memories. */\r
+\r
+ uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the address hold time.\r
+ This parameter can be a value between 0 and 0xF. \r
+ @note This parameter is not used with synchronous NOR Flash memories.*/\r
+\r
+ uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the data setup time.\r
+ This parameter can be a value between 0 and 0xFF.\r
+ @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */\r
+\r
+ uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the bus turnaround.\r
+ This parameter can be a value between 0 and 0xF.\r
+ @note This parameter is only used for multiplexed NOR Flash memories. */\r
+\r
+ uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.\r
+ This parameter can be a value between 1 and 0xF.\r
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */\r
+\r
+ uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue\r
+ to the memory before getting the first data.\r
+ The parameter value depends on the memory type as shown below:\r
+ - It must be set to 0 in case of a CRAM\r
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses\r
+ - It may assume a value between 0 and 0xF in NOR Flash memories\r
+ with synchronous burst mode enable */\r
+\r
+ uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. \r
+ This parameter can be a value of @ref FSMC_Access_Mode */\r
+}FSMC_NORSRAMTimingInitTypeDef;\r
+\r
+/** \r
+ * @brief FSMC NOR/SRAM Init structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.\r
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */\r
+\r
+ uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are\r
+ multiplexed on the databus or not. \r
+ This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */\r
+\r
+ uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to\r
+ the corresponding memory bank.\r
+ This parameter can be a value of @ref FSMC_Memory_Type */\r
+\r
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.\r
+ This parameter can be a value of @ref FSMC_Data_Width */\r
+\r
+ uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,\r
+ valid only with synchronous burst Flash memories.\r
+ This parameter can be a value of @ref FSMC_Burst_Access_Mode */\r
+\r
+ uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,\r
+ valid only with asynchronous Flash memories.\r
+ This parameter can be a value of @ref FSMC_AsynchronousWait */ \r
+\r
+ uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing\r
+ the Flash memory in burst mode.\r
+ This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */\r
+\r
+ uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash\r
+ memory, valid only when accessing Flash memories in burst mode.\r
+ This parameter can be a value of @ref FSMC_Wrap_Mode */\r
+\r
+ uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one\r
+ clock cycle before the wait state or during the wait state,\r
+ valid only when accessing memories in burst mode. \r
+ This parameter can be a value of @ref FSMC_Wait_Timing */\r
+\r
+ uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. \r
+ This parameter can be a value of @ref FSMC_Write_Operation */\r
+\r
+ uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait\r
+ signal, valid for Flash memory access in burst mode. \r
+ This parameter can be a value of @ref FSMC_Wait_Signal */\r
+\r
+ uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.\r
+ This parameter can be a value of @ref FSMC_Extended_Mode */\r
+\r
+ uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.\r
+ This parameter can be a value of @ref FSMC_Write_Burst */ \r
+\r
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ \r
+\r
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ \r
+}FSMC_NORSRAMInitTypeDef;\r
+\r
+/** \r
+ * @brief Timing parameters For FSMC NAND and PCCARD Banks\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before\r
+ the command assertion for NAND-Flash read or write access\r
+ to common/Attribute or I/O memory space (depending on\r
+ the memory space timing to be configured).\r
+ This parameter can be a value between 0 and 0xFF.*/\r
+\r
+ uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the\r
+ command for NAND-Flash read or write access to\r
+ common/Attribute or I/O memory space (depending on the\r
+ memory space timing to be configured). \r
+ This parameter can be a number between 0x00 and 0xFF */\r
+\r
+ uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address\r
+ (and data for write access) after the command deassertion\r
+ for NAND-Flash read or write access to common/Attribute\r
+ or I/O memory space (depending on the memory space timing\r
+ to be configured).\r
+ This parameter can be a number between 0x00 and 0xFF */\r
+\r
+ uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the\r
+ databus is kept in HiZ after the start of a NAND-Flash\r
+ write access to common/Attribute or I/O memory space (depending\r
+ on the memory space timing to be configured).\r
+ This parameter can be a number between 0x00 and 0xFF */\r
+}FSMC_NAND_PCCARDTimingInitTypeDef;\r
+\r
+/** \r
+ * @brief FSMC NAND Init structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.\r
+ This parameter can be a value of @ref FSMC_NAND_Bank */\r
+\r
+ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.\r
+ This parameter can be any value of @ref FSMC_Wait_feature */\r
+\r
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.\r
+ This parameter can be any value of @ref FSMC_Data_Width */\r
+\r
+ uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.\r
+ This parameter can be any value of @ref FSMC_ECC */\r
+\r
+ uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.\r
+ This parameter can be any value of @ref FSMC_ECC_Page_Size */\r
+\r
+ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
+ delay between CLE low and RE low.\r
+ This parameter can be a value between 0 and 0xFF. */\r
+\r
+ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
+ delay between ALE low and RE low.\r
+ This parameter can be a number between 0x0 and 0xFF */ \r
+\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ \r
+\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */\r
+}FSMC_NANDInitTypeDef;\r
+\r
+/** \r
+ * @brief FSMC PCCARD Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.\r
+ This parameter can be any value of @ref FSMC_Wait_feature */\r
+\r
+ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
+ delay between CLE low and RE low.\r
+ This parameter can be a value between 0 and 0xFF. */\r
+\r
+ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
+ delay between ALE low and RE low.\r
+ This parameter can be a number between 0x0 and 0xFF */ \r
+\r
+ \r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */\r
+\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ \r
+ \r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ \r
+}FSMC_PCCARDInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup FSMC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_NORSRAM_Bank \r
+ * @{\r
+ */\r
+#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)\r
+#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)\r
+#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)\r
+#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_NAND_Bank \r
+ * @{\r
+ */ \r
+#define FSMC_Bank2_NAND ((uint32_t)0x00000010)\r
+#define FSMC_Bank3_NAND ((uint32_t)0x00000100)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_PCCARD_Bank \r
+ * @{\r
+ */ \r
+#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM2) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM3) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM4))\r
+\r
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
+ ((BANK) == FSMC_Bank3_NAND))\r
+\r
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
+ ((BANK) == FSMC_Bank3_NAND) || \\r
+ ((BANK) == FSMC_Bank4_PCCARD))\r
+\r
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
+ ((BANK) == FSMC_Bank3_NAND) || \\r
+ ((BANK) == FSMC_Bank4_PCCARD))\r
+\r
+/** @defgroup FSMC_NOR_SRAM_Controller \r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing \r
+ * @{\r
+ */\r
+\r
+#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)\r
+#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)\r
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \\r
+ ((MUX) == FSMC_DataAddressMux_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Memory_Type \r
+ * @{\r
+ */\r
+\r
+#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)\r
+#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)\r
+#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)\r
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \\r
+ ((MEMORY) == FSMC_MemoryType_PSRAM)|| \\r
+ ((MEMORY) == FSMC_MemoryType_NOR))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Width \r
+ * @{\r
+ */\r
+\r
+#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)\r
+#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)\r
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \\r
+ ((WIDTH) == FSMC_MemoryDataWidth_16b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Burst_Access_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) \r
+#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)\r
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \\r
+ ((STATE) == FSMC_BurstAccessMode_Enable))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FSMC_AsynchronousWait \r
+ * @{\r
+ */\r
+#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)\r
+#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)\r
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \\r
+ ((STATE) == FSMC_AsynchronousWait_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Signal_Polarity \r
+ * @{\r
+ */\r
+#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)\r
+#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)\r
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \\r
+ ((POLARITY) == FSMC_WaitSignalPolarity_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wrap_Mode \r
+ * @{\r
+ */\r
+#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) \r
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \\r
+ ((MODE) == FSMC_WrapMode_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Timing \r
+ * @{\r
+ */\r
+#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)\r
+#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) \r
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \\r
+ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Write_Operation \r
+ * @{\r
+ */\r
+#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)\r
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \\r
+ ((OPERATION) == FSMC_WriteOperation_Enable)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Signal \r
+ * @{\r
+ */\r
+#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) \r
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \\r
+ ((SIGNAL) == FSMC_WaitSignal_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Extended_Mode \r
+ * @{\r
+ */\r
+#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)\r
+#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)\r
+\r
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \\r
+ ((MODE) == FSMC_ExtendedMode_Enable)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Write_Burst \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) \r
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \\r
+ ((BURST) == FSMC_WriteBurst_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Address_Setup_Time \r
+ * @{\r
+ */\r
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Address_Hold_Time \r
+ * @{\r
+ */\r
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Setup_Time \r
+ * @{\r
+ */\r
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Bus_Turn_around_Duration \r
+ * @{\r
+ */\r
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_CLK_Division \r
+ * @{\r
+ */\r
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Latency \r
+ * @{\r
+ */\r
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Access_Mode \r
+ * @{\r
+ */\r
+#define FSMC_AccessMode_A ((uint32_t)0x00000000)\r
+#define FSMC_AccessMode_B ((uint32_t)0x10000000) \r
+#define FSMC_AccessMode_C ((uint32_t)0x20000000)\r
+#define FSMC_AccessMode_D ((uint32_t)0x30000000)\r
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \\r
+ ((MODE) == FSMC_AccessMode_B) || \\r
+ ((MODE) == FSMC_AccessMode_C) || \\r
+ ((MODE) == FSMC_AccessMode_D))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FSMC_NAND_PCCARD_Controller \r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_feature \r
+ * @{\r
+ */\r
+#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)\r
+#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)\r
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \\r
+ ((FEATURE) == FSMC_Waitfeature_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup FSMC_ECC \r
+ * @{\r
+ */\r
+#define FSMC_ECC_Disable ((uint32_t)0x00000000)\r
+#define FSMC_ECC_Enable ((uint32_t)0x00000040)\r
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \\r
+ ((STATE) == FSMC_ECC_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_ECC_Page_Size \r
+ * @{\r
+ */\r
+#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)\r
+#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)\r
+#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)\r
+#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)\r
+#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)\r
+#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)\r
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_512Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_8192Bytes))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_TCLR_Setup_Time \r
+ * @{\r
+ */\r
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_TAR_Setup_Time \r
+ * @{\r
+ */\r
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Setup_Time \r
+ * @{\r
+ */\r
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Setup_Time \r
+ * @{\r
+ */\r
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Hold_Setup_Time \r
+ * @{\r
+ */\r
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_HiZ_Setup_Time \r
+ * @{\r
+ */\r
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Interrupt_sources \r
+ * @{\r
+ */\r
+#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)\r
+#define FSMC_IT_Level ((uint32_t)0x00000010)\r
+#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)\r
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))\r
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \\r
+ ((IT) == FSMC_IT_Level) || \\r
+ ((IT) == FSMC_IT_FallingEdge)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Flags \r
+ * @{\r
+ */\r
+#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)\r
+#define FSMC_FLAG_Level ((uint32_t)0x00000002)\r
+#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)\r
+#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)\r
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \\r
+ ((FLAG) == FSMC_FLAG_Level) || \\r
+ ((FLAG) == FSMC_FLAG_FallingEdge) || \\r
+ ((FLAG) == FSMC_FLAG_FEMPT))\r
+\r
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+/* NOR/SRAM Controller functions **********************************************/\r
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);\r
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
+\r
+/* NAND Controller functions **************************************************/\r
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);\r
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);\r
+\r
+/* PCCARD Controller functions ************************************************/\r
+void FSMC_PCCARDDeInit(void);\r
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
+void FSMC_PCCARDCmd(FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);\r
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F4xx_FSMC_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_gpio.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the GPIO firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_GPIO_H\r
+#define __STM32F4xx_GPIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \\r
+ ((PERIPH) == GPIOB) || \\r
+ ((PERIPH) == GPIOC) || \\r
+ ((PERIPH) == GPIOD) || \\r
+ ((PERIPH) == GPIOE) || \\r
+ ((PERIPH) == GPIOF) || \\r
+ ((PERIPH) == GPIOG) || \\r
+ ((PERIPH) == GPIOH) || \\r
+ ((PERIPH) == GPIOI))\r
+ \r
+/** \r
+ * @brief GPIO Configuration Mode enumeration \r
+ */ \r
+typedef enum\r
+{ \r
+ GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */\r
+ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */\r
+ GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */\r
+ GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */\r
+}GPIOMode_TypeDef;\r
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \\r
+ ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))\r
+\r
+/** \r
+ * @brief GPIO Output type enumeration \r
+ */ \r
+typedef enum\r
+{ \r
+ GPIO_OType_PP = 0x00,\r
+ GPIO_OType_OD = 0x01\r
+}GPIOOType_TypeDef;\r
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))\r
+\r
+\r
+/** \r
+ * @brief GPIO Output Maximum frequency enumeration \r
+ */ \r
+typedef enum\r
+{ \r
+ GPIO_Speed_2MHz = 0x00, /*!< Low speed */\r
+ GPIO_Speed_25MHz = 0x01, /*!< Medium speed */\r
+ GPIO_Speed_50MHz = 0x02, /*!< Fast speed */\r
+ GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */\r
+}GPIOSpeed_TypeDef;\r
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \\r
+ ((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz)) \r
+\r
+/** \r
+ * @brief GPIO Configuration PullUp PullDown enumeration \r
+ */ \r
+typedef enum\r
+{ \r
+ GPIO_PuPd_NOPULL = 0x00,\r
+ GPIO_PuPd_UP = 0x01,\r
+ GPIO_PuPd_DOWN = 0x02\r
+}GPIOPuPd_TypeDef;\r
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \\r
+ ((PUPD) == GPIO_PuPd_DOWN))\r
+\r
+/** \r
+ * @brief GPIO Bit SET and Bit RESET enumeration \r
+ */ \r
+typedef enum\r
+{ \r
+ Bit_RESET = 0,\r
+ Bit_SET\r
+}BitAction;\r
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))\r
+\r
+\r
+/** \r
+ * @brief GPIO Init structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.\r
+ This parameter can be any value of @ref GPIO_pins_define */\r
+\r
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref GPIOMode_TypeDef */\r
+\r
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.\r
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */\r
+\r
+ GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.\r
+ This parameter can be a value of @ref GPIOOType_TypeDef */\r
+\r
+ GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.\r
+ This parameter can be a value of @ref GPIOPuPd_TypeDef */\r
+}GPIO_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup GPIO_pins_define \r
+ * @{\r
+ */ \r
+#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */\r
+#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */\r
+#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */\r
+#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */\r
+#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */\r
+#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */\r
+#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */\r
+#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */\r
+#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */\r
+#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */\r
+#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */\r
+#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */\r
+#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */\r
+#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */\r
+#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */\r
+#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */\r
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */\r
+\r
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))\r
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \\r
+ ((PIN) == GPIO_Pin_1) || \\r
+ ((PIN) == GPIO_Pin_2) || \\r
+ ((PIN) == GPIO_Pin_3) || \\r
+ ((PIN) == GPIO_Pin_4) || \\r
+ ((PIN) == GPIO_Pin_5) || \\r
+ ((PIN) == GPIO_Pin_6) || \\r
+ ((PIN) == GPIO_Pin_7) || \\r
+ ((PIN) == GPIO_Pin_8) || \\r
+ ((PIN) == GPIO_Pin_9) || \\r
+ ((PIN) == GPIO_Pin_10) || \\r
+ ((PIN) == GPIO_Pin_11) || \\r
+ ((PIN) == GPIO_Pin_12) || \\r
+ ((PIN) == GPIO_Pin_13) || \\r
+ ((PIN) == GPIO_Pin_14) || \\r
+ ((PIN) == GPIO_Pin_15))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup GPIO_Pin_sources \r
+ * @{\r
+ */ \r
+#define GPIO_PinSource0 ((uint8_t)0x00)\r
+#define GPIO_PinSource1 ((uint8_t)0x01)\r
+#define GPIO_PinSource2 ((uint8_t)0x02)\r
+#define GPIO_PinSource3 ((uint8_t)0x03)\r
+#define GPIO_PinSource4 ((uint8_t)0x04)\r
+#define GPIO_PinSource5 ((uint8_t)0x05)\r
+#define GPIO_PinSource6 ((uint8_t)0x06)\r
+#define GPIO_PinSource7 ((uint8_t)0x07)\r
+#define GPIO_PinSource8 ((uint8_t)0x08)\r
+#define GPIO_PinSource9 ((uint8_t)0x09)\r
+#define GPIO_PinSource10 ((uint8_t)0x0A)\r
+#define GPIO_PinSource11 ((uint8_t)0x0B)\r
+#define GPIO_PinSource12 ((uint8_t)0x0C)\r
+#define GPIO_PinSource13 ((uint8_t)0x0D)\r
+#define GPIO_PinSource14 ((uint8_t)0x0E)\r
+#define GPIO_PinSource15 ((uint8_t)0x0F)\r
+\r
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \\r
+ ((PINSOURCE) == GPIO_PinSource1) || \\r
+ ((PINSOURCE) == GPIO_PinSource2) || \\r
+ ((PINSOURCE) == GPIO_PinSource3) || \\r
+ ((PINSOURCE) == GPIO_PinSource4) || \\r
+ ((PINSOURCE) == GPIO_PinSource5) || \\r
+ ((PINSOURCE) == GPIO_PinSource6) || \\r
+ ((PINSOURCE) == GPIO_PinSource7) || \\r
+ ((PINSOURCE) == GPIO_PinSource8) || \\r
+ ((PINSOURCE) == GPIO_PinSource9) || \\r
+ ((PINSOURCE) == GPIO_PinSource10) || \\r
+ ((PINSOURCE) == GPIO_PinSource11) || \\r
+ ((PINSOURCE) == GPIO_PinSource12) || \\r
+ ((PINSOURCE) == GPIO_PinSource13) || \\r
+ ((PINSOURCE) == GPIO_PinSource14) || \\r
+ ((PINSOURCE) == GPIO_PinSource15))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup GPIO_Alternat_function_selection_define \r
+ * @{\r
+ */ \r
+/** \r
+ * @brief AF 0 selection \r
+ */ \r
+#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */\r
+#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */\r
+#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\r
+#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */\r
+#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 1 selection \r
+ */ \r
+#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 2 selection \r
+ */ \r
+#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */\r
+#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */\r
+#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 3 selection \r
+ */ \r
+#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */\r
+#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */\r
+#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */\r
+#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 4 selection \r
+ */ \r
+#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */\r
+#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */\r
+#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 5 selection \r
+ */ \r
+#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */\r
+#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 6 selection \r
+ */ \r
+#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 7 selection \r
+ */ \r
+#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */\r
+#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */\r
+#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */\r
+#define GPIO_AF_I2S3ext ((uint8_t)0x07) /* I2S3ext Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 8 selection \r
+ */ \r
+#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */\r
+#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */\r
+#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 9 selection \r
+ */ \r
+#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */\r
+#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */\r
+#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */\r
+#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */\r
+#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 10 selection \r
+ */ \r
+#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */\r
+#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 11 selection \r
+ */ \r
+#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 12 selection \r
+ */ \r
+#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */\r
+#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */\r
+#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 13 selection \r
+ */ \r
+#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 15 selection \r
+ */ \r
+#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */\r
+\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \\r
+ ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \\r
+ ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \\r
+ ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \\r
+ ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \\r
+ ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \\r
+ ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \\r
+ ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \\r
+ ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \\r
+ ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \\r
+ ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \\r
+ ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \\r
+ ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \\r
+ ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \\r
+ ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \\r
+ ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \\r
+ ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \\r
+ ((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup GPIO_Legacy \r
+ * @{\r
+ */\r
+ \r
+#define GPIO_Mode_AIN GPIO_Mode_AN\r
+\r
+#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS\r
+#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS\r
+#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+/* Function used to set the GPIO configuration to the default reset state ****/\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+\r
+/* GPIO Read and Write functions **********************************************/\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);\r
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+\r
+/* GPIO Alternate functions configuration function ****************************/\r
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F4xx_GPIO_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_hash.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the HASH \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_HASH_H\r
+#define __STM32F4xx_HASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HASH\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief HASH Init structure definition\r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t HASH_AlgoSelection; /*!< SHA-1 or MD5. This parameter can be a value \r
+ of @ref HASH_Algo_Selection */\r
+ uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value \r
+ of @ref HASH_processor_Algorithm_Mode */\r
+ uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or \r
+ bit-string. This parameter can be a value of\r
+ @ref HASH_Data_Type */\r
+ uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter\r
+ can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */\r
+}HASH_InitTypeDef;\r
+\r
+/** \r
+ * @brief HASH message digest result structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t Data[5]; /*!< Message digest result : 5x 32bit words for SHA1 or \r
+ 4x 32bit words for MD5 */\r
+} HASH_MsgDigest; \r
+\r
+/** \r
+ * @brief HASH context swapping structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t HASH_IMR; \r
+ uint32_t HASH_STR; \r
+ uint32_t HASH_CR; \r
+ uint32_t HASH_CSR[51]; \r
+}HASH_Context;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup HASH_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup HASH_Algo_Selection \r
+ * @{\r
+ */ \r
+#define HASH_AlgoSelection_SHA1 ((uint16_t)0x0000) /*!< HASH function is SHA1 */\r
+#define HASH_AlgoSelection_MD5 ((uint16_t)0x0080) /*!< HASH function is MD5 */\r
+\r
+#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \\r
+ ((ALGOSELECTION) == HASH_AlgoSelection_MD5))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_processor_Algorithm_Mode \r
+ * @{\r
+ */ \r
+#define HASH_AlgoMode_HASH ((uint16_t)0x0000) /*!< Algorithm is HASH */ \r
+#define HASH_AlgoMode_HMAC ((uint16_t)0x0040) /*!< Algorithm is HMAC */\r
+\r
+#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \\r
+ ((ALGOMODE) == HASH_AlgoMode_HMAC))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Data_Type \r
+ * @{\r
+ */ \r
+#define HASH_DataType_32b ((uint16_t)0x0000)\r
+#define HASH_DataType_16b ((uint16_t)0x0010)\r
+#define HASH_DataType_8b ((uint16_t)0x0020)\r
+#define HASH_DataType_1b ((uint16_t)0x0030)\r
+\r
+#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \\r
+ ((DATATYPE) == HASH_DataType_16b)|| \\r
+ ((DATATYPE) == HASH_DataType_8b)|| \\r
+ ((DATATYPE) == HASH_DataType_1b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode \r
+ * @{\r
+ */ \r
+#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */\r
+#define HASH_HMACKeyType_LongKey ((uint32_t)0x00010000) /*!< HMAC Key is > 64 bytes */\r
+\r
+#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \\r
+ ((KEYTYPE) == HASH_HMACKeyType_LongKey))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Number_of_valid_bits_in_last_word_of_the_message \r
+ * @{\r
+ */ \r
+#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_interrupts_definition \r
+ * @{\r
+ */ \r
+#define HASH_IT_DINI ((uint8_t)0x01) /*!< A new block can be entered into the input buffer (DIN)*/\r
+#define HASH_IT_DCI ((uint8_t)0x02) /*!< Digest calculation complete */\r
+\r
+#define IS_HASH_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))\r
+#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_flags_definition \r
+ * @{\r
+ */ \r
+#define HASH_FLAG_DINIS ((uint16_t)0x0001) /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer.*/\r
+#define HASH_FLAG_DCIS ((uint16_t)0x0002) /*!< Digest calculation complete */\r
+#define HASH_FLAG_DMAS ((uint16_t)0x0004) /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */\r
+#define HASH_FLAG_BUSY ((uint16_t)0x0008) /*!< The hash core is Busy : processing a block of data */\r
+#define HASH_FLAG_DINNE ((uint16_t)0x1000) /*!< DIN not empty : The input buffer contains at least one word of data */\r
+\r
+#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \\r
+ ((FLAG) == HASH_FLAG_DCIS) || \\r
+ ((FLAG) == HASH_FLAG_DMAS) || \\r
+ ((FLAG) == HASH_FLAG_BUSY) || \\r
+ ((FLAG) == HASH_FLAG_DINNE)) \r
+\r
+#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \\r
+ ((FLAG) == HASH_FLAG_DCIS)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+ \r
+/* Function used to set the HASH configuration to the default reset state ****/\r
+void HASH_DeInit(void);\r
+\r
+/* HASH Configuration function ************************************************/\r
+void HASH_Init(HASH_InitTypeDef* HASH_InitStruct);\r
+void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct);\r
+void HASH_Reset(void);\r
+\r
+/* HASH Message Digest generation functions ***********************************/\r
+void HASH_DataIn(uint32_t Data);\r
+uint8_t HASH_GetInFIFOWordsNbr(void);\r
+void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber);\r
+void HASH_StartDigest(void);\r
+void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest);\r
+\r
+/* HASH Context swapping functions ********************************************/\r
+void HASH_SaveContext(HASH_Context* HASH_ContextSave);\r
+void HASH_RestoreContext(HASH_Context* HASH_ContextRestore);\r
+\r
+/* HASH's DMA interface function **********************************************/\r
+void HASH_DMACmd(FunctionalState NewState);\r
+\r
+/* HASH Interrupts and flags management functions *****************************/\r
+void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState);\r
+FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG);\r
+void HASH_ClearFlag(uint16_t HASH_FLAG);\r
+ITStatus HASH_GetITStatus(uint8_t HASH_IT);\r
+void HASH_ClearITPendingBit(uint8_t HASH_IT);\r
+\r
+/* High Level SHA1 functions **************************************************/\r
+ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]);\r
+ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen,\r
+ uint8_t *Input, uint32_t Ilen,\r
+ uint8_t Output[20]);\r
+\r
+/* High Level MD5 functions ***************************************************/\r
+ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]);\r
+ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen,\r
+ uint8_t *Input, uint32_t Ilen,\r
+ uint8_t Output[16]);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F4xx_HASH_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_i2c.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the I2C firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_I2C_H\r
+#define __STM32F4xx_I2C_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2C\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief I2C Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.\r
+ This parameter must be set to a value lower than 400kHz */\r
+\r
+ uint16_t I2C_Mode; /*!< Specifies the I2C mode.\r
+ This parameter can be a value of @ref I2C_mode */\r
+\r
+ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.\r
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */\r
+\r
+ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.\r
+ This parameter can be a 7-bit or 10-bit address. */\r
+\r
+ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.\r
+ This parameter can be a value of @ref I2C_acknowledgement */\r
+\r
+ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.\r
+ This parameter can be a value of @ref I2C_acknowledged_address */\r
+}I2C_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+\r
+/** @defgroup I2C_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \\r
+ ((PERIPH) == I2C2) || \\r
+ ((PERIPH) == I2C3))\r
+/** @defgroup I2C_mode \r
+ * @{\r
+ */\r
+\r
+#define I2C_Mode_I2C ((uint16_t)0x0000)\r
+#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) \r
+#define I2C_Mode_SMBusHost ((uint16_t)0x000A)\r
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \\r
+ ((MODE) == I2C_Mode_SMBusDevice) || \\r
+ ((MODE) == I2C_Mode_SMBusHost))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_duty_cycle_in_fast_mode \r
+ * @{\r
+ */\r
+\r
+#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */\r
+#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */\r
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \\r
+ ((CYCLE) == I2C_DutyCycle_2))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_acknowledgement\r
+ * @{\r
+ */\r
+\r
+#define I2C_Ack_Enable ((uint16_t)0x0400)\r
+#define I2C_Ack_Disable ((uint16_t)0x0000)\r
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \\r
+ ((STATE) == I2C_Ack_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_transfer_direction \r
+ * @{\r
+ */\r
+\r
+#define I2C_Direction_Transmitter ((uint8_t)0x00)\r
+#define I2C_Direction_Receiver ((uint8_t)0x01)\r
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \\r
+ ((DIRECTION) == I2C_Direction_Receiver))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_acknowledged_address \r
+ * @{\r
+ */\r
+\r
+#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)\r
+#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)\r
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \\r
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_registers \r
+ * @{\r
+ */\r
+\r
+#define I2C_Register_CR1 ((uint8_t)0x00)\r
+#define I2C_Register_CR2 ((uint8_t)0x04)\r
+#define I2C_Register_OAR1 ((uint8_t)0x08)\r
+#define I2C_Register_OAR2 ((uint8_t)0x0C)\r
+#define I2C_Register_DR ((uint8_t)0x10)\r
+#define I2C_Register_SR1 ((uint8_t)0x14)\r
+#define I2C_Register_SR2 ((uint8_t)0x18)\r
+#define I2C_Register_CCR ((uint8_t)0x1C)\r
+#define I2C_Register_TRISE ((uint8_t)0x20)\r
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \\r
+ ((REGISTER) == I2C_Register_CR2) || \\r
+ ((REGISTER) == I2C_Register_OAR1) || \\r
+ ((REGISTER) == I2C_Register_OAR2) || \\r
+ ((REGISTER) == I2C_Register_DR) || \\r
+ ((REGISTER) == I2C_Register_SR1) || \\r
+ ((REGISTER) == I2C_Register_SR2) || \\r
+ ((REGISTER) == I2C_Register_CCR) || \\r
+ ((REGISTER) == I2C_Register_TRISE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_NACK_position \r
+ * @{\r
+ */\r
+\r
+#define I2C_NACKPosition_Next ((uint16_t)0x0800)\r
+#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)\r
+#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \\r
+ ((POSITION) == I2C_NACKPosition_Current))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_SMBus_alert_pin_level \r
+ * @{\r
+ */\r
+\r
+#define I2C_SMBusAlert_Low ((uint16_t)0x2000)\r
+#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)\r
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \\r
+ ((ALERT) == I2C_SMBusAlert_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_PEC_position \r
+ * @{\r
+ */\r
+\r
+#define I2C_PECPosition_Next ((uint16_t)0x0800)\r
+#define I2C_PECPosition_Current ((uint16_t)0xF7FF)\r
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \\r
+ ((POSITION) == I2C_PECPosition_Current))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_IT_BUF ((uint16_t)0x0400)\r
+#define I2C_IT_EVT ((uint16_t)0x0200)\r
+#define I2C_IT_ERR ((uint16_t)0x0100)\r
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_IT_SMBALERT ((uint32_t)0x01008000)\r
+#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)\r
+#define I2C_IT_PECERR ((uint32_t)0x01001000)\r
+#define I2C_IT_OVR ((uint32_t)0x01000800)\r
+#define I2C_IT_AF ((uint32_t)0x01000400)\r
+#define I2C_IT_ARLO ((uint32_t)0x01000200)\r
+#define I2C_IT_BERR ((uint32_t)0x01000100)\r
+#define I2C_IT_TXE ((uint32_t)0x06000080)\r
+#define I2C_IT_RXNE ((uint32_t)0x06000040)\r
+#define I2C_IT_STOPF ((uint32_t)0x02000010)\r
+#define I2C_IT_ADD10 ((uint32_t)0x02000008)\r
+#define I2C_IT_BTF ((uint32_t)0x02000004)\r
+#define I2C_IT_ADDR ((uint32_t)0x02000002)\r
+#define I2C_IT_SB ((uint32_t)0x02000001)\r
+\r
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))\r
+\r
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \\r
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \\r
+ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \\r
+ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \\r
+ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \\r
+ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \\r
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_flags_definition \r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief SR2 register flags \r
+ */\r
+\r
+#define I2C_FLAG_DUALF ((uint32_t)0x00800000)\r
+#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)\r
+#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)\r
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)\r
+#define I2C_FLAG_TRA ((uint32_t)0x00040000)\r
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)\r
+#define I2C_FLAG_MSL ((uint32_t)0x00010000)\r
+\r
+/** \r
+ * @brief SR1 register flags \r
+ */\r
+\r
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)\r
+#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)\r
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)\r
+#define I2C_FLAG_OVR ((uint32_t)0x10000800)\r
+#define I2C_FLAG_AF ((uint32_t)0x10000400)\r
+#define I2C_FLAG_ARLO ((uint32_t)0x10000200)\r
+#define I2C_FLAG_BERR ((uint32_t)0x10000100)\r
+#define I2C_FLAG_TXE ((uint32_t)0x10000080)\r
+#define I2C_FLAG_RXNE ((uint32_t)0x10000040)\r
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)\r
+#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)\r
+#define I2C_FLAG_BTF ((uint32_t)0x10000004)\r
+#define I2C_FLAG_ADDR ((uint32_t)0x10000002)\r
+#define I2C_FLAG_SB ((uint32_t)0x10000001)\r
+\r
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
+\r
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \\r
+ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \\r
+ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \\r
+ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \\r
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \\r
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \\r
+ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \\r
+ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \\r
+ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \\r
+ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \\r
+ ((FLAG) == I2C_FLAG_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Events \r
+ * @{\r
+ */\r
+\r
+/**\r
+ ===============================================================================\r
+ I2C Master Events (Events grouped in order of communication)\r
+ ===============================================================================\r
+ */\r
+\r
+/** \r
+ * @brief Communication start\r
+ * \r
+ * After sending the START condition (I2C_GenerateSTART() function) the master \r
+ * has to wait for this event. It means that the Start condition has been correctly \r
+ * released on the I2C bus (the bus is free, no other devices is communicating).\r
+ * \r
+ */\r
+/* --EV5 */\r
+#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */\r
+\r
+/** \r
+ * @brief Address Acknowledge\r
+ * \r
+ * After checking on EV5 (start condition correctly released on the bus), the \r
+ * master sends the address of the slave(s) with which it will communicate \r
+ * (I2C_Send7bitAddress() function, it also determines the direction of the communication: \r
+ * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges \r
+ * his address. If an acknowledge is sent on the bus, one of the following events will \r
+ * be set:\r
+ * \r
+ * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED \r
+ * event is set.\r
+ * \r
+ * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED \r
+ * is set\r
+ * \r
+ * 3) In case of 10-Bit addressing mode, the master (just after generating the START \r
+ * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() \r
+ * function). Then master should wait on EV9. It means that the 10-bit addressing \r
+ * header has been correctly sent on the bus. Then master should send the second part of \r
+ * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master \r
+ * should wait for event EV6. \r
+ * \r
+ */\r
+\r
+/* --EV6 */\r
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */\r
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */\r
+/* --EV9 */\r
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */\r
+\r
+/** \r
+ * @brief Communication events\r
+ * \r
+ * If a communication is established (START condition generated and slave address \r
+ * acknowledged) then the master has to check on one of the following events for \r
+ * communication procedures:\r
+ * \r
+ * 1) Master Receiver mode: The master has to wait on the event EV7 then to read \r
+ * the data received from the slave (I2C_ReceiveData() function).\r
+ * \r
+ * 2) Master Transmitter mode: The master has to send data (I2C_SendData() \r
+ * function) then to wait on event EV8 or EV8_2.\r
+ * These two events are similar: \r
+ * - EV8 means that the data has been written in the data register and is \r
+ * being shifted out.\r
+ * - EV8_2 means that the data has been physically shifted out and output \r
+ * on the bus.\r
+ * In most cases, using EV8 is sufficient for the application.\r
+ * Using EV8_2 leads to a slower communication but ensure more reliable test.\r
+ * EV8_2 is also more suitable than EV8 for testing on the last data transmission \r
+ * (before Stop condition generation).\r
+ * \r
+ * @note In case the user software does not guarantee that this event EV7 is \r
+ * managed before the current byte end of transfer, then user may check on EV7 \r
+ * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+ * In this case the communication may be slower.\r
+ * \r
+ */\r
+\r
+/* Master RECEIVER mode -----------------------------*/ \r
+/* --EV7 */\r
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */\r
+\r
+/* Master TRANSMITTER mode --------------------------*/\r
+/* --EV8 */\r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */\r
+/* --EV8_2 */\r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */\r
+\r
+\r
+/**\r
+ ===============================================================================\r
+ I2C Slave Events (Events grouped in order of communication)\r
+ ===============================================================================\r
+ */\r
+\r
+\r
+/** \r
+ * @brief Communication start events\r
+ * \r
+ * Wait on one of these events at the start of the communication. It means that \r
+ * the I2C peripheral detected a Start condition on the bus (generated by master \r
+ * device) followed by the peripheral address. The peripheral generates an ACK \r
+ * condition on the bus (if the acknowledge feature is enabled through function \r
+ * I2C_AcknowledgeConfig()) and the events listed above are set :\r
+ * \r
+ * 1) In normal case (only one address managed by the slave), when the address \r
+ * sent by the master matches the own address of the peripheral (configured by \r
+ * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set \r
+ * (where XXX could be TRANSMITTER or RECEIVER).\r
+ * \r
+ * 2) In case the address sent by the master matches the second address of the \r
+ * peripheral (configured by the function I2C_OwnAddress2Config() and enabled \r
+ * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED \r
+ * (where XXX could be TRANSMITTER or RECEIVER) are set.\r
+ * \r
+ * 3) In case the address sent by the master is General Call (address 0x00) and \r
+ * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) \r
+ * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. \r
+ * \r
+ */\r
+\r
+/* --EV1 (all the events below are variants of EV1) */ \r
+/* 1) Case of One Single Address managed by the slave */\r
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */\r
+\r
+/* 2) Case of Dual address managed by the slave */\r
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */\r
+\r
+/* 3) Case of General Call enabled for the slave */\r
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */\r
+\r
+/** \r
+ * @brief Communication events\r
+ * \r
+ * Wait on one of these events when EV1 has already been checked and: \r
+ * \r
+ * - Slave RECEIVER mode:\r
+ * - EV2: When the application is expecting a data byte to be received. \r
+ * - EV4: When the application is expecting the end of the communication: master \r
+ * sends a stop condition and data transmission is stopped.\r
+ * \r
+ * - Slave Transmitter mode:\r
+ * - EV3: When a byte has been transmitted by the slave and the application is expecting \r
+ * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and\r
+ * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be \r
+ * used when the user software doesn't guarantee the EV3 is managed before the\r
+ * current byte end of transfer.\r
+ * - EV3_2: When the master sends a NACK in order to tell slave that data transmission \r
+ * shall end (before sending the STOP condition). In this case slave has to stop sending \r
+ * data bytes and expect a Stop condition on the bus.\r
+ * \r
+ * @note In case the user software does not guarantee that the event EV2 is \r
+ * managed before the current byte end of transfer, then user may check on EV2 \r
+ * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+ * In this case the communication may be slower.\r
+ *\r
+ */\r
+\r
+/* Slave RECEIVER mode --------------------------*/ \r
+/* --EV2 */\r
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */\r
+/* --EV4 */\r
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */\r
+\r
+/* Slave TRANSMITTER mode -----------------------*/\r
+/* --EV3 */\r
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */\r
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */\r
+/* --EV3_2 */\r
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */\r
+\r
+/*\r
+ ===============================================================================\r
+ End of Events Description\r
+ ===============================================================================\r
+ */\r
+\r
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_own_address1 \r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_clock_speed \r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+/* Function used to set the I2C configuration to the default reset state *****/\r
+void I2C_DeInit(I2C_TypeDef* I2Cx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);\r
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+\r
+/* Data transfers functions ***************************************************/ \r
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);\r
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);\r
+\r
+/* PEC management functions ***************************************************/ \r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+\r
+/* Interrupts, events and flags management functions **************************/\r
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);\r
+\r
+/* \r
+ ===============================================================================\r
+ I2C State Monitoring Functions\r
+ ===============================================================================\r
+ This I2C driver provides three different ways for I2C state monitoring\r
+ depending on the application requirements and constraints:\r
+ \r
+ \r
+ 1. Basic state monitoring (Using I2C_CheckEvent() function)\r
+ -----------------------------------------------------------\r
+ It compares the status registers (SR1 and SR2) content to a given event\r
+ (can be the combination of one or more flags).\r
+ It returns SUCCESS if the current status includes the given flags \r
+ and returns ERROR if one or more flags are missing in the current status.\r
+\r
+ - When to use\r
+ - This function is suitable for most applications as well as for startup \r
+ activity since the events are fully described in the product reference \r
+ manual (RM0090).\r
+ - It is also suitable for users who need to define their own events.\r
+\r
+ - Limitations\r
+ - If an error occurs (ie. error flags are set besides to the monitored \r
+ flags), the I2C_CheckEvent() function may return SUCCESS despite \r
+ the communication hold or corrupted real state. \r
+ In this case, it is advised to use error interrupts to monitor \r
+ the error events and handle them in the interrupt IRQ handler.\r
+ \r
+ Note \r
+ For error management, it is advised to use the following functions:\r
+ - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
+ - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.\r
+ Where x is the peripheral instance (I2C1, I2C2 ...)\r
+ - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the \r
+ I2Cx_ER_IRQHandler() function in order to determine which error occurred.\r
+ - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() \r
+ and/or I2C_GenerateStop() in order to clear the error flag and source \r
+ and return to correct communication status.\r
+ \r
+ \r
+ 2. Advanced state monitoring (Using the function I2C_GetLastEvent())\r
+ -------------------------------------------------------------------- \r
+ Using the function I2C_GetLastEvent() which returns the image of both status \r
+ registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
+ by 16 bits and concatenated to Status Register 1).\r
+\r
+ - When to use\r
+ - This function is suitable for the same applications above but it \r
+ allows to overcome the mentioned limitation of I2C_GetFlagStatus() \r
+ function.\r
+ - The returned value could be compared to events already defined in \r
+ this file or to custom values defined by user.\r
+ This function is suitable when multiple flags are monitored at the \r
+ same time.\r
+ - At the opposite of I2C_CheckEvent() function, this function allows \r
+ user to choose when an event is accepted (when all events flags are \r
+ set and no other flags are set or just when the needed flags are set \r
+ like I2C_CheckEvent() function.\r
+\r
+ - Limitations\r
+ - User may need to define his own events.\r
+ - Same remark concerning the error management is applicable for this \r
+ function if user decides to check only regular communication flags \r
+ (and ignores error flags).\r
+ \r
+ \r
+ 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())\r
+ -----------------------------------------------------------------------\r
+ \r
+ Using the function I2C_GetFlagStatus() which simply returns the status of \r
+ one single flag (ie. I2C_FLAG_RXNE ...). \r
+\r
+ - When to use\r
+ - This function could be used for specific applications or in debug \r
+ phase.\r
+ - It is suitable when only one flag checking is needed (most I2C \r
+ events are monitored through multiple flags).\r
+ - Limitations: \r
+ - When calling this function, the Status register is accessed. \r
+ Some flags are cleared when the status register is accessed. \r
+ So checking the status of one Flag, may clear other ones.\r
+ - Function may need to be called twice or more in order to monitor \r
+ one single event. \r
+ */\r
+\r
+/*\r
+ ===============================================================================\r
+ 1. Basic state monitoring\r
+ ===============================================================================\r
+ */\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);\r
+/*\r
+ ===============================================================================\r
+ 2. Advanced state monitoring\r
+ ===============================================================================\r
+ */\r
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);\r
+/*\r
+ ===============================================================================\r
+ 3. Flag-based state monitoring\r
+ ===============================================================================\r
+ */\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+\r
+\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F4xx_I2C_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_iwdg.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the IWDG \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_IWDG_H\r
+#define __STM32F4xx_IWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup IWDG\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup IWDG_Exported_Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup IWDG_WriteAccess\r
+ * @{\r
+ */\r
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)\r
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)\r
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \\r
+ ((ACCESS) == IWDG_WriteAccess_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_prescaler \r
+ * @{\r
+ */\r
+#define IWDG_Prescaler_4 ((uint8_t)0x00)\r
+#define IWDG_Prescaler_8 ((uint8_t)0x01)\r
+#define IWDG_Prescaler_16 ((uint8_t)0x02)\r
+#define IWDG_Prescaler_32 ((uint8_t)0x03)\r
+#define IWDG_Prescaler_64 ((uint8_t)0x04)\r
+#define IWDG_Prescaler_128 ((uint8_t)0x05)\r
+#define IWDG_Prescaler_256 ((uint8_t)0x06)\r
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \\r
+ ((PRESCALER) == IWDG_Prescaler_8) || \\r
+ ((PRESCALER) == IWDG_Prescaler_16) || \\r
+ ((PRESCALER) == IWDG_Prescaler_32) || \\r
+ ((PRESCALER) == IWDG_Prescaler_64) || \\r
+ ((PRESCALER) == IWDG_Prescaler_128)|| \\r
+ ((PRESCALER) == IWDG_Prescaler_256))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Flag \r
+ * @{\r
+ */\r
+#define IWDG_FLAG_PVU ((uint16_t)0x0001)\r
+#define IWDG_FLAG_RVU ((uint16_t)0x0002)\r
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))\r
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/* Prescaler and Counter configuration functions ******************************/\r
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);\r
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);\r
+void IWDG_SetReload(uint16_t Reload);\r
+void IWDG_ReloadCounter(void);\r
+\r
+/* IWDG activation function ***************************************************/\r
+void IWDG_Enable(void);\r
+\r
+/* Flag management function ***************************************************/\r
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F4xx_IWDG_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_pwr.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the PWR firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_PWR_H\r
+#define __STM32F4xx_PWR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWR\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup PWR_PVD_detection_level \r
+ * @{\r
+ */ \r
+\r
+#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0\r
+#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1\r
+#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2\r
+#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3\r
+#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4\r
+#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5\r
+#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6\r
+#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7\r
+\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \\r
+ ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \\r
+ ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \\r
+ ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup PWR_Regulator_state_in_STOP_mode \r
+ * @{\r
+ */\r
+\r
+#define PWR_Regulator_ON ((uint32_t)0x00000000)\r
+#define PWR_Regulator_LowPower PWR_CR_LPDS\r
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \\r
+ ((REGULATOR) == PWR_Regulator_LowPower))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_STOP_mode_entry \r
+ * @{\r
+ */\r
+\r
+#define PWR_STOPEntry_WFI ((uint8_t)0x01)\r
+#define PWR_STOPEntry_WFE ((uint8_t)0x02)\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))\r
+\r
+/** @defgroup PWR_Regulator_Voltage_Scale \r
+ * @{\r
+ */\r
+\r
+#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x00004000)\r
+#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00000000)\r
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || ((VOLTAGE) == PWR_Regulator_Voltage_Scale2))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Flag \r
+ * @{\r
+ */\r
+\r
+#define PWR_FLAG_WU PWR_CSR_WUF\r
+#define PWR_FLAG_SB PWR_CSR_SBF\r
+#define PWR_FLAG_PVDO PWR_CSR_PVDO\r
+#define PWR_FLAG_BRR PWR_CSR_BRR\r
+#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY\r
+\r
+/** @defgroup PWR_Flag_Legacy \r
+ * @{\r
+ */\r
+#define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY \r
+/**\r
+ * @}\r
+ */\r
+\r
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \\r
+ ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \\r
+ ((FLAG) == PWR_FLAG_VOSRDY))\r
+\r
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+/* Function used to set the PWR configuration to the default reset state ******/ \r
+void PWR_DeInit(void);\r
+\r
+/* Backup Domain Access function **********************************************/ \r
+void PWR_BackupAccessCmd(FunctionalState NewState);\r
+\r
+/* PVD configuration functions ************************************************/ \r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);\r
+void PWR_PVDCmd(FunctionalState NewState);\r
+\r
+/* WakeUp pins configuration functions ****************************************/ \r
+void PWR_WakeUpPinCmd(FunctionalState NewState);\r
+\r
+/* Main and Backup Regulators configuration functions *************************/ \r
+void PWR_BackupRegulatorCmd(FunctionalState NewState);\r
+void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);\r
+\r
+/* FLASH Power Down configuration functions ***********************************/ \r
+void PWR_FlashPowerDownCmd(FunctionalState NewState);\r
+\r
+/* Low Power modes configuration functions ************************************/ \r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);\r
+void PWR_EnterSTANDBYMode(void);\r
+\r
+/* Flags management functions *************************************************/ \r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);\r
+void PWR_ClearFlag(uint32_t PWR_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F4xx_PWR_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_rcc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the RCC firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_RCC_H\r
+#define __STM32F4xx_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */\r
+ uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */\r
+ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */\r
+ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */\r
+}RCC_ClocksTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup RCC_HSE_configuration \r
+ * @{\r
+ */\r
+#define RCC_HSE_OFF ((uint8_t)0x00)\r
+#define RCC_HSE_ON ((uint8_t)0x01)\r
+#define RCC_HSE_Bypass ((uint8_t)0x05)\r
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
+ ((HSE) == RCC_HSE_Bypass))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_PLL_Clock_Source \r
+ * @{\r
+ */\r
+#define RCC_PLLSource_HSI ((uint32_t)0x00000000)\r
+#define RCC_PLLSource_HSE ((uint32_t)0x00400000)\r
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \\r
+ ((SOURCE) == RCC_PLLSource_HSE))\r
+#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)\r
+#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))\r
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))\r
+#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))\r
+ \r
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))\r
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_System_Clock_Source \r
+ * @{\r
+ */\r
+#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)\r
+#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)\r
+#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)\r
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_AHB_Clock_Source\r
+ * @{\r
+ */\r
+#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)\r
+#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)\r
+#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)\r
+#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)\r
+#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)\r
+#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)\r
+#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)\r
+#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)\r
+#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)\r
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \\r
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \\r
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \\r
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \\r
+ ((HCLK) == RCC_SYSCLK_Div512))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_APB1_APB2_Clock_Source\r
+ * @{\r
+ */\r
+#define RCC_HCLK_Div1 ((uint32_t)0x00000000)\r
+#define RCC_HCLK_Div2 ((uint32_t)0x00001000)\r
+#define RCC_HCLK_Div4 ((uint32_t)0x00001400)\r
+#define RCC_HCLK_Div8 ((uint32_t)0x00001800)\r
+#define RCC_HCLK_Div16 ((uint32_t)0x00001C00)\r
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \\r
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \\r
+ ((PCLK) == RCC_HCLK_Div16))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_Interrupt_Source \r
+ * @{\r
+ */\r
+#define RCC_IT_LSIRDY ((uint8_t)0x01)\r
+#define RCC_IT_LSERDY ((uint8_t)0x02)\r
+#define RCC_IT_HSIRDY ((uint8_t)0x04)\r
+#define RCC_IT_HSERDY ((uint8_t)0x08)\r
+#define RCC_IT_PLLRDY ((uint8_t)0x10)\r
+#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)\r
+#define RCC_IT_CSS ((uint8_t)0x80)\r
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))\r
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \\r
+ ((IT) == RCC_IT_PLLI2SRDY))\r
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_LSE_Configuration \r
+ * @{\r
+ */\r
+#define RCC_LSE_OFF ((uint8_t)0x00)\r
+#define RCC_LSE_ON ((uint8_t)0x01)\r
+#define RCC_LSE_Bypass ((uint8_t)0x04)\r
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
+ ((LSE) == RCC_LSE_Bypass))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_RTC_Clock_Source\r
+ * @{\r
+ */\r
+#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)\r
+#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)\r
+#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)\r
+#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)\r
+#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)\r
+#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)\r
+#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)\r
+#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)\r
+#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)\r
+#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)\r
+#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)\r
+#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)\r
+#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)\r
+#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)\r
+#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)\r
+#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)\r
+#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)\r
+#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)\r
+#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)\r
+#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)\r
+#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)\r
+#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)\r
+#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)\r
+#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)\r
+#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)\r
+#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)\r
+#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)\r
+#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)\r
+#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)\r
+#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)\r
+#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)\r
+#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)\r
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_I2S_Clock_Source\r
+ * @{\r
+ */\r
+#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)\r
+#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)\r
+\r
+#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_AHB1_Peripherals \r
+ * @{\r
+ */ \r
+#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)\r
+#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)\r
+#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)\r
+#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)\r
+#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)\r
+#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)\r
+#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)\r
+#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)\r
+#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)\r
+#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)\r
+#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)\r
+#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)\r
+#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)\r
+#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)\r
+#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)\r
+#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)\r
+#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)\r
+#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)\r
+#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)\r
+#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)\r
+#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)\r
+#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)\r
+#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)\r
+#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00))\r
+#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))\r
+#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_AHB2_Peripherals \r
+ * @{\r
+ */ \r
+#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)\r
+#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)\r
+#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)\r
+#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)\r
+#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)\r
+#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_AHB3_Peripherals \r
+ * @{\r
+ */ \r
+#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)\r
+#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_APB1_Peripherals \r
+ * @{\r
+ */ \r
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)\r
+#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)\r
+#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)\r
+#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)\r
+#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)\r
+#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)\r
+#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)\r
+#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)\r
+#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)\r
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)\r
+#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)\r
+#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)\r
+#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)\r
+#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)\r
+#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)\r
+#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)\r
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)\r
+#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)\r
+#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)\r
+#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)\r
+#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)\r
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)\r
+#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)\r
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_APB2_Peripherals \r
+ * @{\r
+ */ \r
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)\r
+#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)\r
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)\r
+#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)\r
+#define RCC_APB2Periph_ADC ((uint32_t)0x00000100)\r
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)\r
+#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)\r
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)\r
+#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)\r
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)\r
+#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)\r
+#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)\r
+#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)\r
+#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)\r
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00))\r
+#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_MCO1_Clock_Source_Prescaler\r
+ * @{\r
+ */\r
+#define RCC_MCO1Source_HSI ((uint32_t)0x00000000)\r
+#define RCC_MCO1Source_LSE ((uint32_t)0x00200000)\r
+#define RCC_MCO1Source_HSE ((uint32_t)0x00400000)\r
+#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)\r
+#define RCC_MCO1Div_1 ((uint32_t)0x00000000)\r
+#define RCC_MCO1Div_2 ((uint32_t)0x04000000)\r
+#define RCC_MCO1Div_3 ((uint32_t)0x05000000)\r
+#define RCC_MCO1Div_4 ((uint32_t)0x06000000)\r
+#define RCC_MCO1Div_5 ((uint32_t)0x07000000)\r
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \\r
+ ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))\r
+ \r
+#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \\r
+ ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \\r
+ ((DIV) == RCC_MCO1Div_5)) \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_MCO2_Clock_Source_Prescaler\r
+ * @{\r
+ */\r
+#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)\r
+#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)\r
+#define RCC_MCO2Source_HSE ((uint32_t)0x80000000)\r
+#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)\r
+#define RCC_MCO2Div_1 ((uint32_t)0x00000000)\r
+#define RCC_MCO2Div_2 ((uint32_t)0x20000000)\r
+#define RCC_MCO2Div_3 ((uint32_t)0x28000000)\r
+#define RCC_MCO2Div_4 ((uint32_t)0x30000000)\r
+#define RCC_MCO2Div_5 ((uint32_t)0x38000000)\r
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \\r
+ ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))\r
+ \r
+#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \\r
+ ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \\r
+ ((DIV) == RCC_MCO2Div_5)) \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_Flag \r
+ * @{\r
+ */\r
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)\r
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)\r
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)\r
+#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)\r
+#define RCC_FLAG_LSERDY ((uint8_t)0x41)\r
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61)\r
+#define RCC_FLAG_BORRST ((uint8_t)0x79)\r
+#define RCC_FLAG_PINRST ((uint8_t)0x7A)\r
+#define RCC_FLAG_PORRST ((uint8_t)0x7B)\r
+#define RCC_FLAG_SFTRST ((uint8_t)0x7C)\r
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)\r
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)\r
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)\r
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \\r
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \\r
+ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \\r
+ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \\r
+ ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \\r
+ ((FLAG) == RCC_FLAG_PLLI2SRDY))\r
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+/* Function used to set the RCC clock configuration to the default reset state */\r
+void RCC_DeInit(void);\r
+\r
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/\r
+void RCC_HSEConfig(uint8_t RCC_HSE);\r
+ErrorStatus RCC_WaitForHSEStartUp(void);\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);\r
+void RCC_HSICmd(FunctionalState NewState);\r
+void RCC_LSEConfig(uint8_t RCC_LSE);\r
+void RCC_LSICmd(FunctionalState NewState);\r
+\r
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);\r
+void RCC_PLLCmd(FunctionalState NewState);\r
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);\r
+void RCC_PLLI2SCmd(FunctionalState NewState);\r
+\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);\r
+void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);\r
+void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);\r
+\r
+/* System, AHB and APB busses clocks configuration functions ******************/\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);\r
+uint8_t RCC_GetSYSCLKSource(void);\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK);\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK);\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);\r
+\r
+/* Peripheral clocks configuration functions **********************************/\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);\r
+void RCC_RTCCLKCmd(FunctionalState NewState);\r
+void RCC_BackupResetCmd(FunctionalState NewState);\r
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); \r
+\r
+void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);\r
+void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);\r
+void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+\r
+void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);\r
+void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);\r
+void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+\r
+void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);\r
+void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);\r
+void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);\r
+void RCC_ClearFlag(void);\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F4xx_RCC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_rng.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the Random \r
+ * Number Generator(RNG) firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_RNG_H\r
+#define __STM32F4xx_RNG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RNG\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/ \r
+\r
+/** @defgroup RNG_Exported_Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup RNG_flags_definition \r
+ * @{\r
+ */ \r
+#define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */\r
+#define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */\r
+#define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */\r
+\r
+#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \\r
+ ((RNG_FLAG) == RNG_FLAG_CECS) || \\r
+ ((RNG_FLAG) == RNG_FLAG_SECS))\r
+#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \\r
+ ((RNG_FLAG) == RNG_FLAG_SECS))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RNG_interrupts_definition \r
+ * @{\r
+ */ \r
+#define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */\r
+#define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */\r
+\r
+#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00))\r
+#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+/* Function used to set the RNG configuration to the default reset state *****/ \r
+void RNG_DeInit(void);\r
+\r
+/* Configuration function *****************************************************/\r
+void RNG_Cmd(FunctionalState NewState);\r
+\r
+/* Get 32 bit Random number function ******************************************/\r
+uint32_t RNG_GetRandomNumber(void);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void RNG_ITConfig(FunctionalState NewState);\r
+FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);\r
+void RNG_ClearFlag(uint8_t RNG_FLAG);\r
+ITStatus RNG_GetITStatus(uint8_t RNG_IT);\r
+void RNG_ClearITPendingBit(uint8_t RNG_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F4xx_RNG_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_rtc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the RTC firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_RTC_H\r
+#define __STM32F4xx_RTC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RTC\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief RTC Init structures definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.\r
+ This parameter can be a value of @ref RTC_Hour_Formats */\r
+ \r
+ uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.\r
+ This parameter must be set to a value lower than 0x7F */\r
+ \r
+ uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.\r
+ This parameter must be set to a value lower than 0x7FFF */\r
+}RTC_InitTypeDef;\r
+\r
+/** \r
+ * @brief RTC Time structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.\r
+ This parameter must be set to a value in the 0-12 range\r
+ if the RTC_HourFormat_12 is selected or 0-23 range if\r
+ the RTC_HourFormat_24 is selected. */\r
+\r
+ uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.\r
+ This parameter must be set to a value in the 0-59 range. */\r
+ \r
+ uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.\r
+ This parameter must be set to a value in the 0-59 range. */\r
+\r
+ uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.\r
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */\r
+}RTC_TimeTypeDef; \r
+\r
+/** \r
+ * @brief RTC Date structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.\r
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */\r
+ \r
+ uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format).\r
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */\r
+\r
+ uint8_t RTC_Date; /*!< Specifies the RTC Date.\r
+ This parameter must be set to a value in the 1-31 range. */\r
+ \r
+ uint8_t RTC_Year; /*!< Specifies the RTC Date Year.\r
+ This parameter must be set to a value in the 0-99 range. */\r
+}RTC_DateTypeDef;\r
+\r
+/** \r
+ * @brief RTC Alarm structure definition \r
+ */\r
+typedef struct\r
+{\r
+ RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */\r
+\r
+ uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.\r
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */\r
+\r
+ uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.\r
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */\r
+ \r
+ uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.\r
+ If the Alarm Date is selected, this parameter\r
+ must be set to a value in the 1-31 range.\r
+ If the Alarm WeekDay is selected, this \r
+ parameter can be a value of @ref RTC_WeekDay_Definitions */\r
+}RTC_AlarmTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup RTC_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Hour_Formats \r
+ * @{\r
+ */ \r
+#define RTC_HourFormat_24 ((uint32_t)0x00000000)\r
+#define RTC_HourFormat_12 ((uint32_t)0x00000040)\r
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \\r
+ ((FORMAT) == RTC_HourFormat_24))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Asynchronous_Predivider \r
+ * @{\r
+ */ \r
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Synchronous_Predivider \r
+ * @{\r
+ */ \r
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Time_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))\r
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)\r
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)\r
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_AM_PM_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_H12_AM ((uint8_t)0x00)\r
+#define RTC_H12_PM ((uint8_t)0x40)\r
+#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Year_Date_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Month_Date_Definitions \r
+ * @{\r
+ */ \r
+\r
+/* Coded in BCD format */\r
+#define RTC_Month_January ((uint8_t)0x01)\r
+#define RTC_Month_February ((uint8_t)0x02)\r
+#define RTC_Month_March ((uint8_t)0x03)\r
+#define RTC_Month_April ((uint8_t)0x04)\r
+#define RTC_Month_May ((uint8_t)0x05)\r
+#define RTC_Month_June ((uint8_t)0x06)\r
+#define RTC_Month_July ((uint8_t)0x07)\r
+#define RTC_Month_August ((uint8_t)0x08)\r
+#define RTC_Month_September ((uint8_t)0x09)\r
+#define RTC_Month_October ((uint8_t)0x10)\r
+#define RTC_Month_November ((uint8_t)0x11)\r
+#define RTC_Month_December ((uint8_t)0x12)\r
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))\r
+#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_WeekDay_Definitions \r
+ * @{\r
+ */ \r
+ \r
+#define RTC_Weekday_Monday ((uint8_t)0x01)\r
+#define RTC_Weekday_Tuesday ((uint8_t)0x02)\r
+#define RTC_Weekday_Wednesday ((uint8_t)0x03)\r
+#define RTC_Weekday_Thursday ((uint8_t)0x04)\r
+#define RTC_Weekday_Friday ((uint8_t)0x05)\r
+#define RTC_Weekday_Saturday ((uint8_t)0x06)\r
+#define RTC_Weekday_Sunday ((uint8_t)0x07)\r
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Friday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Sunday))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Alarm_Definitions\r
+ * @{\r
+ */ \r
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))\r
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Friday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Sunday))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_AlarmDateWeekDay_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)\r
+#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)\r
+\r
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \\r
+ ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_AlarmMask_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_AlarmMask_None ((uint32_t)0x00000000)\r
+#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)\r
+#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)\r
+#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)\r
+#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)\r
+#define RTC_AlarmMask_All ((uint32_t)0x80808080)\r
+#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Alarms_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Alarm_A ((uint32_t)0x00000100)\r
+#define RTC_Alarm_B ((uint32_t)0x00000200)\r
+#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))\r
+#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+ /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions\r
+ * @{\r
+ */ \r
+#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. \r
+ There is no comparison on sub seconds \r
+ for Alarm */\r
+#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm \r
+ comparison. Only SS[0] is compared. */\r
+#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm \r
+ comparison. Only SS[1:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm \r
+ comparison. Only SS[2:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm \r
+ comparison. Only SS[3:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm \r
+ comparison. Only SS[4:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm \r
+ comparison. Only SS[5:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm \r
+ comparison. Only SS[6:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm \r
+ comparison. Only SS[7:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm \r
+ comparison. Only SS[8:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm \r
+ comparison. Only SS[9:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm \r
+ comparison. Only SS[10:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm \r
+ comparison.Only SS[11:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm \r
+ comparison. Only SS[12:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm \r
+ comparison.Only SS[13:0] are compared */\r
+#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match \r
+ to activate alarm. */\r
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_None))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Alarm_Sub_Seconds_Value\r
+ * @{\r
+ */ \r
+\r
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Wakeup_Timer_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)\r
+#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)\r
+#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)\r
+#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)\r
+#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)\r
+#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)\r
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \\r
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \\r
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \\r
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \\r
+ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \\r
+ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))\r
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Time_Stamp_Edges_definitions \r
+ * @{\r
+ */ \r
+#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)\r
+#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)\r
+#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \\r
+ ((EDGE) == RTC_TimeStampEdge_Falling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Output_selection_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Output_Disable ((uint32_t)0x00000000)\r
+#define RTC_Output_AlarmA ((uint32_t)0x00200000)\r
+#define RTC_Output_AlarmB ((uint32_t)0x00400000)\r
+#define RTC_Output_WakeUp ((uint32_t)0x00600000)\r
+ \r
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \\r
+ ((OUTPUT) == RTC_Output_AlarmA) || \\r
+ ((OUTPUT) == RTC_Output_AlarmB) || \\r
+ ((OUTPUT) == RTC_Output_WakeUp))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Output_Polarity_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_OutputPolarity_High ((uint32_t)0x00000000)\r
+#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)\r
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \\r
+ ((POL) == RTC_OutputPolarity_Low))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Digital_Calibration_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_CalibSign_Positive ((uint32_t)0x00000000) \r
+#define RTC_CalibSign_Negative ((uint32_t)0x00000080)\r
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \\r
+ ((SIGN) == RTC_CalibSign_Negative))\r
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+ /** @defgroup RTC_Calib_Output_selection_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) \r
+#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)\r
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \\r
+ ((OUTPUT) == RTC_CalibOutput_1Hz))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Smooth_calib_period_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation\r
+ period is 32s, else 2exp20 RTCCLK seconds */\r
+#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \r
+ period is 16s, else 2exp19 RTCCLK seconds */\r
+#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \r
+ period is 8s, else 2exp18 RTCCLK seconds */\r
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \\r
+ ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \\r
+ ((PERIOD) == RTC_SmoothCalibPeriod_8sec))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added \r
+ during a X -second window = Y - CALM[8:0]. \r
+ with Y = 512, 256, 128 when X = 32, 16, 8 */\r
+#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited\r
+ during a 32-second window = CALM[8:0]. */\r
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \\r
+ ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_DayLightSaving_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)\r
+#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)\r
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \\r
+ ((SAVE) == RTC_DayLightSaving_ADD1H))\r
+\r
+#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)\r
+#define RTC_StoreOperation_Set ((uint32_t)0x00040000)\r
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \\r
+ ((OPERATION) == RTC_StoreOperation_Set))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Tamper_Trigger_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)\r
+#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)\r
+#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)\r
+#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)\r
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \\r
+ ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \\r
+ ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \\r
+ ((TRIGGER) == RTC_TamperTrigger_HighLevel)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Tamper_Filter_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */\r
+\r
+#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 \r
+ consecutive samples at the active level */\r
+#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 \r
+ consecutive samples at the active level */\r
+#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 \r
+ consecutive samples at the active leve. */\r
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \\r
+ ((FILTER) == RTC_TamperFilter_2Sample) || \\r
+ ((FILTER) == RTC_TamperFilter_4Sample) || \\r
+ ((FILTER) == RTC_TamperFilter_8Sample))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 32768 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 16384 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 8192 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 4096 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 2048 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 1024 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 512 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 256 */\r
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before \r
+ sampling during 1 RTCCLK cycle */\r
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before \r
+ sampling during 2 RTCCLK cycles */\r
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before \r
+ sampling during 4 RTCCLK cycles */\r
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before \r
+ sampling during 8 RTCCLK cycles */\r
+\r
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \\r
+ ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \\r
+ ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \\r
+ ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Tamper_Pins_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Tamper_1 RTC_TAFCR_TAMP1E\r
+#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Tamper_Pin_Selection \r
+ * @{\r
+ */ \r
+#define RTC_TamperPin_PC13 ((uint32_t)0x00000000)\r
+#define RTC_TamperPin_PI8 ((uint32_t)0x00010000)\r
+#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \\r
+ ((PIN) == RTC_TamperPin_PI8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_TimeStamp_Pin_Selection \r
+ * @{\r
+ */ \r
+#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000)\r
+#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000)\r
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \\r
+ ((PIN) == RTC_TimeStampPin_PI8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Output_Type_ALARM_OUT \r
+ * @{\r
+ */ \r
+#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)\r
+#define RTC_OutputType_PushPull ((uint32_t)0x00040000)\r
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \\r
+ ((TYPE) == RTC_OutputType_PushPull))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Add_1_Second_Parameter_Definitions\r
+ * @{\r
+ */ \r
+#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)\r
+#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)\r
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \\r
+ ((SEL) == RTC_ShiftAdd1S_Set))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Substract_Fraction_Of_Second_Value\r
+ * @{\r
+ */ \r
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Backup_Registers_Definitions \r
+ * @{\r
+ */\r
+\r
+#define RTC_BKP_DR0 ((uint32_t)0x00000000)\r
+#define RTC_BKP_DR1 ((uint32_t)0x00000001)\r
+#define RTC_BKP_DR2 ((uint32_t)0x00000002)\r
+#define RTC_BKP_DR3 ((uint32_t)0x00000003)\r
+#define RTC_BKP_DR4 ((uint32_t)0x00000004)\r
+#define RTC_BKP_DR5 ((uint32_t)0x00000005)\r
+#define RTC_BKP_DR6 ((uint32_t)0x00000006)\r
+#define RTC_BKP_DR7 ((uint32_t)0x00000007)\r
+#define RTC_BKP_DR8 ((uint32_t)0x00000008)\r
+#define RTC_BKP_DR9 ((uint32_t)0x00000009)\r
+#define RTC_BKP_DR10 ((uint32_t)0x0000000A)\r
+#define RTC_BKP_DR11 ((uint32_t)0x0000000B)\r
+#define RTC_BKP_DR12 ((uint32_t)0x0000000C)\r
+#define RTC_BKP_DR13 ((uint32_t)0x0000000D)\r
+#define RTC_BKP_DR14 ((uint32_t)0x0000000E)\r
+#define RTC_BKP_DR15 ((uint32_t)0x0000000F)\r
+#define RTC_BKP_DR16 ((uint32_t)0x00000010)\r
+#define RTC_BKP_DR17 ((uint32_t)0x00000011)\r
+#define RTC_BKP_DR18 ((uint32_t)0x00000012)\r
+#define RTC_BKP_DR19 ((uint32_t)0x00000013)\r
+#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \\r
+ ((BKP) == RTC_BKP_DR1) || \\r
+ ((BKP) == RTC_BKP_DR2) || \\r
+ ((BKP) == RTC_BKP_DR3) || \\r
+ ((BKP) == RTC_BKP_DR4) || \\r
+ ((BKP) == RTC_BKP_DR5) || \\r
+ ((BKP) == RTC_BKP_DR6) || \\r
+ ((BKP) == RTC_BKP_DR7) || \\r
+ ((BKP) == RTC_BKP_DR8) || \\r
+ ((BKP) == RTC_BKP_DR9) || \\r
+ ((BKP) == RTC_BKP_DR10) || \\r
+ ((BKP) == RTC_BKP_DR11) || \\r
+ ((BKP) == RTC_BKP_DR12) || \\r
+ ((BKP) == RTC_BKP_DR13) || \\r
+ ((BKP) == RTC_BKP_DR14) || \\r
+ ((BKP) == RTC_BKP_DR15) || \\r
+ ((BKP) == RTC_BKP_DR16) || \\r
+ ((BKP) == RTC_BKP_DR17) || \\r
+ ((BKP) == RTC_BKP_DR18) || \\r
+ ((BKP) == RTC_BKP_DR19))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Input_parameter_format_definitions \r
+ * @{\r
+ */ \r
+#define RTC_Format_BIN ((uint32_t)0x000000000)\r
+#define RTC_Format_BCD ((uint32_t)0x000000001)\r
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Flags_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)\r
+#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)\r
+#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)\r
+#define RTC_FLAG_TSF ((uint32_t)0x00000800)\r
+#define RTC_FLAG_WUTF ((uint32_t)0x00000400)\r
+#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)\r
+#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)\r
+#define RTC_FLAG_INITF ((uint32_t)0x00000040)\r
+#define RTC_FLAG_RSF ((uint32_t)0x00000020)\r
+#define RTC_FLAG_INITS ((uint32_t)0x00000010)\r
+#define RTC_FLAG_SHPF ((uint32_t)0x00000008)\r
+#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)\r
+#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)\r
+#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)\r
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \\r
+ ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \\r
+ ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \\r
+ ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \\r
+ ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \\r
+ ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \\r
+ ((FLAG) == RTC_FLAG_SHPF))\r
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Interrupts_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_IT_TS ((uint32_t)0x00008000)\r
+#define RTC_IT_WUT ((uint32_t)0x00004000)\r
+#define RTC_IT_ALRB ((uint32_t)0x00002000)\r
+#define RTC_IT_ALRA ((uint32_t)0x00001000)\r
+#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */\r
+#define RTC_IT_TAMP1 ((uint32_t)0x00020000)\r
+\r
+#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))\r
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \\r
+ ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \\r
+ ((IT) == RTC_IT_TAMP1))\r
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Legacy \r
+ * @{\r
+ */ \r
+#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig\r
+#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+/* Function used to set the RTC configuration to the default reset state *****/\r
+ErrorStatus RTC_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);\r
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);\r
+void RTC_WriteProtectionCmd(FunctionalState NewState);\r
+ErrorStatus RTC_EnterInitMode(void);\r
+void RTC_ExitInitMode(void);\r
+ErrorStatus RTC_WaitForSynchro(void);\r
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState);\r
+void RTC_BypassShadowCmd(FunctionalState NewState);\r
+\r
+/* Time and Date configuration functions **************************************/\r
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);\r
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);\r
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);\r
+uint32_t RTC_GetSubSecond(void);\r
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);\r
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);\r
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);\r
+\r
+/* Alarms (Alarm A and Alarm B) configuration functions **********************/\r
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);\r
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);\r
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);\r
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);\r
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);\r
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);\r
+\r
+/* WakeUp Timer configuration functions ***************************************/\r
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);\r
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);\r
+uint32_t RTC_GetWakeUpCounter(void);\r
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);\r
+\r
+/* Daylight Saving configuration functions ************************************/\r
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);\r
+uint32_t RTC_GetStoreOperation(void);\r
+\r
+/* Output pin Configuration function ******************************************/\r
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);\r
+\r
+/* Digital Calibration configuration functions *********************************/\r
+ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);\r
+ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);\r
+void RTC_CalibOutputCmd(FunctionalState NewState);\r
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);\r
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, \r
+ uint32_t RTC_SmoothCalibPlusPulses,\r
+ uint32_t RTC_SmouthCalibMinusPulsesValue);\r
+\r
+/* TimeStamp configuration functions ******************************************/\r
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);\r
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,\r
+ RTC_DateTypeDef* RTC_StampDateStruct);\r
+uint32_t RTC_GetTimeStampSubSecond(void);\r
+\r
+/* Tampers configuration functions ********************************************/\r
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);\r
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);\r
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);\r
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);\r
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);\r
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);\r
+void RTC_TamperPullUpCmd(FunctionalState NewState);\r
+\r
+/* Backup Data Registers configuration functions ******************************/\r
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);\r
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);\r
+\r
+/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration\r
+ functions ******************************************************************/\r
+void RTC_TamperPinSelection(uint32_t RTC_TamperPin);\r
+void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin);\r
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType);\r
+\r
+/* RTC_Shift_control_synchonisation_functions *********************************/\r
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);\r
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);\r
+void RTC_ClearFlag(uint32_t RTC_FLAG);\r
+ITStatus RTC_GetITStatus(uint32_t RTC_IT);\r
+void RTC_ClearITPendingBit(uint32_t RTC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F4xx_RTC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_sdio.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the SDIO firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_SDIO_H\r
+#define __STM32F4xx_SDIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SDIO\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+typedef struct\r
+{\r
+ uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.\r
+ This parameter can be a value of @ref SDIO_Clock_Edge */\r
+\r
+ uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is\r
+ enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_Clock_Bypass */\r
+\r
+ uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or\r
+ disabled when the bus is idle.\r
+ This parameter can be a value of @ref SDIO_Clock_Power_Save */\r
+\r
+ uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.\r
+ This parameter can be a value of @ref SDIO_Bus_Wide */\r
+\r
+ uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_Hardware_Flow_Control */\r
+\r
+ uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.\r
+ This parameter can be a value between 0x00 and 0xFF. */\r
+ \r
+} SDIO_InitTypeDef;\r
+\r
+typedef struct\r
+{\r
+ uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent\r
+ to a card as part of a command message. If a command\r
+ contains an argument, it must be loaded into this register\r
+ before writing the command to the command register */\r
+\r
+ uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */\r
+\r
+ uint32_t SDIO_Response; /*!< Specifies the SDIO response type.\r
+ This parameter can be a value of @ref SDIO_Response_Type */\r
+\r
+ uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_Wait_Interrupt_State */\r
+\r
+ uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)\r
+ is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_CPSM_State */\r
+} SDIO_CmdInitTypeDef;\r
+\r
+typedef struct\r
+{\r
+ uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */\r
+\r
+ uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */\r
+ \r
+ uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.\r
+ This parameter can be a value of @ref SDIO_Data_Block_Size */\r
+ \r
+ uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer\r
+ is a read or write.\r
+ This parameter can be a value of @ref SDIO_Transfer_Direction */\r
+ \r
+ uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.\r
+ This parameter can be a value of @ref SDIO_Transfer_Type */\r
+ \r
+ uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)\r
+ is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_DPSM_State */\r
+} SDIO_DataInitTypeDef;\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup SDIO_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDIO_Clock_Edge \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)\r
+#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)\r
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \\r
+ ((EDGE) == SDIO_ClockEdge_Falling))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Clock_Bypass \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)\r
+#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) \r
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \\r
+ ((BYPASS) == SDIO_ClockBypass_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Clock_Power_Save \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)\r
+#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) \r
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \\r
+ ((SAVE) == SDIO_ClockPowerSave_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Bus_Wide \r
+ * @{\r
+ */\r
+\r
+#define SDIO_BusWide_1b ((uint32_t)0x00000000)\r
+#define SDIO_BusWide_4b ((uint32_t)0x00000800)\r
+#define SDIO_BusWide_8b ((uint32_t)0x00001000)\r
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \\r
+ ((WIDE) == SDIO_BusWide_8b))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Hardware_Flow_Control \r
+ * @{\r
+ */\r
+\r
+#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)\r
+#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)\r
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \\r
+ ((CONTROL) == SDIO_HardwareFlowControl_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Power_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_PowerState_OFF ((uint32_t)0x00000000)\r
+#define SDIO_PowerState_ON ((uint32_t)0x00000003)\r
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup SDIO_Interrupt_sources\r
+ * @{\r
+ */\r
+\r
+#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)\r
+#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)\r
+#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)\r
+#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)\r
+#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)\r
+#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)\r
+#define SDIO_IT_CMDREND ((uint32_t)0x00000040)\r
+#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)\r
+#define SDIO_IT_DATAEND ((uint32_t)0x00000100)\r
+#define SDIO_IT_STBITERR ((uint32_t)0x00000200)\r
+#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)\r
+#define SDIO_IT_CMDACT ((uint32_t)0x00000800)\r
+#define SDIO_IT_TXACT ((uint32_t)0x00001000)\r
+#define SDIO_IT_RXACT ((uint32_t)0x00002000)\r
+#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)\r
+#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)\r
+#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)\r
+#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)\r
+#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)\r
+#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)\r
+#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)\r
+#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)\r
+#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)\r
+#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)\r
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Command_Index\r
+ * @{\r
+ */\r
+\r
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Response_Type\r
+ * @{\r
+ */\r
+\r
+#define SDIO_Response_No ((uint32_t)0x00000000)\r
+#define SDIO_Response_Short ((uint32_t)0x00000040)\r
+#define SDIO_Response_Long ((uint32_t)0x000000C0)\r
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \\r
+ ((RESPONSE) == SDIO_Response_Short) || \\r
+ ((RESPONSE) == SDIO_Response_Long))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Wait_Interrupt_State\r
+ * @{\r
+ */\r
+\r
+#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */\r
+#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */\r
+#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */\r
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \\r
+ ((WAIT) == SDIO_Wait_Pend))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_CPSM_State\r
+ * @{\r
+ */\r
+\r
+#define SDIO_CPSM_Disable ((uint32_t)0x00000000)\r
+#define SDIO_CPSM_Enable ((uint32_t)0x00000400)\r
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Response_Registers\r
+ * @{\r
+ */\r
+\r
+#define SDIO_RESP1 ((uint32_t)0x00000000)\r
+#define SDIO_RESP2 ((uint32_t)0x00000004)\r
+#define SDIO_RESP3 ((uint32_t)0x00000008)\r
+#define SDIO_RESP4 ((uint32_t)0x0000000C)\r
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \\r
+ ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Data_Length \r
+ * @{\r
+ */\r
+\r
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Data_Block_Size \r
+ * @{\r
+ */\r
+\r
+#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)\r
+#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)\r
+#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)\r
+#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)\r
+#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)\r
+#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)\r
+#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)\r
+#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)\r
+#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)\r
+#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)\r
+#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)\r
+#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)\r
+#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)\r
+#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)\r
+#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)\r
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_2b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_4b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_8b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_16b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_32b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_64b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_128b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_256b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_512b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_1024b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_2048b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_4096b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_8192b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_16384b)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Transfer_Direction \r
+ * @{\r
+ */\r
+\r
+#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)\r
+#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)\r
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \\r
+ ((DIR) == SDIO_TransferDir_ToSDIO))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Transfer_Type \r
+ * @{\r
+ */\r
+\r
+#define SDIO_TransferMode_Block ((uint32_t)0x00000000)\r
+#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)\r
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \\r
+ ((MODE) == SDIO_TransferMode_Block))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_DPSM_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_DPSM_Disable ((uint32_t)0x00000000)\r
+#define SDIO_DPSM_Enable ((uint32_t)0x00000001)\r
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Flags \r
+ * @{\r
+ */\r
+\r
+#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)\r
+#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)\r
+#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)\r
+#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)\r
+#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)\r
+#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)\r
+#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)\r
+#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)\r
+#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)\r
+#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)\r
+#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)\r
+#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)\r
+#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)\r
+#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)\r
+#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)\r
+#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)\r
+#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)\r
+#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)\r
+#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)\r
+#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)\r
+#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)\r
+#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)\r
+#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)\r
+#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)\r
+#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \\r
+ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \\r
+ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \\r
+ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \\r
+ ((FLAG) == SDIO_FLAG_TXUNDERR) || \\r
+ ((FLAG) == SDIO_FLAG_RXOVERR) || \\r
+ ((FLAG) == SDIO_FLAG_CMDREND) || \\r
+ ((FLAG) == SDIO_FLAG_CMDSENT) || \\r
+ ((FLAG) == SDIO_FLAG_DATAEND) || \\r
+ ((FLAG) == SDIO_FLAG_STBITERR) || \\r
+ ((FLAG) == SDIO_FLAG_DBCKEND) || \\r
+ ((FLAG) == SDIO_FLAG_CMDACT) || \\r
+ ((FLAG) == SDIO_FLAG_TXACT) || \\r
+ ((FLAG) == SDIO_FLAG_RXACT) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOF) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOF) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOE) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOE) || \\r
+ ((FLAG) == SDIO_FLAG_TXDAVL) || \\r
+ ((FLAG) == SDIO_FLAG_RXDAVL) || \\r
+ ((FLAG) == SDIO_FLAG_SDIOIT) || \\r
+ ((FLAG) == SDIO_FLAG_CEATAEND))\r
+\r
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))\r
+\r
+#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \\r
+ ((IT) == SDIO_IT_DCRCFAIL) || \\r
+ ((IT) == SDIO_IT_CTIMEOUT) || \\r
+ ((IT) == SDIO_IT_DTIMEOUT) || \\r
+ ((IT) == SDIO_IT_TXUNDERR) || \\r
+ ((IT) == SDIO_IT_RXOVERR) || \\r
+ ((IT) == SDIO_IT_CMDREND) || \\r
+ ((IT) == SDIO_IT_CMDSENT) || \\r
+ ((IT) == SDIO_IT_DATAEND) || \\r
+ ((IT) == SDIO_IT_STBITERR) || \\r
+ ((IT) == SDIO_IT_DBCKEND) || \\r
+ ((IT) == SDIO_IT_CMDACT) || \\r
+ ((IT) == SDIO_IT_TXACT) || \\r
+ ((IT) == SDIO_IT_RXACT) || \\r
+ ((IT) == SDIO_IT_TXFIFOHE) || \\r
+ ((IT) == SDIO_IT_RXFIFOHF) || \\r
+ ((IT) == SDIO_IT_TXFIFOF) || \\r
+ ((IT) == SDIO_IT_RXFIFOF) || \\r
+ ((IT) == SDIO_IT_TXFIFOE) || \\r
+ ((IT) == SDIO_IT_RXFIFOE) || \\r
+ ((IT) == SDIO_IT_TXDAVL) || \\r
+ ((IT) == SDIO_IT_RXDAVL) || \\r
+ ((IT) == SDIO_IT_SDIOIT) || \\r
+ ((IT) == SDIO_IT_CEATAEND))\r
+\r
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Read_Wait_Mode \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)\r
+#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)\r
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \\r
+ ((MODE) == SDIO_ReadWaitMode_DATA2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/* Function used to set the SDIO configuration to the default reset state ****/\r
+void SDIO_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);\r
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);\r
+void SDIO_ClockCmd(FunctionalState NewState);\r
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);\r
+uint32_t SDIO_GetPowerState(void);\r
+\r
+/* Command path state machine (CPSM) management functions *********************/\r
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);\r
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);\r
+uint8_t SDIO_GetCommandResponse(void);\r
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);\r
+\r
+/* Data path state machine (DPSM) management functions ************************/\r
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
+uint32_t SDIO_GetDataCounter(void);\r
+uint32_t SDIO_ReadData(void);\r
+void SDIO_WriteData(uint32_t Data);\r
+uint32_t SDIO_GetFIFOCount(void);\r
+\r
+/* SDIO IO Cards mode management functions ************************************/\r
+void SDIO_StartSDIOReadWait(FunctionalState NewState);\r
+void SDIO_StopSDIOReadWait(FunctionalState NewState);\r
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);\r
+void SDIO_SetSDIOOperation(FunctionalState NewState);\r
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);\r
+\r
+/* CE-ATA mode management functions *******************************************/\r
+void SDIO_CommandCompletionCmd(FunctionalState NewState);\r
+void SDIO_CEATAITCmd(FunctionalState NewState);\r
+void SDIO_SendCEATACmd(FunctionalState NewState);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void SDIO_DMACmd(FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);\r
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);\r
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);\r
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);\r
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F4xx_SDIO_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_spi.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the SPI \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_SPI_H\r
+#define __STM32F4xx_SPI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SPI\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief SPI Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.\r
+ This parameter can be a value of @ref SPI_data_direction */\r
+\r
+ uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.\r
+ This parameter can be a value of @ref SPI_mode */\r
+\r
+ uint16_t SPI_DataSize; /*!< Specifies the SPI data size.\r
+ This parameter can be a value of @ref SPI_data_size */\r
+\r
+ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.\r
+ This parameter can be a value of @ref SPI_Clock_Polarity */\r
+\r
+ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.\r
+ This parameter can be a value of @ref SPI_Clock_Phase */\r
+\r
+ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by\r
+ hardware (NSS pin) or by software using the SSI bit.\r
+ This parameter can be a value of @ref SPI_Slave_Select_management */\r
+ \r
+ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be\r
+ used to configure the transmit and receive SCK clock.\r
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler\r
+ @note The communication clock is derived from the master\r
+ clock. The slave clock does not need to be set. */\r
+\r
+ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.\r
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */\r
+\r
+ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */\r
+}SPI_InitTypeDef;\r
+\r
+/** \r
+ * @brief I2S Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.\r
+ This parameter can be a value of @ref I2S_Mode */\r
+\r
+ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.\r
+ This parameter can be a value of @ref I2S_Standard */\r
+\r
+ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.\r
+ This parameter can be a value of @ref I2S_Data_Format */\r
+\r
+ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.\r
+ This parameter can be a value of @ref I2S_MCLK_Output */\r
+\r
+ uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.\r
+ This parameter can be a value of @ref I2S_Audio_Frequency */\r
+\r
+ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.\r
+ This parameter can be a value of @ref I2S_Clock_Polarity */\r
+}I2S_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup SPI_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \\r
+ ((PERIPH) == SPI2) || \\r
+ ((PERIPH) == SPI3))\r
+\r
+#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \\r
+ ((PERIPH) == SPI2) || \\r
+ ((PERIPH) == SPI3) || \\r
+ ((PERIPH) == I2S2ext) || \\r
+ ((PERIPH) == I2S3ext))\r
+\r
+#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \\r
+ ((PERIPH) == SPI3))\r
+\r
+#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \\r
+ ((PERIPH) == SPI3) || \\r
+ ((PERIPH) == I2S2ext) || \\r
+ ((PERIPH) == I2S3ext))\r
+\r
+#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \\r
+ ((PERIPH) == I2S3ext))\r
+\r
+\r
+/** @defgroup SPI_data_direction \r
+ * @{\r
+ */\r
+ \r
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)\r
+#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)\r
+#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)\r
+#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)\r
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \\r
+ ((MODE) == SPI_Direction_2Lines_RxOnly) || \\r
+ ((MODE) == SPI_Direction_1Line_Rx) || \\r
+ ((MODE) == SPI_Direction_1Line_Tx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_mode \r
+ * @{\r
+ */\r
+\r
+#define SPI_Mode_Master ((uint16_t)0x0104)\r
+#define SPI_Mode_Slave ((uint16_t)0x0000)\r
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \\r
+ ((MODE) == SPI_Mode_Slave))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_data_size \r
+ * @{\r
+ */\r
+\r
+#define SPI_DataSize_16b ((uint16_t)0x0800)\r
+#define SPI_DataSize_8b ((uint16_t)0x0000)\r
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \\r
+ ((DATASIZE) == SPI_DataSize_8b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_Clock_Polarity \r
+ * @{\r
+ */\r
+\r
+#define SPI_CPOL_Low ((uint16_t)0x0000)\r
+#define SPI_CPOL_High ((uint16_t)0x0002)\r
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \\r
+ ((CPOL) == SPI_CPOL_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Clock_Phase \r
+ * @{\r
+ */\r
+\r
+#define SPI_CPHA_1Edge ((uint16_t)0x0000)\r
+#define SPI_CPHA_2Edge ((uint16_t)0x0001)\r
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \\r
+ ((CPHA) == SPI_CPHA_2Edge))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Slave_Select_management \r
+ * @{\r
+ */\r
+\r
+#define SPI_NSS_Soft ((uint16_t)0x0200)\r
+#define SPI_NSS_Hard ((uint16_t)0x0000)\r
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \\r
+ ((NSS) == SPI_NSS_Hard))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_BaudRate_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)\r
+#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)\r
+#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)\r
+#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)\r
+#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)\r
+#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)\r
+#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)\r
+#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)\r
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_256))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_MSB_LSB_transmission \r
+ * @{\r
+ */\r
+\r
+#define SPI_FirstBit_MSB ((uint16_t)0x0000)\r
+#define SPI_FirstBit_LSB ((uint16_t)0x0080)\r
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \\r
+ ((BIT) == SPI_FirstBit_LSB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_Mode \r
+ * @{\r
+ */\r
+\r
+#define I2S_Mode_SlaveTx ((uint16_t)0x0000)\r
+#define I2S_Mode_SlaveRx ((uint16_t)0x0100)\r
+#define I2S_Mode_MasterTx ((uint16_t)0x0200)\r
+#define I2S_Mode_MasterRx ((uint16_t)0x0300)\r
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \\r
+ ((MODE) == I2S_Mode_SlaveRx) || \\r
+ ((MODE) == I2S_Mode_MasterTx)|| \\r
+ ((MODE) == I2S_Mode_MasterRx))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+/** @defgroup SPI_I2S_Standard \r
+ * @{\r
+ */\r
+\r
+#define I2S_Standard_Phillips ((uint16_t)0x0000)\r
+#define I2S_Standard_MSB ((uint16_t)0x0010)\r
+#define I2S_Standard_LSB ((uint16_t)0x0020)\r
+#define I2S_Standard_PCMShort ((uint16_t)0x0030)\r
+#define I2S_Standard_PCMLong ((uint16_t)0x00B0)\r
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \\r
+ ((STANDARD) == I2S_Standard_MSB) || \\r
+ ((STANDARD) == I2S_Standard_LSB) || \\r
+ ((STANDARD) == I2S_Standard_PCMShort) || \\r
+ ((STANDARD) == I2S_Standard_PCMLong))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SPI_I2S_Data_Format \r
+ * @{\r
+ */\r
+\r
+#define I2S_DataFormat_16b ((uint16_t)0x0000)\r
+#define I2S_DataFormat_16bextended ((uint16_t)0x0001)\r
+#define I2S_DataFormat_24b ((uint16_t)0x0003)\r
+#define I2S_DataFormat_32b ((uint16_t)0x0005)\r
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \\r
+ ((FORMAT) == I2S_DataFormat_16bextended) || \\r
+ ((FORMAT) == I2S_DataFormat_24b) || \\r
+ ((FORMAT) == I2S_DataFormat_32b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_MCLK_Output \r
+ * @{\r
+ */\r
+\r
+#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)\r
+#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)\r
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \\r
+ ((OUTPUT) == I2S_MCLKOutput_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_Audio_Frequency \r
+ * @{\r
+ */\r
+\r
+#define I2S_AudioFreq_192k ((uint32_t)192000)\r
+#define I2S_AudioFreq_96k ((uint32_t)96000)\r
+#define I2S_AudioFreq_48k ((uint32_t)48000)\r
+#define I2S_AudioFreq_44k ((uint32_t)44100)\r
+#define I2S_AudioFreq_32k ((uint32_t)32000)\r
+#define I2S_AudioFreq_22k ((uint32_t)22050)\r
+#define I2S_AudioFreq_16k ((uint32_t)16000)\r
+#define I2S_AudioFreq_11k ((uint32_t)11025)\r
+#define I2S_AudioFreq_8k ((uint32_t)8000)\r
+#define I2S_AudioFreq_Default ((uint32_t)2)\r
+\r
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \\r
+ ((FREQ) <= I2S_AudioFreq_192k)) || \\r
+ ((FREQ) == I2S_AudioFreq_Default))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SPI_I2S_Clock_Polarity \r
+ * @{\r
+ */\r
+\r
+#define I2S_CPOL_Low ((uint16_t)0x0000)\r
+#define I2S_CPOL_High ((uint16_t)0x0008)\r
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \\r
+ ((CPOL) == I2S_CPOL_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_DMA_transfer_requests \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)\r
+#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)\r
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_NSS_internal_software_management \r
+ * @{\r
+ */\r
+\r
+#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)\r
+#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)\r
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \\r
+ ((INTERNAL) == SPI_NSSInternalSoft_Reset))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_Transmit_Receive \r
+ * @{\r
+ */\r
+\r
+#define SPI_CRC_Tx ((uint8_t)0x00)\r
+#define SPI_CRC_Rx ((uint8_t)0x01)\r
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_direction_transmit_receive \r
+ * @{\r
+ */\r
+\r
+#define SPI_Direction_Rx ((uint16_t)0xBFFF)\r
+#define SPI_Direction_Tx ((uint16_t)0x4000)\r
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \\r
+ ((DIRECTION) == SPI_Direction_Tx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_IT_TXE ((uint8_t)0x71)\r
+#define SPI_I2S_IT_RXNE ((uint8_t)0x60)\r
+#define SPI_I2S_IT_ERR ((uint8_t)0x50)\r
+#define I2S_IT_UDR ((uint8_t)0x53)\r
+#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58)\r
+\r
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == SPI_I2S_IT_RXNE) || \\r
+ ((IT) == SPI_I2S_IT_ERR))\r
+\r
+#define SPI_I2S_IT_OVR ((uint8_t)0x56)\r
+#define SPI_IT_MODF ((uint8_t)0x55)\r
+#define SPI_IT_CRCERR ((uint8_t)0x54)\r
+\r
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))\r
+\r
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \\r
+ ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\\r
+ ((IT) == SPI_I2S_IT_TIFRFE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_flags_definition \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)\r
+#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)\r
+#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)\r
+#define I2S_FLAG_UDR ((uint16_t)0x0008)\r
+#define SPI_FLAG_CRCERR ((uint16_t)0x0010)\r
+#define SPI_FLAG_MODF ((uint16_t)0x0020)\r
+#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)\r
+#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)\r
+#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100)\r
+\r
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))\r
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \\r
+ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \\r
+ ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \\r
+ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \\r
+ ((FLAG) == SPI_I2S_FLAG_TIFRFE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_polynomial \r
+ * @{\r
+ */\r
+\r
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_Legacy \r
+ * @{\r
+ */\r
+\r
+#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx\r
+#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx\r
+#define SPI_IT_TXE SPI_I2S_IT_TXE\r
+#define SPI_IT_RXNE SPI_I2S_IT_RXNE\r
+#define SPI_IT_ERR SPI_I2S_IT_ERR\r
+#define SPI_IT_OVR SPI_I2S_IT_OVR\r
+#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE\r
+#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE\r
+#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR\r
+#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY\r
+#define SPI_DeInit SPI_I2S_DeInit\r
+#define SPI_ITConfig SPI_I2S_ITConfig\r
+#define SPI_DMACmd SPI_I2S_DMACmd\r
+#define SPI_SendData SPI_I2S_SendData\r
+#define SPI_ReceiveData SPI_I2S_ReceiveData\r
+#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus\r
+#define SPI_ClearFlag SPI_I2S_ClearFlag\r
+#define SPI_GetITStatus SPI_I2S_GetITStatus\r
+#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+/* Function used to set the SPI configuration to the default reset state *****/ \r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);\r
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);\r
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+\r
+void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);\r
+\r
+/* Data transfers functions ***************************************************/ \r
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);\r
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);\r
+\r
+/* Hardware CRC Calculation functions *****************************************/\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F4xx_SPI_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_syscfg.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the SYSCFG firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_SYSCFG_H\r
+#define __STM32F4xx_SYSCFG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SYSCFG\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+ \r
+/** @defgroup SYSCFG_Exported_Constants \r
+ * @{\r
+ */ \r
+\r
+/** @defgroup SYSCFG_EXTI_Port_Sources \r
+ * @{\r
+ */ \r
+#define EXTI_PortSourceGPIOA ((uint8_t)0x00)\r
+#define EXTI_PortSourceGPIOB ((uint8_t)0x01)\r
+#define EXTI_PortSourceGPIOC ((uint8_t)0x02)\r
+#define EXTI_PortSourceGPIOD ((uint8_t)0x03)\r
+#define EXTI_PortSourceGPIOE ((uint8_t)0x04)\r
+#define EXTI_PortSourceGPIOF ((uint8_t)0x05)\r
+#define EXTI_PortSourceGPIOG ((uint8_t)0x06)\r
+#define EXTI_PortSourceGPIOH ((uint8_t)0x07)\r
+#define EXTI_PortSourceGPIOI ((uint8_t)0x08)\r
+ \r
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOI)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup SYSCFG_EXTI_Pin_Sources \r
+ * @{\r
+ */ \r
+#define EXTI_PinSource0 ((uint8_t)0x00)\r
+#define EXTI_PinSource1 ((uint8_t)0x01)\r
+#define EXTI_PinSource2 ((uint8_t)0x02)\r
+#define EXTI_PinSource3 ((uint8_t)0x03)\r
+#define EXTI_PinSource4 ((uint8_t)0x04)\r
+#define EXTI_PinSource5 ((uint8_t)0x05)\r
+#define EXTI_PinSource6 ((uint8_t)0x06)\r
+#define EXTI_PinSource7 ((uint8_t)0x07)\r
+#define EXTI_PinSource8 ((uint8_t)0x08)\r
+#define EXTI_PinSource9 ((uint8_t)0x09)\r
+#define EXTI_PinSource10 ((uint8_t)0x0A)\r
+#define EXTI_PinSource11 ((uint8_t)0x0B)\r
+#define EXTI_PinSource12 ((uint8_t)0x0C)\r
+#define EXTI_PinSource13 ((uint8_t)0x0D)\r
+#define EXTI_PinSource14 ((uint8_t)0x0E)\r
+#define EXTI_PinSource15 ((uint8_t)0x0F)\r
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \\r
+ ((PINSOURCE) == EXTI_PinSource1) || \\r
+ ((PINSOURCE) == EXTI_PinSource2) || \\r
+ ((PINSOURCE) == EXTI_PinSource3) || \\r
+ ((PINSOURCE) == EXTI_PinSource4) || \\r
+ ((PINSOURCE) == EXTI_PinSource5) || \\r
+ ((PINSOURCE) == EXTI_PinSource6) || \\r
+ ((PINSOURCE) == EXTI_PinSource7) || \\r
+ ((PINSOURCE) == EXTI_PinSource8) || \\r
+ ((PINSOURCE) == EXTI_PinSource9) || \\r
+ ((PINSOURCE) == EXTI_PinSource10) || \\r
+ ((PINSOURCE) == EXTI_PinSource11) || \\r
+ ((PINSOURCE) == EXTI_PinSource12) || \\r
+ ((PINSOURCE) == EXTI_PinSource13) || \\r
+ ((PINSOURCE) == EXTI_PinSource14) || \\r
+ ((PINSOURCE) == EXTI_PinSource15))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup SYSCFG_Memory_Remap_Config \r
+ * @{\r
+ */ \r
+#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)\r
+#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)\r
+#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)\r
+#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)\r
+ \r
+#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \\r
+ ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \\r
+ ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \\r
+ ((REMAP) == SYSCFG_MemoryRemap_FSMC))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup SYSCFG_ETHERNET_Media_Interface \r
+ * @{\r
+ */ \r
+#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) \r
+#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) \r
+\r
+#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \\r
+ ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+ \r
+void SYSCFG_DeInit(void);\r
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);\r
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);\r
+void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); \r
+void SYSCFG_CompensationCellCmd(FunctionalState NewState); \r
+FlagStatus SYSCFG_GetCompensationCellStatus(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F4xx_SYSCFG_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_tim.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the TIM firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_TIM_H\r
+#define __STM32F4xx_TIM_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief TIM Time Base Init structure definition \r
+ * @note This structure is used with all TIMx except for TIM6 and TIM7. \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
+ This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.\r
+ This parameter can be a value of @ref TIM_Counter_Mode */\r
+\r
+ uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active\r
+ Auto-Reload Register at the next update event.\r
+ This parameter must be a number between 0x0000 and 0xFFFF. */ \r
+\r
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.\r
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */\r
+\r
+ uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter\r
+ reaches zero, an update event is generated and counting restarts\r
+ from the RCR value (N).\r
+ This means in PWM mode that (N+1) corresponds to:\r
+ - the number of PWM periods in edge-aligned mode\r
+ - the number of half PWM period in center-aligned mode\r
+ This parameter must be a number between 0x00 and 0xFF. \r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+} TIM_TimeBaseInitTypeDef; \r
+\r
+/** \r
+ * @brief TIM Output Compare Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_State */\r
+\r
+ uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_State\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
+ This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+ uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+} TIM_OCInitTypeDef;\r
+\r
+/** \r
+ * @brief TIM Input Capture Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.\r
+ This parameter can be a value of @ref TIM_Channel */\r
+\r
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint16_t TIM_ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between 0x0 and 0xF */\r
+} TIM_ICInitTypeDef;\r
+\r
+/** \r
+ * @brief BDTR structure definition \r
+ * @note This structure is used only with TIM1 and TIM8. \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.\r
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */\r
+\r
+ uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.\r
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */\r
+\r
+ uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.\r
+ This parameter can be a value of @ref TIM_Lock_level */ \r
+\r
+ uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the\r
+ switching-on of the outputs.\r
+ This parameter can be a number between 0x00 and 0xFF */\r
+\r
+ uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. \r
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */\r
+\r
+ uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.\r
+ This parameter can be a value of @ref TIM_Break_Polarity */\r
+\r
+ uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. \r
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */\r
+} TIM_BDTRInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup TIM_Exported_constants \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10) || \\r
+ ((PERIPH) == TIM11) || \\r
+ ((PERIPH) == TIM12) || \\r
+ (((PERIPH) == TIM13) || \\r
+ ((PERIPH) == TIM14)))\r
+/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ \r
+#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10) || \\r
+ ((PERIPH) == TIM11) || \\r
+ ((PERIPH) == TIM12) || \\r
+ ((PERIPH) == TIM13) || \\r
+ ((PERIPH) == TIM14))\r
+ \r
+/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */\r
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM12))\r
+/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */\r
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8))\r
+/* LIST4: TIM1 and TIM8 */\r
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM8))\r
+/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */\r
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) || \\r
+ ((PERIPH) == TIM8))\r
+/* LIST6: TIM2, TIM5 and TIM11 */ \r
+#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \\r
+ ((TIMx) == TIM5) || \\r
+ ((TIMx) == TIM11))\r
+\r
+/** @defgroup TIM_Output_Compare_and_PWM_modes \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCMode_Timing ((uint16_t)0x0000)\r
+#define TIM_OCMode_Active ((uint16_t)0x0010)\r
+#define TIM_OCMode_Inactive ((uint16_t)0x0020)\r
+#define TIM_OCMode_Toggle ((uint16_t)0x0030)\r
+#define TIM_OCMode_PWM1 ((uint16_t)0x0060)\r
+#define TIM_OCMode_PWM2 ((uint16_t)0x0070)\r
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2))\r
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2) || \\r
+ ((MODE) == TIM_ForcedAction_Active) || \\r
+ ((MODE) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_One_Pulse_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_OPMode_Single ((uint16_t)0x0008)\r
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)\r
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \\r
+ ((MODE) == TIM_OPMode_Repetitive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Channel \r
+ * @{\r
+ */\r
+\r
+#define TIM_Channel_1 ((uint16_t)0x0000)\r
+#define TIM_Channel_2 ((uint16_t)0x0004)\r
+#define TIM_Channel_3 ((uint16_t)0x0008)\r
+#define TIM_Channel_4 ((uint16_t)0x000C)\r
+ \r
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2) || \\r
+ ((CHANNEL) == TIM_Channel_3) || \\r
+ ((CHANNEL) == TIM_Channel_4))\r
+ \r
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2))\r
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2) || \\r
+ ((CHANNEL) == TIM_Channel_3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Clock_Division_CKD \r
+ * @{\r
+ */\r
+\r
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)\r
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)\r
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)\r
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \\r
+ ((DIV) == TIM_CKD_DIV2) || \\r
+ ((DIV) == TIM_CKD_DIV4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Counter_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_CounterMode_Up ((uint16_t)0x0000)\r
+#define TIM_CounterMode_Down ((uint16_t)0x0010)\r
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)\r
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)\r
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)\r
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \\r
+ ((MODE) == TIM_CounterMode_Down) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPolarity_High ((uint16_t)0x0000)\r
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)\r
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \\r
+ ((POLARITY) == TIM_OCPolarity_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_N_Polarity \r
+ * @{\r
+ */\r
+ \r
+#define TIM_OCNPolarity_High ((uint16_t)0x0000)\r
+#define TIM_OCNPolarity_Low ((uint16_t)0x0008)\r
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \\r
+ ((POLARITY) == TIM_OCNPolarity_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OutputState_Disable ((uint16_t)0x0000)\r
+#define TIM_OutputState_Enable ((uint16_t)0x0001)\r
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \\r
+ ((STATE) == TIM_OutputState_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_N_State\r
+ * @{\r
+ */\r
+\r
+#define TIM_OutputNState_Disable ((uint16_t)0x0000)\r
+#define TIM_OutputNState_Enable ((uint16_t)0x0004)\r
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \\r
+ ((STATE) == TIM_OutputNState_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Capture_Compare_State\r
+ * @{\r
+ */\r
+\r
+#define TIM_CCx_Enable ((uint16_t)0x0001)\r
+#define TIM_CCx_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \\r
+ ((CCX) == TIM_CCx_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Capture_Compare_N_State\r
+ * @{\r
+ */\r
+\r
+#define TIM_CCxN_Enable ((uint16_t)0x0004)\r
+#define TIM_CCxN_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \\r
+ ((CCXN) == TIM_CCxN_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Break_Input_enable_disable \r
+ * @{\r
+ */\r
+\r
+#define TIM_Break_Enable ((uint16_t)0x1000)\r
+#define TIM_Break_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \\r
+ ((STATE) == TIM_Break_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Break_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_BreakPolarity_Low ((uint16_t)0x0000)\r
+#define TIM_BreakPolarity_High ((uint16_t)0x2000)\r
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \\r
+ ((POLARITY) == TIM_BreakPolarity_High))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_AOE_Bit_Set_Reset \r
+ * @{\r
+ */\r
+\r
+#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)\r
+#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \\r
+ ((STATE) == TIM_AutomaticOutput_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Lock_level\r
+ * @{\r
+ */\r
+\r
+#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)\r
+#define TIM_LOCKLevel_1 ((uint16_t)0x0100)\r
+#define TIM_LOCKLevel_2 ((uint16_t)0x0200)\r
+#define TIM_LOCKLevel_3 ((uint16_t)0x0300)\r
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \\r
+ ((LEVEL) == TIM_LOCKLevel_1) || \\r
+ ((LEVEL) == TIM_LOCKLevel_2) || \\r
+ ((LEVEL) == TIM_LOCKLevel_3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OSSIState_Enable ((uint16_t)0x0400)\r
+#define TIM_OSSIState_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \\r
+ ((STATE) == TIM_OSSIState_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state\r
+ * @{\r
+ */\r
+\r
+#define TIM_OSSRState_Enable ((uint16_t)0x0800)\r
+#define TIM_OSSRState_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \\r
+ ((STATE) == TIM_OSSRState_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Idle_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCIdleState_Set ((uint16_t)0x0100)\r
+#define TIM_OCIdleState_Reset ((uint16_t)0x0000)\r
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \\r
+ ((STATE) == TIM_OCIdleState_Reset))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_N_Idle_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCNIdleState_Set ((uint16_t)0x0200)\r
+#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)\r
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \\r
+ ((STATE) == TIM_OCNIdleState_Reset))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)\r
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)\r
+#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)\r
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
+ ((POLARITY) == TIM_ICPolarity_Falling)|| \\r
+ ((POLARITY) == TIM_ICPolarity_BothEdge))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \r
+ connected to IC1, IC2, IC3 or IC4, respectively */\r
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+ connected to IC2, IC1, IC4 or IC3, respectively. */\r
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */\r
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_TRC))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */\r
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */\r
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */\r
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */\r
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_interrupt_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_IT_Update ((uint16_t)0x0001)\r
+#define TIM_IT_CC1 ((uint16_t)0x0002)\r
+#define TIM_IT_CC2 ((uint16_t)0x0004)\r
+#define TIM_IT_CC3 ((uint16_t)0x0008)\r
+#define TIM_IT_CC4 ((uint16_t)0x0010)\r
+#define TIM_IT_COM ((uint16_t)0x0020)\r
+#define TIM_IT_Trigger ((uint16_t)0x0040)\r
+#define TIM_IT_Break ((uint16_t)0x0080)\r
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))\r
+\r
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \\r
+ ((IT) == TIM_IT_CC1) || \\r
+ ((IT) == TIM_IT_CC2) || \\r
+ ((IT) == TIM_IT_CC3) || \\r
+ ((IT) == TIM_IT_CC4) || \\r
+ ((IT) == TIM_IT_COM) || \\r
+ ((IT) == TIM_IT_Trigger) || \\r
+ ((IT) == TIM_IT_Break))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Base_address \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)\r
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)\r
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)\r
+#define TIM_DMABase_DIER ((uint16_t)0x0003)\r
+#define TIM_DMABase_SR ((uint16_t)0x0004)\r
+#define TIM_DMABase_EGR ((uint16_t)0x0005)\r
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)\r
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)\r
+#define TIM_DMABase_CCER ((uint16_t)0x0008)\r
+#define TIM_DMABase_CNT ((uint16_t)0x0009)\r
+#define TIM_DMABase_PSC ((uint16_t)0x000A)\r
+#define TIM_DMABase_ARR ((uint16_t)0x000B)\r
+#define TIM_DMABase_RCR ((uint16_t)0x000C)\r
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)\r
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)\r
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)\r
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)\r
+#define TIM_DMABase_BDTR ((uint16_t)0x0011)\r
+#define TIM_DMABase_DCR ((uint16_t)0x0012)\r
+#define TIM_DMABase_OR ((uint16_t)0x0013)\r
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \\r
+ ((BASE) == TIM_DMABase_CR2) || \\r
+ ((BASE) == TIM_DMABase_SMCR) || \\r
+ ((BASE) == TIM_DMABase_DIER) || \\r
+ ((BASE) == TIM_DMABase_SR) || \\r
+ ((BASE) == TIM_DMABase_EGR) || \\r
+ ((BASE) == TIM_DMABase_CCMR1) || \\r
+ ((BASE) == TIM_DMABase_CCMR2) || \\r
+ ((BASE) == TIM_DMABase_CCER) || \\r
+ ((BASE) == TIM_DMABase_CNT) || \\r
+ ((BASE) == TIM_DMABase_PSC) || \\r
+ ((BASE) == TIM_DMABase_ARR) || \\r
+ ((BASE) == TIM_DMABase_RCR) || \\r
+ ((BASE) == TIM_DMABase_CCR1) || \\r
+ ((BASE) == TIM_DMABase_CCR2) || \\r
+ ((BASE) == TIM_DMABase_CCR3) || \\r
+ ((BASE) == TIM_DMABase_CCR4) || \\r
+ ((BASE) == TIM_DMABase_BDTR) || \\r
+ ((BASE) == TIM_DMABase_DCR) || \\r
+ ((BASE) == TIM_DMABase_OR)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Burst_Length \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)\r
+#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)\r
+#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)\r
+#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)\r
+#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)\r
+#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)\r
+#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)\r
+#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)\r
+#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)\r
+#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)\r
+#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)\r
+#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)\r
+#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)\r
+#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)\r
+#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)\r
+#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)\r
+#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)\r
+#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)\r
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \\r
+ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_18Transfers))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMA_Update ((uint16_t)0x0100)\r
+#define TIM_DMA_CC1 ((uint16_t)0x0200)\r
+#define TIM_DMA_CC2 ((uint16_t)0x0400)\r
+#define TIM_DMA_CC3 ((uint16_t)0x0800)\r
+#define TIM_DMA_CC4 ((uint16_t)0x1000)\r
+#define TIM_DMA_COM ((uint16_t)0x2000)\r
+#define TIM_DMA_Trigger ((uint16_t)0x4000)\r
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)\r
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)\r
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)\r
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)\r
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Internal_Trigger_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_TS_ITR0 ((uint16_t)0x0000)\r
+#define TIM_TS_ITR1 ((uint16_t)0x0010)\r
+#define TIM_TS_ITR2 ((uint16_t)0x0020)\r
+#define TIM_TS_ITR3 ((uint16_t)0x0030)\r
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)\r
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)\r
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)\r
+#define TIM_TS_ETRF ((uint16_t)0x0070)\r
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3) || \\r
+ ((SELECTION) == TIM_TS_TI1F_ED) || \\r
+ ((SELECTION) == TIM_TS_TI1FP1) || \\r
+ ((SELECTION) == TIM_TS_TI2FP2) || \\r
+ ((SELECTION) == TIM_TS_ETRF))\r
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_TIx_External_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)\r
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)\r
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Polarity \r
+ * @{\r
+ */ \r
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)\r
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)\r
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \\r
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Prescaler_Reload_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)\r
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)\r
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \\r
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Forced_Action \r
+ * @{\r
+ */\r
+\r
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)\r
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)\r
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \\r
+ ((ACTION) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Encoder_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)\r
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)\r
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)\r
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \\r
+ ((MODE) == TIM_EncoderMode_TI2) || \\r
+ ((MODE) == TIM_EncoderMode_TI12))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup TIM_Event_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_EventSource_Update ((uint16_t)0x0001)\r
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)\r
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)\r
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)\r
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)\r
+#define TIM_EventSource_COM ((uint16_t)0x0020)\r
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)\r
+#define TIM_EventSource_Break ((uint16_t)0x0080)\r
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Update_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow\r
+ or the setting of UG bit, or an update generation\r
+ through the slave mode controller. */\r
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */\r
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \\r
+ ((SOURCE) == TIM_UpdateSource_Regular))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Preload_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)\r
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \\r
+ ((STATE) == TIM_OCPreload_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Fast_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCFast_Enable ((uint16_t)0x0004)\r
+#define TIM_OCFast_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \\r
+ ((STATE) == TIM_OCFast_Disable))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Clear_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCClear_Enable ((uint16_t)0x0080)\r
+#define TIM_OCClear_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \\r
+ ((STATE) == TIM_OCClear_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Trigger_Output_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)\r
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)\r
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)\r
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)\r
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)\r
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)\r
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)\r
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)\r
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \\r
+ ((SOURCE) == TIM_TRGOSource_Enable) || \\r
+ ((SOURCE) == TIM_TRGOSource_Update) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_SlaveMode_Reset ((uint16_t)0x0004)\r
+#define TIM_SlaveMode_Gated ((uint16_t)0x0005)\r
+#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)\r
+#define TIM_SlaveMode_External1 ((uint16_t)0x0007)\r
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \\r
+ ((MODE) == TIM_SlaveMode_Gated) || \\r
+ ((MODE) == TIM_SlaveMode_Trigger) || \\r
+ ((MODE) == TIM_SlaveMode_External1))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Master_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)\r
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \\r
+ ((STATE) == TIM_MasterSlaveMode_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+/** @defgroup TIM_Remap \r
+ * @{\r
+ */\r
+\r
+#define TIM2_TIM8_TRGO ((uint16_t)0x0000)\r
+#define TIM2_ETH_PTP ((uint16_t)0x0400)\r
+#define TIM2_USBFS_SOF ((uint16_t)0x0800)\r
+#define TIM2_USBHS_SOF ((uint16_t)0x0C00)\r
+\r
+#define TIM5_GPIO ((uint16_t)0x0000)\r
+#define TIM5_LSI ((uint16_t)0x0040)\r
+#define TIM5_LSE ((uint16_t)0x0080)\r
+#define TIM5_RTC ((uint16_t)0x00C0)\r
+\r
+#define TIM11_GPIO ((uint16_t)0x0000)\r
+#define TIM11_HSE ((uint16_t)0x0002)\r
+\r
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\\r
+ ((TIM_REMAP) == TIM2_ETH_PTP)||\\r
+ ((TIM_REMAP) == TIM2_USBFS_SOF)||\\r
+ ((TIM_REMAP) == TIM2_USBHS_SOF)||\\r
+ ((TIM_REMAP) == TIM5_GPIO)||\\r
+ ((TIM_REMAP) == TIM5_LSI)||\\r
+ ((TIM_REMAP) == TIM5_LSE)||\\r
+ ((TIM_REMAP) == TIM5_RTC)||\\r
+ ((TIM_REMAP) == TIM11_GPIO)||\\r
+ ((TIM_REMAP) == TIM11_HSE))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+/** @defgroup TIM_Flags \r
+ * @{\r
+ */\r
+\r
+#define TIM_FLAG_Update ((uint16_t)0x0001)\r
+#define TIM_FLAG_CC1 ((uint16_t)0x0002)\r
+#define TIM_FLAG_CC2 ((uint16_t)0x0004)\r
+#define TIM_FLAG_CC3 ((uint16_t)0x0008)\r
+#define TIM_FLAG_CC4 ((uint16_t)0x0010)\r
+#define TIM_FLAG_COM ((uint16_t)0x0020)\r
+#define TIM_FLAG_Trigger ((uint16_t)0x0040)\r
+#define TIM_FLAG_Break ((uint16_t)0x0080)\r
+#define TIM_FLAG_CC1OF ((uint16_t)0x0200)\r
+#define TIM_FLAG_CC2OF ((uint16_t)0x0400)\r
+#define TIM_FLAG_CC3OF ((uint16_t)0x0800)\r
+#define TIM_FLAG_CC4OF ((uint16_t)0x1000)\r
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \\r
+ ((FLAG) == TIM_FLAG_CC1) || \\r
+ ((FLAG) == TIM_FLAG_CC2) || \\r
+ ((FLAG) == TIM_FLAG_CC3) || \\r
+ ((FLAG) == TIM_FLAG_CC4) || \\r
+ ((FLAG) == TIM_FLAG_COM) || \\r
+ ((FLAG) == TIM_FLAG_Trigger) || \\r
+ ((FLAG) == TIM_FLAG_Break) || \\r
+ ((FLAG) == TIM_FLAG_CC1OF) || \\r
+ ((FLAG) == TIM_FLAG_CC2OF) || \\r
+ ((FLAG) == TIM_FLAG_CC3OF) || \\r
+ ((FLAG) == TIM_FLAG_CC4OF))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Filer_Value \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Filter \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Legacy \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer\r
+#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers\r
+#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers\r
+#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers\r
+#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers\r
+#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers\r
+#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers\r
+#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers\r
+#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers\r
+#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers\r
+#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers\r
+#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers\r
+#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers\r
+#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers\r
+#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers\r
+#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers\r
+#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers\r
+#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+/* TimeBase management ********************************************************/\r
+void TIM_DeInit(TIM_TypeDef* TIMx);\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);\r
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Output Compare management **************************************************/\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);\r
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);\r
+\r
+/* Input Capture management ***************************************************/\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+\r
+/* Advanced-control timers (TIM1 and TIM8) specific features ******************/\r
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);\r
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);\r
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Interrupts, DMA and flags management ***************************************/\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Clocks management **********************************************************/\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r
+\r
+/* Synchronization management *************************************************/\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+\r
+/* Specific interface management **********************************************/ \r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Specific remapping management **********************************************/\r
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F4xx_TIM_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_usart.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the USART \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_USART_H\r
+#define __STM32F4xx_USART_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup USART\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+\r
+/** \r
+ * @brief USART Init Structure definition \r
+ */ \r
+ \r
+typedef struct\r
+{\r
+ uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.\r
+ The baud rate is computed using the following formula:\r
+ - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))\r
+ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 \r
+ Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */\r
+\r
+ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
+ This parameter can be a value of @ref USART_Word_Length */\r
+\r
+ uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.\r
+ This parameter can be a value of @ref USART_Stop_Bits */\r
+\r
+ uint16_t USART_Parity; /*!< Specifies the parity mode.\r
+ This parameter can be a value of @ref USART_Parity\r
+ @note When parity is enabled, the computed parity is inserted\r
+ at the MSB position of the transmitted data (9th bit when\r
+ the word length is set to 9 data bits; 8th bit when the\r
+ word length is set to 8 data bits). */\r
+ \r
+ uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Mode */\r
+\r
+ uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled\r
+ or disabled.\r
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */\r
+} USART_InitTypeDef;\r
+\r
+/** \r
+ * @brief USART Clock Init Structure definition \r
+ */ \r
+ \r
+typedef struct\r
+{\r
+\r
+ uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Clock */\r
+\r
+ uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock.\r
+ This parameter can be a value of @ref USART_Clock_Polarity */\r
+\r
+ uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.\r
+ This parameter can be a value of @ref USART_Clock_Phase */\r
+\r
+ uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r
+ This parameter can be a value of @ref USART_Last_Bit */\r
+} USART_ClockInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup USART_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
+ ((PERIPH) == USART2) || \\r
+ ((PERIPH) == USART3) || \\r
+ ((PERIPH) == UART4) || \\r
+ ((PERIPH) == UART5) || \\r
+ ((PERIPH) == USART6))\r
+\r
+#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
+ ((PERIPH) == USART2) || \\r
+ ((PERIPH) == USART3) || \\r
+ ((PERIPH) == USART6))\r
+\r
+/** @defgroup USART_Word_Length \r
+ * @{\r
+ */ \r
+ \r
+#define USART_WordLength_8b ((uint16_t)0x0000)\r
+#define USART_WordLength_9b ((uint16_t)0x1000)\r
+ \r
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \\r
+ ((LENGTH) == USART_WordLength_9b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Stop_Bits \r
+ * @{\r
+ */ \r
+ \r
+#define USART_StopBits_1 ((uint16_t)0x0000)\r
+#define USART_StopBits_0_5 ((uint16_t)0x1000)\r
+#define USART_StopBits_2 ((uint16_t)0x2000)\r
+#define USART_StopBits_1_5 ((uint16_t)0x3000)\r
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \\r
+ ((STOPBITS) == USART_StopBits_0_5) || \\r
+ ((STOPBITS) == USART_StopBits_2) || \\r
+ ((STOPBITS) == USART_StopBits_1_5))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Parity \r
+ * @{\r
+ */ \r
+ \r
+#define USART_Parity_No ((uint16_t)0x0000)\r
+#define USART_Parity_Even ((uint16_t)0x0400)\r
+#define USART_Parity_Odd ((uint16_t)0x0600) \r
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \\r
+ ((PARITY) == USART_Parity_Even) || \\r
+ ((PARITY) == USART_Parity_Odd))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Mode \r
+ * @{\r
+ */ \r
+ \r
+#define USART_Mode_Rx ((uint16_t)0x0004)\r
+#define USART_Mode_Tx ((uint16_t)0x0008)\r
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Hardware_Flow_Control \r
+ * @{\r
+ */ \r
+#define USART_HardwareFlowControl_None ((uint16_t)0x0000)\r
+#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)\r
+#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)\r
+#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)\r
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
+ (((CONTROL) == USART_HardwareFlowControl_None) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_CTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock \r
+ * @{\r
+ */ \r
+#define USART_Clock_Disable ((uint16_t)0x0000)\r
+#define USART_Clock_Enable ((uint16_t)0x0800)\r
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \\r
+ ((CLOCK) == USART_Clock_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock_Polarity \r
+ * @{\r
+ */\r
+ \r
+#define USART_CPOL_Low ((uint16_t)0x0000)\r
+#define USART_CPOL_High ((uint16_t)0x0400)\r
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock_Phase\r
+ * @{\r
+ */\r
+\r
+#define USART_CPHA_1Edge ((uint16_t)0x0000)\r
+#define USART_CPHA_2Edge ((uint16_t)0x0200)\r
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Last_Bit\r
+ * @{\r
+ */\r
+\r
+#define USART_LastBit_Disable ((uint16_t)0x0000)\r
+#define USART_LastBit_Enable ((uint16_t)0x0100)\r
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \\r
+ ((LASTBIT) == USART_LastBit_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Interrupt_definition \r
+ * @{\r
+ */\r
+ \r
+#define USART_IT_PE ((uint16_t)0x0028)\r
+#define USART_IT_TXE ((uint16_t)0x0727)\r
+#define USART_IT_TC ((uint16_t)0x0626)\r
+#define USART_IT_RXNE ((uint16_t)0x0525)\r
+#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */\r
+#define USART_IT_IDLE ((uint16_t)0x0424)\r
+#define USART_IT_LBD ((uint16_t)0x0846)\r
+#define USART_IT_CTS ((uint16_t)0x096A)\r
+#define USART_IT_ERR ((uint16_t)0x0060)\r
+#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */\r
+#define USART_IT_NE ((uint16_t)0x0260)\r
+#define USART_IT_FE ((uint16_t)0x0160)\r
+\r
+/** @defgroup USART_Legacy \r
+ * @{\r
+ */\r
+#define USART_IT_ORE USART_IT_ORE_ER \r
+/**\r
+ * @}\r
+ */\r
+\r
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))\r
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \\r
+ ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \\r
+ ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))\r
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_DMA_Requests \r
+ * @{\r
+ */\r
+\r
+#define USART_DMAReq_Tx ((uint16_t)0x0080)\r
+#define USART_DMAReq_Rx ((uint16_t)0x0040)\r
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_WakeUp_methods\r
+ * @{\r
+ */\r
+\r
+#define USART_WakeUp_IdleLine ((uint16_t)0x0000)\r
+#define USART_WakeUp_AddressMark ((uint16_t)0x0800)\r
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \\r
+ ((WAKEUP) == USART_WakeUp_AddressMark))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_LIN_Break_Detection_Length \r
+ * @{\r
+ */\r
+ \r
+#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)\r
+#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)\r
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \\r
+ (((LENGTH) == USART_LINBreakDetectLength_10b) || \\r
+ ((LENGTH) == USART_LINBreakDetectLength_11b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_IrDA_Low_Power \r
+ * @{\r
+ */\r
+\r
+#define USART_IrDAMode_LowPower ((uint16_t)0x0004)\r
+#define USART_IrDAMode_Normal ((uint16_t)0x0000)\r
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \\r
+ ((MODE) == USART_IrDAMode_Normal))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Flags \r
+ * @{\r
+ */\r
+\r
+#define USART_FLAG_CTS ((uint16_t)0x0200)\r
+#define USART_FLAG_LBD ((uint16_t)0x0100)\r
+#define USART_FLAG_TXE ((uint16_t)0x0080)\r
+#define USART_FLAG_TC ((uint16_t)0x0040)\r
+#define USART_FLAG_RXNE ((uint16_t)0x0020)\r
+#define USART_FLAG_IDLE ((uint16_t)0x0010)\r
+#define USART_FLAG_ORE ((uint16_t)0x0008)\r
+#define USART_FLAG_NE ((uint16_t)0x0004)\r
+#define USART_FLAG_FE ((uint16_t)0x0002)\r
+#define USART_FLAG_PE ((uint16_t)0x0001)\r
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \\r
+ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \\r
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \\r
+ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \\r
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))\r
+ \r
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
+\r
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001))\r
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)\r
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+/* Function used to set the USART configuration to the default reset state ***/ \r
+void USART_DeInit(USART_TypeDef* USARTx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);\r
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* Data transfers functions ***************************************************/ \r
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);\r
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);\r
+\r
+/* Multi-Processor Communication functions ************************************/\r
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* LIN mode functions *********************************************************/\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SendBreak(USART_TypeDef* USARTx);\r
+\r
+/* Half-duplex mode function **************************************************/\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* Smartcard mode functions ***************************************************/\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);\r
+\r
+/* IrDA mode functions ********************************************************/\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F4xx_USART_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_wwdg.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains all the functions prototypes for the WWDG firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_WWDG_H\r
+#define __STM32F4xx_WWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup WWDG\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup WWDG_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup WWDG_Prescaler \r
+ * @{\r
+ */\r
+ \r
+#define WWDG_Prescaler_1 ((uint32_t)0x00000000)\r
+#define WWDG_Prescaler_2 ((uint32_t)0x00000080)\r
+#define WWDG_Prescaler_4 ((uint32_t)0x00000100)\r
+#define WWDG_Prescaler_8 ((uint32_t)0x00000180)\r
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \\r
+ ((PRESCALER) == WWDG_Prescaler_2) || \\r
+ ((PRESCALER) == WWDG_Prescaler_4) || \\r
+ ((PRESCALER) == WWDG_Prescaler_8))\r
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)\r
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+ \r
+/* Function used to set the WWDG configuration to the default reset state ****/ \r
+void WWDG_DeInit(void);\r
+\r
+/* Prescaler, Refresh window and Counter configuration functions **************/\r
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);\r
+void WWDG_SetWindowValue(uint8_t WindowValue);\r
+void WWDG_EnableIT(void);\r
+void WWDG_SetCounter(uint8_t Counter);\r
+\r
+/* WWDG activation function ***************************************************/\r
+void WWDG_Enable(uint8_t Counter);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+FlagStatus WWDG_GetFlagStatus(void);\r
+void WWDG_ClearFlag(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F4xx_WWDG_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file misc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file provides all the miscellaneous firmware functions (add-on\r
+ * to CMSIS functions).\r
+ * \r
+ * @verbatim \r
+ * \r
+ * =================================================================== \r
+ * How to configure Interrupts using driver \r
+ * =================================================================== \r
+ * \r
+ * This section provide functions allowing to configure the NVIC interrupts (IRQ).\r
+ * The Cortex-M4 exceptions are managed by CMSIS functions.\r
+ *\r
+ * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()\r
+ * function according to the following table.\r
+ \r
+ * The table below gives the allowed values of the pre-emption priority and subpriority according\r
+ * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r
+ * ==========================================================================================================================\r
+ * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r
+ * ==========================================================================================================================\r
+ * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority\r
+ * | | | 4 bits for subpriority\r
+ * --------------------------------------------------------------------------------------------------------------------------\r
+ * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority\r
+ * | | | 3 bits for subpriority\r
+ * -------------------------------------------------------------------------------------------------------------------------- \r
+ * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority\r
+ * | | | 2 bits for subpriority\r
+ * -------------------------------------------------------------------------------------------------------------------------- \r
+ * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority\r
+ * | | | 1 bits for subpriority\r
+ * -------------------------------------------------------------------------------------------------------------------------- \r
+ * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority\r
+ * | | | 0 bits for subpriority \r
+ * ========================================================================================================================== \r
+ *\r
+ * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() \r
+ *\r
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. \r
+ * The pending IRQ priority will be managed only by the subpriority.\r
+ *\r
+ * @note IRQ priority order (sorted by highest to lowest priority):\r
+ * - Lowest pre-emption priority\r
+ * - Lowest subpriority\r
+ * - Lowest hardware priority (IRQ number)\r
+ *\r
+ * @endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "misc.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MISC \r
+ * @brief MISC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup MISC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.\r
+ * @param NVIC_PriorityGroup: specifies the priority grouping bits length. \r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority\r
+ * 4 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority\r
+ * 0 bits for subpriority\r
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. \r
+ * The pending IRQ priority will be managed only by the subpriority. \r
+ * @retval None\r
+ */\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r
+ \r
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the NVIC peripheral according to the specified\r
+ * parameters in the NVIC_InitStruct.\r
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r
+ * function should be called before. \r
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains\r
+ * the configuration information for the specified NVIC peripheral.\r
+ * @retval None\r
+ */\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
+{\r
+ uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); \r
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r
+ \r
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
+ {\r
+ /* Compute the Corresponding IRQ Priority --------------------------------*/ \r
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;\r
+ tmppre = (0x4 - tmppriority);\r
+ tmpsub = tmpsub >> tmppriority;\r
+\r
+ tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r
+ tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);\r
+ \r
+ tmppriority = tmppriority << 0x04;\r
+ \r
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;\r
+ \r
+ /* Enable the Selected IRQ Channels --------------------------------------*/\r
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Selected IRQ Channels -------------------------------------*/\r
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the vector table location and Offset.\r
+ * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.\r
+ * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.\r
+ * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.\r
+ * @retval None\r
+ */\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));\r
+ assert_param(IS_NVIC_OFFSET(Offset)); \r
+ \r
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);\r
+}\r
+\r
+/**\r
+ * @brief Selects the condition for the system to enter low power mode.\r
+ * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.\r
+ * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.\r
+ * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.\r
+ * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_LP(LowPowerMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ SCB->SCR |= LowPowerMode;\r
+ }\r
+ else\r
+ {\r
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the SysTick clock source.\r
+ * @param SysTick_CLKSource: specifies the SysTick clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.\r
+ * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.\r
+ * @retval None\r
+ */\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
+ {\r
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_exti.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the EXTI peripheral: \r
+ * - Initialization and Configuration\r
+ * - Interrupts and flags management\r
+ *\r
+ * @verbatim \r
+ * \r
+ * ===================================================================\r
+ * EXTI features\r
+ * ===================================================================\r
+ * \r
+ * External interrupt/event lines are mapped as following:\r
+ * 1- All available GPIO pins are connected to the 16 external \r
+ * interrupt/event lines from EXTI0 to EXTI15.\r
+ * 2- EXTI line 16 is connected to the PVD Output\r
+ * 3- EXTI line 17 is connected to the RTC Alarm event\r
+ * 4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event \r
+ * 5- EXTI line 19 is connected to the Ethernet Wakeup event\r
+ * 6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event \r
+ * 7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events \r
+ * 8- EXTI line 22 is connected to the RTC Wakeup event\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * =================================================================== \r
+ * \r
+ * In order to use an I/O pin as an external interrupt source, follow\r
+ * steps below:\r
+ * 1- Configure the I/O in input mode using GPIO_Init()\r
+ * 2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()\r
+ * 3- Select the mode(interrupt, event) and configure the trigger \r
+ * selection (Rising, falling or both) using EXTI_Init()\r
+ * 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()\r
+ * \r
+ * @note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx\r
+ * registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+ * \r
+ * @endverbatim \r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx_exti.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI \r
+ * @brief EXTI driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup EXTI_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the EXTI peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void EXTI_DeInit(void)\r
+{\r
+ EXTI->IMR = 0x00000000;\r
+ EXTI->EMR = 0x00000000;\r
+ EXTI->RTSR = 0x00000000;\r
+ EXTI->FTSR = 0x00000000;\r
+ EXTI->PR = 0x007FFFFF;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the EXTI peripheral according to the specified\r
+ * parameters in the EXTI_InitStruct.\r
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure\r
+ * that contains the configuration information for the EXTI peripheral.\r
+ * @retval None\r
+ */\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));\r
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));\r
+ assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); \r
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));\r
+\r
+ tmp = (uint32_t)EXTI_BASE;\r
+ \r
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)\r
+ {\r
+ /* Clear EXTI line configuration */\r
+ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;\r
+ EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;\r
+ \r
+ tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+ \r
+ /* Select the trigger for the selected external interrupts */\r
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)\r
+ {\r
+ /* Rising Falling edge */\r
+ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ else\r
+ {\r
+ tmp = (uint32_t)EXTI_BASE;\r
+ tmp += EXTI_InitStruct->EXTI_Trigger;\r
+\r
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+ /* Disable the selected external lines */\r
+ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each EXTI_InitStruct member with its reset value.\r
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;\r
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;\r
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;\r
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;\r
+}\r
+\r
+/**\r
+ * @brief Generates a Software interrupt on selected EXTI line.\r
+ * @param EXTI_Line: specifies the EXTI line on which the software interrupt\r
+ * will be generated.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..22)\r
+ * @retval None\r
+ */\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->SWIER |= EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Group2 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line flag is set or not.\r
+ * @param EXTI_Line: specifies the EXTI line flag to check.\r
+ * This parameter can be EXTI_Linex where x can be(0..22)\r
+ * @retval The new state of EXTI_Line (SET or RESET).\r
+ */\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+ \r
+ if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending flags.\r
+ * @param EXTI_Line: specifies the EXTI lines flags to clear.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..22)\r
+ * @retval None\r
+ */\r
+void EXTI_ClearFlag(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line is asserted or not.\r
+ * @param EXTI_Line: specifies the EXTI line to check.\r
+ * This parameter can be EXTI_Linex where x can be(0..22)\r
+ * @retval The new state of EXTI_Line (SET or RESET).\r
+ */\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+ \r
+ enablestatus = EXTI->IMR & EXTI_Line;\r
+ if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending bits.\r
+ * @param EXTI_Line: specifies the EXTI lines to clear.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..22)\r
+ * @retval None\r
+ */\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_gpio.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the GPIO peripheral: \r
+ * - Initialization and Configuration\r
+ * - GPIO Read and Write\r
+ * - GPIO Alternate functions configuration\r
+ * \r
+ * @verbatim\r
+ *\r
+ * ===================================================================\r
+ * How to use this driver\r
+ * =================================================================== \r
+ * 1. Enable the GPIO AHB clock using the following function\r
+ * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);\r
+ * \r
+ * 2. Configure the GPIO pin(s) using GPIO_Init()\r
+ * Four possible configuration are available for each pin:\r
+ * - Input: Floating, Pull-up, Pull-down.\r
+ * - Output: Push-Pull (Pull-up, Pull-down or no Pull)\r
+ * Open Drain (Pull-up, Pull-down or no Pull).\r
+ * In output mode, the speed is configurable: 2 MHz, 25 MHz,\r
+ * 50 MHz or 100 MHz.\r
+ * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)\r
+ * Open Drain (Pull-up, Pull-down or no Pull).\r
+ * - Analog: required mode when a pin is to be used as ADC channel\r
+ * or DAC output.\r
+ * \r
+ * 3- Peripherals alternate function:\r
+ * - For ADC and DAC, configure the desired pin in analog mode using \r
+ * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;\r
+ * - For other peripherals (TIM, USART...):\r
+ * - Connect the pin to the desired peripherals' Alternate \r
+ * Function (AF) using GPIO_PinAFConfig() function\r
+ * - Configure the desired pin in alternate function mode using\r
+ * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ * - Select the type, pull-up/pull-down and output speed via \r
+ * GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
+ * - Call GPIO_Init() function\r
+ * \r
+ * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()\r
+ * \r
+ * 5. To set/reset the level of a pin configured in output mode use\r
+ * GPIO_SetBits()/GPIO_ResetBits()\r
+ * \r
+ * 6. During and just after reset, the alternate functions are not \r
+ * active and the GPIO pins are configured in input floating mode\r
+ * (except JTAG pins).\r
+ *\r
+ * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as \r
+ * general-purpose (PC14 and PC15, respectively) when the LSE\r
+ * oscillator is off. The LSE has priority over the GPIO function.\r
+ *\r
+ * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as \r
+ * general-purpose PH0 and PH1, respectively, when the HSE \r
+ * oscillator is off. The HSE has priority over the GPIO function.\r
+ * \r
+ * @endverbatim \r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx_gpio.h"\r
+#include "stm32f4xx_rcc.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO \r
+ * @brief GPIO driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup GPIO_Group1 Initialization and Configuration\r
+ * @brief Initialization and Configuration\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset values.\r
+ * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).\r
+ * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+\r
+ if (GPIOx == GPIOA)\r
+ {\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOB)\r
+ {\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOC)\r
+ {\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOD)\r
+ {\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOE)\r
+ {\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOF)\r
+ {\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOG)\r
+ {\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOH)\r
+ {\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if (GPIOx == GPIOI)\r
+ {\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);\r
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.\r
+ * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains\r
+ * the configuration information for the specified GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));\r
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));\r
+ assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));\r
+\r
+ /* -------------------------Configure the port pins---------------- */\r
+ /*-- GPIO Mode Configuration --*/\r
+ for (pinpos = 0x00; pinpos < 0x10; pinpos++)\r
+ {\r
+ pos = ((uint32_t)0x01) << pinpos;\r
+ /* Get the port pins position */\r
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;\r
+\r
+ if (currentpin == pos)\r
+ {\r
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));\r
+ GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));\r
+\r
+ if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))\r
+ {\r
+ /* Check Speed mode parameters */\r
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));\r
+\r
+ /* Speed mode configuration */\r
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));\r
+ GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));\r
+\r
+ /* Check Output mode parameters */\r
+ assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));\r
+\r
+ /* Output mode configuration*/\r
+ GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;\r
+ GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));\r
+ }\r
+\r
+ /* Pull-up Pull down resistor configuration*/\r
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));\r
+ GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each GPIO_InitStruct member with its default value.\r
+ * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ /* Reset GPIO init structure parameters values */\r
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;\r
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;\r
+ GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;\r
+ GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+}\r
+\r
+/**\r
+ * @brief Locks GPIO Pins configuration registers.\r
+ * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r
+ * @note The configuration of the locked GPIO pins can no longer be modified\r
+ * until the next reset.\r
+ * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be locked.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ __IO uint32_t tmp = 0x00010000;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ tmp |= GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Reset LCKK bit */\r
+ GPIOx->LCKR = GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Group2 GPIO Read and Write\r
+ * @brief GPIO Read and Write\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ GPIO Read and Write\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads the specified input port pin.\r
+ * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to read.\r
+ * This parameter can be GPIO_Pin_x where x can be (0..15).\r
+ * @retval The input port pin value.\r
+ */\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+\r
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO input data port.\r
+ * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r
+ * @retval GPIO input data port value.\r
+ */\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+\r
+ return ((uint16_t)GPIOx->IDR);\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified output data port bit.\r
+ * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to read.\r
+ * This parameter can be GPIO_Pin_x where x can be (0..15).\r
+ * @retval The output port pin value.\r
+ */\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+\r
+ if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO output data port.\r
+ * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r
+ * @retval GPIO output data port value.\r
+ */\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+\r
+ return ((uint16_t)GPIOx->ODR);\r
+}\r
+\r
+/**\r
+ * @brief Sets the selected data port bits.\r
+ * @note This functions uses GPIOx_BSRR register to allow atomic read/modify \r
+ * accesses. In this way, there is no risk of an IRQ occurring between\r
+ * the read and the modify access.\r
+ * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ GPIOx->BSRRL = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Clears the selected data port bits.\r
+ * @note This functions uses GPIOx_BSRR register to allow atomic read/modify \r
+ * accesses. In this way, there is no risk of an IRQ occurring between\r
+ * the read and the modify access.\r
+ * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ GPIOx->BSRRH = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Sets or clears the selected data port bit.\r
+ * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).\r
+ * @param BitVal: specifies the value to be written to the selected bit.\r
+ * This parameter can be one of the BitAction enum values:\r
+ * @arg Bit_RESET: to clear the port pin\r
+ * @arg Bit_SET: to set the port pin\r
+ * @retval None\r
+ */\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+ assert_param(IS_GPIO_BIT_ACTION(BitVal));\r
+\r
+ if (BitVal != Bit_RESET)\r
+ {\r
+ GPIOx->BSRRL = GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BSRRH = GPIO_Pin ;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes data to the specified GPIO data port.\r
+ * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r
+ * @param PortVal: specifies the value to be written to the port output data register.\r
+ * @retval None\r
+ */\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+\r
+ GPIOx->ODR = PortVal;\r
+}\r
+\r
+/**\r
+ * @brief Toggles the specified GPIO pins..\r
+ * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: Specifies the pins to be toggled.\r
+ * @retval None\r
+ */\r
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+\r
+ GPIOx->ODR ^= GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function\r
+ * @brief GPIO Alternate functions configuration function\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ GPIO Alternate functions configuration function\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Changes the mapping of the specified pin.\r
+ * @param GPIOx: where x can be (A..I) to select the GPIO peripheral.\r
+ * @param GPIO_PinSource: specifies the pin for the Alternate function.\r
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+ * @param GPIO_AFSelection: selects the pin to used as Alternate function.\r
+ * This parameter can be one of the following values:\r
+ * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) \r
+ * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) \r
+ * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) \r
+ * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) \r
+ * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)\r
+ * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1\r
+ * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1\r
+ * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2\r
+ * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2\r
+ * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2\r
+ * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3\r
+ * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3\r
+ * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3\r
+ * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3\r
+ * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4\r
+ * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4\r
+ * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4\r
+ * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5\r
+ * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5\r
+ * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6\r
+ * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7\r
+ * @arg GPIO_AF_USART1: Connect USART1 pins to AF7\r
+ * @arg GPIO_AF_USART2: Connect USART2 pins to AF7\r
+ * @arg GPIO_AF_USART3: Connect USART3 pins to AF7\r
+ * @arg GPIO_AF_UART4: Connect UART4 pins to AF8\r
+ * @arg GPIO_AF_UART5: Connect UART5 pins to AF8\r
+ * @arg GPIO_AF_USART6: Connect USART6 pins to AF8\r
+ * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9\r
+ * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9\r
+ * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9\r
+ * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9\r
+ * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9\r
+ * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10\r
+ * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10\r
+ * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11\r
+ * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12\r
+ * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12\r
+ * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12\r
+ * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13\r
+ * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15\r
+ * @retval None\r
+ */\r
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)\r
+{\r
+ uint32_t temp = 0x00;\r
+ uint32_t temp_2 = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+ assert_param(IS_GPIO_AF(GPIO_AF));\r
+ \r
+ temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r
+ GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r
+ temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;\r
+ GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_rcc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Reset and clock control (RCC) peripheral:\r
+ * - Internal/external clocks, PLL, CSS and MCO configuration\r
+ * - System, AHB and APB busses clocks configuration\r
+ * - Peripheral clocks configuration\r
+ * - Interrupts and flags management\r
+ *\r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * RCC specific features\r
+ * ===================================================================\r
+ * \r
+ * After reset the device is running from Internal High Speed oscillator \r
+ * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache \r
+ * and I-Cache are disabled, and all peripherals are off except internal\r
+ * SRAM, Flash and JTAG.\r
+ * - There is no prescaler on High speed (AHB) and Low speed (APB) busses;\r
+ * all peripherals mapped on these busses are running at HSI speed.\r
+ * - The clock for all peripherals is switched off, except the SRAM and FLASH.\r
+ * - All GPIOs are in input floating state, except the JTAG pins which\r
+ * are assigned to be used for debug purpose.\r
+ * \r
+ * Once the device started from reset, the user application has to: \r
+ * - Configure the clock source to be used to drive the System clock\r
+ * (if the application needs higher frequency/performance)\r
+ * - Configure the System clock frequency and Flash settings \r
+ * - Configure the AHB and APB busses prescalers\r
+ * - Enable the clock for the peripheral(s) to be used\r
+ * - Configure the clock source(s) for peripherals which clocks are not\r
+ * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) \r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx_rcc.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC \r
+ * @brief RCC driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ------------ RCC registers bit address in the alias region ----------- */\r
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)\r
+/* --- CR Register ---*/\r
+/* Alias word address of HSION bit */\r
+#define CR_OFFSET (RCC_OFFSET + 0x00)\r
+#define HSION_BitNumber 0x00\r
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))\r
+/* Alias word address of CSSON bit */\r
+#define CSSON_BitNumber 0x13\r
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))\r
+/* Alias word address of PLLON bit */\r
+#define PLLON_BitNumber 0x18\r
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))\r
+/* Alias word address of PLLI2SON bit */\r
+#define PLLI2SON_BitNumber 0x1A\r
+#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))\r
+\r
+/* --- CFGR Register ---*/\r
+/* Alias word address of I2SSRC bit */\r
+#define CFGR_OFFSET (RCC_OFFSET + 0x08)\r
+#define I2SSRC_BitNumber 0x17\r
+#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))\r
+\r
+/* --- BDCR Register ---*/\r
+/* Alias word address of RTCEN bit */\r
+#define BDCR_OFFSET (RCC_OFFSET + 0x70)\r
+#define RTCEN_BitNumber 0x0F\r
+#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))\r
+/* Alias word address of BDRST bit */\r
+#define BDRST_BitNumber 0x10\r
+#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))\r
+/* --- CSR Register ---*/\r
+/* Alias word address of LSION bit */\r
+#define CSR_OFFSET (RCC_OFFSET + 0x74)\r
+#define LSION_BitNumber 0x00\r
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))\r
+/* ---------------------- RCC registers bit mask ------------------------ */\r
+/* CFGR register bit mask */\r
+#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)\r
+#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)\r
+\r
+/* RCC Flag Mask */\r
+#define FLAG_MASK ((uint8_t)0x1F)\r
+\r
+/* CR register byte 3 (Bits[23:16]) base address */\r
+#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)\r
+\r
+/* CIR register byte 2 (Bits[15:8]) base address */\r
+#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))\r
+\r
+/* CIR register byte 3 (Bits[23:16]) base address */\r
+#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))\r
+\r
+/* BDCR register base address */\r
+#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions\r
+ * @brief Internal and external clocks, PLL, CSS and MCO configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Internal/external clocks, PLL, CSS and MCO configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the internal/external clocks,\r
+ PLLs, CSS and MCO pins.\r
+ \r
+ 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through\r
+ the PLL as System clock source.\r
+\r
+ 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC\r
+ clock source.\r
+\r
+ 3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or\r
+ through the PLL as System clock source. Can be used also as RTC clock source.\r
+\r
+ 4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. \r
+\r
+ 5. PLL (clocked by HSI or HSE), featuring two different output clocks:\r
+ - The first output is used to generate the high speed system clock (up to 168 MHz)\r
+ - The second output is used to generate the clock for the USB OTG FS (48 MHz),\r
+ the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).\r
+\r
+ 6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve \r
+ high-quality audio performance on the I2S interface.\r
+ \r
+ 7. CSS (Clock security system), once enable and if a HSE clock failure occurs \r
+ (HSE used directly or through PLL as System clock source), the System clock\r
+ is automatically switched to HSI and an interrupt is generated if enabled. \r
+ The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) \r
+ exception vector. \r
+\r
+ 8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL\r
+ clock (through a configurable prescaler) on PA8 pin.\r
+\r
+ 9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S\r
+ clock (through a configurable prescaler) on PC9 pin.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the RCC clock configuration to the default reset state.\r
+ * @note The default reset state of the clock configuration is given below:\r
+ * - HSI ON and used as system clock source\r
+ * - HSE, PLL and PLLI2S OFF\r
+ * - AHB, APB1 and APB2 prescaler set to 1.\r
+ * - CSS, MCO1 and MCO2 OFF\r
+ * - All interrupts disabled\r
+ * @note This function doesn't modify the configuration of the\r
+ * - Peripheral clocks\r
+ * - LSI, LSE and RTC clocks \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_DeInit(void)\r
+{\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset CFGR register */\r
+ RCC->CFGR = 0x00000000;\r
+\r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset PLLCFGR register */\r
+ RCC->PLLCFGR = 0x24003010;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External High Speed oscillator (HSE).\r
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
+ * software should wait on HSERDY flag to be set indicating that HSE clock\r
+ * is stable and can be used to clock the PLL and/or system clock.\r
+ * @note HSE state can not be changed if it is used directly or through the\r
+ * PLL as system clock. In this case, you have to select another source\r
+ * of the system clock then change the HSE state (ex. disable it).\r
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. \r
+ * @note This function reset the CSSON bit, so if the Clock security system(CSS)\r
+ * was previously enabled you have to enable it again after calling this\r
+ * function. \r
+ * @param RCC_HSE: specifies the new state of the HSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after\r
+ * 6 HSE oscillator clock cycles.\r
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator\r
+ * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_HSEConfig(uint8_t RCC_HSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSE(RCC_HSE));\r
+\r
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r
+ *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;\r
+\r
+ /* Set the new HSE configuration -------------------------------------------*/\r
+ *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;\r
+}\r
+\r
+/**\r
+ * @brief Waits for HSE start-up.\r
+ * @note This functions waits on HSERDY flag to be set and return SUCCESS if \r
+ * this flag is set, otherwise returns ERROR if the timeout is reached \r
+ * and this flag is not set. The timeout value is defined by the constant\r
+ * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending\r
+ * on the HSE crystal used in your application. \r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: HSE oscillator is stable and ready to use\r
+ * - ERROR: HSE oscillator not yet ready\r
+ */\r
+ErrorStatus RCC_WaitForHSEStartUp(void)\r
+{\r
+ __IO uint32_t startupcounter = 0;\r
+ ErrorStatus status = ERROR;\r
+ FlagStatus hsestatus = RESET;\r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r
+ startupcounter++;\r
+ } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));\r
+\r
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ }\r
+ return (status);\r
+}\r
+\r
+/**\r
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal HSI RC.\r
+ * @param HSICalibrationValue: specifies the calibration trimming value.\r
+ * This parameter must be a number between 0 and 0x1F.\r
+ * @retval None\r
+ */\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));\r
+\r
+ tmpreg = RCC->CR;\r
+\r
+ /* Clear HSITRIM[4:0] bits */\r
+ tmpreg &= ~RCC_CR_HSITRIM;\r
+\r
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r
+ tmpreg |= (uint32_t)HSICalibrationValue << 3;\r
+\r
+ /* Store the new value */\r
+ RCC->CR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).\r
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.\r
+ * It is used (enabled by hardware) as system clock source after startup\r
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure\r
+ * of the HSE used directly or indirectly as system clock (if the Clock\r
+ * Security System CSS is enabled). \r
+ * @note HSI can not be stopped if it is used as system clock source. In this case,\r
+ * you have to select another source of the system clock then stop the HSI. \r
+ * @note After enabling the HSI, the application software should wait on HSIRDY\r
+ * flag to be set indicating that HSI clock is stable and can be used as\r
+ * system clock source. \r
+ * @param NewState: new state of the HSI.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
+ * clock cycles. \r
+ * @retval None\r
+ */\r
+void RCC_HSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External Low Speed oscillator (LSE).\r
+ * @note As the LSE is in the Backup domain and write access is denied to\r
+ * this domain after reset, you have to enable write access using \r
+ * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE\r
+ * (to be done once after reset). \r
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application\r
+ * software should wait on LSERDY flag to be set indicating that LSE clock\r
+ * is stable and can be used to clock the RTC.\r
+ * @param RCC_LSE: specifies the new state of the LSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after\r
+ * 6 LSE oscillator clock cycles.\r
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator\r
+ * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_LSEConfig(uint8_t RCC_LSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE(RCC_LSE));\r
+\r
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
+ /* Reset LSEON bit */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;\r
+\r
+ /* Reset LSEBYP bit */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;\r
+\r
+ /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */\r
+ switch (RCC_LSE)\r
+ {\r
+ case RCC_LSE_ON:\r
+ /* Set LSEON bit */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;\r
+ break;\r
+ case RCC_LSE_Bypass:\r
+ /* Set LSEBYP and LSEON bits */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).\r
+ * @note After enabling the LSI, the application software should wait on \r
+ * LSIRDY flag to be set indicating that LSI clock is stable and can\r
+ * be used to clock the IWDG and/or the RTC.\r
+ * @note LSI can not be disabled if the IWDG is running. \r
+ * @param NewState: new state of the LSI.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
+ * clock cycles. \r
+ * @retval None\r
+ */\r
+void RCC_LSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the main PLL clock source, multiplication and division factors.\r
+ * @note This function must be used only when the main PLL is disabled.\r
+ * \r
+ * @param RCC_PLLSource: specifies the PLL entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry\r
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. \r
+ * \r
+ * @param PLLM: specifies the division factor for PLL VCO input clock\r
+ * This parameter must be a number between 0 and 63.\r
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input\r
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r
+ * of 2 MHz to limit PLL jitter.\r
+ * \r
+ * @param PLLN: specifies the multiplication factor for PLL VCO output clock\r
+ * This parameter must be a number between 192 and 432.\r
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO\r
+ * output frequency is between 192 and 432 MHz.\r
+ * \r
+ * @param PLLP: specifies the division factor for main system clock (SYSCLK)\r
+ * This parameter must be a number in the range {2, 4, 6, or 8}.\r
+ * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on\r
+ * the System clock frequency.\r
+ * \r
+ * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks\r
+ * This parameter must be a number between 4 and 15.\r
+ * @note If the USB OTG FS is used in your application, you have to set the\r
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,\r
+ * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work\r
+ * correctly.\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
+ assert_param(IS_RCC_PLLM_VALUE(PLLM));\r
+ assert_param(IS_RCC_PLLN_VALUE(PLLN));\r
+ assert_param(IS_RCC_PLLP_VALUE(PLLP));\r
+ assert_param(IS_RCC_PLLQ_VALUE(PLLQ));\r
+\r
+ RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |\r
+ (PLLQ << 24);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the main PLL.\r
+ * @note After enabling the main PLL, the application software should wait on \r
+ * PLLRDY flag to be set indicating that PLL clock is stable and can\r
+ * be used as system clock source.\r
+ * @note The main PLL can not be disabled if it is used as system clock source\r
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.\r
+ * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_PLLCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the PLLI2S clock multiplication and division factors.\r
+ * \r
+ * @note This function must be used only when the PLLI2S is disabled.\r
+ * @note PLLI2S clock source is common with the main PLL (configured in \r
+ * RCC_PLLConfig function ) \r
+ * \r
+ * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock\r
+ * This parameter must be a number between 192 and 432.\r
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO \r
+ * output frequency is between 192 and 432 MHz.\r
+ * \r
+ * @param PLLI2SR: specifies the division factor for I2S clock\r
+ * This parameter must be a number between 2 and 7.\r
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz\r
+ * on the I2S clock frequency.\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));\r
+ assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));\r
+\r
+ RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PLLI2S. \r
+ * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. \r
+ * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_PLLI2SCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Clock Security System.\r
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator\r
+ * is automatically disabled and an interrupt is generated to inform the\r
+ * software about the failure (Clock Security System Interrupt, CSSI),\r
+ * allowing the MCU to perform rescue operations. The CSSI is linked to \r
+ * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. \r
+ * @param NewState: new state of the Clock Security System.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Selects the clock source to output on MCO1 pin(PA8).\r
+ * @note PA8 should be configured in alternate function mode.\r
+ * @param RCC_MCO1Source: specifies the clock source to output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source\r
+ * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source\r
+ * @param RCC_MCO1Div: specifies the MCO1 prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO1Div_1: no division applied to MCO1 clock\r
+ * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock\r
+ * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock\r
+ * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock\r
+ * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock\r
+ * @retval None\r
+ */\r
+void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));\r
+ assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); \r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */\r
+ tmpreg &= CFGR_MCO1_RESET_MASK;\r
+\r
+ /* Select MCO1 clock source and prescaler */\r
+ tmpreg |= RCC_MCO1Source | RCC_MCO1Div;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg; \r
+}\r
+\r
+/**\r
+ * @brief Selects the clock source to output on MCO2 pin(PC9).\r
+ * @note PC9 should be configured in alternate function mode.\r
+ * @param RCC_MCO2Source: specifies the clock source to output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source\r
+ * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source\r
+ * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source\r
+ * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source\r
+ * @param RCC_MCO2Div: specifies the MCO2 prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO2Div_1: no division applied to MCO2 clock\r
+ * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock\r
+ * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock\r
+ * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock\r
+ * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock\r
+ * @retval None\r
+ */\r
+void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));\r
+ assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear MCO2 and MCO2PRE[2:0] bits */\r
+ tmpreg &= CFGR_MCO2_RESET_MASK;\r
+\r
+ /* Select MCO2 clock source and prescaler */\r
+ tmpreg |= RCC_MCO2Source | RCC_MCO2Div;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions\r
+ * @brief System, AHB and APB busses clocks configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ System, AHB and APB busses clocks configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the System, AHB, APB1 and \r
+ APB2 busses clocks.\r
+ \r
+ 1. Several clock sources can be used to drive the System clock (SYSCLK): HSI,\r
+ HSE and PLL.\r
+ The AHB clock (HCLK) is derived from System clock through configurable prescaler\r
+ and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...).\r
+ APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through \r
+ configurable prescalers and used to clock the peripherals mapped on these busses.\r
+ You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. \r
+\r
+@note All the peripheral clocks are derived from the System clock (SYSCLK) except:\r
+ - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or\r
+ from an external clock mapped on the I2S_CKIN pin. \r
+ You have to use RCC_I2SCLKConfig() function to configure this clock. \r
+ - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock\r
+ divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()\r
+ functions to configure this clock. \r
+ - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz\r
+ to work correctly, while the SDIO require a frequency equal or lower than\r
+ to 48. This clock is derived of the main PLL through PLLQ divider.\r
+ - IWDG clock which is always the LSI clock.\r
+ \r
+ 2. The maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 82 MHz and PCLK1 42 MHz.\r
+ Depending on the device voltage range, the maximum frequency should be \r
+ adapted accordingly:\r
+ +-------------------------------------------------------------------------------------+ \r
+ | Latency | HCLK clock frequency (MHz) |\r
+ | |---------------------------------------------------------------------| \r
+ | | voltage range | voltage range | voltage range | voltage range |\r
+ | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |\r
+ |---------------|----------------|----------------|-----------------|-----------------| \r
+ |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |\r
+ |---------------|----------------|----------------|-----------------|-----------------| \r
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | \r
+ |---------------|----------------|----------------|-----------------|-----------------| \r
+ |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |\r
+ |---------------|----------------|----------------|-----------------|-----------------| \r
+ |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |\r
+ |---------------|----------------|----------------|-----------------|-----------------| \r
+ |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |\r
+ |---------------|----------------|----------------|-----------------|-----------------| \r
+ |5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 | \r
+ |---------------|----------------|----------------|-----------------|-----------------| \r
+ |6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 | \r
+ |---------------|----------------|----------------|-----------------|-----------------| \r
+ |7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120| \r
+ +-------------------------------------------------------------------------------------+ \r
+ @note When VOS bit (in PWR_CR register) is reset to '0\92, the maximum value of HCLK is 144 MHz.\r
+ You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the system clock (SYSCLK).\r
+ * @note The HSI is used (enabled by hardware) as system clock source after\r
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case\r
+ * of failure of the HSE used directly or indirectly as system clock\r
+ * (if the Clock Security System CSS is enabled).\r
+ * @note A switch from one clock source to another occurs only if the target\r
+ * clock source is ready (clock stable after startup delay or PLL locked). \r
+ * If a clock source which is not yet ready is selected, the switch will\r
+ * occur when the clock source will be ready. \r
+ * You can use RCC_GetSYSCLKSource() function to know which clock is\r
+ * currently used as system clock source. \r
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source\r
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source\r
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source\r
+ * @retval None\r
+ */\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear SW[1:0] bits */\r
+ tmpreg &= ~RCC_CFGR_SW;\r
+\r
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
+ tmpreg |= RCC_SYSCLKSource;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the clock source used as system clock.\r
+ * @param None\r
+ * @retval The clock source used as system clock. The returned value can be one\r
+ * of the following:\r
+ * - 0x00: HSI used as system clock\r
+ * - 0x04: HSE used as system clock\r
+ * - 0x08: PLL used as system clock\r
+ */\r
+uint8_t RCC_GetSYSCLKSource(void)\r
+{\r
+ return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));\r
+}\r
+\r
+/**\r
+ * @brief Configures the AHB clock (HCLK).\r
+ * @note Depending on the device voltage range, the software has to set correctly\r
+ * these bits to ensure that HCLK not exceed the maximum allowed frequency\r
+ * (for more details refer to section above\r
+ * "CPU, AHB and APB busses clocks configuration functions")\r
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from \r
+ * the system clock (SYSCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK\r
+ * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2\r
+ * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4\r
+ * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8\r
+ * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16\r
+ * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64\r
+ * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r
+ * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r
+ * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r
+ * @retval None\r
+ */\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear HPRE[3:0] bits */\r
+ tmpreg &= ~RCC_CFGR_HPRE;\r
+\r
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r
+ tmpreg |= RCC_SYSCLK;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the Low Speed APB clock (PCLK1).\r
+ * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from \r
+ * the AHB clock (HCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HCLK_Div1: APB1 clock = HCLK\r
+ * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2\r
+ * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4\r
+ * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8\r
+ * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16\r
+ * @retval None\r
+ */\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear PPRE1[2:0] bits */\r
+ tmpreg &= ~RCC_CFGR_PPRE1;\r
+\r
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the High Speed APB clock (PCLK2).\r
+ * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from \r
+ * the AHB clock (HCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HCLK_Div1: APB2 clock = HCLK\r
+ * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2\r
+ * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4\r
+ * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8\r
+ * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16\r
+ * @retval None\r
+ */\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear PPRE2[2:0] bits */\r
+ tmpreg &= ~RCC_CFGR_PPRE2;\r
+\r
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK << 3;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, \r
+ * PCLK1 and PCLK2. \r
+ * \r
+ * @note The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\r
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)\r
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors. \r
+ * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature.\r
+ * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value\r
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ * \r
+ * @note The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ * \r
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold\r
+ * the clocks frequencies.\r
+ * \r
+ * @note This function can be used by the user application to compute the \r
+ * baudrate for the communication peripherals or configure other parameters.\r
+ * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function\r
+ * must be called to update the structure's field. Otherwise, any\r
+ * configuration based on this function will be incorrect.\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
+{\r
+ uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+\r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock source */\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
+ break;\r
+ case 0x04: /* HSE used as system clock source */\r
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;\r
+ break;\r
+ case 0x08: /* PLL used as system clock source */\r
+\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\r
+ SYSCLK = PLL_VCO / PLLP\r
+ */ \r
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\r
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r
+ \r
+ if (pllsource != 0)\r
+ {\r
+ /* HSE used as PLL clock source */\r
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r
+ }\r
+ else\r
+ {\r
+ /* HSI used as PLL clock source */\r
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); \r
+ }\r
+\r
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\r
+ RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;\r
+ break;\r
+ default:\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
+ break;\r
+ }\r
+ /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/\r
+\r
+ /* Get HCLK prescaler */\r
+ tmp = RCC->CFGR & RCC_CFGR_HPRE;\r
+ tmp = tmp >> 4;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* HCLK clock frequency */\r
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
+\r
+ /* Get PCLK1 prescaler */\r
+ tmp = RCC->CFGR & RCC_CFGR_PPRE1;\r
+ tmp = tmp >> 10;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* PCLK1 clock frequency */\r
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+\r
+ /* Get PCLK2 prescaler */\r
+ tmp = RCC->CFGR & RCC_CFGR_PPRE2;\r
+ tmp = tmp >> 13;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* PCLK2 clock frequency */\r
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group3 Peripheral clocks configuration functions\r
+ * @brief Peripheral clocks configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Peripheral clocks configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the Peripheral clocks. \r
+ \r
+ 1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31.\r
+ \r
+ 2. After restart from Reset or wakeup from STANDBY, all peripherals are off\r
+ except internal SRAM, Flash and JTAG. Before to start using a peripheral you\r
+ have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd()\r
+ , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.\r
+\r
+ 3. To reset the peripherals configuration (to the default state after device reset)\r
+ you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and \r
+ RCC_APB1PeriphResetCmd() functions.\r
+ \r
+ 4. To further reduce power consumption in SLEEP mode the peripheral clocks can\r
+ be disabled prior to executing the WFI or WFE instructions. You can do this\r
+ using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and\r
+ RCC_APB1PeriphClockLPModeCmd() functions. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC clock (RTCCLK).\r
+ * @note As the RTC clock configuration bits are in the Backup domain and write\r
+ * access is denied to this domain after reset, you have to enable write\r
+ * access using PWR_BackupAccessCmd(ENABLE) function before to configure\r
+ * the RTC clock source (to be done once after reset). \r
+ * @note Once the RTC clock is configured it can't be changed unless the \r
+ * Backup domain is reset using RCC_BackupResetCmd() function, or by\r
+ * a Power On Reset (POR).\r
+ * \r
+ * @param RCC_RTCCLKSource: specifies the RTC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected\r
+ * as RTC clock, where x:[2,31]\r
+ * \r
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to\r
+ * work in STOP and STANDBY modes, and can be used as wakeup source.\r
+ * However, when the HSE clock is used as RTC clock source, the RTC\r
+ * cannot be used in STOP and STANDBY modes. \r
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
+ * RTC clock source).\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
+\r
+ if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)\r
+ { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear RTCPRE[4:0] bits */\r
+ tmpreg &= ~RCC_CFGR_RTCPRE;\r
+\r
+ /* Configure HSE division factor for RTC clock */\r
+ tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+ }\r
+ \r
+ /* Select the RTC clock source */\r
+ RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC clock.\r
+ * @note This function must be used only after the RTC clock source was selected\r
+ * using the RCC_RTCCLKConfig function.\r
+ * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases the Backup domain reset.\r
+ * @note This function resets the RTC peripheral (including the backup registers)\r
+ * and the RTC clock source selection in RCC_CSR register.\r
+ * @note The BKPSRAM is not affected by this reset. \r
+ * @param NewState: new state of the Backup domain reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_BackupResetCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the I2S clock source (I2SCLK).\r
+ * @note This function must be called before enabling the I2S APB clock.\r
+ * @param RCC_I2SCLKSource: specifies the I2S clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source\r
+ * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin\r
+ * used as I2S clock source\r
+ * @retval None\r
+ */\r
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));\r
+\r
+ *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHB1Periph_GPIOA: GPIOA clock\r
+ * @arg RCC_AHB1Periph_GPIOB: GPIOB clock \r
+ * @arg RCC_AHB1Periph_GPIOC: GPIOC clock\r
+ * @arg RCC_AHB1Periph_GPIOD: GPIOD clock\r
+ * @arg RCC_AHB1Periph_GPIOE: GPIOE clock\r
+ * @arg RCC_AHB1Periph_GPIOF: GPIOF clock\r
+ * @arg RCC_AHB1Periph_GPIOG: GPIOG clock\r
+ * @arg RCC_AHB1Periph_GPIOG: GPIOG clock\r
+ * @arg RCC_AHB1Periph_GPIOI: GPIOI clock\r
+ * @arg RCC_AHB1Periph_CRC: CRC clock\r
+ * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock\r
+ * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock\r
+ * @arg RCC_AHB1Periph_DMA1: DMA1 clock\r
+ * @arg RCC_AHB1Periph_DMA2: DMA2 clock\r
+ * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock\r
+ * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock\r
+ * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock\r
+ * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock\r
+ * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock\r
+ * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));\r
+\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHB1ENR |= RCC_AHB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHB1ENR &= ~RCC_AHB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHB2Periph_DCMI: DCMI clock\r
+ * @arg RCC_AHB2Periph_CRYP: CRYP clock\r
+ * @arg RCC_AHB2Periph_HASH: HASH clock\r
+ * @arg RCC_AHB2Periph_RNG: RNG clock\r
+ * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHB2ENR |= RCC_AHB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHB2ENR &= ~RCC_AHB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB3 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.\r
+ * This parameter must be: RCC_AHB3Periph_FSMC\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHB3ENR |= RCC_AHB3Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHB3ENR &= ~RCC_AHB3Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2: TIM2 clock\r
+ * @arg RCC_APB1Periph_TIM3: TIM3 clock\r
+ * @arg RCC_APB1Periph_TIM4: TIM4 clock\r
+ * @arg RCC_APB1Periph_TIM5: TIM5 clock\r
+ * @arg RCC_APB1Periph_TIM6: TIM6 clock\r
+ * @arg RCC_APB1Periph_TIM7: TIM7 clock\r
+ * @arg RCC_APB1Periph_TIM12: TIM12 clock\r
+ * @arg RCC_APB1Periph_TIM13: TIM13 clock\r
+ * @arg RCC_APB1Periph_TIM14: TIM14 clock\r
+ * @arg RCC_APB1Periph_WWDG: WWDG clock\r
+ * @arg RCC_APB1Periph_SPI2: SPI2 clock\r
+ * @arg RCC_APB1Periph_SPI3: SPI3 clock\r
+ * @arg RCC_APB1Periph_USART2: USART2 clock\r
+ * @arg RCC_APB1Periph_USART3: USART3 clock\r
+ * @arg RCC_APB1Periph_UART4: UART4 clock\r
+ * @arg RCC_APB1Periph_UART5: UART5 clock\r
+ * @arg RCC_APB1Periph_I2C1: I2C1 clock\r
+ * @arg RCC_APB1Periph_I2C2: I2C2 clock\r
+ * @arg RCC_APB1Periph_I2C3: I2C3 clock\r
+ * @arg RCC_APB1Periph_CAN1: CAN1 clock\r
+ * @arg RCC_APB1Periph_CAN2: CAN2 clock\r
+ * @arg RCC_APB1Periph_PWR: PWR clock\r
+ * @arg RCC_APB1Periph_DAC: DAC clock\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1ENR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1ENR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_TIM1: TIM1 clock\r
+ * @arg RCC_APB2Periph_TIM8: TIM8 clock\r
+ * @arg RCC_APB2Periph_USART1: USART1 clock\r
+ * @arg RCC_APB2Periph_USART6: USART6 clock\r
+ * @arg RCC_APB2Periph_ADC1: ADC1 clock\r
+ * @arg RCC_APB2Periph_ADC2: ADC2 clock\r
+ * @arg RCC_APB2Periph_ADC3: ADC3 clock\r
+ * @arg RCC_APB2Periph_SDIO: SDIO clock\r
+ * @arg RCC_APB2Periph_SPI1: SPI1 clock\r
+ * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock\r
+ * @arg RCC_APB2Periph_TIM9: TIM9 clock\r
+ * @arg RCC_APB2Periph_TIM10: TIM10 clock\r
+ * @arg RCC_APB2Periph_TIM11: TIM11 clock\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2ENR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2ENR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases AHB1 peripheral reset.\r
+ * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHB1Periph_GPIOA: GPIOA clock\r
+ * @arg RCC_AHB1Periph_GPIOB: GPIOB clock \r
+ * @arg RCC_AHB1Periph_GPIOC: GPIOC clock\r
+ * @arg RCC_AHB1Periph_GPIOD: GPIOD clock\r
+ * @arg RCC_AHB1Periph_GPIOE: GPIOE clock\r
+ * @arg RCC_AHB1Periph_GPIOF: GPIOF clock\r
+ * @arg RCC_AHB1Periph_GPIOG: GPIOG clock\r
+ * @arg RCC_AHB1Periph_GPIOG: GPIOG clock\r
+ * @arg RCC_AHB1Periph_GPIOI: GPIOI clock\r
+ * @arg RCC_AHB1Periph_CRC: CRC clock\r
+ * @arg RCC_AHB1Periph_DMA1: DMA1 clock\r
+ * @arg RCC_AHB1Periph_DMA2: DMA2 clock\r
+ * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock\r
+ * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock\r
+ * \r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHB1RSTR |= RCC_AHB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHB1RSTR &= ~RCC_AHB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases AHB2 peripheral reset.\r
+ * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHB2Periph_DCMI: DCMI clock\r
+ * @arg RCC_AHB2Periph_CRYP: CRYP clock\r
+ * @arg RCC_AHB2Periph_HASH: HASH clock\r
+ * @arg RCC_AHB2Periph_RNG: RNG clock\r
+ * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock\r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHB2RSTR |= RCC_AHB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHB2RSTR &= ~RCC_AHB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases AHB3 peripheral reset.\r
+ * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.\r
+ * This parameter must be: RCC_AHB3Periph_FSMC\r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHB3RSTR |= RCC_AHB3Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHB3RSTR &= ~RCC_AHB3Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2: TIM2 clock\r
+ * @arg RCC_APB1Periph_TIM3: TIM3 clock\r
+ * @arg RCC_APB1Periph_TIM4: TIM4 clock\r
+ * @arg RCC_APB1Periph_TIM5: TIM5 clock\r
+ * @arg RCC_APB1Periph_TIM6: TIM6 clock\r
+ * @arg RCC_APB1Periph_TIM7: TIM7 clock\r
+ * @arg RCC_APB1Periph_TIM12: TIM12 clock\r
+ * @arg RCC_APB1Periph_TIM13: TIM13 clock\r
+ * @arg RCC_APB1Periph_TIM14: TIM14 clock\r
+ * @arg RCC_APB1Periph_WWDG: WWDG clock\r
+ * @arg RCC_APB1Periph_SPI2: SPI2 clock\r
+ * @arg RCC_APB1Periph_SPI3: SPI3 clock\r
+ * @arg RCC_APB1Periph_USART2: USART2 clock\r
+ * @arg RCC_APB1Periph_USART3: USART3 clock\r
+ * @arg RCC_APB1Periph_UART4: UART4 clock\r
+ * @arg RCC_APB1Periph_UART5: UART5 clock\r
+ * @arg RCC_APB1Periph_I2C1: I2C1 clock\r
+ * @arg RCC_APB1Periph_I2C2: I2C2 clock\r
+ * @arg RCC_APB1Periph_I2C3: I2C3 clock\r
+ * @arg RCC_APB1Periph_CAN1: CAN1 clock\r
+ * @arg RCC_APB1Periph_CAN2: CAN2 clock\r
+ * @arg RCC_APB1Periph_PWR: PWR clock\r
+ * @arg RCC_APB1Periph_DAC: DAC clock\r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1RSTR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1RSTR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_TIM1: TIM1 clock\r
+ * @arg RCC_APB2Periph_TIM8: TIM8 clock\r
+ * @arg RCC_APB2Periph_USART1: USART1 clock\r
+ * @arg RCC_APB2Periph_USART6: USART6 clock\r
+ * @arg RCC_APB2Periph_ADC1: ADC1 clock\r
+ * @arg RCC_APB2Periph_ADC2: ADC2 clock\r
+ * @arg RCC_APB2Periph_ADC3: ADC3 clock\r
+ * @arg RCC_APB2Periph_SDIO: SDIO clock\r
+ * @arg RCC_APB2Periph_SPI1: SPI1 clock\r
+ * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock\r
+ * @arg RCC_APB2Periph_TIM9: TIM9 clock\r
+ * @arg RCC_APB2Periph_TIM10: TIM10 clock\r
+ * @arg RCC_APB2Periph_TIM11: TIM11 clock\r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2RSTR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2RSTR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHB1Periph_GPIOA: GPIOA clock\r
+ * @arg RCC_AHB1Periph_GPIOB: GPIOB clock \r
+ * @arg RCC_AHB1Periph_GPIOC: GPIOC clock\r
+ * @arg RCC_AHB1Periph_GPIOD: GPIOD clock\r
+ * @arg RCC_AHB1Periph_GPIOE: GPIOE clock\r
+ * @arg RCC_AHB1Periph_GPIOF: GPIOF clock\r
+ * @arg RCC_AHB1Periph_GPIOG: GPIOG clock\r
+ * @arg RCC_AHB1Periph_GPIOG: GPIOG clock\r
+ * @arg RCC_AHB1Periph_GPIOI: GPIOI clock\r
+ * @arg RCC_AHB1Periph_CRC: CRC clock\r
+ * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock\r
+ * @arg RCC_AHB1Periph_DMA1: DMA1 clock\r
+ * @arg RCC_AHB1Periph_DMA2: DMA2 clock\r
+ * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock\r
+ * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock\r
+ * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock\r
+ * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock\r
+ * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock\r
+ * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHB1LPENR |= RCC_AHB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHB1LPENR &= ~RCC_AHB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHB2Periph_DCMI: DCMI clock\r
+ * @arg RCC_AHB2Periph_CRYP: CRYP clock\r
+ * @arg RCC_AHB2Periph_HASH: HASH clock\r
+ * @arg RCC_AHB2Periph_RNG: RNG clock\r
+ * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHB2LPENR |= RCC_AHB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHB2LPENR &= ~RCC_AHB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.\r
+ * This parameter must be: RCC_AHB3Periph_FSMC\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHB3LPENR |= RCC_AHB3Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHB3LPENR &= ~RCC_AHB3Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2: TIM2 clock\r
+ * @arg RCC_APB1Periph_TIM3: TIM3 clock\r
+ * @arg RCC_APB1Periph_TIM4: TIM4 clock\r
+ * @arg RCC_APB1Periph_TIM5: TIM5 clock\r
+ * @arg RCC_APB1Periph_TIM6: TIM6 clock\r
+ * @arg RCC_APB1Periph_TIM7: TIM7 clock\r
+ * @arg RCC_APB1Periph_TIM12: TIM12 clock\r
+ * @arg RCC_APB1Periph_TIM13: TIM13 clock\r
+ * @arg RCC_APB1Periph_TIM14: TIM14 clock\r
+ * @arg RCC_APB1Periph_WWDG: WWDG clock\r
+ * @arg RCC_APB1Periph_SPI2: SPI2 clock\r
+ * @arg RCC_APB1Periph_SPI3: SPI3 clock\r
+ * @arg RCC_APB1Periph_USART2: USART2 clock\r
+ * @arg RCC_APB1Periph_USART3: USART3 clock\r
+ * @arg RCC_APB1Periph_UART4: UART4 clock\r
+ * @arg RCC_APB1Periph_UART5: UART5 clock\r
+ * @arg RCC_APB1Periph_I2C1: I2C1 clock\r
+ * @arg RCC_APB1Periph_I2C2: I2C2 clock\r
+ * @arg RCC_APB1Periph_I2C3: I2C3 clock\r
+ * @arg RCC_APB1Periph_CAN1: CAN1 clock\r
+ * @arg RCC_APB1Periph_CAN2: CAN2 clock\r
+ * @arg RCC_APB1Periph_PWR: PWR clock\r
+ * @arg RCC_APB1Periph_DAC: DAC clock\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1LPENR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1LPENR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_TIM1: TIM1 clock\r
+ * @arg RCC_APB2Periph_TIM8: TIM8 clock\r
+ * @arg RCC_APB2Periph_USART1: USART1 clock\r
+ * @arg RCC_APB2Periph_USART6: USART6 clock\r
+ * @arg RCC_APB2Periph_ADC1: ADC1 clock\r
+ * @arg RCC_APB2Periph_ADC2: ADC2 clock\r
+ * @arg RCC_APB2Periph_ADC3: ADC3 clock\r
+ * @arg RCC_APB2Periph_SDIO: SDIO clock\r
+ * @arg RCC_APB2Periph_SPI1: SPI1 clock\r
+ * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock\r
+ * @arg RCC_APB2Periph_TIM9: TIM9 clock\r
+ * @arg RCC_APB2Periph_TIM10: TIM10 clock\r
+ * @arg RCC_APB2Periph_TIM11: TIM11 clock\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2LPENR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2LPENR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group4 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified RCC interrupts.\r
+ * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt\r
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt \r
+ * @param NewState: new state of the specified RCC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_IT(RCC_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC flag is set or not.\r
+ * @param RCC_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+ * @arg RCC_FLAG_PLLRDY: main PLL clock ready\r
+ * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready\r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+ * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset\r
+ * @arg RCC_FLAG_PINRST: Pin reset\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset\r
+ * @arg RCC_FLAG_SFTRST: Software reset\r
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
+ * @arg RCC_FLAG_LPWRRST: Low Power reset\r
+ * @retval The new state of RCC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint32_t statusreg = 0;\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_FLAG(RCC_FLAG));\r
+\r
+ /* Get the RCC register index */\r
+ tmp = RCC_FLAG >> 5;\r
+ if (tmp == 1) /* The flag to check is in CR register */\r
+ {\r
+ statusreg = RCC->CR;\r
+ }\r
+ else if (tmp == 2) /* The flag to check is in BDCR register */\r
+ {\r
+ statusreg = RCC->BDCR;\r
+ }\r
+ else /* The flag to check is in CSR register */\r
+ {\r
+ statusreg = RCC->CSR;\r
+ }\r
+\r
+ /* Get the flag position */\r
+ tmp = RCC_FLAG & FLAG_MASK;\r
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC reset flags.\r
+ * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,\r
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_ClearFlag(void)\r
+{\r
+ /* Set RMVF bit to clear the reset flags */\r
+ RCC->CSR |= RCC_CSR_RMVF;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC interrupt has occurred or not.\r
+ * @param RCC_IT: specifies the RCC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt\r
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval The new state of RCC_IT (SET or RESET).\r
+ */\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_GET_IT(RCC_IT));\r
+\r
+ /* Check the status of the specified RCC interrupt */\r
+ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the RCC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC's interrupt pending bits.\r
+ * @param RCC_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt\r
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval None\r
+ */\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r
+\r
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
+ pending bits */\r
+ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_syscfg.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file provides firmware functions to manage the SYSCFG peripheral.\r
+ *\r
+ * @verbatim\r
+ * \r
+ * ===================================================================\r
+ * How to use this driver\r
+ * ===================================================================\r
+ * \r
+ * This driver provides functions for:\r
+ * \r
+ * 1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()\r
+ * \r
+ * 2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()\r
+ * \r
+ * 3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()\r
+ *\r
+ * @note SYSCFG APB clock must be enabled to get write access to SYSCFG registers,\r
+ * using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx_syscfg.h"\r
+#include "stm32f4xx_rcc.h"\r
+\r
+/** @addtogroup STM32F4xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SYSCFG \r
+ * @brief SYSCFG driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ------------ RCC registers bit address in the alias region ----------- */\r
+#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)\r
+/* --- PMC Register ---*/ \r
+/* Alias word address of MII_RMII_SEL bit */ \r
+#define PMC_OFFSET (SYSCFG_OFFSET + 0x04) \r
+#define MII_RMII_SEL_BitNumber ((uint8_t)0x17) \r
+#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) \r
+\r
+/* --- CMPCR Register ---*/ \r
+/* Alias word address of CMP_PD bit */ \r
+#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) \r
+#define CMP_PD_BitNumber ((uint8_t)0x00) \r
+#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) \r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SYSCFG_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Deinitializes the Alternate Functions (remap and EXTI configuration)\r
+ * registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SYSCFG_DeInit(void)\r
+{\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Changes the mapping of the specified pin.\r
+ * @param SYSCFG_Memory: selects the memory remapping.\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 \r
+ * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000\r
+ * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000\r
+ * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000\r
+ * @retval None\r
+ */\r
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));\r
+\r
+ SYSCFG->MEMRMP = SYSCFG_MemoryRemap;\r
+}\r
+\r
+/**\r
+ * @brief Selects the GPIO pin used as EXTI Line.\r
+ * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for\r
+ * EXTI lines where x can be (A..I).\r
+ * @param EXTI_PinSourcex: specifies the EXTI line to be configured.\r
+ * This parameter can be EXTI_PinSourcex where x can be (0..15, except\r
+ * for EXTI_PortSourceGPIOI x can be (0..11).\r
+ * @retval None\r
+ */\r
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)\r
+{\r
+ uint32_t tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));\r
+ assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));\r
+\r
+ tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));\r
+ SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;\r
+ SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));\r
+}\r
+\r
+/**\r
+ * @brief Selects the ETHERNET media interface \r
+ * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. \r
+ * This parameter can be one of the following values: \r
+ * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected\r
+ * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected \r
+ * @retval None \r
+ */\r
+void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) \r
+{ \r
+ assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); \r
+ /* Configure MII_RMII selection bit */ \r
+ *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the I/O Compensation Cell.\r
+ * @note The I/O compensation cell can be used only when the device supply\r
+ * voltage ranges from 2.4 to 3.6 V. \r
+ * @param NewState: new state of the I/O Compensation Cell.\r
+ * This parameter can be one of the following values:\r
+ * @arg ENABLE: I/O compensation cell enabled \r
+ * @arg DISABLE: I/O compensation cell power-down mode \r
+ * @retval None\r
+ */\r
+void SYSCFG_CompensationCellCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the I/O Compensation Cell ready flag is set or not.\r
+ * @param None\r
+ * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)\r
+ */\r
+FlagStatus SYSCFG_GetCompensationCellStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ \r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple GPIO (parallel port) IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Standard demo include. */\r
+#include "partest.h"\r
+\r
+/* Starter kit includes. */\r
+#include "iar_stm32f407zg_sk.h"\r
+\r
+/* Only the LEDs on one of the two seven segment displays are used. */\r
+#define partstMAX_LEDS 4\r
+\r
+static const Led_TypeDef xLEDs[ partstMAX_LEDS ] = { LED1, LED2, LED3, LED4 };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Initialise all four LEDs that are built onto the starter kit. */\r
+ STM_EVAL_LEDInit( LED1 );\r
+ STM_EVAL_LEDInit( LED2 );\r
+ STM_EVAL_LEDInit( LED3 );\r
+ STM_EVAL_LEDInit( LED4 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned long ulLED, signed portBASE_TYPE xValue )\r
+{\r
+ if( ulLED < partstMAX_LEDS )\r
+ {\r
+ if( xValue == pdTRUE )\r
+ {\r
+ STM_EVAL_LEDOn( xLEDs[ ulLED ] );\r
+ }\r
+ else\r
+ {\r
+ STM_EVAL_LEDOff( xLEDs[ ulLED ] );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned long ulLED )\r
+{\r
+ if( ulLED < partstMAX_LEDS )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ STM_EVAL_LEDToggle( xLEDs[ ulLED ] );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Flash Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>23</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\iostm32f4xxx.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>5.30.0.51236</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>JLINK_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>6.30.3.53229</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CLowLevel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCBE8Slave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CDevice</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoadersV3</name>\r
+ <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F4xxx.board</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OverrideDefFlashBoard</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDeviceConfigMacroFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimEnablePSP</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspOverrideConfig</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspConfigFile</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>GDBSERVER_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>14</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadioV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCUSBDevice</name>\r
+ <version>1</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceRadio</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetList</name>\r
+ <version>6</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>120.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSourceDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>#UNINITIALIZED#</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>Browse to your RDI driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDIJTAGJET_ID</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JTAGjetConfigure</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>STLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>120.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>Browse to your third-party driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XDS100_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCXDS100AttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Flash Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>21</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Flash Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Flash Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Flash Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>19</version>\r
+ <state>38</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>3</version>\r
+ <state>6</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>2</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No specifier a, A.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>2</version>\r
+ <state>5</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>4.41A</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>6.30.3.53229</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>STM32F4xxx ST STM32F4xxx</state>\r
+ </option>\r
+ <option>\r
+ <name>GenLowLevelInterface</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianModeBE</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGBufferedTerminalOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenStdoutInterface</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules04</name>\r
+ <version>0</version>\r
+ <state>011111111111111110111111111111011111111111111011110100111111111111111111111111111111111111111111101111111111111011111111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>19</version>\r
+ <state>38</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>19</version>\r
+ <state>38</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>28</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state>USE_STDPERIPH_DRIVER</state>\r
+ <state>STM32F4XX</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state>Pa082</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>1</version>\r
+ <state>0000000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IEndianMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangConformance</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSignedPlainChar</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
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+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\stm32f4xx_it.c</name>\r
+ </file>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+ </project>\r
+ <batchBuild>\r
+ <batchDefinition>\r
+ <name>All</name>\r
+ <member>\r
+ <project>RTOSDemo</project>\r
+ <configuration>Flash Debug</configuration>\r
+ </member>\r
+ </batchDefinition>\r
+ </batchBuild>\r
+</workspace>\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#include <FreeRTOSConfig.h>\r
+\r
+\r
+ RSEG CODE:CODE(2)\r
+ thumb\r
+\r
+ EXTERN ulRegTest1LoopCounter\r
+ EXTERN ulRegTest2LoopCounter\r
+\r
+ PUBLIC vRegTest1Task\r
+ PUBLIC vRegTest2Task\r
+ PUBLIC vRegTestClearFlopRegistersToParameterValue\r
+ PUBLIC ulRegTestCheckFlopRegistersContainParameterValue\r
+ \r
+/*-----------------------------------------------------------*/\r
+\r
+vRegTest1Task\r
+\r
+ /* Fill the core registers with known values. */\r
+ mov r0, #100\r
+ mov r1, #101\r
+ mov r2, #102\r
+ mov r3, #103\r
+ mov r4, #104\r
+ mov r5, #105\r
+ mov r6, #106\r
+ mov r7, #107\r
+ mov r8, #108\r
+ mov r9, #109\r
+ mov r10, #110\r
+ mov r11, #111\r
+ mov r12, #112\r
+\r
+ /* Fill the VFP registers with known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg1_loop:\r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+ \r
+ vmov r0, r1, d0\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ \r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+ \r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg1_loopf_pass\r
+\r
+reg1_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg1_error_loopf\r
+\r
+reg1_loopf_pass\r
+\r
+ cmp r0, #100\r
+ bne reg1_error_loop\r
+ cmp r1, #101\r
+ bne reg1_error_loop\r
+ cmp r2, #102\r
+ bne reg1_error_loop\r
+ cmp r3, #103\r
+ bne reg1_error_loop\r
+ cmp r4, #104\r
+ bne reg1_error_loop\r
+ cmp r5, #105\r
+ bne reg1_error_loop\r
+ cmp r6, #106\r
+ bne reg1_error_loop\r
+ cmp r7, #107\r
+ bne reg1_error_loop\r
+ cmp r8, #108\r
+ bne reg1_error_loop\r
+ cmp r9, #109\r
+ bne reg1_error_loop\r
+ cmp r10, #110\r
+ bne reg1_error_loop\r
+ cmp r11, #111\r
+ bne reg1_error_loop\r
+ cmp r12, #112\r
+ bne reg1_error_loop\r
+ \r
+ /* Everything passed, increment the loop counter. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest1LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+ \r
+ /* Start again. */\r
+ b reg1_loop\r
+\r
+reg1_error_loop:\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ b reg1_error_loop\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+vRegTest2Task\r
+\r
+ /* Set all the core registers to known values. */\r
+ mov r0, #-1\r
+ mov r1, #1\r
+ mov r2, #2\r
+ mov r3, #3\r
+ mov r4, #4\r
+ mov r5, #5\r
+ mov r6, #6\r
+ mov r7, #7\r
+ mov r8, #8\r
+ mov r9, #9\r
+ mov r10, #10\r
+ mov r11, #11\r
+ mov r12, #12\r
+\r
+ /* Set all the VFP to known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg2_loop:\r
+ \r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+ \r
+ vmov r0, r1, d0\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ \r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+ \r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg2_loopf_pass\r
+\r
+reg2_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg2_error_loopf\r
+\r
+reg2_loopf_pass\r
+\r
+ cmp r0, #-1\r
+ bne reg2_error_loop\r
+ cmp r1, #1\r
+ bne reg2_error_loop\r
+ cmp r2, #2\r
+ bne reg2_error_loop\r
+ cmp r3, #3\r
+ bne reg2_error_loop\r
+ cmp r4, #4\r
+ bne reg2_error_loop\r
+ cmp r5, #5\r
+ bne reg2_error_loop\r
+ cmp r6, #6\r
+ bne reg2_error_loop\r
+ cmp r7, #7\r
+ bne reg2_error_loop\r
+ cmp r8, #8\r
+ bne reg2_error_loop\r
+ cmp r9, #9\r
+ bne reg2_error_loop\r
+ cmp r10, #10\r
+ bne reg2_error_loop\r
+ cmp r11, #11\r
+ bne reg2_error_loop\r
+ cmp r12, #12\r
+ bne reg2_error_loop\r
+ \r
+ /* Increment the loop counter to indicate this test is still functioning\r
+ correctly. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest2LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+ \r
+ /* Start again. */\r
+ b reg2_loop\r
+\r
+reg2_error_loop:\r
+ /* If this line is hit then there was an error in a core register value.\r
+ This loop ensures the loop counter variable stops incrementing. */\r
+ b reg2_error_loop\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+vRegTestClearFlopRegistersToParameterValue\r
+\r
+ /* Clobber the auto saved registers. */\r
+ vmov d0, r0, r0\r
+ vmov d1, r0, r0\r
+ vmov d2, r0, r0\r
+ vmov d3, r0, r0\r
+ vmov d4, r0, r0\r
+ vmov d5, r0, r0\r
+ vmov d6, r0, r0\r
+ vmov d7, r0, r0\r
+ bx lr\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ulRegTestCheckFlopRegistersContainParameterValue\r
+\r
+ vmov r1, s0\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s1\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s2\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s3\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s4\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s5\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s6\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s7\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s8\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s9\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s10\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s11\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s12\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s13\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s14\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s15\r
+ cmp r0, r1\r
+ bne return_error\r
+ \r
+return_pass\r
+ mov r0, #1\r
+ bx lr\r
+\r
+return_error\r
+ mov r0, #0\r
+ bx lr\r
+\r
+ END\r
+ \r
--- /dev/null
+/***************************************************************************\r
+ **\r
+ ** Common definition for IAR EW ARM\r
+ **\r
+ ** Used with ARM IAR C/C++ Compiler and Assembler.\r
+ **\r
+ ** (c) Copyright IAR Systems 2006\r
+ **\r
+ ** $Revision: 48478 $\r
+ **\r
+ ***************************************************************************/\r
+#include <intrinsics.h>\r
+\r
+#ifndef __ARM_COMM_DEF_H\r
+#define __ARM_COMM_DEF_H\r
+\r
+#define MHZ *1000000l\r
+#define KHZ *1000l\r
+#define HZ *1l\r
+\r
+#ifndef FALSE\r
+#define FALSE (1 == 0)\r
+#endif\r
+\r
+#ifndef TRUE\r
+#define TRUE (1 == 1)\r
+#endif\r
+\r
+#ifndef NULL\r
+#define NULL ((void*)0)\r
+#endif\r
+\r
+typedef double Flo64; // Double precision floating point\r
+typedef double * pFlo64;\r
+typedef float Flo32; // Single precision floating point\r
+typedef float * pFlo32;\r
+typedef signed long long Int64S; // Signed 64 bit quantity\r
+typedef signed long long * pInt64S;\r
+typedef unsigned long long Int64U; // Unsigned 64 bit quantity\r
+typedef unsigned long long * pInt64U;\r
+typedef signed int Int32S; // Signed 32 bit quantity\r
+typedef signed int * pInt32S;\r
+typedef unsigned int Int32U; // Unsigned 32 bit quantity\r
+typedef unsigned int * pInt32U;\r
+typedef signed short Int16S; // Signed 16 bit quantity\r
+typedef signed short * pInt16S;\r
+typedef unsigned short Int16U; // Unsigned 16 bit quantity\r
+typedef unsigned short * pInt16U;\r
+typedef signed char Int8S; // Signed 8 bit quantity\r
+typedef signed char * pInt8S;\r
+typedef unsigned char Int8U; // Unsigned 8 bit quantity\r
+typedef unsigned char * pInt8U;\r
+typedef unsigned int Boolean; // Boolean\r
+typedef unsigned int * pBoolean;\r
+\r
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))\r
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))\r
+#define _2BL(a) (Int8U)(a),(Int8U)(a>>8)\r
+#define _2BB(a) (Int8U)(a>>8),(Int8U)(a),\r
+#define _3BL(a) (Int8U)(a),(Int8U)(a>>8),(Int8U)(a>>16)\r
+#define _3BB(a) (Int8U)(a>>16),(Int8U)(a>>8),(Int8U)(a)\r
+#define _4BL(a) (Int8U)(a),(Int8U)(a>>8),(Int8U)(a>>16),(Int8U)(a>>24)\r
+#define _4BB(a) (Int8U)(a>>24),(Int8U)(a>>16),(Int8U)(a>>8),(Int8U)(a)\r
+\r
+typedef void * (*CommUserFpnt_t)(void *);\r
+typedef void (*VoidFpnt_t)(void);\r
+\r
+// Atomic exchange of data between a memory cell and a register\r
+// return value of the memory cell\r
+#if __CORE__ < 7\r
+inline __arm Int32U AtomicExchange (Int32U State, pInt32U Flag)\r
+{\r
+ asm("swp r0, r0, [r1]");\r
+ return(State);\r
+}\r
+\r
+#define IRQ_FLAG 0x80\r
+#define FIQ_FLAG 0x40\r
+\r
+inline __arm Int32U EntrCritSection(void)\r
+{\r
+unsigned long tmp;\r
+ tmp = __get_CPSR();\r
+ __set_CPSR(tmp | IRQ_FLAG);\r
+ return(tmp);\r
+}\r
+\r
+inline __arm void ExtCritSection(Int32U Save)\r
+{\r
+unsigned long tmp;\r
+ tmp = __get_CPSR();\r
+ __set_CPSR(tmp & (Save | ~IRQ_FLAG));\r
+}\r
+\r
+inline __arm Int32U EntrCritSectionFiq(void)\r
+{\r
+unsigned long tmp;\r
+ tmp = __get_CPSR();\r
+ __set_CPSR(tmp | (IRQ_FLAG | FIQ_FLAG));\r
+ return(tmp);\r
+}\r
+\r
+inline __arm void ExtCritSectionFiq(Int32U Save)\r
+{\r
+unsigned long tmp;\r
+ tmp = __get_CPSR();\r
+ __set_CPSR(tmp & (Save | ~(IRQ_FLAG | FIQ_FLAG)));\r
+}\r
+\r
+#define ENTR_CRT_SECTION(Save) Save = EntrCritSection()\r
+#define EXT_CRT_SECTION(Save) ExtCritSection(Save)\r
+\r
+#define ENTR_CRT_SECTION_F(Save) Save = EntrCritSectionFiq()\r
+#define EXT_CRT_SECTION_F(Save) ExtCritSectionFiq(Save)\r
+\r
+#elif ((__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__) || (__CORE__ == __ARM7M__) || (__CORE__ == __ARM7EM__))\r
+\r
+extern Int32U CriticalSecCntr;\r
+\r
+inline void EntrCritSection(void)\r
+{\r
+ if(CriticalSecCntr == 0)\r
+ {\r
+ asm("CPSID i");\r
+ }\r
+ // avoid lost of one count in case of simultaneously calling from both places\r
+ ++CriticalSecCntr;\r
+}\r
+\r
+inline void ExtCritSection(void)\r
+{\r
+ if(--CriticalSecCntr == 0)\r
+ {\r
+ asm("CPSIE i");\r
+ }\r
+}\r
+\r
+inline Int32U AtomicExchange (Int32U State, pInt32U Flag)\r
+{\r
+Int32U Hold;\r
+ EntrCritSection();\r
+ Hold = *Flag;\r
+ *Flag = State;\r
+ ExtCritSection();\r
+ return(Hold);\r
+}\r
+\r
+#define ENTR_CRT_SECTION() EntrCritSection()\r
+#define EXT_CRT_SECTION() ExtCritSection()\r
+#endif\r
+\r
+#define LongToBin(n) (((n >> 21) & 0x80) | \\r
+ ((n >> 18) & 0x40) | \\r
+ ((n >> 15) & 0x20) | \\r
+ ((n >> 12) & 0x10) | \\r
+ ((n >> 9) & 0x08) | \\r
+ ((n >> 6) & 0x04) | \\r
+ ((n >> 3) & 0x02) | \\r
+ ((n ) & 0x01))\r
+\r
+#define __BIN(n) LongToBin(0x##n##l)\r
+\r
+#define BIN8(n) __BIN(n)\r
+#define BIN(n) __BIN(n)\r
+#define BIN16(b1,b2) (( __BIN(b1) << 8UL) + \\r
+ __BIN(b2))\r
+#define BIN32(b1,b2,b3,b4) ((((Int32U)__BIN(b1)) << 24UL) + \\r
+ (((Int32U)__BIN(b2)) << 16UL) + \\r
+ (((Int32U)__BIN(b3)) << 8UL) + \\r
+ (Int32U)__BIN(b4))\r
+\r
+#endif // __ARM_COMM_DEF_H\r
--- /dev/null
+/**/\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "iar_stm32f407zg_sk.h"\r
+\r
+/** \r
+ * @{\r
+ */ \r
+GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,\r
+ LED4_GPIO_PORT};\r
+const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,\r
+ LED4_PIN};\r
+const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,\r
+ LED4_GPIO_CLK};\r
+\r
+GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,\r
+ USER_BUTTON_GPIO_PORT,RIGHT_BUTTON_GPIO_PORT, LEFT_BUTTON_GPIO_PORT,\r
+ UP_BUTTON_GPIO_PORT,DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; \r
+\r
+const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,\r
+ USER_BUTTON_PIN,RIGHT_BUTTON_PIN, LEFT_BUTTON_PIN,\r
+ UP_BUTTON_PIN,DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; \r
+\r
+const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,\r
+ USER_BUTTON_GPIO_CLK,RIGHT_BUTTON_GPIO_CLK, LEFT_BUTTON_GPIO_CLK,\r
+ UP_BUTTON_GPIO_CLK,DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};\r
+\r
+const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,\r
+ TAMPER_BUTTON_EXTI_LINE, \r
+ USER_BUTTON_EXTI_LINE,\r
+ RIGHT_BUTTON_EXTI_LINE,\r
+ LEFT_BUTTON_EXTI_LINE, \r
+ UP_BUTTON_EXTI_LINE,\r
+ DOWN_BUTTON_EXTI_LINE,\r
+ SEL_BUTTON_EXTI_LINE};\r
+\r
+const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,\r
+ TAMPER_BUTTON_EXTI_PORT_SOURCE, \r
+ USER_BUTTON_EXTI_PORT_SOURCE,\r
+ RIGHT_BUTTON_EXTI_PORT_SOURCE,\r
+ LEFT_BUTTON_EXTI_PORT_SOURCE, \r
+ UP_BUTTON_EXTI_PORT_SOURCE,\r
+ DOWN_BUTTON_EXTI_PORT_SOURCE,\r
+ SEL_BUTTON_EXTI_PORT_SOURCE};\r
+ \r
+const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,\r
+ TAMPER_BUTTON_EXTI_PIN_SOURCE, \r
+ USER_BUTTON_EXTI_PIN_SOURCE,\r
+ RIGHT_BUTTON_EXTI_PIN_SOURCE,\r
+ LEFT_BUTTON_EXTI_PIN_SOURCE, \r
+ UP_BUTTON_EXTI_PIN_SOURCE,\r
+ DOWN_BUTTON_EXTI_PIN_SOURCE,\r
+ SEL_BUTTON_EXTI_PIN_SOURCE}; \r
+const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,\r
+ USER_BUTTON_EXTI_IRQn,RIGHT_BUTTON_EXTI_IRQn,\r
+ LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,\r
+ DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};\r
+\r
+USART_TypeDef* COM_USART[COMn] = {EVAL_COM1,EVAL_COM2}; \r
+\r
+GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};\r
+ \r
+GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT,EVAL_COM2_RX_GPIO_PORT};\r
+\r
+const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK,EVAL_COM2_CLK};\r
+\r
+const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK,EVAL_COM2_TX_GPIO_CLK};\r
+ \r
+const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};\r
+\r
+const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};\r
+\r
+const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};\r
+ \r
+const uint16_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE, EVAL_COM2_TX_SOURCE};\r
+\r
+const uint16_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE, EVAL_COM1_RX_SOURCE};\r
+ \r
+const uint16_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF, EVAL_COM2_TX_AF};\r
+ \r
+const uint16_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF, EVAL_COM2_RX_AF};\r
+\r
+NVIC_InitTypeDef NVIC_InitStructure;\r
+\r
+/**\r
+ * @}\r
+ */ \r
+void STM_EVAL_GPIOReset(void)\r
+{\r
+ GPIO_DeInit(GPIOA);\r
+ GPIO_DeInit(GPIOB);\r
+ GPIO_DeInit(GPIOC);\r
+ GPIO_DeInit(GPIOD);\r
+ GPIO_DeInit(GPIOE);\r
+ GPIO_DeInit(GPIOF);\r
+ GPIO_DeInit(GPIOG);\r
+ GPIO_DeInit(GPIOH);\r
+ GPIO_DeInit(GPIOI);\r
+}\r
+/**\r
+ * @brief Configures LED GPIO.\r
+ * @param Led: Specifies the Led to be configured. \r
+ * This parameter can be one of following parameters:\r
+ * @arg LED1\r
+ * @arg LED2\r
+ * @arg LED3\r
+ * @arg LED4\r
+ * @retval None\r
+ */\r
+void STM_EVAL_LEDInit(Led_TypeDef Led)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+ \r
+ /* Enable the GPIO_LED Clock */\r
+ RCC_AHB1PeriphClockCmd(GPIO_CLK[Led], ENABLE);\r
+\r
+\r
+ /* Configure the GPIO_LED pin */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r
+ GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);\r
+}\r
+\r
+/**\r
+ * @brief Turns selected LED On.\r
+ * @param Led: Specifies the Led to be set on. \r
+ * This parameter can be one of following parameters:\r
+ * @arg LED1\r
+ * @arg LED2\r
+ * @arg LED3\r
+ * @arg LED4 \r
+ * @retval None\r
+ */\r
+void STM_EVAL_LEDOn(Led_TypeDef Led)\r
+{\r
+ GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];\r
+}\r
+\r
+/**\r
+ * @brief Turns selected LED Off.\r
+ * @param Led: Specifies the Led to be set off. \r
+ * This parameter can be one of following parameters:\r
+ * @arg LED1\r
+ * @arg LED2\r
+ * @arg LED3\r
+ * @arg LED4 \r
+ * @retval None\r
+ */\r
+void STM_EVAL_LEDOff(Led_TypeDef Led)\r
+{\r
+ GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led]; \r
+}\r
+\r
+/**\r
+ * @brief Toggles the selected LED.\r
+ * @param Led: Specifies the Led to be toggled. \r
+ * This parameter can be one of following parameters:\r
+ * @arg LED1\r
+ * @arg LED2\r
+ * @arg LED3\r
+ * @arg LED4 \r
+ * @retval None\r
+ */\r
+void STM_EVAL_LEDToggle(Led_TypeDef Led)\r
+{\r
+ GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];\r
+}\r
+\r
+/**\r
+ * @brief Configures Button GPIO and EXTI Line.\r
+ * @param Button: Specifies the Button to be configured.\r
+ * This parameter can be one of following parameters: \r
+ * @arg BUTTON_WAKEUP: Wakeup Push Button\r
+ * @arg BUTTON_TAMPER: Tamper Push Button \r
+ * @arg BUTTON_KEY: Key Push Button \r
+ * @arg BUTTON_RIGHT: Joystick Right Push Button \r
+ * @arg BUTTON_LEFT: Joystick Left Push Button \r
+ * @arg BUTTON_UP: Joystick Up Push Button \r
+ * @arg BUTTON_DOWN: Joystick Down Push Button\r
+ * @arg BUTTON_SEL: Joystick Sel Push Button\r
+ * @param Button_Mode: Specifies Button mode.\r
+ * This parameter can be one of following parameters: \r
+ * @arg BUTTON_MODE_GPIO: Button will be used as simple IO \r
+ * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt\r
+ * generation capability \r
+ * @retval None\r
+ */\r
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+ EXTI_InitTypeDef EXTI_InitStructure;\r
+ NVIC_InitTypeDef NVIC_InitStructure;\r
+\r
+\r
+ /* Enable the BUTTON Clock */\r
+ RCC_AHB1PeriphClockCmd(BUTTON_CLK[Button], ENABLE);\r
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+\r
+ /* Configure Button pin as input */\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+ GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];\r
+ GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);\r
+\r
+\r
+ if (Button_Mode == BUTTON_MODE_EXTI)\r
+ {\r
+ /* Connect Button EXTI Line to Button GPIO Pin */\r
+ SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);\r
+\r
+ /* Configure Button EXTI line */\r
+ EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];\r
+ EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;\r
+\r
+ if(Button != BUTTON_WAKEUP)\r
+ {\r
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; \r
+ }\r
+ else\r
+ {\r
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; \r
+ }\r
+ EXTI_InitStructure.EXTI_LineCmd = ENABLE;\r
+ EXTI_Init(&EXTI_InitStructure);\r
+\r
+ /* Enable and set Button EXTI Interrupt to the lowest priority */\r
+ NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];\r
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;\r
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;\r
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+\r
+ NVIC_Init(&NVIC_InitStructure); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the selected Button state.\r
+ * @param Button: Specifies the Button to be checked.\r
+ * This parameter can be one of following parameters: \r
+ * @arg BUTTON_WAKEUP: Wakeup Push Button\r
+ * @arg BUTTON_TAMPER: Tamper Push Button \r
+ * @arg BUTTON_KEY: Key Push Button \r
+ * @arg BUTTON_RIGHT: Joystick Right Push Button \r
+ * @arg BUTTON_LEFT: Joystick Left Push Button \r
+ * @arg BUTTON_UP: Joystick Up Push Button \r
+ * @arg BUTTON_DOWN: Joystick Down Push Button\r
+ * @arg BUTTON_SEL: Joystick Sel Push Button \r
+ * @retval The Button GPIO pin value.\r
+ */\r
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)\r
+{\r
+ return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures COM port.\r
+ * @param COM: Specifies the COM port to be configured.\r
+ * This parameter can be one of following parameters: \r
+ * @arg COM1\r
+ * @arg COM2 \r
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that\r
+ * contains the configuration information for the specified USART peripheral.\r
+ * @retval None\r
+ */\r
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+ /* Enable GPIO clock */\r
+ RCC_AHB1PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM], ENABLE);\r
+\r
+ if (COM == COM1)\r
+ {\r
+ /* Enable UART clock */\r
+ RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE);\r
+ }\r
+\r
+ /* Connect PXx to USARTx_Tx*/\r
+ GPIO_PinAFConfig(COM_TX_PORT[COM], COM_TX_PIN_SOURCE[COM], COM_TX_AF[COM]);\r
+\r
+ /* Connect PXx to USARTx_Rx*/\r
+ GPIO_PinAFConfig(COM_RX_PORT[COM], COM_RX_PIN_SOURCE[COM], COM_RX_AF[COM]);\r
+\r
+ /* Configure USART Tx as alternate function */\r
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+\r
+ GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r
+ GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);\r
+\r
+ /* Configure USART Rx as alternate function */\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];\r
+ GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);\r
+\r
+ /* USART configuration */\r
+ USART_Init(COM_USART[COM], USART_InitStruct);\r
+ \r
+ /* Enable USART */\r
+ USART_Cmd(COM_USART[COM], ENABLE);\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file iar_stm32f407zg_sk.h\r
+ * @brief This file contains definitions for Leds, push-buttons\r
+ * and COM ports hardware resources.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+ \r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __IAR_STM32F407ZG_SK_H\r
+#define __IAR_STM32F407ZG_SK_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+ \r
+typedef enum \r
+{\r
+ LED1 = 0,\r
+ LED2 = 1,\r
+ LED3 = 2,\r
+ LED4 = 3\r
+} Led_TypeDef;\r
+\r
+typedef enum \r
+{ \r
+ BUTTON_WAKEUP = 0,\r
+ BUTTON_TAMPER = 1,\r
+ BUTTON_USER = 2,\r
+ BUTTON_RIGHT = 3,\r
+ BUTTON_LEFT = 4,\r
+ BUTTON_UP = 5,\r
+ BUTTON_DOWN = 6,\r
+ BUTTON_SEL = 7\r
+} Button_TypeDef;\r
+\r
+typedef enum \r
+{ \r
+ BUTTON_MODE_GPIO = 0,\r
+ BUTTON_MODE_EXTI = 1\r
+} ButtonMode_TypeDef;\r
+\r
+typedef enum \r
+{\r
+ COM1 = 0,\r
+ COM2 = 1\r
+} COM_TypeDef; \r
+\r
+#define LEDn 4\r
+\r
+#define LED1_PIN GPIO_Pin_6\r
+#define LED1_GPIO_PORT GPIOF\r
+#define LED1_GPIO_CLK RCC_AHB1Periph_GPIOF \r
+ \r
+#define LED2_PIN GPIO_Pin_7\r
+#define LED2_GPIO_PORT GPIOF\r
+#define LED2_GPIO_CLK RCC_AHB1Periph_GPIOF \r
+ \r
+#define LED3_PIN GPIO_Pin_8\r
+#define LED3_GPIO_PORT GPIOF\r
+#define LED3_GPIO_CLK RCC_AHB1Periph_GPIOF \r
+ \r
+#define LED4_PIN GPIO_Pin_9\r
+#define LED4_GPIO_PORT GPIOF\r
+#define LED4_GPIO_CLK RCC_AHB1Periph_GPIOF\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @addtogroup IAR_STM32F407ZG_SK_LOW_LEVEL_BUTTON\r
+ * @{\r
+ */ \r
+#define BUTTONn 8 /**/\r
+\r
+/**\r
+ * @brief Wakeup push-button\r
+ */\r
+#define WAKEUP_BUTTON_PIN GPIO_Pin_0\r
+#define WAKEUP_BUTTON_GPIO_PORT GPIOA\r
+#define WAKEUP_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOA\r
+#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line0\r
+#define WAKEUP_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA\r
+#define WAKEUP_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0\r
+#define WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn \r
+\r
+/**\r
+ * @brief Tamper push-button\r
+ */\r
+#define TAMPER_BUTTON_PIN GPIO_Pin_13\r
+#define TAMPER_BUTTON_GPIO_PORT GPIOC\r
+#define TAMPER_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOC\r
+#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13\r
+#define TAMPER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC\r
+#define TAMPER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource13\r
+#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn \r
+\r
+/**\r
+ * @brief Key push-button\r
+ */\r
+#define USER_BUTTON_PIN GPIO_Pin_6\r
+#define USER_BUTTON_GPIO_PORT GPIOG\r
+#define USER_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOG\r
+#define USER_BUTTON_EXTI_LINE EXTI_Line6\r
+#define USER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOG\r
+#define USER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource6\r
+#define USER_BUTTON_EXTI_IRQn EXTI9_5_IRQn\r
+/**\r
+ * @brief Joystick Right\r
+ */\r
+#define RIGHT_BUTTON_PIN GPIO_Pin_3\r
+#define RIGHT_BUTTON_GPIO_PORT GPIOC\r
+#define RIGHT_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOC\r
+#define RIGHT_BUTTON_EXTI_LINE EXTI_Line3\r
+#define RIGHT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC\r
+#define RIGHT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource3\r
+#define RIGHT_BUTTON_EXTI_IRQn EXTI3_IRQn\r
+/**\r
+ * @brief Joystick Left\r
+ */\r
+#define LEFT_BUTTON_PIN GPIO_Pin_11\r
+#define LEFT_BUTTON_GPIO_PORT GPIOG\r
+#define LEFT_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOG\r
+#define LEFT_BUTTON_EXTI_LINE EXTI_Line11\r
+#define LEFT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOG\r
+#define LEFT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource11\r
+#define LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn\r
+/**\r
+ * @brief Joystick Up\r
+ */\r
+#define UP_BUTTON_PIN GPIO_Pin_7\r
+#define UP_BUTTON_GPIO_PORT GPIOG\r
+#define UP_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOG\r
+#define UP_BUTTON_EXTI_LINE EXTI_Line7\r
+#define UP_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOG\r
+#define UP_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource7\r
+#define UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn\r
+/**\r
+ * @brief Joystick Down\r
+ */\r
+#define DOWN_BUTTON_PIN GPIO_Pin_8\r
+#define DOWN_BUTTON_GPIO_PORT GPIOG\r
+#define DOWN_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOG\r
+#define DOWN_BUTTON_EXTI_LINE EXTI_Line8\r
+#define DOWN_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOG\r
+#define DOWN_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource8\r
+#define DOWN_BUTTON_EXTI_IRQn EXTI9_5_IRQn\r
+/**\r
+ * @brief Joystick Sel\r
+ */\r
+#define SEL_BUTTON_PIN GPIO_Pin_15\r
+#define SEL_BUTTON_GPIO_PORT GPIOG\r
+#define SEL_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOG\r
+#define SEL_BUTTON_EXTI_LINE EXTI_Line15\r
+#define SEL_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOG\r
+#define SEL_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource15\r
+#define SEL_BUTTON_EXTI_IRQn EXTI15_10_IRQn\r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup IAR_STM32F407ZG_SK_LOW_LEVEL_COM\r
+ * @{\r
+ */\r
+#define COMn 2\r
+\r
+/**\r
+ * @brief Definition for COM port1, connected to USART6\r
+ */ \r
+#define EVAL_COM1 USART6\r
+#define EVAL_COM1_CLK RCC_APB2Periph_USART6\r
+#define EVAL_COM1_TX_PIN GPIO_Pin_6\r
+#define EVAL_COM1_TX_GPIO_PORT GPIOC\r
+#define EVAL_COM1_TX_GPIO_CLK RCC_AHB1Periph_GPIOC\r
+#define EVAL_COM1_TX_SOURCE GPIO_PinSource6\r
+#define EVAL_COM1_TX_AF GPIO_AF_USART6\r
+#define EVAL_COM1_RX_PIN GPIO_Pin_9\r
+#define EVAL_COM1_RX_GPIO_PORT GPIOG\r
+#define EVAL_COM1_RX_GPIO_CLK RCC_AHB1Periph_GPIOG\r
+#define EVAL_COM1_RX_SOURCE GPIO_PinSource9\r
+#define EVAL_COM1_RX_AF GPIO_AF_USART6\r
+#define EVAL_COM1_IRQn USART6_IRQn\r
+\r
+/**\r
+ * @brief Definition for COM port2, connected to USART3\r
+ */ \r
+#define EVAL_COM2 USART3\r
+#define EVAL_COM2_CLK RCC_APB1Periph_USART3\r
+#define EVAL_COM2_TX_PIN GPIO_Pin_8\r
+#define EVAL_COM2_TX_GPIO_PORT GPIOD\r
+#define EVAL_COM2_TX_GPIO_CLK RCC_AHB1Periph_GPIOD\r
+#define EVAL_COM2_TX_SOURCE GPIO_PinSource8\r
+#define EVAL_COM2_TX_AF GPIO_AF_USART3\r
+#define EVAL_COM2_RX_PIN GPIO_Pin_9\r
+#define EVAL_COM2_RX_GPIO_PORT GPIOD\r
+#define EVAL_COM2_RX_GPIO_CLK RCC_AHB1Periph_GPIOD\r
+#define EVAL_COM2_RX_SOURCE GPIO_PinSource9\r
+#define EVAL_COM2_RX_AF GPIO_AF_USART3\r
+#define EVAL_COM2_RTS_PIN GPIO_Pin_12\r
+#define EVAL_COM2_RTS_GPIO_PORT GPIOD\r
+#define EVAL_COM2_RTS_GPIO_CLK RCC_AHB1Periph_GPIOD\r
+#define EVAL_COM2_RTS_SOURCE GPIO_PinSource12\r
+#define EVAL_COM2_RTS_AF GPIO_AF_USART3\r
+#define EVAL_COM2_CTS_PIN GPIO_Pin_11\r
+#define EVAL_COM2_CTS_GPIO_PORT GPIOD\r
+#define EVAL_COM2_CTS_GPIO_CLK RCC_AHB1Periph_GPIOD\r
+#define EVAL_COM2_CTS_SOURCE GPIO_PinSource11\r
+#define EVAL_COM2_CTS_AF GPIO_AF_USART3\r
+#define EVAL_COM2_IRQn USART3_IRQn\r
+\r
+/**\r
+ * @BUZZER\r
+ */ \r
+#define BUZZER_GPIO_PIN GPIO_Pin_10\r
+#define BUZZER_GPIO_PORT GPIOA\r
+#define BUZZER_GPIO_CLK RCC_AHB1Periph_GPIOA\r
+#define BUZZER_PIN_SOURCE GPIO_PinSource10\r
+#define BUZZER_TIM TIM1\r
+#define RCC_APB2PERIPH_BUZZER_TIM RCC_APB2Periph_TIM1\r
+#define BUZZER_PIN_AF GPIO_AF_TIM1\r
+\r
+/**\r
+ * @USB OTG\r
+ */ \r
+#define OTG_FS_VBUS_PIN GPIO_Pin_9\r
+#define OTG_FS_VBUS_PORT GPIOA\r
+#define OTG_FS_VBUS_CLK RCC_AHB1Periph_GPIOA\r
+#define OTG_FS_VBUS_SOURCE GPIO_PinSource9\r
+\r
+#define USB_FS_VBUSON_PIN GPIO_Pin_2\r
+#define USB_FS_VBUSON_PORT GPIOC\r
+#define USB_FS_VBUSON_CLK RCC_AHB1Periph_GPIOC\r
+#define USB_FS_VBUSON_SOURCE GPIO_PinSource2\r
+\r
+#define USB_FS_FAULT_PIN GPIO_Pin_10\r
+#define USB_FS_FAULT_PORT GPIOB\r
+#define USB_FS_FAULT_CLK RCC_AHB1Periph_GPIOB\r
+#define USB_FS_FAULT_SOURCE GPIO_PinSource10\r
+\r
+/**\r
+ * @USB HOST\r
+ */ \r
+#define OTG_HS_VBUS_PIN GPIO_Pin_13\r
+#define OTG_HS_VBUS_PORT GPIOB\r
+#define OTG_HS_VBUS_CLK RCC_AHB1Periph_GPIOB\r
+#define OTG_HS_VBUS_SOURCE GPIO_PinSource13\r
+\r
+#define USB_HS_VBUSON_PIN GPIO_Pin_3\r
+#define USB_HS_VBUSON_PORT GPIOE\r
+#define USB_HS_VBUSON_CLK RCC_AHB1Periph_GPIOE\r
+#define USB_HS_VBUSON_SOURCE GPIO_PinSource3\r
+\r
+#define USB_HS_FAULT_PIN GPIO_Pin_13\r
+#define USB_HS_FAULT_PORT GPIOD\r
+#define USB_HS_FAULT_CLK RCC_AHB1Periph_GPIOD\r
+#define USB_HS_FAULT_SOURCE GPIO_PinSource13\r
+\r
+#define OTG_HS_ID_PIN GPIO_Pin_12\r
+#define OTG_HS_ID_PORT GPIOB\r
+#define OTG_HS_ID_CLK RCC_AHB1Periph_GPIOB\r
+#define OTG_HS_ID_SOURCE GPIO_PinSource12\r
+\r
+/**\r
+ * @TRIMER\r
+ */ \r
+#define TRIMER_PIN GPIO_Pin_0\r
+#define TRIMER_PORT GPIOC\r
+#define TRIMER_CLK RCC_AHB1Periph_GPIOC\r
+#define TRIMER_SOURCE GPIO_PinSource0\r
+#define TRIMER_CHANNEL ADC_Channel_10\r
+\r
+/** @addtogroup IAR_STM32F407ZG_SK_LOW_LEVEL_SD_FLASH\r
+ * @{\r
+ */ \r
+/**\r
+ * @SD\r
+ */ \r
+#define SD_CP_PIN GPIO_Pin_3\r
+#define SD_CP_PORT GPIOD\r
+#define SD_CP_CLK RCC_AHB1Periph_GPIOD\r
+#define SD_CP_SOURCE GPIO_PinSource3\r
+\r
+#define SD_WP_PIN GPIO_Pin_4\r
+#define SD_WP_PORT GPIOE\r
+#define SD_WP_CLK RCC_AHB1Periph_GPIOE\r
+#define SD_WP_SOURCE GPIO_PinSource4\r
+\r
+#define SD_CMD_PIN GPIO_Pin_2\r
+#define SD_CMD_PORT GPIOD\r
+#define SD_CMD_CLK RCC_AHB1Periph_GPIOD\r
+#define SD_CMD_SOURCE GPIO_PinSource2\r
+\r
+#define SD_D0_PIN GPIO_Pin_8\r
+#define SD_D0_PORT GPIOC\r
+#define SD_D0_CLK RCC_AHB1Periph_GPIOC\r
+#define SD_D0_SOURCE GPIO_PinSource8\r
+\r
+#define SD_D1_PIN GPIO_Pin_9\r
+#define SD_D1_PORT GPIOC\r
+#define SD_D1_CLK RCC_AHB1Periph_GPIOC\r
+#define SD_D1_SOURCE GPIO_PinSource9\r
+\r
+#define SD_D2_PIN GPIO_Pin_10\r
+#define SD_D2_PORT GPIOC\r
+#define SD_D2_CLK RCC_AHB1Periph_GPIOC\r
+#define SD_D2_SOURCE GPIO_PinSource10\r
+\r
+#define SD_D3_PIN GPIO_Pin_11\r
+#define SD_D3_PORT GPIOC\r
+#define SD_D3_CLK RCC_AHB1Periph_GPIOC\r
+#define SD_D3_SOURCE GPIO_PinSource11\r
+\r
+#define SD_CLK_PIN GPIO_Pin_12\r
+#define SD_CLK_PORT GPIOC\r
+#define SD_CLK_CLK RCC_AHB1Periph_GPIOC\r
+#define SD_CLK_SOURCE GPIO_PinSource12\r
+/**\r
+ * @brief SD FLASH SDIO Interface\r
+ */ \r
+#define SD_SDIO_DMA_STREAM3 3\r
+//#define SD_SDIO_DMA_STREAM6 6\r
+\r
+#ifdef SD_SDIO_DMA_STREAM3\r
+ #define SD_SDIO_DMA_STREAM DMA2_Stream3\r
+ #define SD_SDIO_DMA_CHANNEL DMA_Channel_4\r
+ #define SD_SDIO_DMA_FLAG_FEIF DMA_FLAG_FEIF3\r
+ #define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF3\r
+ #define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF3\r
+ #define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF3\r
+ #define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF3 \r
+#elif defined SD_SDIO_DMA_STREAM6\r
+ #define SD_SDIO_DMA_STREAM DMA2_Stream6\r
+ #define SD_SDIO_DMA_CHANNEL DMA_Channel_4\r
+ #define SD_SDIO_DMA_FLAG_FEIF DMA_FLAG_FEIF6\r
+ #define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF6\r
+ #define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF6\r
+ #define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF6\r
+ #define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF6 \r
+#endif /* SD_SDIO_DMA_STREAM3 */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/**\r
+ * @CAN\r
+ */ \r
+#define CAN_TX_PIN GPIO_Pin_9\r
+#define CAN_TX_PORT GPIOB\r
+#define CAN_TX_CLK RCC_AHB1Periph_GPIOB\r
+#define CAN_TX_AF GPIO_AF_CAN1\r
+#define CAN_TX_SOURCE GPIO_PinSource9\r
+\r
+#define CAN_RX_PIN GPIO_Pin_8\r
+#define CAN_RX_PORT GPIOB\r
+#define CAN_RX_CLK RCC_AHB1Periph_GPIOB\r
+#define CAN_RX_AF GPIO_AF_CAN1\r
+#define CAN_RX_SOURCE GPIO_PinSource8\r
+\r
+#define CAN_CTRL_PIN GPIO_Pin_6\r
+#define CAN_CTRL_PORT GPIOD\r
+#define CAN_CTRL_CLK RCC_AHB1Periph_GPIOD\r
+#define CAN_CTRL_SOURCE GPIO_PinSource6\r
+\r
+/**\r
+ * @}\r
+ */ \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup IAR_STM32F407ZG_SK_LOW_LEVEL_Exported_Macros\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup IAR_STM32F407ZG_SK_LOW_LEVEL_Exported_Functions\r
+ * @{\r
+ */\r
+void STM_EVAL_LEDInit(Led_TypeDef Led);\r
+void STM_EVAL_LEDOn(Led_TypeDef Led);\r
+void STM_EVAL_LEDOff(Led_TypeDef Led);\r
+void STM_EVAL_LEDToggle(Led_TypeDef Led);\r
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);\r
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);\r
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); \r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __IAR_STM32F407ZG_SK_H */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;\r
+define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;\r
+define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+\r
+define memory mem with size = 4G;\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite,\r
+ block CSTACK, block HEAP };
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/******************************************************************************\r
+ * >>>>>> NOTE 1: <<<<<<\r
+ *\r
+ * main() can be configured to create either a very simple LED flasher demo, or\r
+ * a more comprehensive test/demo application.\r
+ *\r
+ * To create a very simple LED flasher example, set the\r
+ * mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY constant (defined below) to 1. When\r
+ * this is done, only the standard demo flash tasks are created. The standard\r
+ * demo flash example creates three tasks, each of which toggle an LED at a\r
+ * fixed but different frequency.\r
+ *\r
+ * To create a more comprehensive test and demo application, set\r
+ * mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 0.\r
+ *\r
+ * >>>>>> NOTE 2: <<<<<<\r
+ *\r
+ * In addition to the normal set of standard demo tasks, the comprehensive test\r
+ * makes heavy use of the floating point unit, and forces floating point\r
+ * instructions to be used from interrupts that nest three deep. The nesting\r
+ * starts from the tick hook function, resulting is an abnormally long context\r
+ * switch time. This is done purely to stress test the FPU context switching\r
+ * implementation, and that part of the test can be removed by setting\r
+ * configUSE_TICK_HOOK to 0 in FreeRTOSConfig.h.\r
+ ******************************************************************************\r
+ *\r
+ * main() creates all the demo application tasks and software timers, then starts\r
+ * the scheduler. The web documentation provides more details of the standard\r
+ * demo application tasks, which provide no particular functionality, but do\r
+ * provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill both the core and floating point registers with\r
+ * known values, then check that each register maintains its expected value for\r
+ * the lifetime of the task. Each task uses a different set of values. The reg\r
+ * test tasks execute with a very low priority, so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ * "Check" timer - The check software timer period is initially set to three\r
+ * seconds. The callback function associated with the check software timer\r
+ * checks that all the standard demo tasks, and the register check tasks, are\r
+ * not only still executing, but are executing without reporting any errors. If\r
+ * the check software timer discovers that a task has either stalled, or\r
+ * reported an error, then it changes its own execution period from the initial\r
+ * three seconds, to just 200ms. The check software timer callback function\r
+ * also toggles an LED each time it is called. This provides a visual\r
+ * indication of the system status: If the LED toggles every three seconds,\r
+ * then no issues have been discovered. If the LED toggles every 200ms, then\r
+ * an issue has been discovered with at least one task.\r
+ *\r
+ * Tick hook - The application tick hook is called from the schedulers tick\r
+ * interrupt service routine when configUSE_TICK_HOOK is set to 1 in\r
+ * FreeRTOSConfig.h. In this example, the tick hook is used to test the kernels\r
+ * handling of the floating point units (FPU) context, both at the task level\r
+ * and when nesting interrupts access the floating point unit registers. The\r
+ * tick hook function first fills the FPU registers with a known value, it\r
+ * then triggers a medium priority interrupt. The medium priority interrupt\r
+ * fills the FPU registers with a different value, and triggers a high priority\r
+ * interrupt. The high priority interrupt once again fills the the FPU\r
+ * registers with a known value before returning to the medium priority\r
+ * interrupt. The medium priority interrupt checks that the FPU registers\r
+ * contain the values that it wrote to them, then returns to the tick hook\r
+ * function. Finally, the tick hook function checks that the FPU registers\r
+ * contain the values that it wrote to them, before it too returns.\r
+ *\r
+ * Button interrupt - The button marked "USER" on the starter kit is used to\r
+ * demonstrate how to write an interrupt service routine, and how to synchronise\r
+ * a task with an interrupt. A task is created that blocks on a test semaphore.\r
+ * When the USER button is pressed, the button interrupt handler gives the\r
+ * semaphore, causing the task to unblock. When the task unblocks, it simply\r
+ * increments an execution count variable, then returns to block on the\r
+ * semaphore again.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "flop.h"\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+\r
+/* Hardware and starter kit includes. */\r
+#include "arm_comm.h"\r
+#include "iar_stm32f407zg_sk.h"\r
+#include "stm32f4xx.h"\r
+#include "stm32f4xx_conf.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The LED used by the check timer. */\r
+#define mainCHECK_LED ( 3UL )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The period after which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_RATE_MS constant. */\r
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_RATE_MS constant. */\r
+#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )\r
+\r
+/* Set mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 1 to create a simple demo.\r
+Set mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 0 to create a much more\r
+comprehensive test application. See the comments at the top of this file, and\r
+the documentation page on the http://www.FreeRTOS.org web site for more\r
+information. */\r
+#define mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY 0\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Set up the hardware ready to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * The check timer callback function, as described at the top of this file.\r
+ */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer );\r
+\r
+/*\r
+ * Configure the interrupts used to test the interrupt nesting depth as\r
+ * described at the top of this file.\r
+ */\r
+static void prvSetupNestedFPUInterruptsTest( void );\r
+\r
+/*\r
+ * Register check tasks, and the tasks used to write over and check the contents\r
+ * of the FPU registers, as described at the top of this file. The nature of\r
+ * these files necessitates that they are written in an assembly file.\r
+ */\r
+extern void vRegTest1Task( void *pvParameters );\r
+extern void vRegTest2Task( void *pvParameters );\r
+extern void vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue );\r
+extern unsigned long ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue );\r
+\r
+/*\r
+ * The task that is synchronised with the button interrupt. This is done just\r
+ * to demonstrate how to write interrupt service routines, and how to\r
+ * synchronise a task with an interrupt.\r
+ */\r
+static void prvButtonTestTask( void *pvParameters );\r
+\r
+/*\r
+ * This file can be used to create either a simple LED flasher example, or a\r
+ * comprehensive test/demo application - depending on the setting of the\r
+ * mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY constant defined above. If\r
+ * mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 1, then the following\r
+ * function will create a lot of additional tasks and a software timer. If\r
+ * mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 0, then the following\r
+ * function will do nothing.\r
+ */\r
+static void prvOptionallyCreateComprehensveTestApplication( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The following two variables are used to communicate the status of the\r
+register check tasks to the check software timer. If the variables keep\r
+incrementing, then the register check tasks has not discovered any errors. If\r
+a variable stops incrementing, then an error has been found. */\r
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
+\r
+/* The following variables are used to verify that the interrupt nesting depth\r
+is as intended. ulFPUInterruptNesting is incremented on entry to an interrupt\r
+that uses the FPU, and decremented on exit of the same interrupt.\r
+ulMaxFPUInterruptNesting latches the highest value reached by\r
+ulFPUInterruptNesting. These variables have no other purpose. */\r
+volatile unsigned long ulFPUInterruptNesting = 0UL, ulMaxFPUInterruptNesting = 0UL;\r
+\r
+/* The semaphore used to demonstrate a task being synchronised with an\r
+interrupt. */\r
+static xSemaphoreHandle xTestSemaphore = NULL;\r
+\r
+/* The variable that is incremented by the task synchronised with the button\r
+interrupt. */\r
+volatile unsigned long ulButtonPressCounts = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main(void)\r
+{\r
+ /* Configure the hardware ready to run the test. */\r
+ prvSetupHardware();\r
+ \r
+ /* Start standard demo/test application flash tasks. See the comments at\r
+ the top of this file. The LED flash tasks are always created. The other\r
+ tasks are only created if mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to\r
+ 0 (at the top of this file). See the comments at the top of this file for\r
+ more information. */\r
+ vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );\r
+\r
+ /* The following function will only create more tasks and timers if\r
+ mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 0 (at the top of this\r
+ file). See the comments at the top of this file for more information. */\r
+ prvOptionallyCreateComprehensveTestApplication();\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+ \r
+ /* Infinite loop */\r
+ for( ;; ); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTimerCallback( xTimerHandle xTimer )\r
+{\r
+static long lChangedTimerPeriodAlready = pdFALSE;\r
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
+long lErrorFound = pdFALSE;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none have detected an error. */\r
+\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ lErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ lErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ lErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ lErrorFound = pdTRUE;\r
+ }\r
+ \r
+ /* Check that the register test 1 task is still running. */\r
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
+ {\r
+ lErrorFound = pdTRUE;\r
+ }\r
+ ulLastRegTest1Value = ulRegTest1LoopCounter;\r
+\r
+ /* Check that the register test 2 task is still running. */\r
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
+ {\r
+ lErrorFound = pdTRUE;\r
+ }\r
+ ulLastRegTest2Value = ulRegTest2LoopCounter;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ vParTestToggleLED( mainCHECK_LED ); \r
+ \r
+ /* Have any errors been latch in lErrorFound? If so, shorten the\r
+ period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.\r
+ This will result in an increase in the rate at which mainCHECK_LED\r
+ toggles. */\r
+ if( lErrorFound != pdFALSE )\r
+ {\r
+ if( lChangedTimerPeriodAlready == pdFALSE )\r
+ {\r
+ lChangedTimerPeriodAlready = pdTRUE;\r
+ \r
+ /* This call to xTimerChangePeriod() uses a zero block time.\r
+ Functions called from inside of a timer callback function must\r
+ *never* attempt to block. */\r
+ xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvButtonTestTask( void *pvParameters )\r
+{\r
+ configASSERT( xTestSemaphore );\r
+\r
+ /* This is the task used as an example of how to synchronise a task with\r
+ an interrupt. Each time the button interrupt gives the semaphore, this task\r
+ will unblock, increment its execution counter, then return to block\r
+ again. */\r
+ \r
+ /* Take the semaphore before started to ensure it is in the correct\r
+ state. */\r
+ xSemaphoreTake( xTestSemaphore, mainDONT_BLOCK );\r
+ \r
+ for( ;; )\r
+ {\r
+ xSemaphoreTake( xTestSemaphore, portMAX_DELAY );\r
+ ulButtonPressCounts++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup STM32 system (clock, PLL and Flash configuration) */\r
+ SystemInit();\r
+ \r
+ /* Ensure all priority bits are assigned as preemption priority bits. */\r
+ NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 );\r
+ \r
+ /* Setup the LED outputs. */\r
+ vParTestInitialise();\r
+ \r
+ /* Configure the button input. This configures the interrupt to use the\r
+ lowest interrupt priority, so it is ok to use the ISR safe FreeRTOS API\r
+ from the button interrupt handler. */\r
+ STM_EVAL_PBInit( BUTTON_USER, BUTTON_MODE_EXTI );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ #if ( mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY == 0 )\r
+ {\r
+ /* Just to verify that the interrupt nesting behaves as expected,\r
+ increment ulFPUInterruptNesting on entry, and decrement it on exit. */\r
+ ulFPUInterruptNesting++;\r
+\r
+ /* Fill the FPU registers with 0. */\r
+ vRegTestClearFlopRegistersToParameterValue( 0UL );\r
+ \r
+ /* Trigger a timer 2 interrupt, which will fill the registers with a\r
+ different value and itself trigger a timer 3 interrupt. Note that the\r
+ timers are not actually used. The timer 2 and 3 interrupt vectors are\r
+ just used for convenience. */\r
+ NVIC_SetPendingIRQ( TIM2_IRQn );\r
+ \r
+ /* Ensure that, after returning from the nested interrupts, all the FPU\r
+ registers contain the value to which they were set by the tick hook\r
+ function. */\r
+ configASSERT( ulRegTestCheckFlopRegistersContainParameterValue( 0UL ) );\r
+ \r
+ ulFPUInterruptNesting--;\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupNestedFPUInterruptsTest( void )\r
+{\r
+NVIC_InitTypeDef NVIC_InitStructure;\r
+\r
+ /* Enable the TIM2 interrupt in the NVIC. The timer itself is not used,\r
+ just its interrupt vector to force nesting from software. TIM2 must have\r
+ a lower priority than TIM3, and both must have priorities above\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;\r
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1;\r
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;\r
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+ NVIC_Init( &NVIC_InitStructure );\r
+ \r
+ /* Enable the TIM3 interrupt in the NVIC. The timer itself is not used,\r
+ just its interrupt vector to force nesting from software. TIM2 must have\r
+ a lower priority than TIM3, and both must have priorities above\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+ NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;\r
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 2;\r
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;\r
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+ NVIC_Init( &NVIC_InitStructure );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void TIM3_IRQHandler( void )\r
+{\r
+ /* Just to verify that the interrupt nesting behaves as expected, increment\r
+ ulFPUInterruptNesting on entry, and decrement it on exit. */\r
+ ulFPUInterruptNesting++;\r
+ \r
+ /* This is the highest priority interrupt in the chain of forced nesting\r
+ interrupts, so latch the maximum value reached by ulFPUInterruptNesting.\r
+ This is done purely to allow verification that the nesting depth reaches\r
+ that intended. */\r
+ if( ulFPUInterruptNesting > ulMaxFPUInterruptNesting )\r
+ {\r
+ ulMaxFPUInterruptNesting = ulFPUInterruptNesting;\r
+ }\r
+\r
+ /* Fill the FPU registers with 99 to overwrite the values written by\r
+ TIM2_IRQHandler(). */\r
+ vRegTestClearFlopRegistersToParameterValue( 99UL );\r
+ \r
+ ulFPUInterruptNesting--;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void TIM2_IRQHandler( void )\r
+{\r
+ /* Just to verify that the interrupt nesting behaves as expected, increment\r
+ ulFPUInterruptNesting on entry, and decrement it on exit. */\r
+ ulFPUInterruptNesting++;\r
+ \r
+ /* Fill the FPU registers with 1. */\r
+ vRegTestClearFlopRegistersToParameterValue( 1UL );\r
+ \r
+ /* Trigger a timer 3 interrupt, which will fill the registers with a\r
+ different value. */\r
+ NVIC_SetPendingIRQ( TIM3_IRQn );\r
+\r
+ /* Ensure that, after returning from the nesting interrupt, all the FPU\r
+ registers contain the value to which they were set by this interrupt\r
+ function. */\r
+ configASSERT( ulRegTestCheckFlopRegistersContainParameterValue( 1UL ) );\r
+ \r
+ ulFPUInterruptNesting--;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvOptionallyCreateComprehensveTestApplication( void )\r
+{\r
+ #if ( mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY == 0 )\r
+ {\r
+ xTimerHandle xCheckTimer = NULL;\r
+\r
+ /* Configure the interrupts used to test FPU registers being used from\r
+ nested interrupts. */\r
+ prvSetupNestedFPUInterruptsTest();\r
+\r
+ /* Start all the other standard demo/test tasks. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+\r
+ /* Most importantly, start the tasks that use the FPU. */\r
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
+ \r
+ /* Create the register check tasks, as described at the top of this\r
+ file */\r
+ xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the semaphore that is used to demonstrate a task being\r
+ synchronised with an interrupt. */\r
+ vSemaphoreCreateBinary( xTestSemaphore );\r
+\r
+ /* Create the task that is unblocked by the demonstration interrupt. */\r
+ xTaskCreate( prvButtonTestTask, ( signed char * ) "BtnTest", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );\r
+ \r
+ /* Create the software timer that performs the 'check' functionality,\r
+ as described at the top of this file. */\r
+ xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
+ ); \r
+ \r
+ if( xCheckTimer != NULL )\r
+ {\r
+ xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
+ }\r
+\r
+ /* This task has to be created last as it keeps account of the number of\r
+ tasks it expects to see running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+ }\r
+ #else /* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY */\r
+ {\r
+ /* Just to prevent compiler warnings when the configuration options are\r
+ set such that these static functions are not used. */\r
+ ( void ) vRegTest1Task;\r
+ ( void ) vRegTest2Task;\r
+ ( void ) prvCheckTimerCallback;\r
+ ( void ) prvSetupNestedFPUInterruptsTest;\r
+ }\r
+ #endif /* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void EXTI9_5_IRQHandler(void)\r
+{\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* Only line 6 is enabled, so there is no need to test which line generated\r
+ the interrupt. */\r
+ EXTI_ClearITPendingBit( EXTI_Line6 );\r
+ \r
+ /* This interrupt does nothing more than demonstrate how to synchronise a\r
+ task with an interrupt. First the handler releases a semaphore.\r
+ lHigherPriorityTaskWoken has been initialised to zero. */\r
+ xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );\r
+ \r
+ /* If there was a task that was blocked on the semaphore, and giving the\r
+ semaphore caused the task to unblock, and the unblocked task has a priority\r
+ higher than the currently executing task (the task that this interrupt\r
+ interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE.\r
+ Passing pdTRUE into the following macro call will cause this interrupt to\r
+ return directly to the unblocked, higher priority, task. */\r
+ portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* vApplicationMallocFailedHook() will only be called if\r
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ function that will get called if a call to pvPortMalloc() fails.\r
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+ timer or semaphore is created. It is also called by various parts of the\r
+ demo application. If heap_1.c or heap_2.c are used, then the size of the\r
+ heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+ FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+ to query the size of free heap space that remains (although it does not\r
+ provide information on how the remaining heap might be fragmented). */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
+ task. It is essential that code added to this hook function never attempts\r
+ to block in any way (for example, call xQueueReceive() with a block time\r
+ specified, or call vTaskDelay()). If the application makes use of the\r
+ vTaskDelete() API function (as this demo application does) then it is also\r
+ important that vApplicationIdleHook() is permitted to return to its calling\r
+ function, because it is the responsibility of the idle task to clean up\r
+ memory allocated by the kernel to any task that has since been deleted. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
+@REM\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM \r
+\r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 6.0\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armjlink.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armbat.dll" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\config\flashloader\ST\FlashSTM32F4xxx.board" --backend -B "--endian=little" "--cpu=Cortex-M4" "--fpu=VFPv4" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\CONFIG\debugger\ST\iostm32f4xxx.ddf" "--drv_verify_download" "--semihosting" "--device=STM32F4xxx" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--jlink_interface=SWD" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=120000000,1,2000000" \r
+\r
+\r
--- /dev/null
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+ITMlogFile=$PROJ_DIR$\ITM.log\r
+[watch_formats]\r
+Fmt0={W}0:ultemp 4 0\r
+[PowerLog]\r
+LogEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=0\r
+Title0=I0\r
+Setup0=0 1 0 500 2 0 4 0 0\r
+LiveEnabled=0\r
+LiveFile=PowerLogLive.log\r
+[DataLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+[EventLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+Title0=ITM1\r
+Setup0=1 1 1 1\r
+Title1=ITM2\r
+Setup1=1 1 1 1\r
+Title2=ITM3\r
+Setup2=1 1 1 1\r
+Title3=ITM4\r
+Setup3=1 1 1 1\r
+SumSortOrder=0\r
+[InterruptLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+SumSortOrder=0\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+[Trace2]\r
+Enabled=0\r
+[SWOTraceWindow]\r
+PcSampling=0\r
+InterruptLogs=0\r
+ForcedTimeStamps=0\r
+EventCPI=0\r
+EventEXC=0\r
+EventFOLD=0\r
+EventLSU=0\r
+EventSLEEP=0\r
+[PowerProbe]\r
+Frequency=10000\r
+Probe0=I0\r
+ProbeSetup0=2 1 1 2 0 0\r
+[CallStackLog]\r
+Enabled=0\r
+[DriverProfiling]\r
+Enabled=0\r
+Mode=3\r
+Graph=0\r
+Symbiont=0\r
+Exclusions=\r
+[Disassemble mode]\r
+mode=0\r
+[Breakpoints2]\r
+Bp0=_ 1 "EMUL_CODE" "{$PROJ_DIR$\..\..\Source\tasks.c}.1090.7" 0 0 1 "" 0 "" 0\r
+Count=1\r
+[Aliases]\r
+Count=0\r
+SuppressDialog=0\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+ <ConfigDictionary>\r
+ \r
+ <CurrentConfigs><Project>RTOSDemo/Flash Debug</Project></CurrentConfigs></ConfigDictionary>\r
+ <Desktop>\r
+ <Static>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>292</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Build>\r
+ \r
+ \r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build>\r
+ <TerminalIO/><Debug-Log><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log></Static>\r
+ <Windows>\r
+ \r
+ \r
+ <Wnd0>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-21337-25041</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Common Demo Source</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS_Source</ExpandedNode><ExpandedNode>RTOSDemo/STM32F4xx_StdPeriph_Driver</ExpandedNode><ExpandedNode>RTOSDemo/modules</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd0><Wnd1>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-25290-25172</Identity>\r
+ <TabName>Build</TabName>\r
+ <Factory>Build</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab><Identity>TabID-22929-15481</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd1></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>46</YPos><SelStart>12512</SelStart><SelEnd>12512</SelEnd></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-013492f8><key>iaridepm.enu1</key></Toolbar-013492f8></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>625</Bottom><Right>366</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>219048</sizeVertCX><sizeVertCY>638493</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>313</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>315</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>320774</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Workspace>\r
+\r
+\r
--- /dev/null
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
+@REM\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM \r
+\r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 6.0\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armjlink.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armbat.dll" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\config\flashloader\ST\FlashSTM32F4xxx.board" --backend -B "--endian=little" "--cpu=Cortex-M4" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\CONFIG\debugger\ST\iostm32f4xxx.ddf" "--drv_verify_download" "--semihosting" "--device=STM32F4xxx" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--jlink_interface=SWD" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=120000000,1,2000000" \r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project/>\r
+\r
+\r
--- /dev/null
+[DebugChecksum]\r
+Checksum=1459121027\r
+[Exceptions]\r
+StopOnUncaught=_ 0\r
+StopOnThrow=_ 0\r
+[PowerLog]\r
+LogEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=0\r
+Title0=I0\r
+Setup0=0 1 0 500 2 0 4 0 0\r
+LiveEnabled=0\r
+LiveFile=PowerLogLive.log\r
+[DataLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+[EventLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+SumSortOrder=0\r
+Title0=ITM1\r
+Setup0=1 1 1 1\r
+Title1=ITM2\r
+Setup1=1 1 1 1\r
+Title2=ITM3\r
+Setup2=1 1 1 1\r
+Title3=ITM4\r
+Setup3=1 1 1 1\r
+[InterruptLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+SumSortOrder=0\r
+[Stack]\r
+FillEnabled=0\r
+OverflowWarningsEnabled=1\r
+WarningThreshold=90\r
+SpWarningsEnabled=1\r
+WarnLogOnly=1\r
+UseTrigger=1\r
+TriggerName=main\r
+LimitSize=0\r
+ByteLimit=50\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+[CallStack]\r
+ShowArgs=0\r
+[Disassembly]\r
+MixedMode=1\r
+[StackPlugin]\r
+Enabled=1\r
+OverflowWarningsEnabled=1\r
+WarningThreshold=90\r
+SpWarningsEnabled=1\r
+WarnHow=0\r
+UseTrigger=1\r
+TriggerName=main\r
+LimitSize=0\r
+ByteLimit=50\r
+[Trace2]\r
+Enabled=0\r
+[SWOTraceWindow]\r
+PcSampling=0\r
+InterruptLogs=0\r
+ForcedTimeStamps=0\r
+EventCPI=0\r
+EventEXC=0\r
+EventFOLD=0\r
+EventLSU=0\r
+EventSLEEP=0\r
+[SWOTraceHWSettings]\r
+OverrideDefaultClocks=0\r
+CpuClock=120000000\r
+ClockAutoDetect=1\r
+ClockWanted=4500000\r
+JtagSpeed=2250000\r
+Prescaler=53\r
+TimeStampPrescIndex=0\r
+TimeStampPrescData=0\r
+PcSampCYCTAP=1\r
+PcSampPOSTCNT=15\r
+PcSampIndex=0\r
+DataLogMode=0\r
+ITMportsEnable=0\r
+ITMportsTermIO=0\r
+ITMportsLogFile=0\r
+ITMlogFile=$PROJ_DIR$\ITM.log\r
+[PowerProbe]\r
+Frequency=10000\r
+Probe0=I0\r
+ProbeSetup0=2 1 1 2 0 0\r
+[CallStackLog]\r
+Enabled=0\r
+[DriverProfiling]\r
+Enabled=0\r
+Mode=3\r
+Graph=0\r
+Symbiont=0\r
+Exclusions=\r
+[Disassemble mode]\r
+mode=0\r
+[Breakpoints2]\r
+Count=0\r
+[Aliases]\r
+Count=0\r
+SuppressDialog=0\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+ <ConfigDictionary>\r
+ \r
+ <CurrentConfigs><Project>Test/Flash Debug</Project></CurrentConfigs></ConfigDictionary>\r
+ <Desktop>\r
+ <Static>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>299</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Build>\r
+ \r
+ \r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build>\r
+ </Static>\r
+ <Windows>\r
+ \r
+ \r
+ <Wnd2>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-24013-20283</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>Test</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd2><Wnd3>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-21922-20322</Identity>\r
+ <TabName>Build</TabName>\r
+ <Factory>Build</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane/><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-01349408><key>iaridepm.enu1</key></Toolbar-01349408></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>373</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>223214</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Workspace>\r
+\r
+\r
--- /dev/null
+[BREAKPOINTS]\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 0\r
+Device="AD7160"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+;/******************** (C) COPYRIGHT 2011 STMicroelectronics ********************\r
+;* File Name : startup_stm32f4xx.s\r
+;* Author : MCD Application Team\r
+;* Version : V1.0.0\r
+;* Date : 30-September-2011\r
+;* Description : STM32F4xx devices vector table for EWARM toolchain.\r
+;* This module performs:\r
+;* - Set the initial SP\r
+;* - Set the initial PC == _iar_program_start,\r
+;* - Set the vector table entries with the exceptions ISR \r
+;* address.\r
+;* - Configure the system clock and the external SRAM mounted on \r
+;* STM324xG-EVAL board to be used as data memory (optional, \r
+;* to be enabled by user)\r
+;* - Branches to main in the C library (which eventually\r
+;* calls main()).\r
+;* After Reset the Cortex-M4 processor is in Thread mode,\r
+;* priority is Privileged, and the Stack is set to Main.\r
+;********************************************************************************\r
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+;*******************************************************************************/\r
+;\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; The vector table is normally located at address 0.\r
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
+; The name "__vector_table" has special meaning for C-SPY:\r
+; it is where the SP start value is found, and the NVIC vector\r
+; table register (VTOR) is initialized to this address if != 0.\r
+;\r
+; Cortex-M version\r
+;\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+ SECTION .intvec:CODE:NOROOT(2)\r
+\r
+ EXTERN __iar_program_start\r
+ EXTERN SystemInit\r
+ PUBLIC __vector_table\r
+\r
+ DATA\r
+__vector_table\r
+ DCD sfe(CSTACK)\r
+ DCD Reset_Handler ; Reset Handler\r
+\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ DCD WWDG_IRQHandler ; Window WatchDog \r
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection \r
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line \r
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line \r
+ DCD FLASH_IRQHandler ; FLASH \r
+ DCD RCC_IRQHandler ; RCC \r
+ DCD EXTI0_IRQHandler ; EXTI Line0 \r
+ DCD EXTI1_IRQHandler ; EXTI Line1 \r
+ DCD EXTI2_IRQHandler ; EXTI Line2 \r
+ DCD EXTI3_IRQHandler ; EXTI Line3 \r
+ DCD EXTI4_IRQHandler ; EXTI Line4 \r
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 \r
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 \r
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 \r
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 \r
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 \r
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 \r
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 \r
+ DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s \r
+ DCD CAN1_TX_IRQHandler ; CAN1 TX \r
+ DCD CAN1_RX0_IRQHandler ; CAN1 RX0 \r
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1 \r
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE \r
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s \r
+ DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 \r
+ DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 \r
+ DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11\r
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare \r
+ DCD TIM2_IRQHandler ; TIM2 \r
+ DCD TIM3_IRQHandler ; TIM3 \r
+ DCD TIM4_IRQHandler ; TIM4 \r
+ DCD I2C1_EV_IRQHandler ; I2C1 Event \r
+ DCD I2C1_ER_IRQHandler ; I2C1 Error \r
+ DCD I2C2_EV_IRQHandler ; I2C2 Event \r
+ DCD I2C2_ER_IRQHandler ; I2C2 Error \r
+ DCD SPI1_IRQHandler ; SPI1 \r
+ DCD SPI2_IRQHandler ; SPI2 \r
+ DCD USART1_IRQHandler ; USART1 \r
+ DCD USART2_IRQHandler ; USART2 \r
+ DCD USART3_IRQHandler ; USART3 \r
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s \r
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line \r
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line \r
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 \r
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 \r
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14\r
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare \r
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 \r
+ DCD FSMC_IRQHandler ; FSMC \r
+ DCD SDIO_IRQHandler ; SDIO \r
+ DCD TIM5_IRQHandler ; TIM5 \r
+ DCD SPI3_IRQHandler ; SPI3 \r
+ DCD UART4_IRQHandler ; UART4 \r
+ DCD UART5_IRQHandler ; UART5 \r
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors \r
+ DCD TIM7_IRQHandler ; TIM7 \r
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 \r
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 \r
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 \r
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 \r
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 \r
+ DCD ETH_IRQHandler ; Ethernet \r
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line \r
+ DCD CAN2_TX_IRQHandler ; CAN2 TX \r
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0 \r
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1 \r
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE \r
+ DCD OTG_FS_IRQHandler ; USB OTG FS \r
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 \r
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 \r
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 \r
+ DCD USART6_IRQHandler ; USART6 \r
+ DCD I2C3_EV_IRQHandler ; I2C3 event \r
+ DCD I2C3_ER_IRQHandler ; I2C3 error \r
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out \r
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In \r
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI \r
+ DCD OTG_HS_IRQHandler ; USB OTG HS \r
+ DCD DCMI_IRQHandler ; DCMI \r
+ DCD CRYP_IRQHandler ; CRYP crypto \r
+ DCD HASH_RNG_IRQHandler ; Hash and Rng\r
+ DCD FPU_IRQHandler ; FPU\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+ THUMB\r
+ PUBWEAK Reset_Handler\r
+ SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__iar_program_start\r
+ BX R0\r
+\r
+ PUBWEAK NMI_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+NMI_Handler\r
+ B NMI_Handler\r
+\r
+ PUBWEAK HardFault_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+HardFault_Handler\r
+ B HardFault_Handler\r
+\r
+ PUBWEAK MemManage_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+MemManage_Handler\r
+ B MemManage_Handler\r
+\r
+ PUBWEAK BusFault_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+BusFault_Handler\r
+ B BusFault_Handler\r
+\r
+ PUBWEAK UsageFault_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+UsageFault_Handler\r
+ B UsageFault_Handler\r
+\r
+ PUBWEAK SVC_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+SVC_Handler\r
+ B SVC_Handler\r
+\r
+ PUBWEAK DebugMon_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+DebugMon_Handler\r
+ B DebugMon_Handler\r
+\r
+ PUBWEAK PendSV_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+PendSV_Handler\r
+ B PendSV_Handler\r
+\r
+ PUBWEAK SysTick_Handler\r
+ SECTION .text:CODE:REORDER(1)\r
+SysTick_Handler\r
+ B SysTick_Handler\r
+\r
+ PUBWEAK WWDG_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+WWDG_IRQHandler \r
+ B WWDG_IRQHandler\r
+\r
+ PUBWEAK PVD_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+PVD_IRQHandler \r
+ B PVD_IRQHandler\r
+\r
+ PUBWEAK TAMP_STAMP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TAMP_STAMP_IRQHandler \r
+ B TAMP_STAMP_IRQHandler\r
+\r
+ PUBWEAK RTC_WKUP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+RTC_WKUP_IRQHandler \r
+ B RTC_WKUP_IRQHandler\r
+\r
+ PUBWEAK FLASH_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+FLASH_IRQHandler \r
+ B FLASH_IRQHandler\r
+\r
+ PUBWEAK RCC_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+RCC_IRQHandler \r
+ B RCC_IRQHandler\r
+\r
+ PUBWEAK EXTI0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EXTI0_IRQHandler \r
+ B EXTI0_IRQHandler\r
+\r
+ PUBWEAK EXTI1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EXTI1_IRQHandler \r
+ B EXTI1_IRQHandler\r
+\r
+ PUBWEAK EXTI2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EXTI2_IRQHandler \r
+ B EXTI2_IRQHandler\r
+\r
+ PUBWEAK EXTI3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+EXTI3_IRQHandler\r
+ B EXTI3_IRQHandler\r
+\r
+ PUBWEAK EXTI4_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+EXTI4_IRQHandler \r
+ B EXTI4_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream0_IRQHandler \r
+ B DMA1_Stream0_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream1_IRQHandler \r
+ B DMA1_Stream1_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream2_IRQHandler \r
+ B DMA1_Stream2_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream3_IRQHandler \r
+ B DMA1_Stream3_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream4_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream4_IRQHandler \r
+ B DMA1_Stream4_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream5_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream5_IRQHandler \r
+ B DMA1_Stream5_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream6_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream6_IRQHandler \r
+ B DMA1_Stream6_IRQHandler\r
+\r
+ PUBWEAK ADC_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ADC_IRQHandler \r
+ B ADC_IRQHandler\r
+\r
+ PUBWEAK CAN1_TX_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN1_TX_IRQHandler \r
+ B CAN1_TX_IRQHandler\r
+\r
+ PUBWEAK CAN1_RX0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN1_RX0_IRQHandler \r
+ B CAN1_RX0_IRQHandler\r
+\r
+ PUBWEAK CAN1_RX1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN1_RX1_IRQHandler \r
+ B CAN1_RX1_IRQHandler\r
+\r
+ PUBWEAK CAN1_SCE_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN1_SCE_IRQHandler \r
+ B CAN1_SCE_IRQHandler\r
+\r
+ PUBWEAK EXTI9_5_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+EXTI9_5_IRQHandler \r
+ B EXTI9_5_IRQHandler\r
+\r
+ PUBWEAK TIM1_BRK_TIM9_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM1_BRK_TIM9_IRQHandler \r
+ B TIM1_BRK_TIM9_IRQHandler\r
+\r
+ PUBWEAK TIM1_UP_TIM10_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM1_UP_TIM10_IRQHandler \r
+ B TIM1_UP_TIM10_IRQHandler\r
+\r
+ PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM1_TRG_COM_TIM11_IRQHandler \r
+ B TIM1_TRG_COM_TIM11_IRQHandler\r
+ \r
+ PUBWEAK TIM1_CC_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM1_CC_IRQHandler \r
+ B TIM1_CC_IRQHandler\r
+\r
+ PUBWEAK TIM2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM2_IRQHandler \r
+ B TIM2_IRQHandler\r
+\r
+ PUBWEAK TIM3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM3_IRQHandler \r
+ B TIM3_IRQHandler\r
+\r
+ PUBWEAK TIM4_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM4_IRQHandler \r
+ B TIM4_IRQHandler\r
+\r
+ PUBWEAK I2C1_EV_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+I2C1_EV_IRQHandler \r
+ B I2C1_EV_IRQHandler\r
+\r
+ PUBWEAK I2C1_ER_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+I2C1_ER_IRQHandler \r
+ B I2C1_ER_IRQHandler\r
+\r
+ PUBWEAK I2C2_EV_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+I2C2_EV_IRQHandler \r
+ B I2C2_EV_IRQHandler\r
+\r
+ PUBWEAK I2C2_ER_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+I2C2_ER_IRQHandler \r
+ B I2C2_ER_IRQHandler\r
+\r
+ PUBWEAK SPI1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+SPI1_IRQHandler \r
+ B SPI1_IRQHandler\r
+\r
+ PUBWEAK SPI2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+SPI2_IRQHandler \r
+ B SPI2_IRQHandler\r
+\r
+ PUBWEAK USART1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+USART1_IRQHandler \r
+ B USART1_IRQHandler\r
+\r
+ PUBWEAK USART2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+USART2_IRQHandler \r
+ B USART2_IRQHandler\r
+\r
+ PUBWEAK USART3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+USART3_IRQHandler \r
+ B USART3_IRQHandler\r
+\r
+ PUBWEAK EXTI15_10_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+EXTI15_10_IRQHandler \r
+ B EXTI15_10_IRQHandler\r
+\r
+ PUBWEAK RTC_Alarm_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+RTC_Alarm_IRQHandler \r
+ B RTC_Alarm_IRQHandler\r
+\r
+ PUBWEAK OTG_FS_WKUP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+OTG_FS_WKUP_IRQHandler \r
+ B OTG_FS_WKUP_IRQHandler\r
+ \r
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM8_BRK_TIM12_IRQHandler \r
+ B TIM8_BRK_TIM12_IRQHandler\r
+\r
+ PUBWEAK TIM8_UP_TIM13_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM8_UP_TIM13_IRQHandler \r
+ B TIM8_UP_TIM13_IRQHandler\r
+\r
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM8_TRG_COM_TIM14_IRQHandler \r
+ B TIM8_TRG_COM_TIM14_IRQHandler\r
+\r
+ PUBWEAK TIM8_CC_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM8_CC_IRQHandler \r
+ B TIM8_CC_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream7_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA1_Stream7_IRQHandler \r
+ B DMA1_Stream7_IRQHandler\r
+\r
+ PUBWEAK FSMC_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+FSMC_IRQHandler \r
+ B FSMC_IRQHandler\r
+\r
+ PUBWEAK SDIO_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+SDIO_IRQHandler \r
+ B SDIO_IRQHandler\r
+\r
+ PUBWEAK TIM5_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+TIM5_IRQHandler \r
+ B TIM5_IRQHandler\r
+\r
+ PUBWEAK SPI3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+SPI3_IRQHandler \r
+ B SPI3_IRQHandler\r
+\r
+ PUBWEAK UART4_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+UART4_IRQHandler \r
+ B UART4_IRQHandler\r
+\r
+ PUBWEAK UART5_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+UART5_IRQHandler \r
+ B UART5_IRQHandler\r
+\r
+ PUBWEAK TIM6_DAC_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM6_DAC_IRQHandler \r
+ B TIM6_DAC_IRQHandler\r
+\r
+ PUBWEAK TIM7_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+TIM7_IRQHandler \r
+ B TIM7_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream0_IRQHandler \r
+ B DMA2_Stream0_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream1_IRQHandler \r
+ B DMA2_Stream1_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream2_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream2_IRQHandler \r
+ B DMA2_Stream2_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream3_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream3_IRQHandler \r
+ B DMA2_Stream3_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream4_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream4_IRQHandler \r
+ B DMA2_Stream4_IRQHandler\r
+\r
+ PUBWEAK ETH_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+ETH_IRQHandler \r
+ B ETH_IRQHandler\r
+\r
+ PUBWEAK ETH_WKUP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+ETH_WKUP_IRQHandler \r
+ B ETH_WKUP_IRQHandler\r
+\r
+ PUBWEAK CAN2_TX_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN2_TX_IRQHandler \r
+ B CAN2_TX_IRQHandler\r
+\r
+ PUBWEAK CAN2_RX0_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN2_RX0_IRQHandler \r
+ B CAN2_RX0_IRQHandler\r
+\r
+ PUBWEAK CAN2_RX1_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN2_RX1_IRQHandler \r
+ B CAN2_RX1_IRQHandler\r
+\r
+ PUBWEAK CAN2_SCE_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+CAN2_SCE_IRQHandler \r
+ B CAN2_SCE_IRQHandler\r
+\r
+ PUBWEAK OTG_FS_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+OTG_FS_IRQHandler \r
+ B OTG_FS_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream5_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream5_IRQHandler \r
+ B DMA2_Stream5_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream6_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream6_IRQHandler \r
+ B DMA2_Stream6_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream7_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+DMA2_Stream7_IRQHandler \r
+ B DMA2_Stream7_IRQHandler\r
+\r
+ PUBWEAK USART6_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+USART6_IRQHandler \r
+ B USART6_IRQHandler\r
+\r
+ PUBWEAK I2C3_EV_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+I2C3_EV_IRQHandler \r
+ B I2C3_EV_IRQHandler\r
+\r
+ PUBWEAK I2C3_ER_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+I2C3_ER_IRQHandler \r
+ B I2C3_ER_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+OTG_HS_EP1_OUT_IRQHandler \r
+ B OTG_HS_EP1_OUT_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+OTG_HS_EP1_IN_IRQHandler \r
+ B OTG_HS_EP1_IN_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_WKUP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+OTG_HS_WKUP_IRQHandler \r
+ B OTG_HS_WKUP_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+OTG_HS_IRQHandler \r
+ B OTG_HS_IRQHandler\r
+\r
+ PUBWEAK DCMI_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+DCMI_IRQHandler \r
+ B DCMI_IRQHandler\r
+\r
+ PUBWEAK CRYP_IRQHandler\r
+ SECTION .text:CODE:REORDER(1)\r
+CRYP_IRQHandler \r
+ B CRYP_IRQHandler\r
+\r
+ PUBWEAK HASH_RNG_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+HASH_RNG_IRQHandler \r
+ B HASH_RNG_IRQHandler\r
+\r
+ PUBWEAK FPU_IRQHandler\r
+ SECTION .text:CODE:REORDER(1) \r
+FPU_IRQHandler \r
+ B FPU_IRQHandler\r
+\r
+ END\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f4xx.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 24-October-2011\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.\r
+ * This file contains the system clock configuration for STM32F4xx devices,\r
+ * and is generated by the clock configuration tool\r
+ * stm32f4xx_Clock_Configuration_V1.0.0.xls\r
+ * \r
+ * 1. This file provides two functions and one global variable to be called from \r
+ * user application:\r
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier\r
+ * and Divider factors, AHB/APBx prescalers and Flash settings),\r
+ * depending on the configuration made in the clock xls tool. \r
+ * This function is called at startup just after reset and \r
+ * before branch to main program. This call is made inside\r
+ * the "startup_stm32f4xx.s" file.\r
+ *\r
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+ * by the user application to setup the SysTick \r
+ * timer or configure other parameters.\r
+ * \r
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+ * be called whenever the core clock is changed\r
+ * during program execution.\r
+ *\r
+ * 2. After each device reset the HSI (16 MHz) is used as system clock source.\r
+ * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to\r
+ * configure the system clock before to branch to main program.\r
+ *\r
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()\r
+ * function will do nothing and HSI still used as system clock source. User can \r
+ * add some code to deal with this issue inside the SetSysClock() function.\r
+ *\r
+ * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define\r
+ * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or\r
+ * through PLL, and you are using different crystal you have to adapt the HSE\r
+ * value to your own configuration.\r
+ *\r
+ * 5. This file configures the system clock as follows:\r
+ *=============================================================================\r
+ *=============================================================================\r
+ * Supported STM32F4xx device revision | Rev A\r
+ *-----------------------------------------------------------------------------\r
+ * System Clock source | PLL (HSE)\r
+ *-----------------------------------------------------------------------------\r
+ * SYSCLK(Hz) | 150000000\r
+ *-----------------------------------------------------------------------------\r
+ * HCLK(Hz) | 150000000\r
+ *-----------------------------------------------------------------------------\r
+ * AHB Prescaler | 1\r
+ *-----------------------------------------------------------------------------\r
+ * APB1 Prescaler | 4\r
+ *-----------------------------------------------------------------------------\r
+ * APB2 Prescaler | 2\r
+ *-----------------------------------------------------------------------------\r
+ * HSE Frequency(Hz) | 25000000\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_M | 25\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_N | 300\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_P | 2\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_Q | 7\r
+ *-----------------------------------------------------------------------------\r
+ * PLLI2S_N | NA\r
+ *-----------------------------------------------------------------------------\r
+ * PLLI2S_R | NA\r
+ *-----------------------------------------------------------------------------\r
+ * I2S input clock | NA\r
+ *-----------------------------------------------------------------------------\r
+ * VDD(V) | 3.3\r
+ *-----------------------------------------------------------------------------\r
+ * Main regulator output voltage | Scale1 mode\r
+ *-----------------------------------------------------------------------------\r
+ * Flash Latency(WS) | 4\r
+ *-----------------------------------------------------------------------------\r
+ * Prefetch Buffer | OFF\r
+ *-----------------------------------------------------------------------------\r
+ * Instruction cache | ON\r
+ *-----------------------------------------------------------------------------\r
+ * Data cache | ON\r
+ *-----------------------------------------------------------------------------\r
+ * Require 48MHz for USB OTG FS, | Disabled\r
+ * SDIO and RNG clock |\r
+ *-----------------------------------------------------------------------------\r
+ *=============================================================================\r
+ ****************************************************************************** \r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f4xx_system\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup STM32F4xx_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32f4xx.h"\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/************************* Miscellaneous Configuration ************************/\r
+/*!< Uncomment the following line if you need to use external SRAM mounted\r
+ on STM324xG_EVAL board as data memory */\r
+/* #define DATA_IN_ExtSRAM */\r
+\r
+/*!< Uncomment the following line if you need to relocate your vector Table in\r
+ Internal SRAM. */\r
+/* #define VECT_TAB_SRAM */\r
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. \r
+ This value must be a multiple of 0x200. */\r
+/******************************************************************************/\r
+\r
+/************************* PLL Parameters *************************************/\r
+/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */\r
+#define PLL_M 25\r
+#define PLL_N 300\r
+\r
+/* SYSCLK = PLL_VCO / PLL_P */\r
+#define PLL_P 2\r
+\r
+/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */\r
+#define PLL_Q 7\r
+\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Variables\r
+ * @{\r
+ */\r
+\r
+ uint32_t SystemCoreClock = 150000000;\r
+\r
+ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+static void SetSysClock(void);\r
+#ifdef DATA_IN_ExtSRAM\r
+ static void SystemInit_ExtMemCtl(void); \r
+#endif /* DATA_IN_ExtSRAM */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system\r
+ * Initialize the Embedded Flash Interface, the PLL and update the \r
+ * SystemFrequency variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+ /* FPU settings ------------------------------------------------------------*/\r
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */\r
+ #endif\r
+ /* Reset the RCC clock configuration to the default reset state ------------*/\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset CFGR register */\r
+ RCC->CFGR = 0x00000000;\r
+\r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset PLLCFGR register */\r
+ RCC->PLLCFGR = 0x24003010;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+\r
+#ifdef DATA_IN_ExtSRAM\r
+ SystemInit_ExtMemCtl(); \r
+#endif /* DATA_IN_ExtSRAM */\r
+ \r
+ /* Configure the System clock source, PLL Multiplier and Divider factors, \r
+ AHB/APBx prescalers and Flash settings ----------------------------------*/\r
+ SetSysClock();\r
+\r
+ /* Configure the Vector Table location add offset address ------------------*/\r
+#ifdef VECT_TAB_SRAM\r
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r
+#else\r
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock variable according to Clock Register Values.\r
+ * The SystemCoreClock variable contains the core clock (HCLK), it can\r
+ * be used by the user application to setup the SysTick timer or configure\r
+ * other parameters.\r
+ * \r
+ * @note Each time the core clock (HCLK) changes, this function must be called\r
+ * to update SystemCoreClock variable value. Otherwise, any configuration\r
+ * based on this variable will be incorrect. \r
+ * \r
+ * @note - The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ * \r
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
+ * \r
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
+ * \r
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature. \r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value\r
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ * \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\r
+ \r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+\r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock source */\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ case 0x04: /* HSE used as system clock source */\r
+ SystemCoreClock = HSE_VALUE;\r
+ break;\r
+ case 0x08: /* PLL used as system clock source */\r
+\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\r
+ SYSCLK = PLL_VCO / PLL_P\r
+ */ \r
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\r
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r
+ \r
+ if (pllsource != 0)\r
+ {\r
+ /* HSE used as PLL clock source */\r
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r
+ }\r
+ else\r
+ {\r
+ /* HSI used as PLL clock source */\r
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); \r
+ }\r
+\r
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\r
+ SystemCoreClock = pllvco/pllp;\r
+ break;\r
+ default:\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ }\r
+ /* Compute HCLK frequency --------------------------------------------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+ /* HCLK frequency */\r
+ SystemCoreClock >>= tmp;\r
+}\r
+\r
+/**\r
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors, \r
+ * AHB/APBx prescalers and Flash settings\r
+ * @Note This function should be called only once the RCC clock configuration \r
+ * is reset to the default reset state (done in SystemInit() function). \r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClock(void)\r
+{\r
+/******************************************************************************/\r
+/* PLL (clocked by HSE) used as System clock source */\r
+/******************************************************************************/\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* Enable HSE */\r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++;\r
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ }\r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */\r
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+ PWR->CR |= PWR_CR_VOS;\r
+\r
+ /* HCLK = SYSCLK / 1*/\r
+ RCC->CFGR |= RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK2 = HCLK / 2*/\r
+ RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;\r
+ \r
+ /* PCLK1 = HCLK / 4*/\r
+ RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;\r
+\r
+ /* Configure the main PLL */\r
+ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |\r
+ (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);\r
+\r
+ /* Enable the main PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till the main PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+ \r
+ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */\r
+ FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_4WS;\r
+\r
+ /* Select the main PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= RCC_CFGR_SW_PLL;\r
+\r
+ /* Wait till the main PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock\r
+ configuration. User can add here some code to deal with this error */\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Setup the external memory controller. Called in startup_stm32f4xx.s \r
+ * before jump to __main\r
+ * @param None\r
+ * @retval None\r
+ */ \r
+#ifdef DATA_IN_ExtSRAM\r
+/**\r
+ * @brief Setup the external memory controller.\r
+ * Called in startup_stm32f4xx.s before jump to main.\r
+ * This function configures the external SRAM mounted on STM324xG_EVAL board\r
+ * This SRAM will be used as program data memory (including heap and stack).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit_ExtMemCtl(void)\r
+{\r
+/*-- GPIOs Configuration -----------------------------------------------------*/\r
+/*\r
+ +-------------------+--------------------+------------------+------------------+\r
+ + SRAM pins assignment +\r
+ +-------------------+--------------------+------------------+------------------+\r
+ | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | \r
+ | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | \r
+ | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | \r
+ | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | \r
+ | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | \r
+ | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | \r
+ | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | \r
+ | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+\r
+ | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 | \r
+ | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 | \r
+ | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+\r
+ | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |\r
+ | | PE15 <-> FSMC_D12 |\r
+ +-------------------+--------------------+\r
+*/\r
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */\r
+ RCC->AHB1ENR = 0x00000078;\r
+ \r
+ /* Connect PDx pins to FSMC Alternate function */\r
+ GPIOD->AFR[0] = 0x00cc00cc;\r
+ GPIOD->AFR[1] = 0xcc0ccccc;\r
+ /* Configure PDx pins in Alternate function mode */ \r
+ GPIOD->MODER = 0xaaaa0a0a;\r
+ /* Configure PDx pins speed to 100 MHz */ \r
+ GPIOD->OSPEEDR = 0xffff0f0f;\r
+ /* Configure PDx pins Output type to push-pull */ \r
+ GPIOD->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PDx pins */ \r
+ GPIOD->PUPDR = 0x00000000;\r
+\r
+ /* Connect PEx pins to FSMC Alternate function */\r
+ GPIOE->AFR[0] = 0xc00cc0cc;\r
+ GPIOE->AFR[1] = 0xcccccccc;\r
+ /* Configure PEx pins in Alternate function mode */ \r
+ GPIOE->MODER = 0xaaaa828a;\r
+ /* Configure PEx pins speed to 100 MHz */ \r
+ GPIOE->OSPEEDR = 0xffffc3cf;\r
+ /* Configure PEx pins Output type to push-pull */ \r
+ GPIOE->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PEx pins */ \r
+ GPIOE->PUPDR = 0x00000000;\r
+\r
+ /* Connect PFx pins to FSMC Alternate function */\r
+ GPIOF->AFR[0] = 0x00cccccc;\r
+ GPIOF->AFR[1] = 0xcccc0000;\r
+ /* Configure PFx pins in Alternate function mode */ \r
+ GPIOF->MODER = 0xaa000aaa;\r
+ /* Configure PFx pins speed to 100 MHz */ \r
+ GPIOF->OSPEEDR = 0xff000fff;\r
+ /* Configure PFx pins Output type to push-pull */ \r
+ GPIOF->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PFx pins */ \r
+ GPIOF->PUPDR = 0x00000000;\r
+\r
+ /* Connect PGx pins to FSMC Alternate function */\r
+ GPIOG->AFR[0] = 0x00cccccc;\r
+ GPIOG->AFR[1] = 0x000000c0;\r
+ /* Configure PGx pins in Alternate function mode */ \r
+ GPIOG->MODER = 0x00080aaa;\r
+ /* Configure PGx pins speed to 100 MHz */ \r
+ GPIOG->OSPEEDR = 0x000c0fff;\r
+ /* Configure PGx pins Output type to push-pull */ \r
+ GPIOG->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PGx pins */ \r
+ GPIOG->PUPDR = 0x00000000;\r
+ \r
+/*-- FSMC Configuration ------------------------------------------------------*/\r
+ /* Enable the FSMC interface clock */\r
+ RCC->AHB3ENR = 0x00000001;\r
+\r
+ /* Configure and enable Bank1_SRAM2 */\r
+ FSMC_Bank1->BTCR[2] = 0x00001015;\r
+ FSMC_Bank1->BTCR[3] = 0x00010603;\r
+ FSMC_Bank1E->BWTR[2] = 0x0fffffff;\r
+ /*\r
+ Bank1_SRAM2 is configured as follow:\r
+\r
+ p.FSMC_AddressSetupTime = 3;\r
+ p.FSMC_AddressHoldTime = 0;\r
+ p.FSMC_DataSetupTime = 6;\r
+ p.FSMC_BusTurnAroundDuration = 1;\r
+ p.FSMC_CLKDivision = 0;\r
+ p.FSMC_DataLatency = 0;\r
+ p.FSMC_AccessMode = FSMC_AccessMode_A;\r
+\r
+ FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;\r
+ FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;\r
+ FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;\r
+ FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; \r
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
+ FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
+ FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;\r
+ FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;\r
+*/ \r
+}\r
+#endif /* DATA_IN_ExtSRAM */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief Library configuration file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_CONF_H\r
+#define __STM32F4xx_CONF_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Uncomment the line below to enable peripheral header file inclusion */\r
+#include "stm32f4xx_adc.h"\r
+#include "stm32f4xx_can.h"\r
+#include "stm32f4xx_crc.h"\r
+#include "stm32f4xx_cryp.h"\r
+#include "stm32f4xx_dac.h"\r
+#include "stm32f4xx_dbgmcu.h"\r
+#include "stm32f4xx_dcmi.h"\r
+#include "stm32f4xx_dma.h"\r
+#include "stm32f4xx_exti.h"\r
+#include "stm32f4xx_flash.h"\r
+#include "stm32f4xx_fsmc.h"\r
+#include "stm32f4xx_hash.h"\r
+#include "stm32f4xx_gpio.h"\r
+#include "stm32f4xx_i2c.h"\r
+#include "stm32f4xx_iwdg.h"\r
+#include "stm32f4xx_pwr.h"\r
+#include "stm32f4xx_rcc.h"\r
+#include "stm32f4xx_rng.h"\r
+#include "stm32f4xx_rtc.h"\r
+#include "stm32f4xx_sdio.h"\r
+#include "stm32f4xx_spi.h"\r
+#include "stm32f4xx_syscfg.h"\r
+#include "stm32f4xx_tim.h"\r
+#include "stm32f4xx_usart.h"\r
+#include "stm32f4xx_wwdg.h"\r
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/* If an external clock source is used, then the value of the following define\r
+ should be set to the value of the external clock source, else, if no external\r
+ clock is used, keep this define commented */\r
+/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */\r
+\r
+\r
+/* Uncomment the line below to expanse the "assert_param" macro in the\r
+ Standard Peripheral Library drivers code */\r
+/* #define USE_FULL_ASSERT 1 */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef USE_FULL_ASSERT\r
+\r
+/**\r
+ * @brief The assert_param macro is used for function's parameters check.\r
+ * @param expr: If expr is false, it calls assert_failed function\r
+ * which reports the name of the source file and the source\r
+ * line number of the call that failed.\r
+ * If expr is true, it returns no value.\r
+ * @retval None\r
+ */\r
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+ void assert_failed(uint8_t* file, uint32_t line);\r
+#else\r
+ #define assert_param(expr) ((void)0)\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+#endif /* __STM32F4xx_CONF_H */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file Project/STM32F4xx_StdPeriph_Template/stm32f4xx_it.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief Main Interrupt Service Routines.\r
+ * This file provides template for all exceptions handler and\r
+ * peripherals interrupt service routine.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx_it.h"\r
+\r
+/** @addtogroup Template_Project\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/******************************************************************************/\r
+/* Cortex-M4 Processor Exceptions Handlers */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @brief This function handles NMI exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void NMI_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles Hard Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void HardFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Hard Fault exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Memory Manage exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void MemManage_Handler(void)\r
+{\r
+ /* Go to infinite loop when Memory Manage exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Bus Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void BusFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Bus Fault exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Usage Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void UsageFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Usage Fault exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles SVCall exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+__weak void SVC_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles Debug Monitor exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DebugMon_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles PendSVC exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+__weak void PendSV_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles SysTick Handler.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+__weak void SysTick_Handler(void)\r
+{\r
+\r
+}\r
+\r
+/**\r
+ * @brief This function handles EXTI 3 interrupt request.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+__weak void EXTI9_5_IRQHandler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles EXTI 15-10 interrupt request.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+__weak void EXTI15_10_IRQHandler(void)\r
+{\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_it.h \r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief This file contains the headers of the interrupt handlers.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_IT_H\r
+#define __STM32F4xx_IT_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void NMI_Handler(void);\r
+void HardFault_Handler(void);\r
+void MemManage_Handler(void);\r
+void BusFault_Handler(void);\r
+void UsageFault_Handler(void);\r
+void SVC_Handler(void);\r
+void DebugMon_Handler(void);\r
+void PendSV_Handler(void);\r
+void SysTick_Handler(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F4xx_IT_H */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
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