Add autogenerated test source code to the new MicroBlaze project.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1439 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/gensav_cmd.xml b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/gensav_cmd.xml
index 42f1efa6cef00416fa317e7d7e049dc43eba1605..a1d03d35a7b6166ce3f862960849d98d4e0f5be3 100644 (file)
--- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/gensav_cmd.xml
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/gensav_cmd.xml
@@ -1,2 +1,2 @@
 
-<SAV MODE="TREE" VIEW="ADDRESS"/>
\ No newline at end of file
+<SAV MODE="TREE" VIEW="BUSINTERFACE"/>
\ No newline at end of file

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/_xmsgs/platgen.xmsgs b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/_xmsgs/platgen.xmsgs
index a52da26800bbc0653d0328da87e64132973e14b8..3105fb7e21263095c8ad0939c06723682bc2425e 100644 (file)
--- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/_xmsgs/platgen.xmsgs
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/_xmsgs/platgen.xmsgs
@@ -31,7 +31,7 @@
 
 <msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_ethernetlite</arg>, INSTANCE: <arg fmt="%s" index="2">Ethernet_Lite</arg> - <arg fmt="%s" index="3">This design requires design constraints to guarantee performance.\r
 Please refer to the data sheet for details.  \r
-The AXI clock frequency must be greater than or equal to 50 MHz for 100 Mbs Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet operation.</arg> - <arg fmt="%s" index="4">C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_SP605\system.mhs line 324</arg>\r
+The AXI clock frequency must be greater than or equal to 50 MHz for 100 Mbs Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet operation.</arg> - <arg fmt="%s" index="4">C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetLite\PlatformStudioProject\system.mhs line 324</arg>\r
 </msg>\r
 
 <msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">lmb_v10</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_ilmb</arg> - <arg fmt="%s" index="3">tool</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_LMB_NUM_SLAVES</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_a\data\lmb_v10_v2_1_0.mpd line 70</arg> \r
@@ -121,7 +121,7 @@ The AXI clock frequency must be greater than or equal to 50 MHz for 100 Mbs Ethe
 <msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_NUM_INTR_INPUTS</arg> value to <arg fmt="%s" index="6">4</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 71</arg> \r
 </msg>\r
 
-<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_KIND_OF_INTR</arg> value to <arg fmt="%s" index="6">0b11111111111111111111111111111011</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 72</arg> \r
+<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_KIND_OF_INTR</arg> value to <arg fmt="%s" index="6">0b11111111111111111111111111110111</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 72</arg> \r
 </msg>\r
 
 <msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_KIND_OF_EDGE</arg> value to <arg fmt="%s" index="6">0b11111111111111111111111111111111</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 73</arg> \r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport
index 6ff58f4fae0ebf6b121cdc3725e70878803c767b..931bf725afd2cebc97f2a8802d628169c4961574 100644 (file)
--- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport
@@ -1,9 +1,9 @@
 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
  <header>
-  <DateModified>2011-05-31T10:04:43</DateModified>
+  <DateModified>2011-05-31T17:38:56</DateModified>
   <ModuleName>system</ModuleName>
-  <SummaryTimeStamp>2011-05-31T10:04:43</SummaryTimeStamp>
+  <SummaryTimeStamp>2011-05-31T17:38:55</SummaryTimeStamp>
   <SavedFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport</SavedFilePath>
   <FilterFile>filter.filter</FilterFile>
   <SavedFilterFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise</SavedFilterFilePath>

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/system.xml b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/system.xml
index 992659d8bf309a11a33963839e6ed3fa6cae4995..8c4df390560958ad5e021d492ef870714434ee28 100644 (file)
--- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/system.xml
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/system.xml
@@ -1,47 +1,7 @@
-<EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Tue May 31 10:04:42 2011">
 
-  <SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45t" PACKAGE="fgg484" PART="xc6slx45tfgg484-3" SOURCE="C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.xmp" SPEEDGRADE="-3"/>
+<EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Tue May 31 17:38:54 2011">
 
-  <EXTERNALPORTS>
-    <PORT DIR="I" MHS_INDEX="0" NAME="RESET" RSTPOLARITY="1" SIGIS="RST" SIGNAME="RESET"/>
-    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK"/>
-    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="2" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK"/>
-    <PORT DIR="O" MHS_INDEX="3" NAME="RS232_Uart_1_sout" SIGNAME="RS232_Uart_1_sout"/>
-    <PORT DIR="I" MHS_INDEX="4" NAME="RS232_Uart_1_sin" SIGNAME="RS232_Uart_1_sin"/>
-    <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="5" MSB="0" NAME="LEDs_4Bits_TRI_O" RIGHT="3" SIGNAME="LEDs_4Bits_TRI_O"/>
-    <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="6" MSB="3" NAME="Push_Buttons_4Bits_TRI_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I"/>
-    <PORT DIR="O" MHS_INDEX="7" NAME="mcbx_dram_clk" SIGNAME="mcbx_dram_clk"/>
-    <PORT DIR="O" MHS_INDEX="8" NAME="mcbx_dram_clk_n" SIGNAME="mcbx_dram_clk_n"/>
-    <PORT DIR="O" MHS_INDEX="9" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
-    <PORT DIR="O" MHS_INDEX="10" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
-    <PORT DIR="O" MHS_INDEX="11" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
-    <PORT DIR="O" MHS_INDEX="12" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
-    <PORT DIR="O" MHS_INDEX="13" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
-    <PORT DIR="O" MHS_INDEX="14" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
-    <PORT DIR="O" MHS_INDEX="15" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
-    <PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="16" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba"/>
-    <PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="17" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr"/>
-    <PORT DIR="O" MHS_INDEX="18" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
-    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="15" LSB="0" MHS_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq"/>
-    <PORT DIR="IO" MHS_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
-    <PORT DIR="IO" MHS_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
-    <PORT DIR="IO" MHS_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
-    <PORT DIR="IO" MHS_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
-    <PORT DIR="IO" MHS_INDEX="24" NAME="rzq" SIGNAME="rzq"/>
-    <PORT DIR="IO" MHS_INDEX="25" NAME="zio" SIGNAME="zio"/>
-    <PORT DIR="IO" MHS_INDEX="26" NAME="Ethernet_Lite_MDIO" SIGNAME="Ethernet_Lite_MDIO"/>
-    <PORT DIR="O" MHS_INDEX="27" NAME="Ethernet_Lite_MDC" SIGNAME="Ethernet_Lite_MDC"/>
-    <PORT DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="28" MSB="3" NAME="Ethernet_Lite_TXD" RIGHT="0" SIGNAME="Ethernet_Lite_TXD"/>
-    <PORT DIR="O" MHS_INDEX="29" NAME="Ethernet_Lite_TX_EN" SIGNAME="Ethernet_Lite_TX_EN"/>
-    <PORT DIR="I" MHS_INDEX="30" NAME="Ethernet_Lite_TX_CLK" SIGNAME="Ethernet_Lite_TX_CLK"/>
-    <PORT DIR="I" MHS_INDEX="31" NAME="Ethernet_Lite_COL" SIGNAME="Ethernet_Lite_COL"/>
-    <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="32" MSB="3" NAME="Ethernet_Lite_RXD" RIGHT="0" SIGNAME="Ethernet_Lite_RXD"/>
-    <PORT DIR="I" MHS_INDEX="33" NAME="Ethernet_Lite_RX_ER" SIGNAME="Ethernet_Lite_RX_ER"/>
-    <PORT DIR="I" MHS_INDEX="34" NAME="Ethernet_Lite_RX_CLK" SIGNAME="Ethernet_Lite_RX_CLK"/>
-    <PORT DIR="I" MHS_INDEX="35" NAME="Ethernet_Lite_CRS" SIGNAME="Ethernet_Lite_CRS"/>
-    <PORT DIR="I" MHS_INDEX="36" NAME="Ethernet_Lite_RX_DV" SIGNAME="Ethernet_Lite_RX_DV"/>
-    <PORT DIR="O" MHS_INDEX="37" NAME="Ethernet_Lite_PHY_RST_N" SIGNAME="Ethernet_Lite_PHY_RST_N"/>
-  </EXTERNALPORTS>
+  <SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45t" PACKAGE="fgg484" PART="xc6slx45tfgg484-3" SOURCE="C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.xmp" SPEEDGRADE="-3"/>
 
   <MODULES>
     <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4_0" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="0" MODCLASS="BUS" MODTYPE="axi_interconnect">
@@ -50,7 +10,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6"/>
@@ -271,6 +230,7 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4lite_0" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="axi_interconnect">
       <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
@@ -278,7 +238,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6"/>
@@ -499,6 +458,7 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="8.10.a" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="2" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE">
       <DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION>
@@ -506,7 +466,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_10_a/doc/microblaze.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="100000000"/>
@@ -2519,6 +2478,9 @@
           </PORTMAPS>
         </BUSINTERFACE>
       </BUSINTERFACES>
+      <INTERRUPTINFO TYPE="TARGET">
+        <SOURCE INSTANCE="microblaze_0_intc" INTC_INDEX="0"/>
+      </INTERRUPTINFO>
       <MEMORYMAP>
         <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_d_bram_ctrl" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
           <ACCESSROUTE>
@@ -2583,9 +2545,7 @@
         <PERIPHERAL INSTANCE="microblaze_0_intc"/>
         <PERIPHERAL INSTANCE="MCB_DDR3"/>
       </PERIPHERALS>
-      <INTERRUPTINFO TYPE="TARGET">
-        <SOURCE INSTANCE="microblaze_0_intc" INTC_INDEX="0"/>
-      </INTERRUPTINFO>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_ilmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10">
       <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
@@ -2593,7 +2553,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"/>
         <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
@@ -2631,6 +2590,7 @@
       <IOINTERFACES>
         <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
       </IOINTERFACES>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_dlmb" IPTYPE="BUS" MHS_INDEX="4" MODCLASS="BUS" MODTYPE="lmb_v10">
       <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
@@ -2638,7 +2598,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"/>
         <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
@@ -2676,6 +2635,7 @@
       <IOINTERFACES>
         <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
       </IOINTERFACES>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_i_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
       <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
@@ -2683,7 +2643,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff"/>
@@ -2914,6 +2873,7 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_d_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
       <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
@@ -2921,7 +2881,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
         <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff"/>
@@ -3152,6 +3111,7 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="1.00.a" INSTANCE="microblaze_0_bram_block" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="MEMORY" MODTYPE="bram_block">
       <DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
@@ -3159,7 +3119,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x2000"/>
         <PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32"/>
@@ -3207,6 +3166,7 @@
           </PORTMAPS>
         </BUSINTERFACE>
       </BUSINTERFACES>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="3.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
       <DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
@@ -3214,7 +3174,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="t"/>
         <PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4"/>
@@ -3276,6 +3235,7 @@
       <IOINTERFACES>
         <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
       </IOINTERFACES>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="4.01.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="IP" MODTYPE="clock_generator">
       <DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
@@ -3283,7 +3243,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_01_a/doc/clock_generator.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="6slx45t"/>
@@ -3409,6 +3368,7 @@
         <PORT DIR="O" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
       </PORTS>
       <BUSINTERFACES/>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="2.00.b" INSTANCE="debug_module" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="DEBUG" MODTYPE="mdm">
       <DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION>
@@ -3416,7 +3376,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/doc/mdm.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
         <PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2"/>
@@ -3775,6 +3734,7 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="1.01.a" INSTANCE="RS232_Uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="axi_uartlite">
       <DESCRIPTION TYPE="SHORT">AXI UART (Lite)</DESCRIPTION>
@@ -3782,7 +3742,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_uartlite_v1_01_a/doc/axi_uartlite_ds741.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/>
@@ -3862,6 +3821,9 @@
           </PORTMAPS>
         </IOINTERFACE>
       </IOINTERFACES>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="3"/>
+      </INTERRUPTINFO>
       <MEMORYMAP>
         <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
           <SLAVES>
@@ -3869,9 +3831,7 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
-      <INTERRUPTINFO TYPE="SOURCE">
-        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="0"/>
-      </INTERRUPTINFO>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="1.01.a" INSTANCE="LEDs_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
       <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
@@ -3879,7 +3839,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40020000"/>
@@ -3983,6 +3942,7 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="1.01.a" INSTANCE="Push_Buttons_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
       <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
@@ -3990,7 +3950,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40000000"/>
@@ -4087,6 +4046,9 @@
           </PORTMAPS>
         </IOINTERFACE>
       </IOINTERFACES>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="0"/>
+      </INTERRUPTINFO>
       <MEMORYMAP>
         <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
           <SLAVES>
@@ -4094,9 +4056,7 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
-      <INTERRUPTINFO TYPE="SOURCE">
-        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="1"/>
-      </INTERRUPTINFO>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="1.02.a" INSTANCE="MCB_DDR3" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_s6_ddrx">
       <DESCRIPTION TYPE="SHORT">AXI S6 Memory Controller(DDR/DDR2/DDR3)</DESCRIPTION>
@@ -4104,7 +4064,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_s6_ddrx_v1_02_a/doc/axi_s6_ddrx.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER MPD_INDEX="0" NAME="C_MCB_LOC" VALUE="MEMC3"/>
         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_MCB_RZQ_LOC" TYPE="STRING" VALUE="K7"/>
@@ -4856,6 +4815,7 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="1.00.a" INSTANCE="Ethernet_Lite" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="axi_ethernetlite">
       <DESCRIPTION TYPE="SHORT">AXI 10/100 Ethernet MAC Lite</DESCRIPTION>
@@ -4863,7 +4823,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_ethernetlite_v1_00_a/doc/ds787_axi_ethernetlite.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" VALUE="AXI4LITE"/>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
@@ -5024,6 +4983,9 @@
           </PORTMAPS>
         </IOINTERFACE>
       </IOINTERFACES>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="1"/>
+      </INTERRUPTINFO>
       <MEMORYMAP>
         <MEMRANGE BASEDECIMAL="1088421888" BASENAME="C_BASEADDR" BASEVALUE="0x40e00000" HIGHDECIMAL="1088487423" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40e0ffff" MEMTYPE="REGISTER" MINSIZE="0x02000" SIZE="65536" SIZEABRV="64K">
           <SLAVES>
@@ -5031,9 +4993,7 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
-      <INTERRUPTINFO TYPE="SOURCE">
-        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="2"/>
-      </INTERRUPTINFO>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="1.01.a" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="PERIPHERAL" MODTYPE="axi_timer">
       <DESCRIPTION TYPE="SHORT">AXI Timer/Counter</DESCRIPTION>
@@ -5041,7 +5001,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_timer_v1_01_a/doc/axi_timer_ds764.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
@@ -5124,6 +5083,9 @@
           </PORTMAPS>
         </BUSINTERFACE>
       </BUSINTERFACES>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="2"/>
+      </INTERRUPTINFO>
       <MEMORYMAP>
         <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
           <SLAVES>
@@ -5131,9 +5093,7 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
-      <INTERRUPTINFO TYPE="SOURCE">
-        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="3"/>
-      </INTERRUPTINFO>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="1.01.a" INSTANCE="microblaze_0_intc" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc">
       <DESCRIPTION TYPE="SHORT">AXI Interrupt Controller</DESCRIPTION>
@@ -5141,7 +5101,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_intc_v1_01_a/doc/ds747_axi_intc.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
         <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41200000"/>
@@ -5170,7 +5129,7 @@
           <DESCRIPTION>Interrupt Request Output</DESCRIPTION>
         </PORT>
         <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="2" MPD_INDEX="19" MSB="1" NAME="INTR" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="RS232_Uart_1_Interrupt &amp; Push_Buttons_4Bits_IP2INTC_Irpt &amp; Ethernet_Lite_IP2INTC_Irpt &amp; axi_timer_0_Interrupt" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]">
+        <PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="2" MPD_INDEX="19" MSB="1" NAME="INTR" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt &amp; Ethernet_Lite_IP2INTC_Irpt &amp; axi_timer_0_Interrupt &amp; RS232_Uart_1_Interrupt" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]">
           <SIGNALS>
             <SIGNAL NAME="RS232_Uart_1_Interrupt"/>
             <SIGNAL NAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
@@ -5223,6 +5182,13 @@
           </PORTMAPS>
         </BUSINTERFACE>
       </BUSINTERFACES>
+      <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
+        <SOURCE INSTANCE="Push_Buttons_4Bits" PRIORITY="0" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
+        <SOURCE INSTANCE="Ethernet_Lite" PRIORITY="1" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
+        <SOURCE INSTANCE="axi_timer_0" PRIORITY="2" SIGNAME="axi_timer_0_Interrupt"/>
+        <SOURCE INSTANCE="RS232_Uart_1" PRIORITY="3" SIGNAME="RS232_Uart_1_Interrupt"/>
+        <TARGET INSTANCE="microblaze_0"/>
+      </INTERRUPTINFO>
       <MEMORYMAP>
         <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
           <SLAVES>
@@ -5230,14 +5196,49 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
-      <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
-        <SOURCE INSTANCE="RS232_Uart_1" PRIORITY="0" SIGNAME="RS232_Uart_1_Interrupt"/>
-        <SOURCE INSTANCE="Push_Buttons_4Bits" PRIORITY="1" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
-        <SOURCE INSTANCE="Ethernet_Lite" PRIORITY="2" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
-        <SOURCE INSTANCE="axi_timer_0" PRIORITY="3" SIGNAME="axi_timer_0_Interrupt"/>
-        <TARGET INSTANCE="microblaze_0"/>
-      </INTERRUPTINFO>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
   </MODULES>
 
+  <EXTERNALPORTS>
+    <PORT DIR="I" MHS_INDEX="0" NAME="RESET" RSTPOLARITY="1" SIGIS="RST" SIGNAME="RESET"/>
+    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK"/>
+    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="2" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK"/>
+    <PORT DIR="O" MHS_INDEX="3" NAME="RS232_Uart_1_sout" SIGNAME="RS232_Uart_1_sout"/>
+    <PORT DIR="I" MHS_INDEX="4" NAME="RS232_Uart_1_sin" SIGNAME="RS232_Uart_1_sin"/>
+    <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="5" MSB="0" NAME="LEDs_4Bits_TRI_O" RIGHT="3" SIGNAME="LEDs_4Bits_TRI_O"/>
+    <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="6" MSB="3" NAME="Push_Buttons_4Bits_TRI_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I"/>
+    <PORT DIR="O" MHS_INDEX="7" NAME="mcbx_dram_clk" SIGNAME="mcbx_dram_clk"/>
+    <PORT DIR="O" MHS_INDEX="8" NAME="mcbx_dram_clk_n" SIGNAME="mcbx_dram_clk_n"/>
+    <PORT DIR="O" MHS_INDEX="9" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
+    <PORT DIR="O" MHS_INDEX="10" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
+    <PORT DIR="O" MHS_INDEX="11" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
+    <PORT DIR="O" MHS_INDEX="12" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
+    <PORT DIR="O" MHS_INDEX="13" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
+    <PORT DIR="O" MHS_INDEX="14" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
+    <PORT DIR="O" MHS_INDEX="15" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
+    <PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="16" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba"/>
+    <PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="17" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr"/>
+    <PORT DIR="O" MHS_INDEX="18" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
+    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="15" LSB="0" MHS_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq"/>
+    <PORT DIR="IO" MHS_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
+    <PORT DIR="IO" MHS_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
+    <PORT DIR="IO" MHS_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
+    <PORT DIR="IO" MHS_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
+    <PORT DIR="IO" MHS_INDEX="24" NAME="rzq" SIGNAME="rzq"/>
+    <PORT DIR="IO" MHS_INDEX="25" NAME="zio" SIGNAME="zio"/>
+    <PORT DIR="IO" MHS_INDEX="26" NAME="Ethernet_Lite_MDIO" SIGNAME="Ethernet_Lite_MDIO"/>
+    <PORT DIR="O" MHS_INDEX="27" NAME="Ethernet_Lite_MDC" SIGNAME="Ethernet_Lite_MDC"/>
+    <PORT DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="28" MSB="3" NAME="Ethernet_Lite_TXD" RIGHT="0" SIGNAME="Ethernet_Lite_TXD"/>
+    <PORT DIR="O" MHS_INDEX="29" NAME="Ethernet_Lite_TX_EN" SIGNAME="Ethernet_Lite_TX_EN"/>
+    <PORT DIR="I" MHS_INDEX="30" NAME="Ethernet_Lite_TX_CLK" SIGNAME="Ethernet_Lite_TX_CLK"/>
+    <PORT DIR="I" MHS_INDEX="31" NAME="Ethernet_Lite_COL" SIGNAME="Ethernet_Lite_COL"/>
+    <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="32" MSB="3" NAME="Ethernet_Lite_RXD" RIGHT="0" SIGNAME="Ethernet_Lite_RXD"/>
+    <PORT DIR="I" MHS_INDEX="33" NAME="Ethernet_Lite_RX_ER" SIGNAME="Ethernet_Lite_RX_ER"/>
+    <PORT DIR="I" MHS_INDEX="34" NAME="Ethernet_Lite_RX_CLK" SIGNAME="Ethernet_Lite_RX_CLK"/>
+    <PORT DIR="I" MHS_INDEX="35" NAME="Ethernet_Lite_CRS" SIGNAME="Ethernet_Lite_CRS"/>
+    <PORT DIR="I" MHS_INDEX="36" NAME="Ethernet_Lite_RX_DV" SIGNAME="Ethernet_Lite_RX_DV"/>
+    <PORT DIR="O" MHS_INDEX="37" NAME="Ethernet_Lite_PHY_RST_N" SIGNAME="Ethernet_Lite_PHY_RST_N"/>
+  </EXTERNALPORTS>
+
 </EDKSYSTEM>
\ No newline at end of file

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.filters b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.filters
index db9a31b74ca726ea8081dbfa3a21ea446082de9e..75b425ae1d048edb7a557e6bb537f4f16e6c67a0 100644 (file)
--- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.filters
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.filters
@@ -1,3 +1,4 @@
+
 <FILTERS>
 
   <IDENTIFICATION VERSION="1.2" XTLVERSION="1.2"/>
@@ -93,8 +94,8 @@
   </SET>
 
   <SET CLASS="PROJECT" VIEW_ID="PORT">
-    <HEADERS>
-      <VARIABLE COL_WIDTH="50" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
+    <HEADERS HSCROLL="0" VSCROLL="0">
+      <VARIABLE COL_INDEX="0" COL_WIDTH="400" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
     </HEADERS>
     <SET CLASS="FILTER_GROUP" ID="By Interface" IS_EXPANDED="TRUE">
       <VARIABLE NAME="By Interface" VALUE="By Interface" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.gui b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.gui
index cc7d6cf4aff21576725a2252cba2794e192e9678..9425e448037002857cc4251c179de6085e15a3b3 100644 (file)
--- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.gui
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.gui
@@ -9,14 +9,14 @@
       <VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
       <VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
       <VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="4" COL_WIDTH="154" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="4" COL_WIDTH="492" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
       <VARIABLE COL_INDEX="5" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
       <VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
     </HEADERS>
     <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
     <STATUS>
       <SELECTIONS>
-        <VARIABLE ID="microblaze_0"/>
+        <VARIABLE ID="microblaze_0_intc"/>
       </SELECTIONS>
     </STATUS>
     <SEQUENCES IS_DEF_SEQUENCES="TRUE">
@@ -83,37 +83,74 @@
   </SET>
 
   <SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="PORT">
-    <HEADERS>
-      <VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
+    <HEADERS HSCROLL="0" VSCROLL="0">
+      <VARIABLE COL_INDEX="0" COL_WIDTH="217" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="1" COL_WIDTH="652" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="5" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="7" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="8" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
       <VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
       <VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
     </HEADERS>
     <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
+    <SET ID="microblaze_0" IS_EXPANDED="TRUE"/>
+    <SET ID="RS232_Uart_1" IS_EXPANDED="TRUE"/>
+    <SET ID="microblaze_0_intc" IS_EXPANDED="TRUE">
+      <SET ID="S_AXI" IS_EXPANDED="TRUE"/>
+    </SET>
+    <STATUS>
+      <SELECTIONS>
+        <VARIABLE ID="IRQ" PARENT="microblaze_0_intc"/>
+      </SELECTIONS>
+    </STATUS>
+    <SEQUENCES IS_DEF_SEQUENCES="TRUE">
+      <VARIABLE ID="ExternalPorts" ROW_INDEX="0"/>
+      <VARIABLE ID="axi4_0" ROW_INDEX="1"/>
+      <VARIABLE ID="axi4lite_0" ROW_INDEX="2"/>
+      <VARIABLE ID="microblaze_0" IS_EXPANDED="TRUE" ROW_INDEX="5"/>
+      <VARIABLE ID="microblaze_0_ilmb" ROW_INDEX="4"/>
+      <VARIABLE ID="microblaze_0_dlmb" ROW_INDEX="3"/>
+      <VARIABLE ID="microblaze_0_i_bram_ctrl" ROW_INDEX="8"/>
+      <VARIABLE ID="microblaze_0_d_bram_ctrl" ROW_INDEX="7"/>
+      <VARIABLE ID="microblaze_0_bram_block" ROW_INDEX="6"/>
+      <VARIABLE ID="proc_sys_reset_0" ROW_INDEX="18"/>
+      <VARIABLE ID="clock_generator_0" ROW_INDEX="17"/>
+      <VARIABLE ID="debug_module" ROW_INDEX="10"/>
+      <VARIABLE ID="RS232_Uart_1" IS_EXPANDED="TRUE" ROW_INDEX="16"/>
+      <VARIABLE ID="LEDs_4Bits" ROW_INDEX="13"/>
+      <VARIABLE ID="Push_Buttons_4Bits" ROW_INDEX="14"/>
+      <VARIABLE ID="MCB_DDR3" ROW_INDEX="9"/>
+      <VARIABLE ID="Ethernet_Lite" ROW_INDEX="12"/>
+      <VARIABLE ID="axi_timer_0" ROW_INDEX="15"/>
+      <VARIABLE ID="microblaze_0_intc" IS_EXPANDED="TRUE" ROW_INDEX="11"/>
+    </SEQUENCES>
   </SET>
 
   <SET CLASS="PROJECT" DISPLAYMODE="FOCUS_TREE" VIEW_ID="PORT">
-    <HEADERS>
-      <VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
+    <HEADERS HSCROLL="0" VSCROLL="0">
+      <VARIABLE COL_INDEX="0" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="5" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="7" COL_WIDTH="192" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="8" COL_WIDTH="200" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
       <VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
       <VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
     </HEADERS>
     <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
+    <SET ID="microblaze_0_intc" IS_EXPANDED="TRUE"/>
+    <STATUS>
+      <SELECTIONS>
+        <VARIABLE ID="microblaze_0_intc"/>
+      </SELECTIONS>
+    </STATUS>
   </SET>
 
   <SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="PORT">
@@ -166,10 +203,11 @@
       <VARIABLE COL_INDEX="8" IS_VISIBLE="FALSE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
       <VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
       <VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="Address Type" VIEWTYPE="HEADER"/>
-      <VARIABLE COL_INDEX="9" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Lock" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="9" COL_WIDTH="605" IS_VISIBLE="TRUE" VIEWDISP="Lock" VIEWTYPE="HEADER"/>
     </HEADERS>
+    <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
     <SET ID="microblaze_0" IS_EXPANDED="TRUE"/>
-    <STATUS IS_EXPANDED="TRUE">
+    <STATUS>
       <SELECTIONS/>
     </STATUS>
   </SET>

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/implementation/system_summary.html b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/implementation/system_summary.html
index 0ff23f2cf10afdbc8ee7a4db1109d2a92c654586..a1ba6df8171d70b8b3241acd6a975fff439fa2db 100644 (file)
--- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/implementation/system_summary.html
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/implementation/system_summary.html
@@ -32,11 +32,7 @@
 <TR ALIGN=LEFT><TD>Libgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 <TR ALIGN=LEFT><TD>Simgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 <TR ALIGN=LEFT><TD>BitInit Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>System Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-</TABLE>
-&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>XPS Synthesis Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKSynthesisSumary"><B>[-]</B></a></TD></TR>
-<TR BGCOLOR='#FFFF99'><TD><B>Report</B></TD><TD><B>Generated</B></TD><TD><B>Flip Flops Used</B></TD><TD><B>LUTs Used</B></TD><TD><B>BRAMS Used</B></TD><TD COLSPAN='2'><B>Errors</B></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject\system.log'>System Log File</A></TD><TD>Tue 31. May 18:23:42 2011</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 </TABLE>
 
 
@@ -62,5 +58,5 @@
 </TABLE>
 
 
-<br><center><b>Date Generated:</b> 05/31/2011 - 10:04:43</center>
+<br><center><b>Date Generated:</b> 05/31/2011 - 18:23:42</center>
 </BODY></HTML>
\ No newline at end of file

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.mhs b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.mhs
index c4fd90865e661d0eb97e023100124c4f01ab0159..a0cc03c0571ddaf1cecf41051dcdfd04646dd5d7 100644 (file)
--- a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.mhs
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.mhs
@@ -382,6 +382,6 @@ BEGIN axi_intc
  BUS_INTERFACE S_AXI = axi4lite_0\r
  PORT IRQ = microblaze_0_interrupt\r
  PORT S_AXI_ACLK = clk_50_0000MHzPLL0\r
- PORT INTR = RS232_Uart_1_Interrupt & Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt\r
+ PORT INTR = Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt & RS232_Uart_1_Interrupt\r
 END\r
 \r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/HardwareWithEthernetLite/.project b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/HardwareWithEthernetLite/.project
new file mode 100644 (file)
index 0000000..0060b40
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/HardwareWithEthernetLite/.project
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+       <name>HardwareWithEthernetLite</name>\r
+       <comment></comment>\r
+       <projects>\r
+       </projects>\r
+       <buildSpec>\r
+       </buildSpec>\r
+       <natures>\r
+               <nature>com.xilinx.sdk.hw.HwProject</nature>\r
+       </natures>\r
+</projectDescription>\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/HardwareWithEthernetLite/download.bit b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/HardwareWithEthernetLite/download.bit
new file mode 100644 (file)
index 0000000..f8531f0
Binary files /dev/null and b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/HardwareWithEthernetLite/download.bit differ

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/HardwareWithEthernetLite/system.bit b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/HardwareWithEthernetLite/system.bit
new file mode 100644 (file)
index 0000000..b32ce28
Binary files /dev/null and b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/HardwareWithEthernetLite/system.bit differ

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/HardwareWithEthernetLite/system.xml b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/HardwareWithEthernetLite/system.xml
new file mode 100644 (file)
index 0000000..b3326f4
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/HardwareWithEthernetLite/system.xml
@@ -0,0 +1,6258 @@
+
+<EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Tue May 31 18:29:48 2011">
+
+  <SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45t" PACKAGE="fgg484" PART="xc6slx45tfgg484-3" SOURCE="C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.xmp" SPEEDGRADE="-3"/>
+
+  <EXTERNALPORTS>
+    <PORT DIR="I" MHS_INDEX="0" NAME="RESET" RSTPOLARITY="1" SIGIS="RST" SIGNAME="RESET"/>
+    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK"/>
+    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="2" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK"/>
+    <PORT DIR="O" MHS_INDEX="3" NAME="RS232_Uart_1_sout" SIGNAME="RS232_Uart_1_sout"/>
+    <PORT DIR="I" MHS_INDEX="4" NAME="RS232_Uart_1_sin" SIGNAME="RS232_Uart_1_sin"/>
+    <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="5" MSB="0" NAME="LEDs_4Bits_TRI_O" RIGHT="3" SIGNAME="LEDs_4Bits_TRI_O"/>
+    <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="6" MSB="3" NAME="Push_Buttons_4Bits_TRI_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I"/>
+    <PORT DIR="O" MHS_INDEX="7" NAME="mcbx_dram_clk" SIGIS="CLK" SIGNAME="mcbx_dram_clk"/>
+    <PORT DIR="O" MHS_INDEX="8" NAME="mcbx_dram_clk_n" SIGIS="CLK" SIGNAME="mcbx_dram_clk_n"/>
+    <PORT DIR="O" MHS_INDEX="9" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
+    <PORT DIR="O" MHS_INDEX="10" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
+    <PORT DIR="O" MHS_INDEX="11" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
+    <PORT DIR="O" MHS_INDEX="12" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
+    <PORT DIR="O" MHS_INDEX="13" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
+    <PORT DIR="O" MHS_INDEX="14" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
+    <PORT DIR="O" MHS_INDEX="15" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
+    <PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="16" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba"/>
+    <PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="17" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr"/>
+    <PORT DIR="O" MHS_INDEX="18" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
+    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="15" LSB="0" MHS_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq"/>
+    <PORT DIR="IO" MHS_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
+    <PORT DIR="IO" MHS_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
+    <PORT DIR="IO" MHS_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
+    <PORT DIR="IO" MHS_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
+    <PORT DIR="IO" MHS_INDEX="24" NAME="rzq" SIGNAME="rzq"/>
+    <PORT DIR="IO" MHS_INDEX="25" NAME="zio" SIGNAME="zio"/>
+    <PORT DIR="IO" MHS_INDEX="26" NAME="Ethernet_Lite_MDIO" SIGNAME="Ethernet_Lite_MDIO"/>
+    <PORT DIR="O" MHS_INDEX="27" NAME="Ethernet_Lite_MDC" SIGNAME="Ethernet_Lite_MDC"/>
+    <PORT DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="28" MSB="3" NAME="Ethernet_Lite_TXD" RIGHT="0" SIGNAME="Ethernet_Lite_TXD"/>
+    <PORT DIR="O" MHS_INDEX="29" NAME="Ethernet_Lite_TX_EN" SIGNAME="Ethernet_Lite_TX_EN"/>
+    <PORT DIR="I" MHS_INDEX="30" NAME="Ethernet_Lite_TX_CLK" SIGNAME="Ethernet_Lite_TX_CLK"/>
+    <PORT DIR="I" MHS_INDEX="31" NAME="Ethernet_Lite_COL" SIGNAME="Ethernet_Lite_COL"/>
+    <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="32" MSB="3" NAME="Ethernet_Lite_RXD" RIGHT="0" SIGNAME="Ethernet_Lite_RXD"/>
+    <PORT DIR="I" MHS_INDEX="33" NAME="Ethernet_Lite_RX_ER" SIGNAME="Ethernet_Lite_RX_ER"/>
+    <PORT DIR="I" MHS_INDEX="34" NAME="Ethernet_Lite_RX_CLK" SIGNAME="Ethernet_Lite_RX_CLK"/>
+    <PORT DIR="I" MHS_INDEX="35" NAME="Ethernet_Lite_CRS" SIGNAME="Ethernet_Lite_CRS"/>
+    <PORT DIR="I" MHS_INDEX="36" NAME="Ethernet_Lite_RX_DV" SIGNAME="Ethernet_Lite_RX_DV"/>
+    <PORT DIR="O" MHS_INDEX="37" NAME="Ethernet_Lite_PHY_RST_N" SIGNAME="Ethernet_Lite_PHY_RST_N"/>
+  </EXTERNALPORTS>
+
+  <MODULES>
+    <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4_0" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="0" MODCLASS="BUS" MODTYPE="axi_interconnect">
+      <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Base Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="2">
+          <DESCRIPTION>Number of Slave Slots </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Number of Master Slots </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>AXI ID Widgth </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Widgth </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
+          <DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
+          <DESCRIPTION>Master AXI Data Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>AXI Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Master AXI Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff00000000c0000000">
+          <DESCRIPTION>Master AXI Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c7ffffff">
+          <DESCRIPTION>Master AXI High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000">
+          <DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e100">
+          <DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100">
+          <DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111101">
+          <DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Propagate USER Signals</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="5">
+          <DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="5">
+          <DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>WUSER Signal Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>RUSER Signal Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>BUSER Signal Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003">
+          <DESCRIPTION>AXI Connectivity</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111100">
+          <DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110">
+          <DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000020">
+          <DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000200000002">
+          <DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004">
+          <DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004">
+          <DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Secure</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
+          <DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
+          <DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
+          <DESCRIPTION>Slave AXI W Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
+          <DESCRIPTION>Slave AXI R Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001">
+          <DESCRIPTION>Slave AXI B Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Master AXI AW Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Master AXI AR Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Master AXI W Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Master AXI R Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Master AXI B Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Interconnect Architecture</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Generate Interrupts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
+          <DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
+          <DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Simulation debug</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="interconnect_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="2" MSB="1" NAME="S_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARESETN" DIR="O" MPD_INDEX="3" NAME="M_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT DEF_SIGNAME="clk_100_0000MHzPLL0&amp;clk_100_0000MHzPLL0" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="5" MSB="1" NAME="S_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0&amp;clk_100_0000MHzPLL0" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
+          <SIGNALS>
+            <SIGNAL NAME="clk_100_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_100_0000MHzPLL0"/>
+          </SIGNALS>
+        </PORT>
+        <PORT DEF_SIGNAME="axi4_0_S_AWID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="6" MSB="1" NAME="S_AXI_AWID" RIGHT="0" SIGNAME="axi4_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="7" MSB="63" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="8" MSB="15" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="9" MSB="5" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="11" MSB="3" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="12" MSB="7" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="13" MSB="5" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="14" MSB="7" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWUSER" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="15" MSB="9" NAME="S_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_AWVALID" RIGHT="0" SIGNAME="axi4_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_AWREADY" RIGHT="0" SIGNAME="axi4_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="18" MSB="63" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="19" MSB="7" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_WLAST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_WLAST" RIGHT="0" SIGNAME="axi4_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_WUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="21" MSB="1" NAME="S_AXI_WUSER" RIGHT="0" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_WVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="22" MSB="1" NAME="S_AXI_WVALID" RIGHT="0" SIGNAME="axi4_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_WREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_WREADY" RIGHT="0" SIGNAME="axi4_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_BID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_BID" RIGHT="0" SIGNAME="axi4_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_BUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BUSER" RIGHT="0" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_BVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="27" MSB="1" NAME="S_AXI_BVALID" RIGHT="0" SIGNAME="axi4_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_BREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="28" MSB="1" NAME="S_AXI_BREADY" RIGHT="0" SIGNAME="axi4_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="29" MSB="1" NAME="S_AXI_ARID" RIGHT="0" SIGNAME="axi4_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="30" MSB="63" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="31" MSB="15" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="32" MSB="5" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="33" MSB="3" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="35" MSB="7" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="36" MSB="5" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="37" MSB="7" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARUSER" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="38" MSB="9" NAME="S_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="39" MSB="1" NAME="S_AXI_ARVALID" RIGHT="0" SIGNAME="axi4_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="40" MSB="1" NAME="S_AXI_ARREADY" RIGHT="0" SIGNAME="axi4_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_RID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="41" MSB="1" NAME="S_AXI_RID" RIGHT="0" SIGNAME="axi4_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="42" MSB="63" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="43" MSB="3" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_RLAST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RLAST" RIGHT="0" SIGNAME="axi4_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_RUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="45" MSB="1" NAME="S_AXI_RUSER" RIGHT="0" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_RVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="46" MSB="1" NAME="S_AXI_RVALID" RIGHT="0" SIGNAME="axi4_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_RREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="47" MSB="1" NAME="S_AXI_RREADY" RIGHT="0" SIGNAME="axi4_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="48" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWID" DIR="O" MPD_INDEX="49" NAME="M_AXI_AWID" SIGNAME="axi4_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="52" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="53" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="55" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="56" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="57" MSB="3" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="59" MSB="4" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWVALID" DIR="O" MPD_INDEX="60" NAME="M_AXI_AWVALID" SIGNAME="axi4_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWREADY" DIR="I" MPD_INDEX="61" NAME="M_AXI_AWREADY" SIGNAME="axi4_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_WID" DIR="O" MPD_INDEX="62" NAME="M_AXI_WID" SIGNAME="axi4_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="64" MSB="3" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_WLAST" DIR="O" MPD_INDEX="65" NAME="M_AXI_WLAST" SIGNAME="axi4_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_WUSER" DIR="O" MPD_INDEX="66" NAME="M_AXI_WUSER" SIGNAME="axi4_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_WVALID" DIR="O" MPD_INDEX="67" NAME="M_AXI_WVALID" SIGNAME="axi4_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_WREADY" DIR="I" MPD_INDEX="68" NAME="M_AXI_WREADY" SIGNAME="axi4_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_BID" DIR="I" MPD_INDEX="69" NAME="M_AXI_BID" SIGNAME="axi4_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_BUSER" DIR="I" MPD_INDEX="71" NAME="M_AXI_BUSER" SIGNAME="axi4_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_BVALID" DIR="I" MPD_INDEX="72" NAME="M_AXI_BVALID" SIGNAME="axi4_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_BREADY" DIR="O" MPD_INDEX="73" NAME="M_AXI_BREADY" SIGNAME="axi4_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARID" DIR="O" MPD_INDEX="74" NAME="M_AXI_ARID" SIGNAME="axi4_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="75" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="76" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="77" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="78" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="79" MSB="1" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="81" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="82" MSB="3" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="83" MSB="3" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="84" MSB="4" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARVALID" DIR="O" MPD_INDEX="85" NAME="M_AXI_ARVALID" SIGNAME="axi4_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARREADY" DIR="I" MPD_INDEX="86" NAME="M_AXI_ARREADY" SIGNAME="axi4_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_RID" DIR="I" MPD_INDEX="87" NAME="M_AXI_RID" SIGNAME="axi4_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="88" MSB="31" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="89" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_RLAST" DIR="I" MPD_INDEX="90" NAME="M_AXI_RLAST" SIGNAME="axi4_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_RUSER" DIR="I" MPD_INDEX="91" NAME="M_AXI_RUSER" SIGNAME="axi4_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_RVALID" DIR="I" MPD_INDEX="92" NAME="M_AXI_RVALID" SIGNAME="axi4_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_RREADY" DIR="O" MPD_INDEX="93" NAME="M_AXI_RREADY" SIGNAME="axi4_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="interconnect_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+    </MODULE>
+    <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4lite_0" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="axi_interconnect">
+      <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Base Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Number of Slave Slots </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="7">
+          <DESCRIPTION>Number of Master Slots </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>AXI ID Widgth </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Widgth </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
+          <DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
+          <DESCRIPTION>Master AXI Data Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002">
+          <DESCRIPTION>AXI Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000002000000020000000200000002000000020000000200000002">
+          <DESCRIPTION>Master AXI Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041200000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041c00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040e00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040020000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040600000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000074800000">
+          <DESCRIPTION>Master AXI Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004120ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000041c0ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040e0ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004002ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004060ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007480ffff">
+          <DESCRIPTION>Master AXI High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100">
+          <DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000102faf08002faf08002faf08002faf08002faf08002faf08002faf080">
+          <DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="50000000">
+          <DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Propagate USER Signals</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>WUSER Signal Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>RUSER Signal Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>BUSER Signal Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff">
+          <DESCRIPTION>AXI Connectivity</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110">
+          <DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111101111">
+          <DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Secure</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Slave AXI W Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Slave AXI R Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Slave AXI B Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Master AXI AW Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Master AXI AR Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Master AXI W Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Master AXI R Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Master AXI B Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Interconnect Architecture</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Generate Interrupts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
+          <DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
+          <DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Simulation debug</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/>
+        <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4lite_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="3" MSB="6" NAME="M_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWID" DIR="I" MPD_INDEX="6" NAME="S_AXI_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi4lite_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="18" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="19" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="I" MPD_INDEX="20" NAME="S_AXI_WLAST" SIGNAME="axi4lite_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_WUSER" DIR="I" MPD_INDEX="21" NAME="S_AXI_WUSER" SIGNAME="axi4lite_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="I" MPD_INDEX="22" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="O" MPD_INDEX="23" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_BID" DIR="O" MPD_INDEX="24" NAME="S_AXI_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_BUSER" DIR="O" MPD_INDEX="26" NAME="S_AXI_BUSER" SIGNAME="axi4lite_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="O" MPD_INDEX="27" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="I" MPD_INDEX="28" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARID" DIR="I" MPD_INDEX="29" NAME="S_AXI_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="30" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="31" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="32" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="33" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="35" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="36" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="37" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARUSER" DIR="I" MPD_INDEX="38" NAME="S_AXI_ARUSER" SIGNAME="axi4lite_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="O" MPD_INDEX="40" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_RID" DIR="O" MPD_INDEX="41" NAME="S_AXI_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="42" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="43" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="O" MPD_INDEX="44" NAME="S_AXI_RLAST" SIGNAME="axi4lite_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_RUSER" DIR="O" MPD_INDEX="45" NAME="S_AXI_RUSER" SIGNAME="axi4lite_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="O" MPD_INDEX="46" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="I" MPD_INDEX="47" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="48" MSB="6" NAME="M_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
+          <SIGNALS>
+            <SIGNAL NAME="clk_50_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_50_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_50_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_50_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_50_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_50_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_50_0000MHzPLL0"/>
+          </SIGNALS>
+        </PORT>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="49" MSB="6" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi4lite_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="50" MSB="223" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="55" LSB="0" MPD_INDEX="51" MSB="55" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="52" MSB="20" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="53" MSB="13" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="54" MSB="13" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="55" MSB="27" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="56" MSB="20" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="57" MSB="27" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4lite_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="58" MSB="27" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="59" MSB="6" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4lite_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="60" MSB="6" NAME="M_AXI_AWVALID" RIGHT="0" SIGNAME="axi4lite_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="61" MSB="6" NAME="M_AXI_AWREADY" RIGHT="0" SIGNAME="axi4lite_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="62" MSB="6" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi4lite_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="63" MSB="223" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="64" MSB="27" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_WLAST" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="65" MSB="6" NAME="M_AXI_WLAST" RIGHT="0" SIGNAME="axi4lite_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_WUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="66" MSB="6" NAME="M_AXI_WUSER" RIGHT="0" SIGNAME="axi4lite_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="67" MSB="6" NAME="M_AXI_WVALID" RIGHT="0" SIGNAME="axi4lite_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="68" MSB="6" NAME="M_AXI_WREADY" RIGHT="0" SIGNAME="axi4lite_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="69" MSB="6" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi4lite_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="70" MSB="13" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_BUSER" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="71" MSB="6" NAME="M_AXI_BUSER" RIGHT="0" SIGNAME="axi4lite_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="72" MSB="6" NAME="M_AXI_BVALID" RIGHT="0" SIGNAME="axi4lite_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="73" MSB="6" NAME="M_AXI_BREADY" RIGHT="0" SIGNAME="axi4lite_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="74" MSB="6" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi4lite_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="75" MSB="223" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="55" LSB="0" MPD_INDEX="76" MSB="55" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="77" MSB="20" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="78" MSB="13" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="79" MSB="13" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="80" MSB="27" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="81" MSB="20" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="82" MSB="27" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4lite_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="83" MSB="27" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="84" MSB="6" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4lite_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="85" MSB="6" NAME="M_AXI_ARVALID" RIGHT="0" SIGNAME="axi4lite_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="86" MSB="6" NAME="M_AXI_ARREADY" RIGHT="0" SIGNAME="axi4lite_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="87" MSB="6" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi4lite_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="88" MSB="223" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="89" MSB="13" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_RLAST" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="90" MSB="6" NAME="M_AXI_RLAST" RIGHT="0" SIGNAME="axi4lite_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_RUSER" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="91" MSB="6" NAME="M_AXI_RUSER" RIGHT="0" SIGNAME="axi4lite_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="92" MSB="6" NAME="M_AXI_RVALID" RIGHT="0" SIGNAME="axi4lite_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="93" MSB="6" NAME="M_AXI_RREADY" RIGHT="0" SIGNAME="axi4lite_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+    </MODULE>
+    <MODULE HWVERSION="8.10.a" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="2" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE">
+      <DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">The MicroBlaze 32 bit soft processor</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_10_a/doc/microblaze.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="100000000"/>
+        <PARAMETER MPD_INDEX="2" NAME="C_DATA_SIZE" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="3" NAME="C_DYNAMIC_BUS_SIZING" TYPE="integer" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_INSTANCE" TYPE="string" VALUE="microblaze_0"/>
+        <PARAMETER MPD_INDEX="6" NAME="C_FAULT_TOLERANT" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Fault Tolerance Support</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_ECC_USE_CE_EXCEPTION" TYPE="integer" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_ENDIANNESS" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="9" NAME="C_AREA_OPTIMIZED" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Select implementation to optimize area (with lower instruction throughput)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_OPTIMIZATION" TYPE="integer" VALUE="0"/>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="11" NAME="C_INTERCONNECT" TYPE="integer" VALUE="2">
+          <DESCRIPTION>Select Bus Interfaces</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="12" NAME="C_STREAM_INTERCONNECT" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Select Stream Interfaces</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="13" NAME="C_DPLB_DWIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="14" NAME="C_DPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="15" NAME="C_DPLB_BURST_EN" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="16" NAME="C_DPLB_P2P" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="17" NAME="C_IPLB_DWIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="18" NAME="C_IPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="19" NAME="C_IPLB_BURST_EN" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="20" NAME="C_IPLB_P2P" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="21" NAME="C_M_AXI_DP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="22" NAME="C_M_AXI_DP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="23" NAME="C_M_AXI_DP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_DP_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_DP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="26" NAME="C_M_AXI_DP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="27" NAME="C_M_AXI_DP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="28" NAME="C_M_AXI_DP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
+        <PARAMETER MPD_INDEX="29" NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="30" NAME="C_INTERCONNECT_M_AXI_DP_READ_ISSUING" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="31" NAME="C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="32" NAME="C_M_AXI_IP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="33" NAME="C_M_AXI_IP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_IP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="35" NAME="C_M_AXI_IP_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="36" NAME="C_M_AXI_IP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="37" NAME="C_M_AXI_IP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="38" NAME="C_M_AXI_IP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_IP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
+        <PARAMETER MPD_INDEX="40" NAME="C_INTERCONNECT_M_AXI_IP_READ_ISSUING" TYPE="integer" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="41" NAME="C_D_AXI" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="42" NAME="C_D_PLB" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="43" NAME="C_D_LMB" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="44" NAME="C_I_AXI" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="45" NAME="C_I_PLB" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="46" NAME="C_I_LMB" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="47" NAME="C_USE_MSR_INSTR" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Additional Machine Status Register Instructions</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="48" NAME="C_USE_PCMP_INSTR" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Pattern Comparator</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="49" NAME="C_USE_BARREL" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Barrel Shifter</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="41" MPD_INDEX="50" NAME="C_USE_DIV" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Integer Divider</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="51" NAME="C_USE_HW_MUL" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Integer Multiplier</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="52" NAME="C_USE_FPU" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Floating Point Unit</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="40" MPD_INDEX="53" NAME="C_UNALIGNED_EXCEPTIONS" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Unaligned Data Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="38" MPD_INDEX="54" NAME="C_ILL_OPCODE_EXCEPTION" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Illegal Instruction Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="36" MPD_INDEX="55" NAME="C_M_AXI_I_BUS_EXCEPTION" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Instruction-side AXI Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="37" MPD_INDEX="56" NAME="C_M_AXI_D_BUS_EXCEPTION" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Data-side AXI Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="57" NAME="C_IPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Instruction-side PLB Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="58" NAME="C_DPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Data-side PLB Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="35" MPD_INDEX="59" NAME="C_DIV_ZERO_EXCEPTION" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Integer Divide Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="34" MPD_INDEX="60" NAME="C_FPU_EXCEPTION" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Floating Point Unit Exceptions</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="61" NAME="C_FSL_EXCEPTION" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Stream Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="62" NAME="C_USE_STACK_PROTECTION" TYPE="integer" VALUE="0">
+          <DESCRIPTION>&lt;qt&gt;Enable stack protection&lt;/qt&gt;</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="63" NAME="C_PVR" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Specifies Processor Version Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ENDIAN="BIG" LSB="7" MPD_INDEX="64" MSB="0" NAME="C_PVR_USER1" TYPE="std_logic_vector" VALUE="0x00">
+          <DESCRIPTION>Specify USER1 Bits in Processor Version Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="65" MSB="0" NAME="C_PVR_USER2" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>Specify USER2 Bits in Processor Version Registers</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="66" NAME="C_DEBUG_ENABLED" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable MicroBlaze Debug Module Interface</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="29" MPD_INDEX="67" NAME="C_NUMBER_OF_PC_BRK" TYPE="integer" VALUE="7">
+          <DESCRIPTION>Number of PC Breakpoints </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="31" MPD_INDEX="68" NAME="C_NUMBER_OF_RD_ADDR_BRK" TYPE="integer" VALUE="2">
+          <DESCRIPTION>Number of Read Address Watchpoints </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="30" MPD_INDEX="69" NAME="C_NUMBER_OF_WR_ADDR_BRK" TYPE="integer" VALUE="2">
+          <DESCRIPTION>Number of Write Address Watchpoints </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="70" NAME="C_INTERRUPT_IS_EDGE" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Sense Interrupt on Edge vs. Level </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="71" NAME="C_EDGE_IS_POSITIVE" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Sense Interrupt on Rising vs. Falling Edge </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="72" NAME="C_RESET_MSR" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>Specify Reset Value for Select MSR Bits</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="39" MPD_INDEX="73" NAME="C_OPCODE_0x0_ILLEGAL" TYPE="integer" VALUE="1">
+          <DESCRIPTION>&lt;qt&gt;Generate Illegal Instruction Exception for NULL Instruction&lt;/qt&gt;</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="74" NAME="C_FSL_LINKS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Number of Stream Links </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="75" NAME="C_FSL_DATA_SIZE" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="76" NAME="C_USE_EXTENDED_FSL_INSTR" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Additional Stream Instructions</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="77" NAME="C_M0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="78" NAME="C_S0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="79" NAME="C_M1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="80" NAME="C_S1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="81" NAME="C_M2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="82" NAME="C_S2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="83" NAME="C_M3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="84" NAME="C_S3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="85" NAME="C_M4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="86" NAME="C_S4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="87" NAME="C_M5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="88" NAME="C_S5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="89" NAME="C_M6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="90" NAME="C_S6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="91" NAME="C_M7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="92" NAME="C_S7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="93" NAME="C_M8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="94" NAME="C_S8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="95" NAME="C_M9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="96" NAME="C_S9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="97" NAME="C_M10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="98" NAME="C_S10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="99" NAME="C_M11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="100" NAME="C_S11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="101" NAME="C_M12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="102" NAME="C_S12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="103" NAME="C_M13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="104" NAME="C_S13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="105" NAME="C_M14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="106" NAME="C_S14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="107" NAME="C_M15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="108" NAME="C_S15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="109" NAME="C_M0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="110" NAME="C_S0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="111" NAME="C_M1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="112" NAME="C_S1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="113" NAME="C_M2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="114" NAME="C_S2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="115" NAME="C_M3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="116" NAME="C_S3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="117" NAME="C_M4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="118" NAME="C_S4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="119" NAME="C_M5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="120" NAME="C_S5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="121" NAME="C_M6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="122" NAME="C_S6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="123" NAME="C_M7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="124" NAME="C_S7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="125" NAME="C_M8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="126" NAME="C_S8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="127" NAME="C_M9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="128" NAME="C_S9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="129" NAME="C_M10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="130" NAME="C_S10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="131" NAME="C_M11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="132" NAME="C_S11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="133" NAME="C_M12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="134" NAME="C_S12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="135" NAME="C_M13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="136" NAME="C_S13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="137" NAME="C_M14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="138" NAME="C_S14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="139" NAME="C_M15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="140" NAME="C_S15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="141" NAME="C_ICACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000">
+          <DESCRIPTION>I-Cache Base Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="142" NAME="C_ICACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc7ffffff">
+          <DESCRIPTION>I-Cache High Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="143" NAME="C_USE_ICACHE" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Instruction Cache </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="144" NAME="C_ALLOW_ICACHE_WR" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable I-Cache Writes</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="145" NAME="C_ADDR_TAG_BITS" TYPE="integer" VALUE="13"/>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="32" MPD_INDEX="146" NAME="C_CACHE_BYTE_SIZE" TYPE="integer" VALUE="16384">
+          <DESCRIPTION>Size of the I-Cache in Bytes</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="147" NAME="C_ICACHE_USE_FSL" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="148" NAME="C_ICACHE_LINE_LEN" TYPE="integer" VALUE="4">
+          <DESCRIPTION>Instruction Cache Line Length</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="149" NAME="C_ICACHE_ALWAYS_USED" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Use Cache Links for All I-Cache Memory Accesses </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="150" NAME="C_ICACHE_INTERFACE" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="151" NAME="C_ICACHE_VICTIMS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Number of I-Cache Victims</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="152" NAME="C_ICACHE_STREAMS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Number of I-Cache Streams</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="153" NAME="C_ICACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Use Distributed RAM for I-Cache Tags</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="154" NAME="C_ICACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="155" NAME="C_M_AXI_IC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="156" NAME="C_M_AXI_IC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="157" NAME="C_M_AXI_IC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="158" NAME="C_M_AXI_IC_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="159" NAME="C_M_AXI_IC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="160" NAME="C_M_AXI_IC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="161" NAME="C_M_AXI_IC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="162" NAME="C_M_AXI_IC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
+        <PARAMETER MPD_INDEX="163" NAME="C_M_AXI_IC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
+        <PARAMETER MPD_INDEX="164" NAME="C_M_AXI_IC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="165" NAME="C_M_AXI_IC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
+        <PARAMETER MPD_INDEX="166" NAME="C_M_AXI_IC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
+        <PARAMETER MPD_INDEX="167" NAME="C_M_AXI_IC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="168" NAME="C_M_AXI_IC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="169" NAME="C_M_AXI_IC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="170" NAME="C_INTERCONNECT_M_AXI_IC_READ_ISSUING" TYPE="integer" VALUE="2"/>
+        <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="171" NAME="C_DCACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000">
+          <DESCRIPTION>D-Cache Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="172" NAME="C_DCACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc7ffffff">
+          <DESCRIPTION>D-Cache High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="173" NAME="C_USE_DCACHE" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Data Cache</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="174" NAME="C_ALLOW_DCACHE_WR" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable D-Cache Writes</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="175" NAME="C_DCACHE_ADDR_TAG" TYPE="integer" VALUE="13"/>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="33" MPD_INDEX="176" NAME="C_DCACHE_BYTE_SIZE" TYPE="integer" VALUE="16384">
+          <DESCRIPTION>Size of D-Cache in Bytes</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="177" NAME="C_DCACHE_USE_FSL" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="178" NAME="C_DCACHE_LINE_LEN" TYPE="integer" VALUE="4">
+          <DESCRIPTION>Data Cache Line Length</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="179" NAME="C_DCACHE_ALWAYS_USED" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Use Cache Links for All D-Cache Memory Accesses </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="180" NAME="C_DCACHE_INTERFACE" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="181" NAME="C_DCACHE_USE_WRITEBACK" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Write-back Storage Policy</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="182" NAME="C_DCACHE_VICTIMS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Number of D-Cache Victims</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="183" NAME="C_DCACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Use Distributed RAM for D-Cache Tags</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="184" NAME="C_DCACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="185" NAME="C_M_AXI_DC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="186" NAME="C_M_AXI_DC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="187" NAME="C_M_AXI_DC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="188" NAME="C_M_AXI_DC_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="189" NAME="C_M_AXI_DC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="190" NAME="C_M_AXI_DC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="191" NAME="C_M_AXI_DC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="192" NAME="C_M_AXI_DC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
+        <PARAMETER MPD_INDEX="193" NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="194" NAME="C_M_AXI_DC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
+        <PARAMETER MPD_INDEX="195" NAME="C_M_AXI_DC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="196" NAME="C_M_AXI_DC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
+        <PARAMETER MPD_INDEX="197" NAME="C_M_AXI_DC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
+        <PARAMETER MPD_INDEX="198" NAME="C_M_AXI_DC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="199" NAME="C_M_AXI_DC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="200" NAME="C_M_AXI_DC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="201" NAME="C_INTERCONNECT_M_AXI_DC_READ_ISSUING" TYPE="integer" VALUE="2"/>
+        <PARAMETER MPD_INDEX="202" NAME="C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="203" NAME="C_USE_MMU" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Memory Management</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="204" NAME="C_MMU_DTLB_SIZE" TYPE="integer" VALUE="4">
+          <DESCRIPTION>Data Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="205" NAME="C_MMU_ITLB_SIZE" TYPE="integer" VALUE="2">
+          <DESCRIPTION>Instruction Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="206" NAME="C_MMU_TLB_ACCESS" TYPE="integer" VALUE="3">
+          <DESCRIPTION>Enable Access to Memory Management Special Registers</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="207" NAME="C_MMU_ZONES" TYPE="integer" VALUE="16">
+          <DESCRIPTION>Number of Memory Protection Zones</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="208" NAME="C_MMU_PRIVILEGED_INSTR" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Privileged Instructions</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="209" NAME="C_USE_INTERRUPT" TYPE="integer" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="210" NAME="C_USE_EXT_BRK" TYPE="integer" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="211" NAME="C_USE_EXT_NM_BRK" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="212" NAME="C_USE_BRANCH_TARGET_CACHE" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Branch Target Cache</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="213" NAME="C_BRANCH_TARGET_CACHE_SIZE" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Branch Target Cache Size</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_M_AXI_DC_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_M_AXI_DC_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" NAME="C_INTERCONNECT_M_AXI_DP_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" NAME="C_INTERCONNECT_M_AXI_DP_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="18" NAME="C_INTERCONNECT_M_AXI_DP_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="19" NAME="C_INTERCONNECT_M_AXI_DP_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="20" NAME="C_INTERCONNECT_M_AXI_DP_B_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="21" NAME="C_INTERCONNECT_M_AXI_DC_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="22" NAME="C_INTERCONNECT_M_AXI_DC_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="23" NAME="C_INTERCONNECT_M_AXI_DC_B_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="24" NAME="C_INTERCONNECT_M_AXI_IC_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="25" NAME="C_INTERCONNECT_M_AXI_IC_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="26" NAME="C_INTERCONNECT_M_AXI_IC_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="27" NAME="C_INTERCONNECT_M_AXI_IC_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="28" NAME="C_INTERCONNECT_M_AXI_IC_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="MB_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/>
+        <PORT BUS="DPLB:IPLB:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt"/>
+        <PORT BUS="DLMB:ILMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="RESET" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
+        <PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_BRK" SIGNAME="Ext_BRK"/>
+        <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="5" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK"/>
+        <PORT DIR="I" MPD_INDEX="6" NAME="DBG_STOP" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="7" NAME="MB_Halted" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="8" NAME="MB_Error" SIGNAME="__NOC__"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="INSTR" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="I" MPD_INDEX="10" NAME="IREADY" SIGNAME="microblaze_0_ilmb_LMB_Ready"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="I" MPD_INDEX="11" NAME="IWAIT" SIGNAME="microblaze_0_ilmb_LMB_Wait"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="I" MPD_INDEX="12" NAME="ICE" SIGNAME="microblaze_0_ilmb_LMB_CE"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="I" MPD_INDEX="13" NAME="IUE" SIGNAME="microblaze_0_ilmb_LMB_UE"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="INSTR_ADDR" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:31]"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="IFETCH" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="O" MPD_INDEX="16" NAME="I_AS" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="17" NAME="IPLB_M_ABort" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="IPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="IPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="20" MSB="0" NAME="IPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_IPLB_DWIDTH-1)/8]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="21" NAME="IPLB_M_busLock" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="22" NAME="IPLB_M_lockErr" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="IPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="IPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="25" NAME="IPLB_M_rdBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="26" NAME="IPLB_M_request" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="27" NAME="IPLB_M_RNW" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="28" MSB="0" NAME="IPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="29" MSB="0" NAME="IPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="30" MSB="0" NAME="IPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="IPLB_M_wrBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="32" MSB="0" NAME="IPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="IPLB_MBusy" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="IPLB_MRdErr" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="35" NAME="IPLB_MWrErr" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="36" NAME="IPLB_MIRQ" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="37" NAME="IPLB_MWrBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="38" NAME="IPLB_MWrDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="IPLB_MAddrAck" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="40" NAME="IPLB_MRdBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="IPLB_MRdDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="42" MSB="0" NAME="IPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="43" MSB="0" NAME="IPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="IPLB_MRearbitrate" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="IPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="IPLB_MTimeout" SIGNAME="__NOC__"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="DATA_READ" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="I" MPD_INDEX="48" NAME="DREADY" SIGNAME="microblaze_0_dlmb_LMB_Ready"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="I" MPD_INDEX="49" NAME="DWAIT" SIGNAME="microblaze_0_dlmb_LMB_Wait"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="I" MPD_INDEX="50" NAME="DCE" SIGNAME="microblaze_0_dlmb_LMB_CE"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="I" MPD_INDEX="51" NAME="DUE" SIGNAME="microblaze_0_dlmb_LMB_UE"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="52" MSB="0" NAME="DATA_WRITE" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:31]"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="53" MSB="0" NAME="DATA_ADDR" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:31]"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="O" MPD_INDEX="54" NAME="D_AS" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="O" MPD_INDEX="55" NAME="READ_STROBE" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="O" MPD_INDEX="56" NAME="WRITE_STROBE" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="BYTE_ENABLE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:3]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="DPLB_M_ABort" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="59" MSB="0" NAME="DPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="60" MSB="0" NAME="DPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="61" MSB="0" NAME="DPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_DPLB_DWIDTH-1)/8]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="62" NAME="DPLB_M_busLock" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="63" NAME="DPLB_M_lockErr" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="64" MSB="0" NAME="DPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="65" MSB="0" NAME="DPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="66" NAME="DPLB_M_rdBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="67" NAME="DPLB_M_request" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="68" NAME="DPLB_M_RNW" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="69" MSB="0" NAME="DPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="70" MSB="0" NAME="DPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="71" MSB="0" NAME="DPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="72" NAME="DPLB_M_wrBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="73" MSB="0" NAME="DPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="DPLB_MBusy" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="DPLB_MRdErr" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="76" NAME="DPLB_MWrErr" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="DPLB_MIRQ" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="DPLB_MWrBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="DPLB_MWrDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="80" NAME="DPLB_MAddrAck" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="81" NAME="DPLB_MRdBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="DPLB_MRdDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="83" MSB="0" NAME="DPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="84" MSB="0" NAME="DPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="85" NAME="DPLB_MRearbitrate" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="86" MSB="0" NAME="DPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="87" NAME="DPLB_MTimeout" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="M_AXI_IP_AWID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="89" MSB="31" NAME="M_AXI_IP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="90" MSB="7" NAME="M_AXI_IP_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="91" MSB="2" NAME="M_AXI_IP_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="92" MSB="1" NAME="M_AXI_IP_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="M_AXI_IP_AWLOCK" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="94" MSB="3" NAME="M_AXI_IP_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="95" MSB="2" NAME="M_AXI_IP_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="96" MSB="3" NAME="M_AXI_IP_AWQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="M_AXI_IP_AWVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="M_AXI_IP_AWREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="99" MSB="31" NAME="M_AXI_IP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="100" MSB="3" NAME="M_AXI_IP_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_M_AXI_IP_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="M_AXI_IP_WLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="M_AXI_IP_WVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="M_AXI_IP_WREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="M_AXI_IP_BID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="105" MSB="1" NAME="M_AXI_IP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="106" NAME="M_AXI_IP_BVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="107" NAME="M_AXI_IP_BREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="M_AXI_IP_ARID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="109" MSB="31" NAME="M_AXI_IP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="110" MSB="7" NAME="M_AXI_IP_ARLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="111" MSB="2" NAME="M_AXI_IP_ARSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="112" MSB="1" NAME="M_AXI_IP_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="M_AXI_IP_ARLOCK" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="114" MSB="3" NAME="M_AXI_IP_ARCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="115" MSB="2" NAME="M_AXI_IP_ARPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="116" MSB="3" NAME="M_AXI_IP_ARQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="M_AXI_IP_ARVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="118" NAME="M_AXI_IP_ARREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="119" NAME="M_AXI_IP_RID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="120" MSB="31" NAME="M_AXI_IP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="121" MSB="1" NAME="M_AXI_IP_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="122" NAME="M_AXI_IP_RLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="M_AXI_IP_RVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="124" NAME="M_AXI_IP_RREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWID" DIR="O" MPD_INDEX="125" NAME="M_AXI_DP_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="126" MSB="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="M_AXI_DP_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="128" MSB="2" NAME="M_AXI_DP_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="129" MSB="1" NAME="M_AXI_DP_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="O" MPD_INDEX="130" NAME="M_AXI_DP_AWLOCK" SIGNAME="axi4lite_0_S_AWLOCK"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="131" MSB="3" NAME="M_AXI_DP_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="132" MSB="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="133" MSB="3" NAME="M_AXI_DP_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="O" MPD_INDEX="134" NAME="M_AXI_DP_AWVALID" SIGNAME="axi4lite_0_S_AWVALID"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="I" MPD_INDEX="135" NAME="M_AXI_DP_AWREADY" SIGNAME="axi4lite_0_S_AWREADY"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="136" MSB="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="137" MSB="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DP_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="O" MPD_INDEX="138" NAME="M_AXI_DP_WLAST" SIGNAME="axi4lite_0_S_WLAST"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="O" MPD_INDEX="139" NAME="M_AXI_DP_WVALID" SIGNAME="axi4lite_0_S_WVALID"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="I" MPD_INDEX="140" NAME="M_AXI_DP_WREADY" SIGNAME="axi4lite_0_S_WREADY"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BID" DIR="I" MPD_INDEX="141" NAME="M_AXI_DP_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="142" MSB="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="I" MPD_INDEX="143" NAME="M_AXI_DP_BVALID" SIGNAME="axi4lite_0_S_BVALID"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="O" MPD_INDEX="144" NAME="M_AXI_DP_BREADY" SIGNAME="axi4lite_0_S_BREADY"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARID" DIR="O" MPD_INDEX="145" NAME="M_AXI_DP_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="146" MSB="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="147" MSB="7" NAME="M_AXI_DP_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="148" MSB="2" NAME="M_AXI_DP_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="149" MSB="1" NAME="M_AXI_DP_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="O" MPD_INDEX="150" NAME="M_AXI_DP_ARLOCK" SIGNAME="axi4lite_0_S_ARLOCK"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="151" MSB="3" NAME="M_AXI_DP_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="152" MSB="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="153" MSB="3" NAME="M_AXI_DP_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="O" MPD_INDEX="154" NAME="M_AXI_DP_ARVALID" SIGNAME="axi4lite_0_S_ARVALID"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="I" MPD_INDEX="155" NAME="M_AXI_DP_ARREADY" SIGNAME="axi4lite_0_S_ARREADY"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RID" DIR="I" MPD_INDEX="156" NAME="M_AXI_DP_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="157" MSB="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="158" MSB="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="I" MPD_INDEX="159" NAME="M_AXI_DP_RLAST" SIGNAME="axi4lite_0_S_RLAST"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="I" MPD_INDEX="160" NAME="M_AXI_DP_RVALID" SIGNAME="axi4lite_0_S_RVALID"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="O" MPD_INDEX="161" NAME="M_AXI_DP_RREADY" SIGNAME="axi4lite_0_S_RREADY"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="162" NAME="M_AXI_IC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="163" MSB="31" NAME="M_AXI_IC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="164" MSB="7" NAME="M_AXI_IC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="165" MSB="2" NAME="M_AXI_IC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="166" MSB="1" NAME="M_AXI_IC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="167" NAME="M_AXI_IC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="168" MSB="3" NAME="M_AXI_IC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="169" MSB="2" NAME="M_AXI_IC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="170" MSB="3" NAME="M_AXI_IC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="171" NAME="M_AXI_IC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="172" NAME="M_AXI_IC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="173" MSB="4" NAME="M_AXI_IC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_IC_AWUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="174" MSB="31" NAME="M_AXI_IC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="175" MSB="3" NAME="M_AXI_IC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_IC_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="176" NAME="M_AXI_IC_WLAST" SIGNAME="axi4_0_S_WLAST"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="177" NAME="M_AXI_IC_WVALID" SIGNAME="axi4_0_S_WVALID"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="178" NAME="M_AXI_IC_WREADY" SIGNAME="axi4_0_S_WREADY"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="179" NAME="M_AXI_IC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_IC_WUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="180" NAME="M_AXI_IC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="181" MSB="1" NAME="M_AXI_IC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="182" NAME="M_AXI_IC_BVALID" SIGNAME="axi4_0_S_BVALID"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="183" NAME="M_AXI_IC_BREADY" SIGNAME="axi4_0_S_BREADY"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="184" NAME="M_AXI_IC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_IC_BUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="185" NAME="M_AXI_IC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="M_AXI_IC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="187" MSB="7" NAME="M_AXI_IC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="188" MSB="2" NAME="M_AXI_IC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="189" MSB="1" NAME="M_AXI_IC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="190" NAME="M_AXI_IC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="191" MSB="3" NAME="M_AXI_IC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="192" MSB="2" NAME="M_AXI_IC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="193" MSB="3" NAME="M_AXI_IC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="194" NAME="M_AXI_IC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="195" NAME="M_AXI_IC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="196" MSB="4" NAME="M_AXI_IC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_IC_ARUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="197" NAME="M_AXI_IC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="198" MSB="31" NAME="M_AXI_IC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="199" MSB="1" NAME="M_AXI_IC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="200" NAME="M_AXI_IC_RLAST" SIGNAME="axi4_0_S_RLAST"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="201" NAME="M_AXI_IC_RVALID" SIGNAME="axi4_0_S_RVALID"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="202" NAME="M_AXI_IC_RREADY" SIGNAME="axi4_0_S_RREADY"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="203" NAME="M_AXI_IC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_IC_RUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="204" NAME="M_AXI_DC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="205" MSB="31" NAME="M_AXI_DC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="206" MSB="7" NAME="M_AXI_DC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="207" MSB="2" NAME="M_AXI_DC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="208" MSB="1" NAME="M_AXI_DC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="209" NAME="M_AXI_DC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="210" MSB="3" NAME="M_AXI_DC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="211" MSB="2" NAME="M_AXI_DC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="212" MSB="3" NAME="M_AXI_DC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="213" NAME="M_AXI_DC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="214" NAME="M_AXI_DC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="215" MSB="4" NAME="M_AXI_DC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_DC_AWUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="216" MSB="31" NAME="M_AXI_DC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="217" MSB="3" NAME="M_AXI_DC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DC_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="218" NAME="M_AXI_DC_WLAST" SIGNAME="axi4_0_S_WLAST"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="219" NAME="M_AXI_DC_WVALID" SIGNAME="axi4_0_S_WVALID"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="220" NAME="M_AXI_DC_WREADY" SIGNAME="axi4_0_S_WREADY"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="221" NAME="M_AXI_DC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_DC_WUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="222" NAME="M_AXI_DC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="223" MSB="1" NAME="M_AXI_DC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="224" NAME="M_AXI_DC_BVALID" SIGNAME="axi4_0_S_BVALID"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="225" NAME="M_AXI_DC_BREADY" SIGNAME="axi4_0_S_BREADY"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="226" NAME="M_AXI_DC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_DC_BUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="227" NAME="M_AXI_DC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="228" MSB="31" NAME="M_AXI_DC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="229" MSB="7" NAME="M_AXI_DC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="230" MSB="2" NAME="M_AXI_DC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="231" MSB="1" NAME="M_AXI_DC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="232" NAME="M_AXI_DC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="233" MSB="3" NAME="M_AXI_DC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="234" MSB="2" NAME="M_AXI_DC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="235" MSB="3" NAME="M_AXI_DC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="236" NAME="M_AXI_DC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="237" NAME="M_AXI_DC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="238" MSB="4" NAME="M_AXI_DC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_DC_ARUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="239" NAME="M_AXI_DC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="240" MSB="31" NAME="M_AXI_DC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="241" MSB="1" NAME="M_AXI_DC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="242" NAME="M_AXI_DC_RLAST" SIGNAME="axi4_0_S_RLAST"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="243" NAME="M_AXI_DC_RVALID" SIGNAME="axi4_0_S_RVALID"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="244" NAME="M_AXI_DC_RREADY" SIGNAME="axi4_0_S_RREADY"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="245" NAME="M_AXI_DC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_DC_RUSER_WIDTH-1):0]"/>
+        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Clk" DIR="I" MPD_INDEX="246" NAME="DBG_CLK" SIGNAME="microblaze_0_debug_Dbg_Clk"/>
+        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_TDI" DIR="I" MPD_INDEX="247" NAME="DBG_TDI" SIGNAME="microblaze_0_debug_Dbg_TDI"/>
+        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_TDO" DIR="O" MPD_INDEX="248" NAME="DBG_TDO" SIGNAME="microblaze_0_debug_Dbg_TDO"/>
+        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Reg_En" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="249" MSB="0" NAME="DBG_REG_EN" RIGHT="7" SIGNAME="microblaze_0_debug_Dbg_Reg_En" VECFORMULA="[0:7]"/>
+        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Shift" DIR="I" MPD_INDEX="250" NAME="DBG_SHIFT" SIGNAME="microblaze_0_debug_Dbg_Shift"/>
+        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Capture" DIR="I" MPD_INDEX="251" NAME="DBG_CAPTURE" SIGNAME="microblaze_0_debug_Dbg_Capture"/>
+        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Update" DIR="I" MPD_INDEX="252" NAME="DBG_UPDATE" SIGNAME="microblaze_0_debug_Dbg_Update"/>
+        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Debug_Rst" DIR="I" MPD_INDEX="253" NAME="DEBUG_RST" SIGIS="RST" SIGNAME="microblaze_0_debug_Debug_Rst"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="254" MSB="0" NAME="Trace_Instruction" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="255" NAME="Trace_Valid_Instr" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="256" MSB="0" NAME="Trace_PC" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="257" NAME="Trace_Reg_Write" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="258" MSB="0" NAME="Trace_Reg_Addr" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="14" MPD_INDEX="259" MSB="0" NAME="Trace_MSR_Reg" RIGHT="14" SIGNAME="__NOC__" VECFORMULA="[0:14]"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="260" MSB="0" NAME="Trace_PID_Reg" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="261" MSB="0" NAME="Trace_New_Reg_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="262" NAME="Trace_Exception_Taken" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="263" MSB="0" NAME="Trace_Exception_Kind" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="Trace_Jump_Taken" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="265" NAME="Trace_Delay_Slot" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="266" MSB="0" NAME="Trace_Data_Address" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="267" NAME="Trace_Data_Access" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="268" NAME="Trace_Data_Read" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="269" NAME="Trace_Data_Write" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="270" MSB="0" NAME="Trace_Data_Write_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="271" MSB="0" NAME="Trace_Data_Byte_Enable" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="272" NAME="Trace_DCache_Req" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="273" NAME="Trace_DCache_Hit" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="274" NAME="Trace_DCache_Rdy" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="275" NAME="Trace_DCache_Read" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="276" NAME="Trace_ICache_Req" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="277" NAME="Trace_ICache_Hit" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="278" NAME="Trace_ICache_Rdy" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="279" NAME="Trace_OF_PipeRun" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="280" NAME="Trace_EX_PipeRun" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="281" NAME="Trace_MEM_PipeRun" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="282" NAME="Trace_MB_Halted" SIGNAME="__NOC__"/>
+        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="283" NAME="Trace_Jump_Hit" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="284" NAME="FSL0_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="285" NAME="FSL0_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="286" MSB="0" NAME="FSL0_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="287" NAME="FSL0_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="288" NAME="FSL0_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="289" NAME="FSL0_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="290" NAME="FSL0_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="291" MSB="0" NAME="FSL0_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="292" NAME="FSL0_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="293" NAME="FSL0_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="294" NAME="FSL1_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="295" NAME="FSL1_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="296" MSB="0" NAME="FSL1_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="297" NAME="FSL1_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="298" NAME="FSL1_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="299" NAME="FSL1_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="300" NAME="FSL1_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="301" MSB="0" NAME="FSL1_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="302" NAME="FSL1_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="303" NAME="FSL1_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="304" NAME="FSL2_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="305" NAME="FSL2_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="306" MSB="0" NAME="FSL2_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="307" NAME="FSL2_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="308" NAME="FSL2_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="309" NAME="FSL2_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="310" NAME="FSL2_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="311" MSB="0" NAME="FSL2_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="312" NAME="FSL2_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="313" NAME="FSL2_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="314" NAME="FSL3_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="315" NAME="FSL3_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="316" MSB="0" NAME="FSL3_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="317" NAME="FSL3_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="318" NAME="FSL3_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="319" NAME="FSL3_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="320" NAME="FSL3_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="321" MSB="0" NAME="FSL3_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="322" NAME="FSL3_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="323" NAME="FSL3_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="324" NAME="FSL4_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="325" NAME="FSL4_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="326" MSB="0" NAME="FSL4_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="327" NAME="FSL4_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="328" NAME="FSL4_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="329" NAME="FSL4_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="330" NAME="FSL4_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="331" MSB="0" NAME="FSL4_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="332" NAME="FSL4_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="333" NAME="FSL4_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="334" NAME="FSL5_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="335" NAME="FSL5_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="336" MSB="0" NAME="FSL5_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="337" NAME="FSL5_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="338" NAME="FSL5_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="339" NAME="FSL5_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="340" NAME="FSL5_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="341" MSB="0" NAME="FSL5_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="342" NAME="FSL5_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="343" NAME="FSL5_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="344" NAME="FSL6_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="345" NAME="FSL6_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="346" MSB="0" NAME="FSL6_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="347" NAME="FSL6_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="348" NAME="FSL6_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="349" NAME="FSL6_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="350" NAME="FSL6_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="351" MSB="0" NAME="FSL6_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="352" NAME="FSL6_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="353" NAME="FSL6_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="354" NAME="FSL7_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="355" NAME="FSL7_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="356" MSB="0" NAME="FSL7_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="357" NAME="FSL7_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="358" NAME="FSL7_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="359" NAME="FSL7_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="360" NAME="FSL7_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="361" MSB="0" NAME="FSL7_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="362" NAME="FSL7_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="363" NAME="FSL7_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="364" NAME="FSL8_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="365" NAME="FSL8_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="366" MSB="0" NAME="FSL8_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="367" NAME="FSL8_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="368" NAME="FSL8_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="369" NAME="FSL8_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="370" NAME="FSL8_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="371" MSB="0" NAME="FSL8_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="372" NAME="FSL8_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="373" NAME="FSL8_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="374" NAME="FSL9_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="375" NAME="FSL9_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="376" MSB="0" NAME="FSL9_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="377" NAME="FSL9_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="378" NAME="FSL9_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="379" NAME="FSL9_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="380" NAME="FSL9_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="381" MSB="0" NAME="FSL9_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="382" NAME="FSL9_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="383" NAME="FSL9_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="384" NAME="FSL10_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="385" NAME="FSL10_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="386" MSB="0" NAME="FSL10_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="387" NAME="FSL10_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="388" NAME="FSL10_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="389" NAME="FSL10_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="390" NAME="FSL10_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="391" MSB="0" NAME="FSL10_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="392" NAME="FSL10_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="393" NAME="FSL10_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="394" NAME="FSL11_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="395" NAME="FSL11_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="396" MSB="0" NAME="FSL11_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="397" NAME="FSL11_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="398" NAME="FSL11_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="399" NAME="FSL11_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="400" NAME="FSL11_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="401" MSB="0" NAME="FSL11_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="402" NAME="FSL11_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="403" NAME="FSL11_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="404" NAME="FSL12_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="405" NAME="FSL12_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="406" MSB="0" NAME="FSL12_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="407" NAME="FSL12_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="408" NAME="FSL12_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="409" NAME="FSL12_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="410" NAME="FSL12_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="411" MSB="0" NAME="FSL12_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="412" NAME="FSL12_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="413" NAME="FSL12_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="414" NAME="FSL13_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="415" NAME="FSL13_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="416" MSB="0" NAME="FSL13_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="417" NAME="FSL13_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="418" NAME="FSL13_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="419" NAME="FSL13_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="420" NAME="FSL13_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="421" MSB="0" NAME="FSL13_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="422" NAME="FSL13_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="423" NAME="FSL13_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="424" NAME="FSL14_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="425" NAME="FSL14_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="426" MSB="0" NAME="FSL14_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="427" NAME="FSL14_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="428" NAME="FSL14_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="429" NAME="FSL14_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="430" NAME="FSL14_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="431" MSB="0" NAME="FSL14_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="432" NAME="FSL14_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="433" NAME="FSL14_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="434" NAME="FSL15_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="435" NAME="FSL15_S_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="436" MSB="0" NAME="FSL15_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="437" NAME="FSL15_S_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="438" NAME="FSL15_S_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="439" NAME="FSL15_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="440" NAME="FSL15_M_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="441" MSB="0" NAME="FSL15_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
+        <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="442" NAME="FSL15_M_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="443" NAME="FSL15_M_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="444" NAME="M0_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="445" MSB="31" NAME="M0_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M0_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="446" NAME="M0_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="447" NAME="M0_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="448" NAME="S0_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="449" MSB="31" NAME="S0_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S0_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="450" NAME="S0_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="451" NAME="S0_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="452" NAME="M1_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="453" MSB="31" NAME="M1_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M1_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="454" NAME="M1_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="455" NAME="M1_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="456" NAME="S1_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="457" MSB="31" NAME="S1_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S1_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="458" NAME="S1_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="459" NAME="S1_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="460" NAME="M2_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="461" MSB="31" NAME="M2_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M2_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="462" NAME="M2_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="463" NAME="M2_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="464" NAME="S2_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="465" MSB="31" NAME="S2_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S2_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="466" NAME="S2_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="467" NAME="S2_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="468" NAME="M3_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="469" MSB="31" NAME="M3_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M3_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="470" NAME="M3_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="471" NAME="M3_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="472" NAME="S3_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="473" MSB="31" NAME="S3_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S3_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="474" NAME="S3_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="475" NAME="S3_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="476" NAME="M4_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="477" MSB="31" NAME="M4_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M4_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="478" NAME="M4_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="479" NAME="M4_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="480" NAME="S4_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="481" MSB="31" NAME="S4_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S4_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="482" NAME="S4_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="483" NAME="S4_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="484" NAME="M5_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="485" MSB="31" NAME="M5_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M5_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="486" NAME="M5_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="487" NAME="M5_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="488" NAME="S5_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="489" MSB="31" NAME="S5_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S5_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="490" NAME="S5_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="491" NAME="S5_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="492" NAME="M6_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="493" MSB="31" NAME="M6_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M6_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="494" NAME="M6_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="495" NAME="M6_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="496" NAME="S6_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="497" MSB="31" NAME="S6_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S6_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="498" NAME="S6_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="499" NAME="S6_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="500" NAME="M7_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="501" MSB="31" NAME="M7_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M7_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="502" NAME="M7_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="503" NAME="M7_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="504" NAME="S7_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="505" MSB="31" NAME="S7_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S7_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="506" NAME="S7_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="507" NAME="S7_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="508" NAME="M8_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="509" MSB="31" NAME="M8_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M8_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="510" NAME="M8_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="511" NAME="M8_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="512" NAME="S8_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="513" MSB="31" NAME="S8_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S8_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="514" NAME="S8_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="515" NAME="S8_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="516" NAME="M9_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="517" MSB="31" NAME="M9_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M9_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="518" NAME="M9_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="519" NAME="M9_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="520" NAME="S9_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="521" MSB="31" NAME="S9_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S9_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="522" NAME="S9_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="523" NAME="S9_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="524" NAME="M10_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="525" MSB="31" NAME="M10_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M10_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="526" NAME="M10_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="527" NAME="M10_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="528" NAME="S10_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="529" MSB="31" NAME="S10_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S10_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="530" NAME="S10_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="531" NAME="S10_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="532" NAME="M11_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="533" MSB="31" NAME="M11_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M11_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="534" NAME="M11_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="535" NAME="M11_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="536" NAME="S11_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="537" MSB="31" NAME="S11_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S11_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="538" NAME="S11_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="539" NAME="S11_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="540" NAME="M12_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="541" MSB="31" NAME="M12_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M12_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="542" NAME="M12_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="543" NAME="M12_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="544" NAME="S12_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="545" MSB="31" NAME="S12_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S12_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="546" NAME="S12_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="547" NAME="S12_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="548" NAME="M13_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="549" MSB="31" NAME="M13_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M13_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="550" NAME="M13_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="551" NAME="M13_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="552" NAME="S13_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="553" MSB="31" NAME="S13_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S13_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="554" NAME="S13_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="555" NAME="S13_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="556" NAME="M14_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="557" MSB="31" NAME="M14_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M14_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="558" NAME="M14_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="559" NAME="M14_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="560" NAME="S14_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="561" MSB="31" NAME="S14_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S14_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="562" NAME="S14_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="563" NAME="S14_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="564" NAME="M15_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="565" MSB="31" NAME="M15_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M15_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="566" NAME="M15_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="567" NAME="M15_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="568" NAME="S15_AXIS_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="569" MSB="31" NAME="S15_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S15_AXIS_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="570" NAME="S15_AXIS_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="571" NAME="S15_AXIS_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="572" NAME="ICACHE_FSL_IN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="573" NAME="ICACHE_FSL_IN_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="574" MSB="0" NAME="ICACHE_FSL_IN_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="575" NAME="ICACHE_FSL_IN_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="576" NAME="ICACHE_FSL_IN_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="577" NAME="ICACHE_FSL_OUT_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="578" NAME="ICACHE_FSL_OUT_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="579" MSB="0" NAME="ICACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="580" NAME="ICACHE_FSL_OUT_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="581" NAME="ICACHE_FSL_OUT_FULL" SIGNAME="__NOC__"/>
+        <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="582" NAME="DCACHE_FSL_IN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="583" NAME="DCACHE_FSL_IN_READ" SIGNAME="__NOC__"/>
+        <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="584" MSB="0" NAME="DCACHE_FSL_IN_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="585" NAME="DCACHE_FSL_IN_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="586" NAME="DCACHE_FSL_IN_EXISTS" SIGNAME="__NOC__"/>
+        <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="587" NAME="DCACHE_FSL_OUT_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="588" NAME="DCACHE_FSL_OUT_WRITE" SIGNAME="__NOC__"/>
+        <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="589" MSB="0" NAME="DCACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="590" NAME="DCACHE_FSL_OUT_CONTROL" SIGNAME="__NOC__"/>
+        <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="591" NAME="DCACHE_FSL_OUT_FULL" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="2" NAME="DPLB" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABort"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABus"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_UABus"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_BE"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_busLock"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_lockErr"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_MSize"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_priority"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_rdBurst"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_request"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_RNW"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_size"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_TAttribute"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_type"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrBurst"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrDBus"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MBusy"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MRdErr"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MWrErr"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MIRQ"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MWrBTerm"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MWrDAck"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MAddrAck"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MRdBTerm"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDAck"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDBus"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MRdWdAddr"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MRearbitrate"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MSSize"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MTimeout"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="3" NAME="IPLB" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABort"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABus"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_UABus"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_BE"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_busLock"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_lockErr"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_MSize"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_priority"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_rdBurst"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_request"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_RNW"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_size"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_TAttribute"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_type"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrBurst"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrDBus"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MBusy"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdErr"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MWrErr"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MIRQ"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MWrBTerm"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MWrDAck"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MAddrAck"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdBTerm"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDAck"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDBus"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdWdAddr"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MRearbitrate"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MSSize"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MTimeout"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="0" NAME="DLMB" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="CLK"/>
+            <PORTMAP DIR="I" PHYSICAL="RESET"/>
+            <PORTMAP DIR="I" PHYSICAL="DATA_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="DREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="DWAIT"/>
+            <PORTMAP DIR="I" PHYSICAL="DCE"/>
+            <PORTMAP DIR="I" PHYSICAL="DUE"/>
+            <PORTMAP DIR="O" PHYSICAL="DATA_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="DATA_ADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="D_AS"/>
+            <PORTMAP DIR="O" PHYSICAL="READ_STROBE"/>
+            <PORTMAP DIR="O" PHYSICAL="WRITE_STROBE"/>
+            <PORTMAP DIR="O" PHYSICAL="BYTE_ENABLE"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="5" MPD_INDEX="1" NAME="ILMB" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="CLK"/>
+            <PORTMAP DIR="I" PHYSICAL="RESET"/>
+            <PORTMAP DIR="I" PHYSICAL="INSTR"/>
+            <PORTMAP DIR="I" PHYSICAL="IREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="IWAIT"/>
+            <PORTMAP DIR="I" PHYSICAL="ICE"/>
+            <PORTMAP DIR="I" PHYSICAL="IUE"/>
+            <PORTMAP DIR="O" PHYSICAL="INSTR_ADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="IFETCH"/>
+            <PORTMAP DIR="O" PHYSICAL="I_AS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="M_AXI_DP" PROTOCOL="AXI4LITE" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" MPD_INDEX="5" NAME="M_AXI_IP" PROTOCOL="AXI4LITE" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_AWREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WSTRB"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_WREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_BREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_ARREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="104" NAME="M_AXI_DC" PROTOCOL="AXI4" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_AWREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWUSER"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WSTRB"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WUSER"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BUSER"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARUSER"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_RREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RUSER"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="2" MPD_INDEX="105" NAME="M_AXI_IC" PROTOCOL="AXI4" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_AWREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWUSER"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WSTRB"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WUSER"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BUSER"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARUSER"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_RREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RUSER"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="106" NAME="DEBUG" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="DBG_CLK"/>
+            <PORTMAP DIR="I" PHYSICAL="DBG_TDI"/>
+            <PORTMAP DIR="O" PHYSICAL="DBG_TDO"/>
+            <PORTMAP DIR="I" PHYSICAL="DBG_REG_EN"/>
+            <PORTMAP DIR="I" PHYSICAL="DBG_SHIFT"/>
+            <PORTMAP DIR="I" PHYSICAL="DBG_CAPTURE"/>
+            <PORTMAP DIR="I" PHYSICAL="DBG_UPDATE"/>
+            <PORTMAP DIR="I" PHYSICAL="DEBUG_RST"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBTRACE2" MPD_INDEX="107" NAME="TRACE" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Instruction"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Valid_Instr"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_PC"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Write"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Addr"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_MSR_Reg"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_PID_Reg"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_New_Reg_Value"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Taken"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Kind"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Taken"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Delay_Slot"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Address"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Access"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Read"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write_Value"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Byte_Enable"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Req"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Hit"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Rdy"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Read"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Req"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Hit"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Rdy"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_OF_PipeRun"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_EX_PipeRun"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_MEM_PipeRun"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_MB_Halted"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Hit"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="6" NAME="SFSL0" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="38" NAME="DRFSL0" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="7" NAME="MFSL0" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="39" NAME="DWFSL0" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="8" NAME="SFSL1" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="40" NAME="DRFSL1" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="9" NAME="MFSL1" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="41" NAME="DWFSL1" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="10" NAME="SFSL2" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="42" NAME="DRFSL2" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="11" NAME="MFSL2" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="43" NAME="DWFSL2" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="12" NAME="SFSL3" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="44" NAME="DRFSL3" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="13" NAME="MFSL3" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="45" NAME="DWFSL3" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="14" NAME="SFSL4" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="46" NAME="DRFSL4" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="15" NAME="MFSL4" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="47" NAME="DWFSL4" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="16" NAME="SFSL5" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="48" NAME="DRFSL5" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="17" NAME="MFSL5" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="49" NAME="DWFSL5" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="18" NAME="SFSL6" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="50" NAME="DRFSL6" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="19" NAME="MFSL6" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="51" NAME="DWFSL6" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="20" NAME="SFSL7" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="52" NAME="DRFSL7" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="21" NAME="MFSL7" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="53" NAME="DWFSL7" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="22" NAME="SFSL8" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="54" NAME="DRFSL8" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="23" NAME="MFSL8" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="55" NAME="DWFSL8" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="24" NAME="SFSL9" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="56" NAME="DRFSL9" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="25" NAME="MFSL9" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="57" NAME="DWFSL9" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="26" NAME="SFSL10" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="58" NAME="DRFSL10" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="27" NAME="MFSL10" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="59" NAME="DWFSL10" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="28" NAME="SFSL11" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="60" NAME="DRFSL11" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="29" NAME="MFSL11" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="61" NAME="DWFSL11" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="30" NAME="SFSL12" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="62" NAME="DRFSL12" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="31" NAME="MFSL12" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="63" NAME="DWFSL12" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="32" NAME="SFSL13" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="64" NAME="DRFSL13" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="33" NAME="MFSL13" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="65" NAME="DWFSL13" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="34" NAME="SFSL14" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="66" NAME="DRFSL14" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="35" NAME="MFSL14" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="67" NAME="DWFSL14" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="36" NAME="SFSL15" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="68" NAME="DRFSL15" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="37" NAME="MFSL15" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="69" NAME="DWFSL15" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="70" NAME="M0_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M0_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="71" NAME="S0_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S0_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="72" NAME="M1_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M1_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="73" NAME="S1_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S1_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="74" NAME="M2_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M2_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="75" NAME="S2_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S2_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="76" NAME="M3_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M3_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="77" NAME="S3_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S3_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="78" NAME="M4_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M4_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="79" NAME="S4_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S4_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="80" NAME="M5_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M5_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="81" NAME="S5_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S5_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="82" NAME="M6_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M6_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="83" NAME="S6_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S6_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="84" NAME="M7_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M7_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="85" NAME="S7_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S7_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="86" NAME="M8_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M8_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="87" NAME="S8_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S8_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="88" NAME="M9_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M9_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="89" NAME="S9_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S9_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="90" NAME="M10_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M10_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="91" NAME="S10_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S10_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="92" NAME="M11_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M11_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="93" NAME="S11_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S11_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="94" NAME="M12_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M12_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="95" NAME="S12_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S12_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="96" NAME="M13_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M13_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="97" NAME="S13_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S13_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="98" NAME="M14_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M14_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="99" NAME="S14_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S14_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="100" NAME="M15_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M15_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="101" NAME="S15_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S15_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="103" NAME="IXCL" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_EXISTS"/>
+            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_OUT_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="102" NAME="DXCL" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_EXISTS"/>
+            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_OUT_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_d_bram_ctrl" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_dlmb"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_i_bram_ctrl" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_ilmb"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480ffff" INSTANCE="debug_module" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" INSTANCE="RS232_Uart_1" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" INSTANCE="LEDs_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" INSTANCE="Push_Buttons_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="1088421888" BASENAME="C_BASEADDR" BASEVALUE="0x40e00000" HIGHDECIMAL="1088487423" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40e0ffff" INSTANCE="Ethernet_Lite" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" INSTANCE="microblaze_0_intc" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0xc0000000" HIGHDECIMAL="3355443199" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0xc7ffffff" INSTANCE="MCB_DDR3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="134217728" SIZEABRV="128M">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+      </MEMORYMAP>
+      <PERIPHERALS>
+        <PERIPHERAL INSTANCE="microblaze_0_d_bram_ctrl"/>
+        <PERIPHERAL INSTANCE="microblaze_0_i_bram_ctrl"/>
+        <PERIPHERAL INSTANCE="debug_module"/>
+        <PERIPHERAL INSTANCE="RS232_Uart_1"/>
+        <PERIPHERAL INSTANCE="LEDs_4Bits"/>
+        <PERIPHERAL INSTANCE="Push_Buttons_4Bits"/>
+        <PERIPHERAL INSTANCE="Ethernet_Lite"/>
+        <PERIPHERAL INSTANCE="axi_timer_0"/>
+        <PERIPHERAL INSTANCE="microblaze_0_intc"/>
+        <PERIPHERAL INSTANCE="MCB_DDR3"/>
+      </PERIPHERALS>
+      <INTERRUPTINFO TYPE="TARGET">
+        <SOURCE INSTANCE="microblaze_0_intc" INTC_INDEX="0"/>
+      </INTERRUPTINFO>
+    </MODULE>
+    <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_ilmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10">
+      <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Active High External Reset</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
+        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_ilmb_LMB_Rst"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_ilmb_M_WriteStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_ilmb_LMB_Ready"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_ilmb_LMB_Wait"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_ilmb_LMB_UE"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_ilmb_LMB_CE"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
+      </PORTS>
+      <BUSINTERFACES/>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
+      </IOINTERFACES>
+    </MODULE>
+    <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_dlmb" IPTYPE="BUS" MHS_INDEX="4" MODCLASS="BUS" MODTYPE="lmb_v10">
+      <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Active High External Reset</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
+        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_dlmb_LMB_Ready"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_dlmb_LMB_Wait"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_dlmb_LMB_UE"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_dlmb_LMB_CE"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
+      </PORTS>
+      <BUSINTERFACES/>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
+      </IOINTERFACES>
+    </MODULE>
+    <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_i_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
+      <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff">
+          <DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
+        <PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x40000000">
+          <DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Error Correction Code </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Select Interconnect </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Fault Inject Registers </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>ECC Status and Control Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0">
+          <DESCRIPTION>ECC On/Off Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1">
+          <DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2">
+          <DESCRIPTION>Write Access setting </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
+          <DESCRIPTION>Base Address for PLB Interface</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>High Address for PLB Interface</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>Frequency of PLB Slave</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
+          <DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_ilmb_LMB_Rst"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
+        <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="SLMB"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="SPLB_CTRL"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+    </MODULE>
+    <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_d_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
+      <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff">
+          <DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
+        <PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x40000000">
+          <DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Error Correction Code </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Select Interconnect </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Fault Inject Registers </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>ECC Status and Control Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0">
+          <DESCRIPTION>ECC On/Off Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1">
+          <DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2">
+          <DESCRIPTION>Write Access setting </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
+          <DESCRIPTION>Base Address for PLB Interface</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>High Address for PLB Interface</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>Frequency of PLB Slave</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
+          <DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
+        <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="SLMB"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="SPLB_CTRL"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+    </MODULE>
+    <MODULE HWVERSION="1.00.a" INSTANCE="microblaze_0_bram_block" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="MEMORY" MODTYPE="bram_block">
+      <DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x2000">
+          <DESCRIPTION>Size of BRAM(s) in Bytes</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>Data Width of Port A and B</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>Address Width of Port A and B</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4">
+          <DESCRIPTION>Number of Byte Write Enables</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
+        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
+        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
+        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
+        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
+        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
+        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
+        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
+        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
+        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
+        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
+        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
+        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
+        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_A"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_A"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_EN_A"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_A"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Din_A"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_A"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_B"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_B"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_EN_B"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_B"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_B"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Din_B"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_B"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE HWVERSION="3.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
+      <DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="t">
+          <DESCRIPTION>Device Subfamily</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4">
+          <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The External Reset Input </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4">
+          <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1">
+          <DESCRIPTION>External Reset Active High </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1">
+          <DESCRIPTION>Auxiliary Reset Active High </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Number of Bus Structure Reset Registered Outputs </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Number of Peripheral Reset Registered Outputs </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_NUM_INTERCONNECT_ARESETN" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Number of Active Low Interconnect Reset Registered Outputs </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_NUM_PERP_ARESETN" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Number of Active Low Peripheral Reset Registered Outputs </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="RESET"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/>
+        <PORT CLKFREQUENCY="50000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]"/>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="18" NAME="BUS_STRUCT_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET" VECFORMULA="[0:C_NUM_BUS_RST-1]"/>
+        <PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_RST-1]"/>
+        <PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_0"/>
+            <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_0"/>
+            <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_0"/>
+            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_0"/>
+            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_0"/>
+            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_0"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_1"/>
+            <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_1"/>
+            <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_1"/>
+            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_1"/>
+            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_1"/>
+            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_1"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
+      </IOINTERFACES>
+    </MODULE>
+    <MODULE HWVERSION="4.01.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="IP" MODTYPE="clock_generator">
+      <DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_01_a/doc/clock_generator.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="6slx45t">
+          <DESCRIPTION>Device</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="fgg484">
+          <DESCRIPTION>Package</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-3">
+          <DESCRIPTION>Speed Grade</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="200000000">
+          <DESCRIPTION>Input Clock Frequency (Hz) </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="600000000">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="PLL0">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Buffered </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="600000000">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="INTEGER" VALUE="180">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="PLL0">
+          <DESCRIPTION>Required Group </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="PLL0">
+          <DESCRIPTION>Required Group </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Varaible Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="50000000">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="PLL0">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION> Varaible Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION> Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION> Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Clock Deskew</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Variable Phase Shift</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" VALUE="1"/>
+        <PARAMETER MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Clock Primitive Feedback Buffer</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="94" NAME="C_CLK_GEN" VALUE="UPDATE"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="RESET"/>
+        <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="CLK"/>
+        <PORT CLKFREQUENCY="100000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT CLKFREQUENCY="50000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT CLKFREQUENCY="600000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="clk_600_0000MHzPLL0_nobuf"/>
+        <PORT CLKFREQUENCY="600000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="clk_600_0000MHz180PLL0_nobuf"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="24" NAME="LOCKED" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="I" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="I" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/>
+        <PORT DIR="I" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE HWVERSION="2.00.b" INSTANCE="debug_module" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="DEBUG" MODTYPE="mdm">
+      <DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Debug module for MicroBlaze Soft Processor.</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/doc/mdm.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2">
+          <DESCRIPTION>Specifies the JTAG user-defined register used </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_INTERCONNECT" TYPE="INTEGER" VALUE="2">
+          <DESCRIPTION>Specifies the Bus Interface for the JTAG UART </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x74800000">
+          <DESCRIPTION>Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x7480ffff">
+          <DESCRIPTION>High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="3">
+          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="8">
+          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="12" NAME="C_MB_DBG_PORTS" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Number of MicroBlaze debug ports </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="13" NAME="C_USE_UART" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Enable JTAG UART </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>AXI4LITE protocal</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="Debug_SYS_Rst" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/>
+        <PORT DIR="O" MPD_INDEX="0" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT DEF_SIGNAME="Ext_BRK" DIR="O" MPD_INDEX="2" NAME="Ext_BRK" SIGNAME="Ext_BRK"/>
+        <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="O" MPD_INDEX="3" NAME="Ext_NM_BRK" SIGNAME="Ext_NM_BRK"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="5" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(C_S_AXI_DATA_WIDTH/8-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="11" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="12" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="15" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="17" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="21" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="22" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="25" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="26" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="27" NAME="PLB_PAValid" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="28" NAME="PLB_SAValid" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="29" NAME="PLB_rdPrim" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="30" NAME="PLB_wrPrim" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="31" MSB="0" NAME="PLB_masterID" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="32" NAME="PLB_abort" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="PLB_busLock" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="PLB_RNW" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="35" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="37" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="38" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="PLB_lockErr" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="40" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="PLB_wrBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="PLB_rdBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="PLB_wrPendReq" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="PLB_rdPendReq" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="46" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="48" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="49" NAME="Sl_addrAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="50" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="51" NAME="Sl_wait" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="52" NAME="Sl_rearbitrate" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="53" NAME="Sl_wrDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="54" NAME="Sl_wrComp" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="55" NAME="Sl_wrBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="56" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="Sl_rdDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="Sl_rdComp" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="Sl_rdBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="61" MSB="0" NAME="Sl_MBusy" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="62" MSB="0" NAME="Sl_MWrErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="63" MSB="0" NAME="Sl_MRdErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="64" MSB="0" NAME="Sl_MIRQ" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Clk" DIR="O" MPD_INDEX="65" NAME="Dbg_Clk_0" SIGNAME="microblaze_0_debug_Dbg_Clk"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDI" DIR="O" MPD_INDEX="66" NAME="Dbg_TDI_0" SIGNAME="microblaze_0_debug_Dbg_TDI"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDO" DIR="I" MPD_INDEX="67" NAME="Dbg_TDO_0" SIGNAME="microblaze_0_debug_Dbg_TDO"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Reg_En" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="68" MSB="0" NAME="Dbg_Reg_En_0" RIGHT="7" SIGNAME="microblaze_0_debug_Dbg_Reg_En" VECFORMULA="[0:7]"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Capture" DIR="O" MPD_INDEX="69" NAME="Dbg_Capture_0" SIGNAME="microblaze_0_debug_Dbg_Capture"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Shift" DIR="O" MPD_INDEX="70" NAME="Dbg_Shift_0" SIGNAME="microblaze_0_debug_Dbg_Shift"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Update" DIR="O" MPD_INDEX="71" NAME="Dbg_Update_0" SIGNAME="microblaze_0_debug_Dbg_Update"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Debug_Rst" DIR="O" MPD_INDEX="72" NAME="Dbg_Rst_0" SIGNAME="microblaze_0_debug_Debug_Rst"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="73" NAME="Dbg_Clk_1" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="74" NAME="Dbg_TDI_1" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="Dbg_TDO_1" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="76" MSB="0" NAME="Dbg_Reg_En_1" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="77" NAME="Dbg_Capture_1" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="Dbg_Shift_1" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="79" NAME="Dbg_Update_1" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="80" NAME="Dbg_Rst_1" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="81" NAME="Dbg_Clk_2" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="82" NAME="Dbg_TDI_2" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="83" NAME="Dbg_TDO_2" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="84" MSB="0" NAME="Dbg_Reg_En_2" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="85" NAME="Dbg_Capture_2" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="86" NAME="Dbg_Shift_2" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="Dbg_Update_2" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="Dbg_Rst_2" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="89" NAME="Dbg_Clk_3" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="Dbg_TDI_3" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="91" NAME="Dbg_TDO_3" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="92" MSB="0" NAME="Dbg_Reg_En_3" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="Dbg_Capture_3" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="Dbg_Shift_3" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="95" NAME="Dbg_Update_3" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="Dbg_Rst_3" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="Dbg_Clk_4" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="98" NAME="Dbg_TDI_4" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="Dbg_TDO_4" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="100" MSB="0" NAME="Dbg_Reg_En_4" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
+        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="Dbg_Capture_4" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="Dbg_Shift_4" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="Dbg_Update_4" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="Dbg_Rst_4" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="Dbg_Clk_5" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="Dbg_TDI_5" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="107" NAME="Dbg_TDO_5" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="108" MSB="0" NAME="Dbg_Reg_En_5" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
+        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="Dbg_Capture_5" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="110" NAME="Dbg_Shift_5" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="111" NAME="Dbg_Update_5" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="112" NAME="Dbg_Rst_5" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="Dbg_Clk_6" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="114" NAME="Dbg_TDI_6" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="115" NAME="Dbg_TDO_6" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="116" MSB="0" NAME="Dbg_Reg_En_6" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
+        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="Dbg_Capture_6" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="118" NAME="Dbg_Shift_6" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="119" NAME="Dbg_Update_6" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="120" NAME="Dbg_Rst_6" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="121" NAME="Dbg_Clk_7" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="Dbg_TDI_7" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="Dbg_TDO_7" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="124" MSB="0" NAME="Dbg_Reg_En_7" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
+        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="125" NAME="Dbg_Capture_7" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="126" NAME="Dbg_Shift_7" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="Dbg_Update_7" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="128" NAME="Dbg_Rst_7" SIGNAME="__NOC__"/>
+        <PORT DEF_SIGNAME="bscan_tdi" DIR="O" MPD_INDEX="129" NAME="bscan_tdi" SIGNAME="bscan_tdi"/>
+        <PORT DEF_SIGNAME="bscan_reset" DIR="O" MPD_INDEX="130" NAME="bscan_reset" SIGNAME="bscan_reset"/>
+        <PORT DEF_SIGNAME="bscan_shift" DIR="O" MPD_INDEX="131" NAME="bscan_shift" SIGNAME="bscan_shift"/>
+        <PORT DEF_SIGNAME="bscan_update" DIR="O" MPD_INDEX="132" NAME="bscan_update" SIGNAME="bscan_update"/>
+        <PORT DEF_SIGNAME="bscan_capture" DIR="O" MPD_INDEX="133" NAME="bscan_capture" SIGNAME="bscan_capture"/>
+        <PORT DEF_SIGNAME="bscan_sel1" DIR="O" MPD_INDEX="134" NAME="bscan_sel1" SIGNAME="bscan_sel1"/>
+        <PORT DEF_SIGNAME="bscan_drck1" DIR="O" MPD_INDEX="135" NAME="bscan_drck1" SIGNAME="bscan_drck1"/>
+        <PORT DEF_SIGNAME="bscan_tdo1" DIR="I" MPD_INDEX="136" NAME="bscan_tdo1" SIGNAME="bscan_tdo1"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="137" NAME="Ext_JTAG_DRCK" SIGNAME="__NOC__"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="138" NAME="Ext_JTAG_RESET" SIGNAME="__NOC__"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="139" NAME="Ext_JTAG_SEL" SIGNAME="__NOC__"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="140" NAME="Ext_JTAG_CAPTURE" SIGNAME="__NOC__"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="141" NAME="Ext_JTAG_SHIFT" SIGNAME="__NOC__"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="Ext_JTAG_UPDATE" SIGNAME="__NOC__"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="143" NAME="Ext_JTAG_TDI" SIGNAME="__NOC__"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="144" NAME="Ext_JTAG_TDO" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="1" NAME="SPLB" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="MBDEBUG_0" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_0"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_0"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_0"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_0"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_0"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_0"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_0"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_0"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="3" NAME="MBDEBUG_1" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_1"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_1"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_1"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_1"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_1"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_1"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_1"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_1"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="4" NAME="MBDEBUG_2" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_2"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_2"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_2"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_2"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_2"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_2"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_2"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_2"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="5" NAME="MBDEBUG_3" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_3"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_3"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_3"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_3"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_3"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_3"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_3"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_3"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="6" NAME="MBDEBUG_4" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_4"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_4"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_4"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_4"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_4"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_4"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_4"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_4"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="7" NAME="MBDEBUG_5" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_5"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_5"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_5"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_5"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_5"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_5"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_5"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_5"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="8" NAME="MBDEBUG_6" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_6"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_6"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_6"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_6"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_6"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_6"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_6"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_6"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="9" NAME="MBDEBUG_7" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_7"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_7"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_7"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_7"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_7"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_7"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_7"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_7"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_BSCAN" MPD_INDEX="10" NAME="XMTC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_DRCK"/>
+            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_RESET"/>
+            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SEL"/>
+            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_CAPTURE"/>
+            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SHIFT"/>
+            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_UPDATE"/>
+            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_TDI"/>
+            <PORTMAP DIR="I" PHYSICAL="Ext_JTAG_TDO"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="SPLB"/>
+            <SLAVE BUSINTERFACE="S_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+    </MODULE>
+    <MODULE HWVERSION="1.01.a" INSTANCE="RS232_Uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="axi_uartlite">
+      <DESCRIPTION TYPE="SHORT">AXI UART (Lite)</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_uartlite_v1_01_a/doc/axi_uartlite_ds741.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000">
+          <DESCRIPTION>AXI Clock Frequency </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40600000">
+          <DESCRIPTION>AXI Base Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4060ffff">
+          <DESCRIPTION>AXI High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="C_BAUDRATE" TYPE="INTEGER" VALUE="115200">
+          <DESCRIPTION>UART Lite Baud Rate </DESCRIPTION>
+          <DESCRIPTION>Baud Rate</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_DATA_BITS" TYPE="INTEGER" VALUE="8">
+          <DESCRIPTION>Number of Data Bits in a Serial Frame</DESCRIPTION>
+          <DESCRIPTION>Data Bits</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="8" NAME="C_USE_PARITY" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Use Parity </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="9" NAME="C_ODD_PARITY" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Parity Type </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="21" NAME="TX" SIGNAME="RS232_Uart_1_sout">
+          <DESCRIPTION>Serial Data Out</DESCRIPTION>
+        </PORT>
+        <PORT DIR="I" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="20" NAME="RX" SIGNAME="RS232_Uart_1_sin">
+          <DESCRIPTION>Serial Data In</DESCRIPTION>
+        </PORT>
+        <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="RS232_Uart_1_Interrupt"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="uart_0" TYPE="XIL_UART_V1_hide">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="TX"/>
+            <PORTMAP DIR="I" PHYSICAL="RX"/>
+          </PORTMAPS>
+        </IOINTERFACE>
+      </IOINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="3"/>
+      </INTERRUPTINFO>
+    </MODULE>
+    <MODULE HWVERSION="1.01.a" INSTANCE="LEDs_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
+      <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40020000">
+          <DESCRIPTION>AXI Base Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4002ffff">
+          <DESCRIPTION>AXI High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4">
+          <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
+          <DESCRIPTION>GPIO Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
+          <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
+          <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="LEDs_4Bits_TRI_O" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
+        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
+          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
+        </PORT>
+        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
+          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
+            <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
+            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
+            <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
+            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
+            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
+            <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
+            <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
+          </PORTMAPS>
+        </IOINTERFACE>
+      </IOINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+    </MODULE>
+    <MODULE HWVERSION="1.01.a" INSTANCE="Push_Buttons_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
+      <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40000000">
+          <DESCRIPTION>AXI Base Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4000ffff">
+          <DESCRIPTION>AXI High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4">
+          <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
+          <DESCRIPTION>GPIO Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
+          <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
+          <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
+        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
+          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
+        </PORT>
+        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
+          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
+            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
+            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
+            <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
+            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
+            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
+            <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
+            <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
+          </PORTMAPS>
+        </IOINTERFACE>
+      </IOINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="0"/>
+      </INTERRUPTINFO>
+    </MODULE>
+    <MODULE HWVERSION="1.02.a" INSTANCE="MCB_DDR3" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_s6_ddrx">
+      <DESCRIPTION TYPE="SHORT">AXI S6 Memory Controller(DDR/DDR2/DDR3)</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Spartan-6 memory controller</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_s6_ddrx_v1_02_a/doc/axi_s6_ddrx.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER MPD_INDEX="0" NAME="C_MCB_LOC" VALUE="MEMC3"/>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_MCB_RZQ_LOC" TYPE="STRING" VALUE="K7"/>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="C_MCB_ZIO_LOC" TYPE="STRING" VALUE="R7"/>
+        <PARAMETER MPD_INDEX="3" NAME="C_MCB_PERFORMANCE" TYPE="STRING" VALUE="STANDARD"/>
+        <PARAMETER MPD_INDEX="4" NAME="C_BYPASS_CORE_UCF" VALUE="0"/>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="5" NAME="C_S0_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xc0000000"/>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="6" NAME="C_S0_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xc7ffffff"/>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="7" NAME="C_S1_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="8" NAME="C_S1_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="9" NAME="C_S2_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="10" NAME="C_S2_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="11" NAME="C_S3_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="12" NAME="C_S3_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="13" NAME="C_S4_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="14" NAME="C_S4_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="15" NAME="C_S5_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="16" NAME="C_S5_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="C_MEM_TYPE" TYPE="STRING" VALUE="DDR3"/>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="18" NAME="C_MEM_PARTNO" TYPE="STRING" VALUE="MT41J64M16XX-187E"/>
+        <PARAMETER MPD_INDEX="19" NAME="C_MEM_BASEPARTNO" TYPE="STRING" VALUE="NOT_SET"/>
+        <PARAMETER MPD_INDEX="20" NAME="C_NUM_DQ_PINS" TYPE="INTEGER" VALUE="16"/>
+        <PARAMETER MPD_INDEX="21" NAME="C_MEM_ADDR_WIDTH" TYPE="INTEGER" VALUE="13"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="22" NAME="C_MEM_BANKADDR_WIDTH" TYPE="INTEGER" VALUE="3"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="23" NAME="C_MEM_NUM_COL_BITS" TYPE="INTEGER" VALUE="10"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="24" NAME="C_MEM_TRAS" TYPE="INTEGER" VALUE="37500"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="25" NAME="C_MEM_TRCD" TYPE="INTEGER" VALUE="13130"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="26" NAME="C_MEM_TREFI" TYPE="INTEGER" VALUE="7800000"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="27" NAME="C_MEM_TRFC" TYPE="INTEGER" VALUE="160000"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_MEM_TRP" TYPE="INTEGER" VALUE="13130"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="29" NAME="C_MEM_TWR" TYPE="INTEGER" VALUE="15000"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="30" NAME="C_MEM_TRTP" TYPE="INTEGER" VALUE="7500"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="31" NAME="C_MEM_TWTR" TYPE="INTEGER" VALUE="7500"/>
+        <PARAMETER MPD_INDEX="32" NAME="C_PORT_CONFIG" TYPE="STRING" VALUE="B32_B32_B32_B32"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="33" NAME="C_SKIP_IN_TERM_CAL" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="34" NAME="C_SKIP_IN_TERM_CAL_VALUE" TYPE="STRING" VALUE="NONE"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_MEMCLK_PERIOD" TYPE="INTEGER" VALUE="3333"/>
+        <PARAMETER MPD_INDEX="36" NAME="C_MEM_ADDR_ORDER" TYPE="STRING" VALUE="ROW_BANK_COLUMN"/>
+        <PARAMETER MPD_INDEX="37" NAME="C_MEM_TZQINIT_MAXCNT" TYPE="INTEGER" VALUE="512"/>
+        <PARAMETER MPD_INDEX="38" NAME="C_MEM_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/>
+        <PARAMETER MPD_INDEX="39" NAME="C_SIMULATION" TYPE="STRING" VALUE="FALSE"/>
+        <PARAMETER MPD_INDEX="40" NAME="C_MEM_DDR1_2_ODS" TYPE="STRING" VALUE="FULL"/>
+        <PARAMETER MPD_INDEX="41" NAME="C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/>
+        <PARAMETER MPD_INDEX="42" NAME="C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/>
+        <PARAMETER MPD_INDEX="43" NAME="C_MEM_DDR2_RTT" TYPE="STRING" VALUE="150OHMS"/>
+        <PARAMETER MPD_INDEX="44" NAME="C_MEM_DDR2_DIFF_DQS_EN" TYPE="STRING" VALUE="YES"/>
+        <PARAMETER MPD_INDEX="45" NAME="C_MEM_DDR2_3_PA_SR" TYPE="STRING" VALUE="FULL"/>
+        <PARAMETER MPD_INDEX="46" NAME="C_MEM_DDR2_3_HIGH_TEMP_SR" TYPE="STRING" VALUE="NORMAL"/>
+        <PARAMETER MPD_INDEX="47" NAME="C_MEM_DDR3_CAS_WR_LATENCY" TYPE="INTEGER" VALUE="5"/>
+        <PARAMETER MPD_INDEX="48" NAME="C_MEM_DDR3_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/>
+        <PARAMETER MPD_INDEX="49" NAME="C_MEM_DDR3_ODS" TYPE="STRING" VALUE="DIV6"/>
+        <PARAMETER MPD_INDEX="50" NAME="C_MEM_DDR3_RTT" TYPE="STRING" VALUE="DIV4"/>
+        <PARAMETER MPD_INDEX="51" NAME="C_MEM_DDR3_AUTO_SR" TYPE="STRING" VALUE="ENABLED"/>
+        <PARAMETER MPD_INDEX="52" NAME="C_MEM_MOBILE_PA_SR" TYPE="STRING" VALUE="FULL"/>
+        <PARAMETER MPD_INDEX="53" NAME="C_MEM_MDDR_ODS" TYPE="STRING" VALUE="FULL"/>
+        <PARAMETER MPD_INDEX="54" NAME="C_ARB_ALGORITHM" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="55" NAME="C_ARB_NUM_TIME_SLOTS" TYPE="INTEGER" VALUE="12"/>
+        <PARAMETER MPD_INDEX="56" NAME="C_ARB_TIME_SLOT_0" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
+        <PARAMETER MPD_INDEX="57" NAME="C_ARB_TIME_SLOT_1" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
+        <PARAMETER MPD_INDEX="58" NAME="C_ARB_TIME_SLOT_2" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
+        <PARAMETER MPD_INDEX="59" NAME="C_ARB_TIME_SLOT_3" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
+        <PARAMETER MPD_INDEX="60" NAME="C_ARB_TIME_SLOT_4" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
+        <PARAMETER MPD_INDEX="61" NAME="C_ARB_TIME_SLOT_5" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
+        <PARAMETER MPD_INDEX="62" NAME="C_ARB_TIME_SLOT_6" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
+        <PARAMETER MPD_INDEX="63" NAME="C_ARB_TIME_SLOT_7" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
+        <PARAMETER MPD_INDEX="64" NAME="C_ARB_TIME_SLOT_8" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
+        <PARAMETER MPD_INDEX="65" NAME="C_ARB_TIME_SLOT_9" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
+        <PARAMETER MPD_INDEX="66" NAME="C_ARB_TIME_SLOT_10" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
+        <PARAMETER MPD_INDEX="67" NAME="C_ARB_TIME_SLOT_11" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="68" NAME="C_S0_AXI_ENABLE" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="69" NAME="C_S0_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="70" NAME="C_S0_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="71" NAME="C_S0_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER MPD_INDEX="72" NAME="C_S0_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER MPD_INDEX="73" NAME="C_S0_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="74" NAME="C_S0_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="75" NAME="C_S0_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="76" NAME="C_S0_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/>
+        <PARAMETER MPD_INDEX="77" NAME="C_S0_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
+        <PARAMETER MPD_INDEX="78" NAME="C_S0_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="79" NAME="C_S0_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="80" NAME="C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="81" NAME="C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="82" NAME="C_S1_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="83" NAME="C_S1_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
+        <PARAMETER MPD_INDEX="84" NAME="C_S1_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="85" NAME="C_S1_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER MPD_INDEX="86" NAME="C_S1_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="87" NAME="C_S1_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="88" NAME="C_S1_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="89" NAME="C_S1_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="90" NAME="C_S1_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
+        <PARAMETER MPD_INDEX="91" NAME="C_S1_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
+        <PARAMETER MPD_INDEX="92" NAME="C_S1_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="93" NAME="C_S1_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="94" NAME="C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="95" NAME="C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="96" NAME="C_S2_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="97" NAME="C_S2_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
+        <PARAMETER MPD_INDEX="98" NAME="C_S2_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="99" NAME="C_S2_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER MPD_INDEX="100" NAME="C_S2_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="101" NAME="C_S2_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="102" NAME="C_S2_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="103" NAME="C_S2_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="104" NAME="C_S2_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
+        <PARAMETER MPD_INDEX="105" NAME="C_S2_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
+        <PARAMETER MPD_INDEX="106" NAME="C_S2_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="107" NAME="C_S2_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="108" NAME="C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="109" NAME="C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="110" NAME="C_S3_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="111" NAME="C_S3_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
+        <PARAMETER MPD_INDEX="112" NAME="C_S3_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="113" NAME="C_S3_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER MPD_INDEX="114" NAME="C_S3_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="115" NAME="C_S3_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="116" NAME="C_S3_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="117" NAME="C_S3_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="118" NAME="C_S3_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
+        <PARAMETER MPD_INDEX="119" NAME="C_S3_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
+        <PARAMETER MPD_INDEX="120" NAME="C_S3_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="121" NAME="C_S3_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="122" NAME="C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="123" NAME="C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="124" NAME="C_S4_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="125" NAME="C_S4_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
+        <PARAMETER MPD_INDEX="126" NAME="C_S4_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="127" NAME="C_S4_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER MPD_INDEX="128" NAME="C_S4_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="129" NAME="C_S4_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="130" NAME="C_S4_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="131" NAME="C_S4_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="132" NAME="C_S4_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
+        <PARAMETER MPD_INDEX="133" NAME="C_S4_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
+        <PARAMETER MPD_INDEX="134" NAME="C_S4_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="135" NAME="C_S4_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="136" NAME="C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="137" NAME="C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="138" NAME="C_S5_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="139" NAME="C_S5_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
+        <PARAMETER MPD_INDEX="140" NAME="C_S5_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="141" NAME="C_S5_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER MPD_INDEX="142" NAME="C_S5_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="143" NAME="C_S5_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="144" NAME="C_S5_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="145" NAME="C_S5_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="146" NAME="C_S5_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
+        <PARAMETER MPD_INDEX="147" NAME="C_S5_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
+        <PARAMETER MPD_INDEX="148" NAME="C_S5_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="149" NAME="C_S5_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="150" NAME="C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="151" NAME="C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="152" NAME="C_MCB_USE_EXTERNAL_BUFPLL" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="153" NAME="C_SYS_RST_PRESENT" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S0_AXI_MASTERS" VALUE="microblaze_0.M_AXI_DC &amp; microblaze_0.M_AXI_IC"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="11" NAME="C_INTERCONNECT_S0_AXI_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="12" NAME="C_INTERCONNECT_S0_AXI_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" NAME="C_INTERCONNECT_S0_AXI_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_S0_AXI_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_S0_AXI_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="17" NAME="mcbx_dram_clk" SIGIS="CLK" SIGNAME="mcbx_dram_clk"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="18" NAME="mcbx_dram_clk_n" SIGIS="CLK" SIGNAME="mcbx_dram_clk_n"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="16" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="26" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="13" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="14" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="15" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="24" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="25" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="9" MPD_INDEX="12" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba" VECFORMULA="[C_MEM_BANKADDR_WIDTH-1:0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="12" LSB="0" MHS_INDEX="10" MPD_INDEX="11" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr" VECFORMULA="[C_MEM_ADDR_WIDTH-1:0]"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="27" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
+        <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="15" LSB="0" MHS_INDEX="12" MPD_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq" VECFORMULA="[C_NUM_DQ_PINS-1:0]"/>
+        <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="13" MPD_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
+        <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="14" MPD_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
+        <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="15" MPD_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
+        <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="16" MPD_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
+        <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="17" MPD_INDEX="28" NAME="rzq" SIGNAME="rzq"/>
+        <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="18" MPD_INDEX="29" NAME="zio" SIGNAME="zio"/>
+        <PORT BUS="S0_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="32" NAME="s0_axi_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="30" NAME="ui_clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT CLKFREQUENCY="600000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="0" NAME="sysclk_2x" SIGIS="CLK" SIGNAME="clk_600_0000MHzPLL0_nobuf"/>
+        <PORT CLKFREQUENCY="600000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="1" NAME="sysclk_2x_180" SIGIS="CLK" SIGNAME="clk_600_0000MHz180PLL0_nobuf"/>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="10" NAME="SYS_RST" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="4" NAME="PLL_LOCK" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
+        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="2" NAME="pll_ce_0" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="3" NAME="pll_ce_90" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="5" NAME="pll_lock_bufpll_o" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="6" NAME="sysclk_2x_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="7" NAME="sysclk_2x_180_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="8" NAME="pll_ce_0_bufpll_o" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="9" NAME="pll_ce_90_bufpll_o" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="31" NAME="uo_done_cal" SIGNAME="__NOC__"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_aresetn" DIR="I" MPD_INDEX="33" NAME="s0_axi_aresetn" SIGIS="RST" SIGNAME="axi4_0_M_aresetn"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awid" DIR="I" MPD_INDEX="34" NAME="s0_axi_awid" SIGNAME="axi4_0_M_awid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awaddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="35" MSB="31" NAME="s0_axi_awaddr" RIGHT="0" SIGNAME="axi4_0_M_awaddr" VECFORMULA="[(C_S0_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="36" MSB="7" NAME="s0_axi_awlen" RIGHT="0" SIGNAME="axi4_0_M_awlen" VECFORMULA="[7:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="37" MSB="2" NAME="s0_axi_awsize" RIGHT="0" SIGNAME="axi4_0_M_awsize" VECFORMULA="[2:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="38" MSB="1" NAME="s0_axi_awburst" RIGHT="0" SIGNAME="axi4_0_M_awburst" VECFORMULA="[1:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awlock" DIR="I" MPD_INDEX="39" NAME="s0_axi_awlock" SIGNAME="axi4_0_M_awlock" VECFORMULA="[0:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="40" MSB="3" NAME="s0_axi_awcache" RIGHT="0" SIGNAME="axi4_0_M_awcache" VECFORMULA="[3:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="41" MSB="2" NAME="s0_axi_awprot" RIGHT="0" SIGNAME="axi4_0_M_awprot" VECFORMULA="[2:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="42" MSB="3" NAME="s0_axi_awqos" RIGHT="0" SIGNAME="axi4_0_M_awqos" VECFORMULA="[3:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awvalid" DIR="I" MPD_INDEX="43" NAME="s0_axi_awvalid" SIGNAME="axi4_0_M_awvalid"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awready" DIR="O" MPD_INDEX="44" NAME="s0_axi_awready" SIGNAME="axi4_0_M_awready"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wdata" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="45" MSB="31" NAME="s0_axi_wdata" RIGHT="0" SIGNAME="axi4_0_M_wdata" VECFORMULA="[(C_S0_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wstrb" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="46" MSB="3" NAME="s0_axi_wstrb" RIGHT="0" SIGNAME="axi4_0_M_wstrb" VECFORMULA="[((C_S0_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wlast" DIR="I" MPD_INDEX="47" NAME="s0_axi_wlast" SIGNAME="axi4_0_M_wlast"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wvalid" DIR="I" MPD_INDEX="48" NAME="s0_axi_wvalid" SIGNAME="axi4_0_M_wvalid"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wready" DIR="O" MPD_INDEX="49" NAME="s0_axi_wready" SIGNAME="axi4_0_M_wready"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bid" DIR="O" MPD_INDEX="50" NAME="s0_axi_bid" SIGNAME="axi4_0_M_bid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="51" MSB="1" NAME="s0_axi_bresp" RIGHT="0" SIGNAME="axi4_0_M_bresp" VECFORMULA="[1:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bvalid" DIR="O" MPD_INDEX="52" NAME="s0_axi_bvalid" SIGNAME="axi4_0_M_bvalid"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bready" DIR="I" MPD_INDEX="53" NAME="s0_axi_bready" SIGNAME="axi4_0_M_bready"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arid" DIR="I" MPD_INDEX="54" NAME="s0_axi_arid" SIGNAME="axi4_0_M_arid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_araddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="55" MSB="31" NAME="s0_axi_araddr" RIGHT="0" SIGNAME="axi4_0_M_araddr" VECFORMULA="[(C_S0_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="56" MSB="7" NAME="s0_axi_arlen" RIGHT="0" SIGNAME="axi4_0_M_arlen" VECFORMULA="[7:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="57" MSB="2" NAME="s0_axi_arsize" RIGHT="0" SIGNAME="axi4_0_M_arsize" VECFORMULA="[2:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="58" MSB="1" NAME="s0_axi_arburst" RIGHT="0" SIGNAME="axi4_0_M_arburst" VECFORMULA="[1:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arlock" DIR="I" MPD_INDEX="59" NAME="s0_axi_arlock" SIGNAME="axi4_0_M_arlock" VECFORMULA="[0:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="60" MSB="3" NAME="s0_axi_arcache" RIGHT="0" SIGNAME="axi4_0_M_arcache" VECFORMULA="[3:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="61" MSB="2" NAME="s0_axi_arprot" RIGHT="0" SIGNAME="axi4_0_M_arprot" VECFORMULA="[2:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="62" MSB="3" NAME="s0_axi_arqos" RIGHT="0" SIGNAME="axi4_0_M_arqos" VECFORMULA="[3:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arvalid" DIR="I" MPD_INDEX="63" NAME="s0_axi_arvalid" SIGNAME="axi4_0_M_arvalid"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arready" DIR="O" MPD_INDEX="64" NAME="s0_axi_arready" SIGNAME="axi4_0_M_arready"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rid" DIR="O" MPD_INDEX="65" NAME="s0_axi_rid" SIGNAME="axi4_0_M_rid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rdata" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="s0_axi_rdata" RIGHT="0" SIGNAME="axi4_0_M_rdata" VECFORMULA="[(C_S0_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="67" MSB="1" NAME="s0_axi_rresp" RIGHT="0" SIGNAME="axi4_0_M_rresp" VECFORMULA="[1:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rlast" DIR="O" MPD_INDEX="68" NAME="s0_axi_rlast" SIGNAME="axi4_0_M_rlast"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rvalid" DIR="O" MPD_INDEX="69" NAME="s0_axi_rvalid" SIGNAME="axi4_0_M_rvalid"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_rready" DIR="I" MPD_INDEX="70" NAME="s0_axi_rready" SIGNAME="axi4_0_M_rready"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="71" NAME="s1_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="s1_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="73" MSB="3" NAME="s1_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="74" MSB="31" NAME="s1_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="75" MSB="7" NAME="s1_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="76" MSB="2" NAME="s1_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="s1_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="s1_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="79" MSB="3" NAME="s1_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="80" MSB="2" NAME="s1_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="81" MSB="3" NAME="s1_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="s1_axi_awvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="83" NAME="s1_axi_awready" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="84" MSB="31" NAME="s1_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="85" MSB="3" NAME="s1_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S1_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="86" NAME="s1_axi_wlast" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="87" NAME="s1_axi_wvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="s1_axi_wready" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="89" MSB="3" NAME="s1_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="90" MSB="1" NAME="s1_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="91" NAME="s1_axi_bvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="92" NAME="s1_axi_bready" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="93" MSB="3" NAME="s1_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="s1_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="95" MSB="7" NAME="s1_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="96" MSB="2" NAME="s1_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="97" MSB="1" NAME="s1_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="s1_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="99" MSB="3" NAME="s1_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="100" MSB="2" NAME="s1_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="101" MSB="3" NAME="s1_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="s1_axi_arvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="s1_axi_arready" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="104" MSB="3" NAME="s1_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="105" MSB="31" NAME="s1_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S1_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="106" MSB="1" NAME="s1_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="107" NAME="s1_axi_rlast" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="s1_axi_rvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S1_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="s1_axi_rready" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="110" NAME="s2_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="111" NAME="s2_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="112" MSB="3" NAME="s2_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="113" MSB="31" NAME="s2_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="s2_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="115" MSB="2" NAME="s2_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="116" MSB="1" NAME="s2_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="117" NAME="s2_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="118" MSB="3" NAME="s2_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="119" MSB="2" NAME="s2_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="120" MSB="3" NAME="s2_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="121" NAME="s2_axi_awvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="s2_axi_awready" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="123" MSB="31" NAME="s2_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="124" MSB="3" NAME="s2_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S2_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="125" NAME="s2_axi_wlast" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="126" NAME="s2_axi_wvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="s2_axi_wready" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="128" MSB="3" NAME="s2_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="129" MSB="1" NAME="s2_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="130" NAME="s2_axi_bvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="131" NAME="s2_axi_bready" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="132" MSB="3" NAME="s2_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="133" MSB="31" NAME="s2_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="s2_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="135" MSB="2" NAME="s2_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="136" MSB="1" NAME="s2_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="137" NAME="s2_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="138" MSB="3" NAME="s2_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="139" MSB="2" NAME="s2_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="140" MSB="3" NAME="s2_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="141" NAME="s2_axi_arvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="s2_axi_arready" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="143" MSB="3" NAME="s2_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="144" MSB="31" NAME="s2_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="145" MSB="1" NAME="s2_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="146" NAME="s2_axi_rlast" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="147" NAME="s2_axi_rvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S2_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="148" NAME="s2_axi_rready" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="149" NAME="s3_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="150" NAME="s3_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="151" MSB="3" NAME="s3_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="152" MSB="31" NAME="s3_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="153" MSB="7" NAME="s3_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="154" MSB="2" NAME="s3_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="155" MSB="1" NAME="s3_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="156" NAME="s3_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="157" MSB="3" NAME="s3_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="158" MSB="2" NAME="s3_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="159" MSB="3" NAME="s3_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="160" NAME="s3_axi_awvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="161" NAME="s3_axi_awready" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="162" MSB="31" NAME="s3_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="163" MSB="3" NAME="s3_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S3_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="164" NAME="s3_axi_wlast" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="165" NAME="s3_axi_wvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="166" NAME="s3_axi_wready" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="167" MSB="3" NAME="s3_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="168" MSB="1" NAME="s3_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="169" NAME="s3_axi_bvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="170" NAME="s3_axi_bready" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="171" MSB="3" NAME="s3_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="172" MSB="31" NAME="s3_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="173" MSB="7" NAME="s3_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="174" MSB="2" NAME="s3_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="175" MSB="1" NAME="s3_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="176" NAME="s3_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="177" MSB="3" NAME="s3_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="178" MSB="2" NAME="s3_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="179" MSB="3" NAME="s3_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="180" NAME="s3_axi_arvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="181" NAME="s3_axi_arready" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="182" MSB="3" NAME="s3_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="183" MSB="31" NAME="s3_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="184" MSB="1" NAME="s3_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="185" NAME="s3_axi_rlast" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="186" NAME="s3_axi_rvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="187" NAME="s3_axi_rready" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="188" NAME="s4_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="189" NAME="s4_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="190" MSB="3" NAME="s4_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="191" MSB="31" NAME="s4_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="192" MSB="7" NAME="s4_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="193" MSB="2" NAME="s4_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="194" MSB="1" NAME="s4_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="195" NAME="s4_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="196" MSB="3" NAME="s4_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="197" MSB="2" NAME="s4_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="198" MSB="3" NAME="s4_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="199" NAME="s4_axi_awvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="200" NAME="s4_axi_awready" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="201" MSB="31" NAME="s4_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="202" MSB="3" NAME="s4_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S4_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="203" NAME="s4_axi_wlast" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="204" NAME="s4_axi_wvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="205" NAME="s4_axi_wready" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="206" MSB="3" NAME="s4_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="207" MSB="1" NAME="s4_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="208" NAME="s4_axi_bvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="209" NAME="s4_axi_bready" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="210" MSB="3" NAME="s4_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="211" MSB="31" NAME="s4_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="212" MSB="7" NAME="s4_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="213" MSB="2" NAME="s4_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="214" MSB="1" NAME="s4_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="215" NAME="s4_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="216" MSB="3" NAME="s4_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="217" MSB="2" NAME="s4_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="218" MSB="3" NAME="s4_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="219" NAME="s4_axi_arvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="220" NAME="s4_axi_arready" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="221" MSB="3" NAME="s4_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="222" MSB="31" NAME="s4_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="223" MSB="1" NAME="s4_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="224" NAME="s4_axi_rlast" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="225" NAME="s4_axi_rvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="226" NAME="s4_axi_rready" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="227" NAME="s5_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="228" NAME="s5_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="229" MSB="3" NAME="s5_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="230" MSB="31" NAME="s5_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="231" MSB="7" NAME="s5_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="232" MSB="2" NAME="s5_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="233" MSB="1" NAME="s5_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="234" NAME="s5_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="235" MSB="3" NAME="s5_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="236" MSB="2" NAME="s5_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="237" MSB="3" NAME="s5_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="238" NAME="s5_axi_awvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="239" NAME="s5_axi_awready" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="240" MSB="31" NAME="s5_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="241" MSB="3" NAME="s5_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S5_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="242" NAME="s5_axi_wlast" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="243" NAME="s5_axi_wvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="244" NAME="s5_axi_wready" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="245" MSB="3" NAME="s5_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="246" MSB="1" NAME="s5_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="247" NAME="s5_axi_bvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="248" NAME="s5_axi_bready" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="249" MSB="3" NAME="s5_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="250" MSB="31" NAME="s5_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="251" MSB="7" NAME="s5_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="252" MSB="2" NAME="s5_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="253" MSB="1" NAME="s5_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="254" NAME="s5_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="255" MSB="3" NAME="s5_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="256" MSB="2" NAME="s5_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="257" MSB="3" NAME="s5_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="258" NAME="s5_axi_arvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="259" NAME="s5_axi_arready" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="260" MSB="3" NAME="s5_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="261" MSB="31" NAME="s5_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="262" MSB="1" NAME="s5_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="263" NAME="s5_axi_rlast" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="s5_axi_rvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="265" NAME="s5_axi_rready" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S0_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_aresetn"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awid"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awaddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_awready"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_wdata"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_wstrb"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_wlast"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_wvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_wready"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_bid"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_bresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_bvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_bready"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arid"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_araddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_arready"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_rid"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_rdata"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_rresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_rlast"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_rvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_rready"/>
+          </PORTMAPS>
+          <MASTERS>
+            <MASTER BUSINTERFACE="M_AXI_DC" INSTANCE="microblaze_0"/>
+            <MASTER BUSINTERFACE="M_AXI_IC" INSTANCE="microblaze_0"/>
+          </MASTERS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="1" NAME="S1_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_aresetn"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awid"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awaddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_awready"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_wdata"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_wstrb"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_wlast"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_wvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_wready"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_bid"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_bresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_bvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_bready"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arid"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_araddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_arready"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_rid"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_rdata"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_rresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_rlast"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_rvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="2" NAME="S2_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_aresetn"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awid"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awaddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_awready"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_wdata"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_wstrb"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_wlast"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_wvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_wready"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_bid"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_bresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_bvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_bready"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arid"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_araddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_arready"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_rid"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_rdata"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_rresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_rlast"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_rvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S3_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_aresetn"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awid"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awaddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_awready"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_wdata"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_wstrb"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_wlast"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_wvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_wready"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_bid"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_bresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_bvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_bready"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arid"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_araddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_arready"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_rid"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_rdata"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_rresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_rlast"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_rvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="4" NAME="S4_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_aresetn"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awid"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awaddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_awready"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_wdata"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_wstrb"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_wlast"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_wvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_wready"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_bid"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_bresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_bvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_bready"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arid"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_araddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_arready"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_rid"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_rdata"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_rresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_rlast"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_rvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="5" NAME="S5_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_aresetn"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awid"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awaddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_awready"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_wdata"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_wstrb"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_wlast"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_wvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_wready"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_bid"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_bresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_bvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_bready"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arid"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_araddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_arready"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_rid"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_rdata"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_rresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_rlast"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_rvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="memory_0" TYPE="hide_122_XIL_MEMORY_V1">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk_n"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cke"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_odt"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ras_n"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cas_n"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_we_n"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_udm"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ldm"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ba"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_addr"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ddr3_rst"/>
+            <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dq"/>
+            <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs"/>
+            <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs_n"/>
+            <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs"/>
+            <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs_n"/>
+            <PORTMAP DIR="IO" PHYSICAL="rzq"/>
+            <PORTMAP DIR="IO" PHYSICAL="zio"/>
+          </PORTMAPS>
+        </IOINTERFACE>
+      </IOINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0xc0000000" HIGHDECIMAL="3355443199" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0xc7ffffff" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="134217728" SIZEABRV="128M">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S0_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S1_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S1_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S1_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S2_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S2_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S2_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S3_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S3_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S3_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S4_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S4_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S4_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S5_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S5_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S5_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+    </MODULE>
+    <MODULE HWVERSION="1.00.a" INSTANCE="Ethernet_Lite" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="axi_ethernetlite">
+      <DESCRIPTION TYPE="SHORT">AXI 10/100 Ethernet MAC Lite</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation'</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_ethernetlite_v1_00_a/doc/ds787_axi_ethernetlite.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" VALUE="AXI4LITE">
+          <DESCRIPTION>AXI protocol selection </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40e00000">
+          <DESCRIPTION>Ethernetlite Base Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x40e0ffff">
+          <DESCRIPTION>Ethernetlite High Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_S_AXI_ACLK_PERIOD_PS" TYPE="INTEGER" VALUE="20000">
+          <DESCRIPTION>AXI System Clock Period </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Interface Addresses Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Interface Data Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="7" NAME="C_S_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Width of ID Bus on AXI4 </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_INCLUDE_MDIO" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Include MII Management Module</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_INCLUDE_GLOBAL_BUFFERS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Include Global Buffers for PHY clocks</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_INCLUDE_INTERNAL_LOOPBACK" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Include Internal Loopback</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_DUPLEX" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Duplex Mode </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="12" NAME="C_TX_PING_PONG" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Include Second Transmitter Buffer </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="13" NAME="C_RX_PING_PONG" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Include Second Receiver Buffer </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_INCLUDE_PHY_CONSTRAINTS" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Include PHY I/O Constraints </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Interconnect write acceptance </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="16" NAME="C_INTERCONNECT_S_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Interconnect read acceptance </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="17" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Support Narrow Burst on AXI4 </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="IO" IOS="ethernet_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="0" MPD_INDEX="48" NAME="PHY_MDIO" SIGNAME="Ethernet_Lite_MDIO" TRI_I="PHY_MDIO_I" TRI_O="PHY_MDIO_O" TRI_T="PHY_MDIO_T">
+          <DESCRIPTION>Ethernet PHY Management Data</DESCRIPTION>
+        </PORT>
+        <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="44" NAME="PHY_MDC" SIGNAME="Ethernet_Lite_MDC">
+          <DESCRIPTION>Ethernet PHY Management Clock</DESCRIPTION>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="ethernet_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="2" MPD_INDEX="43" MSB="3" NAME="PHY_tx_data" RIGHT="0" SIGNAME="Ethernet_Lite_TXD" VECFORMULA="[3:0]">
+          <DESCRIPTION>Ethernet Transmit Data Output</DESCRIPTION>
+        </PORT>
+        <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="42" NAME="PHY_tx_en" SIGNAME="Ethernet_Lite_TX_EN">
+          <DESCRIPTION>Ethernet Transmit Enable</DESCRIPTION>
+        </PORT>
+        <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="34" NAME="PHY_tx_clk" SIGNAME="Ethernet_Lite_TX_CLK">
+          <DESCRIPTION>Ethernet Transmit Clock Input</DESCRIPTION>
+        </PORT>
+        <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="39" NAME="PHY_col" SIGNAME="Ethernet_Lite_COL">
+          <DESCRIPTION>Ethernet Collision Input</DESCRIPTION>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="ethernet_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="6" MPD_INDEX="38" MSB="3" NAME="PHY_rx_data" RIGHT="0" SIGNAME="Ethernet_Lite_RXD" VECFORMULA="[3:0]">
+          <DESCRIPTION>Ethernet Receive Data Input</DESCRIPTION>
+        </PORT>
+        <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="40" NAME="PHY_rx_er" SIGNAME="Ethernet_Lite_RX_ER">
+          <DESCRIPTION>Ethernet Receive Error Input</DESCRIPTION>
+        </PORT>
+        <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="35" NAME="PHY_rx_clk" SIGNAME="Ethernet_Lite_RX_CLK">
+          <DESCRIPTION>Ethernet Receive Clock Input</DESCRIPTION>
+        </PORT>
+        <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="36" NAME="PHY_crs" SIGNAME="Ethernet_Lite_CRS">
+          <DESCRIPTION>Ethernet Carrier Sense Input</DESCRIPTION>
+        </PORT>
+        <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="37" NAME="PHY_dv" SIGNAME="Ethernet_Lite_RX_DV">
+          <DESCRIPTION>Ethernet Receive Data Valid</DESCRIPTION>
+        </PORT>
+        <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="41" NAME="PHY_rst_n" SIGNAME="Ethernet_Lite_PHY_RST_N">
+          <DESCRIPTION>Ethernet PHY Reset</DESCRIPTION>
+        </PORT>
+        <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="2" NAME="IP2INTC_Irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWID" SIGNAME="axi4lite_0_M_AWID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="5" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_M_AWLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="6" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_AWSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="7" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_M_AWBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="8" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_AWCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="10" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="11" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WLAST" DIR="I" MPD_INDEX="13" NAME="S_AXI_WLAST" SIGNAME="axi4lite_0_M_WLAST"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BID" DIR="O" MPD_INDEX="16" NAME="S_AXI_BID" SIGNAME="axi4lite_0_M_BID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARID" SIGNAME="axi4lite_0_M_ARID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="21" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="22" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_M_ARLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="23" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_ARSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_M_ARBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_ARCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="26" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="27" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RID" DIR="O" MPD_INDEX="28" NAME="S_AXI_RID" SIGNAME="axi4lite_0_M_RID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="29" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="30" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RLAST" DIR="O" MPD_INDEX="31" NAME="S_AXI_RLAST" SIGNAME="axi4lite_0_M_RLAST"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="32" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="33" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
+        <PORT DIR="I" IOS="ethernet_0" MPD_INDEX="45" NAME="PHY_MDIO_I" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IOS="ethernet_0" MPD_INDEX="46" NAME="PHY_MDIO_O" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IOS="ethernet_0" MPD_INDEX="47" NAME="PHY_MDIO_T" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWLEN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWSIZE"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWBURST"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWCACHE"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARLEN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARSIZE"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARBURST"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARCACHE"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="ethernet_0" TYPE="XIL_AXIETHERNET_V1">
+          <PORTMAPS>
+            <PORTMAP DIR="IO" PHYSICAL="PHY_MDIO"/>
+            <PORTMAP DIR="O" PHYSICAL="PHY_MDC"/>
+            <PORTMAP DIR="O" PHYSICAL="PHY_tx_data"/>
+            <PORTMAP DIR="O" PHYSICAL="PHY_tx_en"/>
+            <PORTMAP DIR="I" PHYSICAL="PHY_tx_clk"/>
+            <PORTMAP DIR="I" PHYSICAL="PHY_col"/>
+            <PORTMAP DIR="I" PHYSICAL="PHY_rx_data"/>
+            <PORTMAP DIR="I" PHYSICAL="PHY_rx_er"/>
+            <PORTMAP DIR="I" PHYSICAL="PHY_rx_clk"/>
+            <PORTMAP DIR="I" PHYSICAL="PHY_crs"/>
+            <PORTMAP DIR="I" PHYSICAL="PHY_dv"/>
+            <PORTMAP DIR="O" PHYSICAL="PHY_rst_n"/>
+            <PORTMAP DIR="I" PHYSICAL="PHY_MDIO_I"/>
+            <PORTMAP DIR="O" PHYSICAL="PHY_MDIO_O"/>
+            <PORTMAP DIR="O" PHYSICAL="PHY_MDIO_T"/>
+          </PORTMAPS>
+        </IOINTERFACE>
+      </IOINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="1088421888" BASENAME="C_BASEADDR" BASEVALUE="0x40e00000" HIGHDECIMAL="1088487423" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40e0ffff" MEMTYPE="REGISTER" MINSIZE="0x02000" SIZE="65536" SIZEABRV="64K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="1"/>
+      </INTERRUPTINFO>
+    </MODULE>
+    <MODULE HWVERSION="1.01.a" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="PERIPHERAL" MODTYPE="axi_timer">
+      <DESCRIPTION TYPE="SHORT">AXI Timer/Counter</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Timer counter with AXI interface</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_timer_v1_01_a/doc/axi_timer_ds764.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_COUNT_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>The Width of Counter in Timer</DESCRIPTION>
+          <DESCRIPTION>Count Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="C_ONE_TIMER_ONLY" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Only One Timer is present</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_TRIG0_ASSERT" TYPE="std_logic" VALUE="1">
+          <DESCRIPTION>TRIG0 Active Level</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_TRIG1_ASSERT" TYPE="std_logic" VALUE="1">
+          <DESCRIPTION>TRIG1 Active Level</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_GEN0_ASSERT" TYPE="std_logic" VALUE="1">
+          <DESCRIPTION>GEN0 Active Level</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_GEN1_ASSERT" TYPE="std_logic" VALUE="1">
+          <DESCRIPTION>GEN1 Active Level</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="8" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41c00000">
+          <DESCRIPTION>AXI Base Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="9" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x41c0ffff">
+          <DESCRIPTION>AXI High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="7" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="5" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="axi_timer_0_Interrupt"/>
+        <PORT DIR="I" MPD_INDEX="0" NAME="CaptureTrig0" SIGNAME="__NOC__">
+          <DESCRIPTION>Capture Trig 0</DESCRIPTION>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="1" NAME="CaptureTrig1" SIGNAME="__NOC__">
+          <DESCRIPTION>Capture Trig 1</DESCRIPTION>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="2" NAME="GenerateOut0" SIGNAME="__NOC__">
+          <DESCRIPTION>Generate Out 0</DESCRIPTION>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="3" NAME="GenerateOut1" SIGNAME="__NOC__">
+          <DESCRIPTION>Generate Out 1</DESCRIPTION>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="4" NAME="PWM0" SIGNAME="__NOC__">
+          <DESCRIPTION>Pulse Width Modulation 0</DESCRIPTION>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="6" NAME="Freeze" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="8" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="10" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="13" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="21" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="22" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="24" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="25" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="2"/>
+      </INTERRUPTINFO>
+    </MODULE>
+    <MODULE HWVERSION="1.01.a" INSTANCE="microblaze_0_intc" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc">
+      <DESCRIPTION TYPE="SHORT">AXI Interrupt Controller</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">intc core attached to the AXI</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_intc_v1_01_a/doc/ds747_axi_intc.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41200000">
+          <DESCRIPTION>AXI Base Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4120ffff">
+          <DESCRIPTION>AXI High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_NUM_INTR_INPUTS" TYPE="INTEGER" VALUE="4">
+          <DESCRIPTION>Number of Interrupt Inputs </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_KIND_OF_INTR" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111110111">
+          <DESCRIPTION>Type of Interrupt for Each Input </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_KIND_OF_EDGE" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
+          <DESCRIPTION>Type of Each Edge Senstive Interrupt </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_KIND_OF_LVL" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
+          <DESCRIPTION>Type of Each Level Sensitive Interrupt </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_HAS_IPR" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Support IPR </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_HAS_SIE" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Support SIE </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_HAS_CIE" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Support CIE </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="12" NAME="C_HAS_IVR" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Support IVR </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="13" NAME="C_IRQ_IS_LEVEL" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>IRQ Output Use Level </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1">
+          <DESCRIPTION>The Sense of IRQ Output </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="20" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt">
+          <DESCRIPTION>Interrupt Request Output</DESCRIPTION>
+        </PORT>
+        <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="2" MPD_INDEX="19" MSB="3" NAME="INTR" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt &amp; Ethernet_Lite_IP2INTC_Irpt &amp; axi_timer_0_Interrupt &amp; RS232_Uart_1_Interrupt" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]">
+          <SIGNALS>
+            <SIGNAL NAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
+            <SIGNAL NAME="Ethernet_Lite_IP2INTC_Irpt"/>
+            <SIGNAL NAME="axi_timer_0_Interrupt"/>
+            <SIGNAL NAME="RS232_Uart_1_Interrupt"/>
+          </SIGNALS>
+          <DESCRIPTION>Interrupt Inputs</DESCRIPTION>
+        </PORT>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+      <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
+        <SOURCE INSTANCE="Push_Buttons_4Bits" PRIORITY="0" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
+        <SOURCE INSTANCE="Ethernet_Lite" PRIORITY="1" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
+        <SOURCE INSTANCE="axi_timer_0" PRIORITY="2" SIGNAME="axi_timer_0_Interrupt"/>
+        <SOURCE INSTANCE="RS232_Uart_1" PRIORITY="3" SIGNAME="RS232_Uart_1_Interrupt"/>
+        <TARGET INSTANCE="microblaze_0"/>
+      </INTERRUPTINFO>
+    </MODULE>
+  </MODULES>
+
+</EDKSYSTEM>
\ No newline at end of file

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/HardwareWithEthernetLite/system_bd.bmm b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/HardwareWithEthernetLite/system_bd.bmm
new file mode 100644 (file)
index 0000000..ca5622c
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/HardwareWithEthernetLite/system_bd.bmm
@@ -0,0 +1,32 @@
+// BMM LOC annotation file.\r
+//\r
+// Release 13.1 - Data2MEM O.40d, build 1.9 Aug 19, 2010\r
+// Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.\r
+\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+//\r
+// Processor 'microblaze_0', ID 100, memory map.\r
+//\r
+///////////////////////////////////////////////////////////////////////////////\r
+\r
+ADDRESS_MAP microblaze_0 MICROBLAZE-LE 100\r
+\r
+\r
+    ///////////////////////////////////////////////////////////////////////////////\r
+    //\r
+    // Processor 'microblaze_0' address space 'microblaze_0_bram_block_combined' 0x00000000:0x00001FFF (8 KBytes).\r
+    //\r
+    ///////////////////////////////////////////////////////////////////////////////\r
+\r
+    ADDRESS_SPACE microblaze_0_bram_block_combined RAMB16 [0x00000000:0x00001FFF]\r
+        BUS_BLOCK\r
+            microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_0 [31:24] INPUT = microblaze_0_bram_block_combined_0.mem PLACED = X1Y30;\r
+            microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_1 [23:16] INPUT = microblaze_0_bram_block_combined_1.mem PLACED = X1Y32;\r
+            microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_2 [15:8] INPUT = microblaze_0_bram_block_combined_2.mem PLACED = X0Y30;\r
+            microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_3 [7:0] INPUT = microblaze_0_bram_block_combined_3.mem PLACED = X0Y32;\r
+        END_BUS_BLOCK;\r
+    END_ADDRESS_SPACE;\r
+\r
+END_ADDRESS_MAP;\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/.cproject b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/.cproject
new file mode 100644 (file)
index 0000000..c6fbd0b
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/.cproject
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 4.0.0?>\r
+\r
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
+       <storageModule moduleId="org.eclipse.cdt.core.settings">\r
+               <cconfiguration id="org.eclipse.cdt.core.default.config.1102591381">\r
+                       <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1102591381" moduleId="org.eclipse.cdt.core.settings" name="Configuration">\r
+                               <externalSettings/>\r
+                               <extensions/>\r
+                       </storageModule>\r
+                       <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+               </cconfiguration>\r
+       </storageModule>\r
+</cproject>\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/.project b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/.project
new file mode 100644 (file)
index 0000000..7c08598
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/.project
@@ -0,0 +1,77 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+       <name>RTOSDemoBSP</name>\r
+       <comment></comment>\r
+       <projects>\r
+               <project>HardwareWithEthernetLite</project>\r
+       </projects>\r
+       <buildSpec>\r
+               <buildCommand>\r
+                       <name>org.eclipse.cdt.make.core.makeBuilder</name>\r
+                       <triggers>clean,full,incremental,</triggers>\r
+                       <arguments>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.core.errorOutputParser</key>\r
+                                       <value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.append_environment</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.build.arguments</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.build.command</key>\r
+                                       <value>make</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.build.target.auto</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.build.target.clean</key>\r
+                                       <value>clean</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.build.target.inc</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+                                       <value>false</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.environment</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+                                       <value>false</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                       </arguments>\r
+               </buildCommand>\r
+       </buildSpec>\r
+       <natures>\r
+               <nature>com.xilinx.sdk.sw.SwProjectNature</nature>\r
+               <nature>org.eclipse.cdt.core.cnature</nature>\r
+               <nature>org.eclipse.cdt.make.core.makeNature</nature>\r
+       </natures>\r
+</projectDescription>\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/.sdkproject b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/.sdkproject
new file mode 100644 (file)
index 0000000..d75738c
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/.sdkproject
@@ -0,0 +1,3 @@
+THIRPARTY=false
+PROCESSOR=microblaze_0
+MSS_FILE=system.mss

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/Makefile b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/Makefile
new file mode 100644 (file)
index 0000000..fe2a0ef
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/Makefile
@@ -0,0 +1,21 @@
+# Makefile generated by Xilinx SDK.
+
+-include libgen.options
+
+LIBRARIES = ${PROCESSOR}/lib/libxil.a
+MSS = system.mss
+
+all: libs
+       @echo 'Finished building libraries'
+
+libs: $(LIBRARIES)
+
+$(LIBRARIES): $(MSS)
+       libgen -hw ${HWSPEC}\
+              ${REPOSITORIES}\
+              -pe ${PROCESSOR} \
+              -log libgen.log \
+              $(MSS)
+
+clean:
+       rm -rf ${PROCESSOR}

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/libgen.options b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/libgen.options
new file mode 100644 (file)
index 0000000..e58297d
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/libgen.options
@@ -0,0 +1,3 @@
+PROCESSOR=microblaze_0
+REPOSITORIES=
+HWSPEC=../HardwareWithEthernetLite/system.xml

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/system.mss b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/system.mss
new file mode 100644 (file)
index 0000000..2369c83
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoBSP/system.mss
@@ -0,0 +1,81 @@
+\r
+ PARAMETER VERSION = 2.2.0\r
+\r
+\r
+BEGIN OS\r
+ PARAMETER OS_NAME = standalone\r
+ PARAMETER OS_VER = 3.01.a\r
+ PARAMETER PROC_INSTANCE = microblaze_0\r
+ PARAMETER STDIN = RS232_Uart_1\r
+ PARAMETER STDOUT = RS232_Uart_1\r
+END\r
+\r
+\r
+BEGIN PROCESSOR\r
+ PARAMETER DRIVER_NAME = cpu\r
+ PARAMETER DRIVER_VER = 1.13.a\r
+ PARAMETER HW_INSTANCE = microblaze_0\r
+END\r
+\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = emaclite\r
+ PARAMETER DRIVER_VER = 3.01.a\r
+ PARAMETER HW_INSTANCE = Ethernet_Lite\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = gpio\r
+ PARAMETER DRIVER_VER = 3.00.a\r
+ PARAMETER HW_INSTANCE = LEDs_4Bits\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = s6_ddrx\r
+ PARAMETER DRIVER_VER = 1.00.a\r
+ PARAMETER HW_INSTANCE = MCB_DDR3\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = gpio\r
+ PARAMETER DRIVER_VER = 3.00.a\r
+ PARAMETER HW_INSTANCE = Push_Buttons_4Bits\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = uartlite\r
+ PARAMETER DRIVER_VER = 2.00.a\r
+ PARAMETER HW_INSTANCE = RS232_Uart_1\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = tmrctr\r
+ PARAMETER DRIVER_VER = 2.03.a\r
+ PARAMETER HW_INSTANCE = axi_timer_0\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = uartlite\r
+ PARAMETER DRIVER_VER = 2.00.a\r
+ PARAMETER HW_INSTANCE = debug_module\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = bram\r
+ PARAMETER DRIVER_VER = 3.00.a\r
+ PARAMETER HW_INSTANCE = microblaze_0_d_bram_ctrl\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = bram\r
+ PARAMETER DRIVER_VER = 3.00.a\r
+ PARAMETER HW_INSTANCE = microblaze_0_i_bram_ctrl\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = intc\r
+ PARAMETER DRIVER_VER = 2.02.a\r
+ PARAMETER HW_INSTANCE = microblaze_0_intc\r
+END\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/.cproject b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/.cproject
new file mode 100644 (file)
index 0000000..f675335
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/.cproject
@@ -0,0 +1,1428 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 4.0.0?>\r
+\r
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
+       <storageModule moduleId="org.eclipse.cdt.core.settings">\r
+               <cconfiguration id="xilinx.gnu.mb.exe.debug.1890710697">\r
+                       <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.mb.exe.debug.1890710697" moduleId="org.eclipse.cdt.core.settings" name="Debug">\r
+                               <externalSettings/>\r
+                               <extensions>\r
+                                       <extension id="com.xilinx.sdk.managedbuilder.XELF.mb" point="org.eclipse.cdt.core.BinaryParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                               </extensions>\r
+                       </storageModule>\r
+                       <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+                               <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="xilinx.gnu.mb.exe.debug.1890710697" name="Debug" parent="xilinx.gnu.mb.exe.debug">\r
+                                       <folderInfo id="xilinx.gnu.mb.exe.debug.1890710697." name="/" resourcePath="">\r
+                                               <toolChain id="xilinx.gnu.mb.exe.debug.toolchain.599082172" name="Xilinx MicroBlaze GNU Toolchain" superClass="xilinx.gnu.mb.exe.debug.toolchain">\r
+                                                       <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.mb" id="xilinx.mb.target.gnu.base.debug.274213147" isAbstract="false" name="Debug Platform" superClass="xilinx.mb.target.gnu.base.debug"/>\r
+                                                       <builder buildPath="${workspace_loc:/RTOSDemoSource/Debug}" enableAutoBuild="true" id="xilinx.gnu.mb.toolchain.builder.debug.1579135972" managedBuildOn="true" name="GNU make.Debug" superClass="xilinx.gnu.mb.toolchain.builder.debug"/>\r
+                                                       <tool id="xilinx.gnu.mb.c.toolchain.assembler.debug.1239514963" name="MicroBlaze gcc assembler" superClass="xilinx.gnu.mb.c.toolchain.assembler.debug">\r
+                                                               <option id="xilinx.gnu.mb.assembler.usele.1396275909" superClass="xilinx.gnu.mb.assembler.usele" value="true" valueType="boolean"/>\r
+                                                               <inputType id="xilinx.gnu.assembler.input.637949814" superClass="xilinx.gnu.assembler.input"/>\r
+                                                       </tool>\r
+                                                       <tool id="xilinx.gnu.mb.c.toolchain.compiler.debug.1867440614" name="MicroBlaze gcc compiler" superClass="xilinx.gnu.mb.c.toolchain.compiler.debug">\r
+                                                               <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.337889984" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.compiler.option.debugging.level.617270473" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.mbversion.1451001122" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="8.10.a" valueType="string"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usele.160030529" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usebarrel.1216651937" superClass="xilinx.gnu.mb.compiler.inferred.usebarrel" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usepcmp.1517601997" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usediv.672884238" superClass="xilinx.gnu.mb.compiler.inferred.usediv" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.fpu.2006005452" superClass="xilinx.gnu.mb.compiler.inferred.fpu" value="xilinx.gnu.mb.compiler.inferred.fpu.basic" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.mul.678398498" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.compiler.inferred.swplatform.includes.560760309" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">\r
+                                                                       <listOptionValue builtIn="false" value="../../RTOSDemoBSP/microblaze_0/include"/>\r
+                                                               </option>\r
+                                                               <inputType id="xilinx.gnu.compiler.input.2107818916" name="C source files" superClass="xilinx.gnu.compiler.input"/>\r
+                                                       </tool>\r
+                                                       <tool id="xilinx.gnu.mb.cxx.toolchain.compiler.debug.892124153" name="MicroBlaze g++ compiler" superClass="xilinx.gnu.mb.cxx.toolchain.compiler.debug">\r
+                                                               <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.1589998383" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.compiler.option.debugging.level.128602658" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.mbversion.1802673391" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="8.10.a" valueType="string"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usele.1454232863" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usebarrel.1778832640" superClass="xilinx.gnu.mb.compiler.inferred.usebarrel" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usepcmp.435976827" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usediv.1414449733" superClass="xilinx.gnu.mb.compiler.inferred.usediv" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.fpu.1308489561" superClass="xilinx.gnu.mb.compiler.inferred.fpu" value="xilinx.gnu.mb.compiler.inferred.fpu.basic" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.mul.1215307028" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.compiler.inferred.swplatform.includes.1137996366" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">\r
+                                                                       <listOptionValue builtIn="false" value="../../RTOSDemoBSP/microblaze_0/include"/>\r
+                                                               </option>\r
+                                                       </tool>\r
+                                                       <tool id="xilinx.gnu.mb.toolchain.archiver.1592538942" name="MicroBlaze archiver" superClass="xilinx.gnu.mb.toolchain.archiver"/>\r
+                                                       <tool id="xilinx.gnu.mb.c.toolchain.linker.debug.944775154" name="MicroBlaze gcc linker" superClass="xilinx.gnu.mb.c.toolchain.linker.debug">\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.mbversion.1111013174" superClass="xilinx.gnu.mb.linker.inferred.mbversion" value="8.10.a" valueType="string"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usele.882904483" superClass="xilinx.gnu.mb.linker.inferred.usele" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usebarrel.595799628" superClass="xilinx.gnu.mb.linker.inferred.usebarrel" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usepcmp.1837572058" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usediv.1995633804" superClass="xilinx.gnu.mb.linker.inferred.usediv" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.fpu.1492907557" superClass="xilinx.gnu.mb.linker.inferred.fpu" value="xilinx.gnu.mb.linker.inferred.fpu.basic" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.mul.679446604" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1872729354" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">\r
+                                                                       <listOptionValue builtIn="false" value="../../RTOSDemoBSP/microblaze_0/lib"/>\r
+                                                               </option>\r
+                                                               <option id="xilinx.gnu.c.linker.option.lscript.2086162423" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>\r
+                                                               <inputType id="xilinx.gnu.linker.input.68952515" superClass="xilinx.gnu.linker.input">\r
+                                                                       <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>\r
+                                                                       <additionalInput kind="additionalinput" paths="$(LIBS)"/>\r
+                                                               </inputType>\r
+                                                               <inputType id="xilinx.gnu.linker.input.lscript.258084575" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>\r
+                                                       </tool>\r
+                                                       <tool id="xilinx.gnu.mb.cxx.toolchain.linker.debug.157885767" name="MicroBlaze g++ linker" superClass="xilinx.gnu.mb.cxx.toolchain.linker.debug">\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.mbversion.1177333884" superClass="xilinx.gnu.mb.linker.inferred.mbversion" value="8.10.a" valueType="string"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usele.1758849265" superClass="xilinx.gnu.mb.linker.inferred.usele" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usebarrel.876997851" superClass="xilinx.gnu.mb.linker.inferred.usebarrel" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usepcmp.1810668130" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usediv.507574974" superClass="xilinx.gnu.mb.linker.inferred.usediv" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.fpu.1213315596" superClass="xilinx.gnu.mb.linker.inferred.fpu" value="xilinx.gnu.mb.linker.inferred.fpu.basic" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.mul.36102197" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1705482080" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">\r
+                                                                       <listOptionValue builtIn="false" value="../../RTOSDemoBSP/microblaze_0/lib"/>\r
+                                                               </option>\r
+                                                               <option id="xilinx.gnu.c.linker.option.lscript.1465464686" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>\r
+                                                       </tool>\r
+                                                       <tool id="xilinx.gnu.mb.size.debug.1936094326" name="MicroBlaze Print Size" superClass="xilinx.gnu.mb.size.debug"/>\r
+                                                       <tool id="xilinx.elfcheck.mb.debug.2147351327" name="Xilinx ELF Check" superClass="xilinx.elfcheck.mb.debug">\r
+                                                               <option id="xilinx.elfcheck.option.hwspec.1155867438" superClass="xilinx.elfcheck.option.hwspec" value="-hw ../../HardwareWithEthernetLite/system.xml" valueType="string"/>\r
+                                                               <option id="xilinx.elfcheck.option.procname.2108096300" superClass="xilinx.elfcheck.option.procname" value="-pe microblaze_0" valueType="string"/>\r
+                                                       </tool>\r
+                                               </toolChain>\r
+                                       </folderInfo>\r
+                               </configuration>\r
+                       </storageModule>\r
+                       <storageModule moduleId="scannerConfiguration">\r
+                               <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
+                               <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="makefileGenerator">\r
+                                               <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.release.1186286811;xilinx.gnu.mb.exe.release.1186286811.">\r
+                                       <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="makefileGenerator">\r
+                                                       <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                               </scannerConfigBuildInfo>\r
+                               <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.debug.1890710697;xilinx.gnu.mb.exe.debug.1890710697.">\r
+                                       <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="makefileGenerator">\r
+                                                       <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                               </scannerConfigBuildInfo>\r
+                               <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.debug.1890710697;xilinx.gnu.mb.exe.debug.1890710697.;xilinx.gnu.mb.c.toolchain.compiler.debug.1867440614;xilinx.gnu.compiler.input.2107818916">\r
+                                       <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="makefileGenerator">\r
+                                                       <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                               </scannerConfigBuildInfo>\r
+                               <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.release.1186286811;xilinx.gnu.mb.exe.release.1186286811.;xilinx.gnu.mb.c.toolchain.compiler.release.1828722124;xilinx.gnu.compiler.input.690911521">\r
+                                       <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="makefileGenerator">\r
+                                                       <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                               </scannerConfigBuildInfo>\r
+                       </storageModule>\r
+                       <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+               </cconfiguration>\r
+               <cconfiguration id="xilinx.gnu.mb.exe.release.1186286811">\r
+                       <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.mb.exe.release.1186286811" moduleId="org.eclipse.cdt.core.settings" name="Release">\r
+                               <externalSettings/>\r
+                               <extensions>\r
+                                       <extension id="com.xilinx.sdk.managedbuilder.XELF.mb" point="org.eclipse.cdt.core.BinaryParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                               </extensions>\r
+                       </storageModule>\r
+                       <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+                               <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="xilinx.gnu.mb.exe.release.1186286811" name="Release" parent="xilinx.gnu.mb.exe.release">\r
+                                       <folderInfo id="xilinx.gnu.mb.exe.release.1186286811." name="/" resourcePath="">\r
+                                               <toolChain id="xilinx.gnu.mb.exe.release.toolchain.718912482" name="Xilinx MicroBlaze GNU Toolchain" superClass="xilinx.gnu.mb.exe.release.toolchain">\r
+                                                       <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.mb" id="xilinx.mb.target.gnu.base.release.1280250899" isAbstract="false" name="Debug Platform" superClass="xilinx.mb.target.gnu.base.release"/>\r
+                                                       <builder buildPath="${workspace_loc:/RTOSDemoSource/Release}" enableAutoBuild="true" id="xilinx.gnu.mb.toolchain.builder.release.432669831" managedBuildOn="true" name="GNU make.Release" superClass="xilinx.gnu.mb.toolchain.builder.release"/>\r
+                                                       <tool id="xilinx.gnu.mb.c.toolchain.assembler.release.2062618334" name="MicroBlaze gcc assembler" superClass="xilinx.gnu.mb.c.toolchain.assembler.release">\r
+                                                               <option id="xilinx.gnu.mb.assembler.usele.1004143246" superClass="xilinx.gnu.mb.assembler.usele" value="true" valueType="boolean"/>\r
+                                                               <inputType id="xilinx.gnu.assembler.input.1424192310" superClass="xilinx.gnu.assembler.input"/>\r
+                                                       </tool>\r
+                                                       <tool id="xilinx.gnu.mb.c.toolchain.compiler.release.1828722124" name="MicroBlaze gcc compiler" superClass="xilinx.gnu.mb.c.toolchain.compiler.release">\r
+                                                               <option defaultValue="gnu.c.optimization.level.most" id="xilinx.gnu.compiler.option.optimization.level.1238786955" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.compiler.option.debugging.level.949291389" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.none" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.mbversion.772757699" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="8.10.a" valueType="string"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usele.1473700868" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usebarrel.1861351915" superClass="xilinx.gnu.mb.compiler.inferred.usebarrel" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usepcmp.933103475" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usediv.1452006705" superClass="xilinx.gnu.mb.compiler.inferred.usediv" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.fpu.736763488" superClass="xilinx.gnu.mb.compiler.inferred.fpu" value="xilinx.gnu.mb.compiler.inferred.fpu.basic" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.mul.1393822003" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.compiler.inferred.swplatform.includes.306993152" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">\r
+                                                                       <listOptionValue builtIn="false" value="../../RTOSDemoBSP/microblaze_0/include"/>\r
+                                                               </option>\r
+                                                               <inputType id="xilinx.gnu.compiler.input.690911521" name="C source files" superClass="xilinx.gnu.compiler.input"/>\r
+                                                       </tool>\r
+                                                       <tool id="xilinx.gnu.mb.cxx.toolchain.compiler.release.449737219" name="MicroBlaze g++ compiler" superClass="xilinx.gnu.mb.cxx.toolchain.compiler.release">\r
+                                                               <option defaultValue="gnu.c.optimization.level.most" id="xilinx.gnu.compiler.option.optimization.level.719334230" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.compiler.option.debugging.level.888257007" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.none" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.mbversion.1974867876" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="8.10.a" valueType="string"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usele.1741794988" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usebarrel.1085726307" superClass="xilinx.gnu.mb.compiler.inferred.usebarrel" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usepcmp.183628355" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usediv.1022113972" superClass="xilinx.gnu.mb.compiler.inferred.usediv" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.fpu.1627263935" superClass="xilinx.gnu.mb.compiler.inferred.fpu" value="xilinx.gnu.mb.compiler.inferred.fpu.basic" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.mul.364150553" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.compiler.inferred.swplatform.includes.632505535" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">\r
+                                                                       <listOptionValue builtIn="false" value="../../RTOSDemoBSP/microblaze_0/include"/>\r
+                                                               </option>\r
+                                                       </tool>\r
+                                                       <tool id="xilinx.gnu.mb.toolchain.archiver.156208251" name="MicroBlaze archiver" superClass="xilinx.gnu.mb.toolchain.archiver"/>\r
+                                                       <tool id="xilinx.gnu.mb.c.toolchain.linker.release.1781075016" name="MicroBlaze gcc linker" superClass="xilinx.gnu.mb.c.toolchain.linker.release">\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.mbversion.881243134" superClass="xilinx.gnu.mb.linker.inferred.mbversion" value="8.10.a" valueType="string"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usele.1248988996" superClass="xilinx.gnu.mb.linker.inferred.usele" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usebarrel.354962392" superClass="xilinx.gnu.mb.linker.inferred.usebarrel" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usepcmp.1920529150" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usediv.943020691" superClass="xilinx.gnu.mb.linker.inferred.usediv" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.fpu.2040866770" superClass="xilinx.gnu.mb.linker.inferred.fpu" value="xilinx.gnu.mb.linker.inferred.fpu.basic" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.mul.378837391" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1279322127" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">\r
+                                                                       <listOptionValue builtIn="false" value="../../RTOSDemoBSP/microblaze_0/lib"/>\r
+                                                               </option>\r
+                                                               <option id="xilinx.gnu.c.linker.option.lscript.1907224502" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>\r
+                                                               <inputType id="xilinx.gnu.linker.input.134341694" superClass="xilinx.gnu.linker.input">\r
+                                                                       <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>\r
+                                                                       <additionalInput kind="additionalinput" paths="$(LIBS)"/>\r
+                                                               </inputType>\r
+                                                               <inputType id="xilinx.gnu.linker.input.lscript.1733021603" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>\r
+                                                       </tool>\r
+                                                       <tool id="xilinx.gnu.mb.cxx.toolchain.linker.release.98720932" name="MicroBlaze g++ linker" superClass="xilinx.gnu.mb.cxx.toolchain.linker.release">\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.mbversion.1241661489" superClass="xilinx.gnu.mb.linker.inferred.mbversion" value="8.10.a" valueType="string"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usele.1237060844" superClass="xilinx.gnu.mb.linker.inferred.usele" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usebarrel.1982200182" superClass="xilinx.gnu.mb.linker.inferred.usebarrel" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usepcmp.129183171" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.usediv.1333108220" superClass="xilinx.gnu.mb.linker.inferred.usediv" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.fpu.858346517" superClass="xilinx.gnu.mb.linker.inferred.fpu" value="xilinx.gnu.mb.linker.inferred.fpu.basic" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.mb.linker.inferred.mul.733062971" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1337156964" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">\r
+                                                                       <listOptionValue builtIn="false" value="../../RTOSDemoBSP/microblaze_0/lib"/>\r
+                                                               </option>\r
+                                                               <option id="xilinx.gnu.c.linker.option.lscript.793254984" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>\r
+                                                       </tool>\r
+                                                       <tool id="xilinx.gnu.mb.size.release.751554075" name="MicroBlaze Print Size" superClass="xilinx.gnu.mb.size.release"/>\r
+                                                       <tool id="xilinx.elfcheck.mb.release.941988759" name="Xilinx ELF Check" superClass="xilinx.elfcheck.mb.release">\r
+                                                               <option id="xilinx.elfcheck.option.hwspec.1947090803" superClass="xilinx.elfcheck.option.hwspec" value="-hw ../../HardwareWithEthernetLite/system.xml" valueType="string"/>\r
+                                                               <option id="xilinx.elfcheck.option.procname.1744481658" superClass="xilinx.elfcheck.option.procname" value="-pe microblaze_0" valueType="string"/>\r
+                                                       </tool>\r
+                                               </toolChain>\r
+                                       </folderInfo>\r
+                               </configuration>\r
+                       </storageModule>\r
+                       <storageModule moduleId="scannerConfiguration">\r
+                               <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
+                               <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="makefileGenerator">\r
+                                               <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
+                                       <buildOutputProvider>\r
+                                               <openAction enabled="true" filePath=""/>\r
+                                               <parser enabled="true"/>\r
+                                       </buildOutputProvider>\r
+                                       <scannerInfoProvider id="specsFile">\r
+                                               <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>\r
+                                               <parser enabled="true"/>\r
+                                       </scannerInfoProvider>\r
+                               </profile>\r
+                               <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.release.1186286811;xilinx.gnu.mb.exe.release.1186286811.">\r
+                                       <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="makefileGenerator">\r
+                                                       <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                               </scannerConfigBuildInfo>\r
+                               <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.debug.1890710697;xilinx.gnu.mb.exe.debug.1890710697.">\r
+                                       <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="makefileGenerator">\r
+                                                       <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                               </scannerConfigBuildInfo>\r
+                               <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.debug.1890710697;xilinx.gnu.mb.exe.debug.1890710697.;xilinx.gnu.mb.c.toolchain.compiler.debug.1867440614;xilinx.gnu.compiler.input.2107818916">\r
+                                       <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="makefileGenerator">\r
+                                                       <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                               </scannerConfigBuildInfo>\r
+                               <scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.release.1186286811;xilinx.gnu.mb.exe.release.1186286811.;xilinx.gnu.mb.c.toolchain.compiler.release.1828722124;xilinx.gnu.compiler.input.690911521">\r
+                                       <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="mb-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.PPCGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="powerpc-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-eabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="com.xilinx.managedbuilder.ui.ARMLinuxGCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-xilinxa9-linux-gnueabi-gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="makefileGenerator">\r
+                                                       <runAction arguments="-E -P -v -dD" command="" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                                       <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
+                                               <buildOutputProvider>\r
+                                                       <openAction enabled="true" filePath=""/>\r
+                                                       <parser enabled="true"/>\r
+                                               </buildOutputProvider>\r
+                                               <scannerInfoProvider id="specsFile">\r
+                                                       <runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>\r
+                                                       <parser enabled="true"/>\r
+                                               </scannerInfoProvider>\r
+                                       </profile>\r
+                               </scannerConfigBuildInfo>\r
+                       </storageModule>\r
+                       <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+               </cconfiguration>\r
+       </storageModule>\r
+       <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+               <project id="RTOSDemoSource.xilinx.gnu.mb.exe.1831715756" name="Xilinx MicroBlaze Executable" projectType="xilinx.gnu.mb.exe"/>\r
+       </storageModule>\r
+</cproject>\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/.project b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/.project
new file mode 100644 (file)
index 0000000..40ea646
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/.project
@@ -0,0 +1,82 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+       <name>RTOSDemoSource</name>\r
+       <comment>RTOSDemoBSP - microblaze_0</comment>\r
+       <projects>\r
+               <project>RTOSDemoBSP</project>\r
+       </projects>\r
+       <buildSpec>\r
+               <buildCommand>\r
+                       <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
+                       <arguments>\r
+                               <dictionary>\r
+                                       <key>?name?</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.append_environment</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.autoBuildTarget</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildArguments</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildCommand</key>\r
+                                       <value>make</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildLocation</key>\r
+                                       <value>${workspace_loc:/RTOSDemoSource/Debug}</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>\r
+                                       <value>clean</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.contents</key>\r
+                                       <value>org.eclipse.cdt.make.core.activeConfigSettings</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.fullBuildTarget</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                       </arguments>\r
+               </buildCommand>\r
+               <buildCommand>\r
+                       <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+                       <triggers>full,incremental,</triggers>\r
+                       <arguments>\r
+                       </arguments>\r
+               </buildCommand>\r
+       </buildSpec>\r
+       <natures>\r
+               <nature>org.eclipse.cdt.core.cnature</nature>\r
+               <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+               <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+       </natures>\r
+</projectDescription>\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/emaclite_header.h b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/emaclite_header.h
new file mode 100644 (file)
index 0000000..ca11dd5
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/emaclite_header.h
@@ -0,0 +1,56 @@
+#define TESTAPP_GEN
+\r
+/* $Id: emaclite_header.h,v 1.1.2.2 2010/09/16 12:57:34 svemula Exp $ */\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2003-2010 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+#ifndef EMACLITE_HEADER_H              /* prevent circular inclusions */\r
+#define EMACLITE_HEADER_H              /* by using protection macros */\r
+\r
+\r
+#include "xil_types.h"\r
+#include "xil_assert.h"\r
+#include "xstatus.h"\r
+\r
+int EmacLitePolledExample(u16 DeviceId);\r
+\r
+#endif\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/emaclite_intr_header.h b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/emaclite_intr_header.h
new file mode 100644 (file)
index 0000000..90ff393
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/emaclite_intr_header.h
@@ -0,0 +1,57 @@
+#define TESTAPP_GEN
+\r
+/* $Id: emaclite_intr_header.h,v 1.1.2.2 2010/09/16 12:57:34 svemula Exp $ */\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2003-2010 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+#ifndef EMACLITE_INTR_HEADER_H         /* prevent circular inclusions */\r
+#define EMACLITE_INTR_HEADER_H         /* by using protection macros */\r
+\r
+#include "xil_types.h"\r
+#include "xil_assert.h"\r
+#include "xstatus.h"\r
+\r
+int EmacLiteIntrExample(XIntc* IntcInstancePtr,\r
+                        XEmacLite* EmacLiteInstPtr,\r
+                        u16 EmacLiteDeviceId,\r
+                        u16 EmacLiteIntrId);\r
+\r
+#endif\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/gpio_header.h b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/gpio_header.h
new file mode 100644 (file)
index 0000000..2ff58ec
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/gpio_header.h
@@ -0,0 +1,56 @@
+#define TESTAPP_GEN
+\r
+/* $Id: gpio_header.h,v 1.1.2.2 2010/09/16 13:03:37 svemula Exp $ */\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2003-2010 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+#ifndef GPIO_HEADER_H          /* prevent circular inclusions */\r
+#define GPIO_HEADER_H          /* by using protection macros */\r
+\r
+#include "xil_types.h"\r
+#include "xil_assert.h"\r
+#include "xstatus.h"\r
+\r
+int GpioOutputExample(u16 DeviceId, u32 GpioWidth);\r
+int GpioInputExample(u16 DeviceId, u32 *DataRead);\r
+\r
+#endif\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/gpio_intr_header.h b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/gpio_intr_header.h
new file mode 100644 (file)
index 0000000..d7dbffe
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/gpio_intr_header.h
@@ -0,0 +1,62 @@
+#define TESTAPP_GEN
+\r
+/* $Id: gpio_intr_header.h,v 1.1.2.2 2010/09/16 13:03:37 svemula Exp $ */\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2005-2010 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+#ifndef GPIO_INTR_HEADER_H             /* prevent circular inclusions */\r
+#define GPIO_INTR_HEADER_H             /* by using protection macros */\r
+\r
+#include "xil_types.h"\r
+#include "xil_assert.h"\r
+#include "xstatus.h"\r
+\r
+\r
+int GpioIntrExample(XIntc* IntcInstancePtr,\r
+                        XGpio* InstancePtr,\r
+                        u16 DeviceId,\r
+                        u16 IntrId,\r
+                        u16 IntrMask,\r
+                        u32 *DataRead);\r
+\r
+\r
+#endif\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/intc_header.h b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/intc_header.h
new file mode 100644 (file)
index 0000000..eface14
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/intc_header.h
@@ -0,0 +1,55 @@
+#define TESTAPP_GEN
+\r
+/* $Id: intc_header.h,v 1.1.4.1 2010/09/17 05:32:46 svemula Exp $ */\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2006-2009 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+#ifndef INTC_HEADER_H          /* prevent circular inclusions */\r
+#define INTC_HEADER_H          /* by using protection macros */\r
+\r
+#include "xil_assert.h"\r
+#include "xil_types.h"\r
+#include "xstatus.h"\r
+\r
+int IntcSelfTestExample(u16 DeviceId);\r
+int IntcInterruptSetup(XIntc *IntcInstancePtr, u16 DeviceId);\r
+\r
+#endif\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/lscript.ld b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/lscript.ld
new file mode 100644 (file)
index 0000000..f70a4ba
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/lscript.ld
@@ -0,0 +1,213 @@
+/*******************************************************************/\r
+/*                                                                 */\r
+/* This file is automatically generated by linker script generator.*/\r
+/*                                                                 */\r
+/* Version: Xilinx EDK 13.1 EDK_O.40d                                */\r
+/*                                                                 */\r
+/* Copyright (c) 2010 Xilinx, Inc.  All rights reserved.           */\r
+/*                                                                 */\r
+/* Description : MicroBlaze Linker Script                          */\r
+/*                                                                 */\r
+/*******************************************************************/\r
+\r
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;\r
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;\r
+\r
+/* Define Memories in the system */\r
+\r
+MEMORY\r
+{\r
+   microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl : ORIGIN = 0x00000050, LENGTH = 0x00001FB0\r
+   MCB_DDR3_S0_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x08000000\r
+}\r
+\r
+/* Specify the default entry point to the program */\r
+\r
+ENTRY(_start)\r
+\r
+/* Define the sections, and where they are mapped in memory */\r
+\r
+SECTIONS\r
+{\r
+.vectors.reset 0x00000000 : {\r
+   *(.vectors.reset)\r
+} \r
+\r
+.vectors.sw_exception 0x00000008 : {\r
+   *(.vectors.sw_exception)\r
+} \r
+\r
+.vectors.interrupt 0x00000010 : {\r
+   *(.vectors.interrupt)\r
+} \r
+\r
+.vectors.hw_exception 0x00000020 : {\r
+   *(.vectors.hw_exception)\r
+} \r
+\r
+.text : {\r
+   *(.text)\r
+   *(.text.*)\r
+   *(.gnu.linkonce.t.*)\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.init : {\r
+   KEEP (*(.init))\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.fini : {\r
+   KEEP (*(.fini))\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.rodata : {\r
+   __rodata_start = .;\r
+   *(.rodata)\r
+   *(.rodata.*)\r
+   *(.gnu.linkonce.r.*)\r
+   __rodata_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.sdata2 : {\r
+   . = ALIGN(8);\r
+   __sdata2_start = .;\r
+   *(.sdata2)\r
+   *(.sdata2.*)\r
+   *(.gnu.linkonce.s2.*)\r
+   . = ALIGN(8);\r
+   __sdata2_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.sbss2 : {\r
+   __sbss2_start = .;\r
+   *(.sbss2)\r
+   *(.sbss2.*)\r
+   *(.gnu.linkonce.sb2.*)\r
+   __sbss2_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.data : {\r
+   . = ALIGN(4);\r
+   __data_start = .;\r
+   *(.data)\r
+   *(.data.*)\r
+   *(.gnu.linkonce.d.*)\r
+   __data_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.got : {\r
+   *(.got)\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.got1 : {\r
+   *(.got1)\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.got2 : {\r
+   *(.got2)\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.ctors : {\r
+   __CTOR_LIST__ = .;\r
+   ___CTORS_LIST___ = .;\r
+   KEEP (*crtbegin.o(.ctors))\r
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))\r
+   KEEP (*(SORT(.ctors.*)))\r
+   KEEP (*(.ctors))\r
+   __CTOR_END__ = .;\r
+   ___CTORS_END___ = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.dtors : {\r
+   __DTOR_LIST__ = .;\r
+   ___DTORS_LIST___ = .;\r
+   KEEP (*crtbegin.o(.dtors))\r
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))\r
+   KEEP (*(SORT(.dtors.*)))\r
+   KEEP (*(.dtors))\r
+   __DTOR_END__ = .;\r
+   ___DTORS_END___ = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.eh_frame : {\r
+   *(.eh_frame)\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.jcr : {\r
+   *(.jcr)\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.gcc_except_table : {\r
+   *(.gcc_except_table)\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.sdata : {\r
+   . = ALIGN(8);\r
+   __sdata_start = .;\r
+   *(.sdata)\r
+   *(.sdata.*)\r
+   *(.gnu.linkonce.s.*)\r
+   __sdata_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.sbss : {\r
+   . = ALIGN(4);\r
+   __sbss_start = .;\r
+   *(.sbss)\r
+   *(.sbss.*)\r
+   *(.gnu.linkonce.sb.*)\r
+   . = ALIGN(8);\r
+   __sbss_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.tdata : {\r
+   __tdata_start = .;\r
+   *(.tdata)\r
+   *(.tdata.*)\r
+   *(.gnu.linkonce.td.*)\r
+   __tdata_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.tbss : {\r
+   __tbss_start = .;\r
+   *(.tbss)\r
+   *(.tbss.*)\r
+   *(.gnu.linkonce.tb.*)\r
+   __tbss_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.bss : {\r
+   . = ALIGN(4);\r
+   __bss_start = .;\r
+   *(.bss)\r
+   *(.bss.*)\r
+   *(.gnu.linkonce.b.*)\r
+   *(COMMON)\r
+   . = ALIGN(4);\r
+   __bss_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );\r
+\r
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );\r
+\r
+/* Generate Stack and Heap definitions */\r
+\r
+.heap : {\r
+   . = ALIGN(8);\r
+   _heap = .;\r
+   _heap_start = .;\r
+   . += _HEAP_SIZE;\r
+   _heap_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.stack : {\r
+   _stack_end = .;\r
+   . += _STACK_SIZE;\r
+   . = ALIGN(8);\r
+   _stack = .;\r
+   __stack = _stack;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+_end = .;\r
+}\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/testperiph.c b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/testperiph.c
new file mode 100644 (file)
index 0000000..21b4e95
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/testperiph.c
@@ -0,0 +1,246 @@
+/*
+ *
+ * Xilinx, Inc.
+ * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A 
+ * COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+ * ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR 
+ * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION 
+ * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE 
+ * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION
+ * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO 
+ * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO 
+ * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 
+ * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY 
+ * AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/*
+ * 
+ *
+ * This file is a generated sample test application.
+ *
+ * This application is intended to test and/or illustrate some 
+ * functionality of your system.  The contents of this file may
+ * vary depending on the IP in your system and may use existing
+ * IP driver functions.  These drivers will be generated in your
+ * SDK application project when you run the "Generate Libraries" menu item.
+ *
+ */
+
+\r
+#include <stdio.h>
+#include "xparameters.h"
+#include "xenv_standalone.h"
+#include "xintc.h"
+#include "intc_header.h"
+#include "xbasic_types.h"
+#include "xgpio.h"
+#include "gpio_header.h"
+#include "xbasic_types.h"
+#include "xgpio.h"
+#include "gpio_header.h"
+#include "gpio_intr_header.h"
+#include "uartlite_header.h"
+#include "xtmrctr.h"
+#include "tmrctr_header.h"
+#include "tmrctr_intr_header.h"
+#include "xemaclite.h"
+#include "xemaclite_example.h"
+#include "emaclite_header.h"
+#include "emaclite_intr_header.h"
+\r
+
+#define GPIO_CHANNEL1 1
+\r
+int main() 
+{
+\r
+   static XIntc intc;
+   static XGpio Push_Buttons_4Bits_Gpio;
+   static XTmrCtr axi_timer_0_Timer;
+   static XEmacLite Ethernet_Lite_EmacLite;
+\r
+   XCACHE_ENABLE_ICACHE();
+   XCACHE_ENABLE_DCACHE();
+\r
+   print("---Entering main---\n\r");
+\r
+   
+
+   {
+      int status;
+      
+      print("\r\n Running IntcSelfTestExample() for microblaze_0_intc...\r\n");
+      
+      status = IntcSelfTestExample(XPAR_MICROBLAZE_0_INTC_DEVICE_ID);
+      
+      if (status == 0) {
+         print("IntcSelfTestExample PASSED\r\n");
+      }
+      else {
+         print("IntcSelfTestExample FAILED\r\n");
+      }
+   } 
+       
+   {
+       int Status;
+
+       Status = IntcInterruptSetup(&intc, XPAR_MICROBLAZE_0_INTC_DEVICE_ID);
+       if (Status == 0) {
+          print("Intc Interrupt Setup PASSED\r\n");
+       } 
+       else {
+         print("Intc Interrupt Setup FAILED\r\n");
+      } 
+   }
+   
+
+   {
+      u32 status;
+      
+      print("\r\nRunning GpioOutputExample() for LEDs_4Bits...\r\n");
+
+      status = GpioOutputExample(XPAR_LEDS_4BITS_DEVICE_ID,4);
+      
+      if (status == 0) {
+         print("GpioOutputExample PASSED.\r\n");
+      }
+      else {
+         print("GpioOutputExample FAILED.\r\n");
+      }
+   }
+   
+
+   {
+      u32 status;
+      
+      print("\r\nRunning GpioInputExample() for Push_Buttons_4Bits...\r\n");
+
+      u32 DataRead;
+      
+      status = GpioInputExample(XPAR_PUSH_BUTTONS_4BITS_DEVICE_ID, &DataRead);
+      
+      if (status == 0) {
+         xil_printf("GpioInputExample PASSED. Read data:0x%X\r\n", DataRead);
+      }
+      else {
+         print("GpioInputExample FAILED.\r\n");
+      }
+   }
+   {
+      
+      int Status;
+        
+      u32 DataRead;
+      
+      print(" Press button to Generate Interrupt\r\n");
+      
+      Status = GpioIntrExample(&intc, &Push_Buttons_4Bits_Gpio, \
+                               XPAR_PUSH_BUTTONS_4BITS_DEVICE_ID, \
+                               XPAR_MICROBLAZE_0_INTC_PUSH_BUTTONS_4BITS_IP2INTC_IRPT_INTR, \
+                               GPIO_CHANNEL1, &DataRead);
+       
+      if (Status == 0 ){
+             if(DataRead == 0)
+                print("No button pressed. \r\n");
+             else
+                print("Gpio Interrupt Test PASSED. \r\n"); 
+      } 
+      else {
+         print("Gpio Interrupt Test FAILED.\r\n");
+      }
+       
+   }
+   
+   /*
+    * Peripheral SelfTest will not be run for RS232_Uart_1
+    * because it has been selected as the STDOUT device
+    */
+
+   
+
+   {
+      int status;
+      
+      print("\r\nRunning UartLiteSelfTestExample() for debug_module...\r\n");
+      status = UartLiteSelfTestExample(XPAR_DEBUG_MODULE_DEVICE_ID);
+      if (status == 0) {
+         print("UartLiteSelfTestExample PASSED\r\n");
+      }
+      else {
+         print("UartLiteSelfTestExample FAILED\r\n");
+      }
+   }
+   
+
+   {
+      int status;
+      
+      print("\r\n Running TmrCtrSelfTestExample() for axi_timer_0...\r\n");
+      
+      status = TmrCtrSelfTestExample(XPAR_AXI_TIMER_0_DEVICE_ID, 0x0);
+      
+      if (status == 0) {
+         print("TmrCtrSelfTestExample PASSED\r\n");
+      }
+      else {
+         print("TmrCtrSelfTestExample FAILED\r\n");
+      }
+   }
+   {
+      int Status;
+
+      print("\r\n Running Interrupt Test  for axi_timer_0...\r\n");
+      
+      Status = TmrCtrIntrExample(&intc, &axi_timer_0_Timer, \
+                                 XPAR_AXI_TIMER_0_DEVICE_ID, \
+                                 XPAR_MICROBLAZE_0_INTC_AXI_TIMER_0_INTERRUPT_INTR, 0);
+       
+      if (Status == 0) {
+         print("Timer Interrupt Test PASSED\r\n");
+      } 
+      else {
+         print("Timer Interrupt Test FAILED\r\n");
+      }
+
+   }
+   
+
+   {
+      int status;
+      
+      print("\r\nRunning EmacLitePolledExample() for Ethernet_Lite...\r\n");
+      status = EmacLitePolledExample(XPAR_ETHERNET_LITE_DEVICE_ID);
+      if (status == 0) {
+         print("EmacLite Polled Example PASSED\r\n");
+      }
+      else {
+         print("EmacLite Polled Example FAILED\r\n");
+      }
+   }
+   {
+      int Status;
+
+      print("\r\n Running Interrupt Test  for Ethernet_Lite...\r\n");
+      
+      Status = EmacLiteIntrExample(&intc, &Ethernet_Lite_EmacLite, \
+                               XPAR_ETHERNET_LITE_DEVICE_ID, \
+                               XPAR_MICROBLAZE_0_INTC_ETHERNET_LITE_IP2INTC_IRPT_INTR);
+       
+      if (Status == 0) {
+         print("EmacLite Interrupt Test PASSED\r\n");
+      } 
+      else {
+         print("EmacLite Interrupt Test FAILED\r\n");
+      }
+
+   }
+\r
+   print("---Exiting main---\n\r");
+\r
+   XCACHE_DISABLE_ICACHE();
+   XCACHE_DISABLE_DCACHE();
+\r
+   return 0;
+}
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/tmrctr_header.h b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/tmrctr_header.h
new file mode 100644 (file)
index 0000000..f8c5f5f
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/tmrctr_header.h
@@ -0,0 +1,55 @@
+#define TESTAPP_GEN
+\r
+/* $Id: tmrctr_header.h,v 1.1.2.1 2010/12/01 07:53:56 svemula Exp $ */\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2005-2010 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+#ifndef TMRCTR_HEADER_H                /* prevent circular inclusions */\r
+#define TMRCTR_HEADER_H                /* by using protection macros */\r
+\r
+#include "xil_types.h"\r
+#include "xil_assert.h"\r
+#include "xstatus.h"\r
+\r
+int TmrCtrSelfTestExample(u16 DeviceId, u8 TmrCtrNumber);\r
+\r
+#endif\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/tmrctr_intr_header.h b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/tmrctr_intr_header.h
new file mode 100644 (file)
index 0000000..8beef56
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/tmrctr_intr_header.h
@@ -0,0 +1,60 @@
+#define TESTAPP_GEN
+\r
+/* $Id: tmrctr_intr_header.h,v 1.1.2.1 2010/12/01 07:53:56 svemula Exp $ */\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2005-2010 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+#ifndef TMRCTR_INTR_HEADER_H           /* prevent circular inclusions */\r
+#define TMRCTR_INTR_HEADER_H           /* by using protection macros */\r
+\r
+#include "xil_types.h"\r
+#include "xil_assert.h"\r
+#include "xstatus.h"\r
+\r
+\r
+int TmrCtrIntrExample(XIntc* IntcInstancePtr,\r
+                          XTmrCtr* InstancePtr,\r
+                          u16 DeviceId,\r
+                          u16 IntrId,\r
+                          u8 TmrCtrNumber);\r
+\r
+#endif\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/uartlite_header.h b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/uartlite_header.h
new file mode 100644 (file)
index 0000000..422602e
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/uartlite_header.h
@@ -0,0 +1,55 @@
+#define TESTAPP_GEN
+\r
+/* $Id: uartlite_header.h,v 1.1.2.2 2010/09/16 12:12:57 svemula Exp $ */\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+#ifndef UARTLITE_HEADER_H              /* prevent circular inclusions */\r
+#define UARTLITE_HEADER_H              /* by using protection macros */\r
+\r
+#include "xil_types.h"\r
+#include "xil_assert.h"\r
+#include "xstatus.h"\r
+\r
+int UartLiteSelfTestExample(u16 DeviceId);\r
+\r
+#endif\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xemaclite_example.h b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xemaclite_example.h
new file mode 100644 (file)
index 0000000..8326c34
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xemaclite_example.h
@@ -0,0 +1,135 @@
+#define TESTAPP_GEN
+\r
+/* $Id: xemaclite_example.h,v 1.1.2.1 2010/07/12 08:34:24 svemula Exp $\r
+*/\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+/*****************************************************************************/\r
+/**\r
+*\r
+* @file xemaclite_example.h\r
+*\r
+* Defines common data types, prototypes, and includes the proper headers\r
+* for use with the EmacLite example code residing in this directory.\r
+*\r
+* This file along with xemaclite_example_util.c are utilized with the specific\r
+* example code in the other source code files provided.\r
+*\r
+* These examples are designed to be compiled and utilized within the EDK\r
+* standalone BSP development environment. The readme file contains more\r
+* information on build requirements needed by these examples.\r
+*\r
+* <pre>\r
+* MODIFICATION HISTORY:\r
+*\r
+* Ver   Who  Date     Changes\r
+* ----- ---- -------- -------------------------------------------------------\r
+* 2.00a ktn  04/13/09 First release\r
+* </pre>\r
+*\r
+******************************************************************************/\r
+#ifndef XEMACLITE_EXAMPLE_H\r
+#define XEMACLITE_EXAMPLE_H\r
+\r
+/***************************** Include Files *********************************/\r
+\r
+#include "xparameters.h"\r
+#include "xemaclite.h"\r
+\r
+/************************** Constant Definitions ****************************/\r
+\r
+#define PHY_REG0_OFFSET                0 /* Register 0 of PHY device */\r
+#define PHY_REG1_OFFSET        1 /* Register 1 of PHY device */\r
+\r
+#define PHY_REG0_RESET_MASK    0x8000  /* Reset Phy device */\r
+#define PHY_REG0_LOOPBACK_MASK 0x4000  /* Loopback Enable in Phy */\r
+#define PHY_REG0_SPD_100_MASK  0x2000  /* Speed of 100Mbps for Phy */\r
+\r
+#define PHY_REG1_DETECT_MASK   0x1808  /* Mask to detect PHY device */\r
+\r
+#define EMACLITE_PHY_DELAY_SEC 4       /* Amount of time to delay waiting on\r
+                                        * PHY to reset.\r
+                                        */\r
+\r
+/*\r
+ * The following constants map to the XPAR parameters created in the\r
+ * xparameters.h file. They are defined here such that a user can easily\r
+ * change all the needed parameters in one place.\r
+ */\r
+#define EMAC_DEVICE_ID         XPAR_EMACLITE_0_DEVICE_ID\r
+\r
+/***************** Macros (Inline Functions) Definitions *********************/\r
+\r
+/**************************** Type Definitions ******************************/\r
+\r
+/************************** Function Prototypes *****************************/\r
+\r
+/*\r
+ * Utility functions implemented in xemaclite_example_util.c\r
+ */\r
+void EmacLitePhyDelay(unsigned int Seconds);\r
+u32 EmacLitePhyDetect(XEmacLite *InstancePtr);\r
+int EmacLiteEnablePhyLoopBack(XEmacLite *InstancePtr, u32 PhyAddress);\r
+int EmacLiteDisablePhyLoopBack(XEmacLite *InstancePtr, u32 PhyAddress);\r
+\r
+/************************** Variable Definitions ****************************/\r
+/*\r
+ * Set up valid local MAC addresses. This loop back test uses the LocalAddress\r
+ * both as a source and destination MAC address.\r
+ */\r
+\r
+XEmacLite EmacLiteInstance;    /* Instance of the EmacLite */\r
+\r
+/*\r
+ * Buffers used for Transmission and Reception of Packets. These are declared\r
+ * as global so that they are not a part of the stack.\r
+ */\r
+u8 TxFrame[XEL_MAX_FRAME_SIZE];\r
+u8 RxFrame[XEL_MAX_FRAME_SIZE];\r
+\r
+volatile u32 RecvFrameLength;  /* Indicates the length of the Received packet\r
+                                */\r
+volatile int TransmitComplete; /* Flag to indicate that the Transmission\r
+                                * is complete\r
+                                */\r
+#endif /* XTEMAC_EXAMPLE_H */\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xemaclite_example_util.c b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xemaclite_example_util.c
new file mode 100644 (file)
index 0000000..c85d7ef
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xemaclite_example_util.c
@@ -0,0 +1,265 @@
+#define TESTAPP_GEN
+\r
+/* $Id: xemaclite_example_util.c,v 1.1.2.1 2010/07/12 08:34:25 svemula Exp $ */\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+/*****************************************************************************/\r
+/**\r
+*\r
+* @file xemaclite_example_util.c\r
+*\r
+* This file implements the utility functions for the EmacLite example code.\r
+*\r
+* <pre>\r
+* MODIFICATION HISTORY:\r
+*\r
+* Ver   Who  Date     Changes\r
+* ----- ---- -------- -------------------------------------------------------\r
+* 2.00a  ktn 04/13/09 First release\r
+* 2.00a  ktn 06/13/09 Changed the EmacLitePhyDetect function so that\r
+*                    the function is not in an infinite loop in case of a\r
+*                    faulty Phy device.\r
+* </pre>\r
+*\r
+******************************************************************************/\r
+\r
+/***************************** Include Files *********************************/\r
+\r
+#include "xemaclite_example.h"\r
+#include "stdio.h"\r
+\r
+/************************** Variable Definitions ****************************/\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* This function detects the PHY address by looking for successful MII status\r
+* register contents (PHY register 1). It looks for a PHY that supports\r
+* auto-negotiation and 10Mbps full-duplex and half-duplex. So, this code\r
+* won't work for PHYs that don't support those features, but it's a bit more\r
+* general purpose than matching a specific PHY manufacturer ID.\r
+*\r
+* Note also that on some (older) Xilinx ML4xx boards, PHY address 0 does not\r
+* properly respond to this query. But, since the default is 0 and assuming\r
+* no other address responds, then it seems to work OK.\r
+*\r
+* @param       InstancePtr is the pointer to the instance of EmacLite driver.\r
+*\r
+* @return      The address of the PHY device detected (returns 0 if not\r
+*              detected).\r
+*\r
+* @note\r
+*              The bit mask (0x1808) of the MII status register\r
+*              (PHY Register 1) used in this function are:\r
+*              0x1000: 10Mbps full duplex support.\r
+*              0x0800: 10Mbps half duplex support.\r
+*              0x0008: Auto-negotiation support.\r
+*\r
+******************************************************************************/\r
+u32 EmacLitePhyDetect(XEmacLite *InstancePtr)\r
+{\r
+       u16 PhyData;\r
+       int PhyAddr;\r
+\r
+       /*\r
+        * Verify all 32 MDIO ports.\r
+        */\r
+       for (PhyAddr = 31; PhyAddr >= 0; PhyAddr--) {\r
+               XEmacLite_PhyRead(InstancePtr, PhyAddr, PHY_REG1_OFFSET,\r
+                                &PhyData);\r
+\r
+               if (PhyData != 0xFFFF) {\r
+                       if ((PhyData & PHY_REG1_DETECT_MASK) ==\r
+                       PHY_REG1_DETECT_MASK) {\r
+                               return PhyAddr; /* Found a valid PHY device */\r
+                       }\r
+               }\r
+       }\r
+       /*\r
+        * Unable to detect PHY device returning the default address of 0.\r
+        */\r
+       return 0;\r
+}\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* This function enables the MAC loopback on the PHY.\r
+*\r
+* @param       InstancePtr is the pointer to the instance of EmacLite driver.\r
+* @param       PhyAddress is the address of the Phy device.\r
+*\r
+* @return\r
+*              - XST_SUCCESS if the loop back is enabled.\r
+*              - XST_FAILURE if the loop back was not enabled.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+int EmacLiteEnablePhyLoopBack(XEmacLite *InstancePtr, u32 PhyAddress)\r
+{\r
+       int Status;\r
+       u16 PhyData = 0;\r
+\r
+       /*\r
+        * Set the speed and put the PHY in reset.\r
+        */\r
+       PhyData |= PHY_REG0_SPD_100_MASK;\r
+       Status = XEmacLite_PhyWrite(InstancePtr, PhyAddress, PHY_REG0_OFFSET,\r
+                       PhyData | PHY_REG0_RESET_MASK);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       /*\r
+        * Give sufficient delay for Phy Reset.\r
+        */\r
+       EmacLitePhyDelay(EMACLITE_PHY_DELAY_SEC);\r
+\r
+       /*\r
+        * Set the PHY in loop back.\r
+        */\r
+       XEmacLite_PhyWrite(InstancePtr, PhyAddress, PHY_REG0_OFFSET,\r
+                       PhyData | PHY_REG0_LOOPBACK_MASK);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       /*\r
+        * Give sufficient delay for Phy Loopback Enable.\r
+        */\r
+       EmacLitePhyDelay(1);\r
+\r
+       return XST_SUCCESS;\r
+}\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* This function disables the MAC loopback on the PHY.\r
+*\r
+* @param       InstancePtr is the pointer to the instance of EmacLite driver.\r
+* @param       PhyAddress is the address of the Phy device.\r
+*\r
+* @return\r
+*              - XST_SUCCESS if the loop back was disabled.\r
+*              - XST_FAILURE if the loop back was not disabled.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+int EmacLiteDisablePhyLoopBack(XEmacLite *InstancePtr, u32 PhyAddress)\r
+{\r
+       int Status;\r
+       u16 PhyData;\r
+\r
+       /*\r
+        * Disable loop back through PHY register using MDIO support.\r
+        */\r
+       Status = XEmacLite_PhyRead(InstancePtr, PhyAddress, PHY_REG0_OFFSET,\r
+                                       &PhyData);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       Status = XEmacLite_PhyWrite(InstancePtr,PhyAddress, PHY_REG0_OFFSET,\r
+                                       PhyData & ~(PHY_REG0_LOOPBACK_MASK));\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+\r
+}\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* For PPC we use a usleep call, for Microblaze we use an assembly loop that\r
+* is roughly the same regardless of optimization level, although caches and\r
+* memory access time can make the delay vary.  Just keep in mind that after\r
+* resetting or updating the PHY modes, the PHY typically needs time to recover.\r
+*\r
+* @return   None\r
+*\r
+* @note     None\r
+*\r
+******************************************************************************/\r
+void EmacLitePhyDelay(unsigned int Seconds)\r
+{\r
+#ifdef __MICROBLAZE__\r
+       static int WarningFlag = 0;\r
+\r
+       /* If MB caches are disabled or do not exist, this delay loop could\r
+        * take minutes instead of seconds (e.g., 30x longer).  Print a warning\r
+        * message for the user (once).  If only MB had a built-in timer!\r
+        */\r
+       if (((mfmsr() & 0x20) == 0) && (!WarningFlag)) {\r
+#ifdef STDOUT_BASEADDRESS\r
+               xil_printf("Warning: This example will take ");\r
+               xil_printf("minutes to complete without I-cache enabled \r\n");\r
+#endif\r
+               WarningFlag = 1;\r
+       }\r
+\r
+#define ITERS_PER_SEC   (XPAR_CPU_CORE_CLOCK_FREQ_HZ / 6)\r
+    asm volatile ("\n"\r
+                  "1:               \n\t"\r
+                  "addik r7, r0, %0 \n\t"\r
+                  "2:               \n\t"\r
+                  "addik r7, r7, -1 \n\t"\r
+                  "bneid  r7, 2b    \n\t"\r
+                  "or  r0, r0, r0   \n\t"\r
+                  "bneid %1, 1b     \n\t"\r
+                  "addik %1, %1, -1 \n\t"\r
+                  :: "i"(ITERS_PER_SEC), "d" (Seconds));\r
+\r
+#else\r
+\r
+       usleep(Seconds * 1000000);\r
+\r
+#endif\r
+}\r
+\r
+\r
+\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xemaclite_intr_example.c b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xemaclite_intr_example.c
new file mode 100644 (file)
index 0000000..faa6420
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xemaclite_intr_example.c
@@ -0,0 +1,684 @@
+#define TESTAPP_GEN
+\r
+/* $Id: xemaclite_intr_example.c,v 1.1.2.2 2010/08/06 15:11:04 anirudh Exp $\r
+*/\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2003-2010 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+2* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+/*****************************************************************************/\r
+/**\r
+* @file xemaclite_intr_example.c\r
+*\r
+* This file contains an example for using the EmacLite hardware and driver.\r
+* This file contains an interrupt example outlining the use of interrupts and\r
+* callbacks in the transmission/reception of an Ethernet frame of 1000 bytes of\r
+* payload.\r
+*\r
+* If the MDIO interface is NOT configured in the EmacLite core then this example\r
+* will transmit a frame.\r
+* If the MDIO interface is configured in the EmacLite core then this example\r
+* will enable the MAC loopback in the PHY device, then transmit the frame and\r
+* compare the received frame.\r
+*\r
+* @note\r
+*\r
+* None\r
+*\r
+* <pre>\r
+* MODIFICATION HISTORY:\r
+*\r
+* Ver   Who  Date     Changes\r
+* ----- ---- -------- -----------------------------------------------\r
+* 1.01a ecm  05/21/04 First release\r
+* 1.01a sv   06/06/05 Minor changes to comply to Doxygen and coding guidelines\r
+* 1.01a sv   06/06/06 Minor changes for supporting Test App Interrupt examples\r
+* 2.00a ktn  02/25/09 Updated to use PHY loop back if MDIO is configured in\r
+*                    core\r
+* 3.00a ktn  10/22/09 Updated the example to use the HAL APIs/macros.\r
+*                    Updated example to use the macros that have been changed\r
+*                    in the driver to remove _m from the name of the macro.\r
+* 3.01a ktn  07/08/10 Updated example to support Little Endian MicroBlaze.\r
+*\r
+* </pre>\r
+*\r
+******************************************************************************/\r
+\r
+/***************************** Include Files *********************************/\r
+\r
+#include "xemaclite_example.h"\r
+#include "xintc.h"\r
+#include "xil_exception.h"\r
+#include "xil_io.h"\r
+\r
+/************************** Constant Definitions *****************************/\r
+\r
+#ifndef TESTAPP_GEN\r
+/*\r
+ * The following constants map to the XPAR parameters created in the\r
+ * xparameters.h file. They are defined here such that a user can easily\r
+ * change all the needed parameters in one place.\r
+ */\r
+#define INTC_DEVICE_ID         XPAR_INTC_0_DEVICE_ID\r
+#define INTC_EMACLITE_ID       XPAR_INTC_0_EMACLITE_0_VEC_ID\r
+#endif\r
+\r
+/*\r
+ * The Size of the Test Frame.\r
+ */\r
+#define EMACLITE_TEST_FRAME_SIZE       1000\r
+\r
+/**************************** Type Definitions *******************************/\r
+\r
+/***************** Macros (Inline Functions) Definitions *********************/\r
+\r
+/************************** Function Prototypes ******************************/\r
+\r
+int EmacLiteIntrExample(XIntc *IntcInstancePtr,\r
+                       XEmacLite *EmacLiteInstPtr,\r
+                       u16 EmacLiteDeviceId,\r
+                       u16 EmacLiteIntrId);\r
+\r
+static int EmacLiteSendFrame(XEmacLite *EmacLiteInstPtr,\r
+                                        u32 PayloadSize);\r
+static int EmacLiteRecvFrame(u32 PayloadSize);\r
+static void EmacLiteRecvHandler(void *CallBackRef);\r
+static void EmacLiteSendHandler(void *CallBackRef);\r
+static void EmacLiteDisableIntrSystem(XIntc *IntcInstancePtr,\r
+                                                u16 EmacLiteIntrId);\r
+static int EmacLiteSetupIntrSystem(XIntc *IntcInstancePtr,\r
+                        XEmacLite *EmacLiteInstPtr, u16 EmacLiteIntrId);\r
+\r
+/************************** Variable Definitions *****************************/\r
+\r
+XIntc IntcInstance;            /* Instance of the Interrupt Controller */\r
+\r
+/*\r
+ * Set up valid local and remote MAC addresses. This loop back test uses the\r
+ * LocalAddress both as a source and destination MAC address.\r
+ */\r
+static u8 RemoteAddress[XEL_MAC_ADDR_SIZE] =\r
+{\r
+       0x00, 0x10, 0xa4, 0xb6, 0xfd, 0x09\r
+};\r
+static u8 LocalAddress[XEL_MAC_ADDR_SIZE] =\r
+{\r
+       0x00, 0x0A, 0x35, 0x01, 0x02, 0x03\r
+};\r
+\r
+/****************************************************************************/\r
+/**\r
+*\r
+* This function is the main function of the EmacLite interrupt example.\r
+*\r
+* @param       None.\r
+*\r
+* @return      XST_SUCCESS if successful, otherwise XST_FAILURE.\r
+*\r
+* @note                None.\r
+*\r
+*****************************************************************************/\r
+#ifndef TESTAPP_GEN\r
+int main()\r
+{\r
+       int Status;\r
+\r
+       /*\r
+        * Run the EmacLite interrupt example , specify the parameters\r
+        * generated in xparameters.h.\r
+        */\r
+       Status = EmacLiteIntrExample(&IntcInstance,\r
+                                &EmacLiteInstance,\r
+                                EMAC_DEVICE_ID,\r
+                                INTC_EMACLITE_ID);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+\r
+}\r
+#endif\r
+\r
+/*****************************************************************************/\r
+/**\r
+*\r
+* The main entry point for the EmacLite driver example in interrupt mode.\r
+\r
+* This function will transmit/receive the Ethernet frames and verify the\r
+* data in the received frame (if the MDIO interface is configured in the\r
+* EmacLite core).\r
+* This function simply transmits a frame if the MDIO interface is not\r
+* configured in the EmacLite core.\r
+*\r
+* @param       IntcInstancePtr is a pointer to the instance of the Intc.\r
+* @param       EmacLiteInstPtr is a pointer to the instance of the EmacLite.\r
+* @param       EmacLiteDeviceId is device ID of the XEmacLite Device ,\r
+*              typically XPAR_<EMACLITE_instance>_DEVICE_ID value from\r
+*              xparameters.h.\r
+* @param       EmacLiteIntrId is the interrupt ID and is typically\r
+*              XPAR_<INTC_instance>_<EMACLITE_instance>_VEC_ID value from\r
+*              xparameters.h.\r
+*\r
+* @return      XST_SUCCESS if successful, otherwise XST_FAILURE.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+int EmacLiteIntrExample(XIntc *IntcInstancePtr,\r
+                       XEmacLite *EmacLiteInstPtr,\r
+                       u16 EmacLiteDeviceId,\r
+                       u16 EmacLiteIntrId)\r
+{\r
+       int Status;\r
+       u32 PhyAddress = 0;\r
+       XEmacLite_Config *ConfigPtr;\r
+\r
+       /*\r
+        * Initialize the EmacLite device.\r
+        */\r
+       ConfigPtr = XEmacLite_LookupConfig(EmacLiteDeviceId);\r
+       if (ConfigPtr == NULL) {\r
+               return XST_FAILURE;\r
+       }\r
+       Status = XEmacLite_CfgInitialize(EmacLiteInstPtr,\r
+                                       ConfigPtr,\r
+                                       ConfigPtr->BaseAddress);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       /*\r
+        * Set the MAC address.\r
+        */\r
+       XEmacLite_SetMacAddress(EmacLiteInstPtr, LocalAddress);\r
+\r
+       /*\r
+        * Empty any existing receive frames.\r
+        */\r
+       XEmacLite_FlushReceive(EmacLiteInstPtr);\r
+\r
+\r
+       /*\r
+        * Check if there is a Tx buffer available, if there isn't it is an\r
+        * error.\r
+        */\r
+       if (XEmacLite_TxBufferAvailable(EmacLiteInstPtr) != TRUE) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+\r
+       /*\r
+        * Set up the interrupt infrastructure.\r
+        */\r
+       Status = EmacLiteSetupIntrSystem(IntcInstancePtr,\r
+                                        EmacLiteInstPtr,\r
+                                        EmacLiteIntrId);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       /*\r
+        * Setup the EmacLite handlers.\r
+        */\r
+       XEmacLite_SetRecvHandler((EmacLiteInstPtr), (void *)(EmacLiteInstPtr),\r
+                                (XEmacLite_Handler)EmacLiteRecvHandler);\r
+       XEmacLite_SetSendHandler((EmacLiteInstPtr), (void *)(EmacLiteInstPtr),\r
+                                (XEmacLite_Handler)EmacLiteSendHandler);\r
+\r
+\r
+       /*\r
+        * Enable the interrupts in the EmacLite controller.\r
+        */\r
+       XEmacLite_EnableInterrupts(EmacLiteInstPtr);\r
+       RecvFrameLength = 0;\r
+\r
+       /*\r
+        * If the MDIO is configured in the device.\r
+        */\r
+       if (XEmacLite_IsMdioConfigured(EmacLiteInstPtr)) {\r
+               /*\r
+                * Detect the PHY device and enable the MAC Loop back\r
+                * in the PHY.\r
+                */\r
+               PhyAddress = EmacLitePhyDetect(EmacLiteInstPtr);\r
+               Status = EmacLiteEnablePhyLoopBack(EmacLiteInstPtr,\r
+                                                        PhyAddress);\r
+               if (Status != XST_SUCCESS) {\r
+                       XEmacLite_DisableInterrupts(EmacLiteInstPtr);\r
+                       EmacLiteDisableIntrSystem(IntcInstancePtr,\r
+                                                        EmacLiteIntrId);\r
+                       return XST_FAILURE;\r
+               }\r
+       }\r
+\r
+       /*\r
+        * Transmit an Ethernet frame.\r
+        */\r
+       Status = EmacLiteSendFrame(EmacLiteInstPtr,\r
+                                  EMACLITE_TEST_FRAME_SIZE);\r
+       if (Status != XST_SUCCESS) {\r
+               if (XEmacLite_IsMdioConfigured(EmacLiteInstPtr)) {\r
+                       /*\r
+                        * Disable the MAC Loop back in the PHY and\r
+                        * disable/disconnect the EmacLite Interrupts.\r
+                        */\r
+                       EmacLiteDisablePhyLoopBack(EmacLiteInstPtr,\r
+                                                        PhyAddress);\r
+                       XEmacLite_DisableInterrupts(EmacLiteInstPtr);\r
+                       EmacLiteDisableIntrSystem(IntcInstancePtr,\r
+                                                        EmacLiteIntrId);\r
+                       return XST_FAILURE;\r
+               }\r
+       }\r
+\r
+       /*\r
+        * Wait for the frame to be transmitted.\r
+        */\r
+       while (TransmitComplete == FALSE);\r
+\r
+       /*\r
+        * If the MDIO is not configured in the core then return XST_SUCCESS\r
+        * as the frame has been transmitted.\r
+        */\r
+       if (!XEmacLite_IsMdioConfigured(EmacLiteInstPtr)) {\r
+\r
+               /*\r
+                * Disable and disconnect the EmacLite Interrupts.\r
+                */\r
+               XEmacLite_DisableInterrupts(EmacLiteInstPtr);\r
+               EmacLiteDisableIntrSystem(IntcInstancePtr, EmacLiteIntrId);\r
+               return XST_SUCCESS;\r
+       }\r
+\r
+       /*\r
+        * Wait for the frame to be received.\r
+        */\r
+       while (RecvFrameLength == 0);\r
+\r
+       /*\r
+        * Check the received frame.\r
+        */\r
+       Status = EmacLiteRecvFrame(EMACLITE_TEST_FRAME_SIZE);\r
+\r
+       /*\r
+        *  Diasble the Loop Back.\r
+        */\r
+       if (XEmacLite_IsMdioConfigured(EmacLiteInstPtr)) {\r
+               /*\r
+                * Disable the MAC Loop back in the PHY.\r
+                */\r
+                Status |= EmacLiteDisablePhyLoopBack(EmacLiteInstPtr,\r
+                PhyAddress);\r
+       }\r
+\r
+       /*\r
+        * Disable and disconnect the EmacLite Interrupts.\r
+        */\r
+       XEmacLite_DisableInterrupts(EmacLiteInstPtr);\r
+       EmacLiteDisableIntrSystem(IntcInstancePtr, EmacLiteIntrId);\r
+       if ((Status != XST_SUCCESS) && (Status != XST_NO_DATA)) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+}\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* This function sends a frame of given size. This function assumes interrupt\r
+* mode and sends the frame.\r
+*\r
+* @param       EmacLiteInstPtr is a pointer to the EmacLite instance.\r
+* @param       PayloadSize is the size of the frame to create. The size only\r
+*              reflects the payload size, it does not include the Ethernet\r
+*              header size (14 bytes) nor the Ethernet CRC size (4 bytes).\r
+*\r
+* @return      XST_SUCCESS if successful, else XST_FAILURE.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+static int EmacLiteSendFrame(XEmacLite *EmacLiteInstPtr,  u32 PayloadSize)\r
+{\r
+       int Status;\r
+       u8 *FramePtr;\r
+       u32 Index;\r
+\r
+       /*\r
+        * Set the Complete flag to false.\r
+        */\r
+       TransmitComplete = FALSE;\r
+\r
+       /*\r
+        * Assemble the frame with a destination address and the source address.\r
+        */\r
+       FramePtr = (u8 *)TxFrame;\r
+\r
+       /*\r
+        * Set up the destination address as the local address for\r
+        * Phy Loopback and Internal loopback.\r
+        */\r
+       if (XEmacLite_IsMdioConfigured(EmacLiteInstPtr) ||\r
+               XEmacLite_IsLoopbackConfigured(EmacLiteInstPtr)) {\r
+\r
+               *FramePtr++ = LocalAddress[0];\r
+               *FramePtr++ = LocalAddress[1];\r
+               *FramePtr++ = LocalAddress[2];\r
+               *FramePtr++ = LocalAddress[3];\r
+               *FramePtr++ = LocalAddress[4];\r
+               *FramePtr++ = LocalAddress[5];\r
+       } else {\r
+               /*\r
+                * Fill in the valid Destination MAC address if\r
+                * the Loopback is not enabled.\r
+                */\r
+               *FramePtr++ = RemoteAddress[0];\r
+               *FramePtr++ = RemoteAddress[1];\r
+               *FramePtr++ = RemoteAddress[2];\r
+               *FramePtr++ = RemoteAddress[3];\r
+               *FramePtr++ = RemoteAddress[4];\r
+               *FramePtr++ = RemoteAddress[5];\r
+       }\r
+\r
+       /*\r
+        * Fill in the source MAC address.\r
+        */\r
+       *FramePtr++ = LocalAddress[0];\r
+       *FramePtr++ = LocalAddress[1];\r
+       *FramePtr++ = LocalAddress[2];\r
+       *FramePtr++ = LocalAddress[3];\r
+       *FramePtr++ = LocalAddress[4];\r
+       *FramePtr++ = LocalAddress[5];\r
+\r
+       /*\r
+        * Set up the type/length field - be sure its in network order.\r
+        */\r
+    *((u16 *)FramePtr) = Xil_Htons(PayloadSize);\r
+    FramePtr++;\r
+       FramePtr++;\r
+\r
+       /*\r
+        * Now fill in the data field with known values so we can verify them.\r
+        */\r
+       for (Index = 0; Index < PayloadSize; Index++) {\r
+               *FramePtr++ = (u8)Index;\r
+       }\r
+\r
+       /*\r
+        * Now send the frame.\r
+        */\r
+       Status = XEmacLite_Send(EmacLiteInstPtr, (u8 *)TxFrame,\r
+                               PayloadSize + XEL_HEADER_SIZE);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+}\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* This function receives a frame of given size. This function assumes interrupt\r
+* mode, receives the frame and verifies its contents.\r
+*\r
+* @param       PayloadSize is the size of the frame to receive.\r
+*              The size only reflects the payload size, it does not include the\r
+*              Ethernet header size (14 bytes) nor the Ethernet CRC size (4\r
+*              bytes).\r
+*\r
+* @return      XST_SUCCESS if successful, a driver-specific return code if not.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+static int EmacLiteRecvFrame(u32 PayloadSize)\r
+{\r
+       u8 *FramePtr;\r
+\r
+       /*\r
+        * This assumes MAC does not strip padding or CRC.\r
+        */\r
+       if (RecvFrameLength != 0) {\r
+               int Index;\r
+\r
+               /*\r
+                * Verify length, which should be the payload size.\r
+                */\r
+               if ((RecvFrameLength- (XEL_HEADER_SIZE + XEL_FCS_SIZE)) !=\r
+                               PayloadSize) {\r
+                       return XST_LOOPBACK_ERROR;\r
+               }\r
+\r
+               /*\r
+                * Verify the contents of the Received Frame.\r
+                */\r
+               FramePtr = (u8 *)RxFrame;\r
+               FramePtr += XEL_HEADER_SIZE;    /* Get past the header */\r
+\r
+               for (Index = 0; Index < PayloadSize; Index++) {\r
+                       if (*FramePtr++ != (u8)Index) {\r
+                               return XST_LOOPBACK_ERROR;\r
+                       }\r
+               }\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+}\r
+\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* This function handles the receive callback from the EmacLite driver.\r
+*\r
+* @param       CallBackRef is the call back reference provided to the Handler.\r
+*\r
+* @return      None.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+static void EmacLiteRecvHandler(void *CallBackRef)\r
+{\r
+       XEmacLite *XEmacInstancePtr;\r
+\r
+       /*\r
+        * Convert the argument to something useful.\r
+        */\r
+       XEmacInstancePtr = (XEmacLite *)CallBackRef;\r
+\r
+       /*\r
+        * Handle the Receive callback.\r
+        */\r
+       RecvFrameLength = XEmacLite_Recv(XEmacInstancePtr, (u8 *)RxFrame);\r
+\r
+}\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* This function handles the transmit callback from the EmacLite driver.\r
+*\r
+* @param       CallBackRef is the call back reference provided to the Handler.\r
+*\r
+* @return      None.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+static void EmacLiteSendHandler(void *CallBackRef)\r
+{\r
+       XEmacLite *XEmacInstancePtr;\r
+\r
+       /*\r
+        * Convert the argument to something useful.\r
+        */\r
+       XEmacInstancePtr = (XEmacLite *)CallBackRef;\r
+\r
+       /*\r
+        * Handle the Transmit callback.\r
+        */\r
+       TransmitComplete = TRUE;\r
+\r
+}\r
+\r
+/*****************************************************************************/\r
+/**\r
+*\r
+* This function setups the interrupt system such that interrupts can occur\r
+* for the EmacLite device. This function is application specific since the\r
+* actual system may or may not have an interrupt controller.  The EmacLite\r
+* could be directly connected to a processor without an interrupt controller.\r
+* The user should modify this function to fit the application.\r
+*\r
+* @param       IntcInstancePtr is a pointer to the instance of the Intc.\r
+* @param       EmacLiteInstPtr is a pointer to the instance of the EmacLite.\r
+* @param       EmacLiteIntrId is the interrupt ID and is typically\r
+*              XPAR_<INTC_instance>_<EMACLITE_instance>_VEC_ID\r
+*              value from xparameters.h\r
+*\r
+* @return      XST_SUCCESS if successful, otherwise XST_FAILURE.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+static int EmacLiteSetupIntrSystem(XIntc *IntcInstancePtr,\r
+                        XEmacLite *EmacLiteInstPtr, u16 EmacLiteIntrId)\r
+{\r
+       int Status;\r
+\r
+#ifndef TESTAPP_GEN\r
+       /*\r
+        * Initialize the interrupt controller driver so that it is ready to\r
+        * use.\r
+        */\r
+       Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+#endif\r
+       /*\r
+        * Connect a device driver handler that will be called when an interrupt\r
+        * for the device occurs, the device driver handler performs the\r
+        * specific interrupt processing for the device.\r
+        */\r
+       Status = XIntc_Connect(IntcInstancePtr,\r
+                               EmacLiteIntrId,\r
+                               XEmacLite_InterruptHandler,\r
+                               (void *)(EmacLiteInstPtr));\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+#ifndef TESTAPP_GEN\r
+       /*\r
+        * Start the interrupt controller such that interrupts are enabled for\r
+        * all devices that cause interrupts, specific real mode so that\r
+        * the EmacLite can cause interrupts thru the interrupt controller.\r
+        */\r
+       Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+#endif\r
+\r
+       /*\r
+        * Enable the interrupt for the EmacLite in the Interrupt controller.\r
+        */\r
+       XIntc_Enable(IntcInstancePtr, EmacLiteIntrId);\r
+\r
+#ifndef TESTAPP_GEN\r
+\r
+       /*\r
+        * Initialize the exception table.\r
+        */\r
+       Xil_ExceptionInit();\r
+\r
+       /*\r
+        * Register the interrupt controller handler with the exception table.\r
+        */\r
+       Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,\r
+                               (Xil_ExceptionHandler) XIntc_InterruptHandler,\r
+                               IntcInstancePtr);\r
+\r
+       /*\r
+        * Enable non-critical exceptions.\r
+        */\r
+       Xil_ExceptionEnable();\r
+\r
+#endif /* TESTAPP_GEN */\r
+\r
+       return XST_SUCCESS;\r
+}\r
+\r
+\r
+/*****************************************************************************/\r
+/**\r
+*\r
+* This function disables the interrupts that occur for the EmacLite device.\r
+*\r
+* @param       IntcInstancePtr is the pointer to the instance of the INTC\r
+*              component.\r
+* @param       EmacLiteIntrId is the interrupt ID and is typically\r
+*              XPAR_<INTC_instance>_<EMACLITE_instance>_VEC_ID\r
+*              value from xparameters.h.\r
+*\r
+* @return      None.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+static void EmacLiteDisableIntrSystem(XIntc *IntcInstancePtr,\r
+                                                        u16 EmacLiteIntrId)\r
+{\r
+       /*\r
+        * Disconnect and disable the interrupts for the EmacLite device.\r
+        */\r
+       XIntc_Disconnect(IntcInstancePtr, EmacLiteIntrId);\r
+\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xemaclite_polled_example.c b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xemaclite_polled_example.c
new file mode 100644 (file)
index 0000000..c4b6405
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xemaclite_polled_example.c
@@ -0,0 +1,409 @@
+#define TESTAPP_GEN
+\r
+/* $Id: xemaclite_polled_example.c,v 1.1.2.2 2010/08/06 15:11:04 anirudh Exp $\r
+*/\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2004-2010 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+/*****************************************************************************/\r
+/**\r
+* @file xemaclite_polled_example.c\r
+*\r
+* This file contains an example for using the EmacLite hardware and driver.\r
+* This file contains an polled mode example outlining the transmission/reception\r
+* of an Ethernet frame of 1000 bytes of payload.\r
+*\r
+* If the MDIO interface is NOT configured in the EmacLite core then this example\r
+* will only transmit a frame.\r
+* If the MDIO interface is configured in the EmacLite core then this example\r
+* will enable the MAC loopback in the PHY device, then transmit the frame and\r
+* compare the received frame.\r
+*\r
+* @note\r
+*\r
+* <pre>\r
+* MODIFICATION HISTORY:\r
+*\r
+* Ver   Who  Date     Changes\r
+* ----- ---- -------- -----------------------------------------------\r
+* 1.01a ecm  21/05/04 First release\r
+* 1.01a sv   06/06/05 Minor changes to comply to Doxygen and coding guidelines\r
+* 2.00a ktn  02/25/09 Updated to use PHY loop back if MDIO is configured in\r
+*                    core and updated to be used in Test App\r
+* 3.00a ktn  10/22/09 Updated example to use the macros that have been changed\r
+*                    in the driver to remove _m from the name of the macro.\r
+* 3.01a ktn  07/08/10 Updated example to support Little Endian MicroBlaze.\r
+*\r
+* </pre>\r
+*\r
+*****************************************************************************/\r
+\r
+/***************************** Include Files *********************************/\r
+\r
+#include "xemaclite_example.h"\r
+\r
+/************************** Constant Definitions *****************************/\r
+\r
+/*\r
+ * The Size of the Test Frame.\r
+ */\r
+#define EMACLITE_TEST_FRAME_SIZE       1000\r
+\r
+/**************************** Type Definitions *******************************/\r
+\r
+/***************** Macros (Inline Functions) Definitions *********************/\r
+\r
+/************************** Function Prototypes ******************************/\r
+\r
+int EmacLitePolledExample(u16 DeviceId);\r
+\r
+static int EmacLiteSendFrame(XEmacLite *InstancePtr, u32 PayloadSize);\r
+\r
+static int EmacLiteRecvFrame(u32 PayloadSize);\r
+\r
+/************************** Variable Definitions *****************************/\r
+\r
+/*\r
+ * Set up valid local and remote MAC addresses. This loop back test uses the\r
+ * LocalAddress both as a source and destination MAC address.\r
+ */\r
+static u8 LocalAddress[XEL_MAC_ADDR_SIZE] =\r
+{\r
+       0x00, 0x0A, 0x35, 0x01, 0x02, 0x03\r
+};\r
+static u8 RemoteAddress[XEL_MAC_ADDR_SIZE] =\r
+{\r
+       0x00, 0x10, 0xa4, 0xb6, 0xfd, 0x09\r
+};\r
+\r
+/****************************************************************************/\r
+/**\r
+*\r
+* This function is the main function of the EmacLite polled example.\r
+*\r
+* @param       None.\r
+*\r
+* @return      XST_SUCCESS to indicate success, otherwise XST_FAILURE .\r
+*\r
+* @note                None.\r
+*\r
+*****************************************************************************/\r
+#ifndef TESTAPP_GEN\r
+int main()\r
+{\r
+       int Status;\r
+\r
+       /*\r
+        * Run the EmacLite Polled example, specify the Device ID that is\r
+        * generated in xparameters.h.\r
+        */\r
+       Status = EmacLitePolledExample(EMAC_DEVICE_ID);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+}\r
+#endif\r
+\r
+/*****************************************************************************/\r
+/**\r
+*\r
+* The main entry point for the EmacLite driver example in polled mode.\r
+*\r
+* This function will transmit/receive the Ethernet frames and verify the\r
+* data in the received frame (if the MDIO interface is configured in the\r
+* EmacLite core).\r
+* This function simply transmits a frame if the MDIO interface is not\r
+* configured in the EmacLite core.\r
+*\r
+* @param       DeviceId is device ID of the XEmacLite Device , typically\r
+*              XPAR_<EMAC_instance>_DEVICE_ID value from xparameters.h.\r
+*\r
+* @return      XST_SUCCESS to indicate success, XST_FAILURE otherwise.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+int EmacLitePolledExample(u16 DeviceId)\r
+{\r
+       int Status;\r
+       XEmacLite *EmacLiteInstPtr = &EmacLiteInstance;\r
+       u32 PhyAddress = 0;\r
+       RecvFrameLength = 0;\r
+       XEmacLite_Config *ConfigPtr;\r
+\r
+       /*\r
+        * Initialize the EmacLite device.\r
+        */\r
+       ConfigPtr = XEmacLite_LookupConfig(DeviceId);\r
+       if (ConfigPtr == NULL) {\r
+               return XST_FAILURE;\r
+       }\r
+       Status = XEmacLite_CfgInitialize(EmacLiteInstPtr,\r
+                                       ConfigPtr,\r
+                                       ConfigPtr->BaseAddress);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       /*\r
+        * Set the MAC address.\r
+        */\r
+       XEmacLite_SetMacAddress(EmacLiteInstPtr, LocalAddress);\r
+\r
+       /*\r
+        * Empty any existing receive frames.\r
+        */\r
+       XEmacLite_FlushReceive(EmacLiteInstPtr);\r
+\r
+       /*\r
+        * Check if there is a TX buffer available, if there isn't it is an\r
+        * error.\r
+        */\r
+       if (XEmacLite_TxBufferAvailable(EmacLiteInstPtr) != TRUE) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       /*\r
+        * If the MDIO is configured in the device.\r
+        */\r
+       if (XEmacLite_IsMdioConfigured(EmacLiteInstPtr)) {\r
+               /*\r
+                * Detect the PHY device and enable the MAC Loop back\r
+                * in the PHY.\r
+                */\r
+               PhyAddress = EmacLitePhyDetect(EmacLiteInstPtr);\r
+               Status = EmacLiteEnablePhyLoopBack(EmacLiteInstPtr,\r
+                                                        PhyAddress);\r
+               if (Status != XST_SUCCESS) {\r
+                       return XST_FAILURE;\r
+               }\r
+       }\r
+\r
+\r
+       /*\r
+        * Reset the receive frame length to zero.\r
+        */\r
+       RecvFrameLength = 0;\r
+       Status = EmacLiteSendFrame(EmacLiteInstPtr, EMACLITE_TEST_FRAME_SIZE);\r
+       if (Status != XST_SUCCESS) {\r
+               if (XEmacLite_IsMdioConfigured(EmacLiteInstPtr)) {\r
+                       /*\r
+                        * Disable the MAC Loop back in the PHY.\r
+                        */\r
+                       EmacLiteDisablePhyLoopBack(EmacLiteInstPtr,\r
+                                                        PhyAddress);\r
+                       return XST_FAILURE;\r
+               }\r
+       }\r
+\r
+       /*\r
+        * If the MDIO is not configured in the core then return XST_SUCCESS\r
+        * as the frame has been transmitted.\r
+        */\r
+       if (!XEmacLite_IsMdioConfigured(EmacLiteInstPtr)) {\r
+               return XST_SUCCESS;\r
+       }\r
+\r
+\r
+       /*\r
+        * Poll for receive packet.\r
+        */\r
+       while ((volatile u32)RecvFrameLength == 0)  {\r
+               RecvFrameLength = XEmacLite_Recv(EmacLiteInstPtr,\r
+                                               (u8 *)RxFrame);\r
+       }\r
+\r
+       /*\r
+        * Check the received frame.\r
+        */\r
+       Status = EmacLiteRecvFrame(EMACLITE_TEST_FRAME_SIZE);\r
+       if ((Status != XST_SUCCESS) && (Status != XST_NO_DATA)) {\r
+               /*\r
+                * Disable the MAC Loop back in the PHY.\r
+                */\r
+               EmacLiteDisablePhyLoopBack(EmacLiteInstPtr, PhyAddress);\r
+               return XST_FAILURE;\r
+       }\r
+\r
+\r
+       /*\r
+        * Disable the MAC Loop back in the PHY.\r
+        */\r
+       EmacLiteDisablePhyLoopBack(EmacLiteInstPtr, PhyAddress);\r
+\r
+       return XST_SUCCESS;\r
+}\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* This function sends a frame of given size.\r
+*\r
+* @param       XEmacInstancePtr is a pointer to the XEmacLite instance.\r
+* @param       PayloadSize is the size of the frame to create. The size only\r
+*              reflects the payload size, it does not include the Ethernet\r
+*              header size (14 bytes) nor the Ethernet CRC size (4 bytes).\r
+*\r
+* @return      XST_SUCCESS if successful, else a driver-specific return code.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+static int EmacLiteSendFrame(XEmacLite *InstancePtr, u32 PayloadSize)\r
+{\r
+       u8 *FramePtr;\r
+       int Index;\r
+       FramePtr = (u8 *)TxFrame;\r
+\r
+       /*\r
+        * Set up the destination address as the local address for\r
+        * Phy Loopback.\r
+        */\r
+       if (XEmacLite_IsMdioConfigured(InstancePtr)) {\r
+\r
+               *FramePtr++ = LocalAddress[0];\r
+               *FramePtr++ = LocalAddress[1];\r
+               *FramePtr++ = LocalAddress[2];\r
+               *FramePtr++ = LocalAddress[3];\r
+               *FramePtr++ = LocalAddress[4];\r
+               *FramePtr++ = LocalAddress[5];\r
+       } else {\r
+               /*\r
+                * Fill in the valid Destination MAC address if\r
+                * the Loopback is not enabled.\r
+                */\r
+               *FramePtr++ = RemoteAddress[0];\r
+               *FramePtr++ = RemoteAddress[1];\r
+               *FramePtr++ = RemoteAddress[2];\r
+               *FramePtr++ = RemoteAddress[3];\r
+               *FramePtr++ = RemoteAddress[4];\r
+               *FramePtr++ = RemoteAddress[5];\r
+       }\r
+\r
+       /*\r
+        * Fill in the source MAC address.\r
+        */\r
+       *FramePtr++ = LocalAddress[0];\r
+       *FramePtr++ = LocalAddress[1];\r
+       *FramePtr++ = LocalAddress[2];\r
+       *FramePtr++ = LocalAddress[3];\r
+       *FramePtr++ = LocalAddress[4];\r
+       *FramePtr++ = LocalAddress[5];\r
+\r
+       /*\r
+        * Set up the type/length field - be sure its in network order.\r
+        */\r
+    *((u16 *)FramePtr) = Xil_Htons(PayloadSize);\r
+       FramePtr++;\r
+       FramePtr++;\r
+\r
+       /*\r
+        * Now fill in the data field with known values so we can verify them\r
+        * on receive.\r
+        */\r
+       for (Index = 0; Index < PayloadSize; Index++) {\r
+               *FramePtr++ = (u8)Index;\r
+       }\r
+\r
+       /*\r
+        * Now send the frame.\r
+        */\r
+       return XEmacLite_Send(InstancePtr, (u8 *)TxFrame,\r
+                               PayloadSize + XEL_HEADER_SIZE);\r
+\r
+}\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* This function receives a frame of given size. This function assumes interrupt\r
+* mode, receives the frame and verifies its contents.\r
+*\r
+* @param       PayloadSize is the size of the frame to receive.\r
+*              The size only reflects the payload size, it does not include the\r
+*              Ethernet header size (14 bytes) nor the Ethernet CRC size (4\r
+*              bytes).\r
+*\r
+* @return      XST_SUCCESS if successful, a driver-specific return code if not.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+static int EmacLiteRecvFrame(u32 PayloadSize)\r
+{\r
+       u8 *FramePtr;\r
+\r
+       /*\r
+        * This assumes MAC does not strip padding or CRC.\r
+        */\r
+       if (RecvFrameLength != 0) {\r
+               int Index;\r
+\r
+               /*\r
+                * Verify length, which should be the payload size.\r
+                */\r
+               if ((RecvFrameLength- (XEL_HEADER_SIZE + XEL_FCS_SIZE)) !=\r
+                               PayloadSize) {\r
+                       return XST_LOOPBACK_ERROR;\r
+               }\r
+\r
+               /*\r
+                * Verify the contents of the Received Frame.\r
+                */\r
+               FramePtr = (u8 *)RxFrame;\r
+               FramePtr += XEL_HEADER_SIZE;    /* Get past the header */\r
+\r
+               for (Index = 0; Index < PayloadSize; Index++) {\r
+                       if (*FramePtr++ != (u8)Index) {\r
+                               return XST_LOOPBACK_ERROR;\r
+                       }\r
+               }\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xgpio_intr_tapp_example.c b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xgpio_intr_tapp_example.c
new file mode 100644 (file)
index 0000000..45ee87b
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xgpio_intr_tapp_example.c
@@ -0,0 +1,386 @@
+#define TESTAPP_GEN
+\r
+/* $Id: xgpio_intr_tapp_example.c,v 1.1.2.1 2009/11/25 07:38:15 svemula Exp $ */\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2002-2009 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+/*****************************************************************************/\r
+/**\r
+* @file xgpio_intr_tapp_example.c\r
+*\r
+* This file contains a design example using the GPIO driver (XGpio) in an\r
+* interrupt driven mode of operation. This example does assume that there is\r
+* an interrupt controller in the hardware system and the GPIO device is\r
+* connected to the interrupt controller.\r
+*\r
+* This file is used by the TestAppGen utility to include a simplified test for\r
+* gpio interrupts.\r
+\r
+* The buttons and LEDs are on 2 seperate channels of the GPIO so that interrupts\r
+* are not caused when the LEDs are turned on and off.\r
+*\r
+* <pre>\r
+* MODIFICATION HISTORY:\r
+*\r
+* Ver   Who  Date       Changes\r
+* ----- ---- -------- -------------------------------------------------------\r
+* 2.01a sn   05/09/06 Modified to be used by TestAppGen to include test for\r
+*                    interrupts.\r
+* 3.00a ktn  11/21/09 Updated to use HAL Processor APIs and minior changes\r
+*                    as per coding guidelines.\r
+*</pre>\r
+*\r
+******************************************************************************/\r
+\r
+/***************************** Include Files *********************************/\r
+\r
+#include "xparameters.h"\r
+#include "xgpio.h"\r
+#include "xil_exception.h"\r
+#include "xintc.h"\r
+\r
+/************************** Constant Definitions *****************************/\r
+#ifndef TESTAPP_GEN\r
+/*\r
+ * The following constants map to the names of the hardware instances that\r
+ * were created in the EDK XPS system.  They are only defined here such that\r
+ * a user can easily change all the needed device IDs in one place.\r
+ */\r
+#define GPIO_DEVICE_ID         XPAR_PUSH_BUTTONS_5BIT_DEVICE_ID\r
+#define INTC_DEVICE_ID         XPAR_INTC_0_DEVICE_ID\r
+#define INTC_GPIO_INTERRUPT_ID XPAR_INTC_0_GPIO_3_VEC_ID\r
+#define GPIO_CHANNEL1 1\r
+/*\r
+ * The following constants define the positions of the buttons and LEDs each\r
+ * channel of the GPIO\r
+ */\r
+#define GPIO_ALL_LEDS          0xFFFF\r
+#define GPIO_ALL_BUTTONS       0xFFFF\r
+\r
+/*\r
+ * The following constants define the GPIO channel that is used for the buttons\r
+ * and the LEDs. They allow the channels to be reversed easily.\r
+ */\r
+#define BUTTON_CHANNEL  1      /* Channel 1 of the GPIO Device */\r
+#define LED_CHANNEL     2      /* Channel 2 of the GPIO Device */\r
+#define BUTTON_INTERRUPT XGPIO_IR_CH1_MASK  /* Channel 1 Interrupt Mask */\r
+\r
+/*\r
+ * The following constant determines which buttons must be pressed at the same\r
+ * time to cause interrupt processing to stop and start\r
+ */\r
+#define INTERRUPT_CONTROL_VALUE 0x7\r
+\r
+/*\r
+ * The following constant is used to wait after an LED is turned on to make\r
+ * sure that it is visible to the human eye.  This constant might need to be\r
+ * tuned for faster or slower processor speeds.\r
+ */\r
+#define LED_DELAY       1000000\r
+\r
+#endif\r
+\r
+#define INTR_DELAY     0x00FFFFFF\r
+\r
+\r
+/************************** Function Prototypes ******************************/\r
+void GpioDriverHandler(void *CallBackRef);\r
+\r
+int GpioIntrExample(XIntc* IntcInstancePtr, XGpio* InstancePtr,\r
+                       u16 DeviceId, u16 IntrId,\r
+                       u16 IntrMask, u32 *DataRead);\r
+\r
+int GpioSetupIntrSystem(XIntc* IntcInstancePtr, XGpio* InstancePtr,\r
+                       u16 DeviceId, u16 IntrId, u16 IntrMask);\r
+\r
+void GpioDisableIntr(XIntc* IntcInstancePtr, XGpio* InstancePtr,\r
+                        u16 IntrId, u16 IntrMask);\r
+\r
+/************************** Variable Definitions *****************************/\r
+\r
+/*\r
+ * The following are declared globally so they are zeroed and so they are\r
+ * easily accessible from a debugger\r
+ */\r
+XGpio Gpio; /* The Instance of the GPIO Driver */\r
+\r
+XIntc Intc; /* The Instance of the Interrupt Controller Driver */\r
+\r
+\r
+static u16 GlobalIntrMask; /* GPIO channel mask that is needed by\r
+                           * the Interrupt Handler */\r
+\r
+static volatile u32 IntrFlag; /* Interrupt Handler Flag */\r
+\r
+/****************************************************************************/\r
+/**\r
+* This function is the main function of the GPIO example.  It is responsible\r
+* for initializing the GPIO device, setting up interrupts and providing a\r
+* foreground loop such that interrupt can occur in the background.\r
+*\r
+* @param       None.\r
+*\r
+* @return\r
+*              - XST_SUCCESS to indicate success.\r
+*              - XST_FAILURE to indicate failure.\r
+*\r
+* @note                None.\r
+*\r
+*****************************************************************************/\r
+#ifndef TESTAPP_GEN\r
+int main(void)\r
+{\r
+       int Status;\r
+       u32 DataRead;\r
+\r
+         print(" Press button to Generate Interrupt\r\n");\r
+\r
+         Status = GpioIntrExample(&Intc, &Gpio,\r
+                                  GPIO_DEVICE_ID,\r
+                                  INTC_GPIO_INTERRUPT_ID,\r
+                                  GPIO_CHANNEL1, &DataRead);\r
+\r
+       if (Status == 0 ){\r
+               if(DataRead == 0)\r
+                       print("No button pressed. \r\n");\r
+               else\r
+                       print("Gpio Interrupt Test PASSED. \r\n");\r
+       } else {\r
+                print("Gpio Interrupt Test FAILED.\r\n");\r
+       }\r
+}\r
+#endif\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* This is the entry function from the TestAppGen tool generated application\r
+* which tests the interrupts when enabled in the GPIO\r
+*\r
+* @param       IntcInstancePtr is a reference to the Interrupt Controller\r
+*              driver Instance\r
+* @param       InstancePtr is a reference to the GPIO driver Instance\r
+* @param       DeviceId is the XPAR_<GPIO_instance>_DEVICE_ID value from\r
+*              xparameters.h\r
+* @param       IntrId is XPAR_<INTC_instance>_<GPIO_instance>_IP2INTC_IRPT_INTR\r
+*              value from xparameters.h\r
+* @param       IntrMask is the GPIO channel mask\r
+* @param       DataRead is the pointer where the data read from GPIO Input is\r
+*              returned\r
+*\r
+* @return      XST_SUCCESS if the Test is successful, otherwise XST_FAILURE\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+int GpioIntrExample(XIntc* IntcInstancePtr, XGpio* InstancePtr, u16 DeviceId,\r
+                       u16 IntrId, u16 IntrMask, u32 *DataRead)\r
+{\r
+       int Status;\r
+       u32 delay;\r
+\r
+       /* Initialize the GPIO driver. If an error occurs then exit */\r
+\r
+       Status = XGpio_Initialize(InstancePtr, DeviceId);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       Status = GpioSetupIntrSystem(IntcInstancePtr,\r
+                                InstancePtr,\r
+                                DeviceId,\r
+                                IntrId,\r
+                                IntrMask);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       IntrFlag = 0;\r
+       delay = 0;\r
+\r
+       while(!IntrFlag && (delay < INTR_DELAY)) {\r
+               delay++;\r
+       }\r
+\r
+       GpioDisableIntr(IntcInstancePtr,\r
+                       InstancePtr,\r
+                       IntrId,\r
+                       IntrMask);\r
+\r
+       *DataRead = IntrFlag;\r
+\r
+       return Status;\r
+\r
+}\r
+\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* This function performs the GPIO set up for Interrupts\r
+*\r
+* @param       IntcInstancePtr is a reference to the Interrupt Controller\r
+*              driver Instance\r
+* @param       InstancePtr is a reference to the GPIO driver Instance\r
+* @param       DeviceId is the XPAR_<GPIO_instance>_DEVICE_ID value from\r
+*              xparameters.h\r
+* @param       IntrId is XPAR_<INTC_instance>_<GPIO_instance>_IP2INTC_IRPT_INTR\r
+*              value from xparameters.h\r
+* @param       IntrMask is the GPIO channel mask\r
+*\r
+* @return      XST_SUCCESS if the Test is successful, otherwise XST_FAILURE\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+int GpioSetupIntrSystem(XIntc* IntcInstancePtr, XGpio* InstancePtr,\r
+                       u16 DeviceId, u16 IntrId, u16 IntrMask)\r
+\r
+{\r
+       int Result;\r
+\r
+       GlobalIntrMask = IntrMask;\r
+\r
+#ifndef TESTAPP_GEN\r
+       /*\r
+        * Initialize the interrupt controller driver so that it's ready to use.\r
+        * specify the device ID that was generated in xparameters.h\r
+        */\r
+       Result = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);\r
+       if (Result != XST_SUCCESS) {\r
+               return Result;\r
+       }\r
+#endif\r
+\r
+       /* Hook up simple interrupt service routine for TestApp */\r
+\r
+       Result = XIntc_Connect(IntcInstancePtr, IntrId,\r
+                                 (XInterruptHandler)GpioDriverHandler,\r
+                                 InstancePtr);\r
+\r
+       /*\r
+        * Enable the GPIO channel interrupts so that push button can be detected\r
+        * and enable interrupts for the GPIO device\r
+        */\r
+       XGpio_InterruptEnable(InstancePtr, IntrMask);\r
+       XGpio_InterruptGlobalEnable(InstancePtr);\r
+\r
+       /* Enable the interrupt vector at the interrupt controller */\r
+       XIntc_Enable(IntcInstancePtr, IntrId);\r
+\r
+#ifndef TESTAPP_GEN\r
+\r
+       /*\r
+        * Initialize the exception table and register the interrupt\r
+        * controller handler with the exception table\r
+        */\r
+       Xil_ExceptionInit();\r
+       Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,\r
+                                (Xil_ExceptionHandler)XIntc_InterruptHandler,\r
+                                IntcInstancePtr);\r
+\r
+       /* Enable non-critical exceptions */\r
+       Xil_ExceptionEnable();\r
+\r
+       /*\r
+        * Start the interrupt controller such that interrupts are recognized\r
+        * and handled by the processor\r
+        */\r
+       Result = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);\r
+#endif\r
+\r
+       if (Result != XST_SUCCESS) {\r
+               return Result;\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+}\r
+\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* This is the interrupt handler routine for the GPIO for this example.\r
+*\r
+* @param       CallbackRef is the Callback reference for the handler.\r
+*\r
+* @return      None.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+void GpioDriverHandler(void *CallbackRef)\r
+{\r
+       XGpio *GpioPtr = (XGpio *)CallbackRef;\r
+\r
+       IntrFlag = 1;\r
+       /*\r
+        * Clear the Interrupt\r
+        */\r
+       XGpio_InterruptClear(GpioPtr, GlobalIntrMask);\r
+\r
+}\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* This function disables the interrupts for the GPIO\r
+*\r
+* @param       IntcInstancePtr is a pointer to the Interrupt Controller\r
+*              driver Instance\r
+* @param       InstancePtr is a pointer to the GPIO driver Instance\r
+* @param       IntrId is XPAR_<INTC_instance>_<GPIO_instance>_IP2INTC_IRPT_INTR\r
+*              value from xparameters.h\r
+* @param       IntrMask is the GPIO channel mask\r
+*\r
+* @return      None\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+void GpioDisableIntr(XIntc* IntcInstancePtr, XGpio* InstancePtr,\r
+                       u16 IntrId, u16 IntrMask)\r
+{\r
+       XGpio_InterruptDisable(InstancePtr, IntrMask);\r
+       XIntc_Disable(IntcInstancePtr, IntrId);\r
+       return;\r
+}\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xgpio_tapp_example.c b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xgpio_tapp_example.c
new file mode 100644 (file)
index 0000000..5e94be9
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xgpio_tapp_example.c
@@ -0,0 +1,294 @@
+#define TESTAPP_GEN
+\r
+/* $Id: xgpio_tapp_example.c,v 1.1.2.1 2009/11/25 07:38:15 svemula Exp $ */\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2005-2009 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+\r
+/*****************************************************************************/\r
+/**\r
+* @file xgpio_tapp_example.c\r
+*\r
+* This file contains a example for using GPIO hardware and driver.\r
+* This example assumes that there is a UART Device or STDIO Device in the\r
+* hardware system.\r
+*\r
+* This example can be run on the Xilinx ML300 board using the Prototype Pins &\r
+* LEDs of the board connected to the GPIO and the Push Buttons connected.\r
+*\r
+* @note\r
+*\r
+* None\r
+*\r
+* <pre>\r
+* MODIFICATION HISTORY:\r
+*\r
+* Ver  Who  Date         Changes\r
+* ----- ---- -------- -----------------------------------------------\r
+* 1.00a sv   04/15/05 Initial release for TestApp integration.\r
+* 3.00a sv   11/21/09 Updated to use HAL Processor APIs.\r
+* </pre>\r
+*\r
+*****************************************************************************/\r
+\r
+/***************************** Include Files ********************************/\r
+\r
+#include "xparameters.h"\r
+#include "xgpio.h"\r
+#include "stdio.h"\r
+#include "xstatus.h"\r
+\r
+/************************** Constant Definitions ****************************/\r
+\r
+/*\r
+ * The following constant is used to wait after an LED is turned on to make\r
+ * sure that it is visible to the human eye.  This constant might need to be\r
+ * tuned for faster or slower processor speeds.\r
+ */\r
+#define LED_DELAY        1000000\r
+\r
+/* following constant is used to determine which channel of the GPIO is\r
+ * used if there are 2 channels supported in the GPIO.\r
+ */\r
+#define LED_CHANNEL 1\r
+\r
+#define LED_MAX_BLINK  0x1     /* Number of times the LED Blinks */\r
+\r
+#define GPIO_BITWIDTH  16      /* This is the width of the GPIO */\r
+\r
+#define printf xil_printf      /* A smaller footprint printf */\r
+\r
+/*\r
+ * The following constants map to the XPAR parameters created in the\r
+ * xparameters.h file. They are defined here such that a user can easily\r
+ * change all the needed parameters in one place.\r
+ */\r
+#ifndef TESTAPP_GEN\r
+#define GPIO_OUTPUT_DEVICE_ID  XPAR_LEDS_4BIT_DEVICE_ID\r
+#define GPIO_INPUT_DEVICE_ID   XPAR_LEDS_4BIT_DEVICE_ID\r
+#endif /* TESTAPP_GEN */\r
+\r
+/**************************** Type Definitions ******************************/\r
+\r
+\r
+/***************** Macros (Inline Functions) Definitions *******************/\r
+\r
+\r
+/************************** Function Prototypes ****************************/\r
+\r
+int GpioOutputExample(u16 DeviceId, u32 GpioWidth);\r
+\r
+int GpioInputExample(u16 DeviceId, u32 *DataRead);\r
+\r
+void GpioDriverHandler(void *CallBackRef);\r
+\r
+\r
+/************************** Variable Definitions **************************/\r
+\r
+/*\r
+ * The following are declared globally so they are zeroed and so they are\r
+ * easily accessible from a debugger\r
+ */\r
+XGpio GpioOutput; /* The driver instance for GPIO Device configured as O/P */\r
+XGpio GpioInput;  /* The driver instance for GPIO Device configured as I/P */\r
+\r
+/*****************************************************************************/\r
+/**\r
+* Main function to call the example.This function is not included if the\r
+* example is generated from the TestAppGen test tool.\r
+*\r
+* @param       None\r
+*\r
+* @return      XST_SUCCESS if successful, XST_FAILURE if unsuccessful\r
+*\r
+* @note                None\r
+*\r
+******************************************************************************/\r
+#ifndef TESTAPP_GEN\r
+int main(void)\r
+{\r
+       int Status;\r
+       u32 InputData;\r
+\r
+       Status = GpioOutputExample(GPIO_OUTPUT_DEVICE_ID, GPIO_BITWIDTH);\r
+       if (Status != XST_SUCCESS) {\r
+                 return XST_FAILURE;\r
+       }\r
+\r
+       Status = GpioInputExample(GPIO_INPUT_DEVICE_ID, &InputData);\r
+       if (Status != XST_SUCCESS) {\r
+                 return XST_FAILURE;\r
+       }\r
+\r
+       printf("Data read from GPIO Input is  0x%x \n", (int)InputData);\r
+\r
+       return XST_SUCCESS;\r
+}\r
+#endif\r
+\r
+\r
+/*****************************************************************************/\r
+/**\r
+*\r
+* This function does a minimal test on the GPIO device configured as OUTPUT\r
+* and driver as a  example.\r
+*\r
+*\r
+* @param       DeviceId is the XPAR_<GPIO_instance>_DEVICE_ID value from\r
+*              xparameters.h\r
+* @param       GpioWidth is the width of the GPIO\r
+*\r
+* @return      XST_SUCCESS if successful, XST_FAILURE if unsuccessful\r
+*\r
+* @note                None\r
+*\r
+****************************************************************************/\r
+int GpioOutputExample(u16 DeviceId, u32 GpioWidth)\r
+{\r
+       u32 Data;\r
+       volatile int Delay;\r
+       u32 LedBit;\r
+       u32 LedLoop;\r
+       int Status;\r
+\r
+       /*\r
+        * Initialize the GPIO driver so that it's ready to use,\r
+        * specify the device ID that is generated in xparameters.h\r
+        */\r
+        Status = XGpio_Initialize(&GpioOutput, DeviceId);\r
+        if (Status != XST_SUCCESS)  {\r
+                 return XST_FAILURE;\r
+        }\r
+\r
+\r
+        /*\r
+         * Set the direction for all signals to be outputs\r
+         */\r
+        XGpio_SetDataDirection(&GpioOutput, LED_CHANNEL, 0x0);\r
+\r
+        /*\r
+         * Set the GPIO outputs to low\r
+         */\r
+        XGpio_DiscreteWrite(&GpioOutput, LED_CHANNEL, 0x0);\r
+\r
+        for (LedBit = 0x0; LedBit < GpioWidth; LedBit++)  {\r
+\r
+               for (LedLoop = 0; LedLoop < LED_MAX_BLINK; LedLoop++) {\r
+\r
+                       /*\r
+                        * Set the GPIO Output to High\r
+                        */\r
+                       XGpio_DiscreteWrite(&GpioOutput, LED_CHANNEL,\r
+                                               1 << LedBit);\r
+\r
+#ifndef __SIM__\r
+                       /*\r
+                        * Wait a small amount of time so the LED is visible\r
+                        */\r
+                       for (Delay = 0; Delay < LED_DELAY; Delay++);\r
+\r
+#endif\r
+                       /*\r
+                        * Clear the GPIO Output\r
+                        */\r
+                       XGpio_DiscreteClear(&GpioOutput, LED_CHANNEL,\r
+                                               1 << LedBit);\r
+\r
+\r
+#ifndef __SIM__\r
+                       /*\r
+                        * Wait a small amount of time so the LED is visible\r
+                        */\r
+                       for (Delay = 0; Delay < LED_DELAY; Delay++);\r
+#endif\r
+\r
+                 }\r
+\r
+        }\r
+\r
+        return XST_SUCCESS;\r
+\r
+}\r
+\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* This function  performs a test on the GPIO driver/device with the GPIO\r
+* configured as INPUT\r
+*\r
+* @param        DeviceId is the XPAR_<GPIO_instance>_DEVICE_ID value from\r
+*                        xparameters.h\r
+* @param        DataRead is the pointer where the data read from GPIO Input is\r
+*                        returned\r
+*\r
+* @return      XST_SUCCESS if the Test is successful, otherwise XST_FAILURE\r
+*\r
+* @note          None.\r
+*\r
+******************************************************************************/\r
+int GpioInputExample(u16 DeviceId, u32 *DataRead)\r
+{\r
+        int Status;\r
+\r
+        /*\r
+         * Initialize the GPIO driver so that it's ready to use,\r
+         * specify the device ID that is generated in xparameters.h\r
+         */\r
+        Status = XGpio_Initialize(&GpioInput, DeviceId);\r
+        if (Status != XST_SUCCESS) {\r
+                 return XST_FAILURE;\r
+        }\r
+\r
+        /*\r
+         * Set the direction for all signals to be inputs\r
+         */\r
+        XGpio_SetDataDirection(&GpioInput, LED_CHANNEL, 0xFFFFFFFF);\r
+\r
+        /*\r
+         * Read the state of the data so that it can be  verified\r
+         */\r
+        *DataRead = XGpio_DiscreteRead(&GpioInput, LED_CHANNEL);\r
+\r
+        return XST_SUCCESS;\r
+\r
+}\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xintc_tapp_example.c b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xintc_tapp_example.c
new file mode 100644 (file)
index 0000000..a759313
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xintc_tapp_example.c
@@ -0,0 +1,265 @@
+#define TESTAPP_GEN
+\r
+\r
+/* $Id: xintc_tapp_example.c,v 1.1.4.1 2010/09/17 05:32:46 svemula Exp $ */\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2002-2009 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+/******************************************************************************/\r
+/**\r
+*\r
+* @file xintc_tapp_example.c\r
+*\r
+* This file contains a self test example using the Interrupt Controller driver\r
+* (XIntc) and hardware device. Please reference other device driver examples to\r
+* see more examples of how the Intc and interrupts can be used by a software\r
+* application.\r
+*\r
+* This example shows the use of the Interrupt Controller both with a PowerPC405\r
+* and MicroBlaze processor.\r
+*\r
+* The TestApp Gen utility uses this file to perform the self test and setup\r
+* of Intc for interrupts.\r
+*\r
+* @note\r
+*\r
+* None\r
+*\r
+* <pre>\r
+*\r
+* MODIFICATION HISTORY:\r
+*\r
+* Ver   Who  Date       Changes\r
+* ----- ---- -------- --------------------------------------------------------\r
+* 1.00a sv   06/29/05  Created for Test App Integration\r
+* 1.00c sn   05/09/06  Added Interrupt Setup Function\r
+* 2.00a ktn  10/20/09  Updated to use HAL Processor APIs and minor changes as\r
+*                     per coding guidelines.\r
+* </pre>\r
+******************************************************************************/\r
+\r
+/***************************** Include Files *********************************/\r
+\r
+#include "xparameters.h"\r
+#include "xstatus.h"\r
+#include "xintc.h"\r
+#include "xil_exception.h"\r
+\r
+\r
+/************************** Constant Definitions *****************************/\r
+\r
+/*\r
+ * The following constants map to the XPAR parameters created in the\r
+ * xparameters.h file. They are defined here such that a user can easily\r
+ * change all the needed parameters in one place. This definition is not\r
+ * included if the example is generated from the TestAppGen test tool.\r
+ */\r
+#ifndef TESTAPP_GEN\r
+#define INTC_DEVICE_ID           XPAR_INTC_0_DEVICE_ID\r
+#endif\r
+\r
+/**************************** Type Definitions *******************************/\r
+\r
+\r
+/***************** Macros (Inline Functions) Definitions *********************/\r
+\r
+\r
+/************************** Function Prototypes ******************************/\r
+\r
+int IntcSelfTestExample(u16 DeviceId);\r
+int IntcInterruptSetup(XIntc *IntcInstancePtr, u16 DeviceId);\r
+\r
+/************************** Variable Definitions *****************************/\r
+\r
+static XIntc InterruptController; /* Instance of the Interrupt Controller */\r
+\r
+\r
+/*****************************************************************************/\r
+/**\r
+*\r
+* This is the main function for the Interrupt Controller example. This\r
+* function is not included if the example is generated from the TestAppGen test\r
+* tool.\r
+*\r
+* @param       None.\r
+*\r
+* @return      XST_SUCCESS to indicate success, otherwise XST_FAILURE.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+#ifndef TESTAPP_GEN\r
+int main(void)\r
+{\r
+       int Status;\r
+\r
+       /*\r
+        *  Run the Intc example , specify the Device ID generated in\r
+        * xparameters.h.\r
+        */\r
+       Status = IntcSelfTestExample(INTC_DEVICE_ID);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+\r
+}\r
+#endif\r
+\r
+/*****************************************************************************/\r
+/**\r
+*\r
+* This function runs a self-test on the driver/device. This is a destructive\r
+* test. This function is an example of how to use the interrupt controller\r
+* driver component (XIntc) and the hardware device.  This function is designed\r
+* to work without any hardware devices to cause interrupts.  It may not return\r
+* if the interrupt controller is not properly connected to the processor in\r
+* either software or hardware.\r
+*\r
+* This function relies on the fact that the interrupt controller hardware\r
+* has come out of the reset state such that it will allow interrupts to be\r
+* simulated by the software.\r
+*\r
+* @param       DeviceId is device ID of the Interrupt Controller Device,\r
+*              typically XPAR_<INTC_instance>_DEVICE_ID value from\r
+*              xparameters.h.\r
+*\r
+* @return      XST_SUCCESS to indicate success, otherwise XST_FAILURE.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+int IntcSelfTestExample(u16 DeviceId)\r
+{\r
+       int Status;\r
+\r
+       /*\r
+        * Initialize the interrupt controller driver so that it is ready to use.\r
+        */\r
+       Status = XIntc_Initialize(&InterruptController, DeviceId);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+\r
+       /*\r
+        * Perform a self-test to ensure that the hardware was built correctly.\r
+        */\r
+       Status = XIntc_SelfTest(&InterruptController);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+\r
+}\r
+\r
+\r
+/*****************************************************************************/\r
+/**\r
+*\r
+* This function is used by the TestAppGen generated application to setup\r
+* the interrupt controller.\r
+*\r
+* @param       IntcInstancePtr is the reference to the Interrupt Controller\r
+*              instance.\r
+* @param       DeviceId is device ID of the Interrupt Controller Device,\r
+*              typically XPAR_<INTC_instance>_DEVICE_ID value from\r
+*              xparameters.h.\r
+*\r
+* @return      XST_SUCCESS to indicate success, otherwise XST_FAILURE.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+int IntcInterruptSetup(XIntc *IntcInstancePtr, u16 DeviceId)\r
+{\r
+\r
+       int Status;\r
+\r
+       /*\r
+        * Initialize the interrupt controller driver so that it is\r
+        * ready to use.\r
+        */\r
+       Status = XIntc_Initialize(IntcInstancePtr, DeviceId);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       /*\r
+        * Perform a self-test to ensure that the hardware was built  correctly.\r
+        */\r
+       Status = XIntc_SelfTest(IntcInstancePtr);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       /*\r
+        * Initialize the exception table.\r
+        */\r
+       Xil_ExceptionInit();\r
+\r
+       /*\r
+        * Register the interrupt controller handler with the exception table.\r
+        */\r
+       Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,\r
+                       (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,\r
+                       (void*) 0);\r
+\r
+       /*\r
+        * Enable exceptions.\r
+        */\r
+       Xil_ExceptionEnable();\r
+\r
+       /*\r
+        * Start the interrupt controller such that interrupts are enabled for\r
+        * all devices that cause interrupts.\r
+        */\r
+       Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+\r
+}\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xtmrctr_intr_example.c b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xtmrctr_intr_example.c
new file mode 100644 (file)
index 0000000..067a0ab
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xtmrctr_intr_example.c
@@ -0,0 +1,457 @@
+#define TESTAPP_GEN
+\r
+/* $Id: xtmrctr_intr_example.c,v 1.1.2.1 2010/12/01 07:53:56 svemula Exp $ */\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2002-2010 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+/*****************************************************************************/\r
+/**\r
+* @file  xtmrctr_intr_example.c\r
+*\r
+* This file contains a design example using the timer counter driver\r
+* (XTmCtr) and hardware device using interrupt mode.This example assumes\r
+* that the interrupt controller is also present as a part of the system\r
+*\r
+* This file can be used as a standalone example or by the TestAppGen utility\r
+* to include a test for Timer interrupts.\r
+*\r
+*\r
+*\r
+* <pre>\r
+* MODIFICATION HISTORY:\r
+*\r
+* Ver   Who  Date       Changes\r
+* ----- ---- -------- -----------------------------------------------\r
+* 1.00b jhl  02/13/02 First release\r
+* 1.00b sv   04/26/05 Minor changes to comply to Doxygen and coding guidelines\r
+* 1.00b sn   05/09/06 Modified to be used by TestAppGen to include test for\r
+*                    interrupts.\r
+* 2.00a ktn  10/30/09 Updated to use HAL API's and minor changes as per coding\r
+*                    guidelines.\r
+*</pre>\r
+******************************************************************************/\r
+\r
+/***************************** Include Files *********************************/\r
+\r
+#include "xparameters.h"\r
+#include "xtmrctr.h"\r
+#include "xintc.h"\r
+#include "xil_exception.h"\r
+\r
+/************************** Constant Definitions *****************************/\r
+#ifndef TESTAPP_GEN\r
+/*\r
+ * The following constants map to the XPAR parameters created in the\r
+ * xparameters.h file. They are only defined here such that a user can easily\r
+ * change all the needed parameters in one place.\r
+ */\r
+#define TMRCTR_DEVICE_ID       XPAR_TMRCTR_0_DEVICE_ID\r
+#define INTC_DEVICE_ID         XPAR_INTC_0_DEVICE_ID\r
+#define TMRCTR_INTERRUPT_ID    XPAR_INTC_0_TMRCTR_0_VEC_ID\r
+\r
+/*\r
+ * The following constant determines which timer counter of the device that is\r
+ * used for this example, there are currently 2 timer counters in a device\r
+ * and this example uses the first one, 0, the timer numbers are 0 based\r
+ */\r
+#define TIMER_CNTR_0    0\r
+\r
+#endif\r
+/*\r
+ * The following constant is used to set the reset value of the timer counter,\r
+ * making this number larger reduces the amount of time this example consumes\r
+ * because it is the value the timer counter is loaded with when it is started\r
+ */\r
+#define RESET_VALUE     0xF0000000\r
+\r
+\r
+\r
+/**************************** Type Definitions *******************************/\r
+\r
+\r
+/***************** Macros (Inline Functions) Definitions *********************/\r
+\r
+\r
+/************************** Function Prototypes ******************************/\r
+\r
+int TmrCtrIntrExample(XIntc* IntcInstancePtr,\r
+                       XTmrCtr* InstancePtr,\r
+                       u16 DeviceId,\r
+                       u16 IntrId,\r
+                       u8 TmrCtrNumber);\r
+\r
+static int TmrCtrSetupIntrSystem(XIntc* IntcInstancePtr,\r
+                               XTmrCtr* InstancePtr,\r
+                               u16 DeviceId,\r
+                               u16 IntrId,\r
+                               u8 TmrCtrNumber);\r
+\r
+void TimerCounterHandler(void *CallBackRef, u8 TmrCtrNumber);\r
+\r
+void TmrCtrDisableIntr(XIntc* IntcInstancePtr, u16 IntrId);\r
+\r
+/************************** Variable Definitions *****************************/\r
+#ifndef TESTAPP_GEN\r
+XIntc InterruptController;  /* The instance of the Interrupt Controller */\r
+\r
+XTmrCtr TimerCounterInst;   /* The instance of the Timer Counter */\r
+#endif\r
+/*\r
+ * The following variables are shared between non-interrupt processing and\r
+ * interrupt processing such that they must be global.\r
+ */\r
+volatile int TimerExpired;\r
+\r
+\r
+/*****************************************************************************/\r
+/**\r
+* This function is the main function of the Tmrctr example using Interrupts.\r
+*\r
+* @param       None.\r
+*\r
+* @return      XST_SUCCESS to indicate success, else XST_FAILURE to indicate a\r
+*              Failure.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+#ifndef TESTAPP_GEN\r
+int main(void)\r
+{\r
+\r
+       int Status;\r
+\r
+       /*\r
+        * Run the Timer Counter - Interrupt example.\r
+        */\r
+       Status = TmrCtrIntrExample(&InterruptController,\r
+                                 &TimerCounterInst,\r
+                                 TMRCTR_DEVICE_ID,\r
+                                 TMRCTR_INTERRUPT_ID,\r
+                                 TIMER_CNTR_0);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+\r
+}\r
+#endif\r
+\r
+/*****************************************************************************/\r
+/**\r
+* This function does a minimal test on the timer counter device and driver as a\r
+* design example.  The purpose of this function is to illustrate how to use the\r
+* XTmrCtr component.  It initializes a timer counter and then sets it up in\r
+* compare mode with auto reload such that a periodic interrupt is generated.\r
+*\r
+* This function uses interrupt driven mode of the timer counter.\r
+*\r
+* @param       IntcInstancePtr is a pointer to the Interrupt Controller\r
+*              driver Instance\r
+* @param       TmrCtrInstancePtr is a pointer to the XTmrCtr driver Instance\r
+* @param       DeviceId is the XPAR_<TmrCtr_instance>_DEVICE_ID value from\r
+*              xparameters.h\r
+* @param       IntrId is XPAR_<INTC_instance>_<TmrCtr_instance>_INTERRUPT_INTR\r
+*              value from xparameters.h\r
+* @param       TmrCtrNumber is the number of the timer to which this\r
+*              handler is associated with.\r
+*\r
+* @return      XST_SUCCESS if the Test is successful, otherwise XST_FAILURE\r
+*\r
+* @note                This function contains an infinite loop such that if interrupts\r
+*              are not working it may never return.\r
+*\r
+*****************************************************************************/\r
+int TmrCtrIntrExample(XIntc* IntcInstancePtr,\r
+                       XTmrCtr* TmrCtrInstancePtr,\r
+                       u16 DeviceId,\r
+                       u16 IntrId,\r
+                       u8 TmrCtrNumber)\r
+{\r
+       int Status;\r
+       int LastTimerExpired = 0;\r
+\r
+       /*\r
+        * Initialize the timer counter so that it's ready to use,\r
+        * specify the device ID that is generated in xparameters.h\r
+        */\r
+       Status = XTmrCtr_Initialize(TmrCtrInstancePtr, DeviceId);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       /*\r
+        * Perform a self-test to ensure that the hardware was built\r
+        * correctly, use the 1st timer in the device (0)\r
+        */\r
+       Status = XTmrCtr_SelfTest(TmrCtrInstancePtr, TmrCtrNumber);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       /*\r
+        * Connect the timer counter to the interrupt subsystem such that\r
+        * interrupts can occur.  This function is application specific.\r
+        */\r
+       Status = TmrCtrSetupIntrSystem(IntcInstancePtr,\r
+                                       TmrCtrInstancePtr,\r
+                                       DeviceId,\r
+                                       IntrId,\r
+                                       TmrCtrNumber);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       /*\r
+        * Setup the handler for the timer counter that will be called from the\r
+        * interrupt context when the timer expires, specify a pointer to the\r
+        * timer counter driver instance as the callback reference so the handler\r
+        * is able to access the instance data\r
+        */\r
+       XTmrCtr_SetHandler(TmrCtrInstancePtr, TimerCounterHandler,\r
+                                          TmrCtrInstancePtr);\r
+\r
+       /*\r
+        * Enable the interrupt of the timer counter so interrupts will occur\r
+        * and use auto reload mode such that the timer counter will reload\r
+        * itself automatically and continue repeatedly, without this option\r
+        * it would expire once only\r
+        */\r
+       XTmrCtr_SetOptions(TmrCtrInstancePtr, TmrCtrNumber,\r
+                               XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION);\r
+\r
+       /*\r
+        * Set a reset value for the timer counter such that it will expire\r
+        * eariler than letting it roll over from 0, the reset value is loaded\r
+        * into the timer counter when it is started\r
+        */\r
+       XTmrCtr_SetResetValue(TmrCtrInstancePtr, TmrCtrNumber, RESET_VALUE);\r
+\r
+       /*\r
+        * Start the timer counter such that it's incrementing by default,\r
+        * then wait for it to timeout a number of times\r
+        */\r
+       XTmrCtr_Start(TmrCtrInstancePtr, TmrCtrNumber);\r
+\r
+       while (1) {\r
+               /*\r
+                * Wait for the first timer counter to expire as indicated by the\r
+                * shared variable which the handler will increment\r
+                */\r
+               while (TimerExpired == LastTimerExpired) {\r
+               }\r
+               LastTimerExpired = TimerExpired;\r
+\r
+               /*\r
+                * If it has expired a number of times, then stop the timer counter\r
+                * and stop this example\r
+                */\r
+               if (TimerExpired == 3) {\r
+\r
+                       XTmrCtr_Stop(TmrCtrInstancePtr, TmrCtrNumber);\r
+                       break;\r
+               }\r
+       }\r
+\r
+       TmrCtrDisableIntr(IntcInstancePtr, DeviceId);\r
+       return XST_SUCCESS;\r
+}\r
+\r
+/*****************************************************************************/\r
+/**\r
+* This function is the handler which performs processing for the timer counter.\r
+* It is called from an interrupt context such that the amount of processing\r
+* performed should be minimized.  It is called when the timer counter expires\r
+* if interrupts are enabled.\r
+*\r
+* This handler provides an example of how to handle timer counter interrupts\r
+* but is application specific.\r
+*\r
+* @param       CallBackRef is a pointer to the callback function\r
+* @param       TmrCtrNumber is the number of the timer to which this\r
+*              handler is associated with.\r
+*\r
+* @return      None.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+void TimerCounterHandler(void *CallBackRef, u8 TmrCtrNumber)\r
+{\r
+       XTmrCtr *InstancePtr = (XTmrCtr *)CallBackRef;\r
+\r
+       /*\r
+        * Check if the timer counter has expired, checking is not necessary\r
+        * since that's the reason this function is executed, this just shows\r
+        * how the callback reference can be used as a pointer to the instance\r
+        * of the timer counter that expired, increment a shared variable so\r
+        * the main thread of execution can see the timer expired\r
+        */\r
+       if (XTmrCtr_IsExpired(InstancePtr, TmrCtrNumber)) {\r
+               TimerExpired++;\r
+               if(TimerExpired == 3) {\r
+                       XTmrCtr_SetOptions(InstancePtr, TmrCtrNumber, 0);\r
+               }\r
+       }\r
+}\r
+\r
+/*****************************************************************************/\r
+/**\r
+* This function setups the interrupt system such that interrupts can occur\r
+* for the timer counter. This function is application specific since the actual\r
+* system may or may not have an interrupt controller.  The timer counter could\r
+* be directly connected to a processor without an interrupt controller.  The\r
+* user should modify this function to fit the application.\r
+*\r
+* @param       IntcInstancePtr is a pointer to the Interrupt Controller\r
+*              driver Instance.\r
+* @param       TmrCtrInstancePtr is a pointer to the XTmrCtr driver Instance.\r
+* @param       DeviceId is the XPAR_<TmrCtr_instance>_DEVICE_ID value from\r
+*              xparameters.h.\r
+* @param       IntrId is XPAR_<INTC_instance>_<TmrCtr_instance>_VEC_ID\r
+*              value from xparameters.h.\r
+* @param       TmrCtrNumber is the number of the timer to which this\r
+*              handler is associated with.\r
+*\r
+* @return      XST_SUCCESS if the Test is successful, otherwise XST_FAILURE.\r
+*\r
+* @note                This function contains an infinite loop such that if interrupts\r
+*              are not working it may never return.\r
+*\r
+******************************************************************************/\r
+static int TmrCtrSetupIntrSystem(XIntc* IntcInstancePtr,\r
+                                XTmrCtr* TmrCtrInstancePtr,\r
+                                u16 DeviceId,\r
+                                u16 IntrId,\r
+                                u8 TmrCtrNumber)\r
+{\r
+        int Status;\r
+\r
+ #ifndef TESTAPP_GEN\r
+       /*\r
+        * Initialize the interrupt controller driver so that\r
+        * it's ready to use, specify the device ID that is generated in\r
+        * xparameters.h\r
+        */\r
+       Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+#endif\r
+       /*\r
+        * Connect a device driver handler that will be called when an interrupt\r
+        * for the device occurs, the device driver handler performs the specific\r
+        * interrupt processing for the device\r
+        */\r
+       Status = XIntc_Connect(IntcInstancePtr, IntrId,\r
+                               (XInterruptHandler)XTmrCtr_InterruptHandler,\r
+                               (void *)TmrCtrInstancePtr);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+#ifndef TESTAPP_GEN\r
+       /*\r
+        * Start the interrupt controller such that interrupts are enabled for\r
+        * all devices that cause interrupts, specific real mode so that\r
+        * the timer counter can cause interrupts thru the interrupt controller.\r
+        */\r
+       Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+#endif\r
+\r
+       /*\r
+        * Enable the interrupt for the timer counter\r
+        */\r
+       XIntc_Enable(IntcInstancePtr, IntrId);\r
+\r
+#ifndef TESTAPP_GEN\r
+       /*\r
+        * Initialize the exception table.\r
+        */\r
+       Xil_ExceptionInit();\r
+\r
+       /*\r
+        * Register the interrupt controller handler with the exception table.\r
+        */\r
+       Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,\r
+                                       (Xil_ExceptionHandler)\r
+                                       XIntc_InterruptHandler,\r
+                                       IntcInstancePtr);\r
+\r
+       /*\r
+        * Enable non-critical exceptions.\r
+        */\r
+       Xil_ExceptionEnable();\r
+\r
+#endif\r
+       return XST_SUCCESS;\r
+}\r
+\r
+\r
+/******************************************************************************/\r
+/**\r
+*\r
+* This function disables the interrupts for the Timer.\r
+*\r
+* @param       IntcInstancePtr is a reference to the Interrupt Controller\r
+*              driver Instance.\r
+* @param       IntrId is XPAR_<INTC_instance>_<Timer_instance>_VEC_ID\r
+*              value from xparameters.h.\r
+*\r
+* @return      None.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+void TmrCtrDisableIntr(XIntc* IntcInstancePtr, u16 IntrId)\r
+{\r
+       /*\r
+        * Disable the interrupt for the timer counter\r
+        */\r
+       XIntc_Disable(IntcInstancePtr, IntrId);\r
+\r
+       return;\r
+}\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xtmrctr_selftest_example.c b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xtmrctr_selftest_example.c
new file mode 100644 (file)
index 0000000..fe5ef01
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xtmrctr_selftest_example.c
@@ -0,0 +1,174 @@
+#define TESTAPP_GEN
+\r
+/* $Id: xtmrctr_selftest_example.c,v 1.1.2.1 2010/12/01 07:53:56 svemula Exp $ */\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2002-2010 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+/*****************************************************************************/\r
+/**\r
+* @file xtmrctr_selftest_example.c\r
+*\r
+* This file contains a example for  using the Timer Counter hardware and\r
+* driver\r
+*\r
+* @note\r
+*\r
+* None\r
+*\r
+* <pre>\r
+* MODIFICATION HISTORY:\r
+*\r
+* Ver   Who  Date       Changes\r
+* ----- ---- -------- -----------------------------------------------\r
+* 1.00a sv   04/25/05 Initial release for TestApp integration.\r
+* 2.00a ktn  11/26/09 Minor changes as per coding guidelines.\r
+* </pre>\r
+*\r
+*****************************************************************************/\r
+\r
+/***************************** Include Files ********************************/\r
+\r
+#include "xparameters.h"\r
+#include "xtmrctr.h"\r
+\r
+\r
+/************************** Constant Definitions ****************************/\r
+\r
+/*\r
+ * The following constants map to the XPAR parameters created in the\r
+ * xparameters.h file. They are defined here such that a user can easily\r
+ * change all the needed parameters in one place.\r
+ */\r
+#define TMRCTR_DEVICE_ID  XPAR_TMRCTR_0_DEVICE_ID\r
+\r
+/*\r
+ * This example only uses the 1st of the 2 timer counters contained in a\r
+ * single timer counter hardware device\r
+ */\r
+#define TIMER_COUNTER_0         0\r
+\r
+/**************************** Type Definitions ******************************/\r
+\r
+\r
+/***************** Macros (Inline Functions) Definitions *******************/\r
+\r
+\r
+/************************** Function Prototypes ****************************/\r
+\r
+int TmrCtrSelfTestExample(u16 DeviceId, u8 TmrCtrNumber);\r
+\r
+/************************** Variable Definitions **************************/\r
+\r
+XTmrCtr TimerCounter; /* The instance of the timer counter */\r
+\r
+\r
+/*****************************************************************************/\r
+/**\r
+* Main function to call the example. This function is not included if the\r
+* example is generated from the TestAppGen test tool.\r
+*\r
+* @param       None\r
+*\r
+* @return   XST_SUCCESS to indicate success, else XST_FAILURE to indicate\r
+*                 a Failure.\r
+*\r
+* @note         None\r
+*\r
+******************************************************************************/\r
+#ifndef TESTAPP_GEN\r
+int main(void)\r
+{\r
+       int Status;\r
+\r
+       Status = TmrCtrSelfTestExample(TMRCTR_DEVICE_ID, TIMER_COUNTER_0);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+}\r
+#endif\r
+\r
+\r
+/*****************************************************************************/\r
+/**\r
+*\r
+* This function does a minimal test on the TmrCtr device and driver as a\r
+* design example. The purpose of this function is to illustrate\r
+* how to use the XTmrCtr component.\r
+*\r
+*\r
+* @param       DeviceId is the XPAR_<TMRCTR_instance>_DEVICE_ID value from\r
+*              xparameters.h\r
+* @param       TmrCtrNumber is the timer counter of the device to operate on.\r
+*              Each device may contain multiple timer counters.\r
+*              The timer number is a zero based number with a range of\r
+*              0 - (XTC_DEVICE_TIMER_COUNT - 1).\r
+*\r
+* @return      XST_SUCCESS if successful, XST_FAILURE if unsuccessful\r
+*\r
+* @note                None\r
+*\r
+****************************************************************************/\r
+int TmrCtrSelfTestExample(u16 DeviceId, u8 TmrCtrNumber)\r
+{\r
+       int Status;\r
+       XTmrCtr *TmrCtrInstancePtr = &TimerCounter;\r
+\r
+       /*\r
+        * Initialize the TmrCtr driver so that it iss ready to use\r
+        */\r
+       Status = XTmrCtr_Initialize(TmrCtrInstancePtr, DeviceId);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       /*\r
+        * Perform a self-test to ensure that the hardware was built\r
+        * correctly, use the 1st timer in the device (0)\r
+        */\r
+       Status = XTmrCtr_SelfTest(TmrCtrInstancePtr, TmrCtrNumber);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+}\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xuartlite_selftest_example.c b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xuartlite_selftest_example.c
new file mode 100644 (file)
index 0000000..12a0aa0
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/src/xuartlite_selftest_example.c
@@ -0,0 +1,166 @@
+#define TESTAPP_GEN
+\r
+/* $Id: xuartlite_selftest_example.c,v 1.1.2.1 2009/11/24 05:14:25 svemula Exp $ */\r
+/******************************************************************************\r
+*\r
+* (c) Copyright 2005-2009 Xilinx, Inc. All rights reserved.\r
+*\r
+* This file contains confidential and proprietary information of Xilinx, Inc.\r
+* and is protected under U.S. and international copyright and other\r
+* intellectual property laws.\r
+*\r
+* DISCLAIMER\r
+* This disclaimer is not a license and does not grant any rights to the\r
+* materials distributed herewith. Except as otherwise provided in a valid\r
+* license issued to you by Xilinx, and to the maximum extent permitted by\r
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL\r
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,\r
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF\r
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;\r
+* and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+* negligence, or under any other theory of liability) for any loss or damage\r
+* of any kind or nature related to, arising under or in connection with these\r
+* materials, including for any direct, or any indirect, special, incidental,\r
+* or consequential loss or damage (including loss of data, profits, goodwill,\r
+* or any type of loss or damage suffered as a result of any action brought by\r
+* a third party) even if such damage or loss was reasonably foreseeable or\r
+* Xilinx had been advised of the possibility of the same.\r
+*\r
+* CRITICAL APPLICATIONS\r
+* Xilinx products are not designed or intended to be fail-safe, or for use in\r
+* any application requiring fail-safe performance, such as life-support or\r
+* safety devices or systems, Class III medical devices, nuclear facilities,\r
+* applications related to the deployment of airbags, or any other applications\r
+* that could lead to death, personal injury, or severe property or\r
+* environmental damage (individually and collectively, "Critical\r
+* Applications"). Customer assumes the sole risk and liability of any use of\r
+* Xilinx products in Critical Applications, subject only to applicable laws\r
+* and regulations governing limitations on product liability.\r
+*\r
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE\r
+* AT ALL TIMES.\r
+*\r
+******************************************************************************/\r
+/****************************************************************************/\r
+/**\r
+*\r
+* @file xuartlite_selftest_example.c\r
+*\r
+* This file contains a design example using the UartLite driver (XUartLite) and\r
+* hardware device.\r
+*\r
+* @note\r
+*\r
+* None\r
+*\r
+* MODIFICATION HISTORY:\r
+* <pre>\r
+* Ver   Who  Date       Changes\r
+* ----- ---- -------- -----------------------------------------------\r
+* 1.00a ecm  01/25/04 First Release.\r
+* 1.00a sv   06/13/05 Minor changes to comply to Doxygen and Coding guidelines\r
+* 2.00a ktn  10/20/09 Minor changes as per coding guidelines.\r
+* </pre>\r
+******************************************************************************/\r
+\r
+/***************************** Include Files *********************************/\r
+\r
+#include "xparameters.h"\r
+#include "xuartlite.h"\r
+\r
+/************************** Constant Definitions *****************************/\r
+\r
+/*\r
+ * The following constants map to the XPAR parameters created in the\r
+ * xparameters.h file. They are defined here such that a user can easily\r
+ * change all the needed parameters in one place.\r
+ */\r
+#define UARTLITE_DEVICE_ID             XPAR_UARTLITE_0_DEVICE_ID\r
+\r
+\r
+/**************************** Type Definitions *******************************/\r
+\r
+\r
+/***************** Macros (Inline Functions) Definitions *********************/\r
+\r
+\r
+/************************** Function Prototypes ******************************/\r
+\r
+int UartLiteSelfTestExample(u16 DeviceId);\r
+\r
+/************************** Variable Definitions *****************************/\r
+\r
+XUartLite UartLite;             /* Instance of the UartLite device */\r
+\r
+/*****************************************************************************/\r
+/**\r
+*\r
+* Main function to call the example. This function is not included if the\r
+* example is generated from the TestAppGen test tool.\r
+*\r
+* @param       None.\r
+*\r
+* @return      XST_SUCCESS if successful, otherwise XST_FAILURE.\r
+*\r
+* @note                None.\r
+*\r
+******************************************************************************/\r
+#ifndef TESTAPP_GEN\r
+int main(void)\r
+{\r
+       int Status;\r
+\r
+       /*\r
+        * Run the UartLite self test example, specify the Device ID that is\r
+        * generated in xparameters.h\r
+        */\r
+       Status = UartLiteSelfTestExample(UARTLITE_DEVICE_ID);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+\r
+}\r
+#endif\r
+\r
+/*****************************************************************************/\r
+/**\r
+*\r
+* This function does a minimal test on the UartLite device and driver as a\r
+* design example. The purpose of this function is to illustrate\r
+* how to use the XUartLite component.\r
+*\r
+*\r
+* @param       DeviceId is the XPAR_<uartlite_instance>_DEVICE_ID value from\r
+*              xparameters.h.\r
+*\r
+* @return      XST_SUCCESS if successful, otherwise XST_FAILURE.\r
+*\r
+* @note                None.\r
+*\r
+****************************************************************************/\r
+int UartLiteSelfTestExample(u16 DeviceId)\r
+{\r
+       int Status;\r
+\r
+       /*\r
+        * Initialize the UartLite driver so that it is ready to use.\r
+        */\r
+       Status = XUartLite_Initialize(&UartLite, DeviceId);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       /*\r
+        * Perform a self-test to ensure that the hardware was built correctly.\r
+        */\r
+       Status = XUartLite_SelfTest(&UartLite);\r
+       if (Status != XST_SUCCESS) {\r
+               return XST_FAILURE;\r
+       }\r
+\r
+       return XST_SUCCESS;\r
+}\r
+\r
+\r