Provide each Risc V task with an initial mstatus register value.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2593 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
index ed2c29885fc86fb621290f9067d0bbe6e191994a..2a0686b8019768fd0bef4de5c00776324f8f8c0c 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
@@ -76,6 +76,8 @@ volatile uint32_t ulx = 0;
  */\r
 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
 {\r
+uint32_t mstatus;\r
+const uint32_t ulMPIE_Bit = 0x80, ulMPP_Bits = 0x1800;\r
        /*\r
           X1 to X31 integer registers for the 'I' profile, X1 to X15 for the 'E' profile.\r
 \r
@@ -94,10 +96,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
                x28-31          t3-6                    Temporaries                                     Caller\r
        */\r
 \r
-       /* To ensure alignment. */\r
-       //_RB_  pxTopOfStack--;\r
-       //_RB_  pxTopOfStack--;\r
-       //_RB_pxTopOfStack--;\r
+       /* Start task with interrupt enabled. */\r
+       __asm volatile ("csrr %0, mstatus" : "=r"(mstatus));\r
+       mstatus |= ulMPIE_Bit | ulMPP_Bits;\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = mstatus;\r
 \r
        /* Numbers correspond to the x register number. */\r
        pxTopOfStack--;\r

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
index f376b61e3ab3cc66fc6efc13a55cd1110b35e080..4a128cb32e58be7b52bd253228202daf53fd0737 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
@@ -36,7 +36,7 @@
     #error Assembler has not defined __riscv_xlen\r
 #endif\r
 \r
-#define CONTEXT_SIZE ( 28 * WORD_SIZE )\r
+#define CONTEXT_SIZE ( 30 * WORD_SIZE )\r
 \r
 .global xPortStartFirstTask\r
 .global vPortTrapHandler\r
@@ -48,41 +48,40 @@
 .align 8\r
 xPortStartFirstTask:\r
 \r
-    lw  sp, pxCurrentTCB            /* Load pxCurrentTCB. */\r
-    lw  sp, 0( sp )                 /* Read sp from first TCB member. */\r
-\r
-    lw  x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */\r
-    lw  x5, 2 * WORD_SIZE( sp )     /* t0 */\r
-    lw  x6, 3 * WORD_SIZE( sp )     /* t1 */\r
-    lw  x7, 4 * WORD_SIZE( sp )     /* t2 */\r
-    lw  x8, 5 * WORD_SIZE( sp )     /* s0/fp */\r
-    lw  x9, 6 * WORD_SIZE( sp )     /* s1 */\r
-    lw  x10, 7 * WORD_SIZE( sp )    /* a0 */\r
-    lw  x11, 8 * WORD_SIZE( sp )    /* a1 */\r
-    lw  x12, 9 * WORD_SIZE( sp )    /* a2 */\r
-    lw  x13, 10 * WORD_SIZE( sp )   /* a3 */\r
-    lw  x14, 11 * WORD_SIZE( sp )   /* a4 */\r
-    lw  x15, 12 * WORD_SIZE( sp )   /* a5 */\r
-    lw  x16, 13 * WORD_SIZE( sp )   /* a6 */\r
-    lw  x17, 14 * WORD_SIZE( sp )   /* a7 */\r
-    lw  x18, 15 * WORD_SIZE( sp )   /* s2 */\r
-    lw  x19, 16 * WORD_SIZE( sp )   /* s3 */\r
-    lw  x20, 17 * WORD_SIZE( sp )   /* s4 */\r
-    lw  x21, 18 * WORD_SIZE( sp )   /* s5 */\r
-    lw  x22, 19 * WORD_SIZE( sp )   /* s6 */\r
-    lw  x23, 20 * WORD_SIZE( sp )   /* s7 */\r
-    lw  x24, 21 * WORD_SIZE( sp )   /* s8 */\r
-    lw  x25, 22 * WORD_SIZE( sp )   /* s9 */\r
-    lw  x26, 23 * WORD_SIZE( sp )   /* s10 */\r
-    lw  x27, 24 * WORD_SIZE( sp )   /* s11 */\r
-    lw  x28, 25 * WORD_SIZE( sp )   /* t3 */\r
-    lw  x29, 26 * WORD_SIZE( sp )   /* t4 */\r
-    lw  x30, 27 * WORD_SIZE( sp )   /* t5 */\r
-    lw  x31, 28 * WORD_SIZE( sp )   /* t6 */\r
-    addi    sp, sp, CONTEXT_SIZE\r
-    csrs    mstatus, 8              /* Enable machine interrupts. */\r
-    csrs    mie, 8                  /* Enable soft interrupt. */\r
-    ret\r
+       lw  sp, pxCurrentTCB            /* Load pxCurrentTCB. */\r
+       lw  sp, 0( sp )                 /* Read sp from first TCB member. */\r
+\r
+       lw  x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */\r
+       lw  x5, 2 * WORD_SIZE( sp )     /* t0 */\r
+       lw  x6, 3 * WORD_SIZE( sp )     /* t1 */\r
+       lw  x7, 4 * WORD_SIZE( sp )     /* t2 */\r
+       lw  x8, 5 * WORD_SIZE( sp )     /* s0/fp */\r
+       lw  x9, 6 * WORD_SIZE( sp )     /* s1 */\r
+       lw  x10, 7 * WORD_SIZE( sp )    /* a0 */\r
+       lw  x11, 8 * WORD_SIZE( sp )    /* a1 */\r
+       lw  x12, 9 * WORD_SIZE( sp )    /* a2 */\r
+       lw  x13, 10 * WORD_SIZE( sp )   /* a3 */\r
+       lw  x14, 11 * WORD_SIZE( sp )   /* a4 */\r
+       lw  x15, 12 * WORD_SIZE( sp )   /* a5 */\r
+       lw  x16, 13 * WORD_SIZE( sp )   /* a6 */\r
+       lw  x17, 14 * WORD_SIZE( sp )   /* a7 */\r
+       lw  x18, 15 * WORD_SIZE( sp )   /* s2 */\r
+       lw  x19, 16 * WORD_SIZE( sp )   /* s3 */\r
+       lw  x20, 17 * WORD_SIZE( sp )   /* s4 */\r
+       lw  x21, 18 * WORD_SIZE( sp )   /* s5 */\r
+       lw  x22, 19 * WORD_SIZE( sp )   /* s6 */\r
+       lw  x23, 20 * WORD_SIZE( sp )   /* s7 */\r
+       lw  x24, 21 * WORD_SIZE( sp )   /* s8 */\r
+       lw  x25, 22 * WORD_SIZE( sp )   /* s9 */\r
+       lw  x26, 23 * WORD_SIZE( sp )   /* s10 */\r
+       lw  x27, 24 * WORD_SIZE( sp )   /* s11 */\r
+       lw  x28, 25 * WORD_SIZE( sp )   /* t3 */\r
+       lw  x29, 26 * WORD_SIZE( sp )   /* t4 */\r
+       lw  x30, 27 * WORD_SIZE( sp )   /* t5 */\r
+       lw  x31, 28 * WORD_SIZE( sp )   /* t6 */\r
+       addi    sp, sp, CONTEXT_SIZE\r
+       csrs    mstatus, 8              /* Enable machine interrupts. */\r
+       ret\r
 \r
 /*-----------------------------------------------------------*/\r
 \r
@@ -118,59 +117,63 @@ vPortTrapHandler:
        sw x30, 27 * WORD_SIZE( sp )\r
        sw x31, 28 * WORD_SIZE( sp )\r
 \r
-    lw  t0, pxCurrentTCB            /* Load pxCurrentTCB. */\r
-    sw  sp, 0( t0 )                 /* Write sp from first TCB member. */\r
+       csrr t0, mstatus                /* Required for MPIE bit. */\r
+       sw t0, 29 * WORD_SIZE( sp )\r
+\r
+       lw  t0, pxCurrentTCB            /* Load pxCurrentTCB. */\r
+       sw  sp, 0( t0 )                 /* Write sp to first TCB member. */\r
 \r
        csrr a0, mcause\r
        csrr a1, mepc\r
        mv a2, sp\r
+/*_RB_ Does stack need aligning here? */\r
        jal handle_trap\r
        csrw mepc, a0\r
        /* Save exception return address. */\r
        sw a0, 0( sp )\r
 \r
 \r
-       # Remain in M-mode after mret\r
-       li t0, 0x00001800 /* MSTATUS MPP */\r
-       csrs mstatus, t0\r
-\r
-    lw  sp, pxCurrentTCB            /* Load pxCurrentTCB. */\r
-    lw  sp, 0( sp )                 /* Read sp from first TCB member. */\r
-\r
-    /* Load mret with the address of the next task. */\r
-    lw t0, 0( sp )\r
-    csrw mepc, t0\r
-\r
-    lw  x1, 1 * WORD_SIZE( sp )\r
-    lw  x5, 2 * WORD_SIZE( sp )     /* t0 */\r
-    lw  x6, 3 * WORD_SIZE( sp )     /* t1 */\r
-    lw  x7, 4 * WORD_SIZE( sp )     /* t2 */\r
-    lw  x8, 5 * WORD_SIZE( sp )     /* s0/fp */\r
-    lw  x9, 6 * WORD_SIZE( sp )     /* s1 */\r
-    lw  x10, 7 * WORD_SIZE( sp )    /* a0 */\r
-    lw  x11, 8 * WORD_SIZE( sp )    /* a1 */\r
-    lw  x12, 9 * WORD_SIZE( sp )    /* a2 */\r
-    lw  x13, 10 * WORD_SIZE( sp )   /* a3 */\r
-    lw  x14, 11 * WORD_SIZE( sp )   /* a4 */\r
-    lw  x15, 12 * WORD_SIZE( sp )   /* a5 */\r
-    lw  x16, 13 * WORD_SIZE( sp )   /* a6 */\r
-    lw  x17, 14 * WORD_SIZE( sp )   /* a7 */\r
-    lw  x18, 15 * WORD_SIZE( sp )   /* s2 */\r
-    lw  x19, 16 * WORD_SIZE( sp )   /* s3 */\r
-    lw  x20, 17 * WORD_SIZE( sp )   /* s4 */\r
-    lw  x21, 18 * WORD_SIZE( sp )   /* s5 */\r
-    lw  x22, 19 * WORD_SIZE( sp )   /* s6 */\r
-    lw  x23, 20 * WORD_SIZE( sp )   /* s7 */\r
-    lw  x24, 21 * WORD_SIZE( sp )   /* s8 */\r
-    lw  x25, 22 * WORD_SIZE( sp )   /* s9 */\r
-    lw  x26, 23 * WORD_SIZE( sp )   /* s10 */\r
-    lw  x27, 24 * WORD_SIZE( sp )   /* s11 */\r
-    lw  x28, 25 * WORD_SIZE( sp )   /* t3 */\r
-    lw  x29, 26 * WORD_SIZE( sp )   /* t4 */\r
-    lw  x30, 27 * WORD_SIZE( sp )   /* t5 */\r
-    lw  x31, 28 * WORD_SIZE( sp )   /* t6 */\r
-    addi    sp, sp, CONTEXT_SIZE\r
-\r
-    mret\r
+       lw  sp, pxCurrentTCB            /* Load pxCurrentTCB. */\r
+       lw  sp, 0( sp )                 /* Read sp from first TCB member. */\r
+\r
+       /* Load mret with the address of the next task. */\r
+       lw t0, 0( sp )\r
+       csrw mepc, t0\r
+\r
+       /* Load mstatus with the interrupt enable bits used by the task. */\r
+       lw  t0, 29 * WORD_SIZE( sp )\r
+       csrw mstatus, t0                /* Required for MPIE bit. */\r
+\r
+       lw  x1, 1 * WORD_SIZE( sp )\r
+       lw  x5, 2 * WORD_SIZE( sp )     /* t0 */\r
+       lw  x6, 3 * WORD_SIZE( sp )     /* t1 */\r
+       lw  x7, 4 * WORD_SIZE( sp )     /* t2 */\r
+       lw  x8, 5 * WORD_SIZE( sp )     /* s0/fp */\r
+       lw  x9, 6 * WORD_SIZE( sp )     /* s1 */\r
+       lw  x10, 7 * WORD_SIZE( sp )    /* a0 */\r
+       lw  x11, 8 * WORD_SIZE( sp )    /* a1 */\r
+       lw  x12, 9 * WORD_SIZE( sp )    /* a2 */\r
+       lw  x13, 10 * WORD_SIZE( sp )   /* a3 */\r
+       lw  x14, 11 * WORD_SIZE( sp )   /* a4 */\r
+       lw  x15, 12 * WORD_SIZE( sp )   /* a5 */\r
+       lw  x16, 13 * WORD_SIZE( sp )   /* a6 */\r
+       lw  x17, 14 * WORD_SIZE( sp )   /* a7 */\r
+       lw  x18, 15 * WORD_SIZE( sp )   /* s2 */\r
+       lw  x19, 16 * WORD_SIZE( sp )   /* s3 */\r
+       lw  x20, 17 * WORD_SIZE( sp )   /* s4 */\r
+       lw  x21, 18 * WORD_SIZE( sp )   /* s5 */\r
+       lw  x22, 19 * WORD_SIZE( sp )   /* s6 */\r
+       lw  x23, 20 * WORD_SIZE( sp )   /* s7 */\r
+       lw  x24, 21 * WORD_SIZE( sp )   /* s8 */\r
+       lw  x25, 22 * WORD_SIZE( sp )   /* s9 */\r
+       lw  x26, 23 * WORD_SIZE( sp )   /* s10 */\r
+       lw  x27, 24 * WORD_SIZE( sp )   /* s11 */\r
+       lw  x28, 25 * WORD_SIZE( sp )   /* t3 */\r
+       lw  x29, 26 * WORD_SIZE( sp )   /* t4 */\r
+       lw  x30, 27 * WORD_SIZE( sp )   /* t5 */\r
+       lw  x31, 28 * WORD_SIZE( sp )   /* t6 */\r
+       addi    sp, sp, CONTEXT_SIZE\r
+\r
+       mret\r
 \r
 \r