\r
static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
{\r
-const char *const pcHeader = ( int8_t * ) "Task State Priority Stack #\r\n************************************************\r\n";\r
+const char *const pcHeader = "Task State Priority Stack #\r\n************************************************\r\n";\r
\r
/* Remove compile time warnings about unused parameters, and check the\r
write buffer is not NULL. NOTE - for simplicity, this example assumes the\r
\r
/* Generate a table of task stats. */\r
strcpy( ( char * ) pcWriteBuffer, pcHeader );\r
- vTaskList( pcWriteBuffer + strlen( pcHeader ) );\r
+ vTaskList( ( char * ) pcWriteBuffer + strlen( pcHeader ) );\r
\r
/* There is no more data to return after this single string, so return\r
pdFALSE. */\r
\r
static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
{\r
-const char * const pcHeader = ( int8_t * ) "Task Abs Time % Time\r\n****************************************\r\n";\r
+const char * const pcHeader = "Task Abs Time % Time\r\n****************************************\r\n";\r
\r
/* Remove compile time warnings about unused parameters, and check the\r
write buffer is not NULL. NOTE - for simplicity, this example assumes the\r
--- /dev/null
+\r
+#ifndef STDINT_INC\r
+#define STDINT_INC\r
+\r
+/* This file will get picked up when stdint.h does not appear in the default\r
+include path (which it doesn't seem to be - even though the file exists). */\r
+\r
+typedef signed char int8_t;\r
+typedef unsigned char uint8_t;\r
+typedef short int16_t;\r
+typedef unsigned short uint16_t;\r
+typedef long int32_t;\r
+typedef unsigned long uint32_t;\r
+\r
+#endif /* STDINT_INC */\r
/*\r
- FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. \r
+ FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
All rights reserved\r
\r
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
***************************************************************************\r
\r
\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
license and Real Time Engineers Ltd. contact details.\r
\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
fully thread aware and reentrant UDP/IP stack.\r
\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
- Integrity Systems, who sell the code with commercial support, \r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
indemnification and middleware, under the OpenRTOS brand.\r
- \r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
- engineered and independently SIL3 certified version for use in safety and \r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
mission critical applications that require provable dependability.\r
*/\r
\r
#define INCLUDE_xTaskGetIdleTaskHandle 0\r
#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0\r
\r
+/* Tick interrupt vector - this must match the INTIT_vect definition contained\r
+in the ior5fnnnn.h header file included at the top of this file (the value is\r
+dependent on the hardware being used. */\r
+#define configTICK_VECTOR 56\r
\r
/******************************************************************************\r
* PORT SPECIFIC CONFIGURATION OPTIONS\r
/*\r
- FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. \r
+ FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
All rights reserved\r
\r
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
***************************************************************************\r
\r
\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
license and Real Time Engineers Ltd. contact details.\r
\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
fully thread aware and reentrant UDP/IP stack.\r
\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
- Integrity Systems, who sell the code with commercial support, \r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
indemnification and middleware, under the OpenRTOS brand.\r
- \r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
- engineered and independently SIL3 certified version for use in safety and \r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
mission critical applications that require provable dependability.\r
*/\r
\r
/* This variable is incremented each time the demo timer expires. */\r
static volatile unsigned long ulDemoSoftwareTimerCounter = 0UL;\r
\r
-/* RL78/G13 Option Byte Definition. Watchdog disabled, LVI enabled, OCD interface\r
+/* RL78 Option Byte Definition. Watchdog disabled, LVI enabled, OCD interface\r
enabled. */\r
__root __far const unsigned char OptionByte[] @ 0x00C0 =\r
{\r
- WATCHDOG_DISABLED, LVI_ENABLED, RESERVED_FF, OCD_ENABLED\r
+ 0x6eU, 0xffU, 0xe8U, 0x85U\r
};\r
\r
/* Security byte definition */\r
\r
/* Create the RegTest tasks as described at the top of this file. */\r
xTaskCreate( vRegTest1, "Reg1", configMINIMAL_STACK_SIZE, NULL, 0, NULL );\r
- xTaskCreate( vRegTest2, "Reg2", configMINIMAL_STACK_SIZE, NULL, 0, NULL ); \r
+ xTaskCreate( vRegTest2, "Reg2", configMINIMAL_STACK_SIZE, NULL, 0, NULL );\r
\r
/* Create the software timer that performs the 'check' functionality,\r
as described at the top of this file. */\r
( void * ) 0, /* The ID is not used, so can be set to anything. */\r
prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
);\r
- \r
+\r
/* Create the software timer that just increments a variable for demo\r
purposes. */\r
xDemoTimer = xTimerCreate( "DemoTimer",/* A text name, purely to help debugging. */\r
( void * ) 0, /* The ID is not used, so can be set to anything. */\r
prvDemoTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
);\r
- \r
+\r
/* Start both the check timer and the demo timer. The timers won't actually\r
start until the scheduler is started. */\r
xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
xTimerStart( xDemoTimer, mainDONT_BLOCK );\r
- \r
+\r
/* Finally start the scheduler running. */\r
vTaskStartScheduler();\r
\r
{\r
xErrorStatus = pdFAIL;\r
}\r
- \r
+\r
if( xArePollingQueuesStillRunning() != pdTRUE )\r
{\r
xErrorStatus = pdFAIL;\r
}\r
- \r
+\r
if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
{\r
xErrorStatus = pdFAIL;\r
{\r
xErrorStatus = pdFAIL;\r
}\r
- \r
+\r
/* Ensure that the demo software timer has expired\r
mainDEMO_TIMER_INCREMENTS_PER_CHECK_TIMER_TIMEOUT times in between\r
each call of this function. A critical section is not required to access\r
{\r
ulDemoSoftwareTimerCounter = 0UL;\r
}\r
- \r
+\r
if( ( xErrorStatus == pdFAIL ) && ( xChangedTimerPeriodAlready == pdFALSE ) )\r
{\r
/* An error has occurred, but the timer's period has not yet been changed,\r
timer's period means the LED will toggle at a faster rate, giving a\r
visible indication that something has gone wrong. */\r
xChangedTimerPeriodAlready = pdTRUE;\r
- \r
+\r
/* This call to xTimerChangePeriod() uses a zero block time. Functions\r
called from inside of a timer callback function must *never* attempt to\r
block. */\r
xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
}\r
- \r
+\r
/* Toggle the LED. The toggle rate will depend on whether or not an error\r
has been found in any tasks. */\r
mainLED_0 = !mainLED_0;\r
/* Set fMX */\r
CMC = 0x00;\r
MSTOP = 1U;\r
- \r
+\r
/* Set fMAIN */\r
MCM0 = 0U;\r
- \r
+\r
/* Set fSUB */\r
XTSTOP = 1U;\r
OSMC = 0x10;\r
- \r
+\r
/* Set fCLK */\r
CSS = 0U;\r
- \r
+\r
/* Set fIH */\r
HIOSTOP = 0U;\r
}\r
#else\r
{\r
- unsigned char ucTempStabset, ucTempStabWait; \r
+ unsigned char ucTempStabset, ucTempStabWait;\r
\r
/* Set fMX */\r
CMC = 0x41;\r
OSTS = 0x07;\r
MSTOP = 0U;\r
ucTempStabset = 0xFF;\r
- \r
+\r
do\r
{\r
ucTempStabWait = OSTC;\r
ucTempStabWait &= ucTempStabset;\r
}\r
while( ucTempStabWait != ucTempStabset );\r
- \r
+\r
/* Set fMAIN */\r
MCM0 = 1U;\r
- \r
+\r
/* Set fSUB */\r
XTSTOP = 1U;\r
OSMC = 0x10;\r
- \r
+\r
/* Set fCLK */\r
CSS = 0U;\r
- \r
+\r
/* Set fIH */\r
HIOSTOP = 0U;\r
}\r
#endif /* configCLOCK_SOURCE == 1 */\r
- \r
+\r
/* LED port initialization - set port register. */\r
P7 &= 0x7F;\r
- \r
+\r
/* Set port mode register. */\r
PM7 &= 0x7F;\r
- \r
+\r
/* Switch pin initialization - enable pull-up resistor. */\r
PU12_bit.no0 = 1;\r
\r
management options. If there is a lot of heap memory free then the\r
configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up\r
RAM. */\r
- xFreeHeapSpace = xPortGetFreeHeapSize(); \r
+ xFreeHeapSpace = xPortGetFreeHeapSize();\r
}\r
\r
--- /dev/null
+\r
+#ifndef STDINT_INC\r
+#define STDINT_INC\r
+\r
+/* This file will get picked up when stdint.h does not appear in the default\r
+include path (which it doesn't seem to be - even though the file exists). */\r
+\r
+typedef signed char int8_t;\r
+typedef unsigned char uint8_t;\r
+typedef short int16_t;\r
+typedef unsigned short uint16_t;\r
+typedef long int32_t;\r
+typedef unsigned long uint32_t;\r
+\r
+#endif /* STDINT_INC */\r
--- /dev/null
+\r
+#ifndef STDINT_INC\r
+#define STDINT_INC\r
+\r
+/* This file will get picked up when stdint.h does not appear in the default\r
+include path (which it doesn't seem to be - even though the file exists). */\r
+\r
+typedef signed char int8_t;\r
+typedef unsigned char uint8_t;\r
+typedef short int16_t;\r
+typedef unsigned short uint16_t;\r
+typedef long int32_t;\r
+typedef unsigned long uint32_t;\r
+\r
+#endif /* STDINT_INC */\r
#ifndef _TYPE_DEFINE_H_\r
#define _TYPE_DEFINE_H_\r
\r
+#include <stdint.h>\r
\r
typedef unsigned char Bool;\r
\r
\r
typedef signed char char8_t;\r
typedef unsigned char uchar8_t;\r
-typedef signed char int8_t;\r
-typedef unsigned char uint8_t;\r
typedef signed short short16_t;\r
typedef unsigned short ushort16_t;\r
-typedef signed long int32_t;\r
-typedef unsigned long uint32_t;\r
typedef signed long long32_t;\r
typedef unsigned long ulong32_t;\r
\r
--- /dev/null
+\r
+#ifndef STDINT_INC\r
+#define STDINT_INC\r
+\r
+/* This file will get picked up when stdint.h does not appear in the default\r
+include path (which it doesn't seem to be - even though the file exists). */\r
+\r
+typedef signed char int8_t;\r
+typedef unsigned char uint8_t;\r
+typedef short int16_t;\r
+typedef unsigned short uint16_t;\r
+typedef long int32_t;\r
+typedef unsigned long uint32_t;\r
+\r
+#endif /* STDINT_INC */\r
// based on linux-header by Russel Nelson\r
\r
#define PP_ChipID 0x0000 // offset 0h -> Corp-ID\r
- \r
+\r
// offset 2h -> Model/Product Number\r
#define LED_RED (1<<8)\r
#define LED_GREEN (1<<10)\r
\r
GPIO_IOCLR = 0xf << 4; // Put address on bus\r
GPIO_IOSET = addr << 4;\r
- \r
+\r
GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus\r
GPIO_IOSET = data << 16;\r
\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOCLR = IOW; // Toggle IOW-signal\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOSET = IOW;\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
\r
GPIO_IOCLR = 0xf << 4;\r
GPIO_IOSET = ((addr | 1) << 4); // And put next address on bus\r
GPIO_IOCLR = 0xff << 16; // Write high order byte to data bus\r
GPIO_IOSET = data >> 8 << 16;\r
\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOCLR = IOW; // Toggle IOW-signal\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOSET = IOW;\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
}\r
\r
// Reads a word in little-endian byte order from a specified port-address\r
GPIO_IOCLR = 0xf << 4; // Put address on bus\r
GPIO_IOSET = addr << 4;\r
\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOCLR = IOR; // IOR-signal low\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
value = (GPIO_IOPIN >> 16) & 0xff; // get low order byte from data bus\r
GPIO_IOSET = IOR;\r
\r
GPIO_IOSET = 1 << 4; // IOR high and put next address on bus\r
\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOCLR = IOR; // IOR-signal low\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
value |= ((GPIO_IOPIN >> 8) & 0xff00); // get high order byte from data bus\r
GPIO_IOSET = IOR; // IOR-signal low\r
- \r
+\r
return value;\r
}\r
\r
GPIO_IOCLR = 0xf << 4; // Put address on bus\r
GPIO_IOSET = (addr+1) << 4;\r
\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOCLR = IOR; // IOR-signal low\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
value = ((GPIO_IOPIN >> 8) & 0xff00); // get high order byte from data bus\r
GPIO_IOSET = IOR; // IOR-signal high\r
\r
GPIO_IOCLR = 1 << 4; // Put low address on bus\r
\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOCLR = IOR; // IOR-signal low\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
value |= (GPIO_IOPIN >> 16) & 0xff; // get low order byte from data bus\r
GPIO_IOSET = IOR;\r
\r
GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus\r
GPIO_IOSET = uip_buf[u] << 16; // write low order byte to data bus\r
\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOCLR = IOW; // Toggle IOW-signal\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOSET = IOW;\r
\r
GPIO_IOCLR = 0xf << 4; // Put address on bus\r
GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus\r
GPIO_IOSET = uip_buf[u+1] << 16; // write low order byte to data bus\r
\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOCLR = IOW; // Toggle IOW-signal\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOSET = IOW;\r
}\r
\r
GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus\r
GPIO_IOSET = uip_appdata[u] << 16; // write low order byte to data bus\r
\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOCLR = IOW; // Toggle IOW-signal\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOSET = IOW;\r
\r
GPIO_IOCLR = 0xf << 4; // Put address on bus\r
GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus\r
GPIO_IOSET = uip_appdata[u+1] << 16; // write low order byte to data bus\r
\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOCLR = IOW; // Toggle IOW-signal\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOSET = IOW;\r
}\r
\r
GPIO_IODIR &= ~(0xff << 16);\r
\r
GPIO_IOCLR = 0xf << 4; // put address on bus\r
- GPIO_IOSET = RX_FRAME_PORT << 4; \r
+ GPIO_IOSET = RX_FRAME_PORT << 4;\r
\r
// Read bytes into uip_buf\r
u = 0;\r
\r
GPIO_IOCLR = IOR; // IOR-signal low\r
uip_buf[u] = GPIO_IOPIN >> 16; // get high order byte from data bus\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
GPIO_IOSET = IOR; // IOR-signal high\r
\r
GPIO_IOSET = 1 << 4; // put address on bus\r
\r
GPIO_IOCLR = IOR; // IOR-signal low\r
- asm volatile ( "NOP" );\r
+ __asm volatile ( "NOP" );\r
uip_buf[u+1] = GPIO_IOPIN >> 16; // get high order byte from data bus\r
GPIO_IOSET = IOR; // IOR-signal high\r
u += 2;\r
#define xTaskStatusType TaskStatus_t\r
#define xTimerHandle TimerHandle_t\r
#define xCoRoutineHandle CoRoutineHandle_t\r
+#define xListItem ListItem_t\r
+#define xList List_t\r
+#define xTimeOutType TimeOut_t\r
\r
#endif /* INC_FREERTOS_H */\r
\r
/*\r
- FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. \r
+ FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
All rights reserved\r
\r
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
/* ISR to handle manual context switches (from a call to taskYIELD()). */\r
void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));\r
\r
-/* \r
+/*\r
* The scheduler can only be started from ARM mode, hence the inclusion of this\r
* function here.\r
*/\r
/*\r
* Called by portYIELD() or taskYIELD() to manually force a context switch.\r
*\r
- * When a context switch is performed from the task level the saved task \r
+ * When a context switch is performed from the task level the saved task\r
* context is made to look as if it occurred from within the tick ISR. This\r
* way the same restore context function can be used when restoring the context\r
* saved from the ISR or that saved from a call to vPortYieldProcessor.\r
*/\r
void vPortYieldProcessor( void )\r
{\r
- /* Within an IRQ ISR the link register has an offset from the true return \r
- address, but an SWI ISR does not. Add the offset manually so the same \r
+ /* Within an IRQ ISR the link register has an offset from the true return\r
+ address, but an SWI ISR does not. Add the offset manually so the same\r
ISR return code can be used in both cases. */\r
- asm volatile ( "ADD LR, LR, #4" );\r
+ __asm volatile ( "ADD LR, LR, #4" );\r
\r
/* Perform the context switch. First save the context of the current task. */\r
portSAVE_CONTEXT();\r
vTaskSwitchContext();\r
\r
/* Restore the context of the new task. */\r
- portRESTORE_CONTEXT(); \r
+ portRESTORE_CONTEXT();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
+/*\r
* The ISR used for the scheduler tick depends on whether the cooperative or\r
* the preemptive scheduler is being used.\r
*/\r
\r
#if configUSE_PREEMPTION == 0\r
\r
- /* The cooperative scheduler requires a normal IRQ service routine to \r
+ /* The cooperative scheduler requires a normal IRQ service routine to\r
simply increment the system tick. */\r
void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));\r
void vNonPreemptiveTick( void )\r
- { \r
+ {\r
uint32_t ulDummy;\r
- \r
+\r
/* Increment the tick count - which may wake some tasks but as the\r
preemptive scheduler is not being used any woken task is not given\r
processor time no matter what its priority. */\r
xTaskIncrementTick();\r
- \r
+\r
/* Clear the PIT interrupt. */\r
ulDummy = AT91C_BASE_PITC->PITC_PIVR;\r
- \r
+\r
/* End the interrupt in the AIC. */\r
AT91C_BASE_AIC->AIC_EOICR = ulDummy;\r
}\r
void vPreemptiveTick( void )\r
{\r
/* Save the context of the current task. */\r
- portSAVE_CONTEXT(); \r
+ portSAVE_CONTEXT();\r
\r
/* Increment the tick count - this may wake a task. */\r
if( xTaskIncrementTick() != pdFALSE )\r
/* Find the highest priority task that is ready to run. */\r
vTaskSwitchContext();\r
}\r
- \r
+\r
/* End the interrupt in the AIC. */\r
AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;;\r
- \r
+\r
portRESTORE_CONTEXT();\r
}\r
\r
\r
void vPortDisableInterruptsFromThumb( void )\r
{\r
- asm volatile ( \r
+ __asm volatile (\r
"STMDB SP!, {R0} \n\t" /* Push R0. */\r
"MRS R0, CPSR \n\t" /* Get CPSR. */\r
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\r
"LDMIA SP!, {R0} \n\t" /* Pop R0. */\r
"BX R14" ); /* Return back to thumb. */\r
}\r
- \r
+\r
void vPortEnableInterruptsFromThumb( void )\r
{\r
- asm volatile ( \r
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \r
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \r
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \r
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \r
+ __asm volatile (\r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */\r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */\r
"LDMIA SP!, {R0} \n\t" /* Pop R0. */\r
"BX R14" ); /* Return back to thumb. */\r
}\r
void vPortEnterCritical( void )\r
{\r
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */\r
- asm volatile ( \r
+ __asm volatile (\r
"STMDB SP!, {R0} \n\t" /* Push R0. */\r
"MRS R0, CPSR \n\t" /* Get CPSR. */\r
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\r
"MSR CPSR, R0 \n\t" /* Write back modified value. */\r
"LDMIA SP!, {R0}" ); /* Pop R0. */\r
\r
- /* Now interrupts are disabled ulCriticalNesting can be accessed \r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed\r
directly. Increment ulCriticalNesting to keep a count of how many times\r
portENTER_CRITICAL() has been called. */\r
ulCriticalNesting++;\r
if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
{\r
/* Enable interrupts as per portEXIT_CRITICAL(). */\r
- asm volatile ( \r
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \r
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \r
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \r
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \r
+ __asm volatile (\r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */\r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */\r
"LDMIA SP!, {R0}" ); /* Pop R0. */\r
}\r
}\r
#define portSTACK_GROWTH ( -1 )\r
#define portTICK_RATE_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
#define portBYTE_ALIGNMENT 8\r
-#define portNOP() asm volatile ( "NOP" );\r
+#define portNOP() __asm volatile ( "NOP" );\r
/*-----------------------------------------------------------*/\r
\r
\r
extern volatile uint32_t ulCriticalNesting; \\r
\\r
/* Set the LR to the task stack. */ \\r
- asm volatile ( \\r
+ __asm volatile ( \\r
"LDR R0, =pxCurrentTCB \n\t" \\r
"LDR R0, [R0] \n\t" \\r
"LDR LR, [R0] \n\t" \\r
extern volatile uint32_t ulCriticalNesting; \\r
\\r
/* Push R0 as we are going to use the register. */ \\r
- asm volatile ( \\r
+ __asm volatile ( \\r
"STMDB SP!, {R0} \n\t" \\r
\\r
/* Set R0 to point to the task stack pointer. */ \\r
\r
\r
#define portYIELD_FROM_ISR() vTaskSwitchContext()\r
-#define portYIELD() asm volatile ( "SWI 0" )\r
+#define portYIELD() __asm volatile ( "SWI 0" )\r
/*-----------------------------------------------------------*/\r
\r
\r
#else\r
\r
#define portDISABLE_INTERRUPTS() \\r
- asm volatile ( \\r
+ __asm volatile ( \\r
"STMDB SP!, {R0} \n\t" /* Push R0. */ \\r
"MRS R0, CPSR \n\t" /* Get CPSR. */ \\r
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \\r
"LDMIA SP!, {R0} " ) /* Pop R0. */\r
\r
#define portENABLE_INTERRUPTS() \\r
- asm volatile ( \\r
+ __asm volatile ( \\r
"STMDB SP!, {R0} \n\t" /* Push R0. */ \\r
"MRS R0, CPSR \n\t" /* Get CPSR. */ \\r
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \\r
#if( configASSERT_DEFINED == 1 )\r
{\r
volatile uint32_t ulOriginalPriority;\r
- volatile int8_t * const pcFirstUserPriorityRegister = ( volatile int8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
volatile uint8_t ucMaxPriorityValue;\r
\r
/* Determine the maximum priority from which ISR safe FreeRTOS API\r
ensure interrupt entry is as fast and simple as possible.\r
\r
Save the interrupt priority value that is about to be clobbered. */\r
- ulOriginalPriority = *pcFirstUserPriorityRegister;\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
\r
/* Determine the number of priority bits available. First write to all\r
possible bits. */\r
- *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
\r
/* Read the value back to see how many bits stuck. */\r
- ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
\r
/* Use the same mask on the maximum system call priority. */\r
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
\r
/* Restore the clobbered interrupt priority register to its original\r
value. */\r
- *pcFirstUserPriorityRegister = ulOriginalPriority;\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
}\r
#endif /* conifgASSERT_DEFINED */\r
\r
#if( configASSERT_DEFINED == 1 )\r
{\r
volatile uint32_t ulOriginalPriority;\r
- volatile int8_t * const pcFirstUserPriorityRegister = ( volatile int8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
volatile uint8_t ucMaxPriorityValue;\r
\r
/* Determine the maximum priority from which ISR safe FreeRTOS API\r
ensure interrupt entry is as fast and simple as possible.\r
\r
Save the interrupt priority value that is about to be clobbered. */\r
- ulOriginalPriority = *pcFirstUserPriorityRegister;\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
\r
/* Determine the number of priority bits available. First write to all\r
possible bits. */\r
- *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
\r
/* Read the value back to see how many bits stuck. */\r
- ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
\r
/* Use the same mask on the maximum system call priority. */\r
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
\r
/* Restore the clobbered interrupt priority register to its original\r
value. */\r
- *pcFirstUserPriorityRegister = ulOriginalPriority;\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
}\r
#endif /* conifgASSERT_DEFINED */\r
\r
#if( configASSERT_DEFINED == 1 )\r
{\r
volatile uint32_t ulOriginalPriority;\r
- volatile int8_t * const pcFirstUserPriorityRegister = ( volatile int8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
volatile uint8_t ucMaxPriorityValue;\r
\r
/* Determine the maximum priority from which ISR safe FreeRTOS API\r
ensure interrupt entry is as fast and simple as possible.\r
\r
Save the interrupt priority value that is about to be clobbered. */\r
- ulOriginalPriority = *pcFirstUserPriorityRegister;\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
\r
/* Determine the number of priority bits available. First write to all\r
possible bits. */\r
- *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
\r
/* Read the value back to see how many bits stuck. */\r
- ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
\r
/* Use the same mask on the maximum system call priority. */\r
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
\r
/* Restore the clobbered interrupt priority register to its original\r
value. */\r
- *pcFirstUserPriorityRegister = ulOriginalPriority;\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
}\r
#endif /* conifgASSERT_DEFINED */\r
\r
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
-#define portMAX_8_BIT_VALUE ( ( int8_t ) 0xff )\r
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )\r
#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )\r
#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )\r
#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
#if( configASSERT_DEFINED == 1 )\r
{\r
volatile uint32_t ulOriginalPriority;\r
- volatile int8_t * const pcFirstUserPriorityRegister = ( volatile int8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
volatile uint8_t ucMaxPriorityValue;\r
\r
/* Determine the maximum priority from which ISR safe FreeRTOS API\r
ensure interrupt entry is as fast and simple as possible.\r
\r
Save the interrupt priority value that is about to be clobbered. */\r
- ulOriginalPriority = *pcFirstUserPriorityRegister;\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
\r
/* Determine the number of priority bits available. First write to all\r
possible bits. */\r
- *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
\r
/* Read the value back to see how many bits stuck. */\r
- ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
\r
/* Use the same mask on the maximum system call priority. */\r
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
\r
/* Restore the clobbered interrupt priority register to its original\r
value. */\r
- *pcFirstUserPriorityRegister = ulOriginalPriority;\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
}\r
#endif /* conifgASSERT_DEFINED */\r
\r
#if( configASSERT_DEFINED == 1 )\r
{\r
volatile uint32_t ulOriginalPriority;\r
- volatile int8_t * const pcFirstUserPriorityRegister = ( int8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
volatile uint8_t ucMaxPriorityValue;\r
\r
/* Determine the maximum priority from which ISR safe FreeRTOS API\r
ensure interrupt entry is as fast and simple as possible.\r
\r
Save the interrupt priority value that is about to be clobbered. */\r
- ulOriginalPriority = *pcFirstUserPriorityRegister;\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
\r
/* Determine the number of priority bits available. First write to all\r
possible bits. */\r
- *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
\r
/* Read the value back to see how many bits stuck. */\r
- ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
\r
/* Use the same mask on the maximum system call priority. */\r
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
\r
/* Restore the clobbered interrupt priority register to its original\r
value. */\r
- *pcFirstUserPriorityRegister = ulOriginalPriority;\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
}\r
#endif /* conifgASSERT_DEFINED */\r
\r
#if( configASSERT_DEFINED == 1 )\r
{\r
volatile uint32_t ulOriginalPriority;\r
- volatile int8_t * const pcFirstUserPriorityRegister = ( int8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
volatile uint8_t ucMaxPriorityValue;\r
\r
/* Determine the maximum priority from which ISR safe FreeRTOS API\r
ensure interrupt entry is as fast and simple as possible.\r
\r
Save the interrupt priority value that is about to be clobbered. */\r
- ulOriginalPriority = *pcFirstUserPriorityRegister;\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
\r
/* Determine the number of priority bits available. First write to all\r
possible bits. */\r
- *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
\r
/* Read the value back to see how many bits stuck. */\r
- ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
\r
/* Use the same mask on the maximum system call priority. */\r
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
\r
/* Restore the clobbered interrupt priority register to its original\r
value. */\r
- *pcFirstUserPriorityRegister = ulOriginalPriority;\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
}\r
#endif /* conifgASSERT_DEFINED */\r
\r
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