*\r
*/\r
#if( portUSING_MPU_WRAPPERS == 1 )\r
- portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters, portBASE_TYPE xRunPrivileged );\r
+ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters, portBASE_TYPE xRunPrivileged ) PRIVILEGED_FUNCTION;\r
#else\r
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters );\r
#endif\r
* Setup the hardware ready for the scheduler to take control. This generally\r
* sets up a tick interrupt and sets timers for the correct tick frequency.\r
*/\r
-portBASE_TYPE xPortStartScheduler( void );\r
+portBASE_TYPE xPortStartScheduler( void ) PRIVILEGED_FUNCTION;\r
\r
/*\r
* Undo any hardware/ISR setup that was performed by xPortStartScheduler() so\r
* the hardware is left in its original condition after the scheduler stops\r
* executing.\r
*/\r
-void vPortEndScheduler( void );\r
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;\r
\r
/*\r
* The structures and methods of manipulating the MPU are contained within the\r
*/\r
#if( portUSING_MPU_WRAPPERS == 1 ) \r
struct xMEMORY_REGION;\r
- void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, portSTACK_TYPE *pxBottomOfStack, unsigned portSHORT usStackDepth );\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, portSTACK_TYPE *pxBottomOfStack, unsigned portSHORT usStackDepth ) PRIVILEGED_FUNCTION;\r
#endif\r
\r
#ifdef __cplusplus\r