-# The IMX27 ADS eval board has a single IMX27 chip\r
-# Note: tested on IMX27ADS Board REV-2.6 and REV-2.8\r
-source [find target/imx27.cfg]\r
-$_TARGETNAME configure -event gdb-attach { reset init }\r
-$_TARGETNAME configure -event reset-init { imx27ads_init }\r
-\r
-# The IMX27 ADS board has a NOR flash on CS0\r
-flash_bank cfi 0xc0000000 0x00200000 2 2 0\r
-\r
-proc imx27ads_init { } {\r
- # This setup puts RAM at 0xA0000000\r
-\r
- # reset the board correctly\r
- reset run\r
- reset halt\r
-\r
- mww 0x10000000 0x20040304\r
- mww 0x10020000 0x00000000\r
- mww 0x10000004 0xDFFBFCFB\r
- mww 0x10020004 0xFFFFFFFF\r
-\r
- sleep 100\r
-\r
- # ========================================\r
- # Configure DDR on CSD0 -- initial reset\r
- # ========================================\r
- mww 0xD8001010 0x00000008 \r
-\r
- # ========================================\r
- # Configure PSRAM on CS5 \r
- # ========================================\r
- mww 0xd8002050 0x0000dcf6\r
- mww 0xd8002054 0x444a4541 \r
- mww 0xd8002058 0x44443302 \r
-\r
- # ========================================\r
- # Configure16 bit NorFlash on CS0\r
- # ========================================\r
- mww 0xd8002000 0x0000CC03 \r
- mww 0xd8002004 0xa0330D01 \r
- mww 0xd8002008 0x00220800 \r
-\r
- # ========================================\r
- # Configure CPLD on CS4 \r
- # ========================================\r
- mww 0xd8002040 0x0000DCF6 \r
- mww 0xd8002044 0x444A4541 \r
- mww 0xd8002048 0x44443302 \r
-\r
- # ========================================\r
- # Configure DDR on CSD0 -- wait 5000 cycle \r
- # ========================================\r
- mww 0x10027828 0x55555555 \r
- mww 0x10027830 0x55555555 \r
- mww 0x10027834 0x55555555 \r
- mww 0x10027838 0x00005005 \r
- mww 0x1002783C 0x15555555 \r
-\r
- mww 0xD8001010 0x00000004 \r
-\r
- mww 0xD8001004 0x00795729 \r
-\r
- mww 0xD8001000 0x92200000 \r
- mww 0xA0000F00 0x0\r
-\r
- mww 0xD8001000 0xA2200000 \r
- mww 0xA0000F00 0x0\r
- mww 0xA0000F00 0x0\r
-\r
- mww 0xD8001000 0xB2200000 \r
- mwb 0xA0000033 0xFF\r
- mwb 0xA1000000 0xAA\r
-\r
- mww 0xD8001000 0x82228085 \r
-}\r
+# The IMX27 ADS eval board has a single IMX27 chip
+# Note: tested on IMX27ADS Board REV-2.6 and REV-2.8
+source [find target/imx27.cfg]
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { imx27ads_init }
+
+# The IMX27 ADS board has a NOR flash on CS0
+flash_bank cfi 0xc0000000 0x00200000 2 2 0
+
+proc imx27ads_init { } {
+ # This setup puts RAM at 0xA0000000
+
+ # reset the board correctly
+ reset run
+ reset halt
+
+ mww 0x10000000 0x20040304
+ mww 0x10020000 0x00000000
+ mww 0x10000004 0xDFFBFCFB
+ mww 0x10020004 0xFFFFFFFF
+
+ sleep 100
+
+ # ========================================
+ # Configure DDR on CSD0 -- initial reset
+ # ========================================
+ mww 0xD8001010 0x00000008
+
+ # ========================================
+ # Configure PSRAM on CS5
+ # ========================================
+ mww 0xd8002050 0x0000dcf6
+ mww 0xd8002054 0x444a4541
+ mww 0xd8002058 0x44443302
+
+ # ========================================
+ # Configure16 bit NorFlash on CS0
+ # ========================================
+ mww 0xd8002000 0x0000CC03
+ mww 0xd8002004 0xa0330D01
+ mww 0xd8002008 0x00220800
+
+ # ========================================
+ # Configure CPLD on CS4
+ # ========================================
+ mww 0xd8002040 0x0000DCF6
+ mww 0xd8002044 0x444A4541
+ mww 0xd8002048 0x44443302
+
+ # ========================================
+ # Configure DDR on CSD0 -- wait 5000 cycle
+ # ========================================
+ mww 0x10027828 0x55555555
+ mww 0x10027830 0x55555555
+ mww 0x10027834 0x55555555
+ mww 0x10027838 0x00005005
+ mww 0x1002783C 0x15555555
+
+ mww 0xD8001010 0x00000004
+
+ mww 0xD8001004 0x00795729
+
+ mww 0xD8001000 0x92200000
+ mww 0xA0000F00 0x0
+
+ mww 0xD8001000 0xA2200000
+ mww 0xA0000F00 0x0
+ mww 0xA0000F00 0x0
+
+ mww 0xD8001000 0xB2200000
+ mwb 0xA0000033 0xFF
+ mwb 0xA1000000 0xAA
+
+ mww 0xD8001000 0x82228085
+}
-# $Header: $\r
-# This will make the test program for ARM.\r
-\r
-PROC=arm\r
-TYPE=none-linux-gnueabi\r
-LDSCRIPT=ldscript\r
-\r
-PATH:=/opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/:$(PATH)\r
-CC=$(PROC)-$(TYPE)-gcc\r
-AS=$(PROC)-$(TYPE)-as\r
-AR=$(PROC)-$(TYPE)-ar\r
-LD=$(PROC)-$(TYPE)-ld\r
-NM=$(PROC)-$(TYPE)-nm\r
-OBJDUMP=$(PROC)-$(TYPE)-objdump\r
-CFLAGS= -g -c -mcpu=arm1136j-s\r
-\r
-all: test.elf\r
-\r
-# Make a little endian image:\r
-# In Eclipse, add the line :\r
-# source gdbinit \r
-# to : Run -> Debug... (menu) -> Commands (tab): Commands (listbox)\r
-# To start gdb from a window use : arm-elf-gdb --command=gdbinit\r
-test.elf: test.c Makefile ldscript crt0.S\r
- $(CC) $(CFLAGS) -o crt0.o crt0.S\r
- $(CC) $(CFLAGS) -o test.o test.c\r
- $(LD) -g -v -T$(LDSCRIPT) -o test.elf crt0.o test.o \r
- $(NM) test.elf\r
-\r
- \r
-dump:\r
- $(OBJDUMP) --all-headers test.elf\r
-\r
-dump_test:\r
- $(OBJDUMP) --disassemble test.elf\r
-\r
-dump_full:\r
- $(OBJDUMP) --full-contents test.elf\r
-\r
-clean:\r
- -/bin/rm -f *.o *~ test.elf\r
-\r
+# $Header: $
+# This will make the test program for ARM.
+
+PROC=arm
+TYPE=none-linux-gnueabi
+LDSCRIPT=ldscript
+
+PATH:=/opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/:$(PATH)
+CC=$(PROC)-$(TYPE)-gcc
+AS=$(PROC)-$(TYPE)-as
+AR=$(PROC)-$(TYPE)-ar
+LD=$(PROC)-$(TYPE)-ld
+NM=$(PROC)-$(TYPE)-nm
+OBJDUMP=$(PROC)-$(TYPE)-objdump
+CFLAGS= -g -c -mcpu=arm1136j-s
+
+all: test.elf
+
+# Make a little endian image:
+# In Eclipse, add the line :
+# source gdbinit
+# to : Run -> Debug... (menu) -> Commands (tab): Commands (listbox)
+# To start gdb from a window use : arm-elf-gdb --command=gdbinit
+test.elf: test.c Makefile ldscript crt0.S
+ $(CC) $(CFLAGS) -o crt0.o crt0.S
+ $(CC) $(CFLAGS) -o test.o test.c
+ $(LD) -g -v -T$(LDSCRIPT) -o test.elf crt0.o test.o
+ $(NM) test.elf
+
+
+dump:
+ $(OBJDUMP) --all-headers test.elf
+
+dump_test:
+ $(OBJDUMP) --disassemble test.elf
+
+dump_full:
+ $(OBJDUMP) --full-contents test.elf
+
+clean:
+ -/bin/rm -f *.o *~ test.elf
+
-/* Sample initialization file */\r
- \r
- .extern main\r
- .extern exit\r
- \r
-/* .text is used instead of .section .text so it works with arm-aout too. */\r
- .text\r
- .code 32\r
- .align 0\r
-\r
- .global _mainCRTStartup\r
- .global _start\r
- .global start\r
-start:\r
-_start:\r
-_mainCRTStartup:\r
-\r
-/* Start by setting up a stack */\r
- /* Set up the stack pointer to end of bss */\r
- ldr r3, .LC2\r
- mov sp, r3\r
-\r
- sub sl, sp, #512 /* Still assumes 512 bytes below sl */\r
-\r
- mov a2, #0 /* Second arg: fill value */\r
- mov fp, a2 /* Null frame pointer */\r
- mov r7, a2 /* Null frame pointer for Thumb */\r
- \r
- ldr a1, .LC1 /* First arg: start of memory block */\r
- ldr a3, .LC2 /* Second arg: end of memory block */\r
- sub a3, a3, a1 /* Third arg: length of block */\r
- \r
- mov r0, #0 /* no arguments */\r
- mov r1, #0 /* no argv either */\r
-\r
- bl main\r
- bl exit /* Should not return */\r
-\r
- /* For Thumb, constants must be after the code since only \r
- positive offsets are supported for PC relative addresses. */\r
- \r
- .align 0\r
-.LC1:\r
- .word __bss_start__\r
-.LC2:\r
- .word __bss_end__\r
-\r
+/* Sample initialization file */
+
+ .extern main
+ .extern exit
+
+/* .text is used instead of .section .text so it works with arm-aout too. */
+ .text
+ .code 32
+ .align 0
+
+ .global _mainCRTStartup
+ .global _start
+ .global start
+start:
+_start:
+_mainCRTStartup:
+
+/* Start by setting up a stack */
+ /* Set up the stack pointer to end of bss */
+ ldr r3, .LC2
+ mov sp, r3
+
+ sub sl, sp, #512 /* Still assumes 512 bytes below sl */
+
+ mov a2, #0 /* Second arg: fill value */
+ mov fp, a2 /* Null frame pointer */
+ mov r7, a2 /* Null frame pointer for Thumb */
+
+ ldr a1, .LC1 /* First arg: start of memory block */
+ ldr a3, .LC2 /* Second arg: end of memory block */
+ sub a3, a3, a1 /* Third arg: length of block */
+
+ mov r0, #0 /* no arguments */
+ mov r1, #0 /* no argv either */
+
+ bl main
+ bl exit /* Should not return */
+
+ /* For Thumb, constants must be after the code since only
+ positive offsets are supported for PC relative addresses. */
+
+ .align 0
+.LC1:
+ .word __bss_start__
+.LC2:
+ .word __bss_end__
+
-echo Setting up for the FreeScale iMX31 Board.\n\r
-# SETUP GDB :\r
-#\r
-# Common gdb setup for ARM CPUs\r
-set complaints 1\r
-set output-radix 10\r
-set input-radix 10\r
-set prompt (arm-gdb) \r
-set endian little\r
-dir .\r
-\r
-\r
-# DEFINE MACROS :\r
-#\r
-# Create a "refresh" macro to update gdb's screens after the cpu\r
-# has been stopped by the other CPU or following an "monitor allstop" \r
-define refresh\r
- monitor set hbreak\r
- cont\r
- monitor clear hbreak\r
-end\r
-\r
-\r
-# CONNECT TO TARGET :\r
-target remote 127.0.0.1:3333\r
-monitor reset run\r
-#FIX!!!! should be reset init!\r
-monitor reset halt\r
-\r
-# iMX31 PDK board initialization commands:\r
-\r
-#// init_ccm\r
-\r
-monitor mww 0x53FC0000 0x040\r
-monitor mww 0x53F80000 0x074B0B7D\r
-\r
-#//532-133-66.5\r
-#//monitor mww 0x53F80004 0xFF871D58\r
-#//monitor mww 0x53F80010 0x0033280C\r
-\r
-#// 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40\r
-monitor mww 0x53F80004 0xFF871D50\r
-monitor mww 0x53F80010 0x00271C1B\r
-\r
-#// 208-104-52\r
-#//monitor mww 0x53F80004 0xFF871D48\r
-#//monitor mww 0x53F80010 0x04002000\r
-\r
-\r
-#// Configure CPLD on CS5 \r
-monitor mww 0xb8002050 0x0000DCF6\r
-monitor mww 0xb8002054 0x444A4541\r
-monitor mww 0xb8002058 0x44443302\r
-\r
-#// Disable maximum drive strength for SDRAM/DDR lines by clearing DSE1 bits\r
-#// in SW_PAD_CTL registers\r
-\r
-#// SDCLK\r
-monitor mww 0x43FAC26C 0\r
- \r
-#// CAS\r
-monitor mww 0x43FAC270 0\r
- \r
-#// RAS\r
-monitor mww 0x43FAC274 0\r
- \r
-#// CS2 (CSD0)\r
-monitor mww 0x43FAC27C 0x1000\r
- \r
-#// DQM3\r
-monitor mww 0x43FAC284 0\r
- \r
-#// DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)\r
-monitor mww 0x43FAC288 0\r
-monitor mww 0x43FAC28C 0\r
-monitor mww 0x43FAC290 0\r
-monitor mww 0x43FAC294 0\r
-monitor mww 0x43FAC298 0\r
-monitor mww 0x43FAC29C 0\r
-monitor mww 0x43FAC2A0 0\r
-monitor mww 0x43FAC2A4 0\r
-monitor mww 0x43FAC2A8 0\r
-monitor mww 0x43FAC2AC 0\r
-monitor mww 0x43FAC2B0 0\r
-monitor mww 0x43FAC2B4 0\r
-monitor mww 0x43FAC2B8 0\r
-monitor mww 0x43FAC2BC 0\r
-monitor mww 0x43FAC2C0 0\r
-monitor mww 0x43FAC2C4 0\r
-monitor mww 0x43FAC2C8 0\r
-monitor mww 0x43FAC2CC 0\r
-monitor mww 0x43FAC2D0 0\r
-monitor mww 0x43FAC2D4 0\r
-monitor mww 0x43FAC2D8 0\r
-monitor mww 0x43FAC2DC 0\r
-\r
-#// Initialization script for 32 bit DDR on MX31 PDK \r
-monitor mww 0xB8001010 0x00000004\r
-monitor mww 0xB8001004 0x006ac73a\r
-monitor mww 0xB8001000 0x92100000\r
-monitor mww 0x80000f00 0x12344321\r
-monitor mww 0xB8001000 0xa2100000\r
-monitor mww 0x80000000 0x12344321\r
-monitor mww 0x80000000 0x12344321\r
-monitor mww 0xB8001000 0xb2100000\r
-#monitor char 0x80000033 0xda\r
-monitor mwb 0x80000033 0xda\r
-#monitor char 0x81000000 0xff\r
-monitor mwb 0x81000000 0xff\r
-monitor mww 0xB8001000 0x82226080\r
-monitor mww 0x80000000 0xDEADBEEF\r
-monitor mww 0xB8001010 0x0000000c\r
-\r
-# LOAD IMAGE :\r
-#\r
-\r
-# Load the program executable called "u-boot"\r
-load test.elf\r
-\r
-# Load the symbols for the program.\r
-symbol-file test.elf\r
-\r
-# RUN TO MAIN :\r
-#\r
-# Set a breakpoint at main().\r
-#b reset\r
-b main\r
-\r
-# Run to the breakpoint.\r
-c\r
+echo Setting up for the FreeScale iMX31 Board.\n
+# SETUP GDB :
+#
+# Common gdb setup for ARM CPUs
+set complaints 1
+set output-radix 10
+set input-radix 10
+set prompt (arm-gdb)
+set endian little
+dir .
+
+# DEFINE MACROS :
+#
+# Create a "refresh" macro to update gdb's screens after the cpu
+# has been stopped by the other CPU or following an "monitor allstop"
+define refresh
+ monitor set hbreak
+ cont
+ monitor clear hbreak
+end
+
+# CONNECT TO TARGET :
+target remote 127.0.0.1:3333
+monitor reset run
+#FIX!!!! should be reset init!
+monitor reset halt
+
+# iMX31 PDK board initialization commands:
+
+#// init_ccm
+
+monitor mww 0x53FC0000 0x040
+monitor mww 0x53F80000 0x074B0B7D
+
+#//532-133-66.5
+#//monitor mww 0x53F80004 0xFF871D58
+#//monitor mww 0x53F80010 0x0033280C
+
+#// 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
+monitor mww 0x53F80004 0xFF871D50
+monitor mww 0x53F80010 0x00271C1B
+
+#// 208-104-52
+#//monitor mww 0x53F80004 0xFF871D48
+#//monitor mww 0x53F80010 0x04002000
+
+#// Configure CPLD on CS5
+monitor mww 0xb8002050 0x0000DCF6
+monitor mww 0xb8002054 0x444A4541
+monitor mww 0xb8002058 0x44443302
+
+#// Disable maximum drive strength for SDRAM/DDR lines by clearing DSE1 bits
+#// in SW_PAD_CTL registers
+
+#// SDCLK
+monitor mww 0x43FAC26C 0
+
+#// CAS
+monitor mww 0x43FAC270 0
+
+#// RAS
+monitor mww 0x43FAC274 0
+
+#// CS2 (CSD0)
+monitor mww 0x43FAC27C 0x1000
+
+#// DQM3
+monitor mww 0x43FAC284 0
+
+#// DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
+monitor mww 0x43FAC288 0
+monitor mww 0x43FAC28C 0
+monitor mww 0x43FAC290 0
+monitor mww 0x43FAC294 0
+monitor mww 0x43FAC298 0
+monitor mww 0x43FAC29C 0
+monitor mww 0x43FAC2A0 0
+monitor mww 0x43FAC2A4 0
+monitor mww 0x43FAC2A8 0
+monitor mww 0x43FAC2AC 0
+monitor mww 0x43FAC2B0 0
+monitor mww 0x43FAC2B4 0
+monitor mww 0x43FAC2B8 0
+monitor mww 0x43FAC2BC 0
+monitor mww 0x43FAC2C0 0
+monitor mww 0x43FAC2C4 0
+monitor mww 0x43FAC2C8 0
+monitor mww 0x43FAC2CC 0
+monitor mww 0x43FAC2D0 0
+monitor mww 0x43FAC2D4 0
+monitor mww 0x43FAC2D8 0
+monitor mww 0x43FAC2DC 0
+
+#// Initialization script for 32 bit DDR on MX31 PDK
+monitor mww 0xB8001010 0x00000004
+monitor mww 0xB8001004 0x006ac73a
+monitor mww 0xB8001000 0x92100000
+monitor mww 0x80000f00 0x12344321
+monitor mww 0xB8001000 0xa2100000
+monitor mww 0x80000000 0x12344321
+monitor mww 0x80000000 0x12344321
+monitor mww 0xB8001000 0xb2100000
+#monitor char 0x80000033 0xda
+monitor mwb 0x80000033 0xda
+#monitor char 0x81000000 0xff
+monitor mwb 0x81000000 0xff
+monitor mww 0xB8001000 0x82226080
+monitor mww 0x80000000 0xDEADBEEF
+monitor mww 0xB8001010 0x0000000c
+
+# LOAD IMAGE :
+#
+
+# Load the program executable called "u-boot"
+load test.elf
+
+# Load the symbols for the program.
+symbol-file test.elf
+
+# RUN TO MAIN :
+#
+# Set a breakpoint at main().
+#b reset
+b main
+
+# Run to the breakpoint.
+c
-SECTIONS\r
-{\r
- . = 0x80000100;\r
- .text : { *(.text) }\r
- .data ALIGN(0x10): { *(.data) }\r
- .bss ALIGN(0x10): {\r
- __bss_start__ = ABSOLUTE(.);\r
- *(.bss)\r
- . += 0x100;\r
- }\r
- __bss_end__ = .;\r
-PROVIDE (__stack = .);\r
- _end = .;\r
- .debug_info 0 : { *(.debug_info) }\r
- .debug_abbrev 0 : { *(.debug_abbrev) }\r
- .debug_line 0 : { *(.debug_line) }\r
- .debug_frame 0 : { *(.debug_frame) }\r
-}\r
+SECTIONS
+{
+ . = 0x80000100;
+ .text : { *(.text) }
+ .data ALIGN(0x10): { *(.data) }
+ .bss ALIGN(0x10): {
+ __bss_start__ = ABSOLUTE(.);
+ *(.bss)
+ . += 0x100;
+ }
+ __bss_end__ = .;
+PROVIDE (__stack = .);
+ _end = .;
+ .debug_info 0 : { *(.debug_info) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+}
projects / openocd / commitdiff