--- /dev/null
+/*\r
+ FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <75x_lib.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* Timer clock. */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 12800 )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Library includes. */\r
+#include "75x_GPIO.h"\r
+#include "75x_map.h"\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines for the LED's \r
+ *-----------------------------------------------------------*/\r
+\r
+#define partstNUM_LEDS 4\r
+\r
+typedef struct GPIOMAP\r
+{\r
+ GPIO_TypeDef *pxPort;\r
+ unsigned portLONG ulPin;\r
+ unsigned portLONG ulValue;\r
+} GPIO_MAP;\r
+\r
+static GPIO_MAP xLEDMap[ partstNUM_LEDS ] =\r
+{\r
+ { ( GPIO_TypeDef * )GPIO1_BASE, GPIO_Pin_1, 0UL },\r
+ { ( GPIO_TypeDef * )GPIO0_BASE, GPIO_Pin_16, 0UL },\r
+ { ( GPIO_TypeDef * )GPIO2_BASE, GPIO_Pin_18, 0UL }, \r
+ { ( GPIO_TypeDef * )GPIO2_BASE, GPIO_Pin_19, 0UL } \r
+};\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{ \r
+GPIO_InitTypeDef GPIO_InitStructure ;\r
+\r
+ /* Configure the bits used to flash LED's on port 1 as output. */\r
+\r
+ /* Configure LED3 */\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16;\r
+ GPIO_Init(GPIO0,&GPIO_InitStructure);\r
+\r
+ /* Configure LED2 */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;\r
+ GPIO_Init(GPIO1, &GPIO_InitStructure);\r
+\r
+ /* Configure LED4 and LED5 */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_18 | GPIO_Pin_19;\r
+ GPIO_Init(GPIO2, &GPIO_InitStructure);\r
+\r
+ vParTestSetLED( 0, 0 );\r
+ vParTestSetLED( 1, 0 );\r
+ vParTestSetLED( 2, 0 );\r
+ vParTestSetLED( 3, 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ if( uxLED < partstNUM_LEDS )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ if( xValue )\r
+ {\r
+ GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_RESET );\r
+ xLEDMap[ uxLED ].ulValue = 0;\r
+ }\r
+ else\r
+ {\r
+ GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_SET );\r
+ xLEDMap[ uxLED ].ulValue = 1; \r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED < partstNUM_LEDS )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ if( xLEDMap[ uxLED ].ulValue == 1 )\r
+ {\r
+ GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_RESET );\r
+ xLEDMap[ uxLED ].ulValue = 0;\r
+ }\r
+ else\r
+ {\r
+ GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_SET );\r
+ xLEDMap[ uxLED ].ulValue = 1; \r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+}\r
+\r
+\r
+\r
+\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_adc.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006 \r
+* Description : This file contains all the functions prototypes for the\r
+* ADC software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1 \r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, \r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING \r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_ADC_H\r
+#define __75x_ADC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* ADC Init structure definition */\r
+typedef struct\r
+{\r
+ u16 ADC_ConversionMode;\r
+ u16 ADC_ExtTrigger;\r
+ u16 ADC_AutoClockOff;\r
+ u8 ADC_SamplingPrescaler;\r
+ u8 ADC_ConversionPrescaler;\r
+ u8 ADC_FirstChannel;\r
+ u8 ADC_ChannelNumber;\r
+ }ADC_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* ADC control status flags */\r
+#define ADC_FLAG_ECH 0x0001\r
+#define ADC_FLAG_EOC 0x0002\r
+#define ADC_FLAG_JECH 0x0004\r
+#define ADC_FLAG_JEOC 0x0008\r
+#define ADC_FLAG_AnalogWatchdog0_LowThreshold 0x0010\r
+#define ADC_FLAG_AnalogWatchdog0_HighThreshold 0x0020\r
+#define ADC_FLAG_AnalogWatchdog1_LowThreshold 0x0040\r
+#define ADC_FLAG_AnalogWatchdog1_HighThreshold 0x0080\r
+#define ADC_FLAG_AnalogWatchdog2_LowThreshold 0x0100\r
+#define ADC_FLAG_AnalogWatchdog2_HighThreshold 0x0200\r
+#define ADC_FLAG_AnalogWatchdog3_LowThreshold 0x0400\r
+#define ADC_FLAG_AnalogWatchdog3_HighThreshold 0x0800\r
+\r
+/* ADC Interrupt sources */\r
+#define ADC_IT_ECH 0x0001\r
+#define ADC_IT_EOC 0x0002\r
+#define ADC_IT_JECH 0x0004\r
+#define ADC_IT_JEOC 0x0008\r
+#define ADC_IT_AnalogWatchdog0_LowThreshold 0x0010\r
+#define ADC_IT_AnalogWatchdog0_HighThreshold 0x0020\r
+#define ADC_IT_AnalogWatchdog1_LowThreshold 0x0040\r
+#define ADC_IT_AnalogWatchdog1_HighThreshold 0x0080\r
+#define ADC_IT_AnalogWatchdog2_LowThreshold 0x0100\r
+#define ADC_IT_AnalogWatchdog2_HighThreshold 0x0200\r
+#define ADC_IT_AnalogWatchdog3_LowThreshold 0x0400\r
+#define ADC_IT_AnalogWatchdog3_HighThreshold 0x0800\r
+#define ADC_IT_ALL 0x0FFF\r
+\r
+/* ADC Watchdogs Thresholds */\r
+#define ADC_AnalogWatchdog0 0x0030\r
+#define ADC_AnalogWatchdog1 0x00C0\r
+#define ADC_AnalogWatchdog2 0x0300\r
+#define ADC_AnalogWatchdog3 0x0C00\r
+\r
+/* ADC Channels */\r
+#define ADC_CHANNEL0 0x0\r
+#define ADC_CHANNEL1 0x1\r
+#define ADC_CHANNEL2 0x2\r
+#define ADC_CHANNEL3 0x3\r
+#define ADC_CHANNEL4 0x4\r
+#define ADC_CHANNEL5 0x5\r
+#define ADC_CHANNEL6 0x6\r
+#define ADC_CHANNEL7 0x7\r
+#define ADC_CHANNEL8 0x8\r
+#define ADC_CHANNEL9 0x9\r
+#define ADC_CHANNEL10 0xA\r
+#define ADC_CHANNEL11 0xB\r
+#define ADC_CHANNEL12 0xC\r
+#define ADC_CHANNEL13 0xD\r
+#define ADC_CHANNEL14 0xE\r
+#define ADC_CHANNEL15 0xF\r
+\r
+/* ADC DMA Channels */\r
+#define ADC_DMA_CHANNEL0 0x0001\r
+#define ADC_DMA_CHANNEL1 0x0002\r
+#define ADC_DMA_CHANNEL2 0x0004\r
+#define ADC_DMA_CHANNEL3 0x0008\r
+#define ADC_DMA_CHANNEL4 0x0010\r
+#define ADC_DMA_CHANNEL5 0x0020\r
+#define ADC_DMA_CHANNEL6 0x0040\r
+#define ADC_DMA_CHANNEL7 0x0080\r
+#define ADC_DMA_CHANNEL8 0x0100\r
+#define ADC_DMA_CHANNEL9 0x0200\r
+#define ADC_DMA_CHANNEL10 0x0400\r
+#define ADC_DMA_CHANNEL11 0x0800\r
+#define ADC_DMA_CHANNEL12 0x1000\r
+#define ADC_DMA_CHANNEL13 0x2000\r
+#define ADC_DMA_CHANNEL14 0x4000\r
+#define ADC_DMA_CHANNEL15 0x8000\r
+\r
+/* Trigger conversion detection */\r
+#define ADC_ExtTrigger_LowLevel 0x4FFF\r
+#define ADC_ExtTrigger_HighLevel 0x5000\r
+#define ADC_ExtTrigger_FallingEdge 0x6000\r
+#define ADC_ExtTrigger_RisingEdge 0x7000\r
+#define ADC_ExtTrigger_Disable 0x8FFF\r
+\r
+/* DMA enable config */\r
+#define ADC_DMA_ExtTrigger_HighLevel 0x6000\r
+#define ADC_DMA_ExtTrigger_LowLevel 0x4FFF\r
+#define ADC_DMA_Enable 0x8000\r
+#define ADC_DMA_Disable 0x3FFF\r
+\r
+/* Injected Trigger conversion detection */\r
+#define ADC_Injec_ExtTrigger_RisingEdge 0x6000\r
+#define ADC_Injec_ExtTrigger_FallingEdge 0xDFFF\r
+#define ADC_Injec_ExtTrigger_Disable 0x3FFF\r
+\r
+/* Start Conversion */\r
+#define ADC_Conversion_Start 0x0001\r
+#define ADC_Conversion_Stop 0xFFFE\r
+\r
+/* ADC Conversion Modes */\r
+#define ADC_ConversionMode_Scan 0x8000\r
+#define ADC_ConversionMode_OneShot 0x7FFF\r
+\r
+/* Auto Clock Off */\r
+#define ADC_AutoClockOff_Enable 0x4000\r
+#define ADC_AutoClockOff_Disable 0xBFFF\r
+\r
+/* Calibration */\r
+#define ADC_Calibration_ON 0x0002\r
+#define ADC_CalibAverage_Disable 0x0020\r
+#define ADC_CalibAverage_Enable 0xFFDF\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+void ADC_DeInit(void);\r
+void ADC_Init(ADC_InitTypeDef *ADC_InitStruct);\r
+void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);\r
+void ADC_Cmd(FunctionalState NewState);\r
+void ADC_StartCalibration(u16 ADC_CalibAverage);\r
+FlagStatus ADC_GetCalibrationStatus(void);\r
+void ADC_ConversionCmd(u16 ADC_Conversion);\r
+FlagStatus ADC_GetSTARTBitStatus(void);\r
+void ADC_AutoClockOffConfig(FunctionalState NewState);\r
+u16 ADC_GetConversionValue(u8 ADC_CHANNEL);\r
+void ADC_ITConfig(u16 ADC_IT, FunctionalState NewState);\r
+void ADC_AnalogWatchdogConfig(u16 ADC_AnalogWatchdog, u8 ADC_CHANNEL, \r
+ u16 LowThreshold, u16 HighThreshold);\r
+void ADC_AnalogWatchdogCmd(u16 ADC_AnalogWatchdog, FunctionalState NewState);\r
+u16 ADC_GetAnalogWatchdogResult(u16 ADC_AnalogWatchdog);\r
+void ADC_StartInjectedConversion(void);\r
+void ADC_InjectedConversionConfig(u16 ADC_Injec_ExtTrigger, u8 FirstChannel, u8 ChannelNumber);\r
+void ADC_DMAConfig(u16 ADC_DMA_CHANNEL, FunctionalState NewState);\r
+void ADC_DMACmd(u16 ADC_DMA);\r
+u16 ADC_GetDMAFirstEnabledChannel(void);\r
+FlagStatus ADC_GetFlagStatus(u16 ADC_FLAG);\r
+void ADC_ClearFlag(u16 ADC_FLAG);\r
+ITStatus ADC_GetITStatus(u16 ADC_IT);\r
+void ADC_ClearITPendingBit(u16 ADC_IT);\r
+\r
+#endif /*__75x_ADC_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_can.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* CAN bus software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_CAN_H\r
+#define __75x_CAN_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/* CAN Init structure define */\r
+typedef struct\r
+{\r
+ u8 CAN_ConfigParameters;\r
+ u32 CAN_Bitrate;\r
+}CAN_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Standard bitrates available*/\r
+enum\r
+{\r
+ CAN_BITRATE_100K,\r
+ CAN_BITRATE_125K,\r
+ CAN_BITRATE_250K,\r
+ CAN_BITRATE_500K,\r
+ CAN_BITRATE_1M\r
+};\r
+\r
+/* Control register*/\r
+#define CAN_CR_TEST 0x0080\r
+#define CAN_CR_CCE 0x0040\r
+#define CAN_CR_DAR 0x0020\r
+#define CAN_CR_EIE 0x0008\r
+#define CAN_CR_SIE 0x0004\r
+#define CAN_CR_IE 0x0002\r
+#define CAN_CR_INIT 0x0001\r
+\r
+/* Status register */\r
+#define CAN_SR_BOFF 0x0080\r
+#define CAN_SR_EWARN 0x0040\r
+#define CAN_SR_EPASS 0x0020\r
+#define CAN_SR_RXOK 0x0010\r
+#define CAN_SR_TXOK 0x0008\r
+#define CAN_SR_LEC 0x0007\r
+\r
+/* Test register*/\r
+#define CAN_TESTR_RX 0x0080\r
+#define CAN_TESTR_TX1 0x0040\r
+#define CAN_TESTR_TX0 0x0020\r
+#define CAN_TESTR_LBACK 0x0010\r
+#define CAN_TESTR_SILENT 0x0008\r
+#define CAN_TESTR_BASIC 0x0004\r
+\r
+/* IFn / Command Request register*/\r
+#define CAN_CRR_BUSY 0x8000\r
+\r
+/* IFn / Command Mask register*/\r
+#define CAN_CMR_WRRD 0x0080\r
+#define CAN_CMR_MASK 0x0040\r
+#define CAN_CMR_ARB 0x0020\r
+#define CAN_CMR_CONTROL 0x0010\r
+#define CAN_CMR_CLRINTPND 0x0008\r
+#define CAN_CMR_TXRQSTNEWDAT 0x0004\r
+#define CAN_CMR_DATAA 0x0002\r
+#define CAN_CMR_DATAB 0x0001\r
+\r
+/* IFn / Mask 2 register*/\r
+#define CAN_M2R_MXTD 0x8000\r
+#define CAN_M2R_MDIR 0x4000\r
+\r
+/* IFn / Arbitration 2 register*/\r
+#define CAN_A2R_MSGVAL 0x8000\r
+#define CAN_A2R_XTD 0x4000\r
+#define CAN_A2R_DIR 0x2000\r
+\r
+/* IFn / Message Control register*/\r
+#define CAN_MCR_NEWDAT 0x8000\r
+#define CAN_MCR_MSGLST 0x4000\r
+#define CAN_MCR_INTPND 0x2000\r
+#define CAN_MCR_UMASK 0x1000\r
+#define CAN_MCR_TXIE 0x0800\r
+#define CAN_MCR_RXIE 0x0400\r
+#define CAN_MCR_RMTEN 0x0200\r
+#define CAN_MCR_TXRQST 0x0100\r
+#define CAN_MCR_EOB 0x0080\r
+\r
+\r
+/* Wake-up modes*/\r
+enum\r
+{\r
+ CAN_WAKEUP_ON_EXT,\r
+ CAN_WAKEUP_ON_CAN\r
+};\r
+\r
+\r
+/* CAN message structure*/\r
+typedef struct\r
+{\r
+ u32 IdType;\r
+ u32 Id;\r
+ u8 Dlc;\r
+ u8 Data[8];\r
+} canmsg;\r
+\r
+/* Message ID types*/\r
+enum\r
+{\r
+ CAN_STD_ID,\r
+ CAN_EXT_ID\r
+};\r
+\r
+/* Message ID limits*/\r
+\r
+#define CAN_LAST_STD_ID ((1<<11) - 1)\r
+#define CAN_LAST_EXT_ID ((1L<<29) - 1)\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void CAN_Init (CAN_InitTypeDef *CAN_InitStruct);\r
+void CAN_DeInit (void);\r
+void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct);\r
+void CAN_SetBitrate(u32 bitrate);\r
+void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp);\r
+ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj);\r
+ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType);\r
+ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast);\r
+void CAN_InvalidateAllMsgObj(void);\r
+ErrorStatus CAN_ReleaseMessage(u32 msgobj);\r
+ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg);\r
+ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg);\r
+ErrorStatus CAN_WaitEndOfTx(void);\r
+ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg);\r
+ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg);\r
+void CAN_EnterTestMode(u8 TestMask);\r
+void CAN_EnterInitMode(u8 InitMask);\r
+void CAN_LeaveInitMode(void);\r
+void CAN_LeaveTestMode(void);\r
+void CAN_ReleaseTxMessage(u32 msgobj);\r
+void CAN_ReleaseRxMessage(u32 msgobj);\r
+u32 CAN_IsMessageWaiting(u32 msgobj);\r
+u32 CAN_IsTransmitRequested(u32 msgobj);\r
+u32 CAN_IsInterruptPending(u32 msgobj);\r
+u32 CAN_IsObjectValid(u32 msgobj);\r
+\r
+#endif /* __75x_CAN_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_cfg.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* CFG software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_CFG_H\r
+#define __75x_CFG_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+#define CFG_BootSpace_FLASH 0x00000000\r
+#define CFG_BootSpace_SRAM 0x00000002\r
+#define CFG_BootSpace_ExtSMI 0x00000003\r
+\r
+#define CFG_FLASHBurst_Disable 0xFFFFFEFF\r
+#define CFG_FLASHBurst_Enable 0x00000100\r
+\r
+#define CFG_USBFilter_Disable 0xFFFFFDFF\r
+#define CFG_USBFilter_Enable 0x00000200\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void CFG_BootSpaceConfig(u32 CFG_BootSpace);\r
+void CFG_FLASHBurstConfig(u32 CFG_FLASHBurst);\r
+void CFG_USBFilterConfig(u32 CFG_USBFilter);\r
+FlagStatus CFG_GetFlagStatus(void);\r
+\r
+#endif /* __75x_CFG_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_conf.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : Library configuration file.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_CONF_H\r
+#define __75x_CONF_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Comment the line below to compile the library in release mode */\r
+//#define DEBUG\r
+\r
+/************************************* SMI ************************************/\r
+//#define _SMI\r
+\r
+/************************************* CFG ************************************/\r
+#define _CFG\r
+\r
+/************************************* MRCC ************************************/\r
+#define _MRCC\r
+\r
+/************************************* ADC ************************************/\r
+//#define _ADC\r
+\r
+/************************************* TB *************************************/\r
+#define _TB\r
+\r
+/************************************* TIM ************************************/\r
+#define _TIM\r
+#define _TIM0\r
+#define _TIM1\r
+#define _TIM2\r
+\r
+/************************************* PWM ************************************/\r
+#define _PWM\r
+\r
+/************************************* WDG ************************************/\r
+#define _WDG\r
+\r
+/************************************* SSP ************************************/\r
+//#define _SSP\r
+//#define _SSP0\r
+//#define _SSP1\r
+\r
+/************************************* CAN ************************************/\r
+//#define _CAN\r
+\r
+/************************************* I2C ************************************/\r
+//#define _I2C\r
+\r
+/************************************* UART ***********************************/\r
+#define _UART\r
+#define _UART0\r
+#define _UART1\r
+#define _UART2\r
+\r
+/************************************* GPIO ***********************************/\r
+#define _GPIO\r
+#define _GPIO0\r
+#define _GPIO1\r
+#define _GPIO2\r
+#define _GPIOREMAP\r
+\r
+/************************************* DMA ************************************/\r
+//#define _DMA\r
+//#define _DMA_Stream0\r
+//#define _DMA_Stream1\r
+//#define _DMA_Stream2\r
+//#define _DMA_Stream3\r
+\r
+/************************************* RTC ************************************/\r
+//#define _RTC\r
+\r
+/************************************* EXTIT **********************************/\r
+#define _EXTIT\r
+\r
+/************************************* EIC ************************************/\r
+#define _EIC\r
+\r
+/* Comment the following line, depending on the external Quartz oscillator used\r
+ in your application */\r
+#define Main_Oscillator 4000000 /* 4 MHz Quartz oscillator used */\r
+//#define Main_Oscillator 8000000 /* 8 MHz Quartz oscillator used */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+#endif /* __75x_CONF_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_dma.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006 \r
+* Description : This file contains all the functions prototypes for the\r
+* DMA software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1 \r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, \r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING \r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion ------------------------------------ */\r
+#ifndef __75x_DMA_H\r
+#define __75x_DMA_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* DMA Init structure definition */\r
+typedef struct\r
+{\r
+ u32 DMA_SRCBaseAddr;\r
+ u32 DMA_DSTBaseAddr; \r
+ u16 DMA_BufferSize; \r
+ u16 DMA_SRC; \r
+ u16 DMA_DST; \r
+ u16 DMA_SRCSize;\r
+ u16 DMA_SRCBurst;\r
+ u16 DMA_DSTSize;\r
+ u16 DMA_Mode; \r
+ u16 DMA_M2M; \r
+ u16 DMA_DIR; \r
+}DMA_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* DMA interrupt Mask */\r
+#define DMA_IT_SI0 0x0001\r
+#define DMA_IT_SI1 0x0002\r
+#define DMA_IT_SI2 0x0004\r
+#define DMA_IT_SI3 0x0008\r
+#define DMA_IT_SE0 0x0010\r
+#define DMA_IT_SE1 0x0020\r
+#define DMA_IT_SE2 0x0040\r
+#define DMA_IT_SE3 0x0080\r
+#define DMA_IT_ALL 0x00FF\r
+\r
+/* DMA Flags */\r
+#define DMA_FLAG_SI0 0x0001\r
+#define DMA_FLAG_SI1 0x0002\r
+#define DMA_FLAG_SI2 0x0004\r
+#define DMA_FLAG_SI3 0x0008\r
+#define DMA_FLAG_SE0 0x0010\r
+#define DMA_FLAG_SE1 0x0020\r
+#define DMA_FLAG_SE2 0x0040\r
+#define DMA_FLAG_SE3 0x0080\r
+#define DMA_FLAG_ACT0 0x0100\r
+#define DMA_FLAG_ACT1 0x0200\r
+#define DMA_FLAG_ACT2 0x0400\r
+#define DMA_FLAG_ACT3 0x0800\r
+\r
+/* DMA Increment Current Source Register */\r
+#define DMA_SRC_INCR 0x0002\r
+#define DMA_SRC_NOT_INCR 0xFFFD\r
+\r
+/* DMA Increment Current Destination Register */\r
+#define DMA_DST_INCR 0x0004\r
+#define DMA_DST_NOT_INCR 0xFFFB\r
+\r
+/* Source to DMA data width */\r
+#define DMA_SRCSize_Byte 0x0000\r
+#define DMA_SRCSize_HalfWord 0x0008\r
+#define DMA_SRCSize_Word 0x0010\r
+\r
+/* DMA source burst size */\r
+#define DMA_SRCBurst_1Data 0x0000\r
+#define DMA_SRCBurst_4Data 0x0020\r
+#define DMA_SRCBurst_8Data 0x0040\r
+#define DMA_SRCBurst_16Data 0x0060\r
+\r
+/* DMA destination data width */\r
+#define DMA_DSTSize_Byte 0x0000\r
+#define DMA_DSTSize_HalfWord 0x0080\r
+#define DMA_DSTSize_Word 0x0100\r
+\r
+/* DMA mode */\r
+#define DMA_Mode_Circular 0x0200\r
+#define DMA_Mode_Normal 0xFDFF\r
+\r
+/* Memory to Memory Transfer */\r
+#define DMA_M2M_Enable 0x0800\r
+#define DMA_M2M_Disable 0xF7FF\r
+\r
+/* Direction Transfer */\r
+#define DMA_DIR_PeriphDST 0x2000\r
+#define DMA_DIR_PeriphSRC 0xDFFF\r
+\r
+/* DMA streamx Registers */\r
+#define DMA_SOURCEL 0x00000000 /* source base address low register */\r
+#define DMA_SOURCEH 0x00000004 /* source base address high register */\r
+#define DMA_DESTL 0x00000008 /* destination base address low register */\r
+#define DMA_DESTH 0x0000000C /* destination base address high register */\r
+#define DMA_MAX 0x00000010 /* Maximum count register */\r
+#define DMA_CTRL 0x00000014 /* Control register */\r
+#define DMA_SOCURRH 0x00000018 /* Current Source address high register */\r
+#define DMA_SOCURRL 0x0000001C /* Current Source address low register */\r
+#define DMA_DECURRH 0x00000020 /* Current Destination address high register */\r
+#define DMA_DECURRL 0x00000024 /* Current Destination address low register */\r
+#define DMA_TCNT 0x00000028 /* Terminal Counter Register */\r
+#define DMA_LUBUFF 0x0000002C /* Last Used Buffer location */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void DMA_DeInit(DMA_Stream_TypeDef* DMA_Streamx);\r
+void DMA_Init(DMA_Stream_TypeDef* DMA_Streamx, DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_Cmd(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState);\r
+void DMA_ITConfig(u16 DMA_IT, FunctionalState NewState);\r
+u32 DMA_GetCurrDSTAddr(DMA_Stream_TypeDef* DMA_Streamx);\r
+u32 DMA_GetCurrSRCAddr(DMA_Stream_TypeDef* DMA_Streamx);\r
+u16 DMA_GetTerminalCounter(DMA_Stream_TypeDef* DMA_Streamx);\r
+void DMA_LastBufferSweepConfig(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState);\r
+void DMA_LastBufferAddrConfig(DMA_Stream_TypeDef* DMA_Streamx, u16 DMA_LastBufferAddr);\r
+FlagStatus DMA_GetFlagStatus(u16 DMA_FLAG);\r
+void DMA_ClearFlag(u16 DMA_FLAG);\r
+ITStatus DMA_GetITStatus(u16 DMA_IT);\r
+void DMA_ClearITPendingBit(u16 DMA_IT);\r
+\r
+#endif /* __75x_DMA_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_eic.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* EIC software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_EIC_H\r
+#define __75x_EIC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ u8 EIC_IRQChannel;\r
+ u8 EIC_IRQChannelPriority;\r
+ FunctionalState EIC_IRQChannelCmd;\r
+}EIC_IRQInitTypeDef;\r
+\r
+typedef struct\r
+{\r
+ u8 EIC_FIQChannel;\r
+ FunctionalState EIC_FIQChannelCmd;\r
+}EIC_FIQInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* IRQ channels */\r
+#define WAKUP_IRQChannel 0\r
+#define TIM2_OC2_IRQChannel 1\r
+#define TIM2_OC1_IRQChannel 2\r
+#define TIM2_IC12_IRQChannel 3\r
+#define TIM2_UP_IRQChannel 4\r
+#define TIM1_OC2_IRQChannel 5\r
+#define TIM1_OC1_IRQChannel 6\r
+#define TIM1_IC12_IRQChannel 7\r
+#define TIM1_UP_IRQChannel 8\r
+#define TIM0_OC2_IRQChannel 9\r
+#define TIM0_OC1_IRQChannel 10\r
+#define TIM0_IC12_IRQChannel 11\r
+#define TIM0_UP_IRQChannel 12\r
+#define PWM_OC123_IRQChannel 13\r
+#define PWM_EM_IRQChannel 14\r
+#define PWM_UP_IRQChannel 15\r
+#define I2C_IRQChannel 16\r
+#define SSP1_IRQChannel 17\r
+#define SSP0_IRQChannel 18\r
+#define UART2_IRQChannel 19\r
+#define UART1_IRQChannel 20\r
+#define UART0_IRQChannel 21\r
+#define CAN_IRQChannel 22\r
+#define USB_LP_IRQChannel 23\r
+#define USB_HP_IRQChannel 24\r
+#define ADC_IRQChannel 25\r
+#define DMA_IRQChannel 26\r
+#define EXTIT_IRQChannel 27\r
+#define MRCC_IRQChannel 28\r
+#define FLASHSMI_IRQChannel 29\r
+#define RTC_IRQChannel 30\r
+#define TB_IRQChannel 31\r
+\r
+/* FIQ channels */\r
+#define EXTIT_Line0_FIQChannel 0x00000001\r
+#define WATCHDOG_FIQChannel 0x00000002\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void EIC_DeInit(void);\r
+void EIC_IRQInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct);\r
+void EIC_FIQInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct);\r
+void EIC_IRQStructInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct);\r
+void EIC_FIQStructInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct);\r
+void EIC_IRQCmd(FunctionalState NewState);\r
+void EIC_FIQCmd(FunctionalState NewState);\r
+u8 EIC_GetCurrentIRQChannel(void);\r
+u8 EIC_GetCurrentIRQChannelPriority(void);\r
+void EIC_CurrentIRQPriorityConfig(u8 NewPriority);\r
+u8 EIC_GetCurrentFIQChannel(void);\r
+void EIC_ClearFIQPendingBit(u8 EIC_FIQChannel);\r
+\r
+#endif /* __75x_EIC_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_extit.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* EXTIT software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_EXTIT_H\r
+#define __75x_EXTIT_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* EXTIT Trigger enumeration */\r
+typedef enum\r
+{\r
+ EXTIT_ITTrigger_Falling = 1,\r
+ EXTIT_ITTrigger_Rising\r
+}EXTITTrigger_TypeDef;\r
+\r
+/* EXTIT Init Structure definition */\r
+typedef struct\r
+{\r
+ u32 EXTIT_ITLine;\r
+ EXTITTrigger_TypeDef EXTIT_ITTrigger;\r
+ FunctionalState EXTIT_ITLineCmd;\r
+}EXTIT_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* EXTIT Lines */\r
+#define EXTIT_ITLineNone 0x0000 /* No interrupt selected */\r
+#define EXTIT_ITLine0 0x0001 /* External interrupt line 0 */\r
+#define EXTIT_ITLine1 0x0002 /* External interrupt line 1 */\r
+#define EXTIT_ITLine2 0x0004 /* External interrupt line 2 */\r
+#define EXTIT_ITLine3 0x0008 /* External interrupt line 3 */\r
+#define EXTIT_ITLine4 0x0010 /* External interrupt line 4 */\r
+#define EXTIT_ITLine5 0x0020 /* External interrupt line 5 */\r
+#define EXTIT_ITLine6 0x0040 /* External interrupt line 6 */\r
+#define EXTIT_ITLine7 0x0080 /* External interrupt line 7 */\r
+#define EXTIT_ITLine8 0x0100 /* External interrupt line 8 */\r
+#define EXTIT_ITLine9 0x0200 /* External interrupt line 9 */\r
+#define EXTIT_ITLine10 0x0400 /* External interrupt line 10 */\r
+#define EXTIT_ITLine11 0x0800 /* External interrupt line 11 */\r
+#define EXTIT_ITLine12 0x1000 /* External interrupt line 12 */\r
+#define EXTIT_ITLine13 0x2000 /* External interrupt line 13 */\r
+#define EXTIT_ITLine14 0x4000 /* External interrupt line 14 */\r
+#define EXTIT_ITLine15 0x8000 /* External interrupt line 15 */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void EXTIT_DeInit(void);\r
+void EXTIT_Init(EXTIT_InitTypeDef* EXTIT_InitStruct);\r
+void EXTIT_StructInit(EXTIT_InitTypeDef* EXTIT_InitStruct);\r
+void EXTIT_GenerateSWInterrupt(u16 EXTIT_ITLine);\r
+FlagStatus EXTIT_GetFlagStatus(u16 EXTIT_ITLine);\r
+void EXTIT_ClearFlag(u16 EXTIT_ITLine);\r
+ITStatus EXTIT_GetITStatus(u16 EXTIT_ITLine);\r
+void EXTIT_ClearITPendingBit(u16 EXTIT_ITLine);\r
+\r
+#endif /* __75x_EXTIT_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_gpio.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* GPIO software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_GPIO_H\r
+#define __75x_GPIO_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Configuration Mode enumeration */\r
+typedef enum\r
+{ GPIO_Mode_AIN = 1,\r
+ GPIO_Mode_IN_FLOATING,\r
+ GPIO_Mode_IPD,\r
+ GPIO_Mode_IPU,\r
+ GPIO_Mode_Out_OD,\r
+ GPIO_Mode_Out_PP,\r
+ GPIO_Mode_AF_OD,\r
+ GPIO_Mode_AF_PP\r
+}GPIOMode_TypeDef;\r
+\r
+/* GPIO Init structure definition */\r
+typedef struct\r
+{\r
+ u32 GPIO_Pin;\r
+ GPIOMode_TypeDef GPIO_Mode;\r
+}GPIO_InitTypeDef;\r
+\r
+/* Bit_SET and Bit_RESET enumeration */\r
+typedef enum\r
+{ Bit_RESET = 0,\r
+ Bit_SET\r
+}BitAction;\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* GPIO pins define */\r
+#define GPIO_Pin_None 0x00000000 /* No pin selected */\r
+#define GPIO_Pin_0 0x00000001 /* Pin 0 selected */\r
+#define GPIO_Pin_1 0x00000002 /* Pin 1 selected */\r
+#define GPIO_Pin_2 0x00000004 /* Pin 2 selected */\r
+#define GPIO_Pin_3 0x00000008 /* Pin 3 selected */\r
+#define GPIO_Pin_4 0x00000010 /* Pin 4 selected */\r
+#define GPIO_Pin_5 0x00000020 /* Pin 5 selected */\r
+#define GPIO_Pin_6 0x00000040 /* Pin 6 selected */\r
+#define GPIO_Pin_7 0x00000080 /* Pin 7 selected */\r
+#define GPIO_Pin_8 0x00000100 /* Pin 8 selected */\r
+#define GPIO_Pin_9 0x00000200 /* Pin 9 selected */\r
+#define GPIO_Pin_10 0x00000400 /* Pin 10 selected */\r
+#define GPIO_Pin_11 0x00000800 /* Pin 11 selected */\r
+#define GPIO_Pin_12 0x00001000 /* Pin 12 selected */\r
+#define GPIO_Pin_13 0x00002000 /* Pin 13 selected */\r
+#define GPIO_Pin_14 0x00004000 /* Pin 14 selected */\r
+#define GPIO_Pin_15 0x00008000 /* Pin 15 selected */\r
+#define GPIO_Pin_16 0x00010000 /* Pin 16 selected */\r
+#define GPIO_Pin_17 0x00020000 /* Pin 17 selected */\r
+#define GPIO_Pin_18 0x00040000 /* Pin 18 selected */\r
+#define GPIO_Pin_19 0x00080000 /* Pin 19 selected */\r
+#define GPIO_Pin_20 0x00100000 /* Pin 20 selected */\r
+#define GPIO_Pin_21 0x00200000 /* Pin 21 selected */\r
+#define GPIO_Pin_22 0x00400000 /* Pin 22 selected */\r
+#define GPIO_Pin_23 0x00800000 /* Pin 23 selected */\r
+#define GPIO_Pin_24 0x01000000 /* Pin 24 selected */\r
+#define GPIO_Pin_25 0x02000000 /* Pin 25 selected */\r
+#define GPIO_Pin_26 0x04000000 /* Pin 26 selected */\r
+#define GPIO_Pin_27 0x08000000 /* Pin 27 selected */\r
+#define GPIO_Pin_28 0x10000000 /* Pin 28 selected */\r
+#define GPIO_Pin_29 0x20000000 /* Pin 29 selected */\r
+#define GPIO_Pin_30 0x40000000 /* Pin 30 selected */\r
+#define GPIO_Pin_31 0x80000000 /* Pin 31 selected */\r
+#define GPIO_Pin_All 0xFFFFFFFF /* All pins selected */\r
+\r
+/* GPIO Remap define */\r
+#define GPIO_Remap_SMI_CS3_EN 0x23 /* SMI CS3 Enable */\r
+#define GPIO_Remap_SMI_CS2_EN 0x22 /* SMI CS2 Enable */\r
+#define GPIO_Remap_SMI_CS1_EN 0x21 /* SMI CS1 Enable */\r
+#define GPIO_Remap_SMI_EN 0x20 /* SMI Enable */\r
+#define GPIO_Remap_DBGOFF 0x45 /* JTAG Disable */\r
+#define GPIO_Remap_UART1 0x44 /* UART1 Alternate Function mapping */\r
+#define GPIO_Remap_UART2 0x43 /* UART2 Alternate Function mapping */\r
+#define GPIO_Remap_SSP1 0x42 /* SSP1 Alternate Function mapping */\r
+#define GPIO_Remap_TIM2 0x41 /* TIM2 Alternate Function mapping */\r
+#define GPIO_Remap_TIM0 0x40 /* TIM0 Alternate Function mapping */\r
+\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);\r
+u32 GPIO_Read(GPIO_TypeDef* GPIOx);\r
+u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin);\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, u32 PortVal);\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx,u32 GPIO_Pin, BitAction BitVal);\r
+void GPIO_PinMaskConfig(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, FunctionalState NewState);\r
+u32 GPIO_GetPortMask(GPIO_TypeDef* GPIOx);\r
+void GPIO_PinRemapConfig(u16 GPIO_Remap, FunctionalState NewState);\r
+\r
+#endif /* __75x_GPIO_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_i2c.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006 \r
+* Description : This file contains all the functions prototypes for the\r
+* I2C software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, \r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING \r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion ------------------------------------ */\r
+#ifndef __75x_I2C_H\r
+#define __75x_I2C_H\r
+\r
+/* Includes ----------------------------------------------------------------- */\r
+#include "75x_map.h"\r
+\r
+/* Exported types ----------------------------------------------------------- */\r
+/* I2C Init structure definition */\r
+typedef struct\r
+{\r
+ u32 I2C_CLKSpeed;\r
+ u16 I2C_OwnAddress;\r
+ u8 I2C_GeneralCall;\r
+ u8 I2C_Ack;\r
+}I2C_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* General Call */\r
+#define I2C_GeneralCall_Enable 0x10\r
+#define I2C_GeneralCall_Disable 0xEF\r
+\r
+/* Acknowledgement */\r
+#define I2C_Ack_Enable 0x04\r
+#define I2C_Ack_Disable 0xFB\r
+\r
+/* I2C Flags */\r
+#define I2C_FLAG_SB 0x0001\r
+#define I2C_FLAG_M_SL 0x0002\r
+#define I2C_FLAG_ADSL 0x0004\r
+#define I2C_FLAG_BTF 0x0008\r
+#define I2C_FLAG_BUSY 0x0010\r
+#define I2C_FLAG_TRA 0x0020\r
+#define I2C_FLAG_ADD10 0x0040\r
+#define I2C_FLAG_EVF 0x0080\r
+#define I2C_FLAG_GCAL 0x0100\r
+#define I2C_FLAG_BERR 0x0200\r
+#define I2C_FLAG_ARLO 0x0400\r
+#define I2C_FLAG_STOPF 0x0800\r
+#define I2C_FLAG_AF 0x1000\r
+#define I2C_FLAG_ENDAD 0x2000\r
+#define I2C_FLAG_ACK 0x4000\r
+\r
+/* I2C Events */\r
+#define I2C_EVENT_SLAVE_ADDRESS_MATCHED ( I2C_FLAG_EVF | I2C_FLAG_BUSY |I2C_FLAG_ADSL) \r
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF ) \r
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA ) \r
+#define I2C_EVENT_MASTER_MODE_SELECT ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_SB ) \r
+#define I2C_EVENT_MASTER_MODE_SELECTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_ENDAD ) \r
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF ) \r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF | I2C_FLAG_TRA ) \r
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL |I2C_FLAG_ADD10 ) \r
+#define I2C_EVENT_SLAVE_STOP_DETECTED I2C_FLAG_STOPF \r
+#define I2C_EVENT_SLAVE_ACK_FAILURE ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA | I2C_FLAG_AF) \r
+\r
+#define I2C_BUS_ERROR_DETECTED I2C_FLAG_BERR\r
+#define I2C_ARBITRATION_LOST I2C_FLAG_ARLO\r
+#define I2C_SLAVE_GENERAL_CALL (I2C_FLAG_BUSY | I2C_FLAG_GCAL)\r
+\r
+/* Master/Receiver Mode */ \r
+#define I2C_MODE_TRANSMITTER 0x00\r
+#define I2C_MODE_RECEIVER 0x01\r
+\r
+/* I2C Registers offset */\r
+#define I2C_CR 0x00\r
+#define I2C_SR1 0x04\r
+#define I2C_SR2 0x08\r
+#define I2C_CCR 0x0C\r
+#define I2C_OAR1 0x10\r
+#define I2C_OAR2 0x14\r
+#define I2C_DR 0x18\r
+#define I2C_ECCR 0x1C\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void I2C_DeInit(void);\r
+void I2C_Init(I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_Cmd(FunctionalState NewState);\r
+void I2C_GenerateSTART(FunctionalState NewState);\r
+void I2C_GenerateSTOP(FunctionalState NewState);\r
+void I2C_AcknowledgeConfig(FunctionalState NewState);\r
+void I2C_ITConfig(FunctionalState NewState);\r
+u16 I2C_GetLastEvent(void);\r
+ErrorStatus I2C_CheckEvent(u16 I2C_EVENT);\r
+void I2C_SendData(u8 Data);\r
+u8 I2C_ReceiveData(void);\r
+void I2C_Send7bitAddress(u8 Address, u8 Direction);\r
+u8 I2C_ReadRegister(u8 I2C_Register);\r
+FlagStatus I2C_GetFlagStatus(u16 I2C_FLAG);\r
+void I2C_ClearFlag(u16 I2C_FLAG, ...);\r
+\r
+#endif /* __75x_I2C_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_lib.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file includes the peripherals header files in the\r
+* user application.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_LIB_H\r
+#define __75x_LIB_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+#ifdef _SMI\r
+ #include "75x_smi.h"\r
+#endif /*_SMI */\r
+\r
+#ifdef _CFG\r
+ #include "75x_cfg.h"\r
+#endif /*_CFG*/\r
+\r
+#ifdef _MRCC\r
+ #include "75x_mrcc.h"\r
+#endif /*_MRCC */\r
+\r
+#ifdef _ADC\r
+ #include "75x_adc.h"\r
+#endif /*_ADC */\r
+\r
+#ifdef _TB\r
+ #include "75x_tb.h"\r
+#endif /*_TB */\r
+\r
+#ifdef _TIM\r
+ #include "75x_tim.h"\r
+#endif /*_TIM */\r
+\r
+#ifdef _PWM\r
+ #include "75x_pwm.h"\r
+#endif /*_PWM */\r
+\r
+#ifdef _WDG\r
+ #include "75x_wdg.h"\r
+#endif /*_WDG */\r
+\r
+#ifdef _SSP\r
+ #include "75x_ssp.h"\r
+#endif /*_SSP */\r
+\r
+#ifdef _CAN\r
+ #include "75x_can.h"\r
+#endif /*_CAN */\r
+\r
+#ifdef _I2C\r
+ #include "75x_i2c.h"\r
+#endif /*_I2C */\r
+\r
+#ifdef _UART\r
+ #include "75x_uart.h"\r
+#endif /*_UART */\r
+\r
+#ifdef _GPIO\r
+ #include "75x_gpio.h"\r
+#endif /*_GPIO */\r
+\r
+#ifdef _DMA\r
+ #include "75x_dma.h"\r
+#endif /*_DMA */\r
+\r
+#ifdef _RTC\r
+ #include "75x_rtc.h"\r
+#endif /*_RTC */\r
+\r
+#ifdef _EXTIT\r
+ #include "75x_extit.h"\r
+#endif /*_EXTIT */\r
+\r
+#ifdef _EIC\r
+ #include "75x_eic.h"\r
+#endif /*_EIC */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void debug(void);\r
+\r
+#endif /* __75x_LIB_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_map.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the peripheral register's definitions\r
+* and memory mapping.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_MAP_H\r
+#define __75x_MAP_H\r
+\r
+#ifndef EXT\r
+ #define EXT extern\r
+#endif /* EXT */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_conf.h"\r
+#include "75x_type.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/******************************************************************************/\r
+/* IP registers structures */\r
+/******************************************************************************/\r
+\r
+/*------------------------ Analog to Digital Converter -----------------------*/\r
+typedef struct\r
+{\r
+ vu16 CLR0;\r
+ u16 EMPTY1;\r
+ vu16 CLR1;\r
+ u16 EMPTY2;\r
+ vu16 CLR2;\r
+ u16 EMPTY3;\r
+ vu16 CLR3;\r
+ u16 EMPTY4;\r
+ vu16 CLR4;\r
+ u16 EMPTY5;\r
+ vu16 TRA0;\r
+ u16 EMPTY6;\r
+ vu16 TRA1;\r
+ u16 EMPTY7;\r
+ vu16 TRA2;\r
+ u16 EMPTY8;\r
+ vu16 TRA3;\r
+ u16 EMPTY9;\r
+ vu16 TRB0;\r
+ u16 EMPTY10;\r
+ vu16 TRB1;\r
+ u16 EMPTY11;\r
+ vu16 TRB2;\r
+ u16 EMPTY12;\r
+ vu16 TRB3;\r
+ u16 EMPTY13;\r
+ vu16 DMAR;\r
+ u16 EMPTY14[7];\r
+ vu16 DMAE;\r
+ u16 EMPTY15 ;\r
+ vu16 PBR;\r
+ u16 EMPTY16;\r
+ vu16 IMR;\r
+ u16 EMPTY17;\r
+ vu16 D0;\r
+ u16 EMPTY18;\r
+ vu16 D1;\r
+ u16 EMPTY19;\r
+ vu16 D2;\r
+ u16 EMPTY20;\r
+ vu16 D3;\r
+ u16 EMPTY21;\r
+ vu16 D4;\r
+ u16 EMPTY22;\r
+ vu16 D5;\r
+ u16 EMPTY23;\r
+ vu16 D6;\r
+ u16 EMPTY24;\r
+ vu16 D7;\r
+ u16 EMPTY25;\r
+ vu16 D8;\r
+ u16 EMPTY26;\r
+ vu16 D9;\r
+ u16 EMPTY27;\r
+ vu16 D10;\r
+ u16 EMPTY28;\r
+ vu16 D11;\r
+ u16 EMPTY29;\r
+ vu16 D12;\r
+ u16 EMPTY30;\r
+ vu16 D13;\r
+ u16 EMPTY31;\r
+ vu16 D14;\r
+ u16 EMPTY32;\r
+ vu16 D15;\r
+ u16 EMPTY33;\r
+} ADC_TypeDef;\r
+\r
+/*------------------------ Controller Area Network ---------------------------*/\r
+typedef struct\r
+{\r
+ vu16 CRR; \r
+ u16 EMPTY1;\r
+ vu16 CMR; \r
+ u16 EMPTY2;\r
+ vu16 M1R; \r
+ u16 EMPTY3;\r
+ vu16 M2R; \r
+ u16 EMPTY4;\r
+ vu16 A1R; \r
+ u16 EMPTY5;\r
+ vu16 A2R; \r
+ u16 EMPTY6;\r
+ vu16 MCR; \r
+ u16 EMPTY7;\r
+ vu16 DA1R; \r
+ u16 EMPTY8;\r
+ vu16 DA2R; \r
+ u16 EMPTY9;\r
+ vu16 DB1R; \r
+ u16 EMPTY10;\r
+ vu16 DB2R; \r
+ u16 EMPTY11[27];\r
+} CAN_MsgObj_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu16 CR; \r
+ u16 EMPTY1;\r
+ vu16 SR; \r
+ u16 EMPTY2;\r
+ vu16 ERR; \r
+ u16 EMPTY3;\r
+ vu16 BTR; \r
+ u16 EMPTY4;\r
+ vu16 IDR; \r
+ u16 EMPTY5;\r
+ vu16 TESTR; \r
+ u16 EMPTY6;\r
+ vu16 BRPR; \r
+ u16 EMPTY7[3];\r
+ CAN_MsgObj_TypeDef sMsgObj[2];\r
+ u16 EMPTY8[16];\r
+ vu16 TXR1R; \r
+ u16 EMPTY9;\r
+ vu16 TXR2R; \r
+ u16 EMPTY10[13];\r
+ vu16 ND1R; \r
+ u16 EMPTY11;\r
+ vu16 ND2R; \r
+ u16 EMPTY12[13];\r
+ vu16 IP1R; \r
+ u16 EMPTY13;\r
+ vu16 IP2R; \r
+ u16 EMPTY14[13];\r
+ vu16 MV1R; \r
+ u16 EMPTY15;\r
+ vu16 MV2R; \r
+ u16 EMPTY16;\r
+} CAN_TypeDef;\r
+\r
+/*--------------------------- Configuration Register -------------------------*/\r
+typedef struct\r
+{\r
+ vu32 GLCONF;\r
+} CFG_TypeDef;\r
+\r
+/*-------------------------------- DMA Controller ----------------------------*/\r
+typedef struct\r
+{\r
+ vu16 SOURCEL;\r
+ u16 EMPTY1;\r
+ vu16 SOURCEH;\r
+ u16 EMPTY2;\r
+ vu16 DESTL;\r
+ u16 EMPTY3;\r
+ vu16 DESTH;\r
+ u16 EMPTY4;\r
+ vu16 MAX;\r
+ u16 EMPTY5;\r
+ vu16 CTRL;\r
+ u16 EMPTY6;\r
+ vuc16 SOCURRH;\r
+ u16 EMPTY7;\r
+ vuc16 SOCURRL;\r
+ u16 EMPTY8;\r
+ vuc16 DECURRH;\r
+ u16 EMPTY9;\r
+ vuc16 DECURRL;\r
+ u16 EMPTY10;\r
+ vuc16 TCNT;\r
+ u16 EMPTY11;\r
+ vu16 LUBUFF;\r
+ u16 EMPTY12;\r
+} DMA_Stream_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu16 MASK;\r
+ u16 EMPTY4;\r
+ vu16 CLR;\r
+ u16 EMPTY5;\r
+ vuc16 STATUS;\r
+ u16 EMPTY6;\r
+ vu16 LAST; \r
+ u16 EMPTY7;\r
+} DMA_TypeDef;\r
+\r
+/*----------------------- Enhanced Interrupt Controller ----------------------*/\r
+typedef struct\r
+{\r
+ vu32 ICR; \r
+ vuc32 CICR; \r
+ vu32 CIPR;\r
+ u32 EMPTY1;\r
+ vu32 FIER;\r
+ vu32 FIPR;\r
+ vu32 IVR;\r
+ vu32 FIR;\r
+ vu32 IER;\r
+ u32 EMPTY2[7];\r
+ vu32 IPR;\r
+ u32 EMPTY3[7];\r
+ vu32 SIRn[32];\r
+} EIC_TypeDef;\r
+\r
+/*------------------------- External Interrupt Controller --------------------*/\r
+typedef struct\r
+{\r
+ vu32 MR;\r
+ vu32 TSR;\r
+ vu32 SWIR;\r
+ vu32 PR;\r
+} EXTIT_TypeDef;\r
+\r
+/*-------------------------- General Purpose IO ports ------------------------*/\r
+typedef struct\r
+{\r
+ vu32 PC0;\r
+ vu32 PC1;\r
+ vu32 PC2;\r
+ vu32 PD;\r
+ vu32 PM;\r
+} GPIO_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 REMAP0R;\r
+ vu32 REMAP1R;\r
+} GPIOREMAP_TypeDef;\r
+\r
+/*--------------------------------- I2C interface ----------------------------*/\r
+typedef struct\r
+{\r
+ vu8 CR; \r
+ u8 EMPTY1[3];\r
+ vu8 SR1;\r
+ u8 EMPTY2[3];\r
+ vu8 SR2;\r
+ u8 EMPTY3[3];\r
+ vu8 CCR;\r
+ u8 EMPTY4[3];\r
+ vu8 OAR1;\r
+ u8 EMPTY5[3];\r
+ vu8 OAR2;\r
+ u8 EMPTY6[3];\r
+ vu8 DR;\r
+ u8 EMPTY7[3];\r
+ vu8 ECCR;\r
+ u8 EMPTY8[3];\r
+} I2C_TypeDef;\r
+\r
+/*---------------------------- Power, Reset and Clocks -----------------------*/\r
+typedef struct\r
+{\r
+ vu32 CLKCTL;\r
+ vu32 RFSR;\r
+ vu32 PWRCTRL;\r
+ u32 EMPTY1;\r
+ vu32 PCLKEN;\r
+ vu32 PSWRES;\r
+ u32 EMPTY2[2];\r
+ vu32 BKP0;\r
+ vu32 BKP1;\r
+} MRCC_TypeDef;\r
+\r
+/*-------------------------------- Real Time Clock ---------------------------*/\r
+typedef struct\r
+{\r
+ vu16 CRH;\r
+ u16 EMPTY;\r
+ vu16 CRL;\r
+ u16 EMPTY1;\r
+ vu16 PRLH;\r
+ u16 EMPTY2;\r
+ vu16 PRLL;\r
+ u16 EMPTY3;\r
+ vu16 DIVH;\r
+ u16 EMPTY4;\r
+ vu16 DIVL;\r
+ u16 EMPTY5;\r
+ vu16 CNTH;\r
+ u16 EMPTY6;\r
+ vu16 CNTL;\r
+ u16 EMPTY7;\r
+ vu16 ALRH;\r
+ u16 EMPTY8;\r
+ vu16 ALRL;\r
+ u16 EMPTY9;\r
+} RTC_TypeDef;\r
+\r
+/*---------------------------- Serial Memory Interface -----------------------*/\r
+typedef struct\r
+{\r
+ vu32 CR1;\r
+ vu32 CR2;\r
+ vu32 SR;\r
+ vu32 TR;\r
+ vuc32 RR;\r
+} SMI_TypeDef;\r
+\r
+/*--------------------------------- Timer Base -------------------------------*/\r
+typedef struct\r
+{\r
+ vu16 CR;\r
+ u16 EMPTY1;\r
+ vu16 SCR;\r
+ u16 EMPTY2;\r
+ vu16 IMCR;\r
+ u16 EMPTY3[7];\r
+ vu16 RSR;\r
+ u16 EMPTY4;\r
+ vu16 RER;\r
+ u16 EMPTY5;\r
+ vu16 ISR;\r
+ u16 EMPTY6;\r
+ vu16 CNT;\r
+ u16 EMPTY7;\r
+ vu16 PSC;\r
+ u16 EMPTY8[3];\r
+ vu16 ARR;\r
+ u16 EMPTY9[13];\r
+ vu16 ICR1;\r
+ u16 EMPTY10;\r
+} TB_TypeDef;\r
+\r
+/*------------------------------------ TIM -----------------------------------*/\r
+typedef struct\r
+{\r
+ vu16 CR;\r
+ u16 EMPTY1;\r
+ vu16 SCR;\r
+ u16 EMPTY2;\r
+ vu16 IMCR;\r
+ u16 EMPTY3;\r
+ vu16 OMR1;\r
+ u16 EMPTY4[5];\r
+ vu16 RSR;\r
+ u16 EMPTY5;\r
+ vu16 RER;\r
+ u16 EMPTY6;\r
+ vu16 ISR;\r
+ u16 EMPTY7;\r
+ vu16 CNT;\r
+ u16 EMPTY8;\r
+ vu16 PSC;\r
+ u16 EMPTY9[3];\r
+ vu16 ARR;\r
+ u16 EMPTY10;\r
+ vu16 OCR1;\r
+ u16 EMPTY11;\r
+ vu16 OCR2;\r
+ u16 EMPTY12[9];\r
+ vu16 ICR1;\r
+ u16 EMPTY13;\r
+ vu16 ICR2;\r
+ u16 EMPTY14[9];\r
+ vu16 DMAB;\r
+ u16 EMPTY15;\r
+} TIM_TypeDef;\r
+\r
+/*------------------------------------ PWM -----------------------------------*/\r
+typedef struct\r
+{\r
+ vu16 CR;\r
+ u16 EMPTY1;\r
+ vu16 SCR;\r
+ u16 EMPTY2[3];\r
+ vu16 OMR1;\r
+ u16 EMPTY3;\r
+ vu16 OMR2;\r
+ u16 EMPTY4[3];\r
+ vu16 RSR;\r
+ u16 EMPTY5;\r
+ vu16 RER;\r
+ u16 EMPTY6;\r
+ vu16 ISR;\r
+ u16 EMPTY7;\r
+ vu16 CNT;\r
+ u16 EMPTY8;\r
+ vu16 PSC;\r
+ u16 EMPTY9;\r
+ vu16 RCR;\r
+ u16 EMPTY10;\r
+ vu16 ARR;\r
+ u16 EMPTY11;\r
+ vu16 OCR1;\r
+ u16 EMPTY12;\r
+ vu16 OCR2;\r
+ u16 EMPTY13;\r
+ vu16 OCR3;\r
+ u16 EMPTY14[15];\r
+ vu16 DTR;\r
+ u16 EMPTY15;\r
+ vu16 DMAB;\r
+ u16 EMPTY16;\r
+} PWM_TypeDef;\r
+\r
+/*----------------------- Synchronous Serial Peripheral ----------------------*/\r
+typedef struct\r
+{\r
+ vu32 CR0;\r
+ vu32 CR1;\r
+ vu32 DR;\r
+ vu32 SR;\r
+ vu32 PR;\r
+ vu32 IMSCR;\r
+ vu32 RISR;\r
+ vu32 MISR;\r
+ vu32 ICR;\r
+ vu32 DMACR;\r
+} SSP_TypeDef;\r
+\r
+/*---------------- Universal Asynchronous Receiver Transmitter ---------------*/\r
+typedef struct\r
+{\r
+ vu16 DR;\r
+ u16 EMPTY;\r
+ vu16 RSR;\r
+ u16 EMPTY1[9];\r
+ vu16 FR;\r
+ u16 EMPTY2;\r
+ vu16 BKR;\r
+ u16 EMPTY3[3];\r
+ vu16 IBRD;\r
+ u16 EMPTY4;\r
+ vu16 FBRD;\r
+ u16 EMPTY5;\r
+ vu16 LCR;\r
+ u16 EMPTY6;\r
+ vu16 CR;\r
+ u16 EMPTY7;\r
+ vu16 IFLS;\r
+ u16 EMPTY8;\r
+ vu16 IMSC;\r
+ u16 EMPTY9;\r
+ vu16 RIS;\r
+ u16 EMPTY10;\r
+ vu16 MIS;\r
+ u16 EMPTY11;\r
+ vu16 ICR;\r
+ u16 EMPTY12;\r
+ vu16 DMACR;\r
+ u16 EMPTY13;\r
+} UART_TypeDef;\r
+\r
+/*---------------------------------- WATCHDOG --------------------------------*/\r
+typedef struct\r
+{\r
+ vu16 CR;\r
+ u16 EMPTY1;\r
+ vu16 PR;\r
+ u16 EMPTY2;\r
+ vu16 VR;\r
+ u16 EMPTY3;\r
+ vu16 CNT;\r
+ u16 EMPTY4;\r
+ vu16 SR;\r
+ u16 EMPTY5;\r
+ vu16 MR;\r
+ u16 EMPTY6;\r
+ vu16 KR;\r
+ u16 EMPTY7;\r
+} WDG_TypeDef;\r
+\r
+/*******************************************************************************\r
+* Peripherals' Base addresses\r
+*******************************************************************************/\r
+\r
+#define SRAM_BASE 0x40000000\r
+\r
+#define CONFIG_BASE 0x60000000\r
+\r
+#define SMIR_BASE 0x90000000\r
+\r
+#define PERIPH_BASE 0xFFFF0000\r
+\r
+#define CFG_BASE (CONFIG_BASE + 0x0010)\r
+#define MRCC_BASE (CONFIG_BASE + 0x0020)\r
+#define ADC_BASE (PERIPH_BASE + 0x8400)\r
+#define TB_BASE (PERIPH_BASE + 0x8800)\r
+#define TIM0_BASE (PERIPH_BASE + 0x8C00)\r
+#define TIM1_BASE (PERIPH_BASE + 0x9000)\r
+#define TIM2_BASE (PERIPH_BASE + 0x9400)\r
+#define PWM_BASE (PERIPH_BASE + 0x9800)\r
+#define WDG_BASE (PERIPH_BASE + 0xB000)\r
+#define SSP0_BASE (PERIPH_BASE + 0xB800)\r
+#define SSP1_BASE (PERIPH_BASE + 0xBC00)\r
+#define CAN_BASE (PERIPH_BASE + 0xC400)\r
+#define I2C_BASE (PERIPH_BASE + 0xCC00)\r
+#define UART0_BASE (PERIPH_BASE + 0xD400)\r
+#define UART1_BASE (PERIPH_BASE + 0xD800)\r
+#define UART2_BASE (PERIPH_BASE + 0xDC00)\r
+#define GPIO0_BASE (PERIPH_BASE + 0xE400)\r
+#define GPIOREMAP_BASE (PERIPH_BASE + 0xE420)\r
+#define GPIO1_BASE (PERIPH_BASE + 0xE440)\r
+#define GPIO2_BASE (PERIPH_BASE + 0xE480)\r
+#define DMA_BASE (PERIPH_BASE + 0xECF0)\r
+#define DMA_Stream0_BASE (PERIPH_BASE + 0xEC00)\r
+#define DMA_Stream1_BASE (PERIPH_BASE + 0xEC40)\r
+#define DMA_Stream2_BASE (PERIPH_BASE + 0xEC80)\r
+#define DMA_Stream3_BASE (PERIPH_BASE + 0xECC0)\r
+#define RTC_BASE (PERIPH_BASE + 0xF000)\r
+#define EXTIT_BASE (PERIPH_BASE + 0xF400)\r
+#define EIC_BASE (PERIPH_BASE + 0xF800)\r
+\r
+/*******************************************************************************\r
+ IPs' declaration\r
+*******************************************************************************/\r
+\r
+/*------------------- Non Debug Mode -----------------------------------------*/\r
+\r
+#ifndef DEBUG\r
+ #define SMI ((SMI_TypeDef *) SMIR_BASE)\r
+ #define CFG ((CFG_TypeDef *) CFG_BASE)\r
+ #define MRCC ((MRCC_TypeDef *) MRCC_BASE)\r
+ #define ADC ((ADC_TypeDef *) ADC_BASE)\r
+ #define TB ((TB_TypeDef *) TB_BASE)\r
+ #define TIM0 ((TIM_TypeDef *) TIM0_BASE)\r
+ #define TIM1 ((TIM_TypeDef *) TIM1_BASE)\r
+ #define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+ #define PWM ((PWM_TypeDef *) PWM_BASE)\r
+ #define WDG ((WDG_TypeDef *) WDG_BASE)\r
+ #define SSP0 ((SSP_TypeDef *) SSP0_BASE)\r
+ #define SSP1 ((SSP_TypeDef *) SSP1_BASE)\r
+ #define CAN ((CAN_TypeDef *) CAN_BASE)\r
+ #define I2C ((I2C_TypeDef *) I2C_BASE)\r
+ #define UART0 ((UART_TypeDef *) UART0_BASE)\r
+ #define UART1 ((UART_TypeDef *) UART1_BASE)\r
+ #define UART2 ((UART_TypeDef *) UART2_BASE)\r
+ #define GPIO0 ((GPIO_TypeDef *) GPIO0_BASE)\r
+ #define GPIOREMAP ((GPIOREMAP_TypeDef *) GPIOREMAP_BASE)\r
+ #define GPIO1 ((GPIO_TypeDef *) GPIO1_BASE)\r
+ #define GPIO2 ((GPIO_TypeDef *) GPIO2_BASE)\r
+ #define DMA ((DMA_TypeDef *) DMA_BASE)\r
+ #define DMA_Stream0 ((DMA_Stream_TypeDef *) DMA_Stream0_BASE)\r
+ #define DMA_Stream1 ((DMA_Stream_TypeDef *) DMA_Stream1_BASE)\r
+ #define DMA_Stream2 ((DMA_Stream_TypeDef *) DMA_Stream2_BASE)\r
+ #define DMA_Stream3 ((DMA_Stream_TypeDef *) DMA_Stream3_BASE)\r
+ #define RTC ((RTC_TypeDef *) RTC_BASE)\r
+ #define EXTIT ((EXTIT_TypeDef *) EXTIT_BASE)\r
+ #define EIC ((EIC_TypeDef *) EIC_BASE)\r
+#else /* DEBUG */\r
+ #ifdef _SMI\r
+ EXT SMI_TypeDef *SMI;\r
+ #endif /*_SMI */\r
+\r
+ #ifdef _CFG\r
+ EXT CFG_TypeDef *CFG;\r
+ #endif /*_CFG */\r
+\r
+ #ifdef _MRCC\r
+ EXT MRCC_TypeDef *MRCC;\r
+ #endif /*_MRCC */\r
+\r
+ #ifdef _ADC\r
+ EXT ADC_TypeDef *ADC;\r
+ #endif /*_ADC */ \r
+\r
+ #ifdef _TB\r
+ EXT TB_TypeDef *TB;\r
+ #endif /*_TB */\r
+\r
+ #ifdef _TIM0\r
+ EXT TIM_TypeDef *TIM0;\r
+ #endif /*_TIM0 */\r
+\r
+ #ifdef _TIM1\r
+ EXT TIM_TypeDef *TIM1;\r
+ #endif /*_TIM1 */\r
+\r
+ #ifdef _TIM2\r
+ EXT TIM_TypeDef *TIM2;\r
+ #endif /*_TIM2 */\r
+\r
+ #ifdef _PWM\r
+ EXT PWM_TypeDef *PWM;\r
+ #endif /*_PWM */\r
+\r
+ #ifdef _WDG\r
+ EXT WDG_TypeDef *WDG;\r
+ #endif /*_WDG */\r
+\r
+ #ifdef _SSP0\r
+ EXT SSP_TypeDef *SSP0;\r
+ #endif /*_SSP0 */\r
+\r
+ #ifdef _SSP1\r
+ EXT SSP_TypeDef *SSP1;\r
+ #endif /*_SSP1 */\r
+\r
+ #ifdef _CAN\r
+ EXT CAN_TypeDef *CAN;\r
+ #endif /*_CAN */\r
+\r
+ #ifdef _I2C\r
+ EXT I2C_TypeDef *I2C;\r
+ #endif /*_I2C */\r
+\r
+ #ifdef _UART0\r
+ EXT UART_TypeDef *UART0;\r
+ #endif /*_UART0 */\r
+\r
+ #ifdef _UART1\r
+ EXT UART_TypeDef *UART1;\r
+ #endif /*_UART1 */\r
+\r
+ #ifdef _UART2\r
+ EXT UART_TypeDef *UART2;\r
+ #endif /*_UART2 */\r
+\r
+ #ifdef _GPIO0\r
+ EXT GPIO_TypeDef *GPIO0;\r
+ #endif /*_GPIO0 */\r
+\r
+ #ifdef _GPIOREMAP\r
+ EXT GPIOREMAP_TypeDef *GPIOREMAP;\r
+ #endif /*_GPIOREMAP */\r
+\r
+ #ifdef _GPIO1\r
+ EXT GPIO_TypeDef *GPIO1;\r
+ #endif /*_GPIO1 */\r
+\r
+ #ifdef _GPIO2\r
+ EXT GPIO_TypeDef *GPIO2;\r
+ #endif /*_GPIO2 */\r
+\r
+ #ifdef _DMA\r
+ EXT DMA_TypeDef *DMA;\r
+ #endif /*_DMA */\r
+\r
+ #ifdef _DMA_Stream0\r
+ EXT DMA_Stream_TypeDef *DMA_Stream0;\r
+ #endif /*_DMA_Stream0 */\r
+\r
+ #ifdef _DMA_Stream1\r
+ EXT DMA_Stream_TypeDef *DMA_Stream1;\r
+ #endif /*_DMA_Stream1 */\r
+\r
+ #ifdef _DMA_Stream2\r
+ EXT DMA_Stream_TypeDef *DMA_Stream2;\r
+ #endif /*_DMA_Stream2 */\r
+\r
+ #ifdef _DMA_Stream3\r
+ EXT DMA_Stream_TypeDef *DMA_Stream3;\r
+ #endif /*_DMA_Stream3 */\r
+\r
+ #ifdef _RTC\r
+ EXT RTC_TypeDef *RTC;\r
+ #endif /*_RTC */\r
+\r
+ #ifdef _EXTIT\r
+ EXT EXTIT_TypeDef *EXTIT;\r
+ #endif /*_EXTIT */\r
+\r
+ #ifdef _EIC\r
+ EXT EIC_TypeDef *EIC;\r
+ #endif /*_EIC */\r
+ \r
+#endif /* DEBUG */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+#endif /* __75x_MAP_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_mrcc.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* MRCC software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_MRCC_H\r
+#define __75x_MRCC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* MRCC Buck-up registers */\r
+typedef enum\r
+{\r
+ MRCC_BKP0,\r
+ MRCC_BKP1\r
+}MRCC_BKPReg;\r
+\r
+typedef enum\r
+{\r
+ FREEOSC,\r
+ OSC4MPLL,\r
+ OSC4M,\r
+ CKRTC,\r
+ Disabled,\r
+ OSC4M_Div128,\r
+ LPOSC,\r
+ OSC32K,\r
+ Internal,\r
+ External,\r
+ ON,\r
+ OFF\r
+}CLKSourceTypeDef;\r
+\r
+\r
+typedef struct\r
+{\r
+ CLKSourceTypeDef CKSYS_Source; /* FREEOSC, OSC4MPLL, OSC4M, CKRTC */\r
+ CLKSourceTypeDef CKRTC_Source; /* Disabled, OSC4M_Div128, OSC32K, LPOSC */\r
+ CLKSourceTypeDef CKUSB_Source; /* Disabled, Internal, External */\r
+ CLKSourceTypeDef PLL_Status; /* ON, OFF */\r
+ CLKSourceTypeDef OSC4M_Status; /* ON, OFF */\r
+ CLKSourceTypeDef LPOSC_Status; /* ON, OFF */\r
+ CLKSourceTypeDef OSC32K_Status; /* ON, OFF */\r
+ u32 CKSYS_Frequency; \r
+ u32 HCLK_Frequency; \r
+ u32 CKTIM_Frequency; \r
+ u32 PCLK_Frequency; \r
+}MRCC_ClocksTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Oscillator divider by 2 */\r
+#define MRCC_XTDIV2_Disable 0xFFFF7FFF\r
+#define MRCC_XTDIV2_Enable 0x00008000\r
+\r
+/* System clock source */\r
+#define MRCC_CKSYS_FREEOSC 0x01\r
+#define MRCC_CKSYS_OSC4M 0x02\r
+#define MRCC_CKSYS_OSC4MPLL 0x03\r
+#define MRCC_CKSYS_RTC 0x04\r
+\r
+/* PLL multiplication factors */\r
+#define MRCC_PLL_Disabled 0xFEFFFFFF\r
+#define MRCC_PLL_NoChange 0x00000001\r
+#define MRCC_PLL_Mul_12 0x18000000\r
+#define MRCC_PLL_Mul_14 0x10000000\r
+#define MRCC_PLL_Mul_15 0x08000000\r
+#define MRCC_PLL_Mul_16 0x00000000\r
+\r
+/* AHB clock source */\r
+#define MRCC_CKSYS_Div1 0x00000000\r
+#define MRCC_CKSYS_Div2 0x00000008\r
+#define MRCC_CKSYS_Div4 0x00000010\r
+#define MRCC_CKSYS_Div8 0x00000018\r
+\r
+/* TIM clock source */\r
+#define MRCC_HCLK_Div1 0x00000000\r
+#define MRCC_HCLK_Div2 0x00000001\r
+#define MRCC_HCLK_Div4 0x00000002\r
+#define MRCC_HCLK_Div8 0x00000003\r
+\r
+/* APB clock source */\r
+#define MRCC_CKTIM_Div1 0xFFFFFFFB\r
+#define MRCC_CKTIM_Div2 0x00000004\r
+\r
+/* RTC clock sources */\r
+#define MRCC_CKRTC_OSC4M_Div128 0x01000000\r
+#define MRCC_CKRTC_OSC32K 0x02000000\r
+#define MRCC_CKRTC_LPOSC 0x03000000\r
+\r
+/* USB clock sources */\r
+#define MRCC_CKUSB_Internal 0xFFBFFFFF\r
+#define MRCC_CKUSB_External 0x00400000\r
+\r
+/* MRCC Interrupts */\r
+#define MRCC_IT_LOCK 0x40000000\r
+#define MRCC_IT_NCKD 0x00080000\r
+\r
+/* Peripheral Clock */\r
+#define MRCC_Peripheral_ALL 0x1975623F\r
+#define MRCC_Peripheral_EXTIT 0x10000000\r
+#define MRCC_Peripheral_RTC 0x08000000\r
+#define MRCC_Peripheral_GPIO 0x01000000\r
+#define MRCC_Peripheral_UART2 0x00400000\r
+#define MRCC_Peripheral_UART1 0x00200000\r
+#define MRCC_Peripheral_UART0 0x00100000\r
+#define MRCC_Peripheral_I2C 0x00040000\r
+#define MRCC_Peripheral_CAN 0x00010000\r
+#define MRCC_Peripheral_SSP1 0x00004000\r
+#define MRCC_Peripheral_SSP0 0x00002000\r
+#define MRCC_Peripheral_USB 0x00000200\r
+#define MRCC_Peripheral_PWM 0x00000020\r
+#define MRCC_Peripheral_TIM2 0x00000010\r
+#define MRCC_Peripheral_TIM1 0x00000008\r
+#define MRCC_Peripheral_TIM0 0x00000004\r
+#define MRCC_Peripheral_TB 0x00000002\r
+#define MRCC_Peripheral_ADC 0x00000001\r
+\r
+/* Clock sources to measure theire frequency */\r
+#define MRCC_ClockSource_CKSYS 0x01\r
+#define MRCC_ClockSource_HCLK 0x02\r
+#define MRCC_ClockSource_PCLK 0x03\r
+#define MRCC_ClockSource_CKTIM 0x04\r
+\r
+/* Low Power Debug Mode */\r
+#define MRCC_LPDM_Disable 0xFFFFFFF7\r
+#define MRCC_LPDM_Enable 0x00000008\r
+\r
+/* WFI Mode parameters */\r
+#define MRCC_WFIParam_FLASHPowerDown 0x00000000\r
+#define MRCC_WFIParam_FLASHOn 0x00000010\r
+#define MRCC_WFIParam_FLASHOff 0x00004000\r
+\r
+/* STOP Mode parameters */\r
+#define MRCC_STOPParam_Default 0x00000000\r
+#define MRCC_STOPParam_OSC4MOff 0x00008000\r
+#define MRCC_STOPParam_FLASHOff 0x00004000\r
+#define MRCC_STOPParam_MVREGOff 0x00002000\r
+\r
+/* I/O Pins voltage range */\r
+#define MRCC_IOVoltageRange_5V 0xFFFEFFFF\r
+#define MRCC_IOVoltageRange_3V3 0x00010000\r
+\r
+/* Clock sources to output on MCO pin */\r
+#define MRCC_MCO_HCLK 0x00000000\r
+#define MRCC_MCO_PCLK 0x00000040\r
+#define MRCC_MCO_OSC4M 0x00000080\r
+#define MRCC_MCO_CKPLL2 0x000000C0\r
+#define MRCC_MCOPrescaler_1 0xFFFFFFDF\r
+#define MRCC_MCOPrescaler_2 0x00000020\r
+\r
+/* 4MHz main oscillator configuration */\r
+#define MRCC_OSC4M_Default 0xFFFCFFFF\r
+#define MRCC_OSC4M_Disable 0x00020000\r
+#define MRCC_OSC4M_Bypass 0x00010000\r
+\r
+/* OSC32K oscillator configuration */\r
+#define MRCC_OSC32K_Disable 0xDFFFFFFF\r
+#define MRCC_OSC32K_Enable 0x20000000\r
+#define MRCC_OSC32KBypass_Disable 0xBFFFFFFF\r
+#define MRCC_OSC32KBypass_Enable 0x40000000\r
+\r
+/* LPOSC oscillator configuration */\r
+#define MRCC_LPOSC_Disable 0xEFFFFFFF\r
+#define MRCC_LPOSC_Enable 0x10000000\r
+\r
+/* RTC measurement configuration */\r
+#define MRCC_RTCM_Disable 0xFBFFFFFF\r
+#define MRCC_RTCM_Enable 0x04000000\r
+\r
+/* MRCC Flags */\r
+#define MRCC_FLAG_LOCK 0x3F\r
+#define MRCC_FLAG_LOCKIF 0x3D\r
+#define MRCC_FLAG_CKSEL 0x37\r
+#define MRCC_FLAG_CKOSCSEL 0x35\r
+#define MRCC_FLAG_NCKD 0x32\r
+#define MRCC_FLAG_SWR 0x5D\r
+#define MRCC_FLAG_WDGR 0x5C\r
+#define MRCC_FLAG_EXTR 0x5B\r
+#define MRCC_FLAG_WKP 0x5A\r
+#define MRCC_FLAG_STDB 0x59\r
+#define MRCC_FLAG_BCOUNT 0x58\r
+#define MRCC_FLAG_OSC32KRDY 0x7F\r
+#define MRCC_FLAG_CKRTCOK 0x7B\r
+#define MRCC_FLAG_LPDONE 0x67\r
+#define MRCC_FLAG_LP 0x60\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void MRCC_DeInit(void);\r
+void MRCC_XTDIV2Config(u32 MRCC_XTDIV2);\r
+ErrorStatus MRCC_CKSYSConfig(u32 MRCC_CKSYS, u32 MRCC_PLL);\r
+void MRCC_HCLKConfig(u32 MRCC_HCLK);\r
+void MRCC_CKTIMConfig(u32 MRCC_CKTIM);\r
+void MRCC_PCLKConfig(u32 MRCC_PCLK);\r
+ErrorStatus MRCC_CKRTCConfig(u32 MRCC_CKRTC);\r
+ErrorStatus MRCC_CKUSBConfig(u32 MRCC_CKUSB);\r
+void MRCC_ITConfig(u32 MRCC_IT, FunctionalState NewState);\r
+void MRCC_PeripheralClockConfig(u32 MRCC_Peripheral, FunctionalState NewState);\r
+void MRCC_PeripheralSWResetConfig(u32 MRCC_Peripheral, FunctionalState NewState);\r
+void MRCC_GetClocksStatus(MRCC_ClocksTypeDef* MRCC_ClocksStatus);\r
+void MRCC_LPMC_DBGConfig(u32 MRCC_LPDM);\r
+void MRCC_EnterWFIMode(u32 MRCC_WFIParam);\r
+void MRCC_EnterSTOPMode(u32 MRCC_STOPParam);\r
+void MRCC_EnterSTANDBYMode(void);\r
+void MRCC_GenerateSWReset(void);\r
+void MRCC_WriteBackupRegister(MRCC_BKPReg MRCC_BKP, u32 Data);\r
+u32 MRCC_ReadBackupRegister(MRCC_BKPReg MRCC_BKP);\r
+void MRCC_IOVoltageRangeConfig(u32 MRCC_IOVoltageRange);\r
+void MRCC_MCOConfig(u32 MRCC_MCO, u32 MCO_MCOPrescaler);\r
+ErrorStatus MRCC_OSC4MConfig(u32 MRCC_OSC4M);\r
+ErrorStatus MRCC_OSC32KConfig(u32 MRCC_OSC32K, u32 MRCC_OSC32KBypass);\r
+ErrorStatus MRCC_LPOSCConfig(u32 MRCC_LPOSC);\r
+void MRCC_RTCMConfig(u32 MRCC_RTCM);\r
+void MRCC_SetBuilderCounter(u8 BuilderCounter);\r
+u16 MRCC_GetCKSYSCounter(void);\r
+FlagStatus MRCC_GetFlagStatus(u8 MRCC_FLAG);\r
+void MRCC_ClearFlag(u8 MRCC_FLAG);\r
+ITStatus MRCC_GetITStatus(u32 MRCC_IT);\r
+void MRCC_ClearITPendingBit(u32 MRCC_IT);\r
+ErrorStatus MRCC_WaitForOSC4MStartUp(void);\r
+\r
+#endif /* __75x_MRCC_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_pwm.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the functions prototypes for the \r
+* PWM software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_PWM_H\r
+#define __75x_PWM_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+typedef struct\r
+{\r
+ u16 PWM_Mode; /* PWM Mode */\r
+ u16 PWM_Prescaler; /* Prescaler value */\r
+ u16 PWM_CounterMode; /* Counter mode: Up/Down, Edge aligned or center aligned */\r
+ u16 PWM_Period; /* Period value */\r
+ u16 PWM_Complementary; /* Complementary PWM selection */\r
+ u16 PWM_OCState; /* Output compare off-state in Run mode */\r
+ u16 PWM_OCNState; /* Complementary Output compare off-state in Run mode */\r
+ u16 PWM_Channel; /* PWM Channel: 1, 2 or 3 */\r
+ u16 PWM_Pulse1; /* PWM or OCM Channel 1 pulse length */\r
+ u16 PWM_Pulse2; /* PWM or OCM Channel 2 pulse length */\r
+ u16 PWM_Pulse3; /* PWM or OCM Channel 3 pulse length */\r
+ u16 PWM_Polarity1; /* PWM, OCM or OPM Channel 1 polarity */\r
+ u16 PWM_Polarity2; /* PWM or OCM Channel 2 polarity */\r
+ u16 PWM_Polarity3; /* PWM or OCM Channel 3 polarity */\r
+ u16 PWM_Polarity1N; /* PWM or OCM Channel 1N polarity */\r
+ u16 PWM_Polarity2N; /* PWM or OCM Channel 2N polarity */\r
+ u16 PWM_Polarity3N; /* PWM or OCM Channel 3N polarity */\r
+ u16 PWM_DTRAccess; /* Enable or disable the configuration of DTR register parameters:\r
+ DeadTime, Emergency, LOCKLevel, OSSIState, OCState and OCNState */\r
+ u16 PWM_DeadTime; /* Dead Time value */\r
+ u16 PWM_Emergency; /* Emergency selection: Enable / Disable */\r
+ u16 PWM_LOCKLevel; /* LOCK level */\r
+ u16 PWM_OSSIState; /* Off-State Selection for Idle state */\r
+ u8 PWM_RepetitionCounter; /* Repetition counter value */\r
+} PWM_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* PWM modes */\r
+#define PWM_Mode_OCTiming 0x0001\r
+#define PWM_Mode_OCActive 0x0002\r
+#define PWM_Mode_OCInactive 0x0003\r
+#define PWM_Mode_OCToggle 0x0004\r
+#define PWM_Mode_PWM 0x0005\r
+\r
+/* PWM Counter Mode */\r
+#define PWM_CounterMode_Up 0x0000\r
+#define PWM_CounterMode_Down 0x0010\r
+#define PWM_CounterMode_CenterAligned1 0x0020\r
+#define PWM_CounterMode_CenterAligned2 0x0040\r
+#define PWM_CounterMode_CenterAligned3 0x0060\r
+\r
+/* PWM Channel */\r
+#define PWM_Channel_1 0x0001\r
+#define PWM_Channel_2 0x0002\r
+#define PWM_Channel_3 0x0004\r
+#define PWM_Channel_ALL 0x0007\r
+\r
+/* PWM Polarity channel 1 */\r
+#define PWM_Polarity1_High 0x0001\r
+#define PWM_Polarity1_Low 0x0002\r
+\r
+/* PWM Polarity channel 2 */\r
+#define PWM_Polarity2_High 0x0001\r
+#define PWM_Polarity2_Low 0x0002\r
+\r
+/* PWM Polarity channel 3 */\r
+#define PWM_Polarity3_High 0x0001\r
+#define PWM_Polarity3_Low 0x0002\r
+\r
+/* PWM Polarity channel 1N */\r
+#define PWM_Polarity1N_High 0x0001\r
+#define PWM_Polarity1N_Low 0x0002\r
+\r
+/* PWM Polarity channel 2N */\r
+#define PWM_Polarity2N_High 0x0001\r
+#define PWM_Polarity2N_Low 0x0002\r
+\r
+/* PWM Polarity channel 3N */\r
+#define PWM_Polarity3N_High 0x0001\r
+#define PWM_Polarity3N_Low 0x0002\r
+\r
+/* PWM interrupt sources */\r
+#define PWM_IT_OC1 0x0100\r
+#define PWM_IT_OC2 0x0200\r
+#define PWM_IT_OC3 0x0400\r
+#define PWM_IT_Update 0x0001\r
+#define PWM_IT_GlobalUpdate 0x1001\r
+#define PWM_IT_Emergency 0x8000\r
+\r
+/* PWM DMA sources */\r
+#define PWM_DMASource_OC1 0x0100\r
+#define PWM_DMASource_OC2 0x0200\r
+#define PWM_DMASource_OC3 0x0400\r
+#define PWM_DMASource_Update 0x0001\r
+\r
+/* PWM DMA Base address */\r
+#define PWM_DMABase_CR 0x0000\r
+#define PWM_DMABase_SCR 0x0800\r
+#define PWM_DMABase_OMR1 0x1800\r
+#define PWM_DMABase_OMR2 0x2000\r
+#define PWM_DMABase_RSR 0x3000\r
+#define PWM_DMABase_RER 0x3800\r
+#define PWM_DMABase_ISR 0x4000\r
+#define PWM_DMABase_CNT 0x4800\r
+#define PWM_DMABase_PSC 0x5000\r
+#define PWM_DMABase_RCR 0x5800\r
+#define PWM_DMABase_ARR 0x6000\r
+#define PWM_DMABase_OCR1 0x6800\r
+#define PWM_DMABase_OCR2 0x7000\r
+#define PWM_DMABase_OCR3 0x7800\r
+#define PWM_DMABase_DTR 0xB800\r
+\r
+/* PWM OCM state */\r
+#define PWM_OCRMState_Enable 0x0005\r
+#define PWM_OCRMState_Disable 0x0006\r
+\r
+/* PWM Flags */\r
+#define PWM_FLAG_OC1 0x0100\r
+#define PWM_FLAG_OC2 0x0200\r
+#define PWM_FLAG_OC3 0x0400\r
+#define PWM_FLAG_Update 0x0001\r
+#define PWM_FLAG_Emergency 0x8000\r
+\r
+/* PWM_ForcedAction */\r
+#define PWM_ForcedAction_Active 0x000A\r
+#define PWM_ForcedAction_InActive 0x0008\r
+\r
+/* PWM TRGO Mode */\r
+#define PWM_TRGOMode_Enable 0x0100\r
+#define PWM_TRGOMode_Update 0x0200\r
+#define PWM_TRGOMode_Reset 0x0000\r
+#define PWM_TRGOMode_OC 0x0300\r
+\r
+/* PWM Complementary outputs Enable/Disable */\r
+#define PWM_Complementary_Disable 0x0001\r
+#define PWM_Complementary_Enable 0x0002\r
+\r
+/* PWM DTR Access Enable/Disable */\r
+#define PWM_DTRAccess_Enable 0x0001\r
+#define PWM_DTRAccess_Disable 0x0002\r
+\r
+/* PWM Emergency input Enable/Disable */\r
+#define PWM_Emergency_Disable 0x0000\r
+#define PWM_Emergency_Enable 0x1000\r
+\r
+/* OC states */\r
+#define PWM_OCNState_Disable 0x0001\r
+#define PWM_OCNState_Enable 0x0002\r
+#define PWM_OCNState_OffState 0x0003\r
+\r
+/* OCN states */\r
+#define PWM_OCState_Disable 0x0004\r
+#define PWM_OCState_Enable 0x0005\r
+#define PWM_OCState_OffState 0x0006\r
+\r
+/* PWM LOCK level */\r
+#define PWM_LOCKLevel_1 0x0400\r
+#define PWM_LOCKLevel_2 0x0800\r
+#define PWM_LOCKLevel_3 0x0C00\r
+#define PWM_LOCKLevel_OFF 0x0000\r
+\r
+/* Off State selection for Idle state */\r
+#define PWM_OSSIState_Disable 0x0000\r
+#define PWM_OSSIState_Enable 0x2000\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+void PWM_DeInit(void);\r
+void PWM_Init(PWM_InitTypeDef* PWM_InitStruct);\r
+void PWM_StructInit(PWM_InitTypeDef *PWM_InitStruct);\r
+void PWM_Cmd(FunctionalState Newstate);\r
+void PWM_CtrlPWMOutputs(FunctionalState Newstate); \r
+void PWM_ITConfig(u16 PWM_IT, FunctionalState Newstate);\r
+void PWM_DMAConfig(u16 PWM_DMASources, u16 PWM_OCRMState, u16 PWM_DMABase);\r
+void PWM_DMACmd(u16 PWM_DMASources, FunctionalState Newstate);\r
+void PWM_SetPrescaler(u16 Prescaler);\r
+void PWM_SetPeriod(u16 Period);\r
+void PWM_SetPulse(u16 PWM_Channel, u16 Pulse);\r
+void PWM_SetPulse1(u16 Pulse);\r
+void PWM_SetPulse2(u16 Pulse);\r
+void PWM_SetPulse3(u16 Pulse);\r
+void PWM_DebugCmd(FunctionalState Newstate);\r
+void PWM_CounterModeConfig(u16 PWM_CounterMode);\r
+void PWM_ForcedOCConfig(u16 PWM_Channel, u16 PWM_ForcedAction);\r
+void PWM_SetDeadTime(u16 DeadTime);\r
+void PWM_ResetCounter(void);\r
+void PWM_TRGOSelection(u16 PWM_TRGOMode);\r
+FlagStatus PWM_GetFlagStatus(u16 PWM_FLAG);\r
+void PWM_ClearFlag(u16 PWM_FLAG);\r
+ITStatus PWM_GetITStatus(u16 PWM_IT);\r
+void PWM_ClearITPendingBit(u16 PWM_IT);\r
+\r
+#endif /* __75x_PWM_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_rtc.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* RTC software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_RTC_H\r
+#define __75x_RTC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* RTC interrupts define */\r
+#define RTC_IT_Overflow 0x0004 /* Overflow interrupt */\r
+#define RTC_IT_Alarm 0x0002 /* Alarm interrupt */\r
+#define RTC_IT_Second 0x0001 /* Second interrupt */\r
+\r
+/* RTC interrupts flags */\r
+#define RTC_FLAG_RTOFF 0x0020 /* RTC Operation OFF flag */\r
+#define RTC_FLAG_RSF 0x0008 /* Registers Synchronized flag */\r
+#define RTC_FLAG_Overflow 0x0004 /* Overflow interrupt flag */\r
+#define RTC_FLAG_Alarm 0x0002 /* Alarm interrupt flag */\r
+#define RTC_FLAG_Second 0x0001 /* Second interrupt flag */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void RTC_DeInit(void);\r
+void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState);\r
+void RTC_EnterConfigMode(void);\r
+void RTC_ExitConfigMode(void);\r
+u32 RTC_GetCounter(void);\r
+void RTC_SetCounter(u32 CounterValue);\r
+void RTC_SetPrescaler(u32 PrescalerValue);\r
+u32 RTC_GetPrescaler(void);\r
+void RTC_SetAlarm(u32 AlarmValue);\r
+u32 RTC_GetDivider(void);\r
+void RTC_WaitForLastTask(void);\r
+void RTC_WaitForSynchro(void);\r
+FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG);\r
+void RTC_ClearFlag(u16 RTC_FLAG);\r
+ITStatus RTC_GetITStatus(u16 RTC_IT);\r
+void RTC_ClearITPendingBit(u16 RTC_IT);\r
+\r
+#endif /* __75x_RTC_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_smi.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* SMI software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_SMI_H\r
+#define __75x_SMI_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ u8 SMI_ClockHold;\r
+ u8 SMI_Prescaler;\r
+ u8 SMI_DeselectTime;\r
+} SMI_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* SMI mode */\r
+#define SMI_Mode_HW 0xEFFFFFFF\r
+#define SMI_Mode_SW 0x10000000\r
+\r
+/* Reception Length */\r
+#define SMI_RxLength_0Bytes 0x00000000\r
+#define SMI_RxLength_1Byte 0x00000010\r
+#define SMI_RxLength_2Bytes 0x00000020\r
+#define SMI_RxLength_3Bytes 0x00000030\r
+#define SMI_RxLength_4Bytes 0x00000040\r
+\r
+/* Transmission Length */\r
+#define SMI_TxLength_0Bytes 0x00000000\r
+#define SMI_TxLength_1Byte 0x00000001\r
+#define SMI_TxLength_2Bytes 0x00000002\r
+#define SMI_TxLength_3Bytes 0x00000003\r
+#define SMI_TxLength_4Bytes 0x00000004\r
+\r
+/* SMI memory Banks */\r
+#define SMI_Bank_0 0x00000001\r
+#define SMI_Bank_1 0x00000002\r
+#define SMI_Bank_2 0x00000004\r
+#define SMI_Bank_3 0x00000008\r
+\r
+/* SMI Interrupts */\r
+#define SMI_IT_WC 0x00000200\r
+#define SMI_IT_TF 0x00000100\r
+\r
+/* Fast Read Mode */\r
+#define SMI_FastRead_Disable 0xFFFF7FFF\r
+#define SMI_FastRead_Enable 0x00008000\r
+\r
+/* Write Burst Mode */\r
+#define SMI_WriteBurst_Disable 0xDFFFFFFF\r
+#define SMI_WriteBurst_Enable 0x20000000\r
+\r
+/* SMI Flags */\r
+#define SMI_FLAG_Bank3_WM 0x00008000\r
+#define SMI_FLAG_Bank2_WM 0x00004000\r
+#define SMI_FLAG_Bank1_WM 0x00002000\r
+#define SMI_FLAG_Bank0_WM 0x00001000\r
+#define SMI_FLAG_ERF2 0x00000800\r
+#define SMI_FLAG_ERF1 0x00000400\r
+#define SMI_FLAG_WC 0x00000200\r
+#define SMI_FLAG_TF 0x00000100\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void SMI_DeInit(void); \r
+void SMI_Init(SMI_InitTypeDef* SMI_InitStruct); \r
+void SMI_StructInit(SMI_InitTypeDef* SMI_InitStruct);\r
+void SMI_ModeConfig(u32 SMI_Mode);\r
+void SMI_TxRxLengthConfig(u32 SMI_TxLength, u32 SMI_RxLength); \r
+void SMI_BankCmd(u32 SMI_Bank, FunctionalState NewState); \r
+void SMI_ITConfig(u32 SMI_IT, FunctionalState NewState); \r
+void SMI_SelectBank(u32 SMI_Bank); \r
+void SMI_SendWENCmd(void); \r
+void SMI_SendRSRCmd(void);\r
+void SMI_SendCmd(u32 Command);\r
+void SMI_FastReadConfig(u32 SMI_FastRead);\r
+void SMI_WriteBurstConfig(u32 SMI_WriteBurst);\r
+void SMI_WriteByte(u32 WriteAddr, u8 Data);\r
+void SMI_WriteHalfWord(u32 WriteAddr, u16 Data);\r
+void SMI_WriteWord(u32 WriteAddr, u32 Data);\r
+u8 SMI_ReadByte(u32 ReadAddr);\r
+u16 SMI_ReadHalfWord(u32 ReadAddr);\r
+u32 SMI_ReadWord(u32 ReadAddr);\r
+u8 SMI_ReadMemoryStatusRegister(void);\r
+FlagStatus SMI_GetFlagStatus(u32 SMI_FLAG);\r
+void SMI_ClearFlag(u32 SMI_FLAG);\r
+ITStatus SMI_GetITStatus(u32 SMI_IT);\r
+void SMI_ClearITPendingBit(u32 SMI_IT);\r
+\r
+#endif /* __75x_SMI_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_SSP.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* SSP software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1 \r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, \r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING \r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_SSP_H\r
+#define __75x_SSP_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* SSP Init structure definition */\r
+typedef struct\r
+{\r
+ u16 SSP_FrameFormat;\r
+ u16 SSP_Mode;\r
+ u16 SSP_CPOL;\r
+ u16 SSP_CPHA;\r
+ u16 SSP_DataSize;\r
+ u16 SSP_NSS;\r
+ u16 SSP_SlaveOutput;\r
+ u8 SSP_ClockRate;\r
+ u8 SSP_ClockPrescaler;\r
+}SSP_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* SSP Frame Format Select */\r
+#define SSP_FrameFormat_TI 0x0010\r
+#define SSP_FrameFormat_Motorola 0xFFCF\r
+\r
+/* SSP Master/Slave Select */\r
+#define SSP_Mode_Master 0xFFFB\r
+#define SSP_Mode_Slave 0x0004\r
+\r
+/* SSP Clock Polarity */\r
+#define SSP_CPOL_Low 0xFFBF\r
+#define SSP_CPOL_High 0x0040\r
+\r
+/* SSP Clock Phase */\r
+#define SSP_CPHA_1Edge 0xFF7F\r
+#define SSP_CPHA_2Edge 0x0080\r
+\r
+/* SSP Data Size */\r
+#define SSP_DataSize_16b 0x000F\r
+#define SSP_DataSize_15b 0x000E\r
+#define SSP_DataSize_14b 0x000D\r
+#define SSP_DataSize_13b 0x000C\r
+#define SSP_DataSize_12b 0x000B\r
+#define SSP_DataSize_11b 0x000A\r
+#define SSP_DataSize_10b 0x0009\r
+#define SSP_DataSize_9b 0x0008\r
+#define SSP_DataSize_8b 0x0007\r
+#define SSP_DataSize_7b 0x0006\r
+#define SSP_DataSize_6b 0x0005\r
+#define SSP_DataSize_5b 0x0004\r
+#define SSP_DataSize_4b 0x0003\r
+\r
+/* SSP Slave Select management config */\r
+#define SSP_NSS_Hard 0xFFEF\r
+#define SSP_NSS_Soft 0x0010\r
+\r
+/* SSP NSS internal config */\r
+#define SSP_NSSInternal_Set 0x0020\r
+#define SSP_NSSInternal_Reset 0xFFDF\r
+\r
+/* SSP Slave output config */\r
+#define SSP_SlaveOutput_Enable 0xFFF7\r
+#define SSP_SlaveOutput_Disable 0x0008\r
+\r
+/* SSP Interrupts */\r
+#define SSP_IT_TxFifo 0x0008\r
+#define SSP_IT_RxFifo 0x0004\r
+#define SSP_IT_RxTimeOut 0x0002\r
+#define SSP_IT_RxOverrun 0x0001\r
+\r
+/* SSP Flags */\r
+#define SSP_FLAG_Busy 0x0024\r
+#define SSP_FLAG_RxFifoFull 0x0023\r
+#define SSP_FLAG_RxFifoNotEmpty 0x0022\r
+#define SSP_FLAG_TxFifoNotFull 0x0021\r
+#define SSP_FLAG_TxFifoEmpty 0x0020\r
+#define SSP_FLAG_TxFifo 0x0043\r
+#define SSP_FLAG_RxFifo 0x0042\r
+#define SSP_FLAG_RxTimeOut 0x0041\r
+#define SSP_FLAG_RxOverrun 0x0040\r
+\r
+/* SSP DMA Requests */\r
+#define SSP0_DMA_Transmit 0x0002\r
+#define SSP0_DMA_Receive 0x0001\r
+\r
+#define SSP0_DMATxReq_Single 0xFFF7\r
+#define SSP0_DMATxReq_Burst 0x0008\r
+\r
+#define SSP0_DMARxReq_Single 0xFFFB\r
+#define SSP0_DMARxReq_Burst 0x0004\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void SSP_DeInit(SSP_TypeDef* SSPx);\r
+void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct);\r
+void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct);\r
+void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState);\r
+void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState);\r
+void SSP_DMACmd(u16 SSP0_DMAtransfer, FunctionalState NewState);\r
+void SSP_DMATxConfig(u16 SSP0_DMATxReq);\r
+void SSP_DMARxConfig(u16 SSP0_DMARxReq);\r
+void SSP_SendData(SSP_TypeDef* SSPx, u16 Data);\r
+u16 SSP_ReceiveData(SSP_TypeDef* SSPx);\r
+void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState);\r
+void SSP_NSSInternalConfig(SSP_TypeDef* SSPx, u16 SSP_NSSState);\r
+FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG);\r
+void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG);\r
+ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT);\r
+void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT);\r
+\r
+#endif /* __75x_SSP_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_tb.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the functions prototypes for the \r
+* TB software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_TB_H\r
+#define __75x_TB_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ u16 TB_Mode; /* TB mode */\r
+ u16 TB_ClockSource; /* TB clock source: CK_TIM or CK_RTC */\r
+ u16 TB_CounterMode; /* TB counter mode */\r
+ u16 TB_ICAPolarity; /* TB Input Capture signal Polarity */\r
+ u16 TB_Prescaler; /* TB Prescaler factor */\r
+ u16 TB_AutoReload; /* TB AutoReload factor */\r
+} TB_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* TB modes */\r
+#define TB_Mode_IC 0x0002\r
+#define TB_Mode_Timing 0x0001\r
+\r
+/* TB clock source */\r
+#define TB_ClockSource_CKTIM 0x0001\r
+#define TB_ClockSource_CKRTC 0x0002\r
+\r
+/* TB Input capture polarity */\r
+#define TB_ICAPolarity_Rising 0x7000\r
+#define TB_ICAPolarity_Falling 0x8000\r
+\r
+/* TB counter modes */\r
+#define TB_CounterMode_Up 0x0000\r
+#define TB_CounterMode_Down 0x0010\r
+#define TB_CounterMode_CenterAligned 0x0060\r
+\r
+/* TB interrupt sources */\r
+#define TB_IT_Update 0x0001\r
+#define TB_IT_IC 0x0004\r
+#define TB_IT_GlobalUpdate 0x8001\r
+\r
+/* TB Flags */\r
+#define TB_FLAG_IC 0x0004\r
+#define TB_FLAG_Update 0x0001\r
+\r
+/* TB Slave Mode Selection */\r
+#define TB_SMSMode_Trigger 0x0018\r
+#define TB_SMSMode_Gated 0x0010\r
+#define TB_SMSMode_External 0x0008 \r
+#define TB_SMSMode_Reset 0x0000\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void TB_DeInit(void);\r
+void TB_Init(TB_InitTypeDef* TB_InitStruct);\r
+void TB_StructInit(TB_InitTypeDef *TB_InitStruct);\r
+void TB_Cmd(FunctionalState Newstate );\r
+void TB_ITConfig(u16 TB_IT, FunctionalState Newstate);\r
+void TB_SetPrescaler(u16 Prescaler);\r
+void TB_ResetCounter(void);\r
+void TB_DebugCmd(FunctionalState Newstate);\r
+void TB_CounterModeConfig(u16 TB_CounterMode);\r
+void TB_SLaveModeConfig(u16 TB_SMSMode);\r
+u16 TB_GetCounter(void);\r
+u16 TB_GetICAP1(void);\r
+void TB_SetCounter(u16 Counter);\r
+FlagStatus TB_GetFlagStatus(u16 TB_FLAG);\r
+void TB_ClearFlag(u16 TB_FLAG);\r
+ITStatus TB_GetITStatus(u16 TB_IT);\r
+void TB_ClearITPendingBit(u16 TB_IT);\r
+\r
+#endif /* __75x_TB_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_tim.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the functions prototypes for the \r
+* TIM software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_TIM_H\r
+#define __75x_TIM_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ u16 TIM_Mode; /* Timer Mode */\r
+ u16 TIM_Prescaler; /* Prescaler value */\r
+ u16 TIM_ClockSource; /* Timer clock source */\r
+ u16 TIM_ExtCLKEdge; /* External clock edge */\r
+ u16 TIM_CounterMode; /* Counter mode: Up/Down, Edge aligned or center aligned */\r
+ u16 TIM_Period; /* Period value */\r
+ u16 TIM_Channel; /* Timer Channel: 1, 2 or All */\r
+ u16 TIM_Pulse1; /* PWM or OCM Channel 1 pulse length */\r
+ u16 TIM_Pulse2; /* PWM or OCM Channel 2 pulse length */\r
+ u16 TIM_RepetitivePulse; /* OPM Repetitive pulse state: enable or disable */\r
+ u16 TIM_Polarity1; /* PWM, OCM or OPM Channel 1 polarity */\r
+ u16 TIM_Polarity2; /* PWM or OCM Channel 2 polarity */\r
+ u16 TIM_IC1Selection; /* Input Capture 1 selection: TI1 or TI2 */\r
+ u16 TIM_IC2Selection; /* Input Capture 2 selection: TI1 or TI2 */\r
+ u16 TIM_IC1Polarity; /* Input Capture 1 polarity */\r
+ u16 TIM_IC2Polarity; /* Input Capture 2 polarity */\r
+ u16 TIM_PWMI_ICSelection; /* PWM Input Capture selection: TI1 or TI2 */\r
+ u16 TIM_PWMI_ICPolarity; /* PWM Input Capture Polarity */\r
+} TIM_InitTypeDef;\r
+\r
+/* Master and slave synchronized Timer peripherals */\r
+typedef enum\r
+{\r
+ PWM_Master = 0x01,\r
+ TIM0_Master,\r
+ TIM1_Master,\r
+ TIM2_Master\r
+}Master_TypeDef;\r
+\r
+typedef enum\r
+{\r
+ PWM_Slave = 0x05,\r
+ TIM0_Slave,\r
+ TIM1_Slave,\r
+ TIM2_Slave\r
+}Slave_TypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* TIM modes */\r
+#define TIM_Mode_OCTiming 0x0001\r
+#define TIM_Mode_OCActive 0x0002\r
+#define TIM_Mode_OCInactive 0x0003\r
+#define TIM_Mode_OCToggle 0x0004\r
+#define TIM_Mode_PWM 0x0005\r
+#define TIM_Mode_PWMI 0x0006\r
+#define TIM_Mode_IC 0x0007\r
+#define TIM_Mode_Encoder1 0x0008\r
+#define TIM_Mode_Encoder2 0x0009\r
+#define TIM_Mode_Encoder3 0x000A\r
+#define TIM_Mode_OPM_PWM 0x000B\r
+#define TIM_Mode_OPM_Toggle 0x000C\r
+#define TIM_Mode_OPM_Active 0x000D\r
+\r
+/* TIM Clock Source */\r
+#define TIM_ClockSource_Internal 0x0001\r
+#define TIM_ClockSource_TI11 0x0002\r
+#define TIM_ClockSource_TI12 0x0003\r
+#define TIM_ClockSource_TI22 0x0004\r
+#define TIM_ClockSource_TI21 0x0005\r
+\r
+/* TIM External Clock Edge */\r
+#define TIM_ExtCLKEdge_Falling 0x0001\r
+#define TIM_ExtCLKEdge_Rising 0x0002\r
+\r
+/* TIM Counter Mode */\r
+#define TIM_CounterMode_Up 0x0000\r
+#define TIM_CounterMode_Down 0x0010\r
+#define TIM_CounterMode_CenterAligned1 0x0020\r
+#define TIM_CounterMode_CenterAligned2 0x0040\r
+#define TIM_CounterMode_CenterAligned3 0x0060\r
+\r
+/* TIM Channel */\r
+#define TIM_Channel_1 0x0001\r
+#define TIM_Channel_2 0x0002\r
+#define TIM_Channel_ALL 0x0003\r
+\r
+/* TIM Polarity channel 1 */\r
+#define TIM_Polarity1_High 0x0001\r
+#define TIM_Polarity1_Low 0x0002\r
+\r
+/* TIM Polarity channel 2 */\r
+#define TIM_Polarity2_High 0x0001\r
+#define TIM_Polarity2_Low 0x0002\r
+\r
+#define TIM_RepetitivePulse_Disable 0x0005\r
+#define TIM_RepetitivePulse_Enable 0x0006\r
+\r
+/* TIM Input Capture channel 1 Selection */\r
+#define TIM_IC1Selection_TI1 0x0001\r
+#define TIM_IC1Selection_TI2 0x0002\r
+\r
+/* TIM Input Capture channel 2 Selection */\r
+#define TIM_IC2Selection_TI1 0x0001\r
+#define TIM_IC2Selection_TI2 0x0002\r
+\r
+/* TIM Input Capture channel 1 Polarity */\r
+#define TIM_IC1Polarity_Falling 0x0001\r
+#define TIM_IC1Polarity_Rising 0x0002\r
+\r
+/* TIM Input Capture channel 2 Polarity */\r
+#define TIM_IC2Polarity_Falling 0x0001\r
+#define TIM_IC2Polarity_Rising 0x0002\r
+\r
+/* TIM PWM Input IC Selection */\r
+#define TIM_PWMI_ICSelection_TI1 0x0001\r
+#define TIM_PWMI_ICSelection_TI2 0x0002\r
+\r
+/* TIM PWM Input IC Polarity */\r
+#define TIM_PWMI_ICPolarity_Falling 0x0003\r
+#define TIM_PWMI_ICPolarity_Rising 0x0004\r
+\r
+/* TIM interrupt sources */\r
+#define TIM_IT_IC1 0x0004\r
+#define TIM_IT_IC2 0x0008\r
+#define TIM_IT_OC1 0x0100\r
+#define TIM_IT_OC2 0x0200\r
+#define TIM_IT_Update 0x0001\r
+#define TIM_IT_GlobalUpdate 0x1001\r
+\r
+/* TIM DMA sources */\r
+#define TIM_DMASource_IC1 0x0004\r
+#define TIM_DMASource_IC2 0x0008\r
+#define TIM_DMASource_OC1 0x0100\r
+#define TIM_DMASource_OC2 0x0200\r
+#define TIM_DMASource_Update 0x0001\r
+\r
+/* TIM DMA Base address */\r
+#define TIM_DMABase_CR 0x0000\r
+#define TIM_DMABase_SCR 0x0800\r
+#define TIM_DMABase_IMCR 0x1000\r
+#define TIM_DMABase_OMR1 0x1800\r
+#define TIM_DMABase_RSR 0x3000\r
+#define TIM_DMABase_RER 0x3800\r
+#define TIM_DMABase_ISR 0x4000\r
+#define TIM_DMABase_CNT 0x4800\r
+#define TIM_DMABase_PSC 0x5000\r
+#define TIM_DMABase_ARR 0x6000\r
+#define TIM_DMABase_OCR1 0x6800\r
+#define TIM_DMABase_OCR2 0x7000\r
+#define TIM_DMABase_ICR1 0x9800\r
+#define TIM_DMABase_ICR2 0xA000\r
+\r
+/* TIM Flags */\r
+#define TIM_FLAG_IC1 0x0004\r
+#define TIM_FLAG_IC2 0x0008\r
+#define TIM_FLAG_OC1 0x0100\r
+#define TIM_FLAG_OC2 0x0200\r
+#define TIM_FLAG_Update 0x0001\r
+\r
+/* TIM_ForcedAction */\r
+#define TIM_ForcedAction_Active 0x000A\r
+#define TIM_ForcedAction_InActive 0x0008\r
+\r
+/* TIM synchronization action */\r
+#define TIM_SynchroAction_Enable 0x0100\r
+#define TIM_SynchroAction_Update 0x0200\r
+#define TIM_SynchroAction_Reset 0x0000\r
+#define TIM_SynchroAction_OC 0x0300\r
+\r
+/* TIM synchronization mode */\r
+#define TIM_SynchroMode_Gated 0x0010\r
+#define TIM_SynchroMode_Trigger 0x0018\r
+#define TIM_SynchroMode_External 0x0008\r
+#define TIM_SynchroMode_Reset 0x0000\r
+\r
+/* OCRM bit states */\r
+#define TIM_OCRMState_Enable 0x0005\r
+#define TIM_OCRMState_Disable 0x0006\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+void TIM_DeInit(TIM_TypeDef *TIMx);\r
+void TIM_Init(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct);\r
+void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct);\r
+void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState Newstate);\r
+void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState Newstate);\r
+void TIM_PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_Channel, FunctionalState Newstate);\r
+void TIM_DMAConfig(u16 TIM_DMASources, u16 TIM_OCRMState, u16 TIM_DMABase);\r
+void TIM_DMACmd(u16 TIM_DMASources, FunctionalState Newstate);\r
+void TIM_ClockSourceConfig(TIM_TypeDef *TIMx, u16 TIM_ClockSource,\r
+ u16 TIM_ExtCLKEdge);\r
+void TIM_SetPrescaler(TIM_TypeDef* TIMx, u16 Prescaler);\r
+void TIM_SetPeriod(TIM_TypeDef* TIMx, u16 Period);\r
+void TIM_SetPulse(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 Pulse);\r
+u16 TIM_GetICAP1(TIM_TypeDef *TIMx);\r
+u16 TIM_GetICAP2(TIM_TypeDef *TIMx);\r
+u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx);\r
+u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx);\r
+void TIM_DebugCmd(TIM_TypeDef *TIMx, FunctionalState Newstate);\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode);\r
+void TIM_ForcedOCConfig(TIM_TypeDef* TIMx, u16 TIM_Channel,\r
+ u16 TIM_ForcedAction);\r
+void TIM_ResetCounter(TIM_TypeDef* TIMx);\r
+void TIM_SynchroConfig(Master_TypeDef Master, Slave_TypeDef Slave,\r
+ u16 TIM_SynchroAction, u16 TIM_SynchroMode);\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG);\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG);\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT);\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT);\r
+\r
+#endif /* __75x_TIM_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_type.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the common data types used for the\r
+* STR75x software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_TYPE_H\r
+#define __75x_TYPE_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Exported types ------------------------------------------------------------*/\r
+typedef signed long s32;\r
+typedef signed short s16;\r
+typedef signed char s8;\r
+\r
+typedef volatile signed long vs32;\r
+typedef volatile signed short vs16;\r
+typedef volatile signed char vs8;\r
+\r
+typedef unsigned long u32;\r
+typedef unsigned short u16;\r
+typedef unsigned char u8;\r
+\r
+typedef volatile unsigned long vu32;\r
+typedef volatile unsigned short vu16;\r
+typedef volatile unsigned char vu8;\r
+\r
+typedef volatile unsigned long const vuc32; /* Read Only */\r
+typedef volatile unsigned short const vuc16; /* Read Only */\r
+typedef volatile unsigned char const vuc8; /* Read Only */\r
+\r
+\r
+typedef enum { FALSE = 0, TRUE = !FALSE } bool;\r
+\r
+typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;\r
+\r
+typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+\r
+typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
+\r
+#define U8_MAX ((u8)255)\r
+#define S8_MAX ((s8)127)\r
+#define S8_MIN ((s8)-128)\r
+#define U16_MAX ((u16)65535u)\r
+#define S16_MAX ((s16)32767)\r
+#define S16_MIN ((s16)-32768)\r
+#define U32_MAX ((u32)4294967295uL)\r
+#define S32_MAX ((s32)2147483647)\r
+#define S32_MIN ((s32)-2147483648)\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+#endif /* __75x_TYPE_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_uart.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* UART software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_UART_H\r
+#define __75x_UART_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* UART FIFO Level enumeration */\r
+typedef enum\r
+{\r
+ UART_FIFOLevel_1_8 = 0x0000, /* FIFO size 16 bytes, FIFO level 2 bytes */\r
+ UART_FIFOLevel_1_4 = 0x0001, /* FIFO size 16 bytes, FIFO level 4 bytes */\r
+ UART_FIFOLevel_1_2 = 0x0002, /* FIFO size 16 bytes, FIFO level 8 bytes */\r
+ UART_FIFOLevel_3_4 = 0x0003, /* FIFO size 16 bytes, FIFO level 12 bytes */\r
+ UART_FIFOLevel_7_8 = 0x0004 /* FIFO size 16 bytes, FIFO level 14 bytes */\r
+}UART_FIFOLevel;\r
+\r
+/* UART Init Structure definition */\r
+typedef struct\r
+{\r
+ u16 UART_WordLength;\r
+ u16 UART_StopBits;\r
+ u16 UART_Parity;\r
+ u32 UART_BaudRate;\r
+ u16 UART_HardwareFlowControl;\r
+ u16 UART_Mode;\r
+ u16 UART_FIFO;\r
+ UART_FIFOLevel UART_TxFIFOLevel;\r
+ UART_FIFOLevel UART_RxFIFOLevel;\r
+}UART_InitTypeDef;\r
+\r
+\r
+/* UART RTS enumeration */\r
+typedef enum\r
+{\r
+ RTSRESET = 1,\r
+ RTSSET\r
+}UART_RTSTypeDef;\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* UART Data Length */\r
+#define UART_WordLength_5D 0x0000 /* 5 bits Data */\r
+#define UART_WordLength_6D 0x0020 /* 6 bits Data */\r
+#define UART_WordLength_7D 0x0040 /* 7 bits Data */\r
+#define UART_WordLength_8D 0x0060 /* 8 bits Data */\r
+ \r
+/* UART Stop Bits */\r
+#define UART_StopBits_1 0xFFF7 /* One stop bit is transmitted at \r
+ the end of frame */\r
+#define UART_StopBits_2 0x0008 /* Tow stop bits are transmitted \r
+ at the end of frame */\r
+\r
+/* UART Parity */\r
+#define UART_Parity_No 0x0000 /* Parity Disable */\r
+#define UART_Parity_Even 0x0006 /* Even Parity */\r
+#define UART_Parity_Odd 0x0002 /* Odd Parity */\r
+#define UART_Parity_OddStick 0x0082 /* 1 is transmitted as bit parity */\r
+#define UART_Parity_EvenStick 0x0086 /* 0 is transmitted as bit parity */\r
+\r
+/* UART Hardware Flow Control */\r
+#define UART_HardwareFlowControl_None 0x0000/* HFC Disable */\r
+#define UART_HardwareFlowControl_RTS 0x4000/* RTS Enable */\r
+#define UART_HardwareFlowControl_CTS 0x8000/* CTS Enable */\r
+#define UART_HardwareFlowControl_RTS_CTS 0xC000/* CTS and RTS Enable */\r
+\r
+/* UART Mode */\r
+#define UART_Mode_Rx 0x0200 /* UART Rx Enabled */\r
+#define UART_Mode_Tx 0x0100 /* UART Tx Enbled */\r
+#define UART_Mode_Tx_Rx 0x0300 /* UART Tx and Rx Enabled */\r
+\r
+/* UART FIFO */\r
+#define UART_FIFO_Disable 0xFFEF /* FIFOs Disable */\r
+#define UART_FIFO_Enable 0x0010 /* FIFOs Enable */\r
+\r
+/* UART Interrupt definition */\r
+#define UART_IT_OverrunError 0x0400 /* Overrun Error interrupt */\r
+#define UART_IT_BreakError 0x0200 /* Break Error interrupt */\r
+#define UART_IT_ParityError 0x0100 /* Parity Error interrupt */\r
+#define UART_IT_FrameError 0x0080 /* Frame Error interrupt */\r
+#define UART_IT_ReceiveTimeOut 0x0040 /* Receive Time Out interrupt */\r
+#define UART_IT_Transmit 0x0020 /* Transmit interrupt */\r
+#define UART_IT_Receive 0x0010 /* Receive interrupt */\r
+#define UART_IT_CTS 0x0002 /* CTS interrupt */\r
+\r
+/* UART0 DMA transfer */\r
+#define UART0_DMATransfer_Single 0xFFF7 /* Single DMA transfer */\r
+#define UART0_DMATransfer_Burst 0x0008 /* Burst DMA transfer */\r
+\r
+/* UART0 DMA On Error */\r
+#define UART0_DMAOnError_Enable 0xFFFB /* DMA receive request enabled\r
+ when the UART0 error interrupt\r
+ is asserted. */\r
+#define UART0_DMAOnError_Disable 0x0004 /* DMA receive request disabled\r
+ when the UART0 error interrupt\r
+ is asserted. */\r
+\r
+/* UART0 DMA Request */\r
+#define UART0_DMAReq_Tx 0x0002 /* Transmit DMA Enable */\r
+#define UART0_DMAReq_Rx 0x0001 /* Receive DMA Enable */\r
+\r
+/* UART FLAG */\r
+#define UART_FLAG_OverrunError 0x23 /* Overrun error flag */\r
+#define UART_FLAG_Break 0x22 /* break error flag */\r
+#define UART_FLAG_ParityError 0x21 /* parity error flag */\r
+#define UART_FLAG_FrameError 0x20 /* frame error flag */\r
+#define UART_FLAG_TxFIFOEmpty 0x47 /* Transmit FIFO Empty flag */\r
+#define UART_FLAG_RxFIFOFull 0x46 /* Receive FIFO Full flag */\r
+#define UART_FLAG_TxFIFOFull 0x45 /* Transmit FIFO Full flag */\r
+#define UART_FLAG_RxFIFOEmpty 0x44 /* Receive FIFO Empty flag */\r
+#define UART_FLAG_Busy 0x43 /* UART Busy flag */\r
+#define UART_FLAG_CTS 0x40 /* CTS flag */\r
+#define UART_RawIT_OverrunError 0x6A /* Overrun Error Masked IT flag */\r
+#define UART_RawIT_BreakError 0x69 /* Break Error Masked IT flag */\r
+#define UART_RawIT_ParityError 0x68 /* Parity Error Masked IT flag */\r
+#define UART_RawIT_FrameError 0x67 /* Frame Error Masked IT flag */\r
+#define UART_RawIT_ReceiveTimeOut 0x66 /* ReceiveTimeOut Masked IT flag */\r
+#define UART_RawIT_Transmit 0x65 /* Transmit Masked IT flag */\r
+#define UART_RawIT_Receive 0x64 /* Receive Masked IT flag */\r
+#define UART_RawIT_CTS 0x61 /* CTS Masked IT flag */\r
+\r
+/* UART LIN break length */\r
+#define UART_LINBreakLength_10 0x0000 /* 10 low bits */\r
+#define UART_LINBreakLength_11 0x0200 /* 11 low bits */\r
+#define UART_LINBreakLength_12 0x0400 /* 12 low bits */\r
+#define UART_LINBreakLength_13 0x0600 /* 13 low bits */\r
+#define UART_LINBreakLength_14 0x0800 /* 14 low bits */\r
+#define UART_LINBreakLength_15 0x0A00 /* 15 low bits */\r
+#define UART_LINBreakLength_16 0x0C00 /* 16 low bits */\r
+#define UART_LINBreakLength_17 0x0E00 /* 17 low bits */\r
+#define UART_LINBreakLength_18 0x1000 /* 18 low bits */\r
+#define UART_LINBreakLength_19 0x1200 /* 19 low bits */\r
+#define UART_LINBreakLength_20 0x1400 /* 20 low bits */\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void UART_DeInit(UART_TypeDef* UARTx);\r
+void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct);\r
+void UART_StructInit(UART_InitTypeDef* UART_InitStruct);\r
+void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState);\r
+void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState);\r
+void UART_DMAConfig(u16 UART0_DMATransfer, u16 UART0_DMAOnError);\r
+void UART_DMACmd(u16 UART0_DMAReq, FunctionalState NewState);\r
+void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState);\r
+void UART_LINConfig(UART_TypeDef* UARTx, u16 UART_LINBreakLength);\r
+void UART_LINCmd(UART_TypeDef* UARTx, FunctionalState NewState);\r
+void UART_SendData(UART_TypeDef* UARTx, u8 Data);\r
+u8 UART_ReceiveData(UART_TypeDef* UARTx);\r
+void UART_SendBreak(UART_TypeDef* UARTx);\r
+void UART_RTSConfig(UART_TypeDef* UARTx,UART_RTSTypeDef RTSState);\r
+FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG);\r
+void UART_ClearFlag(UART_TypeDef* UARTx, u16 UART_FLAG);\r
+ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT);\r
+void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT);\r
+\r
+#endif /* __75x_UART_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_wdg.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* WDG software library.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __75x_WDG_H\r
+#define __75x_WDG_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+ typedef struct\r
+{\r
+ u16 WDG_Mode; /* Watchdog or Timer mode */\r
+ u16 WDG_Preload; /* Preload register */\r
+ u8 WDG_Prescaler; /* Prescaler register */\r
+}WDG_InitTypeDef;\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/* WDG/Timer Select */\r
+#define WDG_Mode_WDG 0x0001\r
+#define WDG_Mode_Timer 0xFFFE\r
+\r
+/* WDG End of Count interrupt request */\r
+#define WDG_IT_EC 0x0001\r
+\r
+/* WDG end of count Flag */\r
+#define WDG_FLAG_EC 0x0001\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void WDG_DeInit(void);\r
+void WDG_Init(WDG_InitTypeDef* WDG_InitStruct);\r
+void WDG_StructInit(WDG_InitTypeDef* WDG_InitStruct);\r
+void WDG_Cmd(FunctionalState NewState);\r
+void WDG_ITConfig(FunctionalState NewState);\r
+u16 WDG_GetCounter(void);\r
+FlagStatus WDG_GetFlagStatus(void);\r
+void WDG_ClearFlag(void);\r
+ITStatus WDG_GetITStatus(void);\r
+void WDG_ClearITPendingBit(void);\r
+\r
+#endif /* __WDG_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : lcd.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* lcd software driver.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion ---------------------------------------*/\r
+#ifndef __LCD_H\r
+#define __LCD_H\r
+\r
+/* Includes --------------------------------------------------------------------*/\r
+#include "75x_lib.h"\r
+\r
+/* Exported types --------------------------------------------------------------*/\r
+\r
+ /* Data lines configuration mode */\r
+ typedef enum\r
+ {\r
+ Input,\r
+ Output\r
+ } DataConfigMode_TypeDef;\r
+\r
+ /* Text color mode */\r
+ typedef enum\r
+ {\r
+ BlackText=0,\r
+ WhiteText=1\r
+ } TextColorMode_TypeDef;\r
+\r
+ /* Dot On/Off mode */\r
+ typedef enum\r
+ {\r
+ Dot_On,\r
+ Dot_Off\r
+ } DotMode_TypeDef;\r
+\r
+/* Exported constants ----------------------------------------------------------*/\r
+\r
+/* LCD Control pins */\r
+#define CtrlPin_E2 0x00000001\r
+#define CtrlPin_E1 0x00000002\r
+#define CtrlPin_RW 0x00000004\r
+#define CtrlPin_DI 0x00000008\r
+\r
+/* LCD Commands */\r
+#define DISPLAY_ON 0xAF\r
+#define DISPLAY_OFF 0xAE\r
+#define START_LINE 0xC0\r
+#define START_COLUMN 0x00\r
+#define CLOCKWISE_OUTPUT 0xA0\r
+#define DYNAMIC_DRIVE 0xA4\r
+#define DUTY_CYCLE 0xA9\r
+#define READ_MODIFY_WRITE_OFF 0xEE\r
+#define SOFTWARE_RESET 0xE2\r
+\r
+/* LCD Lines when LCD is managed as 2*17 characters */\r
+#define Line1 0x0\r
+#define Line2 0x2\r
+\r
+/* Exported macro --------------------------------------------------------------*/\r
+/* Exported functions ----------------------------------------------------------*/\r
+/*----- Low layer function -----*/\r
+void LCD_CtrlLinesConfig(void);\r
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u32 CtrlPins, BitAction BitVal);\r
+void LCD_DataLinesConfig(DataConfigMode_TypeDef Mode);\r
+void LCD_DataLinesWrite(GPIO_TypeDef* GPIOx, u32 PortVal);\r
+\r
+/*----- Medium layer function -----*/\r
+void LCD_CheckMasterStatus(void);\r
+void LCD_CheckSlaveStatus(void);\r
+void LCD_SendMasterCmd(u8 Cmd);\r
+void LCD_SendSlaveCmd(u8 Cmd);\r
+void LCD_SendMasterData(u8 Data);\r
+u32 LCD_ReadMasterData(void);\r
+void LCD_SendSlaveData(u8 Data);\r
+u32 LCD_ReadSlaveData(void);\r
+void LCD_SetMasterPage(u8 Page); \r
+void LCD_SetSlavePage(u8 Page);\r
+void LCD_SetMasterColumn(u8 Address);\r
+void LCD_SetSlaveColumn(u8 Address);\r
+void LCD_DrawChar(u8 Line, u8 Column, u8 Width, u8 *Bmp);\r
+u8 LCD_HexToAsciiLow(u8 byte);\r
+u8 LCD_HexToAsciiHigh(u8 byte);\r
+void LCD_SetTextColor(TextColorMode_TypeDef TextColor);\r
+\r
+/*----- High layer function -----*/\r
+void LCD_Init(void);\r
+/* LCD managed as 2 Lines, 17 characters each one (2Lines*17Char) */\r
+void LCD_ClearLine(u8 Line);\r
+void LCD_DisplayChar(u8 Line, u8 Column, u8 Ascii, TextColorMode_TypeDef CharMode);\r
+void LCD_DisplayString(u8 Line, u8 *ptr, TextColorMode_TypeDef CharMode);\r
+void LCD_Printf(u8* ptr, ...);\r
+/* LCD managed as 122*32 dots */\r
+void LCD_ClearMaster(void);\r
+void LCD_ClearSlave(void);\r
+void LCD_Clear(void);\r
+void LCD_DrawMasterGraphic(u8 *Bmp);\r
+void LCD_DrawSlaveGraphic(u8 *Bmp);\r
+void LCD_DrawGraphic(u8 *Bmp);\r
+void LCD_ScrollGraphic(u8 *Bmp, u32 nCount);\r
+void LCD_DrawPixel(u8 XPos, u8 YPos, DotMode_TypeDef Mode);\r
+void LCD_DrawLine(u8 XPos1, u8 YPos1, u8 XPos2, u8 YPos2);\r
+void LCD_DrawBox(u8 XPos, u8 YPos, u8 Dx, u8 Dy);\r
+\r
+#endif /*__LCD_H */\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE******/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_adc.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file provides all the ADC software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, \r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING \r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_adc.h"\r
+#include "75x_mrcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+/* Mask for Power Down Mode */\r
+#define ADC_PowerDown_Enable 0x8000\r
+#define ADC_PowerDown_Disable 0x7FFF\r
+\r
+/* Mask for Watchdog Thresholds Enable */\r
+#define ADC_AnalogWatchdog_Enable 0x8000\r
+#define ADC_AnalogWatchdog_Disable 0x7FFF\r
+\r
+/* Mask for Injected conversion start */\r
+#define ADC_Injec_ConversionStart 0x8000\r
+\r
+/* DMA enable */\r
+#define ADC_DMA_ExtEnable_Mask 0x4000\r
+\r
+/* Injected start trigger enable */\r
+#define ADC_Injec_ExtTrigger_Enable 0x4000\r
+\r
+/* ADC Masks */\r
+#define ADC_DMAFirstEnabledChannel_Mask 0x000F \r
+#define ADC_DataRegisterOffset 0x0050\r
+#define ADC_FirstChannel_Mask 0xFFF0\r
+#define ADC_ChannelNumber_Mask 0xFC3F\r
+#define ADC_Threshold_Mask 0xFC00\r
+#define ADC_AnalogWatchdogChannel_Mask 0xC3FF\r
+#define ADC_Prescalers_Mask 0x7F18\r
+#define ADC_SPEN_Mask 0x8000\r
+#define ADC_FallingEdge_Mask 0xEFFF\r
+#define ADC_LowLevel_Mask 0x4000\r
+#define ADC_HighLevel_Mask 0xDFFF\r
+#define ADC_Calibration_Mask 0x0002\r
+ \r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_DeInit \r
+* Description : Deinitializes the ADC peripheral registers to their default\r
+* reset values.\r
+* Input : None. \r
+* Output : None \r
+* Return : None. \r
+*******************************************************************************/\r
+void ADC_DeInit(void)\r
+{\r
+ /* Reset the ADC registers values*/\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_ADC,ENABLE);\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_ADC,DISABLE); \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_Init \r
+* Description : Initializes the ADC peripheral according to the specified\r
+* parameters in the ADC_InitStruct.\r
+* Input : - ADC_InitStruct: pointer to an ADC_InitTypeDef structure that\r
+ contains the configuration information for the ADC peripheral.\r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void ADC_Init(ADC_InitTypeDef* ADC_InitStruct)\r
+{\r
+ /* Configure the conversion mode */\r
+ if(ADC_InitStruct->ADC_ConversionMode == ADC_ConversionMode_Scan)\r
+ {\r
+ /* Set the scan conversion mode */\r
+ ADC->CLR2 |= ADC_ConversionMode_Scan;\r
+ }\r
+ else\r
+ {\r
+ /* Set the one-shot conversion mode */\r
+ ADC->CLR2 &= ADC_ConversionMode_OneShot;\r
+ }\r
+ \r
+ /* Configure the external start conversion trigger */\r
+ switch(ADC_InitStruct->ADC_ExtTrigger)\r
+ {\r
+ case ADC_ExtTrigger_HighLevel:\r
+ /* Start conversion on High level of the external trigger (TIM0) */\r
+ ADC->CLR0 &= ADC_HighLevel_Mask;\r
+ ADC->CLR0 |= ADC_ExtTrigger_HighLevel;\r
+ break;\r
+ \r
+ case ADC_ExtTrigger_LowLevel:\r
+ /* Start conversion on low level of the external trigger (TIM0) */\r
+ ADC->CLR0 &= ADC_ExtTrigger_LowLevel; \r
+ ADC->CLR0 |= ADC_LowLevel_Mask;\r
+ break;\r
+ \r
+ case ADC_ExtTrigger_RisingEdge:\r
+ /* Start conversion on rising edge of the external trigger (TIM0) */\r
+ ADC->CLR0 |= ADC_ExtTrigger_RisingEdge;\r
+ break;\r
+ \r
+ case ADC_ExtTrigger_FallingEdge:\r
+ /* Start conversion on falling edge of the external trigger (TIM0) */\r
+ ADC->CLR0 &= ADC_FallingEdge_Mask;\r
+ ADC->CLR0 |= ADC_ExtTrigger_FallingEdge;\r
+ break;\r
+ \r
+ case ADC_ExtTrigger_Disable:\r
+ /* Disable the external trigger and start the conversion by software */\r
+ ADC->CLR0 &= ADC_ExtTrigger_Disable;\r
+ break;\r
+\r
+ default:\r
+ break; \r
+ }\r
+\r
+ /* Configure the auto clock off feature */\r
+ if (ADC_InitStruct->ADC_AutoClockOff == ADC_AutoClockOff_Enable)\r
+ {\r
+ /* Enable the auto clock off feature */\r
+ ADC->CLR4 |= ADC_AutoClockOff_Enable;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the auto clock off feature */\r
+ ADC->CLR4 &= ADC_AutoClockOff_Disable; \r
+ }\r
+ \r
+ /* Clear conversion prescaler CNVP[2:0], sampling prescaler SMPP[2:0] bits \r
+ and Sample prescaler enable SPEN bit */\r
+ ADC->CLR1 &= ADC_Prescalers_Mask;\r
+ /* Set conversion prescaler value (sampling and conversion prescalers are equal\r
+ while SPEN bit is reset */ \r
+ ADC->CLR1 |= (ADC_InitStruct->ADC_ConversionPrescaler<<5);\r
+ \r
+ /* In case ADC_SamplingPrescaler member is different from the conversion one */\r
+ if(ADC_InitStruct->ADC_SamplingPrescaler != ADC_InitStruct->ADC_ConversionPrescaler)\r
+ {\r
+ /* Set the sampling prescaler value */\r
+ ADC->CLR1 |= ADC_InitStruct->ADC_SamplingPrescaler;\r
+ /* Set SPEN bit (sampling and conversion prescalers are different */\r
+ ADC->CLR1 = (ADC->CLR1 | ADC_SPEN_Mask); \r
+ }\r
+ \r
+ /* Clear first channel to be converted FCH[3:0] bits */\r
+ ADC->CLR2 &= ADC_FirstChannel_Mask;\r
+ /* Set the first channel to be converted */\r
+ ADC->CLR2 |= ADC_InitStruct->ADC_FirstChannel;\r
+ /* Clear number of channels to be converted NCH[3:0] bits */\r
+ ADC->CLR2 &= ADC_ChannelNumber_Mask; \r
+ /* Set the number of channels to be converted */\r
+ ADC->CLR2 |= ((ADC_InitStruct->ADC_ChannelNumber)-1<<6);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_StructInit \r
+* Description : Fills each ADC_InitStruct member with its default value.\r
+* Input : - ADC_InitStruct: pointer to an ADC_InitTypeDef structure\r
+ which will be initialized. \r
+* Output : None \r
+* Return : None.\r
+*******************************************************************************/\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)\r
+{\r
+ /* Initialize the ADC_ConversionMode member */\r
+ ADC_InitStruct->ADC_ConversionMode = ADC_ConversionMode_OneShot;\r
+ \r
+ /* Initialize the ADC_ExtTrigger member */\r
+ ADC_InitStruct->ADC_ExtTrigger = ADC_ExtTrigger_Disable;\r
+ \r
+ /* Initialize the ADC_AutoClockOff member */\r
+ ADC_InitStruct->ADC_AutoClockOff = ADC_AutoClockOff_Disable;\r
+ \r
+ /* Initialize the ADC_SamplingPrescaler member */\r
+ ADC_InitStruct->ADC_SamplingPrescaler = 0;\r
+ \r
+ /* Initialize the ADC_ConversionPrescaler member */\r
+ ADC_InitStruct->ADC_ConversionPrescaler = 0;\r
+ \r
+ /* Initialize the ADC_FirstChannel member */\r
+ ADC_InitStruct->ADC_FirstChannel = ADC_CHANNEL0;\r
+ \r
+ /* Initialize the ADC_ChannelNumber member */\r
+ ADC_InitStruct->ADC_ChannelNumber = 1;\r
+ }\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_StartCalibration \r
+* Description : Starts the ADC Calibration. Calibration average enabled/disabled.\r
+* Input : - ADC_CalibAverage: Enables or disables ADC calibration average.\r
+* This parameter can be one of the following values:\r
+* - ADC_CalibAverage_Enable: enable calibration average \r
+* - ADC_CalibAverage_Disable: disable calibration average \r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void ADC_StartCalibration(u16 ADC_CalibAverage)\r
+{\r
+ if (ADC_CalibAverage == ADC_CalibAverage_Enable)\r
+ {\r
+ /* Enable ADC Calibration Average */\r
+ ADC->CLR4 &= ADC_CalibAverage_Enable;\r
+ }\r
+ else\r
+ {\r
+ /* Disable ADC Calibration Average */\r
+ ADC->CLR4 |= ADC_CalibAverage_Disable;\r
+ }\r
+\r
+ /* Start Calibration */\r
+ ADC->CLR0 |= ADC_Calibration_ON;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetCalibrationStatus\r
+* Description : Get the ADC Calibration Status.\r
+* Input : None\r
+* Output : None \r
+* Return : The NewState of the ADC calibration (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ADC_GetCalibrationStatus(void)\r
+{\r
+ /* Check the status of the ADC calibration */\r
+ if((ADC->CLR0 & ADC_Calibration_Mask) != RESET)\r
+ {\r
+ /* Return SET if ADC Calibration is on going */\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ /* Return RESET if ADC Calibration is finished */\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_ConversionCmd\r
+* Description : Starts or stops the ADC conversion.\r
+* Input : - ADC_Conversion: specifies the ADC command to apply.\r
+* This parameter can be one of the following values:\r
+* - ADC_Conversion_Start: start conversion \r
+* - ADC_Conversion_Stop: stop conversion \r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_ConversionCmd (u16 ADC_Conversion)\r
+{\r
+ if (ADC_Conversion == ADC_Conversion_Start)\r
+ {\r
+ /* Start the ADC Conversion */\r
+ ADC->CLR0 |= ADC_Conversion_Start;\r
+ }\r
+ else\r
+ {\r
+ /* Stop the ADC Conversion */\r
+ ADC->CLR0 &= ADC_Conversion_Stop;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetSTARTBitStatus\r
+* Description : Gets the ADC START/STOP bit Status.\r
+* Input : None\r
+* Output : None \r
+* Return : The NewState of the ADC START/STOP bit (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ADC_GetSTARTBitStatus(void)\r
+{\r
+ /* Check the status of the ADC START/STOP bit */\r
+ if((ADC->CLR0 & ADC_Conversion_Start) != RESET)\r
+ {\r
+ /* Return SET if ADC Conversion is started */\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ /* Return RESET if ADC Conversion is stopped */\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_Cmd\r
+* Description : Enables the ADC peripheral or puts it in power down mode.\r
+* - NewState: new state of the ADC peripheral. \r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None \r
+* Return : None.\r
+*******************************************************************************/\r
+void ADC_Cmd(FunctionalState NewState)\r
+{\r
+ if (NewState == DISABLE)\r
+ {\r
+ /* Enable ADC Power Down Mode */\r
+ ADC->CLR4 |= ADC_PowerDown_Enable;\r
+ }\r
+ else\r
+ {\r
+ /* Disable ADC Power Down Mode */\r
+ ADC->CLR4 &= ADC_PowerDown_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_AutoClockOffConfig \r
+* Description : Enables or disables the Auto clock off feature.\r
+* - NewState: new state of the Auto clock off feature. This \r
+* parameter can be: ENABLE or DISABLE. \r
+* Output : None \r
+* Return : None. \r
+*******************************************************************************/\r
+void ADC_AutoClockOffConfig(FunctionalState NewState)\r
+{\r
+ if (NewState == ENABLE)\r
+ {\r
+ /* Enable ADC Auto Clock Off */\r
+ ADC->CLR4 |= ADC_AutoClockOff_Enable;\r
+ }\r
+ else\r
+ {\r
+ /* Disable ADC Auto Clock Off */\r
+ ADC->CLR4 &= ADC_AutoClockOff_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_AnalogWatchdogConfig \r
+* Description : Configures the analog input channel to be used for the selected\r
+* Analog Watchdog and defines its corresponding High and Low \r
+* threshold values. \r
+* Input : - ADC_AnalogWatchdog: specifies the analog watchdog which will\r
+* be affected to the desired converted channel. This parameter\r
+* can be one of the following values: \r
+* - ADC_AnalogWatchdog0: select analog watchdog 0\r
+* - ADC_AnalogWatchdog1: select analog watchdog 1\r
+* - ADC_AnalogWatchdog2: select analog watchdog 2\r
+* - ADC_AnalogWatchdog3: select analog watchdog 3\r
+* - ADC_CHANNEL: specifies the channel linked to the selected \r
+* analog watchdog. This parameter can be ADC_CHANNELx where x \r
+* can be (0..15) \r
+* - LowThreshold: Low Threshold for the selected Analog watchdog\r
+* - HighThreshold: High Threshold for the selected Analog watchdog\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_AnalogWatchdogConfig(u16 ADC_AnalogWatchdog, u8 ADC_CHANNEL, \r
+ u16 LowThreshold, u16 HighThreshold)\r
+{\r
+ switch (ADC_AnalogWatchdog)\r
+ {\r
+ /* Set the selected channel and their corresponding High and Low thresholds */\r
+ case ADC_AnalogWatchdog0 :\r
+ ADC->TRA0 = (ADC->TRA0 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10);\r
+ ADC->TRA0 = (ADC->TRA0 & ADC_Threshold_Mask) | HighThreshold;\r
+ ADC->TRB0 = (ADC->TRB0 & ADC_Threshold_Mask) | LowThreshold;\r
+ break;\r
+\r
+ case ADC_AnalogWatchdog1 :\r
+ ADC->TRA1 = (ADC->TRA1 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10);\r
+ ADC->TRA1 = (ADC->TRA1 & ADC_Threshold_Mask) | HighThreshold;\r
+ ADC->TRB1 = (ADC->TRB1 & ADC_Threshold_Mask) | LowThreshold;\r
+ break;\r
+\r
+ case ADC_AnalogWatchdog2 :\r
+ ADC->TRA2 = (ADC->TRA2 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10);\r
+ ADC->TRA2 = (ADC->TRA2 & ADC_Threshold_Mask) | HighThreshold;\r
+ ADC->TRB2 = (ADC->TRB2 & ADC_Threshold_Mask) | LowThreshold;\r
+ break;\r
+\r
+ case ADC_AnalogWatchdog3 :\r
+ ADC->TRA3 = (ADC->TRA3 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10);\r
+ ADC->TRA3 = (ADC->TRA3 & ADC_Threshold_Mask) | HighThreshold;\r
+ ADC->TRB3 = (ADC->TRB3 & ADC_Threshold_Mask) | LowThreshold;\r
+ break;\r
+\r
+ default:\r
+ break; \r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_AnalogWatchdogCmd \r
+* Description : Enables or disables the selected analog Watchdog.\r
+* Input : - ADC_AnalogWatchdog: specifies the analog watchdog to be \r
+* enabled or disabled. This parameter can be one of the \r
+* following values: \r
+* - ADC_AnalogWatchdog0: select analog watchdog 0\r
+* - ADC_AnalogWatchdog1: select analog watchdog 1\r
+* - ADC_AnalogWatchdog2: select analog watchdog 2\r
+* - ADC_AnalogWatchdog3: select analog watchdog 3\r
+* - NewState: new state of the specified analog watchdog.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None. \r
+*******************************************************************************/\r
+void ADC_AnalogWatchdogCmd(u16 ADC_AnalogWatchdog, FunctionalState NewState)\r
+{\r
+ if (NewState == ENABLE)\r
+ {\r
+ /* Enable the selected ADC AnalogWatchdogx */\r
+ switch (ADC_AnalogWatchdog)\r
+ {\r
+ case ADC_AnalogWatchdog0 : \r
+ ADC->TRB0 |= ADC_AnalogWatchdog_Enable;\r
+ break;\r
+\r
+ case ADC_AnalogWatchdog1 : \r
+ ADC->TRB1 |= ADC_AnalogWatchdog_Enable; \r
+ break;\r
+\r
+ case ADC_AnalogWatchdog2 : \r
+ ADC->TRB2 |= ADC_AnalogWatchdog_Enable; \r
+ break;\r
+\r
+ case ADC_AnalogWatchdog3 : \r
+ ADC->TRB3 |= ADC_AnalogWatchdog_Enable; \r
+ break;\r
+\r
+ default:\r
+ break; \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC AnalogWatchdogx */\r
+ switch (ADC_AnalogWatchdog)\r
+ {\r
+ case ADC_AnalogWatchdog0 : \r
+ ADC->TRB0 &= ADC_AnalogWatchdog_Disable; \r
+ break;\r
+\r
+ case ADC_AnalogWatchdog1 : \r
+ ADC->TRB1 &= ADC_AnalogWatchdog_Disable; \r
+ break;\r
+\r
+ case ADC_AnalogWatchdog2 : \r
+ ADC->TRB2 &= ADC_AnalogWatchdog_Disable; \r
+ break;\r
+\r
+ case ADC_AnalogWatchdog3 : \r
+ ADC->TRB3 &= ADC_AnalogWatchdog_Disable; \r
+ break;\r
+\r
+ default:\r
+ break; \r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetAnalogWatchdogResult\r
+* Description : Returns the comparison result of the selected analog watchdog.\r
+* Input : - ADC_AnalogWatchdog: specifies the analog watchdog channel \r
+* which its comparison result will be returned. This parameter\r
+* can be one of the following values: \r
+* - ADC_AnalogWatchdog0: select analog watchdog 0\r
+* - ADC_AnalogWatchdog1: select analog watchdog 1\r
+* - ADC_AnalogWatchdog2: select analog watchdog 2\r
+* - ADC_AnalogWatchdog3: select analog watchdog 3\r
+* Output : None\r
+* Return : The analog watchdog comparaison result value\r
+*******************************************************************************/\r
+u16 ADC_GetAnalogWatchdogResult(u16 ADC_AnalogWatchdog)\r
+{\r
+ /* Return the selected ADC AnalogWatchdogx comparaison result */\r
+ switch(ADC_AnalogWatchdog)\r
+ {\r
+ case ADC_AnalogWatchdog0 :\r
+ return ((ADC->PBR & ADC_AnalogWatchdog)>>4);\r
+\r
+ case ADC_AnalogWatchdog1 :\r
+ return ((ADC->PBR & ADC_AnalogWatchdog)>>6);\r
+\r
+ case ADC_AnalogWatchdog2 :\r
+ return ((ADC->PBR & ADC_AnalogWatchdog)>>8);\r
+\r
+ case ADC_AnalogWatchdog3 :\r
+ return ((ADC->PBR & ADC_AnalogWatchdog)>>10);\r
+\r
+ default : return (0xFF); /* if a wrong value of ADC_AnalogWatchdog is selected */\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_InjectedConversionConfig\r
+* Description : Configures the start trigger level for the injected channels \r
+* and the injected analog input channels to be converted. \r
+* Input : - ADC_Injec_ExtTrigger: specifies the start trigger level.\r
+* This parameter can be one of the following values:\r
+* - ADC_Injec_ExtTrigger_Disable : external trigger disabled\r
+* - ADC_Injec_ExtTrigger_RisingEdge: external trigger\r
+* configured as rising edge of PWM Timer TRGO signal\r
+* - ADC_Injec_ExtTrigger_FallingEdge: external trigger \r
+* configured as falling edge of PWM Timer TRGO signal \r
+* - FirstChannel: specifies the first injected channel to be\r
+* converted. \r
+* This parameter can be ADC_CHANNELx where x can be (0..15). \r
+* - ChannelNumber: specifies the Number of the injected channels \r
+* to be converted. This parameter can be a value from 1 to 16. \r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_InjectedConversionConfig(u16 ADC_Injec_ExtTrigger, u8 FirstChannel, u8 ChannelNumber)\r
+{\r
+ /* Configure the external start injected conversion trigger */\r
+ switch (ADC_Injec_ExtTrigger)\r
+ {\r
+ case ADC_Injec_ExtTrigger_Disable :\r
+ /* Disable the external trigger and start the injected conversion by software */\r
+ ADC->CLR3 &= ADC_Injec_ExtTrigger_Disable ;\r
+ break;\r
+ case ADC_Injec_ExtTrigger_RisingEdge :\r
+ /* Start injected conversion on rising edge of the external trigger (PWM) */\r
+ ADC->CLR3 |= ADC_Injec_ExtTrigger_RisingEdge;\r
+ break;\r
+ case ADC_Injec_ExtTrigger_FallingEdge :\r
+ /* Start injected conversion on falling edge of the external trigger (PWM) */\r
+ ADC->CLR3 |= ADC_Injec_ExtTrigger_Enable; \r
+ ADC->CLR3 &= ADC_Injec_ExtTrigger_FallingEdge;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ \r
+ /* Clear first injected channel to be converted JFCH[3:0] bits */\r
+ ADC->CLR3 &= ADC_FirstChannel_Mask;\r
+ /* Set the first injected channel to be converted */\r
+ ADC->CLR3 |= FirstChannel;\r
+ /* Clear number of injected channels to be converted JNCH[3:0] bits */\r
+ ADC->CLR3 &= ADC_ChannelNumber_Mask; \r
+ /* Set the number of injected channels to be converted */\r
+ ADC->CLR3 |= ((ChannelNumber-1)<<6);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_StartInjectedConversion\r
+* Description : Starts by software the conversion of the injected input channels.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_StartInjectedConversion(void)\r
+{\r
+ /* Start the injected ADC Conversion */\r
+ ADC->CLR3 |= ADC_Injec_ConversionStart;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetConversionValue\r
+* Description : Reads the conversion result from the appropriate data register.\r
+* Input : - ADC_CHANNEL :specifies the ADC channel which its conversion \r
+* value have to be returned. This parameter can be ADC_CHANNELx\r
+* where x can be (0..15) to select channelx \r
+* Output : None\r
+* Return : The returned value holds the conversion result of the selected \r
+* channel.\r
+*******************************************************************************/\r
+u16 ADC_GetConversionValue(u8 ADC_CHANNEL)\r
+{\r
+ /* Return the conversion result of the selected channel */\r
+ return *((u16 *)(ADC_BASE + ((ADC_CHANNEL<<2) + ADC_DataRegisterOffset)));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_ITConfig\r
+* Description : Enables or disables the specified ADC interrupts.\r
+* Input : - ADC_IT: specifies the ADC interrupts to be enabled or disabled.\r
+* This parameter can be any combination of the following values:\r
+* - ADC_IT_ECH: End of chain conversion interrupt\r
+* - ADC_IT_EOC: End of channel conversion interrupt\r
+* - ADC_IT_JECH: Injected end of chain conversion interrupt\r
+* - ADC_IT_JEOC: Injected end of channel conversion interrupt\r
+* - ADC_IT_AnalogWatchdog0_LowThreshold:\r
+* Analog Watchdog 0 LowThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog0_HighThreshold:\r
+* Analog Watchdog 0 HighThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog1_LowThreshold:\r
+* Analog Watchdog 1 LowThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog1_HighThreshold:\r
+* Analog Watchdog 1 HighThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog2_LowThreshold:\r
+* Analog Watchdog 2 LowThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog2_HighThreshold:\r
+* Analog Watchdog 2 HighThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog3_LowThreshold:\r
+* Analog Watchdog 3 LowThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog3_HighThreshold:\r
+* Analog Watchdog 5 HighThreshold interrupt\r
+* - ADC_IT_ALL: All interrupts\r
+* - NewState: new state of the specified ADC interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_ITConfig(u16 ADC_IT, FunctionalState NewState)\r
+{\r
+ if (NewState == ENABLE)\r
+ {\r
+ /* Enable the selected ADC interrupts */\r
+ ADC->IMR |= ADC_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC interrupts */\r
+ ADC->IMR &= ~ADC_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_DMAConfig\r
+* Description : Configures the ADC\92s DMA interface.\r
+* Input : - ADC_DMA_CHANNEL: specifies the channels to be enabled or \r
+* disabled for DMA transfer. This parameter can be any \r
+* combination of ADC_DMA_CHANNELx where x can be (0..15). \r
+* - NewState: new state of the specified ADC DMA channels.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_DMAConfig(u16 ADC_DMA_CHANNEL, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Enable DMA for the selected channels */\r
+ ADC->DMAR |= ADC_DMA_CHANNEL ;\r
+ }\r
+ else\r
+ {\r
+ /* Disable DMA for the selected channels */\r
+ ADC->DMAR &= ~ADC_DMA_CHANNEL;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_DMACmd\r
+* Description : Enable or disable the DMA transfer for the ADC.\r
+* Input : - ADC_DMA: specifies the DMA command. This parameter can be \r
+* one of the following values:\r
+* - ADC_DMA_Disable: disable the DMA capability\r
+* - ADC_DMA_Enable: enabled by setting the global \r
+* enable bit\r
+* - ADC_DMA_ExtTrigger_HighLevel: enabled by detection of\r
+* high level of TIM2 OC2 signal\r
+* - ADC_DMA_ExtTrigger_LowLevel: enabled by detection of\r
+* low level of TIM2 OC2 signal\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_DMACmd(u16 ADC_DMA)\r
+{\r
+ /* Configure the DMA external trigger enable */\r
+ switch (ADC_DMA)\r
+ {\r
+ case ADC_DMA_Disable :\r
+ /* Disable DMA transfer */\r
+ ADC->DMAE &= ADC_DMA_Disable;\r
+ break;\r
+ \r
+ case ADC_DMA_Enable :\r
+ /* Enable DMA transfer */\r
+ ADC->DMAE |= ADC_DMA_Enable;\r
+ break;\r
+ \r
+ case ADC_DMA_ExtTrigger_HighLevel :\r
+ /* Enable DMA transfer on high level of the external trigger (TIM2) */\r
+ ADC->DMAE &= ADC_DMA_Disable;\r
+ ADC->DMAE |= ADC_DMA_ExtTrigger_HighLevel;\r
+ break;\r
+ \r
+ case ADC_DMA_ExtTrigger_LowLevel :\r
+ /* Enable DMA transfer on low level of the external trigger (TIM2) */\r
+ ADC->DMAE |= ADC_DMA_ExtEnable_Mask; \r
+ ADC->DMAE &= ADC_DMA_ExtTrigger_LowLevel;\r
+ break;\r
+\r
+ default:\r
+ break; \r
+ } \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetDMAFirstEnabledChannel\r
+* Description : Gets the first DMA-enabled channel configured at the time that\r
+* DMA was last globally enabled.\r
+* Input : None\r
+* Output : None\r
+* Return : The first DMA enabled channel\r
+*******************************************************************************/\r
+u16 ADC_GetDMAFirstEnabledChannel(void)\r
+{\r
+ /* Return the DMA first enabled channel */\r
+ return (ADC->DMAE & ADC_DMAFirstEnabledChannel_Mask);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetFlagStatus\r
+* Description : Checks whether the specified ADC flag is set or not.\r
+* Input : - ADC_FLAG: specifies the ADC flag to check. This parameter \r
+* can be one of the following values:\r
+* - ADC_FLAG_ECH: End of chain conversion Flag\r
+* - ADC_FLAG_EOC: End of channel conversion Flag\r
+* - ADC_FLAG_JECH: End of injected chain conversion Flag\r
+* - ADC_FLAG_JEOC: End of injected channel conversion Flag\r
+* - ADC_FLAG_AnalogWatchdog0_LowThreshold: \r
+* Analog Watchdog 0 LowThreshold Flag \r
+* - ADC_FLAG_AnalogWatchdog0_HighThreshold: \r
+* Analog Watchdog 0 HighThreshold Flag \r
+* - ADC_FLAG_AnalogWatchdog1_LowThreshold: \r
+* Analog Watchdog 1 LowThreshold Flag \r
+* - ADC_FLAG_AnalogWatchdog1_HighThreshold: \r
+* Analog Watchdog 1 HighThreshold Flag \r
+* - ADC_FLAG_AnalogWatchdog2_LowThreshold: \r
+* Analog Watchdog 2 LowThreshold Flag \r
+* - ADC_FLAG_AnalogWatchdog2_HighThreshold: \r
+* Analog Watchdog 2 HighThreshold Flag \r
+* - ADC_FLAG_AnalogWatchdog3_LowThreshold: \r
+* Analog Watchdog 3 LowThreshold Flag \r
+* - ADC_FLAG_AnalogWatchdog3_HighThreshold: \r
+* Analog Watchdog 3 HighThreshold Flag \r
+* Output : None \r
+* Return : The new state of the ADC_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ADC_GetFlagStatus(u16 ADC_FLAG)\r
+{\r
+ /* Check the status of the specified ADC flag */\r
+ if((ADC->PBR & ADC_FLAG) != RESET)\r
+ {\r
+ /* Return SET if ADC_FLAG is set */\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ /* Return RESET if ADC_FLAG is reset */\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_ClearFlag\r
+* Description : Clears the ADC\92s pending flags. \r
+* Input : - ADC_FLAG: specifies the flag to clear. This parameter can \r
+* be any combination of the following values:\r
+* - ADC_FLAG_ECH: End of chain conversion flag\r
+* - ADC_FLAG_EOC: End of channel conversion flag\r
+* - ADC_FLAG_JECH: Injected end of chain conversion flag\r
+* - ADC_FLAG_JEOC: Injected end of channel conversion flag\r
+* - ADC_FLAG_AnalogWatchdog0_LowThreshold: \r
+* Analog Watchdog 0 LowThreshold flag \r
+* - ADC_FLAG_AnalogWatchdog0_HighThreshold: \r
+* Analog Watchdog 0 HighThreshold flag \r
+* - ADC_FLAG_AnalogWatchdog1_LowThreshold: \r
+* Analog Watchdog 1 LowThreshold flag \r
+* - ADC_FLAG_AnalogWatchdog1_HighThreshold: \r
+* Analog Watchdog 1 HighThreshold flag \r
+* - ADC_FLAG_AnalogWatchdog2_LowThreshold: \r
+* Analog Watchdog 2 LowThreshold flag \r
+* - ADC_FLAG_AnalogWatchdog2_HighThreshold: \r
+* Analog Watchdog 2 HighThreshold flag \r
+* - ADC_FLAG_AnalogWatchdog3_LowThreshold: \r
+* Analog Watchdog 3 LowThreshold flag \r
+* - ADC_FLAG_AnalogWatchdog3_HighThreshold: \r
+* Analog Watchdog 3 HighThreshold flag \r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_ClearFlag(u16 ADC_FLAG)\r
+{\r
+ /* Clear the selected ADC flag */ \r
+ ADC->PBR = ADC_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetITStatus\r
+* Description : Checks whether the specified ADC interrupt has occured or not.\r
+* Input : - ADC_IT: specifies the ADC interrupt source to check. This \r
+* parameter can be one of the following values:\r
+* - ADC_IT_ECH :End of chain conversion interrupt \r
+* - ADC_IT_EOC :End of channel conversion interrupt\r
+* - ADC_IT_JECH :End of injected chain conversion interrupt\r
+* - ADC_IT_JEOC :End of injected channel conversion interrupt\r
+* - ADC_IT_AnalogWatchdog0_LowThreshold: \r
+* Analog Watchdog 0 LowThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog0_HighThreshold: \r
+* Analog Watchdog 0 HighThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog1_LowThreshold: \r
+* Analog Watchdog 1 LowThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog1_HighThreshold: \r
+* Analog Watchdog 1 HighThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog2_LowThreshold: \r
+* Analog Watchdog 2 LowThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog2_HighThreshold: \r
+* Analog Watchdog 2 HighThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog3_LowThreshold: \r
+* Analog Watchdog 3 LowThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog3_HighThreshold: \r
+* Analog Watchdog 3 HighThreshold interrupt\r
+* Output : None \r
+* Return : The new state of the ADC_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus ADC_GetITStatus(u16 ADC_IT)\r
+{\r
+ /* Check the status of the specified ADC interrupt */\r
+ if((ADC->PBR & ADC_IT) != RESET)\r
+ {\r
+ /* Return SET if the ADC interrupt flag is set */\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ /* Return RESET if the ADC interrupt flag is reset */\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_ClearITPendingBit\r
+* Description : Clears the ADC\92s interrupt pending bits. \r
+* Input : - ADC_IT: specifies the interrupt pending bit to clear. This \r
+* parameter can be can be any combination of the following \r
+* values:\r
+* - ADC_IT_ECH: End of chain conversion interrupt\r
+* - ADC_IT_EOC: End of channel conversion interrupt\r
+* - ADC_IT_JECH: Injected end of chain conversion interrupt\r
+* - ADC_IT_JEOC: Injected end of channel conversion interrupt\r
+* - ADC_IT_AnalogWatchdog0_LowThreshold: \r
+* Analog Watchdog 0 LowThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog0_HighThreshold: \r
+* Analog Watchdog 0 HighThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog1_LowThreshold: \r
+* Analog Watchdog 1 LowThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog1_HighThreshold: \r
+* Analog Watchdog 1 HighThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog2_LowThreshold: \r
+* Analog Watchdog 2 LowThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog2_HighThreshold: \r
+* Analog Watchdog 2 HighThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog3_LowThreshold: \r
+* Analog Watchdog 3 LowThreshold interrupt\r
+* - ADC_IT_AnalogWatchdog3_HighThreshold: \r
+* Analog Watchdog 5 HighThreshold interrupt\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_ClearITPendingBit(u16 ADC_IT)\r
+{\r
+ /* Clear the selected ADC interrupts pending bits */\r
+ ADC->PBR = ADC_IT;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_can.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file provides all the CAN software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_can.h"\r
+#include "75x_mrcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+/* Macro Name : xxx_ID_MSK, xxx_ID_ARB */\r
+/* Description : Form the Mask and Arbitration registers value to filter */\r
+/* a range of identifiers or a fixed identifier, for standard*/\r
+/* and extended IDs */\r
+/*----------------------------------------------------------------------------*/\r
+#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start)))\r
+#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end))\r
+\r
+#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id))\r
+#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id))\r
+\r
+#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2))\r
+#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2))\r
+\r
+#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2))\r
+#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2))\r
+\r
+#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11))\r
+#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03)))\r
+#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11))\r
+#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03)))\r
+\r
+#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11))\r
+#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03)))\r
+#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11))\r
+#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03)))\r
+\r
+/* macro to format the timing register value from the timing parameters*/\r
+#define CAN_TIMING(tseg1, tseg2, sjw, brp) ((((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F))\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* array of pre-defined timing parameters for standard bitrates*/\r
+u16 CanTimings[] = { /* value bitrate NTQ TSEG1 TSEG2 SJW BRP */\r
+ CAN_TIMING(11, 4, 4, 5), /* 0x3AC4 100 kbit/s 16 11 4 4 5 */\r
+ CAN_TIMING(11, 4, 4, 4), /* 0x3AC3 125 kbit/s 16 11 4 4 4 */\r
+ CAN_TIMING( 4, 3, 3, 4), /* 0x2383 250 kbit/s 8 4 3 3 4 */\r
+ CAN_TIMING(13, 2, 1, 1), /* 0x1C00 500 kbit/s 16 13 2 1 1 */\r
+ CAN_TIMING( 4, 3, 1, 1), /* 0x2300 1 Mbit/s 8 4 3 1 1 */\r
+};\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+static u32 GetFreeIF(void);\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_DeInit \r
+* Description : Deinitializes the CAN peripheral registers to their default \r
+* reset values. \r
+* Input : None \r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void CAN_DeInit (void)\r
+{\r
+ /* Reset the CAN registers values*/\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_CAN,ENABLE);\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_CAN,DISABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_Init \r
+* Description : Initializes the CAN peripheral according to the specified \r
+* parameters in the CAN_InitStruct. \r
+* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that\r
+* contains the configuration information for the CAN peripheral. \r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void CAN_Init(CAN_InitTypeDef* CAN_InitStruct)\r
+{\r
+ CAN_EnterInitMode(CAN_CR_CCE | CAN_InitStruct->CAN_ConfigParameters);\r
+ CAN_SetBitrate(CAN_InitStruct->CAN_Bitrate);\r
+ CAN_LeaveInitMode();\r
+ CAN_LeaveTestMode();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_StructInit \r
+* Description : Fills each CAN_InitStruct member with its reset value. \r
+* Input : CAN_InitStruct : pointer to a CAN_InitTypeDef structure which \r
+* will be initialized. \r
+* Output : None \r
+* Return : None. \r
+*******************************************************************************/\r
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)\r
+{\r
+/* Reset CAN init structure parameters values */\r
+ CAN_InitStruct->CAN_ConfigParameters = 0x0;\r
+ CAN_InitStruct->CAN_Bitrate = 0x2301;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_SetBitrate \r
+* Description : Setups a standard CAN bitrate. \r
+* Input : bitrate: specifies the bit rate. \r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void CAN_SetBitrate(u32 bitrate)\r
+{\r
+ CAN->BTR = CanTimings[bitrate]; /* write the predefined timing value */\r
+ CAN->BRPR = 0; /* clear the Extended Baud Rate Prescaler */\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_SetTiming \r
+* Description : Setups the CAN timing with specific parameters \r
+* Input : - tseg1: specifies Time Segment before the sample point.\r
+* This parameter must be a number between 1 and 16. \r
+* - tseg2: Time Segment after the sample point. This parameter \r
+* must be a number between 1 and 8. \r
+* - sjw: Synchronisation Jump Width. This parameter must be \r
+* a number between 1 and 4.\r
+* - brp: Baud Rate Prescaler. This parameter must be a number\r
+* between 1 and 1024. \r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp)\r
+{\r
+ CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp);\r
+ CAN->BRPR = ((brp-1) >> 6) & 0x0F;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GetFreeIF \r
+* Description : Searchs the first free message interface, starting from 0. \r
+* Input : None \r
+* Output : None \r
+* Return : A free message interface number (0 or 1) if found, else 2 \r
+*******************************************************************************/\r
+static u32 GetFreeIF(void)\r
+{\r
+ if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0)\r
+ return 0;\r
+ else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0)\r
+ return 1;\r
+ else\r
+ return 2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_SetUnusedMsgObj \r
+* Description : Configures the message object as unused \r
+* Input : msgobj: specifies the Message object number, from 0 to 31. \r
+* Output : None \r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Interface to treat the message\r
+* - ERROR: No interface found to treat the message\r
+*******************************************************************************/\r
+ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj)\r
+{\r
+ u32 msg_if=0;\r
+\r
+ if ((msg_if = GetFreeIF()) == 2)\r
+ {\r
+ return ERROR;\r
+ }\r
+\r
+ CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD\r
+ | CAN_CMR_MASK\r
+ | CAN_CMR_ARB\r
+ | CAN_CMR_CONTROL\r
+ | CAN_CMR_DATAA\r
+ | CAN_CMR_DATAB;\r
+\r
+ CAN->sMsgObj[msg_if].M1R = 0;\r
+ CAN->sMsgObj[msg_if].M2R = 0;\r
+\r
+ CAN->sMsgObj[msg_if].A1R = 0;\r
+ CAN->sMsgObj[msg_if].A2R = 0;\r
+\r
+ CAN->sMsgObj[msg_if].MCR = 0;\r
+\r
+ CAN->sMsgObj[msg_if].DA1R = 0;\r
+ CAN->sMsgObj[msg_if].DA2R = 0;\r
+ CAN->sMsgObj[msg_if].DB1R = 0;\r
+ CAN->sMsgObj[msg_if].DB2R = 0;\r
+\r
+ CAN->sMsgObj[msg_if].CRR = 1 + msgobj;\r
+ \r
+ return SUCCESS;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_SetTxMsgObj \r
+* Description : Configures the message object as TX. \r
+* Input : - msgobj: specifies the Message object number, from 0 to 31. \r
+* - idType: specifies the identifier type of the frames that\r
+* will be transmitted using this message object.\r
+* This parameter can be one of the following values:\r
+* - CAN_STD_ID (standard ID, 11-bit)\r
+* - CAN_EXT_ID (extended ID, 29-bit) \r
+* Output : None \r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Interface to treat the message\r
+* - ERROR: No interface found to treat the message\r
+*******************************************************************************/\r
+ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType)\r
+{\r
+ u32 msg_if=0;\r
+\r
+ if ((msg_if = GetFreeIF()) == 2)\r
+ {\r
+ return ERROR;\r
+ }\r
+ \r
+ CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD\r
+ | CAN_CMR_MASK\r
+ | CAN_CMR_ARB\r
+ | CAN_CMR_CONTROL\r
+ | CAN_CMR_DATAA\r
+ | CAN_CMR_DATAB;\r
+\r
+ CAN->sMsgObj[msg_if].M1R = 0;\r
+ CAN->sMsgObj[msg_if].A1R = 0;\r
+\r
+ if (idType == CAN_STD_ID)\r
+ {\r
+ CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR;\r
+ CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR;\r
+ }\r
+ else\r
+ {\r
+ CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD;\r
+ CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD;\r
+ }\r
+\r
+ CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB;\r
+\r
+ CAN->sMsgObj[msg_if].DA1R = 0;\r
+ CAN->sMsgObj[msg_if].DA2R = 0;\r
+ CAN->sMsgObj[msg_if].DB1R = 0;\r
+ CAN->sMsgObj[msg_if].DB2R = 0;\r
+\r
+ CAN->sMsgObj[msg_if].CRR = 1 + msgobj;\r
+ \r
+ return SUCCESS;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_SetRxMsgObj \r
+* Description : Configures the message object as RX. \r
+* Input : - msgobj: specifies the Message object number, from 0 to 31. \r
+* - idType: specifies the identifier type of the frames that\r
+* will be transmitted using this message object.\r
+* This parameter can be one of the following values:\r
+* - CAN_STD_ID (standard ID, 11-bit)\r
+* - CAN_EXT_ID (extended ID, 29-bit) \r
+* - idLow: specifies the low part of the identifier range used \r
+* for acceptance filtering.\r
+* - idHigh: specifies the high part of the identifier range \r
+* used for acceptance filtering.\r
+* - singleOrFifoLast: specifies the end-of-buffer indicator.\r
+* This parameter can be one of the following values:\r
+* - TRUE: for a single receive object or a FIFO receive\r
+* object that is the last one of the FIFO. \r
+* - FALSE: for a FIFO receive object that is not the \r
+* last one. \r
+* Output : None \r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Interface to treat the message\r
+* - ERROR: No interface found to treat the message\r
+*******************************************************************************/\r
+ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast)\r
+{\r
+ u32 msg_if=0;\r
+\r
+ if ((msg_if = GetFreeIF()) == 2)\r
+ {\r
+ return ERROR;\r
+ }\r
+ \r
+ CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD\r
+ | CAN_CMR_MASK\r
+ | CAN_CMR_ARB\r
+ | CAN_CMR_CONTROL\r
+ | CAN_CMR_DATAA\r
+ | CAN_CMR_DATAB;\r
+\r
+ if (idType == CAN_STD_ID)\r
+ {\r
+ CAN->sMsgObj[msg_if].M1R = 0;\r
+ CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh);\r
+\r
+ CAN->sMsgObj[msg_if].A1R = 0;\r
+ CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh);\r
+ }\r
+ else\r
+ {\r
+ CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh);\r
+ CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh);\r
+\r
+ CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh);\r
+ CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh);\r
+ }\r
+\r
+ CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0);\r
+\r
+ CAN->sMsgObj[msg_if].DA1R = 0;\r
+ CAN->sMsgObj[msg_if].DA2R = 0;\r
+ CAN->sMsgObj[msg_if].DB1R = 0;\r
+ CAN->sMsgObj[msg_if].DB2R = 0;\r
+\r
+ CAN->sMsgObj[msg_if].CRR = 1 + msgobj;\r
+ \r
+ return SUCCESS;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_InvalidateAllMsgObj \r
+* Description : Configures all the message objects as unused. \r
+* Input : None \r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void CAN_InvalidateAllMsgObj(void)\r
+{\r
+ u32 i=0;\r
+ for (i = 0; i < 32; i++)\r
+ CAN_SetUnusedMsgObj(i);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_ReleaseMessage \r
+* Description : Releases the message object \r
+* Input : - msgobj: specifies the Message object number, from 0 to 31. \r
+* Output : None \r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Interface to treat the message\r
+* - ERROR: No interface found to treat the message\r
+*******************************************************************************/\r
+ErrorStatus CAN_ReleaseMessage(u32 msgobj)\r
+{\r
+ u32 msg_if=0;\r
+\r
+ if ((msg_if = GetFreeIF()) == 2)\r
+ {\r
+ return ERROR;\r
+ }\r
+\r
+ CAN->sMsgObj[msg_if].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT;\r
+ CAN->sMsgObj[msg_if].CRR = 1 + msgobj;\r
+ \r
+ return SUCCESS;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_SendMessage \r
+* Description : Start transmission of a message \r
+* Input : - msgobj: specifies the Message object number, from 0 to 31. \r
+* : - pCanMsg: pointer to the message structure containing data \r
+* to transmit.\r
+* Output : None \r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Transmission OK\r
+* - ERROR: No transmission\r
+*******************************************************************************/\r
+ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg)\r
+{\r
+ if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY)\r
+ {\r
+ return ERROR; \r
+ }\r
+\r
+ CAN->SR &= ~CAN_SR_TXOK;\r
+\r
+ /* read the Arbitration and Message Control*/\r
+ CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL;\r
+\r
+ CAN->sMsgObj[0].CRR = 1 + msgobj;\r
+\r
+ if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY)\r
+ {\r
+ return ERROR; \r
+ }\r
+\r
+ /* update the contents needed for transmission*/\r
+ CAN->sMsgObj[0].CMR = CAN_CMR_WRRD\r
+ | CAN_CMR_ARB\r
+ | CAN_CMR_CONTROL\r
+ | CAN_CMR_DATAA\r
+ | CAN_CMR_DATAB;\r
+\r
+ if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0)\r
+ {\r
+ /* standard ID*/\r
+ CAN->sMsgObj[0].A1R = 0;\r
+ CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id);\r
+ }\r
+ else\r
+ {\r
+ /* extended ID*/\r
+ CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id);\r
+ CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id);\r
+ }\r
+\r
+ CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc;\r
+\r
+ CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0];\r
+ CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2];\r
+ CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4];\r
+ CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6];\r
+\r
+ CAN->sMsgObj[0].CRR = 1 + msgobj;\r
+\r
+ return SUCCESS;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_ReceiveMessage \r
+* Description : Gets the message, if received.\r
+* Input : - msgobj: specifies the Message object number, from 0 to 31. \r
+* - release: specifies the message release indicator.\r
+* This parameter can be one of the following values:\r
+* - TRUE: the message object is released when getting \r
+* the data.\r
+* - FALSE: the message object is not released.\r
+* - pCanMsg: pointer to the message structure where received \r
+* data is copied.\r
+* Output : None \r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Reception OK\r
+* - ERROR: No message pending\r
+*******************************************************************************/\r
+ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg)\r
+{\r
+ if (!CAN_IsMessageWaiting(msgobj))\r
+ {\r
+ return ERROR;\r
+ }\r
+\r
+ CAN->SR &= ~CAN_SR_RXOK;\r
+\r
+ /* read the message contents*/\r
+ CAN->sMsgObj[1].CMR = CAN_CMR_MASK\r
+ | CAN_CMR_ARB\r
+ | CAN_CMR_CONTROL\r
+ | CAN_CMR_CLRINTPND\r
+ | (release ? CAN_CMR_TXRQSTNEWDAT : 0)\r
+ | CAN_CMR_DATAA\r
+ | CAN_CMR_DATAB;\r
+\r
+ CAN->sMsgObj[1].CRR = 1 + msgobj;\r
+\r
+ if (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY)\r
+ {\r
+ return ERROR; \r
+ }\r
+ \r
+ if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0)\r
+ {\r
+ /* standard ID*/\r
+ pCanMsg->IdType = CAN_STD_ID;\r
+ pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF;\r
+ }\r
+ else\r
+ {\r
+ /* extended ID*/\r
+ pCanMsg->IdType = CAN_EXT_ID;\r
+ pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); \r
+ pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11);\r
+ pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27);\r
+ }\r
+\r
+ pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F;\r
+\r
+ pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R;\r
+ pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8);\r
+ pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R;\r
+ pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8);\r
+ pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R;\r
+ pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8);\r
+ pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R;\r
+ pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8);\r
+\r
+ return SUCCESS;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_WaitEndOfTx \r
+* Description : Waits until current transmission is finished. \r
+* Input : None \r
+* Output : None \r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Transmission ended\r
+* - ERROR: Transmission did not occur yet\r
+*******************************************************************************/\r
+ErrorStatus CAN_WaitEndOfTx(void)\r
+{\r
+ if ((CAN->SR & CAN_SR_TXOK) == 0)\r
+ {\r
+ return ERROR;\r
+ }\r
+ CAN->SR &= ~CAN_SR_TXOK;\r
+ \r
+ return SUCCESS;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_BasicSendMessage \r
+* Description : Starts transmission of a message in BASIC mode. This mode \r
+* does not use the message RAM. \r
+* Input : pCanMsg: Pointer to the message structure containing data to \r
+* transmit. \r
+* Output : None \r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Transmission OK\r
+* - ERROR: No transmission\r
+*******************************************************************************/\r
+ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg)\r
+{\r
+ /* clear NewDat bit in IF2 to detect next reception*/\r
+ CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT;\r
+\r
+ CAN->SR &= ~CAN_SR_TXOK;\r
+ CAN->sMsgObj[0].CMR = CAN_CMR_WRRD\r
+ | CAN_CMR_ARB\r
+ | CAN_CMR_CONTROL\r
+ | CAN_CMR_DATAA\r
+ | CAN_CMR_DATAB;\r
+\r
+ if (pCanMsg->IdType == CAN_STD_ID)\r
+ {\r
+ /* standard ID*/\r
+ CAN->sMsgObj[0].A1R = 0;\r
+ CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id);\r
+ }\r
+ else\r
+ {\r
+ /* extended ID*/\r
+ CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id);\r
+ CAN->sMsgObj[0].A2R = ((CAN->sMsgObj[0].A2R) & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id);\r
+ }\r
+\r
+ CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc;\r
+\r
+ CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0];\r
+ CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2];\r
+ CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4];\r
+ CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6];\r
+\r
+ /* request transmission*/\r
+ if (CAN->sMsgObj[0].CRR == CAN_CRR_BUSY )\r
+ {\r
+ return ERROR;\r
+ }\r
+\r
+ return SUCCESS;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_BasicReceiveMessage \r
+* Description : Gets the message in BASIC mode, if received. This mode does\r
+* not use the message RAM. \r
+* Input : pCanMsg: pointer to the message structure where message is copied. \r
+* Output : None \r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Reception OK\r
+* - ERROR: No message pending\r
+*******************************************************************************/\r
+ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg)\r
+{\r
+ if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0)\r
+ {\r
+ return ERROR;\r
+ }\r
+\r
+ CAN->SR &= ~CAN_SR_RXOK;\r
+\r
+ CAN->sMsgObj[1].CMR = CAN_CMR_ARB\r
+ | CAN_CMR_CONTROL\r
+ | CAN_CMR_DATAA\r
+ | CAN_CMR_DATAB;\r
+\r
+ if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0)\r
+ {\r
+ /* standard ID*/\r
+ pCanMsg->IdType = CAN_STD_ID;\r
+ pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF;\r
+ }\r
+ else\r
+ {\r
+ /* extended ID*/\r
+ pCanMsg->IdType = CAN_EXT_ID;\r
+ pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF);\r
+ pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11);\r
+ pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27);\r
+ }\r
+\r
+ pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F;\r
+\r
+ pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R;\r
+ pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8);\r
+ pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R;\r
+ pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8);\r
+ pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R;\r
+ pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8);\r
+ pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R;\r
+ pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8);\r
+\r
+ return SUCCESS;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_EnterInitMode \r
+* Description : Switchs the CAN into initialization mode. This function must\r
+* be used in conjunction with CAN_LeaveInitMode(). \r
+* Input : InitMask: specifies the CAN configuration in normal mode. \r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void CAN_EnterInitMode(u8 InitMask)\r
+{\r
+ CAN->CR = InitMask | CAN_CR_INIT;\r
+ CAN->SR = 0; /* reset the status*/\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_LeaveInitMode \r
+* Description : Leaves the initialization mode (switch into normal mode).\r
+* This function must be used in conjunction with CAN_EnterInitMode(). \r
+* Input : None \r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void CAN_LeaveInitMode(void)\r
+{\r
+ CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_EnterTestMode \r
+* Description : Switchs the CAN into test mode. This function must be used in\r
+* conjunction with CAN_LeaveTestMode(). \r
+* Input : TestMask: specifies the configuration in test modes. \r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void CAN_EnterTestMode(u8 TestMask)\r
+{\r
+ CAN->CR |= CAN_CR_TEST;\r
+ CAN->TESTR |= TestMask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_LeaveTestMode \r
+* Description : Leaves the current test mode (switch into normal mode).\r
+* This function must be used in conjunction with CAN_EnterTestMode(). \r
+* Input : None \r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void CAN_LeaveTestMode(void)\r
+{\r
+ CAN->CR |= CAN_CR_TEST;\r
+ CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC);\r
+ CAN->CR &= ~CAN_CR_TEST;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_ReleaseTxMessage \r
+* Description : Releases the transmit message object.\r
+* Input : - msgobj: specifies the Message object number, from 0 to 31. \r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void CAN_ReleaseTxMessage(u32 msgobj)\r
+{\r
+ CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT;\r
+ CAN->sMsgObj[0].CRR = 1 + msgobj;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_ReleaseRxMessage \r
+* Description : Releases the receive message object. \r
+* Input : - msgobj: specifies the Message object number, from 0 to 31. \r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void CAN_ReleaseRxMessage(u32 msgobj)\r
+{\r
+ CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT;\r
+ CAN->sMsgObj[1].CRR = 1 + msgobj;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_IsMessageWaiting \r
+* Description : Tests the waiting status of a received message. \r
+* Input : - msgobj: specifies the Message object number, from 0 to 31. \r
+* Output : None \r
+* Return : A non-zero value if the corresponding message object has \r
+* received a message waiting to be copied, else 0. \r
+*******************************************************************************/\r
+u32 CAN_IsMessageWaiting(u32 msgobj)\r
+{\r
+ return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16)));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_IsTransmitRequested \r
+* Description : Tests the request status of a transmitted message. \r
+* Input : - msgobj: specifies the Message object number, from 0 to 31. \r
+* Output : None \r
+* Return : A non-zero value if the corresponding message is requested\r
+* to transmit, else 0. \r
+*******************************************************************************/\r
+u32 CAN_IsTransmitRequested(u32 msgobj)\r
+{\r
+ return (msgobj < 16 ? CAN->TXR1R & (1 << msgobj) : CAN->TXR2R & (1 << (msgobj-16)));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_IsInterruptPending \r
+* Description : Tests the interrupt status of a message object. \r
+* Input : - msgobj: specifies the Message object number, from 0 to 31. \r
+* Output : None \r
+* Return : A non-zero value if the corresponding message has an \r
+* interrupt pending, else 0. \r
+*******************************************************************************/\r
+u32 CAN_IsInterruptPending(u32 msgobj)\r
+{\r
+ return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16)));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_IsObjectValid \r
+* Description : Tests the validity of a message object (ready to use). \r
+* Input : - msgobj: specifies the Message object number, from 0 to 31. \r
+* Output : None \r
+* Return : A non-zero value if the corresponding message object is \r
+* valid, else 0. \r
+*******************************************************************************/\r
+u32 CAN_IsObjectValid(u32 msgobj)\r
+{\r
+ return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16)));\r
+}\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_cfg.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file provides all the CFG software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_cfg.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define CFG_SWBOOT_Mask 0xFFFFFFFC\r
+#define CFG_FLASHBusy_Mask 0x00000080\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : CFG_BootSpaceConfig\r
+* Description : Selects which memory space will be remapped at address 0x00.\r
+* Input : - CFG_BootSpace: specifies the memory space to be remapped\r
+* at address 0x00.\r
+* This parameter can be one of the following values:\r
+* - CFG_BootSpace_FLASH\r
+* - CFG_BootSpace_SRAM\r
+* - CFG_BootSpace_ExtSMI\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void CFG_BootSpaceConfig(u32 CFG_BootSpace)\r
+{\r
+ u32 Temp = 0;\r
+ \r
+ /* Clear SW_BOOT[1:0] bits */ \r
+ Temp = CFG->GLCONF & CFG_SWBOOT_Mask;\r
+ \r
+ /* Set SW_BOOT[1:0] bits according to CFG_BootSpace parameter value */ \r
+ Temp |= CFG_BootSpace;\r
+ \r
+ /* Store the new value */ \r
+ CFG->GLCONF = Temp; \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CFG_FLASHBurstConfig\r
+* Description : Enables or disables the FLASH Burst mode.\r
+* Input : - CCFG_FLASHBurst: specifies the new state of the FLASH Burst\r
+* mode.\r
+* This parameter can be one of the following values:\r
+* - CFG_FLASHBurst_Disable\r
+* - CFG_FLASHBurst_Enable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void CFG_FLASHBurstConfig(u32 CFG_FLASHBurst)\r
+{\r
+ if(CFG_FLASHBurst == CFG_FLASHBurst_Enable)\r
+ {\r
+ CFG->GLCONF |= CFG_FLASHBurst_Enable;\r
+ }\r
+ else\r
+ {\r
+ CFG->GLCONF &= CFG_FLASHBurst_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CFG_USBFilterConfig\r
+* Description : Enables or disables the USB Filter.\r
+* Input : - CFG_USBFilter: specifies the new state of the USB Filter.\r
+* This parameter can be one of the following values:\r
+* - CFG_USBFilter_Disable\r
+* - CFG_USBFilter_Enable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void CFG_USBFilterConfig(u32 CFG_USBFilter)\r
+{\r
+ if(CFG_USBFilter == CFG_USBFilter_Enable)\r
+ {\r
+ CFG->GLCONF |= CFG_USBFilter_Enable;\r
+ }\r
+ else\r
+ {\r
+ CFG->GLCONF &= CFG_USBFilter_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CFG_GetFlagStatus\r
+* Description : Checks whether the FLASH Busy flag is set or not.\r
+* Input : None\r
+* Output : None\r
+* Return : The new state of FLASH Busy flag (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus CFG_GetFlagStatus(void)\r
+{\r
+ if((CFG->GLCONF & CFG_FLASHBusy_Mask) != RESET)\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_dma.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006 \r
+* Description : This file provides all the DMA software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, \r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING \r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_dma.h"\r
+#include "75x_mrcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+/* DMA enable */\r
+#define DMA_Enable 0x0001\r
+#define DMA_Disable 0xFFFE\r
+\r
+/* DMA Last Buffer Sweep */\r
+#define DMA_Last0_Enable_Mask 0x0001\r
+#define DMA_Last0_Disable_Mask 0xFFFE\r
+#define DMA_Last1_Enable_Mask 0x0002\r
+#define DMA_Last1_Disable_Mask 0xFFFD\r
+#define DMA_Last2_Enable_Mask 0x0004\r
+#define DMA_Last2_Disable_Mask 0xFFFB\r
+#define DMA_Last3_Enable_Mask 0x0008\r
+#define DMA_Last3_Disable_Mask 0xFFF7\r
+\r
+/* DMA Masks */\r
+#define DMA_Stream0_MASK_Mask 0xFFEE\r
+#define DMA_Stream0_CLR_Mask 0x0011\r
+#define DMA_Stream0_LAST_Mask 0xFFFE\r
+\r
+#define DMA_Stream1_MASK_Mask 0xFFDD\r
+#define DMA_Stream1_CLR_Mask 0x0022\r
+#define DMA_Stream1_LAST_Mask 0xFFFD\r
+\r
+#define DMA_Stream2_MASK_Mask 0xFFBB\r
+#define DMA_Stream2_CLR_Mask 0x0044\r
+#define DMA_Stream2_LAST_Mask 0xFFFB\r
+\r
+#define DMA_Stream3_MASK_Mask 0xFF77\r
+#define DMA_Stream3_CLR_Mask 0x0088\r
+#define DMA_Stream3_LAST_Mask 0xFFF7\r
+\r
+#define DMA_SRCSize_Mask 0xFFE7\r
+#define DMA_SRCBurst_Mask 0xFF9F\r
+#define DMA_DSTSize_Mask 0xFE7F \r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/*******************************************************************************\r
+* Function Name : DMA_DeInit\r
+* Description : Deinitializes the DMA streamx registers to their default reset\r
+* values.\r
+* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA\r
+* Stream.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void DMA_DeInit(DMA_Stream_TypeDef* DMA_Streamx)\r
+{\r
+ /* Reset streamx source base address register */\r
+ DMA_Streamx->SOURCEL = 0;\r
+ DMA_Streamx->SOURCEH = 0;\r
+\r
+ /* Reset streamx destination base address register */\r
+ DMA_Streamx->DESTL = 0;\r
+ DMA_Streamx->DESTH = 0;\r
+\r
+ /* Reset streamx maximum count register */\r
+ DMA_Streamx->MAX = 0;\r
+ /* Reset streamx control register */\r
+ DMA_Streamx->CTRL = 0;\r
+ /* Reset streamx last used buffer location register */\r
+ DMA_Streamx->LUBUFF = 0;\r
+\r
+ switch(*(u32*)&DMA_Streamx)\r
+ {\r
+ case DMA_Stream0_BASE:\r
+ /* Reset interrupt mask, clear and flag bits for stream0 */\r
+ DMA->MASK &= DMA_Stream0_MASK_Mask;\r
+ DMA->CLR |= DMA_Stream0_CLR_Mask;\r
+ DMA->LAST &= DMA_Stream0_LAST_Mask;\r
+ break;\r
+\r
+ case DMA_Stream1_BASE:\r
+ /* Reset interrupt mask, clear and flag bits for stream1 */\r
+ DMA->MASK &= DMA_Stream1_MASK_Mask;\r
+ DMA->CLR |= DMA_Stream1_CLR_Mask;\r
+ DMA->LAST &= DMA_Stream1_LAST_Mask;\r
+ break;\r
+\r
+ case DMA_Stream2_BASE:\r
+ /* Reset interrupt mask, clear and flag bits for stream2 */\r
+ DMA->MASK &= DMA_Stream2_MASK_Mask;\r
+ DMA->CLR |= DMA_Stream2_CLR_Mask;\r
+ DMA->LAST &= DMA_Stream2_LAST_Mask;\r
+ break;\r
+\r
+ case DMA_Stream3_BASE:\r
+ /* Reset interrupt mask, clear and flag bits for stream3 */\r
+ DMA->MASK &= DMA_Stream3_MASK_Mask;\r
+ DMA->CLR |= DMA_Stream3_CLR_Mask;\r
+ DMA->LAST &= DMA_Stream3_LAST_Mask;\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_Init\r
+* Description : Initializes the DMAx stream according to the specified\r
+* parameters in the DMA_InitStruct.\r
+* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA\r
+* Stream.\r
+* - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that\r
+* contains the configuration information for the specified\r
+* DMA stream.\r
+* Output : None\r
+* Return : None\r
+******************************************************************************/\r
+void DMA_Init(DMA_Stream_TypeDef* DMA_Streamx, DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+ /* set the buffer Size */\r
+ DMA_Streamx->MAX = DMA_InitStruct->DMA_BufferSize ;\r
+\r
+ /* Configure the incrementation of the current source Register */\r
+ if(DMA_InitStruct->DMA_SRC == DMA_SRC_INCR)\r
+ {\r
+ /* Increment current source register */\r
+ DMA_Streamx->CTRL |= DMA_SRC_INCR;\r
+ }\r
+ else \r
+ {\r
+ /* Current source register unchanged */\r
+ DMA_Streamx->CTRL &= DMA_SRC_NOT_INCR;\r
+ }\r
+ \r
+ /* Configure the incrementation of the current destination Register */\r
+ if(DMA_InitStruct->DMA_DST == DMA_DST_INCR)\r
+ {\r
+ /* Increment current source register */\r
+ DMA_Streamx->CTRL |= DMA_DST_INCR;\r
+ }\r
+ else \r
+ {\r
+ /* Current source register unchanged */\r
+ DMA_Streamx->CTRL &= DMA_DST_NOT_INCR;\r
+ }\r
+ \r
+ /* Clear source to DMA data width SOSIZE[1:0] bits */\r
+ DMA_Streamx->CTRL &= DMA_SRCSize_Mask;\r
+ /* Set the source to DMA data width */\r
+ DMA_Streamx->CTRL |= DMA_InitStruct->DMA_SRCSize;\r
+ \r
+ /* Clear the DMA peripheral burst size SOBURST[1:0] bits */\r
+ DMA_Streamx->CTRL &= DMA_SRCBurst_Mask;\r
+ /* Set the DMA peripheral burst size */\r
+ DMA_Streamx->CTRL |= DMA_InitStruct->DMA_SRCBurst;\r
+ \r
+ /* Clear destination to DMA dat width DESIZE[1:0] bits */\r
+ DMA_Streamx->CTRL &= DMA_DSTSize_Mask;\r
+ /* Set the destination to DMA data width */\r
+ DMA_Streamx->CTRL |= DMA_InitStruct->DMA_DSTSize;\r
+ \r
+ /* Configure the circular mode */\r
+ if(DMA_InitStruct->DMA_Mode == DMA_Mode_Circular)\r
+ {\r
+ /* Set circular mode */\r
+ DMA_Streamx->CTRL |= DMA_Mode_Circular;\r
+ }\r
+ else \r
+ {\r
+ /* Set normal mode */\r
+ DMA_Streamx->CTRL &= DMA_Mode_Normal;\r
+ } \r
+ \r
+ /* Configure the direction transfer */\r
+ if(DMA_InitStruct->DMA_DIR == DMA_DIR_PeriphDST)\r
+ {\r
+ /* Set peripheral as destination */\r
+ DMA_Streamx->CTRL |= DMA_DIR_PeriphDST;\r
+ }\r
+ else \r
+ {\r
+ /* Set peripheral as source */\r
+ DMA_Streamx->CTRL &= DMA_DIR_PeriphSRC;\r
+ } \r
+ \r
+ /* Configure the memory to memory transfer only for stream3 */\r
+ if(DMA_Streamx == DMA_Stream3)\r
+ {\r
+ if(DMA_InitStruct->DMA_M2M == DMA_M2M_Enable)\r
+ {\r
+ /* Enable memory to memory transfer for stream3 */\r
+ DMA_Streamx->CTRL |= DMA_M2M_Enable;\r
+ }\r
+ else \r
+ {\r
+ /* Disable memory to memory transfer for stream3 */\r
+ DMA_Streamx->CTRL &= DMA_M2M_Disable;\r
+ } \r
+ }\r
+\r
+ /* Configure the source base address */\r
+ DMA_Streamx->SOURCEL = DMA_InitStruct->DMA_SRCBaseAddr;\r
+ DMA_Streamx->SOURCEH = DMA_InitStruct->DMA_SRCBaseAddr >> 16;\r
+\r
+ /* Configure the destination base address */\r
+ DMA_Streamx->DESTL = DMA_InitStruct->DMA_DSTBaseAddr;\r
+ DMA_Streamx->DESTH = DMA_InitStruct->DMA_DSTBaseAddr >> 16;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_StructInit\r
+* Description : Fills each DMA_InitStruct member with its default value.\r
+* Input : DMA_InitStruct : pointer to a DMA_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+ /* Initialize the DMA_BufferSize member */\r
+ DMA_InitStruct->DMA_BufferSize = 0;\r
+\r
+ /* initialize the DMA_SRCBaseAddr member */\r
+ DMA_InitStruct->DMA_SRCBaseAddr = 0;\r
+\r
+ /* Initialize the DMA_DSTBaseAddr member */\r
+ DMA_InitStruct ->DMA_DSTBaseAddr = 0;\r
+ \r
+ /* Initialize the DMA_SRC member */\r
+ DMA_InitStruct->DMA_SRC = DMA_SRC_NOT_INCR;\r
+ \r
+ /* Initialize the DMA_DST member */\r
+ DMA_InitStruct->DMA_DST = DMA_DST_NOT_INCR;\r
+ \r
+ /* Initialize the DMA_SRCSize member */\r
+ DMA_InitStruct->DMA_SRCSize = DMA_SRCSize_Byte;\r
+ \r
+ /* Initialize the DMA_SRCBurst member */\r
+ DMA_InitStruct->DMA_SRCBurst = DMA_SRCBurst_1Data;\r
+ \r
+ /* Initialize the DMA_DSTSize member */\r
+ DMA_InitStruct->DMA_DSTSize = DMA_DSTSize_Byte;\r
+ \r
+ /* Initialize the DMA_Mode member */\r
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;\r
+ \r
+ /* Initialize the DMA_M2M member */\r
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;\r
+\r
+ /* Initialize the DMA_DIR member */\r
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeriphSRC;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_Cmd\r
+* Description : Enables or disables the specified DMA stream.\r
+* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA\r
+* Stream.\r
+* - NewState: new state of the DMAx stream. This parameter can\r
+* be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void DMA_Cmd(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Enable the selected DMA streamx */\r
+ DMA_Streamx->CTRL |= DMA_Enable;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA streamx */\r
+ DMA_Streamx->CTRL &= DMA_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_ITConfig\r
+* Description : Enables or disables the specified DMA interrupts.\r
+* Input : - DMA_IT: specifies the DMA interrupts sources to be enabled\r
+* or disabled. This parameter can be any combination of the\r
+* following values:\r
+* - DMA_IT_SI0: Stream0 transfer end interrupt mask\r
+* - DMA_IT_SI1: Stream1 transfer end interrupt mask\r
+* - DMA_IT_SI2: Stream2 transfer end interrupt mask\r
+* - DMA_IT_SI3: Stream3 transfer end interrupt mask\r
+* - DMA_IT_SE0: Stream0 transfer error interrupt mask\r
+* - DMA_IT_SE1: Stream1 transfer error interrupt mask\r
+* - DMA_IT_SE2: Stream2 transfer error interrupt mask\r
+* - DMA_IT_SE3: Stream3 transfer error interrupt mask\r
+* - DMA_IT_ALL: ALL DMA interrupts mask\r
+* - NewState: new state of the specified DMA interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void DMA_ITConfig(u16 DMA_IT, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Enable the selected DMA interrupts */\r
+ DMA->MASK |= DMA_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA interrupts */\r
+ DMA->MASK &= ~DMA_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_GetCurrDSTAddr\r
+* Description : Returns the current value of the destination address pointer\r
+* related to the specified DMA stream.\r
+* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA\r
+* Stream.\r
+* Output : None\r
+* Return : The current value of the destination address pointer related\r
+* to the specified DMA stream.\r
+*******************************************************************************/\r
+u32 DMA_GetCurrDSTAddr(DMA_Stream_TypeDef* DMA_Streamx)\r
+{ \r
+ u32 Tmp = 0;\r
+\r
+ /* Get high current destination address */\r
+ Tmp = (DMA_Streamx->DECURRH)<<16;\r
+ /* Get low current destination address */\r
+ Tmp |= DMA_Streamx->DECURRL;\r
+\r
+ /* Return the current destination address value for streamx */\r
+ return Tmp;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_GetCurrSRCAddr\r
+* Description : Returns the current value of the source address pointer\r
+* related to the specified DMA stream.\r
+* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA\r
+* Stream.\r
+* Output : None\r
+* Return : The current value of the source address pointer related to\r
+* the specified DMA stream.\r
+*******************************************************************************/\r
+u32 DMA_GetCurrSRCAddr(DMA_Stream_TypeDef* DMA_Streamx)\r
+{\r
+ u32 Tmp = 0;\r
+\r
+ /* Get high current source address */\r
+ Tmp = (DMA_Streamx->SOCURRH)<<16;\r
+ /* Get slow current source address */\r
+ Tmp |= DMA_Streamx->SOCURRL;\r
+\r
+ /* Return the current source address value for streamx */\r
+ return Tmp;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_GetTerminalCounter\r
+* Description : Returns the number of data units remaining in the current\r
+* DMA stream transfer.\r
+* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA\r
+* Stream.\r
+* Output : None\r
+* Return : The number of data units remaining in the current DMA stream\r
+* transfer.\r
+*******************************************************************************/\r
+u16 DMA_GetTerminalCounter(DMA_Stream_TypeDef* DMA_Streamx)\r
+{\r
+ /* Return the terminal counter value for streamx */\r
+ return(DMA_Streamx->TCNT);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_LastBufferSweepConfig\r
+* Description : Activates or disactivates the last buffer sweep mode for the \r
+* DMA streamx configured in circular buffer mode.\r
+* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA\r
+* Stream.\r
+* - NewState: new state of the Last buffer sweep DMA_Streamx. \r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void DMA_LastBufferSweepConfig(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState)\r
+{ \r
+ switch(*(u32*)&DMA_Streamx)\r
+ {\r
+ case DMA_Stream0_BASE:\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Activates the last circular buffer sweep mode for stream0 */\r
+ DMA->LAST |= DMA_Last0_Enable_Mask;\r
+ }\r
+ else\r
+ {\r
+ /* Disactivates the last circular buffer sweep mode for stream0 */\r
+ DMA->LAST &= DMA_Last0_Disable_Mask;\r
+ } \r
+ break;\r
+\r
+ case DMA_Stream1_BASE:\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Activates the last circular buffer sweep mode for stream1 */\r
+ DMA->LAST |= DMA_Last1_Enable_Mask;\r
+ }\r
+ else\r
+ {\r
+ /* Disactivates the last circular buffer sweep mode for stream1 */\r
+ DMA->LAST &= DMA_Last1_Disable_Mask;\r
+ } \r
+ break;\r
+\r
+ case DMA_Stream2_BASE:\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Activates the last circular buffer sweep mode for stream2 */\r
+ DMA->LAST |= DMA_Last2_Enable_Mask;\r
+ }\r
+ else\r
+ {\r
+ /* Disactivates the last circular buffer sweep mode for stream2 */\r
+ DMA->LAST &= DMA_Last2_Disable_Mask;\r
+ } \r
+ break;\r
+\r
+ case DMA_Stream3_BASE:\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Activates the last circular buffer sweep mode for stream3 */\r
+ DMA->LAST |= DMA_Last3_Enable_Mask;\r
+ }\r
+ else\r
+ {\r
+ /* Disactivates the last circular buffer sweep mode for stream3 */\r
+ DMA->LAST &= DMA_Last3_Disable_Mask;\r
+ } \r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_LastBufferAddrConfig\r
+* Description : Configures the circular buffer position where the last data \r
+* to be used by the specified DMA stream is located.\r
+* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA\r
+* Stream.\r
+* - DMA_LastBufferAddr: specifies the circular buffer position\r
+* where the last data to be used by the specified DMA stream\r
+* is located.\r
+* This member must be a number between 0 and the stream BufferSize-1.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void DMA_LastBufferAddrConfig(DMA_Stream_TypeDef* DMA_Streamx, u16 DMA_LastBufferAddr)\r
+{\r
+ /* Set the streamx last data circular buffer location */\r
+ DMA_Streamx->LUBUFF = DMA_LastBufferAddr;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_GetFlagStatus\r
+* Description : Checks whether the specified DMA flag is set or not.\r
+* Input : - DMA_FLAG: specifies the flag to check. This parameter can \r
+* be one of the following values:\r
+* - DMA_FLAG_SI0: Stream0 transfer end flag.\r
+* - DMA_FLAG_SI1: Stream1 transfer end flag.\r
+* - DMA_FLAG_SI2: Stream2 transfer end flag.\r
+* - DMA_FLAG_SI3: Stream3 transfer end flag.\r
+* - DMA_FLAG_SE0: Stream0 transfer error flag.\r
+* - DMA_FLAG_SE1: Stream1 transfer error flag.\r
+* - DMA_FLAG_SE2: Stream2 transfer error flag.\r
+* - DMA_FLAG_SE3: Stream3 transfer error flag.\r
+* - DMA_FLAG_ACT0: Stream0 status.\r
+* - DMA_FLAG_ACT1: Stream1 status.\r
+* - DMA_FLAG_ACT2: Stream2 status.\r
+* - DMA_FLAG_ACT3: Stream3 status.\r
+* Output : None\r
+* Return : The new state of DMA_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus DMA_GetFlagStatus(u16 DMA_FLAG)\r
+{\r
+ /* Check the status of the specified DMA flag */\r
+ if((DMA->STATUS & DMA_FLAG) != RESET)\r
+ {\r
+ /* Return SET if DMA_FLAG is set */\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ /* Return RESET if DMA_FLAG is reset */\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_ClearFlag\r
+* Description : Clears the DMA\92s pending flags.\r
+* Input : - DMA_FLAG: specifies the flag to clear. This parameter can \r
+* be any combination of the following values:\r
+* - DMA_FLAG_SI0: Stream0 transfer end flag.\r
+* - DMA_FLAG_SI1: Stream1 transfer end flag.\r
+* - DMA_FLAG_SI2: Stream2 transfer end flag.\r
+* - DMA_FLAG_SI3: Stream3 transfer end flag.\r
+* - DMA_FLAG_SE0: Stream0 transfer error flag.\r
+* - DMA_FLAG_SE1: Stream1 transfer error flag.\r
+* - DMA_FLAG_SE2: Stream2 transfer error flag.\r
+* - DMA_FLAG_SE3: Stream3 transfer error flag.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void DMA_ClearFlag(u16 DMA_FLAG)\r
+{\r
+ /* Clear the selected DMA flags */ \r
+ DMA->CLR = DMA_FLAG ;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_GetITStatus\r
+* Description : Checks whether the specified DMA interrupt has occured or not.\r
+* Input : - DMA_IT: specifies the DMA interrupt source to check. \r
+* This parameter can be one of the following values:\r
+* - DMA_IT_SI0: Stream0 transfer end interrupt \r
+* - DMA_IT_SI1: Stream1 transfer end interrupt \r
+* - DMA_IT_SI2: Stream2 transfer end interrupt \r
+* - DMA_IT_SI3: Stream3 transfer end interrupt \r
+* - DMA_IT_SE0: Stream0 transfer error interrupt \r
+* - DMA_IT_SE1: Stream1 transfer error interrupt \r
+* - DMA_IT_SE2: Stream2 transfer error interrupt \r
+* - DMA_IT_SE3: Stream3 transfer error interrupt \r
+* Output : None\r
+* Return : The new state of DMA_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus DMA_GetITStatus(u16 DMA_IT)\r
+{\r
+ /* Check the status of the specified DMA interrupt */\r
+ if((DMA->STATUS & DMA_IT) != RESET)\r
+ {\r
+ /* Return SET if the DMA interrupt flag is set */\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ /* Return RESET if the DMA interrupt flag is reset */\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_ClearITPendingBit\r
+* Description : Clears the DMA\92s interrupt pending bits. \r
+* Input : - DMA_IT: specifies the interrupt pending bit to clear. \r
+* This parameter can be any combination of the following values:\r
+* - DMA_IT_SI0: Stream0 transfer end interrupt.\r
+* - DMA_IT_SI1: Stream1 transfer end interrupt.\r
+* - DMA_IT_SI2: Stream2 transfer end interrupt.\r
+* - DMA_IT_SI3: Stream3 transfer end interrupt.\r
+* - DMA_IT_SE0: Stream0 transfer error interrupt.\r
+* - DMA_IT_SE1: Stream1 transfer error interrupt.\r
+* - DMA_IT_SE2: Stream2 transfer error interrupt.\r
+* - DMA_IT_SE3: Stream3 transfer error interrupt.\r
+* - DMA_IT_ALL: All DMA interrupts.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void DMA_ClearITPendingBit(u16 DMA_IT)\r
+{\r
+ /* Clear the selected DMA interrupts pending bits */\r
+ DMA->CLR = DMA_IT ;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_eic.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file provides all the EIC software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_eic.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define EIC_IRQEnable_Mask 0x00000001\r
+#define EIC_IRQDisable_Mask 0xFFFFFFFE\r
+\r
+#define EIC_FIQEnable_Mask 0x00000002\r
+#define EIC_FIQDisable_Mask 0xFFFFFFFD\r
+\r
+#define EIC_SIPL_Mask 0x0000000F\r
+#define EIC_SIPL_Reset_Mask 0xFFFFFFF0\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_DeInit\r
+* Description : Deinitializes the EIC peripheral registers to their default\r
+* reset values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EIC_DeInit(void)\r
+{\r
+ EIC->ICR = 0x00;\r
+ EIC->CIPR = 0x00;\r
+ EIC->FIR = 0x0C;\r
+ EIC->IER = 0x00;\r
+ EIC->IPR = 0xFFFFFFFF;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_IRQInit\r
+* Description : Configures the IRQ channels according to the specified\r
+* parameters in the EIC_IRQInitStruct.\r
+* Input : EIC_IRQInitStruct: pointer to a EIC_IRQInitTypeDef structure.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EIC_IRQInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct)\r
+{\r
+ u32 Tmp = 0;\r
+\r
+ if(EIC_IRQInitStruct->EIC_IRQChannelCmd == ENABLE)\r
+ {\r
+ /* Enable the selected IRQ channel */\r
+ EIC->IER |= 1 << EIC_IRQInitStruct->EIC_IRQChannel;\r
+\r
+ /* Configure the selected IRQ channel priority ***************************/\r
+ /* Clear SIPL[3:0] bits */\r
+ EIC->SIRn[EIC_IRQInitStruct->EIC_IRQChannel] &= EIC_SIPL_Reset_Mask;\r
+\r
+ /* Configure SIPL[3:0] bits according to EIC_IRQChannelPriority parameter */\r
+ Tmp = EIC_IRQInitStruct->EIC_IRQChannelPriority & EIC_SIPL_Mask;\r
+ EIC->SIRn[EIC_IRQInitStruct->EIC_IRQChannel] |= Tmp;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the select IRQ channel */\r
+ EIC->IER &=~ (1 << EIC_IRQInitStruct->EIC_IRQChannel);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_FIQInit\r
+* Description : Configures the FIQ channels according to the specified\r
+* parameters in the EIC_FIQInitStruct.\r
+* Input : EIC_FIQInitStruct: pointer to a EIC_FIQInitTypeDef structure.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EIC_FIQInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct)\r
+{\r
+ if(EIC_FIQInitStruct->EIC_FIQChannelCmd == ENABLE)\r
+ {\r
+ /* Enable the selected FIQ channel */\r
+ EIC->FIER |= EIC_FIQInitStruct->EIC_FIQChannel ;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected FIQ channel */\r
+ EIC->FIER &= ~EIC_FIQInitStruct->EIC_FIQChannel;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_IRQStructInit\r
+* Description : Fills each EIC_IRQInitStruct member with its default value.\r
+* Input : EIC_IRQInitStruct: pointer to a EIC_IRQInitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EIC_IRQStructInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct)\r
+{\r
+ EIC_IRQInitStruct->EIC_IRQChannel = 0x1F;\r
+ EIC_IRQInitStruct->EIC_IRQChannelPriority = 0;\r
+ EIC_IRQInitStruct->EIC_IRQChannelCmd = DISABLE;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_FIQStructInit\r
+* Description : Fills each EIC_FIQInitStruct member with its default value.\r
+* Input : EIC_FIQInitStruct: pointer to a EIC_FIQInitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EIC_FIQStructInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct)\r
+{\r
+ EIC_FIQInitStruct->EIC_FIQChannel = 0x03;\r
+ EIC_FIQInitStruct->EIC_FIQChannelCmd = DISABLE;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_IRQCmd\r
+* Description : Enables or disables EIC IRQ output request to CPU.\r
+* Input : NewState: new state of the EIC IRQ output request to CPU.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EIC_IRQCmd(FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Enable EIC IRQ output request to CPU */\r
+ EIC->ICR |= EIC_IRQEnable_Mask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable EIC IRQ output request to CPU */\r
+ EIC->ICR &= EIC_IRQDisable_Mask;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_FIQCmd\r
+* Description : Enables or disables EIC FIQ output request to CPU.\r
+* Input : NewState: new state of the EIC FIQ output request to CPU.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EIC_FIQCmd(FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Enable EIC FIQ output request to CPU */\r
+ EIC->ICR |= EIC_FIQEnable_Mask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable EIC FIQ output request to CPU */\r
+ EIC->ICR &= EIC_FIQDisable_Mask;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_GetCurrentIRQChannel\r
+* Description : Returns the current served IRQ channel identifier.\r
+* Input : None\r
+* Output : None\r
+* Return : The current served IRQ channel.\r
+*******************************************************************************/\r
+u8 EIC_GetCurrentIRQChannel(void)\r
+{\r
+ /* Read and return the CIC[4:0] bits of CICR register */\r
+ return ((u8) (EIC->CICR));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_GetCurrentIRQChannelPriority\r
+* Description : Returns the priority level of the current served IRQ channel.\r
+* Input : None\r
+* Output : None\r
+* Return : The priority level of the current served IRQ channel.\r
+*******************************************************************************/\r
+u8 EIC_GetCurrentIRQChannelPriority(void)\r
+{\r
+ /* Read and return the CIP[3:0] bits of CIPR register */\r
+ return ((u8) (EIC->CIPR));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_CurrentIRQPriorityConfig\r
+* Description : Changes the priority of the current served IRQ channel.\r
+* The new priority value must be higher, or equal, than the\r
+* priority value associated to the interrupt channel currently\r
+* serviced.\r
+* Input : NewPriority: new priority value of the IRQ interrupt routine\r
+* currently serviced.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EIC_CurrentIRQPriorityConfig(u8 NewPriority)\r
+{\r
+ /* Disable EIC IRQ output request to CPU */\r
+ EIC->ICR &= EIC_IRQDisable_Mask;\r
+\r
+ /* Change the current priority */\r
+ EIC->CIPR = NewPriority;\r
+\r
+ /* Enable EIC IRQ output request to CPU */\r
+ EIC->ICR |= EIC_IRQEnable_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_GetCurrentFIQChannel\r
+* Description : Returns the current served FIQ channel identifier.\r
+* Input : None\r
+* Output : None\r
+* Return : The current served FIQ channel.\r
+*******************************************************************************/\r
+u8 EIC_GetCurrentFIQChannel(void)\r
+{\r
+ /* Read and return the FIP[1:0] bits of FIPR register */\r
+ return ((u8) (EIC->FIPR));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EIC_ClearFIQPendingBit\r
+* Description : Clears the pending bit of the selected FIQ Channel.\r
+* Input : EIC_FIQChannel: specifies the FIQ channel to clear its\r
+* pending bit.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EIC_ClearFIQPendingBit(u8 EIC_FIQChannel)\r
+{\r
+ /* Clear the correspondent FIQ pending bit */\r
+ EIC->FIPR = EIC_FIQChannel ;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_extit.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file provides all the EXTIT software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_extit.h"\r
+#include "75x_mrcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTIT_DeInit\r
+* Description : Deinitializes the EXTIT peripheral registers to their default\r
+* reset values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EXTIT_DeInit(void)\r
+{\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_EXTIT,ENABLE);\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_EXTIT,DISABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTIT_Init\r
+* Description : Initializes the EXTIT peripheral according to the specified\r
+* parameters in the EXTIT_InitStruct .\r
+* Input : - EXTIT_InitStruct: pointer to a EXTIT_InitTypeDef structure\r
+* that contains the configuration information for the EXTIT\r
+* peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EXTIT_Init(EXTIT_InitTypeDef* EXTIT_InitStruct)\r
+{\r
+ if(EXTIT_InitStruct->EXTIT_ITLineCmd == ENABLE)\r
+ {\r
+ /* Enable the selected external interrupts */\r
+ EXTIT->MR |= EXTIT_InitStruct->EXTIT_ITLine;\r
+ \r
+ /* Select the trigger for the selected external interrupts */\r
+ if(EXTIT_InitStruct->EXTIT_ITTrigger == EXTIT_ITTrigger_Falling)\r
+ {\r
+ /* Falling edge */\r
+ EXTIT->TSR &= ~EXTIT_InitStruct->EXTIT_ITLine;\r
+ }\r
+ else if (EXTIT_InitStruct->EXTIT_ITTrigger == EXTIT_ITTrigger_Rising)\r
+ {\r
+ /* Rising edge */\r
+ EXTIT->TSR |= EXTIT_InitStruct->EXTIT_ITLine;\r
+ }\r
+ }\r
+ else if(EXTIT_InitStruct->EXTIT_ITLineCmd == DISABLE)\r
+ {\r
+ /* Disable the selected external interrupts */\r
+ EXTIT->MR &= ~EXTIT_InitStruct->EXTIT_ITLine;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTIT_StructInit\r
+* Description : Fills each EXTIT_InitStruct member with its reset value.\r
+* Input : - EXTIT_InitStruct: pointer to a EXTIT_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EXTIT_StructInit(EXTIT_InitTypeDef* EXTIT_InitStruct)\r
+{\r
+ EXTIT_InitStruct->EXTIT_ITLine = EXTIT_ITLineNone;\r
+ EXTIT_InitStruct->EXTIT_ITTrigger = EXTIT_ITTrigger_Falling;\r
+ EXTIT_InitStruct->EXTIT_ITLineCmd = DISABLE;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTIT_GenerateSWInterrupt\r
+* Description : Generates a Software interrupt.\r
+* Input : - EXTIT_ITLine: specifies the EXTIT lines to be enabled or\r
+* disabled. This parameter can be:\r
+* - EXTIT_ITLinex: External interrupt line x where x(0..15)\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EXTIT_GenerateSWInterrupt(u16 EXTIT_ITLine)\r
+{\r
+ EXTIT->SWIR |= EXTIT_ITLine;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTIT_GetFlagStatus\r
+* Description : Checks whether the specified EXTIT line flag is set or not.\r
+* Input : - EXTIT_ITLine: specifies the EXTIT lines flag to check. \r
+* This parameter can be:\r
+* - EXTIT_ITLinex: External interrupt line x where x(0..15)\r
+* Output : None\r
+* Return : The new state of EXTIT_ITLine (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus EXTIT_GetFlagStatus(u16 EXTIT_ITLine)\r
+{\r
+ if((EXTIT->PR & EXTIT_ITLine) != RESET)\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTIT_ClearFlag\r
+* Description : Clears the EXTIT\92s line pending flags.\r
+* Input : - EXTIT_ITLine: specifies the EXTIT lines flags to clear. \r
+* This parameter can be:\r
+* - EXTIT_ITLinex: External interrupt line x where x(0..15)\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EXTIT_ClearFlag(u16 EXTIT_ITLine)\r
+{\r
+ EXTIT->PR = EXTIT_ITLine;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTIT_GetITStatus\r
+* Description : Checks whether the specified EXTIT line is asserted or not.\r
+* Input : - EXTIT_ITLine: specifies the EXTIT lines to check. \r
+* This parameter can be:\r
+* - EXTIT_ITLinex: External interrupt line x where x(0..15)\r
+* Output : None\r
+* Return : The new state of EXTIT_ITLine (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus EXTIT_GetITStatus(u16 EXTIT_ITLine)\r
+{\r
+ if(((EXTIT->PR & EXTIT_ITLine) != RESET)&& ((EXTIT->MR & EXTIT_ITLine) != RESET))\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTIT_ClearITPendingBit\r
+* Description : Clears the EXTIT\92s line pending bits.\r
+* Input : - EXTIT_ITLine: specifies the EXTIT lines to clear. \r
+* This parameter can be:\r
+* - EXTIT_ITLinex: External interrupt line x where x(0..15)\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EXTIT_ClearITPendingBit(u16 EXTIT_ITLine)\r
+{\r
+ EXTIT->PR = EXTIT_ITLine;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_gpio.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file provides all the GPIO software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_gpio.h"\r
+#include "75x_mrcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define GPIO_Remap_Mask 0x1F /* GPIO remapping mask */\r
+#define GPIO_Pin_Mask 0x000FFFFF /* GPIO1 and GPIO2 all pins mask */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_DeInit\r
+* Description : Deinitializes the GPIOx peripheral registers to their default\r
+* reset values.\r
+* The I/O remapping register 0 and 1 are not reset by this function.\r
+* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Reset the GPIOx registers values */\r
+ GPIOx->PC0 = 0xFFFFFFFF;\r
+ GPIOx->PC1 = 0x0;\r
+ GPIOx->PC2 = 0x0;\r
+ GPIOx->PM = 0x0;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_Init\r
+* Description : Initializes the GPIOx peripheral according to the specified\r
+* parameters in the GPIO_InitStruct. This function will not\r
+* change the configuration for a pin if the corresponding mask\r
+* bit is set, except pins configured as input pull-up or pull-down.\r
+* These pins are automatically masked after each configuration.\r
+* Input :- GPIOx: where x can be (0..2) to select the GPIO peripheral.\r
+* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that\r
+* contains the configuration information for the specified GPIO\r
+* peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ /* GPIOx Mode and Pins Set */\r
+ if((GPIOx != GPIO0) && (GPIO_InitStruct->GPIO_Pin == GPIO_Pin_All))\r
+ {\r
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_Mask;\r
+ }\r
+\r
+ switch(GPIO_InitStruct->GPIO_Mode)\r
+ {\r
+ case GPIO_Mode_AIN:\r
+ GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin;\r
+ break;\r
+\r
+ case GPIO_Mode_IN_FLOATING:\r
+ GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin;\r
+ break;\r
+\r
+ case GPIO_Mode_IPD:\r
+ GPIOx->PM &= ~GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PD &= ~GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PM |= GPIO_InitStruct->GPIO_Pin;\r
+ break;\r
+\r
+ case GPIO_Mode_IPU:\r
+ GPIOx->PM &= ~GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PD |= GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PM |= GPIO_InitStruct->GPIO_Pin;\r
+ break;\r
+\r
+ case GPIO_Mode_Out_OD:\r
+ GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin;\r
+ break;\r
+\r
+ case GPIO_Mode_Out_PP:\r
+ GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin;\r
+ break;\r
+\r
+ case GPIO_Mode_AF_OD:\r
+ GPIOx->PD |= GPIO_InitStruct->GPIO_Pin; \r
+ GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin;\r
+ break;\r
+\r
+ case GPIO_Mode_AF_PP:\r
+ GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin;\r
+ break;\r
+\r
+ default :\r
+ GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin;\r
+ GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin;\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_StructInit\r
+* Description : Fills each GPIO_InitStruct member with its default value.\r
+* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ /* Reset GPIO init structure parameters values */\r
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_Read\r
+* Description : Reads the specified GPIO data port.\r
+* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral.\r
+* Output : None\r
+* Return : GPIO data port word value.\r
+*******************************************************************************/\r
+u32 GPIO_Read(GPIO_TypeDef* GPIOx)\r
+{\r
+ return GPIOx->PD;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_ReadBit\r
+* Description : Reads the specified data port bit.\r
+* Input : - GPIOx: where x can be (0..2) to select the GPIO peripheral.\r
+* : - GPIO_Pin: specifies the port bit to read.\r
+* This parameter can be GPIO_Pin_x where x can be (0..31) for\r
+* GPIO0 and x(0..19) for GPIO1 and GPIO2.\r
+* Output : None\r
+* Return : The port pin value\r
+*******************************************************************************/\r
+u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin)\r
+{\r
+ if ((GPIOx->PD & GPIO_Pin) != Bit_RESET)\r
+ {\r
+ return Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ return Bit_RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_Write\r
+* Description : Writes data to the specified GPIO data port.\r
+* Input :- GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral.\r
+* - PortVal: specifies the value to be written to the data port\r
+* register.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, u32 PortVal)\r
+{\r
+ GPIOx->PD = PortVal;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_WriteBit\r
+* Description : Sets or clears the selected data port bit.\r
+* Input : - GPIOx: where x can be (0..2) to select the GPIO peripheral.\r
+* - GPIO_Pin: specifies the port bit to be written.\r
+* This parameter can be GPIO_Pin_x where x can be (0..31) for\r
+* GPIO0 and x(0..19) for GPIO1 and GPIO2.\r
+* - BitVal: specifies the value to be written to the selected bit.\r
+* This parameter must be one of the BitAction enum values:\r
+* - Bit_RESET: to clear the port pin\r
+* - Bit_SET: to set the port pin\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, BitAction BitVal)\r
+{\r
+ if(BitVal != Bit_RESET)\r
+ {\r
+ GPIOx->PD |= GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->PD &= ~GPIO_Pin;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_PinMaskConfig\r
+* Description : Enables or disables write protection to the selected bits in\r
+* the I/O port registers (PxC2, PxC1, PxC0 and PxD).\r
+* Input :- GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral.\r
+* - GPIO_Pin: specifies the port bit to be protected.\r
+* This parameter can be GPIO_Pin_x where x can be (0..31) for\r
+* GPIO0 and x(0..19) for GPIO1 and GPIO2.\r
+* - NewState: new state of the port pin.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_PinMaskConfig(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ GPIOx->PM |= GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->PM &= ~GPIO_Pin;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_GetPortMask\r
+* Description : Gets the GPIOx port mask value.\r
+* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral.\r
+* Output : None\r
+* Return : GPIO port mask value.\r
+*******************************************************************************/\r
+u32 GPIO_GetPortMask(GPIO_TypeDef* GPIOx)\r
+{\r
+ return GPIOx->PM;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_PinRemapConfig\r
+* Description : Changes the mapping of the specified pin.\r
+* Input :- GPIO_Remap: selects the pin to remap.\r
+* This parameter can be one of the following values:\r
+* - GPIO_Remap_SMI_CS3_EN: Enable SMI CS3 \r
+* - GPIO_Remap_SMI_CS2_EN: Enable SMI CS2\r
+* - GPIO_Remap_SMI_CS1_EN: Enable SMI CS1\r
+* - GPIO_Remap_SMI_EN: Enable SMI Alternate Functions: \r
+* SMI_CS0, SMI_CK, SMI_DIN and SMI_DOUT\r
+* - GPIO_Remap_DBGOFF: JTAG Disable\r
+* - GPIO_Remap_UART1: UART1 Alternate Function mapping\r
+* - GPIO_Remap_UART2: UART2 Alternate Function mapping\r
+* - GPIO_Remap_SSP1: SSP1 Alternate Function mapping\r
+* - GPIO_Remap_TIM2: TIM2 Alternate Function mapping\r
+* - GPIO_Remap_TIM0: TIM0 Alternate Function mapping\r
+* - NewState: new state of the port pin.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_PinRemapConfig(u16 GPIO_Remap, FunctionalState NewState)\r
+{\r
+ u32 GPIOReg = 0;\r
+ u32 PinPos = 0;\r
+\r
+ /* Get the GPIO register index */\r
+ GPIOReg = GPIO_Remap >> 5;\r
+\r
+ /* Get the pin position */\r
+ PinPos = GPIO_Remap & GPIO_Remap_Mask;\r
+\r
+ if(GPIOReg == 1) /* The pin to remap is in REMAP0R register */\r
+ {\r
+ if(NewState == ENABLE)\r
+ {\r
+ GPIOREMAP->REMAP0R |= (1 << PinPos);\r
+ }\r
+ else\r
+ {\r
+ GPIOREMAP->REMAP0R &= ~(1 << PinPos);\r
+ }\r
+ }\r
+ else if(GPIOReg == 2) /* The pin to remap is in REMAP1R register */\r
+ {\r
+ if(NewState == ENABLE)\r
+ {\r
+ GPIOREMAP->REMAP1R |= (1 << PinPos);\r
+ }\r
+ else\r
+ {\r
+ GPIOREMAP->REMAP1R &= ~(1 << PinPos);\r
+ }\r
+ }\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_i2c.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006 \r
+* Description : This file provides all the I2C software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, \r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING \r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_i2c.h"\r
+#include "75x_mrcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* I2C IT enable */\r
+#define I2C_IT_Enable 0x01\r
+#define I2C_IT_Disable 0xFE\r
+\r
+/* I2C Peripheral Enable/Disable */\r
+#define I2C_PE_Set 0x20\r
+#define I2C_PE_Reset 0xDF\r
+\r
+/* I2C START Enable/Disable */\r
+#define I2C_Start_Enable 0x08\r
+#define I2C_Start_Disable 0xF7\r
+\r
+/* I2C STOP Enable/Disable */\r
+#define I2C_Stop_Enable 0x02\r
+#define I2C_Stop_Disable 0xFD\r
+\r
+/* Address direction bit */\r
+#define I2C_ADD0_Set 0x01\r
+#define I2C_ADD0_Reset 0xFE\r
+\r
+/* I2C Masks */\r
+#define I2C_Frequency_Mask 0x1F\r
+#define I2C_AddressHigh_Mask 0xF9\r
+#define I2C_OwnAddress_Mask 0x0300 \r
+#define I2C_StandardMode_Mask 0x7f \r
+#define I2C_FastMode_Mask 0x80 \r
+#define I2C_Event_Mask 0x3FFF\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_DeInit \r
+* Description : Deinitializes the I2C peripheral registers to their default\r
+* reset values. \r
+* Input : None \r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void I2C_DeInit(void)\r
+{\r
+ /* Reset the I2C registers values*/\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_I2C,ENABLE);\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_I2C,DISABLE); \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_Init \r
+* Description : Initializes the I2C peripheral according to the specified\r
+* parameters in the I2C_Initstruct.\r
+* Input : - I2C_InitStruct: pointer to a I2C_InitTypeDef structure that\r
+* contains the configuration information for the specified I2C\r
+* peripheral. \r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void I2C_Init(I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+ u8 ITEState = 0;\r
+ u16 Result = 0x0F;\r
+ u32 APBClock = 8000000;\r
+ MRCC_ClocksTypeDef MRCC_ClocksStatus;\r
+\r
+ /* Get APBClock frequency value */\r
+ MRCC_GetClocksStatus(&MRCC_ClocksStatus);\r
+ APBClock = MRCC_ClocksStatus.PCLK_Frequency;\r
+ /* Save ITE bit state */\r
+ ITEState = I2C->CR & 0xFE;\r
+ /* Disable I2C peripheral to set FR[2:0] bits */\r
+ I2C_Cmd(DISABLE);\r
+ /* Clear frequency FR[2:0] bits */\r
+ I2C->OAR2 &= I2C_Frequency_Mask;\r
+ \r
+ /* Set frequency bits depending on APBClock value */\r
+ if (APBClock < 10000000)\r
+ I2C->OAR2 &= 0x1F;\r
+ else if (APBClock < 16670000)\r
+ I2C->OAR2 |= 0x20;\r
+ else if (APBClock < 26670000)\r
+ I2C->OAR2 |= 0x40;\r
+ else if (APBClock < 40000000)\r
+ I2C->OAR2 |= 0x60;\r
+ else if (APBClock < 53330000)\r
+ I2C->OAR2 |= 0x80;\r
+ else if (APBClock < 66000000)\r
+ I2C->OAR2 |= 0xA0;\r
+ else if (APBClock < 80000000)\r
+ I2C->OAR2 |= 0xC0;\r
+ else if (APBClock < 100000000)\r
+ I2C->OAR2 |= 0xE0;\r
+ I2C_Cmd(ENABLE);\r
+ \r
+ /* Restore the ITE bit state */\r
+ I2C->CR |= ITEState;\r
+\r
+ /* Configure general call */\r
+ if (I2C_InitStruct->I2C_GeneralCall == I2C_GeneralCall_Enable)\r
+ {\r
+ /* Enable general call */\r
+ I2C->CR |= I2C_GeneralCall_Enable;\r
+ }\r
+ else\r
+ {\r
+ /* Disable general call */\r
+ I2C->CR &= I2C_GeneralCall_Disable;\r
+ }\r
+ \r
+ /* Configure acknowledgement */\r
+ if (I2C_InitStruct->I2C_Ack == I2C_Ack_Enable)\r
+ {\r
+ /* Enable acknowledgement */\r
+ I2C->CR |= I2C_Ack_Enable;\r
+ }\r
+ else\r
+ {\r
+ /* Disable acknowledgement */\r
+ I2C->CR &= I2C_Ack_Disable;\r
+ }\r
+ \r
+ /* Configure LSB own address */\r
+ I2C->OAR1 = I2C_InitStruct->I2C_OwnAddress;\r
+ /* Clear MSB own address ADD[9:8] bits */\r
+ I2C->OAR2 &= I2C_AddressHigh_Mask;\r
+ /* Set MSB own address value */\r
+ I2C->OAR2 |= (I2C_InitStruct->I2C_OwnAddress & I2C_OwnAddress_Mask)>>7;\r
+\r
+ /* Configure speed in standard mode */\r
+ if (I2C_InitStruct->I2C_CLKSpeed <= 100000)\r
+ {\r
+ /* Standard mode speed calculate */\r
+ Result = ((APBClock/I2C_InitStruct->I2C_CLKSpeed)-7)/2;\r
+ /* Set speed value and clear FM/SM bit for standard mode in LSB clock divider */\r
+ I2C->CCR = Result & I2C_StandardMode_Mask;\r
+ }\r
+ /* Configure speed in fast mode */\r
+ else if (I2C_InitStruct->I2C_CLKSpeed <= 400000)\r
+ {\r
+ /* Fast mode speed calculate */\r
+ Result = ((APBClock/I2C_InitStruct->I2C_CLKSpeed)-9)/3;\r
+ /* Set speed value and set FM/SM bit for fast mode in LSB clock divider */\r
+ I2C->CCR = Result | I2C_FastMode_Mask;\r
+ }\r
+ /* Set speed in MSB clock divider */\r
+ I2C->ECCR = Result >>7;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_StructInit \r
+* Description : Fills each I2C_InitStruct member with its default value.\r
+* Input : - I2C_InitStruct: pointer to an I2C_InitTypeDef structure\r
+ which will be initialized. \r
+* Output : None \r
+* Return : None. \r
+*******************************************************************************/\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+ /* Initialize the I2C_CLKSpeed member */\r
+ I2C_InitStruct->I2C_CLKSpeed = 5000;\r
+ \r
+ /* Initialize the I2C_OwnAddress member */\r
+ I2C_InitStruct->I2C_OwnAddress = 0x0;\r
+ \r
+ /* Initialize the I2C_GeneralCall member */\r
+ I2C_InitStruct->I2C_GeneralCall = I2C_GeneralCall_Disable;\r
+ \r
+ /* Initialize the I2C_Ack member */\r
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_Cmd \r
+* Description : Enables or disables the I2C peripheral. \r
+* Input : - NewState: new state of the I2C peripheral. This parameter\r
+* can be: ENABLE or DISABLE.\r
+* Output : None \r
+* Return : None. \r
+*******************************************************************************/\r
+void I2C_Cmd(FunctionalState NewState)\r
+{\r
+ if (NewState == ENABLE)\r
+ {\r
+ /* Enable the I2C peripheral by setting twice the PE bit on the CR register */\r
+ I2C->CR |= I2C_PE_Set;\r
+ I2C->CR |= I2C_PE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the I2C peripheral */\r
+ I2C->CR &= I2C_PE_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GenerateSTART \r
+* Description : Generates I2C communication START condition. \r
+* Input : - NewState: new state of the I2C START condition generation.\r
+* This parameter can be: ENABLE or DISABLE. \r
+* Output : None\r
+* Return : None. \r
+*******************************************************************************/\r
+void I2C_GenerateSTART(FunctionalState NewState)\r
+{\r
+ if (NewState == ENABLE)\r
+ {\r
+ /* Generate a START condition */\r
+ I2C->CR |= I2C_Start_Enable;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the START condition generation */\r
+ I2C->CR &= I2C_Start_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GenerateSTOP \r
+* Description : Generates I2C communication STOP condition. \r
+* Input : - NewState: new state of the I2C STOP condition generation.\r
+* This parameter can be: ENABLE or DISABLE. \r
+* Output : None \r
+* Return : None. \r
+*******************************************************************************/\r
+void I2C_GenerateSTOP(FunctionalState NewState)\r
+{\r
+ if (NewState == ENABLE)\r
+ {\r
+ /* Generate a SIOP condition */\r
+ I2C->CR |= I2C_Stop_Enable;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the STOP condition generation */\r
+ I2C->CR &= I2C_Stop_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_AcknowledgeConfig \r
+* Description : Enables or disables I2C acknowledge feature. \r
+* Input : - NewState: new state of the I2C Acknowledgement. \r
+* This parameter can be: ENABLE or DISABLE. \r
+* Output : None \r
+* Return : None. \r
+*******************************************************************************/\r
+void I2C_AcknowledgeConfig(FunctionalState NewState)\r
+{\r
+ if (NewState == ENABLE)\r
+ {\r
+ /* Enable the acknowledgement */\r
+ I2C->CR |= I2C_Ack_Enable;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the acknowledgement */\r
+ I2C->CR &= I2C_Ack_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ITConfig \r
+* Description : Enables or disables the I2C interrupt. \r
+* Input : - NewState: new state of the I2C interrupt.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None \r
+* Return : None. \r
+*******************************************************************************/\r
+void I2C_ITConfig(FunctionalState NewState)\r
+{\r
+ if (NewState == ENABLE)\r
+ {\r
+ /* Enable the I2C interrupt */\r
+ I2C->CR |= I2C_IT_Enable;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the I2C interrupt */\r
+ I2C->CR &= I2C_IT_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GetLastEvent \r
+* Description : Gets the last I2C event that has occurred. \r
+* Input : None \r
+* Output : None \r
+* Return : The Last happened Event. \r
+*******************************************************************************/\r
+u16 I2C_GetLastEvent(void)\r
+{\r
+ u16 Flag1 = 0, Flag2 = 0, LastEvent = 0;\r
+\r
+ Flag1 = I2C->SR1;\r
+ Flag2 = I2C->SR2;\r
+ Flag2 = Flag2<<8;\r
+ /* Get the last event value from I2C status register */\r
+ LastEvent = (((Flag1 | (Flag2)) & I2C_Event_Mask));\r
+ /* Return the last event */\r
+ return LastEvent;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_CheckEvent \r
+* Description : Checks whether the Last I2C Event is equal to the one passed \r
+* as parameter. \r
+* Input : - I2C_EVENT: specifies the event to be checked. This parameter\r
+* can be one of the following values:\r
+* - I2C_EVENT_SLAVE_ADDRESS_MATCHED\r
+* - I2C_EVENT_SLAVE_BYTE_RECEIVED\r
+* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED\r
+* - I2C_EVENT_SLAVE_ACK_FAILURE \r
+* - I2C_EVENT_MASTER_MODE_SELECT\r
+* - I2C_EVENT_MASTER_MODE_SELECTED\r
+* - I2C_EVENT_MASTER_BYTE_RECEIVED\r
+* - I2C_EVENT_MASTER_BYTE_TRANSMITTED\r
+* - I2C_EVENT_MASTER_MODE_ADDRESS10\r
+* - I2C_EVENT_SLAVE_STOP_DETECTED\r
+* Output : None \r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Last event is equal to the I2C_Event\r
+* - ERROR: Last event is different from the I2C_Event \r
+*******************************************************************************/\r
+ErrorStatus I2C_CheckEvent(u16 I2C_EVENT)\r
+{\r
+ u16 LastEvent = I2C_GetLastEvent();\r
+\r
+ /* Check whether the last event is equal to I2C_EVENT */\r
+ if (LastEvent == I2C_EVENT)\r
+ {\r
+ /* Return SUCCESS when last event is equal to I2C_EVENT */\r
+ return SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ /* Return ERROR when last event is different from I2C_EVENT */\r
+ return ERROR;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_SendData \r
+* Description : Sends a data byte. \r
+* Input : - Data: indicates the byte to be transmitted.\r
+* Output : None \r
+* Return : None. \r
+*******************************************************************************/\r
+void I2C_SendData(u8 Data)\r
+{\r
+ /* Write in the DR register the byte to be sent */\r
+ I2C->DR = Data;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ReceiveData \r
+* Description : Reads the received byte. \r
+* Input : None \r
+* Output : None \r
+* Return : The received byte \r
+*******************************************************************************/\r
+u8 I2C_ReceiveData(void)\r
+{\r
+ /* Return from the DR register the received byte */\r
+ return I2C->DR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_Send7bitAddress \r
+* Description : Transmits the address byte to select the slave device. \r
+* Input : - Address: specifies the slave address which will be transmitted \r
+* - Direction: specifies whether the I2C device will be a \r
+* Transmitter or a Receiver. This parameter can be one of the \r
+* following values\r
+* - I2C_MODE_TRANSMITTER: Transmitter mode\r
+* - I2C_MODE_RECEIVER: Receiver mode \r
+* Output : None \r
+* Return : None. \r
+*******************************************************************************/\r
+void I2C_Send7bitAddress(u8 Address, u8 Direction)\r
+{\r
+ /* Test on the direction to define the read/write bit */\r
+ if (Direction == I2C_MODE_RECEIVER)\r
+ {\r
+ /* Set the address bit0 for read */\r
+ Address |= I2C_ADD0_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the address bit0 for write */\r
+ Address &= I2C_ADD0_Reset;\r
+ }\r
+ /* Send the address */\r
+ I2C->DR = Address;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ReadRegister \r
+* Description : Reads the specified I2C register and returns its value. \r
+* Input1 : - I2C_Register: specifies the register to read.\r
+* This parameter can be one of the following values: \r
+* - I2C_CR: CR register. \r
+* - I2C_SR1: SR1 register.\r
+* - I2C_SR2: SR2 register.\r
+* - I2C_CCR: CCR register.\r
+* - I2C_OAR1: OAR1 register.\r
+* - I2C_OAR2: OAR2 register.\r
+* - I2C_DR: DR register.\r
+* - I2C_ECCR: ECCR register.\r
+* Output : None\r
+* Return : The value of the read register. \r
+*******************************************************************************/\r
+u8 I2C_ReadRegister(u8 I2C_Register)\r
+{\r
+ /* Return the selected register value */\r
+ return (*(u8 *)(I2C_BASE + I2C_Register));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GetFlagStatus \r
+* Description : Checks whether the specified I2C flag is set or not.\r
+* Input : - I2C_FLAG: specifies the flag to check. \r
+* This parameter can be one of the following values:\r
+* - I2C_FLAG_SB: Start bit flag (Master mode) \r
+* - I2C_FLAG_M_SL: Master/Slave flag \r
+* - I2C_FLAG_ADSL: Address matched flag (Slave mode) \r
+* - I2C_FLAG_BTF: Byte transfer finished flag \r
+* - I2C_FLAG_BUSY: Bus busy flag \r
+* - I2C_FLAG_TRA: Transmitter/Receiver flag \r
+* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag \r
+* - I2C_FLAG_EVF: Event flag \r
+* - I2C_FLAG_GCAL: General call flag (slave mode) \r
+* - I2C_FLAG_BERR: Bus error flag \r
+* - I2C_FLAG_ARLO: Arbitration lost flag \r
+* - I2C_FLAG_STOPF: Stop detection flag (slave mode) \r
+* - I2C_FLAG_AF: Acknowledge failure flag \r
+* - I2C_FLAG_ENDAD: End of address transmission flag \r
+* - I2C_FLAG_ACK: Acknowledge enable flag \r
+* Output : None \r
+* Return : The NewState of the I2C_FLAG (SET or RESET). \r
+*******************************************************************************/\r
+FlagStatus I2C_GetFlagStatus(u16 I2C_FLAG)\r
+{ \r
+ u16 Flag1 = 0, Flag2 = 0, Flag3 = 0, Tmp = 0;\r
+\r
+ Flag1 = I2C->SR1;\r
+ Flag2 = I2C->SR2;\r
+ Flag2 = Flag2<<8;\r
+ Flag3 = I2C->CR & 0x04;\r
+ \r
+ /* Get all the I2C flags in a unique register*/\r
+ Tmp = (((Flag1 | (Flag2)) & I2C_Event_Mask) | (Flag3<<12)); \r
+ \r
+ /* Check the status of the specified I2C flag */\r
+ if((Tmp & I2C_FLAG) != RESET)\r
+ {\r
+ /* Return SET if I2C_FLAG is set */\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ /* Return RESET if I2C_FLAG is reset */\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ClearFlag \r
+* Description : Clears the I2C\92s pending flags \r
+* Input : - I2C_FLAG: specifies the flag to clear. \r
+* This parameter can be one of the following values:\r
+* - I2C_FLAG_SB: Start bit flag \r
+* - I2C_FLAG_M_SL: Master/Slave flag \r
+* - I2C_FLAG_ADSL: Adress matched flag \r
+* - I2C_FLAG_BTF: Byte transfer finished flag \r
+* - I2C_FLAG_BUSY: Bus busy flag \r
+* - I2C_FLAG_TRA: Transmitter/Receiver flag \r
+* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag \r
+* - I2C_FLAG_EVF: Event flag \r
+* - I2C_FLAG_GCAL: General call flag \r
+* - I2C_FLAG_BERR: Bus error flag \r
+* - I2C_FLAG_ARLO: Arbitration lost flag \r
+* - I2C_FLAG_STOPF: Stop detection flag \r
+* - I2C_FLAG_AF: Acknowledge failure flag \r
+* - I2C_FLAG_ENDAD: End of address transmission flag \r
+* - I2C_FLAG_ACK: Acknowledge enable flag \r
+* - parameter needed in the case that the flag to be cleared\r
+* need a write in one register \r
+* Output : None \r
+* Return : None \r
+*******************************************************************************/\r
+void I2C_ClearFlag(u16 I2C_FLAG, ...)\r
+{\r
+ u8 Tmp = (u8)*((u32 *) & I2C_FLAG + sizeof(I2C_FLAG));\r
+\r
+ /* flags that need a read of the SR2 register to be cleared */\r
+ if ((I2C_FLAG == I2C_FLAG_ADD10) || (I2C_FLAG == I2C_FLAG_EVF) ||\r
+ (I2C_FLAG == I2C_FLAG_STOPF) || (I2C_FLAG == I2C_FLAG_AF) || \r
+ (I2C_FLAG == I2C_FLAG_BERR) || (I2C_FLAG == I2C_FLAG_ARLO) ||\r
+ (I2C_FLAG == I2C_FLAG_ENDAD))\r
+ {\r
+ /* Read the SR2 register */\r
+ (void)I2C->SR2;\r
+\r
+ /* Two flags need a second step to be cleared */\r
+ switch (I2C_FLAG)\r
+ {\r
+ case I2C_FLAG_ADD10:\r
+ /* Send the MSB 10bit address passed as second parameter */\r
+ I2C->DR = Tmp; \r
+ break;\r
+ case I2C_FLAG_ENDAD: \r
+ /* Write to the I2C_CR register by setting PE bit */\r
+ I2C->CR |= I2C_PE_Set;\r
+ break;\r
+ }\r
+ }\r
+ /* flags that need a read of the SR1 register to be cleared */\r
+ else if (I2C_FLAG==I2C_FLAG_SB || I2C_FLAG==I2C_FLAG_ADSL || I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA)\r
+ {\r
+ /* Read the SR1 register */\r
+ (void)I2C->SR1;\r
+\r
+ /* three flags need a second step to be cleared */\r
+ if (I2C_FLAG == I2C_FLAG_SB)\r
+ {\r
+ /* Send the address byte passed as second parameter */\r
+ I2C->DR=Tmp;\r
+ }\r
+ else if (I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA)\r
+ {\r
+ /* return the received byte in the variable passed as second parameter */\r
+ Tmp=I2C->DR;\r
+ }\r
+ }\r
+ /* flags that need to disable the I2C interface */\r
+ else if ( I2C_FLAG==I2C_FLAG_M_SL || I2C_FLAG==I2C_FLAG_GCAL)\r
+ {\r
+ I2C_Cmd(DISABLE);\r
+ I2C_Cmd(ENABLE);\r
+ }\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_it.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : Main Interrupt Service Routines.\r
+* This file can be used to describe all the exceptions\r
+* subroutines that may occur within user application.\r
+* When an interrupt happens, the software will branch\r
+* automatically to the corresponding routine according\r
+* to the interrupt vector loaded in the PC register.\r
+* The following routines are all empty, user can write code\r
+* for exceptions handlers and peripherals IRQ interrupts.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : Undefined_Handler\r
+* Description : This function handles Undefined instruction exception.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void Undefined_Handler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : FIQ_Handler\r
+* Description : This function handles FIQ exception.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void FIQ_Handler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SWI_Handler\r
+* Description : This function handles SW exception.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SWI_Handler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : Prefetch_Handler\r
+* Description : This function handles preftetch abort exception.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void Prefetch_Handler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : Abort_Handler\r
+* Description : This function handles data abort exception.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void Abort_Handler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WAKUP_IRQHandler\r
+* Description : This function handles External line 15(WAKUP) interrupt\r
+* request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void WAKUP_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM2_OC2_IRQHandler\r
+* Description : This function handles TIM2 Output Compare 2 interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM2_OC2_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM2_OC1_IRQHandler\r
+* Description : This function handles TIM2 Output Compare 1 interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM2_OC1_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM2_IC12_IRQHandler\r
+* Description : This function handles TIM2 Input Capture 1 & 2 interrupt\r
+* request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM2_IC12_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM2_UP_IRQHandler\r
+* Description : This function handles TIM2 Update interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM2_UP_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC2_IRQHandler\r
+* Description : This function handles TIM1 Output Compare 2 interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC2_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC1_IRQHandler\r
+* Description : This function handles TIM1 Output Compare 1 interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC1_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_IC12_IRQHandler\r
+* Description : This function handles TIM1 Input Capture 1 & 2 interrupt\r
+* request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_IC12_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_UP_IRQHandler\r
+* Description : This function handles TIM1 Update interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_UP_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM0_OC2_IRQHandler\r
+* Description : This function handles TIM0 Output Compare 2 interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM0_OC2_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM0_OC1_IRQHandler\r
+* Description : This function handles TIM0 Output Compare 1 interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM0_OC1_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM0_IC12_IRQHandler\r
+* Description : This function handles TIM0 Input Capture 1 & 2 interrupt\r
+* request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM0_IC12_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM0_UP_IRQHandler\r
+* Description : This function handles TIM0 Update interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM0_UP_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_OC123_IRQHandler\r
+* Description : This function handles PWM Output Compare 1,2&3 interrupt\r
+* request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_OC123_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_EM_IRQHandler\r
+* Description : This function handles PWM Emergency interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_EM_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_UP_IRQHandler\r
+* Description : This function handles PWM Update interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_UP_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_IRQHandler\r
+* Description : This function handles I2C global interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP1_IRQHandler\r
+* Description : This function handles SSP1 interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SSP1_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP0_IRQHandler\r
+* Description : This function handles SSP0 interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SSP0_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART2_IRQHandler\r
+* Description : This function handles UART2 global interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART2_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART1_IRQHandler\r
+* Description : This function handles UART1 global interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART1_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART0_IRQHandler\r
+* Description : This function handles UART0 global interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART0_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_IRQHandler\r
+* Description : This function handles CAN global interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void CAN_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USBLP_IRQHandler\r
+* Description : This function handles USB Low Priority event interrupt\r
+* request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USB_LP_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USBHP_IRQHandler\r
+* Description : This function handles USB High Priority event interrupt\r
+* request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USB_HP_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_IRQHandler\r
+* Description : This function handles ADC global interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_IRQHandler\r
+* Description : This function handles DMA global interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void DMA_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTIT_IRQHandler\r
+* Description : This function handles External lines 14 to 1 interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EXTIT_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_IRQHandler\r
+* Description : This function handles MRCC interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : FLASHSMI_IRQHandler\r
+* Description : This function handles Flash and SMI global interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void FLASHSMI_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_IRQHandler\r
+* Description : This function handles RTC global interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_IRQHandler(void)\r
+{\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_IRQHandler\r
+* Description : This function handles TB global interrupt request.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TB_IRQHandler(void)\r
+{\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_lib.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file provides all peripherals pointers initialization.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+#define EXT\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_lib.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+#ifdef DEBUG\r
+\r
+/*******************************************************************************\r
+* Function Name : debug\r
+* Description : This function initialize peripherals pointers.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void debug(void)\r
+{\r
+/************************************* SMI ************************************/\r
+#ifdef _SMI\r
+ SMI = (SMI_TypeDef *) SMIR_BASE;\r
+#endif /*_SMI */\r
+\r
+/************************************* CFG ************************************/\r
+#ifdef _CFG\r
+ CFG = (CFG_TypeDef *) CFG_BASE;\r
+#endif /*_CFG */\r
+\r
+/************************************* MRCC ***********************************/\r
+#ifdef _MRCC\r
+ MRCC = (MRCC_TypeDef *) MRCC_BASE;\r
+#endif /*_MRCC */\r
+\r
+/************************************* ADC ************************************/ \r
+#ifdef _ADC\r
+ ADC = (ADC_TypeDef *) ADC_BASE;\r
+#endif /*_ADC */\r
+\r
+/************************************* TB *************************************/\r
+#ifdef _TB\r
+ TB = (TB_TypeDef *) TB_BASE;\r
+#endif /*_TB */\r
+\r
+/************************************* TIM ************************************/\r
+#ifdef _TIM0\r
+ TIM0 = (TIM_TypeDef *) TIM0_BASE;\r
+#endif /*_TIM0 */\r
+\r
+#ifdef _TIM1\r
+ TIM1 = (TIM_TypeDef *) TIM1_BASE;\r
+#endif /*_TIM1 */\r
+\r
+#ifdef _TIM2\r
+ TIM2 = (TIM_TypeDef *) TIM2_BASE;\r
+#endif /*_TIM2 */\r
+\r
+/************************************* PWM ************************************/\r
+#ifdef _PWM\r
+ PWM = (PWM_TypeDef *) PWM_BASE;\r
+#endif /*_PWM */\r
+\r
+/************************************* WDG ************************************/\r
+#ifdef _WDG\r
+ WDG = (WDG_TypeDef *) WDG_BASE;\r
+#endif /*_WDG */\r
+\r
+/************************************* SSP ************************************/\r
+#ifdef _SSP0\r
+ SSP0 = (SSP_TypeDef *) SSP0_BASE;\r
+#endif /*_SSP0 */\r
+\r
+#ifdef _SSP1\r
+ SSP1 = (SSP_TypeDef *) SSP1_BASE;\r
+#endif /*_SSP1 */\r
+\r
+/************************************* CAN ************************************/\r
+#ifdef _CAN\r
+ CAN = (CAN_TypeDef *) CAN_BASE;\r
+#endif /*_CAN */\r
+\r
+/************************************* I2C ************************************/\r
+#ifdef _I2C\r
+ I2C = (I2C_TypeDef *) I2C_BASE;\r
+#endif /*_I2C */\r
+\r
+/************************************* UART ***********************************/\r
+#ifdef _UART0\r
+ UART0 = (UART_TypeDef *) UART0_BASE;\r
+#endif /*_UART0 */\r
+\r
+#ifdef _UART1\r
+ UART1 = (UART_TypeDef *) UART1_BASE;\r
+#endif /*_UART1 */\r
+\r
+#ifdef _UART2\r
+ UART2 = (UART_TypeDef *) UART2_BASE;\r
+#endif /*_UART2 */\r
+\r
+/************************************* GPIO ***********************************/\r
+#ifdef _GPIO0\r
+ GPIO0 = (GPIO_TypeDef *) GPIO0_BASE;\r
+#endif /*_GPIO0 */\r
+\r
+#ifdef _GPIO1\r
+ GPIO1 = (GPIO_TypeDef *) GPIO1_BASE;\r
+#endif /*_GPIO1 */\r
+\r
+#ifdef _GPIO2\r
+ GPIO2 = (GPIO_TypeDef *) GPIO2_BASE;\r
+#endif /*_GPIO2 */\r
+\r
+#ifdef _GPIOREMAP\r
+ GPIOREMAP = (GPIOREMAP_TypeDef *) GPIOREMAP_BASE;\r
+#endif /*_GPIOREMAP */\r
+\r
+/************************************* DMA ************************************/\r
+#ifdef _DMA\r
+ DMA = (DMA_TypeDef *) DMA_BASE;\r
+#endif /*_DMA */\r
+\r
+#ifdef _DMA_Stream0\r
+ DMA_Stream0 = (DMA_Stream_TypeDef *) DMA_Stream0_BASE;\r
+#endif /*_DMA_Stream0 */\r
+\r
+#ifdef _DMA_Stream1 \r
+ DMA_Stream1 = (DMA_Stream_TypeDef *) DMA_Stream1_BASE;\r
+#endif /*_DMA_Stream1 */ \r
+ \r
+#ifdef _DMA_Stream2\r
+ DMA_Stream2 = (DMA_Stream_TypeDef *) DMA_Stream2_BASE;\r
+#endif /*_DMA_Stream2 */ \r
+\r
+#ifdef _DMA_Stream3\r
+ DMA_Stream3 = (DMA_Stream_TypeDef *) DMA_Stream3_BASE;\r
+#endif /*_DMA_Stream3 */\r
+\r
+/************************************* RTC ************************************/\r
+#ifdef _RTC\r
+ RTC = (RTC_TypeDef *) RTC_BASE;\r
+#endif /*_RTC */\r
+\r
+/************************************* EXTIT **********************************/\r
+#ifdef _EXTIT\r
+ EXTIT = (EXTIT_TypeDef *) EXTIT_BASE;\r
+#endif /*_EXTIT */\r
+\r
+/************************************* EIC ************************************/\r
+#ifdef _EIC\r
+ EIC = (EIC_TypeDef *) EIC_BASE;\r
+#endif /*_EIC */\r
+\r
+}\r
+\r
+#endif\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_mrcc.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file provides all the MRCC software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_mrcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define MRCC_FLAG_Mask 0x1F /* MRCC Flag Mask */\r
+\r
+/* MRCC_PWRCTRL mask bits */\r
+#define MRCC_LP_Set_Mask 0x00000001\r
+#define MRCC_LP_Reset_Mask 0xFFFFFFFE\r
+#define MRCC_SWRESET_Mask 0x00000002\r
+#define MRCC_WFI_Mask 0x00000004\r
+#define MRCC_STANDBY_Mask 0x00000006\r
+#define MRCC_LPMC_Reset_Mask 0xFFFFFFF9\r
+#define MRCC_LPDONE_Reset_Mask 0xFFFFFF7F\r
+#define MRCC_LPPARAM_Reset_Mask 0xFFFF1FFF\r
+#define MRCC_WFIParam_Reset_Mask 0xFFFF1FEF\r
+#define MRCC_CKRTCSEL_Set_Mask 0x03000000\r
+#define MRCC_CKRTCSEL_Reset_Mask 0xFCFFFFFF\r
+#define MRCC_CKRTCOK_Mask 0x08000000\r
+#define MRCC_LPOSCEN_Mask 0x10000000\r
+#define MRCC_OSC32KEN_Mask 0x20000000\r
+ \r
+/* MRCC_CLKCTL mask bits */\r
+#define MRCC_PPRESC_Set_Mask 0x00000003\r
+#define MRCC_PPRESC_Reset_Mask 0xFFFFFFFC\r
+#define MRCC_PPRESC2_Mask 0x00000004\r
+#define MRCC_HPRESC_Set_Mask 0x00000018\r
+#define MRCC_HPRESC_Reset_Mask 0xFFFFFFE7\r
+#define MRCC_MCOS_Reset_Mask 0xFFFFFF3F\r
+#define MRCC_XTDIV2_Set_Mask 0x00008000\r
+#define MRCC_XTDIV2_Reset_Mask 0xFFFF7FFF\r
+#define MRCC_OSC4MBYP_Set_Mask 0x00010000\r
+#define MRCC_OSC4MBYP_Reset_Mask 0xFFFEFFFF\r
+#define MRCC_OSC4MOFF_Set_Mask 0x00020000 \r
+#define MRCC_OSC4MOFF_Reset_Mask 0xFFFDFFFF\r
+#define MRCC_NCKDF_Set_Mask 0x00040000\r
+#define MRCC_NCKDF_Reset_Mask 0xFFFBFFFF\r
+#define MRCC_CKOSCSEL_Set_Mask 0x00200000\r
+#define MRCC_CKOSCSEL_Reset_Mask 0xFFDFFFFF\r
+#define MRCC_CKUSBSEL_Mask 0x00400000\r
+#define MRCC_CKSEL_Set_Mask 0x00800000\r
+#define MRCC_CKSEL_Reset_Mask 0xFF7FFFFF\r
+#define MRCC_CKSEL_CKOSCSEL_Mask 0x00A00000\r
+#define MRCC_PLLEN_Set_Mask 0x01000000\r
+#define MRCC_PLLEN_Reset_Mask 0xFEFFFFFF\r
+#define MRCC_PLL2EN_Set_Mask 0x02000000\r
+#define MRCC_PLL2EN_Reset_Mask 0xFDFFFFFF\r
+#define MRCC_MX_Set_Mask 0x18000000\r
+#define MRCC_MX_Reset_Mask 0xE7FFFFFF\r
+#define MRCC_LOCK_Mask 0x80000000\r
+#define MRCC_PLLEN_LOCK_Mask 0x81000000\r
+\r
+/* Typical Value of the OSC4M in Hz */\r
+#define OSC4M_Value 4000000 \r
+\r
+/* Typical Value of the OSC4M divided by 128 (used to clock the RTC) in Hz */\r
+#define OSC4M_Div128_Value 31250\r
+ \r
+/* Typical Value of the OS32K Oscillator Frequency in Hz */\r
+#define OSC32K_Value 32768 \r
+\r
+/* Typical Reset Value of the Internal LPOSC Oscillator Frequency in Hz */\r
+#define LPOSC_Value 245000 \r
+\r
+/* Typical Reset Value of the Internal FREEOSC Oscillator Frequency in Hz */\r
+#define FREEOSC_Value 5000000 \r
+\r
+/* Time out for OSC4M start up */\r
+#define OSC4MStartUp_TimeOut 0xFE\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static ErrorStatus SetCKSYS_FREEOSC(void);\r
+static ErrorStatus SetCKSYS_OSC4M(u32 PLL_State);\r
+static ErrorStatus SetCKSYS_OSC4MPLL(u32 PLL_Mul);\r
+static ErrorStatus SetCKSYS_RTC(u32 PLL_State);\r
+static void WriteLPBit(void);\r
+static void WriteCKOSCSELBit(void);\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_DeInit\r
+* Description : Deinitializes the MRCC peripheral registers to their default\r
+* reset values. \r
+* - Depending on the system clock state, some bits in MRCC_CLKCTL\r
+* register can\92t be reset.\r
+* - The OSC32K, LPOSC and RTC clock selection configuration \r
+* bits in MRCC_PWRCTRL register are not cleared by this \r
+* function. To reset those bits, use the dedicated functions \r
+* available within this driver.\r
+* - The MRCC_RFSR, MRCC_BKP0 and MRCC_BKP1 registers are not\r
+* reset by this function.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_DeInit(void)\r
+{\r
+ /* Try to clear NCKDF bit */\r
+ MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask;\r
+\r
+ if((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET)\r
+ {/* No clock detected on OSC4M */\r
+\r
+ /* Reset LOCKIE, LOCKIF, CKUSBSEL, NCKDIE, OSC4MOFF, OSC4MBYP, MCOS[1:0], \r
+ MCOP, HPRESC[1:0], PPRES[2:0] bits */\r
+ MRCC->CLKCTL &= 0x9FB40000;\r
+ \r
+ if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)\r
+ { \r
+ /* Clear CKOSCSEL bit --------------------------------------------------*/ \r
+ /* Execute CKOSCSEL bit writing sequence */\r
+ WriteCKOSCSELBit();\r
+ }\r
+ }\r
+ else\r
+ {/* Clock present on OSC4M */\r
+\r
+ if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)\r
+ { \r
+ /* Reset CKSEL bit */\r
+ MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;\r
+\r
+ /* Clear CKOSCSEL bit --------------------------------------------------*/\r
+ /* Execute CKOSCSEL bit writing sequence */\r
+ WriteCKOSCSELBit();\r
+ }\r
+\r
+ if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET)\r
+ {\r
+ /* Set CKSEL bit */\r
+ MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; \r
+ }\r
+\r
+ /* Disable PLL */\r
+ MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask;\r
+\r
+ /* Reset LOCKIE, LOCKIF, MX[1:0], CKUSBSEL, NCKDIE, MCOS[1:0], MCOP,\r
+ HPRESC[1:0], PPRES[2:0] bits */\r
+ MRCC->CLKCTL &= 0x87B70000;\r
+\r
+ /* Reset CKSEL bit */\r
+ MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;\r
+\r
+ /* Reset OSC4MOFF and OSC4MBYP bits */\r
+ MRCC->CLKCTL &= 0xFFFCFFFF; \r
+ }\r
+\r
+ /* Reset RTCM, EN33V, LP_PARAM[15:13], WFI_FLASH_EN, LPMC_DBG and LPMC[1:0] bits */\r
+ MRCC->PWRCTRL &= 0xFBFE1FE1;\r
+ \r
+ /* Reset PCLKEN register bits */\r
+ MRCC->PCLKEN = 0x00;\r
+ \r
+ /* Reset PSWRES register bits */\r
+ MRCC->PSWRES = 0x00; \r
+\r
+ /* Clear NCKDF bit */\r
+ MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask; \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_XTDIV2Config\r
+* Description : Enables or disables the oscillator divider by 2. This function\r
+* must not be used when the PLL is enabled.\r
+* Input : - MRCC_XTDIV2: specifies the new state of the oscillator \r
+* divider by 2.\r
+* This parameter can be one of the following values:\r
+* - MRCC_XTDIV2_Disable: oscillator divider by 2 disbaled\r
+* - MRCC_XTDIV2_Enable: oscillator divider by 2 enbaled\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_XTDIV2Config(u32 MRCC_XTDIV2)\r
+{\r
+ if(MRCC_XTDIV2 == MRCC_XTDIV2_Enable)\r
+ {\r
+ MRCC->CLKCTL |= MRCC_XTDIV2_Enable;\r
+ }\r
+ else\r
+ {\r
+ MRCC->CLKCTL &= MRCC_XTDIV2_Disable;\r
+ } \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_CKSYSConfig\r
+* Description : Configures the system clock (CK_SYS).\r
+* Input : - MRCC_CKSYS: specifies the clock source used as system clock.\r
+* This parameter can be one of the following values:\r
+* - MRCC_CKSYS_FREEOSC\r
+* - MRCC_CKSYS_OSC4M\r
+* - MRCC_CKSYS_OSC4MPLL\r
+* - MRCC_CKSYS_RTC (RTC clock source must be previously\r
+* configured using MRCC_CKRTCConfig() function)\r
+* : - MRCC_PLL: specifies the PLL configuration.\r
+* This parameter can be one of the following values:\r
+* - MRCC_PLL_Disabled: PLL disabled\r
+* - MRCC_PLL_NoChange: No change on PLL configuration\r
+* - MRCC_PLL_Mul_12: Multiplication by 12\r
+* - MRCC_PLL_Mul_14: Multiplication by 14\r
+* - MRCC_PLL_Mul_15: Multiplication by 15\r
+* - MRCC_PLL_Mul_16: Multiplication by 16\r
+* Output : None\r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Clock configuration succeeded\r
+* - ERROR: Clock configuration failed\r
+*******************************************************************************/\r
+ErrorStatus MRCC_CKSYSConfig(u32 MRCC_CKSYS, u32 MRCC_PLL)\r
+{\r
+ ErrorStatus Status = ERROR;\r
+\r
+ switch(MRCC_CKSYS)\r
+ {\r
+ case MRCC_CKSYS_FREEOSC:\r
+ if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange))\r
+ {\r
+ Status = SetCKSYS_FREEOSC();\r
+ }\r
+ break;\r
+\r
+ case MRCC_CKSYS_OSC4M:\r
+ if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange))\r
+ {\r
+ Status = SetCKSYS_OSC4M(MRCC_PLL);\r
+ }\r
+ break;\r
+\r
+ case MRCC_CKSYS_OSC4MPLL:\r
+ if((MRCC_PLL == MRCC_PLL_Mul_12) || (MRCC_PLL == MRCC_PLL_Mul_14) ||\r
+ (MRCC_PLL == MRCC_PLL_Mul_15) || (MRCC_PLL == MRCC_PLL_Mul_16))\r
+ {\r
+ Status = SetCKSYS_OSC4MPLL(MRCC_PLL);\r
+ }\r
+ break;\r
+\r
+ case MRCC_CKSYS_RTC:\r
+ if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange))\r
+ { \r
+ Status = SetCKSYS_RTC(MRCC_PLL);\r
+ }\r
+ break;\r
+\r
+ default:\r
+ Status = ERROR;\r
+ break;\r
+ }\r
+ return Status;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_HCLKConfig\r
+* Description : Configures the AHB clock (HCLK).\r
+* Input : - MRCC_HCLK: defines the AHB clock. This clock is derived\r
+* from the system clock(CK_SYS).\r
+* This parameter can be one of the following values:\r
+* - MRCC_CKSYS_Div1: AHB clock = CK_SYS\r
+* - MRCC_CKSYS_Div2: AHB clock = CK_SYS/2\r
+* - MRCC_CKSYS_Div4: AHB clock = CK_SYS/4\r
+* - MRCC_CKSYS_Div8: AHB clock = CK_SYS/8\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_HCLKConfig(u32 MRCC_HCLK)\r
+{\r
+ u32 Temp = 0;\r
+ \r
+ /* Clear HPRESC[1:0] bits */\r
+ Temp = MRCC->CLKCTL & MRCC_HPRESC_Reset_Mask;\r
+ \r
+ /* Set HPRESC[1:0] bits according to MRCC_HCLK value */\r
+ Temp |= MRCC_HCLK;\r
+ \r
+ /* Store the new value */\r
+ MRCC->CLKCTL = Temp; \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_CKTIMConfig\r
+* Description : Configures the TIM clock (CK_TIM).\r
+* Input : - MRCC_CKTIM: defines the TIM clock. This clock is derived\r
+* from the AHB clock(HCLK).\r
+* This parameter can be one of the following values:\r
+* - MRCC_HCLK_Div1: TIM clock = HCLK\r
+* - MRCC_HCLK_Div2: TIM clock = HCLK/2\r
+* - MRCC_HCLK_Div4: TIM clock = HCLK/4\r
+* - MRCC_HCLK_Div8: TIM clock = HCLK/8\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_CKTIMConfig(u32 MRCC_CKTIM)\r
+{\r
+ u32 Temp = 0;\r
+ \r
+ /* Clear PPRESC[1:0] bits */\r
+ Temp = MRCC->CLKCTL & MRCC_PPRESC_Reset_Mask;\r
+ \r
+ /* Set PPRESC[1:0] bits according to MRCC_CKTIM value */\r
+ Temp |= MRCC_CKTIM;\r
+ \r
+ /* Store the new value */\r
+ MRCC->CLKCTL = Temp;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_PCLKConfig\r
+* Description : Configures the APB clock (PCLK).\r
+* Input : - MRCC_PCLK: defines the APB clock. This clock is derived \r
+* from the TIM clock(CK_TIM).\r
+* This parameter can be one of the following values:\r
+* - MRCC_CKTIM_Div1: APB clock = CKTIM\r
+* - MRCC_CKTIM_Div2: APB clock = CKTIM/2\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_PCLKConfig(u32 MRCC_PCLK)\r
+{\r
+ if(MRCC_PCLK == MRCC_CKTIM_Div2)\r
+ {\r
+ MRCC->CLKCTL |= MRCC_CKTIM_Div2;\r
+ }\r
+ else\r
+ {\r
+ MRCC->CLKCTL &= MRCC_CKTIM_Div1;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_CKRTCConfig\r
+* Description : Configures the RTC clock (CK_RTC).\r
+* Input : - MRCC_CKRTC: specifies the clock source to be used as RTC\r
+* clock.\r
+* This parameter can be one of the following values:\r
+* - MRCC_CKRTC_OSC4M_Div128\r
+* - MRCC_CKRTC_OSC32K (OSC32K must be previously enabled\r
+* using MRCC_OSC32KConfig() function)\r
+* - MRCC_CKRTC_LPOSC (LPOSC must be previously enabled\r
+* using MRCC_LPOSCConfig() function)\r
+* Output : None\r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Clock configuration succeeded\r
+* - ERROR: Clock configuration failed\r
+*******************************************************************************/\r
+ErrorStatus MRCC_CKRTCConfig(u32 MRCC_CKRTC)\r
+{\r
+ u32 Tmp = 0;\r
+\r
+ if(((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) &&\r
+ ((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET))\r
+ { \r
+ /* CK_RTC used as CK_SYS clock source */\r
+ return ERROR;\r
+ }\r
+ else\r
+ { \r
+ /* Clear CKRTCSEL[1:0] bits */\r
+ Tmp = MRCC->PWRCTRL & MRCC_CKRTCSEL_Reset_Mask;\r
+\r
+ /* Set CKRTCSEL[1:0] bits according to MRCC_CKRTC value */\r
+ Tmp |= MRCC_CKRTC;\r
+\r
+ /* Store the new value */\r
+ MRCC->PWRCTRL = Tmp; \r
+ }\r
+\r
+ return SUCCESS;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_CKUSBConfig\r
+* Description : Configures the USB clock(CK_USB).\r
+* Input : - MRCC_CKUSB: specifies the clock source to be used as USB\r
+* clock.\r
+* This parameter can be one of the following values:\r
+* - MRCC_CKUSB_Internal(CK_PLL2 enabled)\r
+* - MRCC_CKUSB_External(CK_PLL2 disabled)\r
+* Output : None\r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Clock configuration succeeded\r
+* - ERROR: Clock configuration failed\r
+*******************************************************************************/\r
+ErrorStatus MRCC_CKUSBConfig(u32 MRCC_CKUSB)\r
+{\r
+ if(MRCC_CKUSB == MRCC_CKUSB_External)\r
+ {\r
+ /* Disable CK_PLL2 */\r
+ MRCC->CLKCTL &= MRCC_PLL2EN_Reset_Mask;\r
+\r
+ /* External USB clock selected */\r
+ MRCC->CLKCTL |= MRCC_CKUSB_External;\r
+ }\r
+ else\r
+ {\r
+ if((MRCC->CLKCTL & MRCC_PLLEN_LOCK_Mask) != RESET)\r
+ { /* PLL enabled and locked */\r
+ \r
+ /* Enable CK_PLL2 */\r
+ MRCC->CLKCTL |= MRCC_PLL2EN_Set_Mask;\r
+\r
+ /* Internal USB clock selected */\r
+ MRCC->CLKCTL &= MRCC_CKUSB_Internal;\r
+ }\r
+ else\r
+ {\r
+ /* PLL not enabled */\r
+ return ERROR;\r
+ }\r
+ }\r
+\r
+ return SUCCESS; \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_ITConfig\r
+* Description : Enables or disables the specified MRCC interrupts.\r
+* Input : - MRCC_IT: specifies the MRCC interrupts sources to be\r
+* enabled or disabled. This parameter can be any combination\r
+* of the following values:\r
+* - MRCC_IT_LOCK: PLL lock interrupt\r
+* - MRCC_IT_NCKD: No Clock detected interrupt\r
+* - NewState: new state of the MRCC interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_ITConfig(u32 MRCC_IT, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ MRCC->CLKCTL |= MRCC_IT;\r
+ }\r
+ else\r
+ {\r
+ MRCC->CLKCTL &= ~MRCC_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_PeripheralClockConfig\r
+* Description : Enables or disables the specified peripheral clock.\r
+* Input : - MRCC_Peripheral: specifies the peripheral to gates its\r
+* clock. More than one peripheral can be selected using\r
+* the \93|\94 operator.\r
+* - NewState: new state of the specified peripheral clock.\r
+* This parameter can be one of the following values:\r
+* - ENABLE: the selected peripheral clock is enabled\r
+* - DISABLE: the selected peripheral clock is disabled\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_PeripheralClockConfig(u32 MRCC_Peripheral, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ MRCC->PCLKEN |= MRCC_Peripheral;\r
+ }\r
+ else\r
+ {\r
+ MRCC->PCLKEN &= ~MRCC_Peripheral;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_PeripheralSWResetConfig\r
+* Description : Forces or releases peripheral software reset.\r
+* Input : - MRCC_Peripheral: specifies the peripheral to reset. More\r
+* than one peripheral can be selected using the \93|\94 operator.\r
+* - NewState: new state of the specified peripheral software\r
+* reset. This parameter can be one of the following values:\r
+* - ENABLE: the selected peripheral is kept under reset\r
+* - DISABLE: the selected peripheral exits from reset\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_PeripheralSWResetConfig(u32 MRCC_Peripheral, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ MRCC->PSWRES |= MRCC_Peripheral;\r
+ }\r
+ else\r
+ {\r
+ MRCC->PSWRES &= ~MRCC_Peripheral;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_GetClocksStatus\r
+* Description : Returns the status and frequencies of different on chip clocks.\r
+* Don\92t use this function when CK_SYS is clocked by an external\r
+* clock source (OSC4M bypassed).\r
+* Input : - MRCC_ClocksStatus: pointer to a MRCC_ClocksTypeDef structure\r
+* which will hold the clocks information.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_GetClocksStatus(MRCC_ClocksTypeDef* MRCC_ClocksStatus)\r
+{\r
+ u32 PLLMul = 0;\r
+ u32 Temp = 0;\r
+ u32 Presc = 0;\r
+\r
+ /* Get the Status of PLL */\r
+ if((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) == RESET) \r
+ {\r
+ MRCC_ClocksStatus->PLL_Status = OFF;\r
+ }\r
+ else\r
+ {\r
+ MRCC_ClocksStatus->PLL_Status = ON;\r
+ }\r
+ \r
+ /* Get the Status of OSC4M */\r
+ if((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) == RESET) \r
+ {\r
+ MRCC_ClocksStatus->OSC4M_Status = ON;\r
+ }\r
+ else\r
+ {\r
+ MRCC_ClocksStatus->OSC4M_Status = OFF;\r
+ } \r
+ \r
+ /* Get the Status of LPOSC */\r
+ if((MRCC->PWRCTRL & MRCC_LPOSCEN_Mask) == RESET) \r
+ {\r
+ MRCC_ClocksStatus->LPOSC_Status = OFF;\r
+ }\r
+ else\r
+ {\r
+ MRCC_ClocksStatus->LPOSC_Status = ON;\r
+ } \r
+ \r
+ /* Get the Status of OSC32K */\r
+ if((MRCC->PWRCTRL & MRCC_OSC32KEN_Mask) == RESET) \r
+ {\r
+ MRCC_ClocksStatus->OSC32K_Status = OFF;\r
+ }\r
+ else\r
+ {\r
+ MRCC_ClocksStatus->OSC32K_Status = ON;\r
+ } \r
+ \r
+/* Get CKU_SB source ---------------------------------------------------------*/ \r
+ if((MRCC->CLKCTL & MRCC_CKUSBSEL_Mask) != RESET)\r
+ {\r
+ MRCC_ClocksStatus->CKUSB_Source = External; \r
+ }\r
+ else\r
+ { \r
+ if((MRCC->CLKCTL & MRCC_PLL2EN_Set_Mask) != RESET)\r
+ {\r
+ MRCC_ClocksStatus->CKUSB_Source = Internal;\r
+ \r
+ }\r
+ else \r
+ {\r
+ MRCC_ClocksStatus->CKUSB_Source = Disabled; \r
+ }\r
+ }\r
+\r
+/* Get CK_RTC source ---------------------------------------------------------*/ \r
+ Temp = MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask;\r
+ Temp = Temp >> 24;\r
+ \r
+ switch(Temp)\r
+ {\r
+ case 0x00:\r
+ MRCC_ClocksStatus->CKRTC_Source = Disabled;\r
+ break;\r
+\r
+ case 0x01:\r
+ MRCC_ClocksStatus->CKRTC_Source = OSC4M_Div128;\r
+ break;\r
+\r
+ case 0x02:\r
+ MRCC_ClocksStatus->CKRTC_Source = OSC32K;\r
+ break;\r
+ \r
+ case 0x03:\r
+ MRCC_ClocksStatus->CKRTC_Source = LPOSC; \r
+ break;\r
+ \r
+ default:\r
+ MRCC_ClocksStatus->CKRTC_Source = Disabled;\r
+ break; \r
+ }\r
+ \r
+/* Get CK_SYS source ---------------------------------------------------------*/ \r
+ if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET)\r
+ {/* CK_OSC used as CK_SYS clock source */\r
+ \r
+ if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)\r
+ { /* CK_RTC used as CK_OSC clock source */\r
+ MRCC_ClocksStatus->CKSYS_Source = CKRTC;\r
+ \r
+ if(MRCC_ClocksStatus->CKRTC_Source == OSC32K)\r
+ {\r
+ /* CK_SYS clock frequency */\r
+ MRCC_ClocksStatus->CKSYS_Frequency = OSC32K_Value; \r
+ } \r
+ else if(MRCC_ClocksStatus->CKRTC_Source == LPOSC)\r
+\r
+ {\r
+ /* CK_SYS clock frequency */\r
+ MRCC_ClocksStatus->CKSYS_Frequency = LPOSC_Value; \r
+ }\r
+ else if(MRCC_ClocksStatus->CKRTC_Source == OSC4M_Div128)\r
+\r
+ {\r
+ /* CK_SYS clock frequency */\r
+ MRCC_ClocksStatus->CKSYS_Frequency = OSC4M_Div128_Value; \r
+ }\r
+ }\r
+ else\r
+ { /* OSC4M used as CK_OSC clock source */\r
+ MRCC_ClocksStatus->CKSYS_Source = OSC4M; \r
+ \r
+ if((MRCC->CLKCTL & MRCC_XTDIV2_Set_Mask) != RESET)\r
+ {\r
+ /* CK_SYS clock frequency */\r
+ MRCC_ClocksStatus->CKSYS_Frequency = Main_Oscillator >> 1;\r
+ }\r
+ else\r
+ {\r
+ /* CK_SYS clock frequency */\r
+ MRCC_ClocksStatus->CKSYS_Frequency = Main_Oscillator;\r
+ } \r
+ }\r
+ } \r
+ else\r
+ {/* CK_PLL1 used as CK_SYS clock */\r
+ \r
+ if(MRCC_ClocksStatus->PLL_Status == OFF)\r
+ { /* FREEOSC used as CK_PLL1 clock source */\r
+ MRCC_ClocksStatus->CKSYS_Source = FREEOSC; \r
+ \r
+ /* CK_SYS clock frequency */\r
+ MRCC_ClocksStatus->CKSYS_Frequency = FREEOSC_Value; \r
+ }\r
+ else\r
+ { /* OSC4M followed by PLL used as CK_PLL1 clock source */\r
+ MRCC_ClocksStatus->CKSYS_Source = OSC4MPLL;\r
+ \r
+ /* Get PLL factor ------------------------------------------------------*/\r
+ Temp = MRCC->CLKCTL & MRCC_MX_Set_Mask;\r
+ Temp = Temp >> 27;\r
+ \r
+ switch(Temp)\r
+ {\r
+ case 0x00:\r
+ PLLMul = 16;\r
+ break;\r
+\r
+ case 0x01:\r
+ PLLMul = 15;\r
+ break;\r
+\r
+ case 0x02:\r
+ PLLMul = 14;\r
+ break;\r
+ \r
+ case 0x03:\r
+ PLLMul = 12;\r
+ break;\r
+ \r
+ default:\r
+ PLLMul = 16;\r
+ break; \r
+ } \r
+ \r
+ /* CK_SYS clock frequency */\r
+ MRCC_ClocksStatus->CKSYS_Frequency = OSC4M_Value * PLLMul; \r
+ }\r
+ }\r
+\r
+/* Compute HCLK, CKTIM and PCLK clocks frequencies ---------------------------*/ \r
+ /* Get HCLK prescaler */\r
+ Presc = MRCC->CLKCTL & MRCC_HPRESC_Set_Mask;\r
+ Presc = Presc >> 3;\r
+ /* HCLK clock frequency */\r
+ MRCC_ClocksStatus->HCLK_Frequency = MRCC_ClocksStatus->CKSYS_Frequency >> Presc;\r
+\r
+ /* Get CK_TIM prescaler */\r
+ Presc = MRCC->CLKCTL & MRCC_PPRESC_Set_Mask;\r
+ /* CK_TIM clock frequency */\r
+ MRCC_ClocksStatus->CKTIM_Frequency = MRCC_ClocksStatus->HCLK_Frequency >> Presc;\r
+ \r
+ /* Get PCLK prescaler */\r
+ Presc = MRCC->CLKCTL & MRCC_PPRESC2_Mask;\r
+ Presc = Presc >> 2;\r
+ /* PCLK clock frequency */\r
+ MRCC_ClocksStatus->PCLK_Frequency = MRCC_ClocksStatus->CKTIM_Frequency >> Presc;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_LPMC_DBGonfig\r
+* Description : Enables or disables the Low Power Debug Mode.\r
+* Input : - MRCC_LPDM: specifies the LPDM new state value.\r
+* This parameter can be one of the following values:\r
+* - MRCC_LPDM_Disable\r
+* - MRCC_LPDM_Enable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_LPMC_DBGConfig(u32 MRCC_LPDM)\r
+{\r
+ if(MRCC_LPDM == MRCC_LPDM_Enable)\r
+ {\r
+ MRCC->PWRCTRL |= MRCC_LPDM_Enable;\r
+ }\r
+ else\r
+ {\r
+ MRCC->PWRCTRL &= MRCC_LPDM_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_EnterWFIMode\r
+* Description : Enters WFI mode.\r
+* If the Flash is used in Burst mode, it must be kept enabled\r
+* in WFI mode(use MRCC_WFIParam_FLASHOn as parameter)\r
+* Input : - MRCC_WFIParam: specifies the WFI mode control parameters.\r
+* This parameter can be one of the following values:\r
+* - MRCC_WFIParam_FLASHPowerDown(DMA not allowed during WFI)\r
+* - MRCC_WFIParam_FLASHOn(DMA allowed during WFI)\r
+* - MRCC_WFIParam_FLASHOff(DMA not allowed during WFI)\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_EnterWFIMode(u32 MRCC_WFIParam)\r
+{\r
+/* Low Power mode configuration ----------------------------------------------*/\r
+ /* Clear LPMC[1:0] bits */\r
+ MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask;\r
+\r
+ /* Select WFI mode */\r
+ MRCC->PWRCTRL |= MRCC_WFI_Mask;\r
+\r
+/* Low Power mode control parameters configuration ---------------------------*/\r
+ /* Clear LP_PARAM[15:13] and WFI_FLASH_EN bits */\r
+ MRCC->PWRCTRL &= MRCC_WFIParam_Reset_Mask;\r
+ \r
+ if(MRCC_WFIParam != MRCC_WFIParam_FLASHPowerDown)\r
+ {\r
+ /* Set LP_PARAM[15:13] and WFI_FLASH_EN bits according to MRCC_WFIParam value */\r
+ MRCC->PWRCTRL |= MRCC_WFIParam;\r
+ }\r
+ \r
+/* Execute the Low Power bit writing sequence --------------------------------*/\r
+ WriteLPBit();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_EnterSTOPMode\r
+* Description : Enters STOP mode.\r
+* Input : - MRCC_STOPParam: specifies the STOP mode control parameters.\r
+* This parameter can be one of the following values:\r
+* - MRCC_STOPParam_Default (OSC4M On, FLASH On, MVREG On)\r
+* - MRCC_STOPParam_OSC4MOff\r
+* - MRCC_STOPParam_FLASHOff\r
+* - MRCC_STOPParam_MVREGOff\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_EnterSTOPMode(u32 MRCC_STOPParam)\r
+{\r
+/* Low Power mode configuration ----------------------------------------------*/\r
+ /* Clear LPMC[1:0] bits (STOP mode is selected) */\r
+ MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask;\r
+\r
+/* Low Power mode control parameters configuration ---------------------------*/\r
+ /* Clear LP_PARAM[15:13] bits */\r
+ MRCC->PWRCTRL &= MRCC_LPPARAM_Reset_Mask;\r
+ \r
+ if(MRCC_STOPParam != MRCC_STOPParam_Default)\r
+ {\r
+ /* Set LP_PARAM[15:13] bits according to MRCC_STOPParam value */\r
+ MRCC->PWRCTRL |= MRCC_STOPParam;\r
+ }\r
+\r
+/* Execute the Low Power bit writing sequence --------------------------------*/\r
+ WriteLPBit();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_EnterSTANDBYMode\r
+* Description : Enters STANDBY mode.\r
+* Make sure that WKPF flag is cleared before using this function.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_EnterSTANDBYMode(void)\r
+{\r
+/* Low Power mode configuration ----------------------------------------------*/\r
+ /* Clear LPMC[1:0] bits */\r
+ MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask;\r
+\r
+ /* Select STANDBY mode */\r
+ MRCC->PWRCTRL |= MRCC_STANDBY_Mask;\r
+\r
+/* Execute the Low Power bit writing sequence --------------------------------*/\r
+ WriteLPBit();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_GenerateSWReset\r
+* Description : Generates a system software reset.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_GenerateSWReset(void)\r
+{\r
+/* Low Power mode configuration ----------------------------------------------*/\r
+ /* Clear LPMC[1:0] bits */\r
+ MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask;\r
+\r
+ /* Select software reset */\r
+ MRCC->PWRCTRL |= MRCC_SWRESET_Mask;\r
+\r
+/* Execute the Low Power bit writing sequence --------------------------------*/\r
+ WriteLPBit();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_WriteBackupRegister\r
+* Description : Writes user data to the specified backup register.\r
+* Input : - MRCC_BKP: specifies the backup register.\r
+* This parameter can be one of the following values:\r
+* - MRCC_BKP0\r
+* - MRCC_BKP1\r
+* - Data: data to write.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_WriteBackupRegister(MRCC_BKPReg MRCC_BKP, u32 Data)\r
+{\r
+ if(MRCC_BKP == MRCC_BKP0)\r
+ {\r
+ MRCC->BKP0 = Data;\r
+ }\r
+ else\r
+ {\r
+ MRCC->BKP1 = Data;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_ReadBackupRegister\r
+* Description : Reads data from the specified backup register.\r
+* Input : - MRCC_BKP: specifies the backup register.\r
+* This parameter can be one of the following values:\r
+* - MRCC_BKP0\r
+* - MRCC_BKP1\r
+* Output : None\r
+* Return : The content of the specified backup register.\r
+*******************************************************************************/\r
+u32 MRCC_ReadBackupRegister(MRCC_BKPReg MRCC_BKP)\r
+{\r
+ if(MRCC_BKP == MRCC_BKP0)\r
+ {\r
+ return(MRCC->BKP0);\r
+ }\r
+ else\r
+ {\r
+ return(MRCC->BKP1);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_IOVoltageRangeConfig\r
+* Description : Configures the I/O pins voltage range.\r
+* Input : - MRCC_IOVoltageRange: specifies the I/O pins voltage range.\r
+* This parameter can be one of the following values:\r
+* - MRCC_IOVoltageRange_5V\r
+* - MRCC_IOVoltageRange_3V3\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_IOVoltageRangeConfig(u32 MRCC_IOVoltageRange)\r
+{\r
+ if(MRCC_IOVoltageRange == MRCC_IOVoltageRange_3V3)\r
+ {\r
+ MRCC->PWRCTRL |= MRCC_IOVoltageRange_3V3;\r
+ }\r
+ else\r
+ {\r
+ MRCC->PWRCTRL &= MRCC_IOVoltageRange_5V;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_MCOConfig\r
+* Description : Selects the clock source to output on MCO pin (P0.1).\r
+* To output the clock, the associated alternate function must\r
+* be enabled in the I/O port controller.\r
+* Input : - MRCC_MCO: specifies the clock source to output.\r
+* This parameter can be one of the following values:\r
+* - MRCC_MCO_HCLK\r
+* - MRCC_MCO_PCLK\r
+* - MRCC_MCO_OSC4M\r
+* - MRCC_MCO_CKPLL2\r
+* - MRCC_MCOPrescaler: specifies if prescaler, divide by 1 or 2,\r
+* is applied to this clock before outputting it to MCO pin.\r
+* This parameter can be one of the following values:\r
+* - MRCC_MCOPrescaler_1\r
+* - MRCC_MCOPrescaler_2\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_MCOConfig(u32 MRCC_MCO, u32 MCO_MCOPrescaler)\r
+{\r
+ u32 Temp = 0;\r
+/* MCO prescaler configuration -----------------------------------------------*/\r
+ if(MCO_MCOPrescaler == MRCC_MCOPrescaler_2)\r
+ {\r
+ MRCC->CLKCTL |= MRCC_MCOPrescaler_2;\r
+ }\r
+ else\r
+ {\r
+ MRCC->CLKCTL &= MRCC_MCOPrescaler_1;\r
+ }\r
+\r
+/* MCO selection configuration -----------------------------------------------*/\r
+\r
+ /* Clear MCOS[1:0] bits */\r
+ Temp = MRCC->CLKCTL & MRCC_MCOS_Reset_Mask;\r
+\r
+ /* Set MCOS[1:0] bits according to MRCC_MCO value */\r
+ Temp |= MRCC_MCO;\r
+ \r
+ /* Store the new value */\r
+ MRCC->CLKCTL = Temp;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_OSC4MConfig\r
+* Description : Configures the 4MHz main oscillator (OSC4M).\r
+* This function must be used when the CK_SYS is not clocked\r
+* by the OSC4M and the PLL is not enabled.\r
+* Input : - MRCC_OSC4M: specifies the new state of the OSC4M oscillator.\r
+* This parameter can be one of the following values:\r
+* - MRCC_OSC4M_Default: OSC4M enabled, bypass disabled\r
+* - MRCC_OSC4M_Disable: OSC4M disabled\r
+* - MRCC_OSC4M_Bypass: OSC4M bypassed\r
+* Output : None\r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Clock configuration succeeded\r
+* - ERROR: Clock configuration failed\r
+*******************************************************************************/\r
+ErrorStatus MRCC_OSC4MConfig(u32 MRCC_OSC4M)\r
+{\r
+ ErrorStatus Status = SUCCESS;\r
+\r
+/* If CK_SYS is driven by OSC4M or the PLL is enabled, exit ------------------*/ \r
+ if(((MRCC->CLKCTL & MRCC_CKSEL_CKOSCSEL_Mask) == MRCC_CKSEL_Set_Mask) || \r
+ (((MRCC->CLKCTL & MRCC_CKSEL_CKOSCSEL_Mask) == MRCC_CKSEL_CKOSCSEL_Mask) &&\r
+ ((MRCC->PWRCTRL & MRCC_CKRTCSEL_Reset_Mask) != RESET))||\r
+ ((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET))\r
+ {\r
+ Status = ERROR;\r
+ }\r
+/* Else configure the OSC4MOFF and OSC4MBYP bits -----------------------------*/ \r
+ else\r
+ { \r
+ switch(MRCC_OSC4M)\r
+ {\r
+ case MRCC_OSC4M_Default:\r
+ MRCC->CLKCTL &= MRCC_OSC4MOFF_Reset_Mask & MRCC_OSC4MBYP_Reset_Mask;\r
+ break;\r
+ \r
+ case MRCC_OSC4M_Disable:\r
+ MRCC->CLKCTL &= MRCC_OSC4MBYP_Reset_Mask;\r
+ MRCC->CLKCTL |= MRCC_OSC4MOFF_Set_Mask;\r
+ break;\r
+ \r
+ case MRCC_OSC4M_Bypass:\r
+ MRCC->CLKCTL &= MRCC_OSC4MOFF_Reset_Mask;\r
+ MRCC->CLKCTL |= MRCC_OSC4MBYP_Set_Mask;\r
+ break; \r
+ \r
+ default:\r
+ Status = ERROR;\r
+ break; \r
+ }\r
+ } \r
+ \r
+ return Status; \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_OSC32KConfig\r
+* Description : Configures the OSC32K oscillator.\r
+* This function must be used when the CK_SYS is not clocked by\r
+* the CK_RTC.\r
+* Input : - MRCC_OSC32K: specifies the new state of the OSC32K oscillator.\r
+* This parameter can be one of the following values:\r
+* - MRCC_OSC32K_Disable: OSC32K disabled\r
+* - MRCC_OSC32K_Enable: OSC32K enabled\r
+* - MRCC_OSC32KBypass: specifies if the OSC32K oscillator is\r
+* bypassed or not.\r
+* This parameter can be one of the following values:\r
+* - MRCC_OSC32KBypass_Disable: OSC32K selected\r
+* - MRCC_OSC32KBypass_Enable: OSC32K bypassed \r
+* Output : None\r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Clock configuration succeeded\r
+* - ERROR: Clock configuration failed\r
+*******************************************************************************/\r
+ErrorStatus MRCC_OSC32KConfig(u32 MRCC_OSC32K, u32 MRCC_OSC32KBypass)\r
+{ \r
+/* If CK_SYS is driven by CK_RTC, exit ---------------------------------------*/ \r
+ if(((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) &&\r
+ ((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET))\r
+ {\r
+ return ERROR;\r
+ }\r
+/* Else configure the OSC32KEN and OSC32KBYP bits ----------------------------*/ \r
+ else\r
+ { \r
+ /* Configure OSC32KEN bit */\r
+ if(MRCC_OSC32K == MRCC_OSC32K_Enable)\r
+ {\r
+ MRCC->PWRCTRL |= MRCC_OSC32K_Enable;\r
+ }\r
+ else\r
+ {\r
+ MRCC->PWRCTRL &= MRCC_OSC32K_Disable;\r
+ }\r
+ \r
+ /* Configure OSC32KBYP bit */\r
+ if(MRCC_OSC32KBypass == MRCC_OSC32KBypass_Enable)\r
+ {\r
+ MRCC->PWRCTRL |= MRCC_OSC32KBypass_Enable;\r
+ }\r
+ else\r
+ {\r
+ MRCC->PWRCTRL &= MRCC_OSC32KBypass_Disable;\r
+ } \r
+ \r
+ return SUCCESS; \r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_LPOSCConfig\r
+* Description : Enables or disables the LPOSC oscillator.\r
+* This function must be used when the CK_SYS is not clocked by\r
+* the CK_RTC.\r
+* Input : - MRCC_LPOSC: specifies the new state of the LPOSC oscillator.\r
+* This parameter can be one of the following values:\r
+* - MRCC_LPOSC_Disable: LPOSC disabled\r
+* - MRCC_LPOSC_Enable: LPOSC enabled\r
+* Output : None\r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Clock configuration succeeded\r
+* - ERROR: Clock configuration failed\r
+*******************************************************************************/\r
+ErrorStatus MRCC_LPOSCConfig(u32 MRCC_LPOSC)\r
+{\r
+/* If CK_SYS is driven by CK_RTC or LPOSC is used as CK_RTC clock source, exit*/ \r
+ if((((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) &&\r
+ ((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)) ||\r
+ ((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) == MRCC_CKRTC_LPOSC)) \r
+ {\r
+ return ERROR;\r
+ }\r
+/* Else configure the LPOSCEN bit --------------------------------------------*/ \r
+ else\r
+ { \r
+ if(MRCC_LPOSC == MRCC_LPOSC_Enable)\r
+ {\r
+ MRCC->PWRCTRL |= MRCC_LPOSC_Enable;\r
+ }\r
+ else\r
+ {\r
+ MRCC->PWRCTRL &= MRCC_LPOSC_Disable;\r
+ }\r
+\r
+ return SUCCESS;\r
+ } \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_RTCMConfig\r
+* Description : Enables or disables RTC clock measurement.\r
+* Input : - MRCC_RTCM: specifies whether CK_RTC is connected to TB \r
+* timer IC1 or not.\r
+* This parameter can be one of the following values:\r
+* - MRCC_RTCM_Disable: CK_RTC not connected to TB timer IC1\r
+* - MRCC_RTCM_Enable: CK_RTC connected to TB timer IC1\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_RTCMConfig(u32 MRCC_RTCM)\r
+{\r
+ if(MRCC_RTCM == MRCC_RTCM_Enable)\r
+ {\r
+ MRCC->PWRCTRL |= MRCC_RTCM_Enable;\r
+ }\r
+ else\r
+ {\r
+ MRCC->PWRCTRL &= MRCC_RTCM_Disable;\r
+ } \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_SetBuilderCounter\r
+* Description : Sets the builder counter value which defines the delay for\r
+* the 4MHz main oscillator (OSC4M) clock to be stabilized.\r
+* Input : - BuilderCounter: defines the delay for the OSC4M oscillator\r
+* clock to be stabilized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_SetBuilderCounter(u8 BuilderCounter)\r
+{ \r
+ *(u8 *) 0x60000026 = BuilderCounter;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_GetCKSYSCounter\r
+* Description : Gets the result of the delay applied to CK_SYS before\r
+* starting the CPU.\r
+* Input : None\r
+* Output : None\r
+* Return : SCOUNT value.\r
+*******************************************************************************/\r
+u16 MRCC_GetCKSYSCounter(void)\r
+{\r
+ return((u16)(MRCC->RFSR & 0x0FFF));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_GetFlagStatus\r
+* Description : Checks whether the specified MRCC flag is set or not.\r
+* Input : - MRCC_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - MRCC_FLAG_LOCK: PLL Locked flag\r
+* - MRCC_FLAG_LOCKIF: PLL Lock Interrupt status flag\r
+* - MRCC_FLAG_CKSEL: CK_SYS source staus flag\r
+* - MRCC_FLAG_CKOSCSEL: CK_OSC clock source staus flag\r
+* - MRCC_FLAG_NCKD: No Clock Detected flag\r
+* - MRCC_FLAG_SWR: Software Reset flag\r
+* - MRCC_FLAG_WDGR: Watchdog Reset flag\r
+* - MRCC_FLAG_EXTR: External Reset flag\r
+* - MRCC_FLAG_WKP: Wake-Up flag\r
+* - MRCC_FLAG_STDB: STANDBY flag\r
+* - MRCC_FLAG_BCOUNT: Builder Counter Flag\r
+* - MRCC_FLAG_OSC32KRDY: Oscillator 32K Ready\r
+* - MRCC_FLAG_CKRTCOK: CK_RTC OK\r
+* - MRCC_FLAG_LPDONE: Low Power Bit Sequence has been performed\r
+* - MRCC_FLAG_LP: Low Power Mode Entry\r
+* Output : None\r
+* Return : The new state of MRCC_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus MRCC_GetFlagStatus(u8 MRCC_FLAG)\r
+{\r
+ u32 MRCCReg = 0, FlagPos = 0;\r
+ u32 StatusReg = 0;\r
+\r
+ /* Get the MRCC register index */\r
+ MRCCReg = MRCC_FLAG >> 5;\r
+\r
+ /* Get the flag position */\r
+ FlagPos = MRCC_FLAG & MRCC_FLAG_Mask;\r
+\r
+ if(MRCCReg == 1) /* The flag to check is in CLKCTL register */\r
+ {\r
+ StatusReg = MRCC->CLKCTL;\r
+ }\r
+ else if (MRCCReg == 2) /* The flag to check is in RFSR register */\r
+ {\r
+ StatusReg = MRCC->RFSR;\r
+ }\r
+ else if(MRCCReg == 3) /* The flag to check is in PWRCTRL register */\r
+ {\r
+ StatusReg = MRCC->PWRCTRL;\r
+ }\r
+ \r
+ if((StatusReg & (1 << FlagPos))!= RESET)\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_ClearFlag\r
+* Description : Clears the MRCC\92s pending flags.\r
+* Input : - MRCC_FLAG: specifies the flag to clear.\r
+* This parameter can be one of the following values:\r
+* - MRCC_FLAG_NCKD: No Clock Detected flag\r
+* - MRCC_FLAG_SWR: Software Reset flag\r
+* - MRCC_FLAG_WDGR: Watchdog Reset flag\r
+* - MRCC_FLAG_EXTR: External Reset flag\r
+* - MRCC_FLAG_WKP: Wake-Up flag\r
+* - MRCC_FLAG_STDB: STANDBY flag\r
+* - MRCC_FLAG_LPDONE: Low Power Bit Sequence has been performed\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_ClearFlag(u8 MRCC_FLAG)\r
+{\r
+ u32 MRCCReg = 0, FlagPos = 0;\r
+\r
+ /* Get the MRCC register index */\r
+ MRCCReg = MRCC_FLAG >> 5;\r
+\r
+ /* Get the flag position */\r
+ FlagPos = MRCC_FLAG & MRCC_FLAG_Mask;\r
+\r
+ if(MRCCReg == 1) /* The flag to clear is in CLKCTL register */\r
+ {\r
+ MRCC->CLKCTL &= ~(1 << FlagPos);\r
+ }\r
+ else if (MRCCReg == 2) /* The flag to clear is in RFSR register */\r
+ {\r
+ MRCC->RFSR &= ~(1 << FlagPos);\r
+ }\r
+ else if(MRCCReg == 3) /* The flag to clear is in PWRCTRL register */\r
+ {\r
+ MRCC->PWRCTRL &= ~(1 << FlagPos);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_GetITStatus\r
+* Description : Checks whether the specified MRCC interrupt has occurred or not.\r
+* Input : - MRCC_IT: specifies the MRCC interrupt source to check.\r
+* This parameter can be one of the following values:\r
+* - MRCC_IT_LOCK: PLL lock interrupt\r
+* - MRCC_IT_NCKD: No Clock detected interrupt\r
+* Output : None\r
+* Return : The new state of MRCC_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus MRCC_GetITStatus(u32 MRCC_IT)\r
+{\r
+ /* Check the specified interrupt pending bit */\r
+ if((MRCC->CLKCTL & (MRCC_IT >> 1)) != RESET)\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_ClearITPendingBit\r
+* Description : Clears the MRCC\92s interrupt pending bits.\r
+* Input : - MRCC_IT: specifies the interrupt pending bit to clear.\r
+* This parameter can be any combination of the following\r
+* values:\r
+* - MRCC_IT_LOCK: PLL lock interrupt\r
+* - MRCC_IT_NCKD: No Clock detected interrupt\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void MRCC_ClearITPendingBit(u32 MRCC_IT)\r
+{\r
+ /* Clear the specified interrupt pending bit */\r
+ MRCC->CLKCTL &= ~(MRCC_IT >> 1);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : MRCC_WaitForOSC4MStartUp\r
+* Description : Waits for OSC4M start-up.\r
+* Input : None\r
+* Output : None\r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: OSC4M oscillator is stable and ready to use\r
+* - ERROR: no clock is detected on OSC4M\r
+*******************************************************************************/\r
+ErrorStatus MRCC_WaitForOSC4MStartUp(void)\r
+{\r
+ u32 StartUpCounter = 0;\r
+\r
+ do\r
+ {\r
+ /* Clear No Clock Detected flag */\r
+ if(MRCC_GetFlagStatus(MRCC_FLAG_NCKD) != RESET)\r
+ {\r
+ MRCC_ClearFlag(MRCC_FLAG_NCKD);\r
+ }\r
+\r
+ StartUpCounter++;\r
+\r
+ }while((MRCC_GetFlagStatus(MRCC_FLAG_BCOUNT) == RESET)&&\r
+ (StartUpCounter != OSC4MStartUp_TimeOut));\r
+ \r
+ if(MRCC_GetFlagStatus(MRCC_FLAG_BCOUNT) != RESET)\r
+ {\r
+ return SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ return ERROR;\r
+ } \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SetCKSYS_FREEOSC\r
+* Description : Selects FREEOSC as CK_SYS clock source.\r
+* Input : None\r
+* Output : None\r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Clock configuration succeeded\r
+* - ERROR: Clock configuration failed\r
+*******************************************************************************/\r
+static ErrorStatus SetCKSYS_FREEOSC(void)\r
+{\r
+ /* Check if the PLL is enabled */\r
+ if((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET)\r
+ { \r
+ if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET)\r
+ { /* CK_PLL1 used as Ck_SYS clock source*/\r
+\r
+ if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)\r
+ {/* Check if CK_RTC source clock is present*/ \r
+ if((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) == RESET) \r
+ {\r
+ /* CK_RTC disabled*/\r
+ return ERROR;\r
+ }\r
+ }\r
+ \r
+ /* Select CK_OSC as CK_SYS clock source */\r
+ MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask;\r
+ } \r
+ \r
+ /* Disable PLL */\r
+ MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask;\r
+ }\r
+\r
+ /* Select CK_PLL1 as CK_SYS clock source */\r
+ MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;\r
+\r
+ if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET)\r
+ {\r
+ return SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ return ERROR;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SetCKSYS_OSC4M\r
+* Description : Selects 4MHz main oscillator (OSC4M) as CK_SYS clock source.\r
+* Input : PLL_State: specifies the PLL state.\r
+* Output : None\r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Clock configuration succeeded\r
+* - ERROR: Clock configuration failed\r
+*******************************************************************************/\r
+static ErrorStatus SetCKSYS_OSC4M(u32 PLL_State)\r
+{\r
+/* If OSC4M is not present, exit ---------------------------------------------*/ \r
+ if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) || \r
+ ((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) != RESET) ) \r
+ {\r
+ /* OSC4M disabled or OSC4M clock is not present*/\r
+ return ERROR;\r
+ }\r
+\r
+/* Else configure CKSEL and CKOSCSEL bits ------------------------------------*/ \r
+ if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)\r
+ { /* CK_RTC used as CK_OSC clock */ \r
+ \r
+ if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) \r
+ {\r
+ /* Select CK_PLL1 as CK_SYS clock source */\r
+ MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;\r
+ }\r
+ \r
+ /* Clear CKOSCSEL bit ----------------------------------------------------*/\r
+ /* Execute CKOSCSEL bit writing sequence */\r
+ WriteCKOSCSELBit();\r
+\r
+ /* Check if CKOSCSEL is set to 0 */\r
+ if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)\r
+ {\r
+ return ERROR;\r
+ }\r
+ } \r
+ \r
+ /* Select CK_OSC as CK_SYS clock source */\r
+ MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask;\r
+\r
+ if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET)\r
+ {\r
+ if(PLL_State == MRCC_PLL_Disabled)\r
+ {\r
+ /* Disable PLL */\r
+ MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask;\r
+ }\r
+ \r
+ return SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ return ERROR;\r
+ } \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SetCKSYS_OSC4MPLL\r
+* Description : Selects 4MHz main oscillator (OSC4M) followed by PLL as\r
+* CK_SYS clock source.\r
+* Input : PLL_Mul: specifies the PLL factor.\r
+* Output : None\r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Clock configuration succeeded\r
+* - ERROR: Clock configuration failed\r
+*******************************************************************************/\r
+static ErrorStatus SetCKSYS_OSC4MPLL(u32 PLL_Mul)\r
+{\r
+ /* Check if 4MHz main oscillator clock is present */\r
+ if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) == RESET) && \r
+ ((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) == RESET)) \r
+ { \r
+ if(((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET) &&\r
+ ((MRCC->CLKCTL & MRCC_MX_Set_Mask) == PLL_Mul))\r
+ {\r
+ /* Select CK_PLL1 as CK_SYS clock source */\r
+ MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;\r
+\r
+ if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET)\r
+ {\r
+ return SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ return ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* If CK_RTC is selected as CK_OSC clock source */\r
+ if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)\r
+ {\r
+ if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET)\r
+ {\r
+ /* Clear CKSEL bit */\r
+ MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;\r
+ }\r
+\r
+ /* Clear CKOSCSEL bit ------------------------------------------------*/\r
+ /* Execute CKOSCSEL bit writing sequence */\r
+ WriteCKOSCSELBit();\r
+ \r
+ /* Check if CKOSCSEL is set to 0 */\r
+ if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)\r
+ {\r
+ return ERROR;\r
+ }\r
+ }\r
+\r
+ /* Select CK_OSC as CK_SYS clock source */\r
+ MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask;\r
+\r
+ /* Disable PLL */\r
+ MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask;\r
+\r
+ /* Configure PLL factor */\r
+ if(PLL_Mul == MRCC_PLL_Mul_16)\r
+ {\r
+ MRCC->CLKCTL &= MRCC_MX_Reset_Mask;\r
+ }\r
+ else if((PLL_Mul == MRCC_PLL_Mul_15) || (PLL_Mul == MRCC_PLL_Mul_14) ||\r
+ (PLL_Mul == MRCC_PLL_Mul_12))\r
+ {\r
+ /* Clear MX[1:0] bits */\r
+ MRCC->CLKCTL &= MRCC_MX_Reset_Mask;\r
+ /* Set MX[1:0] bits according to PLL_Mul value */\r
+ MRCC->CLKCTL |= PLL_Mul;\r
+ }\r
+ \r
+ if(Main_Oscillator == 4000000)\r
+ {/* 4 MHz external Quartz oscillator used as main oscillator */\r
+ /* Disable Oscillator Divider by 2 */\r
+ MRCC->CLKCTL &= MRCC_XTDIV2_Reset_Mask;\r
+ }\r
+ else if(Main_Oscillator == 8000000)\r
+ {/* 8 MHz external Quartz oscillator used as main oscillator */\r
+ /* Enable Oscillator Divider by 2 */\r
+ MRCC->CLKCTL |= MRCC_XTDIV2_Set_Mask;\r
+ }\r
+\r
+ /* Enable PLL */\r
+ MRCC->CLKCTL |= MRCC_PLLEN_Set_Mask;\r
+ \r
+ /* Wait until the PLL is locked */\r
+ while((MRCC->CLKCTL & MRCC_LOCK_Mask) == RESET)\r
+ {\r
+ /* If OSC4M clock disapear or the PLL is disabled, exit */\r
+ if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) ||\r
+ ((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) == RESET)) \r
+ {\r
+ return ERROR;\r
+ }\r
+ }\r
+\r
+ /* Select CK_PLL1 as CK_SYS clock source */\r
+ MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;\r
+\r
+ if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET)\r
+ {\r
+ return SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ return ERROR;\r
+ }\r
+ }\r
+ }\r
+ else \r
+ {\r
+ /* OSC4M disabled or OSC4M clock is not present*/\r
+ return ERROR;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SetCKSYS_RTC\r
+* Description : Selects RTC clock (CK_RTC) as CK_SYS clock source.\r
+* Input : PLL_State: specifies the PLL state.\r
+* Output : None\r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Clock configuration succeeded\r
+* - ERROR: Clock configuration failed\r
+*******************************************************************************/\r
+static ErrorStatus SetCKSYS_RTC(u32 PLL_State)\r
+{\r
+ /* Check if CK_RTC clock is enabled and ready to use */\r
+ if(((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) != RESET)||\r
+ ((MRCC->CLKCTL & MRCC_CKRTCOK_Mask) == RESET))\r
+ {\r
+/* Configure CK_RTC as Ck_SYS clock source -----------------------------------*/\r
+ if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) == RESET)\r
+ { \r
+ /* Select CK_PLL1 as CK_SYS clock source */\r
+ MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;\r
+ \r
+ /* Set CKOSCSEL bit ----------------------------------------------------*/\r
+ /* Execute CKOSCSEL bit writing sequence */\r
+ WriteCKOSCSELBit();\r
+ \r
+ /* Check if CKOSCSEL is set to 1 */\r
+ if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) == RESET)\r
+ {\r
+ return ERROR;\r
+ }\r
+ }\r
+ \r
+ /* Select CK_OSC as CK_SYS clock source */\r
+ MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; \r
+ \r
+ if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET)\r
+ {\r
+ if(PLL_State == MRCC_PLL_Disabled)\r
+ {\r
+ /* Disable PLL */\r
+ MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask;\r
+ }\r
+ \r
+ return SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ return ERROR;\r
+ } \r
+ }\r
+ else\r
+ { \r
+ /* CK_RTC disabled */\r
+ return ERROR;\r
+ } \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WriteLPBit\r
+* Description : Executes the Low Power bit writing sequence.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void WriteLPBit(void)\r
+{\r
+ u32 Tmp = 0, Tmp1 = 0, Tmp2 = 0;\r
+\r
+ /* Clear LP_DONE flag */\r
+ MRCC->PWRCTRL &= MRCC_LPDONE_Reset_Mask;\r
+\r
+ Tmp = MRCC->PWRCTRL;\r
+ Tmp1 = Tmp | MRCC_LP_Set_Mask;\r
+ Tmp2 = Tmp & MRCC_LP_Reset_Mask;\r
+\r
+ /* Set LP bit */\r
+ MRCC->PWRCTRL = Tmp1;\r
+\r
+ /* Set LP bit */\r
+ MRCC->PWRCTRL = Tmp1;\r
+\r
+ /* Reset LP bit */\r
+ MRCC->PWRCTRL = Tmp2;\r
+\r
+ /* Set LP bit */\r
+ MRCC->PWRCTRL = Tmp1;\r
+\r
+ /* Read LP bit*/\r
+ Tmp = MRCC->PWRCTRL; \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WriteCKOSCSELBit\r
+* Description : Executes the CKOSCSEL bit writing sequence.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void WriteCKOSCSELBit(void)\r
+{\r
+ u32 Tmp = 0, Tmp1 = 0, Tmp2 = 0;\r
+\r
+ Tmp = MRCC->CLKCTL;\r
+ Tmp1 = Tmp | MRCC_CKOSCSEL_Set_Mask;\r
+ Tmp2 = Tmp & MRCC_CKOSCSEL_Reset_Mask;\r
+\r
+ /* Set CKOSCSEL bit */\r
+ MRCC->CLKCTL = Tmp1;\r
+\r
+ /* Set CKOSCSEL bit */\r
+ MRCC->CLKCTL = Tmp1;\r
+\r
+ /* Reset CKOSCSEL bit */\r
+ MRCC->CLKCTL = Tmp2;\r
+\r
+ /* Set CKOSCSEL bit */\r
+ MRCC->CLKCTL = Tmp1;\r
+ \r
+ /* Read CKOSCSEL bit */\r
+ Tmp = MRCC->CLKCTL;\r
+}\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_pwm.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file provides all the PWM software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_pwm.h"\r
+#include "75x_mrcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* PWM interrupt masks */\r
+#define PWM_IT_Clear_Mask 0x7FFF\r
+#define PWM_IT_Enable_Mask 0xEFFF\r
+\r
+/* PWM_CR Masks bit */\r
+#define PWM_CounterMode_Mask 0xFF8F\r
+#define PWM_DBASE_Mask 0x077F\r
+#define PWM_MasterModeSelection_Mask 0xFC7F\r
+\r
+/* PWM Update flag selection Set/Reset value */\r
+#define PWM_UFS_Reset 0xFFFE\r
+#define PWM_UFS_Set 0x0001\r
+\r
+/* PWM Counter value */\r
+#define PWM_COUNTER_Reset 0x0002\r
+#define PWM_COUNTER_Start 0x0004\r
+#define PWM_COUNTER_Stop 0xFFFB\r
+\r
+/* PWM Debug Mode Set/Reset value */\r
+#define PWM_DBGC_Set 0x0400\r
+#define PWM_DBGC_Reset 0xFBFF\r
+\r
+/* PWM Output Compare Polarity Set/Reset value */\r
+#define PWM_OC1P_Set 0x0020\r
+#define PWM_OC1P_Reset 0xFFDF\r
+\r
+#define PWM_OC1NP_Set 0x0080\r
+#define PWM_OC1NP_Reset 0xFF7F\r
+\r
+#define PWM_OC2P_Set 0x2000\r
+#define PWM_OC2P_Reset 0xDFFF\r
+\r
+#define PWM_OC2NP_Set 0x8000\r
+#define PWM_OC2NP_Reset 0x7FFF\r
+\r
+#define PWM_OC3P_Set 0x0020\r
+#define PWM_OC3P_Reset 0xFFDF\r
+\r
+#define PWM_OC3NP_Set 0x0080\r
+#define PWM_OC3NP_Reset 0xFF7F\r
+\r
+/* PWM Output Compare control mode constant */\r
+#define PWM_OCControl_PWM 0x000C\r
+#define PWM_OCControl_OCToggle 0x0006\r
+#define PWM_OCControl_OCInactive 0x0004\r
+#define PWM_OCControl_OCActive 0x0002\r
+#define PWM_OCControl_OCTiming 0x0000\r
+\r
+/* PWM Output Compare mode Enable value */\r
+#define PWM_OC1_Enable 0x0010\r
+#define PWM_OC2_Enable 0x1000\r
+#define PWM_OC3_Enable 0x0010\r
+\r
+#define PWM_OC1_Disable 0xFFEF\r
+#define PWM_OC2_Disable 0xEFFF\r
+#define PWM_OC3_Disable 0xFFEF\r
+\r
+#define PWM_OC1N_Enable 0x0040\r
+#define PWM_OC2N_Enable 0x4000\r
+#define PWM_OC3N_Enable 0x0040\r
+\r
+#define PWM_OC1N_Disable 0xFFBF\r
+#define PWM_OC2N_Disable 0xBFFF\r
+#define PWM_OC3N_Disable 0xFFBF\r
+\r
+/* PWM Output Compare mode Mask value */\r
+#define PWM_OC1C_Mask 0xFFF1\r
+#define PWM_OC2C_Mask 0xF1FF\r
+#define PWM_OC3C_Mask 0xFFF1\r
+\r
+/* PWM Preload bit Set/Reset value */\r
+#define PWM_PLD1_Set 0x0001\r
+#define PWM_PLD2_Set 0x0100\r
+#define PWM_PLD3_Set 0x0001\r
+\r
+/* PWM OCRM Set/Reset value */\r
+#define PWM_OCMR_Set 0x0080\r
+#define PWM_OCMR_Reset 0xFF7F\r
+\r
+/* PWM_DTR bit Masks value */\r
+#define PWM_DTR_Mask 0xFC00\r
+#define PWM_LOCK_Mask 0xF3FF\r
+\r
+/* PWM MOE Set value */\r
+#define PWM_MOE_Set 0x8000\r
+#define PWM_MOE_Reset 0x7FFF\r
+\r
+/* PWM OSSR bit Set/Reset value */\r
+#define PWM_OSSR_Set 0x4000\r
+#define PWM_OSSR_Reset 0xBFFF\r
+\r
+/* Reset Register Masks */\r
+#define PWM_Prescaler_Reset_Mask 0x0000\r
+#define PWM_Pulse1_Reset_Mask 0x0000\r
+#define PWM_Pulse2_Reset_Mask 0x0000\r
+#define PWM_Pulse3_Reset_Mask 0x0000\r
+#define PWM_Period_Reset_Mask 0xFFFF\r
+#define PWM_RepetitionCounter_Reset_Mask 0x0000\r
+#define PWM_DeadTime_Reset_Mask 0x0000\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void OCM_ModuleConfig(PWM_InitTypeDef* PWM_InitStruct);\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/******************************************************************************\r
+* Function Name : PWM_DeInit\r
+* Description : Deinitializes PWM peripheral registers to their default reset\r
+* values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_DeInit(void)\r
+{\r
+ /* Enters and exits the PWM peripheral to and from reset */\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_PWM,ENABLE);\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_PWM,DISABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_Init\r
+* Description : Initializes the PWM peripheral according to the specified\r
+* parameters in the PWM_InitStruct .\r
+* Input : PWM_InitStruct: pointer to a PWM_InitTypeDef structure that\r
+* contains the configuration information for the PWM peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_Init(PWM_InitTypeDef* PWM_InitStruct)\r
+{\r
+ /* Sets the prescaler value */\r
+ PWM->PSC = PWM_InitStruct->PWM_Prescaler;\r
+\r
+ /* Selects the counter mode */\r
+ PWM->CR &= PWM_CounterMode_Mask;\r
+ PWM->CR |= PWM_InitStruct->PWM_CounterMode;\r
+\r
+ /* Sets the period value */\r
+ PWM->ARR = PWM_InitStruct->PWM_Period;\r
+ \r
+ /* Sets the repetition counter */\r
+ PWM->RCR &= PWM_RepetitionCounter_Reset_Mask;\r
+ PWM->RCR |= PWM_InitStruct->PWM_RepetitionCounter;\r
+ \r
+ /* Configures the PWM according to the PWM_InitTypeDef structure parameters */\r
+ OCM_ModuleConfig(PWM_InitStruct);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_StructInit\r
+* Description : Fills each PWM_InitStruct member with its default value.\r
+* Input : PWM_InitStruct : pointer to a PWM_InitTypeDef structure which\r
+* will be initialized.\r
+* Output : None \r
+* Return : None.\r
+*******************************************************************************/\r
+void PWM_StructInit(PWM_InitTypeDef *PWM_InitStruct)\r
+{\r
+ /* Sets the default configuration */\r
+ PWM_InitStruct->PWM_Mode = PWM_Mode_OCTiming;\r
+ PWM_InitStruct->PWM_Prescaler = PWM_Prescaler_Reset_Mask;\r
+ PWM_InitStruct->PWM_CounterMode = PWM_CounterMode_Up;\r
+ PWM_InitStruct->PWM_Period = PWM_Period_Reset_Mask;\r
+ PWM_InitStruct->PWM_Complementary = PWM_Complementary_Disable;\r
+ PWM_InitStruct->PWM_OCState = PWM_OCState_Disable;\r
+ PWM_InitStruct->PWM_OCNState = PWM_OCNState_Disable;\r
+ PWM_InitStruct->PWM_Channel = PWM_Channel_1;\r
+ PWM_InitStruct->PWM_Pulse1 = PWM_Pulse1_Reset_Mask;\r
+ PWM_InitStruct->PWM_Pulse2 = PWM_Pulse2_Reset_Mask;\r
+ PWM_InitStruct->PWM_Pulse3 = PWM_Pulse3_Reset_Mask;\r
+ PWM_InitStruct->PWM_Polarity1 = PWM_Polarity1_High;\r
+ PWM_InitStruct->PWM_Polarity2 = PWM_Polarity2_High;\r
+ PWM_InitStruct->PWM_Polarity3 = PWM_Polarity3_High;\r
+ PWM_InitStruct->PWM_Polarity1N = PWM_Polarity1N_High;\r
+ PWM_InitStruct->PWM_Polarity2N = PWM_Polarity2N_High;\r
+ PWM_InitStruct->PWM_Polarity3N = PWM_Polarity3N_High;\r
+ PWM_InitStruct->PWM_DTRAccess = PWM_DTRAccess_Disable;\r
+ PWM_InitStruct->PWM_DeadTime = PWM_DeadTime_Reset_Mask;\r
+ PWM_InitStruct->PWM_Emergency = PWM_Emergency_Disable;\r
+ PWM_InitStruct->PWM_LOCKLevel = PWM_LOCKLevel_OFF;\r
+ PWM_InitStruct->PWM_OSSIState = PWM_OSSIState_Disable;\r
+ PWM_InitStruct->PWM_RepetitionCounter = PWM_RepetitionCounter_Reset_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_Cmd\r
+* Description : Enables or disables the PWM peripheral.\r
+* Input : Newstate: new state of the PWM peripheral.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_Cmd(FunctionalState Newstate)\r
+{\r
+ if(Newstate == ENABLE)\r
+ {\r
+ PWM->CR |= PWM_COUNTER_Start;\r
+ }\r
+ else\r
+ {\r
+ PWM->CR &= PWM_COUNTER_Stop;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_CtrlPWMOutputs\r
+* Description : Enables or disables PWM peripheral Main Outputs.\r
+* Input : Newstate: new state of the PWM peripheral Main Outputs. \r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_CtrlPWMOutputs(FunctionalState Newstate)\r
+{\r
+ if(Newstate == ENABLE)\r
+ {\r
+ PWM->DTR |= PWM_MOE_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->DTR &= PWM_MOE_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_ITConfig\r
+* Description : Enables or disables the PWM interrupts.\r
+* Input : - PWM_IT: specifies the PWM interrupts sources to be enabled\r
+* or disabled.\r
+* This parameter can be any combination of the following values:\r
+* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source\r
+* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source\r
+* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source\r
+* - PWM_IT_Update: PWM update Interrupt source\r
+* - PWM_IT_Emergency: PWM Emergency interrupt source\r
+* - PWM_IT_GlobalUpdate: PWM global update Interrupt\r
+* source\r
+* - Newstate: new state of PWM interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_ITConfig(u16 PWM_IT, FunctionalState Newstate)\r
+{ \r
+ u16 PWM_IT_Enable = 0;\r
+\r
+ PWM_IT_Enable = PWM_IT & PWM_IT_Enable_Mask;\r
+\r
+ if(Newstate == ENABLE)\r
+ {\r
+ /* Update interrupt global source: overflow/undeflow, counter reset operation\r
+ or slave mode controller in reset mode */\r
+ if ((PWM_IT & PWM_IT_GlobalUpdate) == PWM_IT_GlobalUpdate)\r
+ {\r
+ PWM->CR &= PWM_UFS_Reset;\r
+ }\r
+ /* Update interrupt source: counter overflow/underflow */\r
+ else if ((PWM_IT & PWM_IT_Update) == PWM_IT_Update)\r
+ {\r
+ PWM->CR |= PWM_UFS_Set;\r
+ }\r
+ /* Select and enable the interrupts requests */\r
+ PWM->RSR |= PWM_IT_Enable;\r
+ PWM->RER |= PWM_IT_Enable;\r
+ }\r
+ /* Disable the interrupts requests */\r
+ else\r
+ {\r
+ PWM->RSR &= ~PWM_IT_Enable;\r
+ PWM->RER &= ~PWM_IT_Enable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_DMAConfig\r
+* Description : Configures the PWM\92s DMA interface.\r
+* Input : - PWM_DMASources: specifies the DMA Request sources.\r
+* This parameter can be any combination of the following values:\r
+* - PWM_DMASource_OC1: PWM Output Compare 1 DMA source\r
+* - PWM_DMASource_OC2: PWM Output Compare 2 DMA source\r
+* - PWM_DMASource_OC3: PWM Output Compare 3 DMA source\r
+* - PWM_DMASource_Update: PWM Update DMA source\r
+* - PWM_OCRMState: the state of output compare request mode.\r
+* This parameter can be one of the following values:\r
+* - PWM_OCRMState_Enable \r
+* - PWM_OCRMState_Disable \r
+* - PWM_DMABase:DMA Base address.\r
+* This parameter can be one of the following values:\r
+* PWM_DMABase_CR, PWM_DMABase_SCR, PWM_DMABase_OMR1, \r
+* PWM_DMABase_OMR2, PWM_DMABase_RSR, PWM_DMABase_RER, \r
+* PWM_DMABase_ISR, PWM_DMABase_CNT, PWM_DMABase_PSC,\r
+* PWM_DMABase_RCR, PWM_DMABase_ARR, PWM_DMABase_OCR1,\r
+* PWM_DMABase_OCR2, PWM_DMABase_OCR3 ,PWM_DMABase_DTR.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_DMAConfig(u16 PWM_DMASources, u16 PWM_OCRMState, u16 PWM_DMABase)\r
+{\r
+ /* Select the DMA requests */\r
+ PWM->RSR &= ~PWM_DMASources;\r
+ \r
+ /* Sets the OCRM state */\r
+ if(PWM_OCRMState == PWM_OCRMState_Enable)\r
+ {\r
+ PWM->RSR |= PWM_OCMR_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->RSR &= PWM_OCMR_Reset;\r
+ }\r
+\r
+ /* Sets the DMA Base address */\r
+ PWM->CR &= PWM_DBASE_Mask;\r
+ PWM->CR |= PWM_DMABase;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_DMACmd\r
+* Description : Enables or disables the PWM\92s DMA interface.\r
+* Input : - PWM_DMASources: specifies the DMA Request sources.\r
+* This parameter can be any combination of the following values:\r
+* - PWM_DMASource_OC1: PWM Output Compare 1 DMA source\r
+* - PWM_DMASource_OC2: PWM Output Compare 2 DMA source\r
+* - PWM_DMASource_OC3: PWM Output Compare 3 DMA source\r
+* - PWM_DMASource_Update: PWM Update DMA source\r
+* - Newstate: new state of the DMA Request sources.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_DMACmd(u16 PWM_DMASources, FunctionalState Newstate)\r
+{\r
+ if(Newstate == ENABLE)\r
+ {\r
+ PWM->RER |= PWM_DMASources;\r
+ }\r
+ else\r
+ {\r
+ PWM->RER &= ~PWM_DMASources;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_SetPrescaler\r
+* Description : Sets the PWM prescaler value.\r
+* Input : Prescaler: PWM prescaler new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_SetPrescaler(u16 Prescaler)\r
+{\r
+ PWM->PSC = Prescaler;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_SetPeriod\r
+* Description : Sets the PWM period value.\r
+* Input : Period: PWM period new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_SetPeriod(u16 Period)\r
+{\r
+ PWM->ARR = Period;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_SetPulse\r
+* Description : Sets the PWM pulse value.\r
+* Input : - PWM_Channel: specifies the PWM channel to be used.\r
+* This parameter can be one of the following values:\r
+* - PWM_Channel_1: PWM Channel 1 is used\r
+* - PWM_Channel_2: PWM Channel 2 is used\r
+* - PWM_Channel_3: PWM Channel 3 is used\r
+* - PWM_Channel_ALL: PWM Channel 1, Channel 2 and 3 are used\r
+* - Pulse: PWM pulse new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_SetPulse(u16 PWM_Channel, u16 Pulse)\r
+{\r
+ /* Sets Channel 1 pulse value */\r
+ if(PWM_Channel == PWM_Channel_1)\r
+ {\r
+ PWM->OCR1 = Pulse;\r
+ }\r
+ /* Sets Channel 2 pulse value */\r
+ else if(PWM_Channel == PWM_Channel_2)\r
+ {\r
+ PWM->OCR2 = Pulse;\r
+ }\r
+ /* Sets Channel 3 pulse value */\r
+ else if(PWM_Channel == PWM_Channel_3)\r
+ {\r
+ PWM->OCR3 = Pulse;\r
+ }\r
+ /* Sets Channel 1, Channel 2 and Channel 3 pulse values */\r
+ else if(PWM_Channel == PWM_Channel_ALL)\r
+ {\r
+ PWM->OCR1 = Pulse;\r
+ PWM->OCR2 = Pulse;\r
+ PWM->OCR3 = Pulse;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_SetPulse1\r
+* Description : Sets the PWM Channel 1 pulse value.\r
+* Input : - Pulse: PWM Channel 1 pulse new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_SetPulse1(u16 Pulse)\r
+{\r
+ PWM->OCR1 = Pulse;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_SetPulse2\r
+* Description : Sets the PWM Channel 2 pulse value.\r
+* Input : - Pulse: PWM Channel 2 pulse new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_SetPulse2(u16 Pulse)\r
+{\r
+ PWM->OCR2 = Pulse;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_SetPulse3\r
+* Description : Sets the PWM Channel 3 pulse value.\r
+* Input : - Pulse: PWM Channel 3 pulse new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_SetPulse3(u16 Pulse)\r
+{\r
+ PWM->OCR3 = Pulse;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_DebugCmd\r
+* Description : Enables or disables PWM peripheral Debug control.\r
+* Input : Newstate: new state of the PWM Debug control.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_DebugCmd(FunctionalState Newstate)\r
+{\r
+ if(Newstate == ENABLE)\r
+ {\r
+ PWM->CR |= PWM_DBGC_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->CR &= PWM_DBGC_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_CounterModeConfig\r
+* Description : Specifies the Counter Mode to be used.\r
+* Input : PWM_CounterMode: specifies the Counter Mode to be used\r
+* This parameter can be one of the following values:\r
+* - PWM_CounterMode_Up: PWM Up Counting Mode\r
+* - PWM_CounterMode_Down: PWM Down Counting Mode\r
+* - PWM_CounterMode_CenterAligned1: PWM Center Aligned1 Mode\r
+* - PWM_CounterMode_CenterAligned2: PWM Center Aligned2 Mode\r
+* - PWM_CounterMode_CenterAligned3: PWM Center Aligned3 Mode\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_CounterModeConfig(u16 PWM_CounterMode)\r
+{\r
+ /* Counter mode configuration */\r
+ PWM->CR &= PWM_CounterMode_Mask;\r
+ PWM->CR |= PWM_CounterMode;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_ForcedOCConfig\r
+* Description : Forces the PWM output waveform to active or inactive level.\r
+* Input : - PWM_Channel: specifies the PWM channel to be used.\r
+* This parameter can be one of the following values:\r
+* - PWM_Channel_1: PWM Channel 1 is used\r
+* - PWM_Channel_2: PWM Channel 2 is used\r
+* - PWM_Channel_3: PWM Channel 3 is used\r
+* - PWM_Channel_ALL: PWM Channel 1, Channel 2 and 3 are used\r
+* - PWM_ForcedAction: specifies the forced Action to be set to the\r
+* output waveform.\r
+* This parameter can be one of the following values:\r
+* - PWM_ForcedAction_Active: Force active level on OCxREF\r
+* - PWM_ForcedAction_InActive: Force inactive level on \r
+* OCxREF\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_ForcedOCConfig(u16 PWM_Channel, u16 PWM_ForcedAction)\r
+{\r
+ /* Channel 1 Forced Output Compare mode configuration */\r
+ if(PWM_Channel == PWM_Channel_1)\r
+ {\r
+ PWM->OMR1 &= PWM_OC1C_Mask;\r
+ PWM->OMR1 |= PWM_ForcedAction;\r
+ }\r
+ /* Channel 2 Forced Output Compare mode configuration */\r
+ else\r
+ {\r
+ if(PWM_Channel == PWM_Channel_2)\r
+ {\r
+ PWM->OMR1 &= PWM_OC2C_Mask;\r
+ PWM->OMR1 |= (PWM_ForcedAction<<8);\r
+ }\r
+ else\r
+ {\r
+ /* Channel 3 Forced Output Compare mode configuration */\r
+ if(PWM_Channel == PWM_Channel_3)\r
+ {\r
+ PWM->OMR2 &= PWM_OC3C_Mask;\r
+ PWM->OMR2 |= PWM_ForcedAction;\r
+ }\r
+ /* Channel 1, Channel 2 and Channel 3 Forced Output Compare mode \r
+ configuration */\r
+ else\r
+ {\r
+ PWM->OMR1 &= PWM_OC1C_Mask;\r
+ PWM->OMR1 |= PWM_ForcedAction;\r
+\r
+ PWM->OMR1 &= PWM_OC2C_Mask;\r
+ PWM->OMR1 |= (PWM_ForcedAction<<8);\r
+ \r
+ PWM->OMR2 &= PWM_OC3C_Mask;\r
+ PWM->OMR2 |= PWM_ForcedAction;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_SetDeadTime\r
+* Description : Inserts dead time between the OCx and OCNx.\r
+* Input : DeadTime: PWM Dead Time value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_SetDeadTime(u16 DeadTime)\r
+{\r
+ /* Sets the dead time value */\r
+ PWM->DTR &= PWM_DTR_Mask;\r
+ PWM->DTR |= DeadTime;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_ResetCounter\r
+* Description : Re-intializes the PWM counter and generates an update of the\r
+* registers.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_ResetCounter(void)\r
+{\r
+ /* Resets the PWM counter */\r
+ PWM->CR |= PWM_COUNTER_Reset;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_TRGOSelection\r
+* Description : Sets the PWM Master Mode selection bits.\r
+* Input : PWM_TRGOMode: specifies the TRGO source.\r
+* This parameter can be one of the following values:\r
+* - PWM_TRGOMode_Enable: The CNT_EN bit is used as TRGO\r
+* - PWM_TRGOMode_Update: The Update event is used as TRGO\r
+* - PWM_TRGOMode_Reset: The CNT_RST bit is used as TRGO\r
+* - PWM_TRGOMode_OC: The OC1 signal is used as TRGO\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_TRGOSelection(u16 PWM_TRGOMode)\r
+{\r
+ /* Sets the synchronization action */\r
+ PWM->CR &= PWM_MasterModeSelection_Mask;\r
+ PWM->CR |= PWM_TRGOMode;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_GetFlagStatus\r
+* Description : Checks whether the specified PWM flag is set or not.\r
+* Input : PWM_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - PWM_FLAG_OC1: Output Compare 1 Flag\r
+* - PWM_FLAG_OC2: Output Compare 2 Flag\r
+* - PWM_FLAG_OC3: Output Compare 3 Flag\r
+* - PWM_FLAG_Update: PWM update Flag\r
+* - PWM_FLAG_Emergency: PWM Emergency Flag\r
+* Output : None\r
+* Return : The new state of the PWM_FLAG(SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus PWM_GetFlagStatus(u16 PWM_FLAG)\r
+{\r
+ if((PWM->ISR & PWM_FLAG) != RESET )\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_ClearFlag\r
+* Description : Clears the PWM\92s pending flags. \r
+* Input : PWM_FLAG: specifies the flag to clear. \r
+* This parameter can be any combination of the following values:\r
+* - PWM_FLAG_OC1: Output Compare 1 flag\r
+* - PWM_FLAG_OC2: Output Compare 2 flag\r
+* - PWM_FLAG_OC3: Output Compare 3 flag\r
+* - PWM_FLAG_Update: PWM update flag\r
+* - PWM_FLAG_Emergency: PWM Emergency flag\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_ClearFlag(u16 PWM_FLAG)\r
+{\r
+ /* Clears the flags */\r
+ PWM->ISR &= ~PWM_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_GetITStatus\r
+* Description : Checks whether the PWM interrupt has occurred or not.\r
+* Input : PWM_IT: specifies the PWM interrupt source to check. \r
+* This parameter can be one of the following values:\r
+* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source\r
+* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source\r
+* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source\r
+* - PWM_IT_Update: PWM update Interrupt source\r
+* - PWM_IT_Emergency: PWM Emergency interrupt source\r
+* - PWM_IT_GlobalUpdate: PWM global update Interrupt\r
+* source\r
+* Output : None\r
+* Return : The new state of the PWM_IT(SET or RESET).\r
+*******************************************************************************/\r
+ITStatus PWM_GetITStatus(u16 PWM_IT)\r
+{\r
+ u16 PWM_IT_Check = 0;\r
+\r
+ /* Calculates the pending bits to be checked */\r
+ PWM_IT_Check = PWM_IT & PWM_IT_Clear_Mask;\r
+ \r
+ if((PWM->ISR & PWM_IT_Check) != RESET )\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWM_ClearITPendingBit\r
+* Description : Clears the PWM's interrupt pending bits.\r
+* Input : PWM_IT: specifies the pending bit to clear.\r
+* This parameter can be any combination of the following values:\r
+* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source\r
+* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source\r
+* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source\r
+* - PWM_IT_Update: PWM update Interrupt source\r
+* - PWM_IT_Emergency: PWM Emergency interrupt source\r
+* - PWM_IT_GlobalUpdate: PWM global update Interrupt\r
+* source\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWM_ClearITPendingBit(u16 PWM_IT)\r
+{\r
+ u16 PWM_IT_Clear = 0;\r
+\r
+ /* Calculates the pending bits to be cleared */\r
+ PWM_IT_Clear = PWM_IT & PWM_IT_Clear_Mask;\r
+\r
+ /* Clears the pending bits */\r
+ PWM->ISR &= ~PWM_IT_Clear;\r
+ \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : OCM_ModuleConfig\r
+* Description : Output Compare Module configuration.\r
+* Input : PWM_InitStruct: pointer to a PWM_InitTypeDef structure that\r
+* contains the configuration information for the PWM peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void OCM_ModuleConfig(PWM_InitTypeDef* PWM_InitStruct)\r
+{\r
+ u16 PWM_OCControl = 0x0000;\r
+ u16 DTR_REG = 0x0000;\r
+ \r
+ if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCTiming)\r
+ {\r
+ PWM_OCControl = PWM_OCControl_OCTiming;\r
+ }\r
+ else\r
+ {\r
+ if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCActive)\r
+ {\r
+ PWM_OCControl = PWM_OCControl_OCActive;\r
+ }\r
+ else\r
+ {\r
+ if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCInactive)\r
+ {\r
+ PWM_OCControl = PWM_OCControl_OCInactive;\r
+ }\r
+ else\r
+ {\r
+ if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCToggle)\r
+ {\r
+ PWM_OCControl = PWM_OCControl_OCToggle;\r
+ }\r
+ else\r
+ {\r
+ PWM_OCControl = PWM_OCControl_PWM;\r
+\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Read DTR register */\r
+ DTR_REG = PWM->DTR & 0x8000;\r
+\r
+/*Channel 1 Configuration-----------------------------------------------------*/\r
+ if(PWM_InitStruct->PWM_Channel == PWM_Channel_1)\r
+ {\r
+ /* PWM Output Complementary Configuration */\r
+ if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable)\r
+ {\r
+ /* Configures Channel 1 on Output Compare mode */\r
+ PWM->OMR1 &= PWM_OC1C_Mask;\r
+ PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable|PWM_OC1N_Enable|PWM_PLD1_Set;\r
+ PWM->OCR1 = PWM_InitStruct->PWM_Pulse1;\r
+ \r
+ /* Sets the OC1 wave polarity */\r
+ if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low)\r
+ {\r
+ PWM->OMR1 |= PWM_OC1P_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR1 &= PWM_OC1P_Reset;\r
+ }\r
+\r
+ /* Sets the OC1N wave polarity */\r
+ if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low)\r
+ {\r
+ PWM->OMR1 |= PWM_OC1NP_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR1 &= PWM_OC1NP_Reset;\r
+ }\r
+ }/* End complementary case */\r
+ /* Single PWM Output configuratuion */\r
+ else\r
+ {\r
+ switch(PWM_InitStruct->PWM_OCState)\r
+ {\r
+ case PWM_OCState_Enable:\r
+ {\r
+ /* Configures Channel 1 on Output Compare mode */\r
+ PWM->OMR1 &= PWM_OC1C_Mask;\r
+ PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable;\r
+ PWM->OMR1 |= PWM_PLD1_Set;\r
+ PWM->OCR1 = PWM_InitStruct->PWM_Pulse1;\r
+\r
+ /* Sets the OC1 wave polarity */\r
+ if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low)\r
+ {\r
+ PWM->OMR1 |= PWM_OC1P_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR1 &= PWM_OC1P_Reset;\r
+ }\r
+ }\r
+ break;\r
+ case PWM_OCState_Disable:\r
+ {\r
+ /* OC1E = 0 and OSSR = 0 sets the polarity */\r
+ PWM->OMR1 &= PWM_OC1_Disable;\r
+ DTR_REG &= PWM_OSSR_Reset;\r
+ }\r
+ break;\r
+ case PWM_OCState_OffState:\r
+ {\r
+ /* OC1E = 0 and OSSR = 1 and sets the polarity */\r
+ PWM->OMR1 &= PWM_OC1_Disable;\r
+ DTR_REG |= PWM_OSSR_Set;\r
+ \r
+ /* Sets the OC1 wave polarity */\r
+ if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low)\r
+ {\r
+ PWM->OMR1 |= PWM_OC1P_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR1 &= PWM_OC1P_Reset;\r
+ }\r
+ }\r
+ break;\r
+ }\r
+\r
+ switch(PWM_InitStruct->PWM_OCNState)\r
+ {\r
+ case PWM_OCNState_Enable:\r
+ {\r
+ /* Configures Channel 1N on Output Compare mode */\r
+ PWM->OMR1 &= PWM_OC1C_Mask;\r
+ PWM->OMR1 |= PWM_OCControl |PWM_OC1N_Enable |PWM_PLD1_Set; \r
+ PWM->OCR1 = PWM_InitStruct->PWM_Pulse1;\r
+\r
+ /* Sets the OC1N wave polarity */\r
+ if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low)\r
+ {\r
+ PWM->OMR1 |= PWM_OC1NP_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR1 &= PWM_OC1NP_Reset;\r
+ }\r
+ }\r
+ break;\r
+ case PWM_OCNState_Disable:\r
+ {\r
+ /* OC1N = 0 OSSR = 0 */\r
+ PWM->OMR1 &= PWM_OC1N_Disable;\r
+ DTR_REG &= PWM_OSSR_Reset;\r
+ }\r
+ break;\r
+ case PWM_OCNState_OffState:\r
+ {\r
+ /* OC1N = 0 OSSR = 1 and sets the polarity */\r
+ PWM->OMR1 &= PWM_OC1N_Disable;\r
+ DTR_REG |= PWM_OSSR_Set;\r
+\r
+ if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low)\r
+ {\r
+ PWM->OMR1 |= PWM_OC1NP_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR1 &= PWM_OC1NP_Reset;\r
+ }\r
+ }\r
+ break;\r
+ } \r
+ } /* End not complementary case */\r
+ }/* end channel 1 */\r
+\r
+/*Channel 2 Configuration-----------------------------------------------------*/\r
+ if(PWM_InitStruct->PWM_Channel == PWM_Channel_2)\r
+ {\r
+ /* PWM Output Complementary Configuration */\r
+ if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable)\r
+ {\r
+ /* Configures Channel 2 on Output Compare mode */\r
+ PWM->OMR1 &= PWM_OC2C_Mask;\r
+ PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_OC2N_Enable|PWM_PLD2_Set;\r
+ PWM->OCR2 = PWM_InitStruct->PWM_Pulse2;\r
+\r
+ /* Set the OC2 wave polarity */\r
+ if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low)\r
+ {\r
+ PWM->OMR1 |= PWM_OC2P_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR1 &= PWM_OC2P_Reset;\r
+ }\r
+\r
+ /* Sets the OC2N wave polarity */\r
+ if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low)\r
+ {\r
+ PWM->OMR1 |= PWM_OC2NP_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR1 &= PWM_OC2NP_Reset;\r
+ }\r
+\r
+ }/* End complentary case */\r
+ else\r
+ /* Single PWM Output configuratuion */\r
+ {\r
+ switch(PWM_InitStruct->PWM_OCState)\r
+ {\r
+ case PWM_OCState_Enable:\r
+ {\r
+ /* Configures Channel 2 on Output Compare mode */\r
+ PWM->OMR1 &= PWM_OC2C_Mask;\r
+ PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_PLD2_Set;\r
+ PWM->OCR2 = PWM_InitStruct->PWM_Pulse2;\r
+\r
+ /* Sets the OC2 wave polarity */\r
+ if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low)\r
+ {\r
+ PWM->OMR1 |= PWM_OC2P_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR1 &= PWM_OC2P_Reset;\r
+ }\r
+ }\r
+ break;\r
+ case PWM_OCState_Disable:\r
+ {\r
+ /* OC2E = 0 and OSSR = 0 */\r
+ PWM->OMR1 &= PWM_OC2_Disable;\r
+ DTR_REG &= PWM_OSSR_Reset;\r
+ }\r
+ break;\r
+ case PWM_OCState_OffState:\r
+ {\r
+ /* OC2E = 0 and OSSR = 1 sets the polarity */\r
+ PWM->OMR1 &= PWM_OC2_Disable;\r
+ DTR_REG |= PWM_OSSR_Set;\r
+ \r
+ /* Sets the OC2 wave polarity */\r
+ if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low)\r
+ {\r
+ PWM->OMR1 |= PWM_OC2P_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR1 &= PWM_OC2P_Reset;\r
+ }\r
+ }\r
+ break;\r
+ }\r
+ switch(PWM_InitStruct->PWM_OCNState)\r
+ {\r
+ case PWM_OCNState_Enable:\r
+ {\r
+ /* Configures Channel 2N on Output Compare mode */\r
+ PWM->OMR1 &= PWM_OC2C_Mask;\r
+ PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2N_Enable|PWM_PLD2_Set;\r
+ PWM->OCR2 = PWM_InitStruct->PWM_Pulse2;\r
+\r
+ /* Sets the OC2 wave polarity */\r
+ if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low)\r
+ {\r
+ PWM->OMR1 |= PWM_OC2NP_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR1 &= PWM_OC2NP_Reset;\r
+ }\r
+ }\r
+ break;\r
+ case PWM_OCNState_Disable:\r
+ {\r
+ /* OC2N = 0 OSSR = 0 */\r
+ PWM->OMR1 &= PWM_OC2N_Disable;\r
+ DTR_REG &= PWM_OSSR_Reset;\r
+ }\r
+ break;\r
+ case PWM_OCNState_OffState:\r
+ {\r
+ /* OC2N = 0 OSSR = 1 and sets the polarity */\r
+ PWM->OMR1 &= PWM_OC2N_Disable;\r
+ DTR_REG |= PWM_OSSR_Set;\r
+ \r
+ if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low)\r
+ {\r
+ PWM->OMR1 |= PWM_OC2NP_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR1 &= PWM_OC2NP_Reset;\r
+ }\r
+ }\r
+ break;\r
+ }\r
+ } /* End not complementary case */\r
+ }/* end channel 2 */\r
+\r
+/*Channel 3 Configuration-----------------------------------------------------*/\r
+ if(PWM_InitStruct->PWM_Channel == PWM_Channel_3)\r
+ {\r
+ /* PWM Output Complementary Configuration */\r
+ if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable)\r
+ {\r
+ /* Configures Channel 3 on Output Compare mode */\r
+ PWM->OMR2 &= PWM_OC3C_Mask;\r
+ PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_OC3N_Enable|PWM_PLD3_Set;\r
+ PWM->OCR3 = PWM_InitStruct->PWM_Pulse3;\r
+\r
+ /* Sets the OC3 wave polarity */\r
+ if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low)\r
+ {\r
+ PWM->OMR2 |= PWM_OC3P_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR2 &= PWM_OC3P_Reset;\r
+ }\r
+\r
+ /* Sets the OC3N wave polarity */\r
+ if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low)\r
+ {\r
+ PWM->OMR2 |= PWM_OC3NP_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR2 &= PWM_OC3NP_Reset;\r
+ }\r
+ }/* End complementary case */\r
+ else\r
+ /* Single PWM Output configuratuion */\r
+ {\r
+ switch(PWM_InitStruct->PWM_OCState)\r
+ {\r
+ case PWM_OCState_Enable:\r
+ {\r
+ /* Configures Channel 3 on Output Compare mode */\r
+ PWM->OMR2 &= PWM_OC3C_Mask;\r
+ PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_PLD3_Set;\r
+ PWM->OCR3 = PWM_InitStruct->PWM_Pulse3;\r
+\r
+ /* Sets the OCC wave polarity */\r
+ if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low)\r
+ {\r
+ PWM->OMR2 |= PWM_OC3P_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR2 &= PWM_OC3P_Reset;\r
+ }\r
+ }\r
+ break;\r
+ case PWM_OCState_Disable:\r
+ {\r
+ /* OC3E = 0 and OSSR = 0 */\r
+ PWM->OMR2 &= PWM_OC3_Disable;\r
+ DTR_REG &= PWM_OSSR_Reset;\r
+ }\r
+ break;\r
+ case PWM_OCState_OffState:\r
+ {\r
+ /* OC3E = 0 and OSSR = 1 sets the polarity */\r
+ PWM->OMR2 &= PWM_OC3_Disable;\r
+ DTR_REG |= PWM_OSSR_Set;\r
+\r
+ if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low)\r
+ {\r
+ PWM->OMR2 |= PWM_OC3P_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR2 &= PWM_OC3P_Reset;\r
+ }\r
+ }\r
+ break;\r
+ }\r
+\r
+ switch(PWM_InitStruct->PWM_OCNState)\r
+ {\r
+ case PWM_OCNState_Enable:\r
+ {\r
+ /* Configures Channel 3N on Output Compare mode */\r
+ PWM->OMR2 &= PWM_OC3C_Mask;\r
+ PWM->OMR2 |= PWM_OCControl |PWM_OC3N_Enable|PWM_PLD3_Set;\r
+ PWM->OCR3 = PWM_InitStruct->PWM_Pulse3;\r
+\r
+ /* Sets the OC3 wave polarity */\r
+ if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low)\r
+ {\r
+ PWM->OMR2 |= PWM_OC3NP_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR2 &= PWM_OC3NP_Reset;\r
+ }\r
+ }\r
+ break;\r
+ case PWM_OCNState_Disable:\r
+ {\r
+ /* OC3N = 0 OSSR = 0 */\r
+ PWM->OMR2 &= PWM_OC3N_Disable;\r
+ DTR_REG &= PWM_OSSR_Reset;\r
+ }\r
+ break;\r
+ case PWM_OCNState_OffState:\r
+ {\r
+ /* OC3N = 0 OSSR = 1 and sets the polarity */\r
+ PWM->OMR2 &= PWM_OC3N_Disable;\r
+ DTR_REG |= PWM_OSSR_Set;\r
+\r
+ if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low)\r
+ {\r
+ PWM->OMR2 |= PWM_OC3NP_Set;\r
+ }\r
+ else\r
+ {\r
+ PWM->OMR2 &= PWM_OC3NP_Reset;\r
+ }\r
+ }\r
+ break;\r
+ }\r
+ } /* End not complementary case */\r
+ }/* end channel 3 */\r
+\r
+ if(PWM_InitStruct->PWM_DTRAccess == PWM_DTRAccess_Enable)\r
+ {\r
+ DTR_REG |= PWM_InitStruct->PWM_LOCKLevel | PWM_InitStruct->PWM_Emergency |\r
+ PWM_InitStruct->PWM_DeadTime | PWM_InitStruct->PWM_OSSIState;\r
+ PWM->DTR = DTR_REG;\r
+ } \r
+}\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_rtc.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file provides all the RTC software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_rtc.h"\r
+#include "75x_mrcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define RTC_CNF_Enable_Mask 0x0010 /* Configuration Flag Enable Mask */\r
+#define RTC_CNF_Disable_Mask 0xFFEF /* Configuration Flag Disable Mask */\r
+#define RTC_LSB_Mask 0x0000FFFF /* RTC LSB Mask */\r
+#define RTC_MSB_Mask 0xFFFF0000 /* RTC MSB Mask */\r
+#define RTC_Prescaler_MSB_Mask 0x000F0000 /* RTC Prescaler MSB Mask */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/*******************************************************************************\r
+* Function Name : RTC_DeInit\r
+* Description : Deinitializes the RTC peripheral registers to their\r
+* default reset values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_DeInit(void)\r
+{\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_RTC,ENABLE);\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_RTC,DISABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_ITConfig\r
+* Description : Enables or disables the specified RTC interrupts.\r
+* Input : - RTC_IT: specifies the RTC interrupts sources to be enabled\r
+* or disabled.\r
+* This parameter can be a combination of one or more of the\r
+* following values:\r
+* - RTC_IT_Overflow: Overflow interrupt\r
+* - RTC_IT_Alarm: Alarm interrupt\r
+* - RTC_IT_Second: Second interrupt\r
+* - NewState: new state of the specified RTC interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ RTC->CRH |= RTC_IT;\r
+ }\r
+ else\r
+ {\r
+ RTC->CRH &= ~RTC_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_EnterConfigMode\r
+* Description : Enters the RTC configuration mode.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_EnterConfigMode(void)\r
+{\r
+ /* Set the CNF flag to enter in the Configuration Mode */\r
+ RTC->CRL |= RTC_CNF_Enable_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_ExitConfigMode\r
+* Description : Exits from the RTC configuration mode.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_ExitConfigMode(void)\r
+{\r
+ /* Reset the CNF flag to exit from the Configuration Mode */\r
+ RTC->CRL &= RTC_CNF_Disable_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_GetCounter\r
+* Description : Gets the RTC counter value.\r
+* Input : None\r
+* Output : None\r
+* Return : RTC counter value.\r
+*******************************************************************************/\r
+u32 RTC_GetCounter(void)\r
+{\r
+ u16 Tmp = 0;\r
+ Tmp = RTC->CNTL;\r
+ \r
+ return (((u32)RTC->CNTH << 16 ) |Tmp) ;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_SetCounter\r
+* Description : Sets the RTC counter value.\r
+* Input : RTC counter new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_SetCounter(u32 CounterValue)\r
+{\r
+ RTC_EnterConfigMode();\r
+ \r
+/* COUNTER Config ------------------------------------------------------------*/\r
+ /* Set RTC COUNTER MSB word */\r
+ RTC->CNTH =(CounterValue & RTC_MSB_Mask) >> 16;\r
+ /* Set RTC COUNTER LSB word */\r
+ RTC->CNTL =(CounterValue & RTC_LSB_Mask);\r
+ \r
+ RTC_ExitConfigMode();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_SetPrescaler\r
+* Description : Sets the RTC prescaler value.\r
+* Input : RTC prescaler new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_SetPrescaler(u32 PrescalerValue)\r
+{\r
+ RTC_EnterConfigMode();\r
+ \r
+/* PRESCALER Config ----------------------------------------------------------*/\r
+ /* Set RTC PRESCALER MSB word */\r
+ RTC->PRLH = (PrescalerValue & RTC_Prescaler_MSB_Mask) >> 16;\r
+ /* Set RTC PRESCALER LSB word */\r
+ RTC->PRLL = (PrescalerValue & RTC_LSB_Mask);\r
+ \r
+ RTC_ExitConfigMode();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_GetPrescaler\r
+* Description : Gets the RTC prescaler value.\r
+* Input : None\r
+* Output : None\r
+* Return : RTC prescaler value.\r
+*******************************************************************************/\r
+u32 RTC_GetPrescaler(void)\r
+{\r
+ u16 Tmp = 0;\r
+ Tmp = RTC->PRLL;\r
+ \r
+ return (((u32)(RTC->PRLH & 0x000F) << 16 ) | Tmp);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_SetAlarm\r
+* Description : Sets the RTC alarm value.\r
+* Input : RTC alarm new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_SetAlarm(u32 AlarmValue)\r
+{\r
+ RTC_EnterConfigMode();\r
+ \r
+/* ALARM Config --------------------------------------------------------------*/\r
+ /* Set the ALARM MSB word */\r
+ RTC->ALRH = (AlarmValue & RTC_MSB_Mask) >> 16;\r
+ /* Set the ALARM LSB word */\r
+ RTC->ALRL = (AlarmValue & RTC_LSB_Mask);\r
+ \r
+ RTC_ExitConfigMode();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_GetDivider\r
+* Description : Gets the RTC divider value.\r
+* Input : None\r
+* Output : None\r
+* Return : RTC Divider value.\r
+*******************************************************************************/\r
+u32 RTC_GetDivider(void)\r
+{\r
+ u16 Tmp = 0;\r
+ Tmp = RTC->DIVL ;\r
+ return (((u32)(RTC->DIVH & 0x000F) << 16 ) | Tmp);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_WaitForLastTask\r
+* Description : Waits until last write operation on RTC registers has finished.\r
+* This function must be called before any write to RTC registers.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_WaitForLastTask(void)\r
+{\r
+ /* Loop until RTOFF flag is set */\r
+ while ((RTC->CRL & RTC_FLAG_RTOFF) == RESET);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_WaitForSynchro\r
+* Description : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) \r
+* are synchronized with RTC APB clock.\r
+* This function must be called before any read operation after \r
+* an APB reset or an APB clock stop.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_WaitForSynchro(void)\r
+{\r
+ /* Clear RSF flag */\r
+ RTC->CRL &= ~RTC_FLAG_RSF;\r
+ \r
+ /* Loop until RSF flag is set */\r
+ while((RTC->CRL & RTC_FLAG_RSF)== RESET);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_GetFlagStatus\r
+* Description : Checks whether the specified RTC flag is set or not.\r
+* Input : RTC_FLAG: specifies the flag to check.\r
+* This parameter can be one the following values:\r
+* - RTC_FLAG_RTOFF: RTC Operation OFF flag\r
+* - RTC_FLAG_RSF: Registers Synchronized flag\r
+* - RTC_FLAG_Overflow: Overflow interrupt flag\r
+* - RTC_FLAG_Alarm: Alarm interrupt flag\r
+* - RTC_FLAG_Second: Second interrupt flag\r
+* Output : None\r
+* Return : The new state of RTC_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG)\r
+{\r
+ if((RTC->CRL & RTC_FLAG) != RESET)\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_ClearFlag\r
+* Description : Clears the RTC\92s pending flags.\r
+* Input : RTC_FLAG: specifies the flag to clear.\r
+* This parameter can be a combination of one or more of\r
+* the following values:\r
+* - RTC_FLAG_RSF: Registers Synchronized flag. This flag\r
+* is cleared only after an APB reset or an APB Clock stop.\r
+* - RTC_FLAG_Overflow: Overflow interrupt flag\r
+* - RTC_FLAG_Alarm: Alarm interrupt flag\r
+* - RTC_FLAG_Second: Second interrupt flag\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_ClearFlag(u16 RTC_FLAG)\r
+{\r
+ /* Clear the coressponding RTC flag */\r
+ RTC->CRL &= ~RTC_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_GetITStatus\r
+* Description : Checks whether the specified RTC interrupt has occured or not.\r
+* Input : RTC_IT: specifies the RTC interrupts sources to check.\r
+* This parameter can be a combination of one or more of\r
+* the following values:\r
+* - RTC_IT_Overflow: Overflow interrupt\r
+* - RTC_IT_Alarm: Alarm interrupt\r
+* - RTC_IT_Second: Second interrupt\r
+* Output : None\r
+* Return : The new state of the RTC_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus RTC_GetITStatus(u16 RTC_IT)\r
+{\r
+ if(((RTC->CRH & RTC_IT) != RESET)&& ((RTC->CRL & RTC_IT) != RESET))\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_ClearITPendingBit\r
+* Description : Clears the RTC\92s interrupt pending bits.\r
+* Input : RTC_IT: specifies the interrupt pending bit to clear. \r
+* This parameter can be any combination of one or more of\r
+* the following values:\r
+* - RTC_IT_Overflow: Overflow interrupt\r
+* - RTC_IT_Alarm: Alarm interrupt\r
+* - RTC_IT_Second: Second interrupt\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_ClearITPendingBit(u16 RTC_IT)\r
+{\r
+ /* Clear the coressponding RTC pending bit */\r
+ RTC->CRL &= ~RTC_IT;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_smi.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file provides all the SMI software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_smi.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* SMI_CR1 mask bits */\r
+#define SMI_HOLDPRESCTCS_RESET_Mask 0xFF00800F\r
+#define SMI_Prescaler_MaxValue 0x7F\r
+#define SMI_DeselectTime_MaxValue 0x0F\r
+#define SMI_ClockHold_Mask 0x00\r
+#define SMI_Prescaler_Mask 0x02\r
+#define SMI_DeselectTime_Mask 0x5\r
+\r
+/* SMI_CR2 mask bits */\r
+#define SMI_BS_RESET_Mask 0xFFFFCFFF\r
+#define SMI_BS_Bank1_Mask 0x00001000\r
+#define SMI_BS_Bank2_Mask 0x00002000\r
+#define SMI_BS_Bank3_Mask 0x00003000\r
+#define SMI_WEN_Mask 0x00000800\r
+#define SMI_RSR_Mask 0x00000400\r
+#define SMI_SEND_Mask 0x00000080\r
+#define SMI_TRARECLENGTH_RESET_Mask 0xFFFFFF88\r
+\r
+/* SMI_SR mask bits */\r
+#define SMI_STATUSREGISTER_Mask 0xFF\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_DeInit\r
+* Description : Deinitializes the SMI peripheral registers to their default\r
+* reset values. This function must not be used when booting\r
+* from the SMI external memory.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_DeInit(void)\r
+{\r
+ SMI->CR1 = 0x00000250;\r
+ SMI->CR2 = 0x00;\r
+ SMI->SR &= 0xFFFFF0FF;\r
+ SMI->TR = 0x00;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_Init\r
+* Description : Initializes the SMI peripheral according to the specified\r
+* parameters in the SMI_InitStruct.\r
+* Input : - SMI_InitStruct: pointer to a SMI_InitTypeDef structure that\r
+* contains the configuration information for the specified\r
+* SMI peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_Init(SMI_InitTypeDef* SMI_InitStruct)\r
+{\r
+ u32 Temp = 0;\r
+ \r
+ /* Clear HOLD[7:0], PRESC[6:0] and TCS[3:0] bits */\r
+ Temp = SMI->CR1 & SMI_HOLDPRESCTCS_RESET_Mask;\r
+\r
+ /* Set HOLD[7:0] bits according to SMI_ClockHold value */\r
+ Temp |= SMI_InitStruct->SMI_ClockHold << 16;\r
+\r
+ if(SMI_InitStruct->SMI_Prescaler <= SMI_Prescaler_MaxValue)\r
+ {\r
+ /* Set PRESC[6:0] bits according to SMI_Prescaler value */\r
+ Temp |= SMI_InitStruct->SMI_Prescaler << 8;\r
+ }\r
+\r
+ if(SMI_InitStruct->SMI_DeselectTime <= SMI_DeselectTime_MaxValue)\r
+ {\r
+ /* Set TCS[3:0] bits according to SMI_DeselectTime value */\r
+ Temp |= SMI_InitStruct->SMI_DeselectTime << 4;\r
+ }\r
+\r
+ /* Store the new value */\r
+ SMI->CR1 = Temp; \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_StructInit\r
+* Description : Fills each SMI_InitStruct member with its reset value.\r
+* Input : - SMI_InitStruct: pointer to a SMI_InitTypeDef structure which\r
+* will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_StructInit(SMI_InitTypeDef* SMI_InitStruct)\r
+{\r
+ /* SMI_CK is sent continuously */\r
+ SMI_InitStruct->SMI_ClockHold = SMI_ClockHold_Mask;\r
+ \r
+ /* SMI_CK = HCLK/2 */\r
+ SMI_InitStruct->SMI_Prescaler = SMI_Prescaler_Mask;\r
+ \r
+ /* Deselect Time set to 6*SMI_CK periods */\r
+ SMI_InitStruct->SMI_DeselectTime = SMI_DeselectTime_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_ModeConfig\r
+* Description : Selects the SMI mode: hardware or software.\r
+* Input : - SMI_Mode: specifies the SMI mode.\r
+* This parameter can be one of the following values:\r
+* - SMI_Mode_HW: SMI in hardware mode\r
+* - SMI_Mode_SW: SMI in software mode\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_ModeConfig(u32 SMI_Mode)\r
+{\r
+ if(SMI_Mode == SMI_Mode_SW)\r
+ { \r
+ SMI->CR1 |= SMI_Mode_SW;\r
+ }\r
+ else\r
+ {\r
+ SMI->CR1 &= SMI_Mode_HW;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_TxRxLengthConfig\r
+* Description : Configures the number of bytes to be transmitted and received\r
+* to/from external memory. This function is used in Software\r
+* mode only.\r
+* Input : - SMI_TxLength: specifies the number of bytes to be transmitted\r
+* to external memory.\r
+* This parameter can be one of the following values:\r
+* - SMI_TxLength_0Bytes: No bytes transmitted \r
+* - SMI_TxLength_1Byte: 1 byte transmitted\r
+* - SMI_TxLength_2Bytes: 2 bytes transmitted\r
+* - SMI_TxLength_3Bytes: 3 bytes transmitted\r
+* - SMI_TxLength_4Bytes: 4 bytes transmitted\r
+* - SMI_RxLength: specifies the number of bytes to be received\r
+* from external memory.\r
+* This parameter can be one of the following values:\r
+* - SMI_RxLength_0Bytes: No bytes received \r
+* - SMI_RxLength_1Byte: 1 byte received\r
+* - SMI_RxLength_2Bytes: 2 bytes received\r
+* - SMI_RxLength_3Bytes: 3 bytes received\r
+* - SMI_RxLength_4Bytes: 4 bytes received\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_TxRxLengthConfig(u32 SMI_TxLength, u32 SMI_RxLength) \r
+{\r
+ u32 Temp = 0;\r
+ \r
+ /* Clear TRA_LENGTH[2:0] and REC_LENGTH[2:0] bits */\r
+ Temp = SMI->CR2 & SMI_TRARECLENGTH_RESET_Mask;\r
+ \r
+ /* Set TRA_LENGTH[2:0] and REC_LENGTH[2:0] bits according to function parameters */\r
+ Temp |= SMI_TxLength | SMI_RxLength;\r
+ \r
+ /* Store the new value */\r
+ SMI->CR2 = Temp;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_BankCmd\r
+* Description : Enables or disables the specified memory Bank.\r
+* Input : - SMI_Bank: specifies the memory Bank to be enabled or disabled.\r
+* This parameter can be any combination of the following values:\r
+* - SMI_Bank_0\r
+* - SMI_Bank_1\r
+* - SMI_Bank_2\r
+* - SMI_Bank_3\r
+* - NewState: new state of the specified memory Bank.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_BankCmd(u32 SMI_Bank, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ SMI->CR1 |= SMI_Bank;\r
+ }\r
+ else\r
+ {\r
+ SMI->CR1 &= ~SMI_Bank;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_ITConfig\r
+* Description : Enables or disables the specified SMI interrupts.\r
+* Input : - SMI_IT: specifies the SMI interrupts sources to be\r
+* enabled or disabled. This parameter can be any combination\r
+* of the following values:\r
+* - SMI_IT_WC : Write Complete Interrupt\r
+* - SMI_IT_TF : Transfer Finished Interrupt\r
+* - NewState: new state of the specified SMI interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_ITConfig(u32 SMI_IT, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ SMI->CR2 |= SMI_IT;\r
+ }\r
+ else\r
+ {\r
+ SMI->CR2 &= ~SMI_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_SelectBank\r
+* Description : Selects the memory Bank to be accessed. Only one Bank can be\r
+* selected at a time.\r
+* Input : - SMI_Bank: specifies the memory Bank to be selected.\r
+* This parameter can be one of the following values:\r
+* - SMI_Bank_0\r
+* - SMI_Bank_1\r
+* - SMI_Bank_2\r
+* - SMI_Bank_3\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_SelectBank(u32 SMI_Bank)\r
+{\r
+ /* Clear BS[1:0] bits (Bank0 is selected)*/\r
+ SMI->CR2 &= SMI_BS_RESET_Mask;\r
+\r
+ switch(SMI_Bank)\r
+ {\r
+ case SMI_Bank_1:\r
+ /* Select Bank1 */\r
+ SMI->CR2 |= SMI_BS_Bank1_Mask;\r
+ break;\r
+\r
+ case SMI_Bank_2:\r
+ /* Select Bank2 */\r
+ SMI->CR2 |= SMI_BS_Bank2_Mask;\r
+ break;\r
+\r
+ case SMI_Bank_3:\r
+ /* Select Bank3 */\r
+ SMI->CR2 |= SMI_BS_Bank3_Mask;\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_SendWENCmd\r
+* Description : Sends a Write Enable command to the selected memory Bank.\r
+* This function is used in Hardware mode only.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_SendWENCmd(void)\r
+{\r
+ SMI->CR2 |= SMI_WEN_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_SendRSRCmd\r
+* Description : Sends a Read Status Register Command to the selected memory\r
+* Bank.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_SendRSRCmd(void)\r
+{\r
+ SMI->CR2 |= SMI_RSR_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_SendCmd\r
+* Description : Sends command to the selected memory Bank. This function is\r
+* used in Software mode only.\r
+* Input : - Command: specifies the command to send to the external memory.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_SendCmd(u32 Command)\r
+{\r
+ /* Load the command in the Transmit Register */\r
+ SMI->TR = Command;\r
+\r
+ /* Start transfer */ \r
+ SMI->CR2 |= SMI_SEND_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_FastReadConfig\r
+* Description : Enables or disables the Fast Read Mode.\r
+* Input : - SMI_FastRead: specifies whether the Fast Read Mode is\r
+* enabled or disabled.\r
+* This parameter can be one of the following values:\r
+* - SMI_FastRead_Disable : Fast Read Mode disabled\r
+* - SMI_FastRead_Enable : Fast Read Mode enabled\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_FastReadConfig(u32 SMI_FastRead)\r
+{\r
+ if(SMI_FastRead == SMI_FastRead_Enable)\r
+ {\r
+ SMI->CR1 |= SMI_FastRead_Enable;\r
+ }\r
+ else\r
+ {\r
+ SMI->CR1 &= SMI_FastRead_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_WriteBurstConfig\r
+* Description : Enables or disables the Write Burst Mode.\r
+* Input : - SMI_WriteBurst: specifies whether the Write Burst Mode is\r
+* enabled or disabled.\r
+* This parameter can be one of the following values:\r
+* - SMI_WriteBurst_Disable : Write Burst Mode disabled\r
+* - SMI_WriteBurst_Enable : Write Burst Mode enabled\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_WriteBurstConfig(u32 SMI_WriteBurst)\r
+{\r
+ if(SMI_WriteBurst == SMI_WriteBurst_Enable)\r
+ {\r
+ SMI->CR1 |= SMI_WriteBurst_Enable;\r
+ }\r
+ else\r
+ {\r
+ SMI->CR1 &= SMI_WriteBurst_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_WriteByte\r
+* Description : Writes a Byte to the selected memory Bank. This function is\r
+* used in Hardware mode only.\r
+* Before calling this function, send a Write Enable command to \r
+* the selected memory Bank using SMI_SendWENCmd() function.\r
+* Input : - WriteAddr: external memory address from which the data will\r
+* be written.\r
+* - Data: data to be written to the external memory.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_WriteByte(u32 WriteAddr, u8 Data)\r
+{\r
+ /* Transfer data to the memory */\r
+ *(u8 *) WriteAddr = Data;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_WriteHalfWord\r
+* Description : Writes a Half Word to the selected memory Bank. This function\r
+* is used in Hardware mode only.\r
+* Before calling this function, send a Write Enable command to \r
+* the selected memory Bank using SMI_SendWENCmd() function.\r
+* Input : - WriteAddr: external memory address from which the data will\r
+* be written.\r
+* - Data: data to be written to the external memory.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_WriteHalfWord(u32 WriteAddr, u16 Data)\r
+{\r
+ /* Transfer data to the memory */\r
+ *(u16 *) WriteAddr = Data;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_WriteWord\r
+* Description : Writes a Word to the selected memory Bank. This function is\r
+* used in Hardware mode only.\r
+* Before calling this function, send a Write Enable command to \r
+* the selected memory Bank using SMI_SendWENCmd() function.\r
+* Input : - WriteAddr: external memory address from which the data will\r
+* be written.\r
+* - Data: data to be written to the external memory.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_WriteWord(u32 WriteAddr, u32 Data)\r
+{\r
+ /* Transfer data to the memory */\r
+ *(u32 *) WriteAddr = Data;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_ReadByte\r
+* Description : Reads a Byte from the selected memory Bank. This function is\r
+* used in Hardware mode only.\r
+* Input : - ReadAddr: external memory address to read from.\r
+* Output : None\r
+* Return : Data read from the external memory.\r
+*******************************************************************************/\r
+u8 SMI_ReadByte(u32 ReadAddr)\r
+{\r
+ return(*(u8 *) ReadAddr);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_ReadHalfWord\r
+* Description : Reads a Half Word from the selected memory Bank. This function\r
+* is used in Hardware mode only.\r
+* Input : - ReadAddr: external memory address to read from.\r
+* Output : None\r
+* Return : Data read from the external memory.\r
+*******************************************************************************/\r
+u16 SMI_ReadHalfWord(u32 ReadAddr)\r
+{\r
+ return(*(u16 *) ReadAddr);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_ReadWord\r
+* Description : Reads a Word from the selected memory Bank. This function is\r
+* used in Hardware mode only.\r
+* Input : - ReadAddr: external memory address to read from.\r
+* Output : None\r
+* Return : Data read from the external memory.\r
+*******************************************************************************/\r
+u32 SMI_ReadWord(u32 ReadAddr)\r
+{\r
+ return(*(u32 *) ReadAddr);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_ReadMemoryStatusRegister\r
+* Description : Reads the status register of the memory connected to the\r
+* selected Bank.\r
+* Input : None\r
+* Output : None\r
+* Return : External memory status register value.\r
+*******************************************************************************/\r
+u8 SMI_ReadMemoryStatusRegister(void)\r
+{\r
+ return((u8) (SMI->SR & SMI_STATUSREGISTER_Mask));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_GetFlagStatus\r
+* Description : Checks whether the specified SMI flag is set or not.\r
+* Input : - SMI_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - SMI_FLAG_Bank3_WM : Memory Bank3 Write Mode flag\r
+* - SMI_FLAG_Bank2_WM : Memory Bank2 Write Mode flag\r
+* - SMI_FLAG_Bank1_WM : Memory Bank1 Write Mode flag\r
+* - SMI_FLAG_Bank0_WM : Memory Bank0 Write Mode flag\r
+* - SMI_FLAG_ERF2 : Error Flag 2: Forbidden Write Request\r
+* - SMI_FLAG_ERF1 : Error Flag 1: Forbidden Access\r
+* - SMI_FLAG_WC : Write Complete flag\r
+* - SMI_FLAG_TF : Transfer Finished flag\r
+* Output : None\r
+* Return : The new state of SMI_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus SMI_GetFlagStatus(u32 SMI_FLAG)\r
+{\r
+ if((SMI->SR & SMI_FLAG) != RESET)\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_ClearFlag\r
+* Description : Clears the SMI\92s pending flags.\r
+* Input : - SMI_FLAG: specifies the flag to clear.\r
+* This parameter can be any combination of the following values:\r
+* - SMI_FLAG_ERF2 : Error Flag 2: Forbidden Write Request\r
+* - SMI_FLAG_ERF1 : Error Flag 1: Forbidden Access\r
+* - SMI_FLAG_WC : Write Complete flag\r
+* - SMI_FLAG_TF : Transfer Finished flag\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_ClearFlag(u32 SMI_FLAG)\r
+{\r
+ SMI->SR &= ~SMI_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_GetITStatus\r
+* Description : Checks whether the specified SMI interrupt has occurred or not.\r
+* Input : - SMI_FLAG: specifies the interrupt source to check.\r
+* This parameter can be one of the following values:\r
+* - SMI_IT_WC : Write Complete Interrupt\r
+* - SMI_IT_TF : Transfer Finished Interrupt\r
+* Output : None\r
+* Return : The new state of SMI_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus SMI_GetITStatus(u32 SMI_IT)\r
+{\r
+ if(((SMI->CR2 & SMI_IT) != RESET) && ((SMI->SR & SMI_IT) != RESET))\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SMI_ClearITPendingBit\r
+* Description : Clears the SMI\92s interrupt pending bits.\r
+* Input : - SMI_FLAG: specifies the interrupts sources to clear.\r
+* This parameter can be any combination of the following values:\r
+* - SMI_IT_WC : Write Complete Interrupt\r
+* - SMI_IT_TF : Transfer Finished Interrupt\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SMI_ClearITPendingBit(u32 SMI_IT)\r
+{\r
+ SMI->SR &= ~SMI_IT;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_ssp.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006 \r
+* Description : This file provides all the SSP software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, \r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING \r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_ssp.h"\r
+#include "75x_mrcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+/* SSP peripheral Enable */\r
+#define SSP_Enable 0x0002\r
+#define SSP_Disable 0xFFFD\r
+\r
+/* SSP Loop Back Mode Enable */\r
+#define SSP_LoopBackMode_Enable 0x0001\r
+#define SSP_LoopBackMode_Disable 0xFFFE\r
+\r
+/* SSP Flag Mask */\r
+#define SSP_Flag_Mask 0x001F\r
+\r
+/* SSP DMA transmit/ receive enable/disable Masks */\r
+#define SSP0_DMA_TransmitEnable 0x0002\r
+#define SSP0_DMA_TransmitDisable 0xFFFD\r
+#define SSP0_DMA_ReceiveEnable 0x0001\r
+#define SSP0_DMA_ReceiveDisable 0xFFFE\r
+\r
+/* SSP Masks */\r
+#define SSP_FrameFormat_Mask 0xFFCF\r
+#define SSP_DataSize_Mask 0xFFF0\r
+#define SSP_ClockRate_Mask 0x00FF\r
+#define SSP_ClockPrescaler_Mask 0xFF00\r
+#define SSP_SSI_Set_Mask 0x0020\r
+#define SSP_SSI_Reset_Mask 0xFFDF\r
+\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_DeInit\r
+* Description : Deinitializes the SSPx peripheral registers to their default\r
+* reset values.\r
+* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SSP_DeInit(SSP_TypeDef* SSPx)\r
+{\r
+ if(SSPx == SSP0)\r
+ {\r
+ /* Reset the SSP0 registers values*/\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP0,ENABLE);\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP0,DISABLE); \r
+ }\r
+ else if (SSPx == SSP1)\r
+ {\r
+ /* Reset the SSP1 registers values*/\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP1,ENABLE);\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP1,DISABLE); \r
+ } \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_Init\r
+* Description : Initializes the SSPx peripheral according to the specified\r
+* parameters in the SSP_InitTypeDef structure.\r
+* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral.\r
+* - SSP_InitStruct: pointer to a SSP_InitTypeDef structure that\r
+* contains the configuration information for the specified SSP\r
+* peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct)\r
+{ \r
+ /* Configure the Frame format */\r
+ if(SSP_InitStruct->SSP_FrameFormat == SSP_FrameFormat_TI)\r
+ { \r
+ /* Clear the FRF[1:0] bits */\r
+ SSPx->CR0 &= SSP_FrameFormat_Mask;\r
+ /* Set the TI frame format */\r
+ SSPx->CR0 |= SSP_FrameFormat_TI;\r
+ }\r
+ else\r
+ {\r
+ /* Set the Motorola frame format */\r
+ SSPx->CR0 &= SSP_FrameFormat_Motorola;\r
+ /* Configure the Clock polarity */\r
+ if(SSP_InitStruct->SSP_CPOL == SSP_CPOL_High)\r
+ { \r
+ /* SCK is held high when no data is being transfered */ \r
+ SSPx->CR0 |= SSP_CPOL_High;\r
+ }\r
+ else\r
+ {\r
+ /* SCK is held low when no data is being transfered */ \r
+ SSPx->CR0 &= SSP_CPOL_Low;\r
+ }\r
+ /* Configure the Clock Phase */\r
+ if(SSP_InitStruct->SSP_CPHA == SSP_CPHA_2Edge)\r
+ { \r
+ /* Data captured on second clock edge */ \r
+ SSPx->CR0 |= SSP_CPHA_2Edge;\r
+ }\r
+ else\r
+ {\r
+ /* Data captured on first clock edge */\r
+ SSPx->CR0 &= SSP_CPHA_1Edge;\r
+ }\r
+ }\r
+ \r
+ /* Configure the Mode */\r
+ if(SSP_InitStruct->SSP_Mode == SSP_Mode_Slave)\r
+ { \r
+ /* Set the slave mode */ \r
+ SSPx->CR1 |= SSP_Mode_Slave;\r
+ /* Configure the Slave output */\r
+ if(SSP_InitStruct->SSP_SlaveOutput == SSP_SlaveOutput_Disable)\r
+ { \r
+ /* Slave output disabled */ \r
+ SSPx->CR1 |= SSP_SlaveOutput_Disable;\r
+ }\r
+ else\r
+ {\r
+ /* Slave output enabled */ \r
+ SSPx->CR1 &= SSP_SlaveOutput_Enable;\r
+ }\r
+ /* Configure the NSS pin */\r
+ if(SSP_InitStruct->SSP_NSS == SSP_NSS_Soft)\r
+ { \r
+ /* Slave selected by software through SSI bit */ \r
+ SSPx->CR1 |= SSP_NSS_Soft;\r
+ SSPx->CR1 &= SSP_SSI_Reset_Mask;\r
+ }\r
+ else\r
+ {\r
+ /* Slave selected by hardware through external SSpin */\r
+ SSPx->CR1 &= SSP_NSS_Hard;\r
+ }\r
+ /* Configure the Clock rate and prescaler in TI slave mode */\r
+ if(SSP_InitStruct->SSP_FrameFormat == SSP_FrameFormat_TI)\r
+ { \r
+ /* Clear clock rate SCR[7:0] bits */\r
+ SSPx->CR0 &= SSP_ClockRate_Mask; \r
+ /* Set the serial clock rate */\r
+ SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<<8);\r
+ /* Clear clock prescaler CPSDVSR[7:0] bits */\r
+ SSPx->PR &= SSP_ClockPrescaler_Mask;\r
+ /* Set the serial clock prescaler */\r
+ SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set the master mode */\r
+ SSPx->CR1 &= SSP_Mode_Master;\r
+ /* Configure the NSS pin */\r
+ if(SSP_InitStruct->SSP_NSS == SSP_NSS_Soft)\r
+ { \r
+ /* Master selected by software through SSI bit */ \r
+ SSPx->CR1 |= SSP_NSS_Soft;\r
+ SSPx->CR1 |= SSP_SSI_Set_Mask;\r
+ }\r
+ else\r
+ {\r
+ /* Master selected by hardware through external SSpin */\r
+ SSPx->CR1 &= SSP_NSS_Hard;\r
+ }\r
+ /* Clear clock rate SCR[7:0] bits */\r
+ SSPx->CR0 &= SSP_ClockRate_Mask; \r
+ /* Set the serial clock rate */\r
+ SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<<8);\r
+ /* Clear clock prescaler CPSDVSR[7:0] bits */\r
+ SSPx->PR &= SSP_ClockPrescaler_Mask;\r
+ /* Set the serial clock prescaler */\r
+ SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler;\r
+ }\r
+ \r
+ /* Clear data size DSS[3:0] bits */\r
+ SSPx->CR0 &= SSP_DataSize_Mask;\r
+ /* Set the data size */\r
+ SSPx->CR0 |= SSP_InitStruct->SSP_DataSize;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_StructInit\r
+* Description : Fills each SSP_InitStruct member with its default value.\r
+* Input : SSP_InitStruct : pointer to a SSP_InitTypeDef structure\r
+ which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct)\r
+{\r
+ /* Initialize the SSP_FrameFormat member */\r
+ SSP_InitStruct->SSP_FrameFormat = SSP_FrameFormat_Motorola;\r
+\r
+ /* Initialize the SSP_Mode member */\r
+ SSP_InitStruct->SSP_Mode = SSP_Mode_Master;\r
+\r
+ /* Initialize the SSP_CPOL member */\r
+ SSP_InitStruct->SSP_CPOL = SSP_CPOL_Low;\r
+\r
+ /* Initialize the SSP_CPHA member */\r
+ SSP_InitStruct->SSP_CPHA = SSP_CPHA_1Edge;\r
+\r
+ /* Initialize the SSP_DataSize member */\r
+ SSP_InitStruct->SSP_DataSize = SSP_DataSize_8b;\r
+ \r
+ /* Initialize the SSP_NSS member */\r
+ SSP_InitStruct->SSP_NSS = SSP_NSS_Hard;\r
+ \r
+ /* Initialize the SSP_SlaveOutput member */\r
+ SSP_InitStruct->SSP_SlaveOutput = SSP_SlaveOutput_Enable;\r
+ \r
+ /* Initialize the SSP_ClockRate member */\r
+ SSP_InitStruct->SSP_ClockRate = 0;\r
+ \r
+ /* Initialize the SSP_ClockPrescaler member */\r
+ SSP_InitStruct->SSP_ClockPrescaler = 0;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_Cmd\r
+* Description : Enables or disables the specified SSP peripheral.\r
+* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral.\r
+* - NewState: new state of the SSPx peripheral. \r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Enable the SSP peripheral */\r
+ SSPx->CR1 |= SSP_Enable;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SSP peripheral */\r
+ SSPx->CR1 &= SSP_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_ITConfig\r
+* Description : Enables or disables the specified SSP interrupts.\r
+* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral.\r
+* - SSP_IT: specifies the SSP interrupts sources to be enabled\r
+* or disabled. This parameter can be any combination of the\r
+* following values:\r
+* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt \r
+* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt \r
+* - SSP_IT_RxTimeOut: Receive timeout interrupt \r
+* - SSP_IT_RxOverrun: Receive overrun interrupt \r
+* - NewState: new state of the specified SSP interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Enable the selected SSP interrupts */\r
+ SSPx->IMSCR |= SSP_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SSP interrupts */\r
+ SSPx->IMSCR &= ~SSP_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_DMACmd\r
+* Description : Configures the SSP0 DMA interface.\r
+* Input : - SSP0_DMAtransfer : specifies the DMA transfer to be \r
+* enabled or disabled. This parameter can be one of the\r
+* following values:\r
+* - SSP0_DMA_Transmit: transmit Fifo DMA transfer\r
+* - SSP0_DMA_Receive: receive Fifo DMA transfer \r
+* - NewState: new state of SSP0 DMA transfer.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SSP_DMACmd(u16 SSP0_DMAtransfer, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE) \r
+ {\r
+ if(SSP0_DMAtransfer == SSP0_DMA_Transmit) \r
+ {\r
+ /* Enable DMA for the transmit FIFO */\r
+ SSP0->DMACR |= SSP0_DMA_TransmitEnable;\r
+ }\r
+ else \r
+ {\r
+ /* Enable DMA for the receive FIFO */\r
+ SSP0->DMACR |= SSP0_DMA_ReceiveEnable;\r
+ }\r
+ }\r
+ else \r
+ {\r
+ if(SSP0_DMAtransfer == SSP0_DMA_Transmit) \r
+ {\r
+ /* Disable DMA for the transmit FIFO */\r
+ SSP0->DMACR &= SSP0_DMA_TransmitDisable;\r
+ }\r
+ else \r
+ {\r
+ /* Disable DMA for the receive FIFO */\r
+ SSP0->DMACR &= SSP0_DMA_ReceiveDisable;\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_DMATxConfig\r
+* Description : Configures the SSP0 DMA transmit transfer.\r
+* Input : - SSP0_DMATxReq : specifies the SSP0 DMA transmit request to \r
+* be enabled. This parameter can be one of the following\r
+* values:\r
+* - SSP0_DMATxReq_Single: Transmit FIFO DMA single \r
+* request enabled\r
+* - SSP0_DMATxReq_Burst: Transmit FIFO DMA burst request\r
+* enabled\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SSP_DMATxConfig(u16 SSP0_DMATxReq)\r
+{\r
+ if(SSP0_DMATxReq == SSP0_DMATxReq_Burst) \r
+ {\r
+ /* Enable DMA transmit burst request */\r
+ SSP0->DMACR |= SSP0_DMATxReq_Burst;\r
+ }\r
+ else \r
+ {\r
+ /* Enable DMA transmit single request */\r
+ SSP0->DMACR &= SSP0_DMATxReq_Single;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_DMARxConfig\r
+* Description : Configures the SSP0 DMA receive transfer.\r
+* Input : - SSP0_DMARxReq : specifies the SSP0 DMA receive request to \r
+* be enabled. This parameter can be one of the following\r
+* values:\r
+* - SSP0_DMARxReq_Single: Receive FIFO DMA burst request\r
+* enabled\r
+* - SSP0_DMARxReq_Burst: Receive FIFO DMA single request\r
+* enabled\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SSP_DMARxConfig(u16 SSP0_DMARxReq)\r
+{\r
+ if(SSP0_DMARxReq == SSP0_DMARxReq_Burst) \r
+ {\r
+ /* Enable DMA receive burst request */\r
+ SSP0->DMACR |= SSP0_DMARxReq_Burst;\r
+ }\r
+ else \r
+ {\r
+ /* Enable DMA receive single request */\r
+ SSP0->DMACR &= SSP0_DMARxReq_Single;\r
+ } \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_SendData\r
+* Description : Transmits a Data through the SSP peripheral.\r
+* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral.\r
+* - Data : Data to be transmitted.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SSP_SendData(SSP_TypeDef* SSPx, u16 Data)\r
+{\r
+ /* Write in the DR register the data to be sent */\r
+ SSPx->DR = Data;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_ReceiveData\r
+* Description : Returns the most recent received data by the SSP peripheral.\r
+* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral.\r
+* Output : None\r
+* Return : The value of the received data.\r
+*******************************************************************************/\r
+u16 SSP_ReceiveData(SSP_TypeDef* SSPx)\r
+{\r
+ /* Return the data in the DR register */ \r
+ return SSPx->DR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_LoopBackConfig\r
+* Description : Enables or disables the Loop back mode for the selected SSP\r
+* peripheral.\r
+* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral.\r
+* - NewState: new state of the Loop Back mode.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Enable loop back mode */\r
+ SSPx->CR1 |= SSP_LoopBackMode_Enable;\r
+ }\r
+ else\r
+ {\r
+ /* Disable loop back mode */\r
+ SSPx->CR1 &= SSP_LoopBackMode_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_NSSInternalConfig\r
+* Description : Configures by software the NSS pin.\r
+* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral.\r
+* - SSP_NSSState: NSS internal state.This parameter can be one\r
+* of the following values:\r
+* - SSP_NSSInternal_Set: Set NSS pin internally\r
+* - SSP_NSSInternal_Reset: Reset NSS pin internally\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SSP_NSSInternalConfig(SSP_TypeDef* SSPx, u16 SSP_NSSState)\r
+{\r
+ if(SSP_NSSState == SSP_NSSInternal_Set)\r
+ {\r
+ /* Set NSS pin internally */\r
+ SSPx->CR1 |= SSP_NSSInternal_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset NSS pin internally */\r
+ SSPx->CR1 &= SSP_NSSInternal_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_GetFlagStatus\r
+* Description : Checks whether the specified SSP flag is set or not.\r
+* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral.\r
+* - SSP_FLAG: specifies the flag to check. This parameter can \r
+* be one of the following values:\r
+* - SSP_FLAG_Busy: busy flag\r
+* - SSP_FLAG_RxFifoFull: Receive FIFO full flag\r
+* - SSP_FLAG_RxFifoNotEmpty: Receive FIFO not empty flag \r
+* - SSP_FLAG_TxFifoNotFull: Transmit FIFO not full flag \r
+* - SSP_FLAG_TxFifoEmpty: Transmit FIFO empty flag \r
+* - SSP_FLAG_TxFifo: Transmit FIFO half empty or less flag\r
+* - SSP_FLAG_RxFifo: Receive FIFO half full or less flag\r
+* - SSP_FLAG_RxTimeOut: Receive timeout flag\r
+* - SSP_FLAG_RxOverrun: Receive overrun flag\r
+* Output : None\r
+* Return : The new state of SSP_FLAG(SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG)\r
+{\r
+ u32 SSPReg = 0, FlagPos = 0;\r
+ u32 StatusReg = 0;\r
+\r
+ /* Get the SSP register index */\r
+ SSPReg = SSP_FLAG >> 5;\r
+\r
+ /* Get the flag position */\r
+ FlagPos = SSP_FLAG & SSP_Flag_Mask;\r
+\r
+ /* Find the register of the flag to check */\r
+ if(SSPReg == 1) \r
+ {\r
+ /* The flag to check is in SR register */\r
+ StatusReg = SSPx->SR; \r
+ }\r
+ else if (SSPReg == 2) \r
+ {\r
+ /* The flag to check is in RISR register */\r
+ StatusReg = SSPx->RISR;\r
+ }\r
+ \r
+ /* Check the status of the specified SSP flag */\r
+ if((StatusReg & (1 << FlagPos)) != RESET)\r
+ {\r
+ /* Return SET if the SSP flag is set */\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ /* Return RESET if the SSP flag is reset */\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_ClearFlag\r
+* Description : Clears the SSPx\92s pending flags.\r
+* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral.\r
+* - SSP_FLAG: specifies the flag to clear. This parameter can \r
+* be one of the following values:\r
+* - SSP_FLAG_RxTimeOut: Receive timeout flag \r
+* - SSP_FLAG_RxOverrun: Receive overrun flag \r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG)\r
+{ \r
+ u8 FlagPos = 0;\r
+\r
+ /* Get the flag position */\r
+ FlagPos = SSP_FLAG & SSP_Flag_Mask;\r
+ \r
+ /* Clear the selected SSP flag */ \r
+ SSPx->ICR = (1 << FlagPos); \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_GetITStatus\r
+* Description : Checks whether the specified SSP interrupt has occurred or not.\r
+* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral.\r
+* - SSP_IT: specifies the interrupt source to check. \r
+* This parameter can be one of the following values:\r
+* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt \r
+* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt \r
+* - SSP_IT_RxTimeOut: Receive timeout interrupt \r
+* - SSP_IT_RxOverrun: Receive overrun interrupt \r
+* Output : None\r
+* Return : The new state of SSP_IT(SET or RESET).\r
+*******************************************************************************/\r
+ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT)\r
+{\r
+ /* Check the status of the specified interrupt flag */\r
+ if((SSPx->MISR & SSP_IT) != RESET)\r
+ {\r
+ /* Return SET if the SSP interrupt flag is set */\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ /* Return RESET if SSP interrupt flag is reset */\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SSP_ClearITPendingBit\r
+* Description : Clears the SSPx\92s interrupt pending bits.\r
+* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral.\r
+* - SSP_IT: specifies the interrupt pending bit to clear. \r
+* This parameter can be any combination of the following values:\r
+* - SSP_IT_RxTimeOut: Receive timeout interrupt \r
+* - SSP_IT_RxOverrun: Receive overrun interrupt \r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT)\r
+{\r
+ /* Clear the selected SSP interrupts pending bits */\r
+ SSPx->ICR = SSP_IT;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_tb.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file provides all the TB software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_tb.h"\r
+#include "75x_mrcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+#define TB_IT_Enable_Mask 0x7FFF\r
+#define TB_IT_Clear_Mask 0x7FFF\r
+#define TB_IC_Enable 0x0004\r
+#define TB_ICPolarity_Set 0x0008\r
+#define TB_ICPolarity_Reset 0xFFF7\r
+#define TB_UFS_Reset 0xFFFE\r
+#define TB_UFS_Set 0x0001\r
+\r
+/* TB debug state */\r
+#define TB_DBGC_Set 0x0400\r
+#define TB_DBGC_Reset 0xFB7F\r
+\r
+/* TB counter state */\r
+#define TB_COUNTER_Reset 0x0002\r
+#define TB_COUNTER_Start 0x0004\r
+#define TB_COUNTER_Stop 0xFFFB\r
+\r
+#define TB_SMS_EXTCLK_Set 0x0008\r
+#define TB_SMS_RESETCLK_Set 0x0000\r
+\r
+/* TB Slave Mode Enable Set/Reset value */\r
+#define TB_SME_Reset 0x731B\r
+#define TB_SME_Set 0x0004\r
+\r
+/* TB Trigger Selection value */\r
+#define TB_TS_IC1_Set 0x0200\r
+\r
+/* TB SCR Masks bit */\r
+#define TB_SlaveModeSelection_Mask 0x7307\r
+#define TB_TriggerSelection_Mask 0x701F\r
+\r
+/* Reset Register Masks */\r
+#define TB_Prescaler_Reset_Mask 0x0000\r
+#define TB_CounterMode_Mask 0xFF8F\r
+#define TB_AutoReload_Reset_Mask 0xFFFF\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+ /******************************************************************************\r
+* Function Name : TB_DeInit\r
+* Description : Deinitializes the TB peripheral registers to their default\r
+* reset values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TB_DeInit(void)\r
+{\r
+ /* Enters and exits the TB peripheral to and from reset */\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TB,ENABLE);\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TB,DISABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_Init\r
+* Description : Initializes TB peripheral according to the specified\r
+* parameters in the TB_InitStruct.\r
+* Input : TB_InitStruct: pointer to a TB_InitTypeDef structure that\r
+* contains the configuration information for the TB peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TB_Init(TB_InitTypeDef* TB_InitStruct)\r
+{\r
+ /* Set the TB prescaler value */\r
+ TB->PSC = TB_InitStruct->TB_Prescaler;\r
+\r
+ /* Set the TB period value */\r
+ TB->ARR = TB_InitStruct->TB_AutoReload;\r
+\r
+ /* Set the corresponding counter mode */\r
+ TB->CR = (TB->CR & TB_CounterMode_Mask) | TB_InitStruct->TB_CounterMode;\r
+\r
+ /* Set the corresponding clock source */\r
+ if(TB_InitStruct->TB_ClockSource == TB_ClockSource_CKRTC)\r
+ { \r
+ TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask;\r
+ TB->SCR |= TB_SMS_EXTCLK_Set | TB_SME_Set | TB_TS_IC1_Set;\r
+ }\r
+ else\r
+ {\r
+ TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask;\r
+ }\r
+\r
+ if(TB_InitStruct->TB_Mode == TB_Mode_IC)\r
+ {\r
+ /* Set the corresponding value in TB SCR register */\r
+ TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask;\r
+ TB->SCR |= TB_SMS_RESETCLK_Set | TB_SME_Set | TB_TS_IC1_Set;\r
+\r
+ /* Set the IC1 enable bit */\r
+ TB->IMCR |= TB_IC_Enable;\r
+\r
+ /* Set the input signal polarity */\r
+ if (TB_InitStruct->TB_ICAPolarity == TB_ICAPolarity_Falling)\r
+ {\r
+ TB->IMCR |= TB_ICPolarity_Set;\r
+ }\r
+ else\r
+ {\r
+ TB->IMCR &= TB_ICPolarity_Reset;\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_StructInit\r
+* Description : Fills each TB_InitStruct member with its default value\r
+* Input : TB_InitStruct : pointer to a TB_InitTypeDef structure which\r
+* will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TB_StructInit(TB_InitTypeDef *TB_InitStruct)\r
+{\r
+ TB_InitStruct->TB_Mode = TB_Mode_Timing;\r
+ TB_InitStruct->TB_ClockSource = TB_ClockSource_CKTIM;\r
+ TB_InitStruct->TB_CounterMode = TB_CounterMode_Up;\r
+ TB_InitStruct->TB_ICAPolarity = TB_ICAPolarity_Rising;\r
+ TB_InitStruct->TB_Prescaler = TB_Prescaler_Reset_Mask;\r
+ TB_InitStruct->TB_AutoReload = TB_AutoReload_Reset_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_Cmd\r
+* Description : Enables or disables the TB peripheral.\r
+* Input : Newstate: new state of the TB peripheral. This parameter can\r
+* be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TB_Cmd(FunctionalState Newstate)\r
+{\r
+ if(Newstate == ENABLE)\r
+ {\r
+ TB->CR |= TB_COUNTER_Start;\r
+ }\r
+ else\r
+ {\r
+ TB->CR &= TB_COUNTER_Stop;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_ITConfig\r
+* Description : Enables or disables the specified TB interrupt.\r
+* Input : - TB_IT: specifies the TB interrupt sources to be enabled or\r
+* disabled.\r
+* This parameter can be any combination of the following values:\r
+* - TB_IT_Update: TB Update interrupt\r
+* - TB_IT_GlobalUpdate: TB Global Update interrupt\r
+* - TB_IT_IC: TB Input Capture interrupt\r
+* - Newstate: new state of the specified TB interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TB_ITConfig(u16 TB_IT, FunctionalState Newstate)\r
+{\r
+ u16 TB_IT_Enable = 0;\r
+\r
+ TB_IT_Enable = TB_IT & TB_IT_Enable_Mask;\r
+\r
+ if(Newstate == ENABLE)\r
+ {\r
+ /* Update interrupt global source: overflow/undeflow, counter reset operation\r
+ or slave mode controller in reset mode */\r
+ if ((TB_IT & TB_IT_GlobalUpdate) == TB_IT_GlobalUpdate)\r
+ {\r
+ TB->CR &= TB_UFS_Reset;\r
+ }\r
+ /* Update interrupt source: counter overflow/underflow */\r
+ else if ((TB_IT & TB_IT_Update) == TB_IT_Update)\r
+ {\r
+ TB->CR |= TB_UFS_Set;\r
+ }\r
+ /* Select and enable the interrupts requests */\r
+ TB->RSR |= TB_IT_Enable;\r
+ TB->RER |= TB_IT_Enable;\r
+ }\r
+ /* Disable the interrupts requests */\r
+ else\r
+ {\r
+ TB->RSR &= ~TB_IT_Enable;\r
+ TB->RER &= ~TB_IT_Enable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_SetPrescaler\r
+* Description : Sets the TB Prescaler value.\r
+* Input : Prescaler: specifies the TB Prescaler value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TB_SetPrescaler(u16 Prescaler)\r
+{\r
+ /* Sets the prescaler value */\r
+ TB->PSC = Prescaler;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_ResetCounter\r
+* Description : Re-intializes the counter and generates an update of the\r
+* registers.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TB_ResetCounter(void)\r
+{\r
+ /* Re-intializes TB counter */\r
+ TB->CR |= TB_COUNTER_Reset;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_DebugCmd\r
+* Description : Enables or disables TB peripheral Debug control.\r
+* Input : Newstate: new state of the TB Debug control.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TB_DebugCmd(FunctionalState Newstate)\r
+{\r
+ if(Newstate == ENABLE)\r
+ {\r
+ TB->CR |= TB_DBGC_Set;\r
+ }\r
+ else\r
+ {\r
+ TB->CR &= TB_DBGC_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_CounterModeConfig\r
+* Description : Configures the TB Counter Mode.\r
+* Input : TB_CounterMode: specifies the TB counter mode to be used.\r
+* This parameter can be one of the following values:\r
+* - TB_CounterMode_Up: TB Up Counting Mode\r
+* - TB_CounterMode_Down: TB Down Counting Mode\r
+* - TB_CounterMode_CenterAligned: TB Center Aligned Mode\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TB_CounterModeConfig(u16 TB_CounterMode)\r
+{\r
+ /* Counter mode configuration */\r
+ TB->CR &= TB_CounterMode_Mask;\r
+ TB->CR |= TB_CounterMode;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_SLaveModeConfig\r
+* Description : Configures the TB slave Mode.\r
+* Input : TB_SMSMode: specifies the TB slave mode to be used.\r
+* This parameter can be one of the following values:\r
+* - TB_SMSMode_Trigger: The counter starts at a rising \r
+* edge of the trigger \r
+* - TB_SMSMode_Gated: The counter clock is enabled when \r
+* trigger signal is high\r
+* - TB_SMSMode_External: The rising edge of selected trigger\r
+* clocks the counter\r
+* - TB_SMSMode_Reset: The rising edge of the selected \r
+* trigger signal resets the counter\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TB_SLaveModeConfig(u16 TB_SMSMode)\r
+{\r
+ TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask;\r
+ TB->SCR |= TB_SME_Set | TB_SMSMode | TB_TS_IC1_Set; \r
+}\r
+/*******************************************************************************\r
+* Function Name : TB_GetCounter\r
+* Description : Gets the TB Counter value.\r
+* Input : None\r
+* Output : None\r
+* Return : The TB counter register value.\r
+*******************************************************************************/\r
+u16 TB_GetCounter(void)\r
+{\r
+ return TB->CNT;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_GetICAP1\r
+* Description : Gets the TB Input capture value.\r
+* Input : None\r
+* Output : None\r
+* Return : The TB ICR1 register value.\r
+*******************************************************************************/\r
+u16 TB_GetICAP1(void)\r
+{\r
+ return TB->ICR1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_SetCounter\r
+* Description : Sets the TB Counter value.\r
+* Input : Counter: specifies the TB Counter value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TB_SetCounter(u16 Counter)\r
+{\r
+ TB->CNT = Counter;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_GetFlagStatus\r
+* Description : Checks whether the specified TB flag is set or not.\r
+* Input : TB_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - TB_FLAG_IC: TB Input Capture flag\r
+* - TB_FLAG_Update: TB update flag\r
+* Output : None\r
+* Return : The new state of the TB_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus TB_GetFlagStatus(u16 TB_FLAG)\r
+{\r
+ if((TB->ISR & TB_FLAG) != RESET )\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_ClearFlag\r
+* Description : Clears the TB\92s pending flags.\r
+* Input : TB_FLAG: specifies the flag to clear.\r
+* This parameter can be any combination of the following values:\r
+* - TB_FLAG_IC: TB Input Capture flag\r
+* - TB_FLAG_Update: TB update flag\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TB_ClearFlag(u16 TB_FLAG)\r
+{\r
+ /* Clears the flags */\r
+ TB->ISR &= ~TB_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_GetITStatus\r
+* Description : Checks whether the specified TB interrupt has occurred or not.\r
+* Input : TB_IT: specifies the interrupt to check.\r
+* This parameter can be one of the following values:\r
+* - TB_IT_Update: TB Update interrupt\r
+* - TB_IT_GlobalUpdate: TB Global Update interrupt\r
+* - TB_IT_IC: TB Input Capture interrupt\r
+* Output : None\r
+* Return : The new state of the TB_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus TB_GetITStatus(u16 TB_IT)\r
+{\r
+ u16 TB_IT_Check = 0;\r
+\r
+ /* Calculates the pending bits to be checked */\r
+ TB_IT_Check = TB_IT & TB_IT_Clear_Mask;\r
+ \r
+ if((TB->ISR & TB_IT_Check) != RESET )\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TB_ClearITPendingBit\r
+* Description : Clears the TB's interrupt pending bits.\r
+* Input : TB_IT: specifies the interrupt pending bit to clear.\r
+* This parameter can be any combination of the following values:\r
+* - TB_IT_Update: TB Update interrupt\r
+* - TB_IT_GlobalUpdate: TB Global Update interrupt\r
+* - TB_IT_IC: TB Input Capture interrupt\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TB_ClearITPendingBit(u16 TB_IT)\r
+{\r
+ u16 TB_IT_Clear = 0;\r
+\r
+ /* Calculates the pending bits to be cleared */\r
+ TB_IT_Clear = TB_IT & TB_IT_Clear_Mask;\r
+\r
+ /* Clears the pending bits */\r
+ TB->ISR &= ~TB_IT_Clear;\r
+}\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_tim.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file provides all the TIM software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_tim.h" \r
+#include "75x_mrcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* TIM interrupt masks */\r
+#define TIM_IT_Clear_Mask 0x7FFF\r
+#define TIM_IT_Enable_Mask 0x7FFF\r
+\r
+/* TIM Input Capture Selection Set/Reset */\r
+#define TIM_IC1S_Set 0x0001\r
+#define TIM_IC1S_Reset 0x003E\r
+\r
+/* TIM Input Capture Selection Set/Reset */\r
+#define TIM_IC2S_Set 0x0002\r
+#define TIM_IC2S_Reset 0x003D\r
+\r
+/* TIM_SCR Masks bit */\r
+#define TIM_Encoder_Mask 0x731C\r
+#define TIM_SlaveModeSelection_Mask 0x7307\r
+#define TIM_TriggerSelection_Mask 0x701F\r
+#define TIM_InternalTriggerSelection_Mask 0x031F\r
+\r
+/* TIM Encoder mode Set value */\r
+#define TIM_Encoder1_Set 0x0001\r
+#define TIM_Encoder2_Set 0x0002\r
+#define TIM_Encoder3_Set 0x0003\r
+\r
+/* TIM Slave Mode Enable Set/Reset value */\r
+#define TIM_SME_Reset 0x731B\r
+#define TIM_SME_Set 0x0004\r
+\r
+/* TIM Internal Trigger Selection value */\r
+#define TIM_ITS_TIM0 0x1000\r
+#define TIM_ITS_TIM1 0x2000\r
+#define TIM_ITS_TIM2 0x3000\r
+#define TIM_ITS_PWM 0x4000\r
+\r
+/* TIM Trigger Selection value */\r
+#define TIM_TS_IC1_Set 0x0200\r
+#define TIM_TS_IC2_Set 0x0300\r
+\r
+/* TIM Slave Mode selction external clock Set value */\r
+#define TIM_SMS_EXTCLK_Set 0x0008\r
+#define TIM_SMS_RESETCLK_Set 0x0000\r
+\r
+/* TIM_CR Masks bit */\r
+#define TIM_DBASE_Mask 0x077F\r
+#define TIM_MasterModeSelection_Mask 0xFC7F\r
+#define TIM_CounterMode_Mask 0xFF8F\r
+\r
+/* TIM Update flag selection Set/Reset value */\r
+#define TIM_UFS_Reset 0xFFFE\r
+#define TIM_UFS_Set 0x0001\r
+\r
+/* TIM Counter value */\r
+#define TIM_COUNTER_Reset 0x0002\r
+#define TIM_COUNTER_Start 0x0004\r
+#define TIM_COUNTER_Stop 0xFFFB\r
+\r
+/* TIM One pulse Mode set value */\r
+#define TIM_OPM_Set 0x0008\r
+#define TIM_OPM_Reset 0xFFF7\r
+\r
+/* TIM Debug Mode Set/Reset value */\r
+#define TIM_DBGC_Set 0x0400\r
+#define TIM_DBGC_Reset 0xFB7F\r
+\r
+/* TIM Input Capture Enable/Disable value */\r
+#define TIM_IC1_Enable 0x0004\r
+#define TIM_IC2_Enable 0x0010\r
+\r
+/* TIM Input Capture Polarity Set/Reset value */\r
+#define TIM_IC1P_Set 0x0008\r
+#define TIM_IC2P_Set 0x0020\r
+#define TIM_IC1P_Reset 0x0037\r
+#define TIM_IC2P_Reset 0x001F\r
+\r
+/* TIM Output Compare Polarity Set/Reset value */\r
+#define TIM_OC1P_Set 0x0020\r
+#define TIM_OC2P_Set 0x2000\r
+#define TIM_OC1P_Reset 0x3F1F\r
+#define TIM_OC2P_Reset 0x1F3F\r
+\r
+/* TIM Output Compare control mode constant */\r
+#define TIM_OCControl_PWM 0x000C\r
+#define TIM_OCControl_OCToggle 0x0006\r
+#define TIM_OCControl_OCInactive 0x0004\r
+#define TIM_OCControl_OCActive 0x0002\r
+#define TIM_OCControl_OCTiming 0x0000\r
+\r
+/* TIM Output Compare mode Enable value */\r
+#define TIM_OC1_Enable 0x0010\r
+#define TIM_OC2_Enable 0x1000\r
+\r
+/* TIM Output Compare mode Mask value */\r
+#define TIM_OC1C_Mask 0x3F31\r
+#define TIM_OC2C_Mask 0x313F\r
+\r
+/* TIM Preload bit Set/Reset value */\r
+#define TIM_PLD1_Set 0x0001\r
+#define TIM_PLD1_Reset 0xFFFE\r
+\r
+#define TIM_PLD2_Set 0x0100\r
+#define TIM_PLD2_Reset 0xFEFF\r
+\r
+/* TIM OCRM Set/Reset value */\r
+#define TIM_OCRM_Set 0x0080\r
+#define TIM_OCRM_Reset 0x030D\r
+\r
+/* Reset Register Masks */\r
+#define TIM_Pulse2_Reset_Mask 0x0000\r
+#define TIM_Prescaler_Reset_Mask 0x0000\r
+#define TIM_Pulse1_Reset_Mask 0x0000\r
+#define TIM_Period_Reset_Mask 0xFFFF\r
+#define TIM_Counter_Reset 0x0002\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void ICAP_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct);\r
+static void Encoder_ModeConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct);\r
+static void OCM_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct);\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/******************************************************************************\r
+* Function Name : TIM_DeInit\r
+* Description : Deinitializes TIM peripheral registers to their default reset\r
+* values.\r
+* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_DeInit(TIM_TypeDef *TIMx)\r
+{ \r
+ if(TIMx == TIM0)\r
+ {\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM0,ENABLE);\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM0,DISABLE);\r
+ }\r
+ else if(TIMx == TIM1)\r
+ {\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM1,ENABLE);\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM1,DISABLE);\r
+ }\r
+ else if(TIMx == TIM2)\r
+ {\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM2,ENABLE);\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM2,DISABLE);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_Init\r
+* Description : Initializes the TIMx peripheral according to the specified\r
+* parameters in the TIM_InitStruct .\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.\r
+* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that\r
+* contains the configuration information for the specified TIM\r
+* peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_Init(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct)\r
+{\r
+ /* Set the prescaler value */\r
+ TIMx->PSC = TIM_InitStruct->TIM_Prescaler;\r
+\r
+ /* Select the clock source */\r
+ TIM_ClockSourceConfig(TIMx, TIM_InitStruct->TIM_ClockSource,\r
+ TIM_InitStruct->TIM_ExtCLKEdge);\r
+\r
+ /* Select the counter mode */\r
+ TIMx->CR &= TIM_CounterMode_Mask;\r
+ TIMx->CR |= TIM_InitStruct->TIM_CounterMode;\r
+\r
+ /* Set the period value */\r
+ TIMx->ARR = TIM_InitStruct->TIM_Period;\r
+\r
+ switch(TIM_InitStruct->TIM_Mode)\r
+ {\r
+ case TIM_Mode_OCTiming: case TIM_Mode_OCActive: case TIM_Mode_OCInactive:\r
+ case TIM_Mode_OCToggle: case TIM_Mode_PWM:\r
+ OCM_ModuleConfig(TIMx, TIM_InitStruct);\r
+ break;\r
+\r
+ case TIM_Mode_PWMI: case TIM_Mode_IC:\r
+ ICAP_ModuleConfig(TIMx, TIM_InitStruct);\r
+ break;\r
+\r
+ case TIM_Mode_Encoder1: case TIM_Mode_Encoder2: case TIM_Mode_Encoder3:\r
+ Encoder_ModeConfig(TIMx, TIM_InitStruct);\r
+ break;\r
+\r
+ case TIM_Mode_OPM_PWM: case TIM_Mode_OPM_Toggle: case TIM_Mode_OPM_Active:\r
+\r
+ /* Output module configuration */\r
+ OCM_ModuleConfig(TIMx, TIM_InitStruct);\r
+\r
+ /* Input module configuration */\r
+ ICAP_ModuleConfig(TIMx, TIM_InitStruct);\r
+ \r
+ /* Set the slave mode to trigger Mode */\r
+ TIMx->SCR |= TIM_SynchroMode_Trigger;\r
+\r
+ /* Repetitive pulse state selection */\r
+ if(TIM_InitStruct->TIM_RepetitivePulse == TIM_RepetitivePulse_Disable)\r
+ {\r
+ TIMx->CR |= TIM_OPM_Set;\r
+ }\r
+ else\r
+ {\r
+ TIMx->CR &= TIM_OPM_Reset;\r
+ }\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_StructInit\r
+* Description : Fills each TIM_InitStruct member with its default value.\r
+* Input : TIM_InitStruct : pointer to a TIM_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None \r
+* Return : None.\r
+*******************************************************************************/\r
+void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_InitStruct->TIM_Mode = TIM_Mode_OCTiming;\r
+ TIM_InitStruct->TIM_Prescaler = TIM_Prescaler_Reset_Mask;\r
+ TIM_InitStruct->TIM_ClockSource = TIM_ClockSource_Internal;\r
+ TIM_InitStruct->TIM_ExtCLKEdge = TIM_ExtCLKEdge_Rising;\r
+ TIM_InitStruct->TIM_CounterMode = TIM_CounterMode_Up;\r
+ TIM_InitStruct->TIM_Period = TIM_Period_Reset_Mask;\r
+ TIM_InitStruct->TIM_Channel = TIM_Channel_ALL;\r
+ TIM_InitStruct->TIM_Pulse1 = TIM_Pulse1_Reset_Mask;\r
+ TIM_InitStruct->TIM_Pulse2 = TIM_Pulse2_Reset_Mask;\r
+ TIM_InitStruct->TIM_RepetitivePulse = TIM_RepetitivePulse_Disable;\r
+ TIM_InitStruct->TIM_Polarity1 = TIM_Polarity1_Low;\r
+ TIM_InitStruct->TIM_Polarity2 = TIM_Polarity2_Low;\r
+ TIM_InitStruct->TIM_IC1Selection = TIM_IC1Selection_TI1;\r
+ TIM_InitStruct->TIM_IC2Selection = TIM_IC2Selection_TI1;\r
+ TIM_InitStruct->TIM_IC1Polarity = TIM_IC1Polarity_Rising;\r
+ TIM_InitStruct->TIM_IC2Polarity = TIM_IC2Polarity_Rising;\r
+ TIM_InitStruct->TIM_PWMI_ICSelection = TIM_PWMI_ICSelection_TI1;\r
+ TIM_InitStruct->TIM_PWMI_ICPolarity = TIM_PWMI_ICPolarity_Rising;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_Cmd\r
+* Description : Enables or disables the specified TIM peripheral.\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.\r
+* - Newstate: new state of the TIMx peripheral.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState Newstate)\r
+{\r
+ if(Newstate == ENABLE)\r
+ { \r
+ TIMx->CR |= TIM_COUNTER_Start;\r
+ }\r
+ else\r
+ {\r
+ TIMx->CR &= TIM_COUNTER_Stop;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ITConfig\r
+* Description : Enables or disables the TIM interrupts.\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.\r
+* - TIM_IT: specifies the TIM interrupts sources to be enabled\r
+* or disabled.\r
+* This parameter can be any combination of the following values:\r
+* - TIM_IT_IC1: Input Capture 1 Interrupt \r
+* - TIM_IT_OC1: Output Compare 1 Interrupt \r
+* - TIM_IT_Update: Timer update Interrupt \r
+* - TIM_IT_GlobalUpdate: Timer global update Interrupt \r
+* - TIM_IT_IC2: Input Capture 2 Interrupt \r
+* - TIM_IT_OC2: Output Compare 2 Interrupt \r
+* - Newstate: new state of the specified TIMx interrupts. \r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState Newstate)\r
+{ \r
+ u16 TIM_IT_Enable = 0;\r
+\r
+ TIM_IT_Enable = TIM_IT & TIM_IT_Enable_Mask;\r
+\r
+ if(Newstate == ENABLE)\r
+ {\r
+ /* Update interrupt global source: overflow/undeflow, counter reset operation\r
+ or slave mode controller in reset mode */\r
+ if((TIM_IT & TIM_IT_GlobalUpdate) == TIM_IT_GlobalUpdate)\r
+ {\r
+ TIMx->CR &= TIM_UFS_Reset;\r
+ }\r
+ /* Update interrupt source: counter overflow/underflow */\r
+ else if((TIM_IT & TIM_IT_Update) == TIM_IT_Update)\r
+ {\r
+ TIMx->CR |= TIM_UFS_Set;\r
+ }\r
+ /* Select and enable the interrupts requests */\r
+ TIMx->RSR |= TIM_IT_Enable;\r
+ TIMx->RER |= TIM_IT_Enable;\r
+ }\r
+ /* Disable the interrupts requests */\r
+ else\r
+ {\r
+ TIMx->RSR &= ~TIM_IT_Enable;\r
+ TIMx->RER &= ~TIM_IT_Enable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_PreloadConfig\r
+* Description : Enables or disables TIM peripheral Preload register on OCRx.\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.\r
+* - TIM_Channel: specifies the TIM channel to be used.\r
+* This parameter can be one of the following values:\r
+* - TIM_Channel_1: TIM Channel 1 is used\r
+* - TIM_Channel_2: TIM Channel 2 is used\r
+* - TIM_Channel_ALL: TIM Channel 1and 2 are used\r
+* - Newstate: new state of the TIMx peripheral Preload register\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_PreloadConfig(TIM_TypeDef *TIMx, u16 TIM_Channel, FunctionalState Newstate)\r
+{\r
+ if(Newstate == ENABLE)\r
+ {\r
+ switch (TIM_Channel)\r
+ {\r
+ case TIM_Channel_1:\r
+ TIMx->OMR1 |= TIM_PLD1_Set;\r
+ break;\r
+ \r
+ case TIM_Channel_2:\r
+ TIMx->OMR1 |= TIM_PLD2_Set;\r
+ break;\r
+\r
+ case TIM_Channel_ALL:\r
+ TIMx->OMR1 |= TIM_PLD1_Set | TIM_PLD2_Set;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ switch (TIM_Channel)\r
+ {\r
+ case TIM_Channel_1:\r
+ TIMx->OMR1 &= TIM_PLD1_Reset;\r
+ break;\r
+ \r
+ case TIM_Channel_2:\r
+ TIMx->OMR1 &= TIM_PLD2_Reset;\r
+ break;\r
+\r
+ case TIM_Channel_ALL:\r
+ TIMx->OMR1 &= TIM_PLD1_Reset & TIM_PLD2_Reset;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ } \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_DMAConfig\r
+* Description : Configures the TIM0\92s DMA interface.\r
+* Input : - TIM_DMASources: specifies the DMA Request sources.\r
+* This parameter can be any combination of the following values:\r
+* - TIM_DMASource_OC1: Output Compare 1 DMA source\r
+* - TIM_DMASource_OC2: Output Compare 2 DMA source\r
+* - TIM_DMASource_IC1: Input Capture 1 DMA source\r
+* - TIM_DMASource_IC2: Input Capture 2 DMA source\r
+* - TIM_DMASource_Update: Timer Update DMA source\r
+* - TIM_OCRMState: the state of output compare request mode.\r
+* This parameter can be one of the following values:\r
+* - TIM_OCRMState_Enable \r
+* - TIM_OCRMState_Disable \r
+* - TIM_DMABase:DMA Base address.\r
+* This parameter can be one of the following values:\r
+* TIM_DMABase_CR, TIM_DMABase_SCR, TIM_DMABase_IMCR,\r
+* TIM_DMABase_OMR1, TIM_DMABase_RSR,\r
+* TIM_DMABase_RER, TIM_DMABase_ISR, TIM_DMABase_CNT, \r
+* TIM_DMABase_PSC, TIM_DMABase_ARR, TIM_DMABase_OCR1, \r
+* TIM_DMABase_OCR2, TIM_DMABase_ICR1, TIM_DMABase_ICR2\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_DMAConfig(u16 TIM_DMASources, u16 TIM_OCRMState, u16 TIM_DMABase)\r
+{\r
+ /* Select the DMA requests */\r
+ TIM0->RSR &= TIM_DMASources;\r
+\r
+ /* Set the OCRM state */\r
+ if(TIM_OCRMState == TIM_OCRMState_Enable)\r
+ {\r
+ TIM0->RSR |= TIM_OCRM_Set;\r
+ }\r
+ else\r
+ {\r
+ TIM0->RSR &= TIM_OCRM_Reset;\r
+ }\r
+\r
+ /* Set the DMA Base address */\r
+ TIM0->CR &= TIM_DBASE_Mask;\r
+ TIM0->CR |= TIM_DMABase;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_DMACmd\r
+* Description : Enables or disables the TIM0\92s DMA interface.\r
+* Input : - TIM_DMASources: specifies the DMA Request sources.\r
+* This parameter can be any combination of the following values:\r
+* - TIM_DMASource_OC1: Output Compare 1 DMA source\r
+* - TIM_DMASource_OC2: Output Compare 2 DMA source\r
+* - TIM_DMASource_IC1: Input Capture 1 DMA source\r
+* - TIM_DMASource_IC2: Input Capture 2 DMA source\r
+* - TIM_DMASource_Update: Timer Update DMA source\r
+* - Newstate: new state of the DMA Request sources.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_DMACmd(u16 TIM_DMASources, FunctionalState Newstate)\r
+{\r
+ if(Newstate == ENABLE)\r
+ {\r
+ TIM0->RER |= TIM_DMASources;\r
+ }\r
+ else\r
+ {\r
+ TIM0->RER &= ~TIM_DMASources;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ClockSourceConfig\r
+* Description : Configures the TIM clock source.\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.\r
+* - TIM_ClockSource: specifies the TIM clock source to be \r
+* selected.\r
+* This parameter can be one of the following values:\r
+* - TIM_ClockSource_Internal: CK_TIM internal clock\r
+* - TIM_ClockSource_TI11: External input pin TI1 \r
+* connected to IC1 channel.\r
+* - TIM_ClockSource_TI12: External input pin TI1\r
+* connected to IC2 channel.\r
+* - TIM_ClockSource_TI22: External input pin TI2\r
+* connected to IC2 channel.\r
+* - TIM_ClockSource_TI21: External input pin TI2\r
+* connected to IC1 channel.\r
+* - TIM_ExtCLKEdge: specifies the External input signal edge.\r
+* This parameter can be one of the following values:\r
+* - TIM_ExtCLKEdge_Falling : Falling edge selected.\r
+* - TIM_ExtCLKEdge_Rising : Rising edge selected.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ClockSourceConfig(TIM_TypeDef *TIMx, u16 TIM_ClockSource,\r
+ u16 TIM_ExtCLKEdge)\r
+{\r
+ if(TIM_ClockSource == TIM_ClockSource_Internal)\r
+ {\r
+ /* CK_TIM is used as clock source */\r
+ TIMx->SCR &= TIM_SME_Reset & TIM_SlaveModeSelection_Mask & TIM_TriggerSelection_Mask;\r
+ }\r
+ else\r
+ /* Input Captures are used as TIM external clock */\r
+ {\r
+ TIMx->SCR &= TIM_SME_Reset & TIM_SlaveModeSelection_Mask & TIM_TriggerSelection_Mask;\r
+ TIMx->SCR |= TIM_SMS_EXTCLK_Set | TIM_SME_Set;\r
+\r
+ if((TIM_ClockSource == TIM_ClockSource_TI11) ||\r
+ (TIM_ClockSource == TIM_ClockSource_TI21))\r
+ /* Input Capture 1 is selected */\r
+ {\r
+ /* Input capture Enable */\r
+ TIMx->IMCR |= TIM_IC1_Enable;\r
+ TIMx->SCR |= TIM_TS_IC1_Set;\r
+\r
+ if(TIM_ExtCLKEdge == TIM_ExtCLKEdge_Falling)\r
+ /* Set the corresponding polarity */\r
+ {\r
+ TIMx->IMCR |= TIM_IC1P_Set;\r
+ }\r
+ else\r
+ { \r
+ TIMx->IMCR &= TIM_IC1P_Reset;\r
+ }\r
+ if(TIM_ClockSource == TIM_ClockSource_TI11)\r
+ {\r
+ /* External signal TI1 connected to IC1 channel */\r
+ TIMx->IMCR &= TIM_IC1S_Reset;\r
+ }\r
+ else\r
+ {\r
+ /* External signal TI2 connected to IC1 channel */\r
+ TIMx->IMCR |= TIM_IC1S_Set;\r
+ }\r
+ }\r
+ else\r
+ /* Input Capture 2 is selected */\r
+ {\r
+ /* Input capture Enable */\r
+ TIMx->IMCR |= TIM_IC2_Enable;\r
+ TIMx->SCR |= TIM_TS_IC2_Set;\r
+\r
+ if(TIM_ExtCLKEdge == TIM_ExtCLKEdge_Falling)\r
+ /* Set the corresponding polarity */\r
+ {\r
+ TIMx->IMCR |= TIM_IC2P_Set;\r
+ }\r
+ else\r
+ {\r
+ TIMx->IMCR &= TIM_IC2P_Reset;\r
+ }\r
+ if(TIM_ClockSource == TIM_ClockSource_TI22)\r
+ {\r
+ /* External signal TI2 connected to IC2 channel */\r
+ TIMx->IMCR &= TIM_IC2S_Reset;\r
+ }\r
+ else\r
+ {\r
+ /* External signal TI1 connected to IC2 channel */\r
+ TIMx->IMCR |= TIM_IC2S_Set;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SetPrescaler\r
+* Description : Sets the TIM prescaler value.\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral\r
+* - Prescaler: TIM prescaler new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SetPrescaler(TIM_TypeDef* TIMx, u16 Prescaler)\r
+{\r
+ TIMx->PSC = Prescaler;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SetPeriod\r
+* Description : Sets the TIM period value.\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral\r
+* - Period: TIM period new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SetPeriod(TIM_TypeDef* TIMx, u16 Period)\r
+{\r
+ TIMx->ARR = Period;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SetPulse\r
+* Description : Sets the TIM pulse value.\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral\r
+* - TIM_Channel: specifies the TIM channel to be used.\r
+* This parameter can be one of the following values:\r
+* - TIM_Channel_1: TIM Channel 1 is used\r
+* - TIM_Channel_2: TIM Channel 2 is used\r
+* - TIM_Channel_ALL: TIM Channel 1and 2 are used\r
+* - Pulse: TIM pulse new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SetPulse(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 Pulse)\r
+{\r
+ /* Set Channel 1 pulse value */\r
+ if(TIM_Channel == TIM_Channel_1)\r
+ {\r
+ TIMx->OCR1 = Pulse;\r
+ }\r
+ /* Set Channel 2 pulse value */\r
+ else if(TIM_Channel == TIM_Channel_2)\r
+ {\r
+ TIMx->OCR2 = Pulse;\r
+ }\r
+ /* Set Channel 1 and Channel 2 pulse values */\r
+ else if(TIM_Channel == TIM_Channel_ALL)\r
+ {\r
+ TIMx->OCR1 = Pulse;\r
+ TIMx->OCR2 = Pulse;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_GetICAP1\r
+* Description : Gets the Input Capture 1 value. \r
+* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral\r
+* Output : None\r
+* Return : Input Capture 1 Register value.\r
+*******************************************************************************/\r
+u16 TIM_GetICAP1(TIM_TypeDef *TIMx)\r
+{\r
+ return TIMx->ICR1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_GetICAP2\r
+* Description : Gets the Input Capture 2 value.\r
+* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral\r
+* Output : None\r
+* Return : Input Capture 2 Register value\r
+*******************************************************************************/\r
+u16 TIM_GetICAP2(TIM_TypeDef *TIMx)\r
+{\r
+ return TIMx->ICR2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_GetPWMIPulse\r
+* Description : Gets the PWM Input pulse value.\r
+* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral\r
+* Output : None\r
+* Return : Input Capture 2 Register value\r
+*******************************************************************************/\r
+u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx)\r
+{\r
+ return TIMx->ICR2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_GetPWMIPeriod\r
+* Description : Gets the PWM Input period value.\r
+* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral\r
+* Output : None\r
+* Return : Input Capture 1 Register value\r
+*******************************************************************************/\r
+u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx)\r
+{\r
+ return TIMx->ICR1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_DebugCmd\r
+* Description : Enables or disables the specified TIM peripheral Debug control.\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral\r
+* - Newstate: new state of the TIMx Debug control.\r
+ This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_DebugCmd(TIM_TypeDef *TIMx, FunctionalState Newstate)\r
+{\r
+ if(Newstate == ENABLE)\r
+ {\r
+ TIMx->CR |= TIM_DBGC_Set;\r
+ }\r
+ else\r
+ {\r
+ TIMx->CR &= TIM_DBGC_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_CounterModeConfig\r
+* Description : Specifies the Counter Mode to be used.\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.\r
+* - TIM_CounterMode: specifies the Counter Mode to be used\r
+* This parameter can be one of the following values:\r
+* - TIM_CounterMode_Up: TIM Up Counting Mode\r
+* - TIM_CounterMode_Down: TIM Down Counting Mode\r
+* - TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1\r
+* - TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2\r
+* - TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode)\r
+{\r
+ /* Counter mode configuration */\r
+ TIMx->CR &= TIM_CounterMode_Mask;\r
+ TIMx->CR |= TIM_CounterMode;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ForcedOCConfig\r
+* Description : Forces the TIM output waveform to active or inactive level.\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.\r
+* - TIM_Channel: specifies the TIM channel to be used.\r
+* This parameter can be one of the following values:\r
+* - TIM_Channel_1: Timer Channel 1 is used\r
+* - TIM_Channel_2: Timer Channel 2 is used\r
+* - TIM_Channel_ALL: Timer Channel 1 and 2 are used\r
+* - TIM_ForcedAction: specifies the forced Action to be set to\r
+* the output waveform.\r
+* This parameter can be one of the following values:\r
+* - TIM_ForcedAction_Active: Force active level on OCxREF\r
+* - TIM_ForcedAction_InActive: Force inactive level on \r
+* OCxREF.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ForcedOCConfig(TIM_TypeDef* TIMx, u16 TIM_Channel,u16 TIM_ForcedAction)\r
+{\r
+ /* Channel 1 Forced Output Compare mode configuration */\r
+ if(TIM_Channel == TIM_Channel_1)\r
+ {\r
+ TIMx->OMR1 &= TIM_OC1C_Mask;\r
+ TIMx->OMR1 |= TIM_ForcedAction;\r
+ }\r
+ /* Channel 2 Forced Output Compare mode configuration */\r
+ else\r
+ {\r
+ if(TIM_Channel == TIM_Channel_2)\r
+ {\r
+ TIMx->OMR1 &= TIM_OC2C_Mask;\r
+ TIMx->OMR1 |= (TIM_ForcedAction<<8);\r
+ }\r
+ /* Channel 1 and Channel 2 Forced Output Compare mode configuration */\r
+ else\r
+ {\r
+ TIMx->OMR1 &= TIM_OC1C_Mask & TIM_OC2C_Mask;\r
+ TIMx->OMR1 |= TIM_ForcedAction |(TIM_ForcedAction<<8);\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ResetCounter\r
+* Description : Re-intializes the TIM counter and generates an update of the\r
+* registers.\r
+* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ResetCounter(TIM_TypeDef* TIMx)\r
+{\r
+ /* Re-intialize the TIM counter */\r
+ TIMx->CR |= TIM_COUNTER_Reset;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SynchroConfig\r
+* Description : Synchronizes two Timers in a specified mode.\r
+* Input : - Master: specifies the peripheral master.\r
+* This parameter can be one of the following values:\r
+* PWM_Master, TIM0_Master, TIM1_Master or TIM2_Master.\r
+* - Slave: specifies the peripheral slave.\r
+* This parameter can be one of the following values:\r
+* PWM_Slave, TIM0_Slave, TIM1_Slave or TIM2_Slave.\r
+* - TIM_SynchroAction: specifies the synchronization Action to \r
+* be used.\r
+* This parameter can be one of the following values:\r
+* - TIM_SynchroAction_Enable: The CNT_EN bit is used as TRGO\r
+* - TIM_SynchroAction_Update: The Update event is used as TRGO\r
+* - TIM_SynchroAction_Reset: The CNT_RST bit is used as TRGO\r
+* - TIM_SynchroAction_OC: The OC1 signal is used as TRGO\r
+* - TIM_SynchroMode: specifies the synchronization Mode to be used.\r
+* This parameter can be one of the following values:\r
+* - TIM_SynchroMode_Gated: Both start and stop of the \r
+* counter is controlled.\r
+* - TIM_SynchroMode_Trigger: Only the start of the \r
+* counter is controlled.\r
+* - TIM_SynchroMode_External: The rising edge of selected trigger \r
+* clocks the counter.\r
+* - TIM_SynchroMode_Reset: The rising edge of the selected trigger \r
+* signal resets the counter and generates an update of the registers.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SynchroConfig(Master_TypeDef Master, Slave_TypeDef Slave,\r
+ u16 TIM_SynchroAction, u16 TIM_SynchroMode)\r
+{\r
+ switch (Slave)\r
+ {\r
+ case PWM_Slave:\r
+ {\r
+ PWM->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask &\r
+ TIM_InternalTriggerSelection_Mask;\r
+ PWM->SCR |= TIM_SynchroMode | TIM_SME_Set;\r
+\r
+ if(Master == TIM1_Master)\r
+ {\r
+ /* Set the internal trigger */\r
+ PWM->SCR |= TIM_ITS_TIM1;\r
+\r
+ /* Set the synchronization action */\r
+ TIM1->CR &= TIM_MasterModeSelection_Mask;\r
+ TIM1->CR |= TIM_SynchroAction;\r
+ }\r
+\r
+ else if(Master == TIM0_Master)\r
+ {\r
+ /* Set the internal trigger */\r
+ PWM->SCR |= TIM_ITS_TIM0;\r
+\r
+ /* Set the synchronization action */\r
+ TIM0->CR &= TIM_MasterModeSelection_Mask;\r
+ TIM0->CR |= TIM_SynchroAction;\r
+ }\r
+\r
+ else if(Master == TIM2_Master)\r
+ {\r
+ /* Set the internal trigger */\r
+ PWM->SCR |= TIM_ITS_TIM2;\r
+\r
+ /* Set the synchronization action */\r
+ TIM2->CR &= TIM_MasterModeSelection_Mask;\r
+ TIM2->CR |= TIM_SynchroAction;\r
+ }\r
+ }\r
+ break;\r
+\r
+ case TIM0_Slave:\r
+ {\r
+ TIM0->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask &\r
+ TIM_InternalTriggerSelection_Mask;\r
+ TIM0->SCR |= TIM_SynchroMode | TIM_SME_Set;\r
+\r
+ if(Master == PWM_Master)\r
+ {\r
+ /* Set the internal trigger */\r
+ TIM0->SCR |= TIM_ITS_PWM;\r
+\r
+ /* Set the synchronization action */\r
+ PWM->CR &= TIM_MasterModeSelection_Mask;\r
+ PWM->CR |= TIM_SynchroAction;\r
+ }\r
+\r
+ else if(Master == TIM1_Master)\r
+ {\r
+ /* Set the internal trigger */\r
+ TIM0->SCR |= TIM_ITS_TIM1;\r
+\r
+ /* Set the synchronization action */\r
+ TIM1->CR &= TIM_MasterModeSelection_Mask;\r
+ TIM1->CR |= TIM_SynchroAction;\r
+ }\r
+\r
+ else if(Master == TIM2_Master)\r
+ {\r
+ /* Set the internal trigger */\r
+ TIM0->SCR |= TIM_ITS_TIM2;\r
+\r
+ /* Set the synchronization action */\r
+ TIM2->CR &= TIM_MasterModeSelection_Mask;\r
+ TIM2->CR |= TIM_SynchroAction;\r
+ }\r
+ }\r
+ break;\r
+\r
+ case TIM1_Slave:\r
+ {\r
+\r
+ TIM1->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask &\r
+ TIM_InternalTriggerSelection_Mask;\r
+ TIM1->SCR |= TIM_SynchroMode | TIM_SME_Set;\r
+ \r
+ if(Master == PWM_Master)\r
+ {\r
+ /* Set the internal trigger */\r
+ TIM1->SCR |= TIM_ITS_PWM;\r
+\r
+ /* Set the synchronization action */\r
+ PWM->CR &= TIM_MasterModeSelection_Mask;\r
+ PWM->CR |= TIM_SynchroAction;\r
+ }\r
+ else if(Master == TIM0_Master)\r
+ {\r
+ /* Set the internal trigger */\r
+ TIM1->SCR |= TIM_ITS_TIM0;\r
+\r
+ /* Set the synchronization action */\r
+ TIM0->CR &= TIM_MasterModeSelection_Mask;\r
+ TIM0->CR |= TIM_SynchroAction;\r
+ }\r
+\r
+ else if(Master == TIM2_Master)\r
+ {\r
+ /* Set the internal trigger */\r
+ TIM1->SCR |= TIM_ITS_TIM2;\r
+\r
+ /* Set the synchronization action */\r
+ TIM2->CR &= TIM_MasterModeSelection_Mask;\r
+ TIM2->CR |= TIM_SynchroAction;\r
+ }\r
+ }\r
+ break;\r
+\r
+ case TIM2_Slave:\r
+ {\r
+ \r
+ TIM2->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask &\r
+ TIM_InternalTriggerSelection_Mask;\r
+ TIM2->SCR |= TIM_SynchroMode | TIM_SME_Set;\r
+\r
+ if(Master == PWM_Master)\r
+ {\r
+ /* Internal trigger selection */\r
+ TIM2->SCR |= TIM_ITS_PWM;\r
+\r
+ /* Set the synchronization action */\r
+ PWM->CR &= TIM_MasterModeSelection_Mask;\r
+ PWM->CR |= TIM_SynchroAction;\r
+ }\r
+\r
+ else if(Master == TIM1_Master)\r
+ {\r
+ /* Internal trigger selection */\r
+ TIM2->SCR |= TIM_ITS_TIM1;\r
+\r
+ /* Set the synchronization action */\r
+ TIM1->CR &= TIM_MasterModeSelection_Mask;\r
+ TIM1->CR |= TIM_SynchroAction;\r
+ }\r
+\r
+ else if(Master == TIM0_Master)\r
+ {\r
+ /* Internal trigger selection */\r
+ TIM2->SCR |= TIM_ITS_TIM0;\r
+\r
+ /* Set the synchronization action */\r
+ TIM0->CR &= TIM_MasterModeSelection_Mask;\r
+ TIM0->CR |= TIM_SynchroAction;\r
+ }\r
+ }\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_GetFlagStatus\r
+* Description : Checks whether the specified TIM flag is set or not.\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.\r
+* - TIM_FLAG: specifies the flag to check. \r
+* This parameter can be one of the following values:\r
+* - TIM_FLAG_IC1: Input Capture 1 Flag\r
+* - TIM_FLAG_OC1: Output Compare 1 Flag\r
+* - TIM_FLAG_Update: Timer update Flag\r
+* - TIM_FLAG_IC2: Input Capture 2 Flag\r
+* - TIM_FLAG_OC2: Output Compare 2 Flag\r
+* Output : None\r
+* Return : The new state of TIM_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG)\r
+{\r
+ if((TIMx->ISR & TIM_FLAG) != RESET )\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ClearFlag\r
+* Description : Clears the TIMx's pending flags.\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.\r
+* - TIM_FLAG: specifies the flag bit to clear.\r
+* This parameter can be any combination of the following values:\r
+* - TIM_FLAG_IC1: Timer Input Capture 1 flag\r
+* - TIM_FLAG_OC1: Timer Output Compare 1 flag\r
+* - TIM_FLAG_Update: Timer update flag\r
+* - TIM_FLAG_IC2: Timer Input Capture 2 flag\r
+* - TIM_FLAG_OC2: Timer Output Compare 2 flag\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG)\r
+{\r
+ /* Clear the flags */\r
+ TIMx->ISR &= ~TIM_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_GetITStatus\r
+* Description : Checks whether the specified TIM interrupt has occurred or not.\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.\r
+* - TIM_IT: specifies the TIM interrupt source to check.\r
+* This parameter can be one of the following values:\r
+* - TIM_IT_IC1: Input Capture 1 interrupt\r
+* - TIM_IT_OC1: Output Compare 1 interrupt\r
+* - TIM_IT_Update: Timer update interrupt\r
+* - TIM_IT_GlobalUpdate: Timer global update interrupt\r
+* - TIM_IT_IC2: Input Capture 2 interrupt\r
+* - TIM_IT_OC2: Output Compare 2 interrupt\r
+* Output : None\r
+* Return : The new state of TIM_IT(SET or RESET).\r
+*******************************************************************************/\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT)\r
+{\r
+ u16 TIM_IT_Check = 0;\r
+\r
+ /* Calculates the pending bits to be checked */\r
+ TIM_IT_Check = TIM_IT & TIM_IT_Clear_Mask;\r
+ \r
+ if((TIMx->ISR & TIM_IT_Check) != RESET )\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ClearITPendingBit\r
+* Description : Clears the TIM's interrupt pending bits.\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.\r
+* - TIM_IT: specifies the interrupt pending bit to clear.\r
+* This parameter can be one of the following values:\r
+* - TIM_IT_IC1: Input Capture 1 Interrupt \r
+* - TIM_IT_OC1: Output Compare 1 Interrupt \r
+* - TIM_IT_Update: Timer update Interrupt \r
+* - TIM_IT_GlobalUpdate: Timer global update Interrupt \r
+* - TIM_IT_IC2: Input Capture 2 Interrupt \r
+* - TIM_IT_OC2: Output Compare 2 Interrupt \r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT)\r
+{\r
+ u16 TIM_IT_Clear = 0;\r
+\r
+ /* Calculate the pending bits to be cleared */\r
+ TIM_IT_Clear = TIM_IT & TIM_IT_Clear_Mask;\r
+\r
+ /* Clear the pending bits */\r
+ TIMx->ISR &= ~TIM_IT_Clear;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : OCM_ModuleConfig\r
+* Description : Output Compare Module configuration\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral\r
+* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that\r
+* contains the configuration information for the specified TIM\r
+* peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void OCM_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct)\r
+{\r
+ u16 TIM_OCControl = 0x0000;\r
+\r
+ if(TIM_InitStruct->TIM_Mode == TIM_Mode_OCTiming)\r
+ {\r
+ TIM_OCControl = TIM_OCControl_OCTiming;\r
+ }\r
+ else\r
+ {\r
+ if((TIM_InitStruct->TIM_Mode == TIM_Mode_OCActive) || \r
+ (TIM_InitStruct->TIM_Mode == TIM_Mode_OPM_Active))\r
+ {\r
+ TIM_OCControl = TIM_OCControl_OCActive;\r
+ }\r
+ else\r
+ {\r
+ if(TIM_InitStruct->TIM_Mode == TIM_Mode_OCInactive)\r
+ {\r
+ TIM_OCControl = TIM_OCControl_OCInactive;\r
+ }\r
+ else\r
+ {\r
+ if((TIM_InitStruct->TIM_Mode == TIM_Mode_OCToggle) ||\r
+ (TIM_InitStruct->TIM_Mode == TIM_Mode_OPM_Toggle))\r
+ {\r
+ TIM_OCControl = TIM_OCControl_OCToggle;\r
+ }\r
+ else\r
+ {\r
+ TIM_OCControl = TIM_OCControl_PWM;\r
+\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ if(TIM_InitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ /* Configure Channel 1 on Output Compare mode */\r
+ TIMx->OMR1 &= TIM_OC1C_Mask;\r
+ TIMx->OMR1 |= TIM_OCControl|TIM_OC1_Enable;\r
+ TIMx->OMR1 |= TIM_PLD1_Set;\r
+ TIMx->OCR1 = TIM_InitStruct->TIM_Pulse1;\r
+\r
+ /* Set the OC1 wave polarity */\r
+ if(TIM_InitStruct->TIM_Polarity1 == TIM_Polarity1_Low)\r
+ {\r
+ TIMx->OMR1 |= TIM_OC1P_Set;\r
+ }\r
+ else\r
+ {\r
+ TIMx->OMR1 &= TIM_OC1P_Reset;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(TIM_InitStruct->TIM_Channel == TIM_Channel_2)\r
+ {\r
+ /* Configure Channel 2 on Output Compare mode */\r
+ TIMx->OMR1 &= TIM_OC2C_Mask;\r
+ TIMx->OMR1 |= TIM_OCControl<<8|TIM_OC2_Enable;\r
+ TIMx->OMR1 |= TIM_PLD2_Set;\r
+ TIMx->OCR2 = TIM_InitStruct->TIM_Pulse2;\r
+\r
+ /* Set the OCB wave polarity */\r
+ if(TIM_InitStruct->TIM_Polarity2 == TIM_Polarity2_Low)\r
+ {\r
+ TIMx->OMR1 |= TIM_OC2P_Set;\r
+ }\r
+ else\r
+ {\r
+ TIMx->OMR1 &= TIM_OC2P_Reset;\r
+ }\r
+ }\r
+ /* Configure Channel 1 and Channel 2 on Output Compare mode */\r
+ else\r
+ {\r
+ TIMx->OMR1 &= TIM_OC1C_Mask & TIM_OC2C_Mask; \r
+ TIMx->OMR1 |= TIM_OCControl|(TIM_OCControl<<8)|TIM_OC1_Enable|TIM_OC2_Enable|\r
+ TIM_PLD1_Set|TIM_PLD2_Set;\r
+\r
+ TIMx->OCR1 = TIM_InitStruct->TIM_Pulse1;\r
+ TIMx->OCR2 = TIM_InitStruct->TIM_Pulse2;\r
+\r
+ /* Set the OC1 wave polarity */\r
+ if(TIM_InitStruct->TIM_Polarity1 == TIM_Polarity1_Low)\r
+ {\r
+ TIMx->OMR1 |= TIM_OC1P_Set;\r
+ }\r
+ else\r
+ {\r
+ TIMx->OMR1 &= TIM_OC1P_Reset;\r
+ }\r
+\r
+ /* Set the OC2 wave polarity */\r
+ if(TIM_InitStruct->TIM_Polarity2 == TIM_Polarity2_Low)\r
+ {\r
+ TIMx->OMR1 |= TIM_OC2P_Set;\r
+ }\r
+ else\r
+ {\r
+ TIMx->OMR1 &= TIM_OC2P_Reset;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ICAP_ModuleConfig\r
+* Description : Input Capture Module configuration\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral\r
+* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that\r
+* contains the configuration information for the specified TIM\r
+* peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void ICAP_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct)\r
+{\r
+ if(TIM_InitStruct->TIM_Mode == TIM_Mode_PWMI)\r
+ { /* PWM input mode configuration */\r
+ TIMx->SCR |= TIM_TS_IC1_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set;\r
+\r
+ /* Channel 1 and channel 2 input selection */\r
+ if(TIM_InitStruct->TIM_PWMI_ICSelection == TIM_PWMI_ICSelection_TI1)\r
+ {\r
+ TIMx->IMCR &= TIM_IC1S_Reset;\r
+ TIMx->IMCR |= TIM_IC2S_Set;\r
+ }\r
+ else\r
+ {\r
+ TIMx->IMCR |= TIM_IC1S_Set;\r
+ TIMx->IMCR &= TIM_IC2S_Reset;\r
+ }\r
+\r
+ /* Channel polarity */\r
+ if(TIM_InitStruct->TIM_PWMI_ICPolarity == TIM_PWMI_ICPolarity_Rising)\r
+ {\r
+ TIMx->IMCR &= TIM_IC1P_Reset;\r
+ TIMx->IMCR |= TIM_IC2P_Set;\r
+ }\r
+ else\r
+ {\r
+ TIMx->IMCR |= TIM_IC1P_Set;\r
+ TIMx->IMCR &= TIM_IC2P_Reset;\r
+ }\r
+\r
+ /* Input capture Enable */\r
+ TIMx->IMCR |= TIM_IC1_Enable |TIM_IC2_Enable;\r
+ }\r
+ else\r
+ {\r
+ if(TIM_InitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ /* Input Capture 1 mode configuration */\r
+ TIMx->SCR &= TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask;\r
+ TIMx->SCR |= TIM_TS_IC1_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set;\r
+ \r
+ /* Channel 1 input selection */\r
+ if(TIM_InitStruct->TIM_IC1Selection == TIM_IC1Selection_TI1)\r
+ {\r
+ TIMx->IMCR &= TIM_IC1S_Reset;\r
+ }\r
+ else\r
+ {\r
+ TIMx->IMCR |= TIM_IC1S_Set;\r
+ }\r
+ /* Channel 1 polarity */\r
+ if(TIM_InitStruct->TIM_IC1Polarity == TIM_IC1Polarity_Rising)\r
+ {\r
+ TIMx->IMCR &= TIM_IC1P_Reset;\r
+ }\r
+ else\r
+ {\r
+ TIMx->IMCR |= TIM_IC1P_Set;\r
+ }\r
+\r
+ /* Input capture Enable */\r
+ TIMx->IMCR |= TIM_IC1_Enable;\r
+ }\r
+ else\r
+ {\r
+ /* Input Capture 2 mode configuration */\r
+ TIMx->SCR &= (TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask);\r
+ TIMx->SCR |= TIM_TS_IC2_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set;\r
+\r
+ /* Channel 2 input selection */\r
+ if(TIM_InitStruct->TIM_IC2Selection == TIM_IC2Selection_TI2)\r
+ {\r
+ TIMx->IMCR &= TIM_IC2S_Reset;\r
+ }\r
+ else\r
+ {\r
+ TIMx->IMCR |= TIM_IC2S_Set;\r
+ }\r
+\r
+ /* Channel 2 polarity */\r
+ if(TIM_InitStruct->TIM_IC2Polarity == TIM_IC2Polarity_Rising)\r
+ {\r
+ TIMx->IMCR &= TIM_IC2P_Reset;\r
+ }\r
+ else\r
+ {\r
+ TIMx->IMCR |= TIM_IC2P_Set;\r
+ }\r
+\r
+ /* Input capture Enable */\r
+ TIMx->IMCR |= TIM_IC2_Enable;\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : Encoder_ModeConfig\r
+* Description : Encoder Mode configuration\r
+* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral\r
+* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that\r
+* contains the configuration information for the specified TIM\r
+* peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void Encoder_ModeConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct)\r
+{\r
+ /* Set Encoder mode */\r
+ TIMx->SCR &= TIM_Encoder_Mask;\r
+ \r
+ if(TIM_InitStruct->TIM_Mode == TIM_Mode_Encoder1) \r
+ {\r
+ TIMx->SCR |= TIM_Encoder1_Set;\r
+ }\r
+ else if (TIM_InitStruct->TIM_Mode == TIM_Mode_Encoder2)\r
+ {\r
+ TIMx->SCR |= TIM_Encoder2_Set;\r
+ }\r
+ else \r
+ {\r
+ TIMx->SCR |= TIM_Encoder3_Set;\r
+ }\r
+\r
+ /* Channel 1 input selection */\r
+ if(TIM_InitStruct->TIM_IC1Selection == TIM_IC1Selection_TI2)\r
+ {\r
+ TIMx->IMCR |= TIM_IC1S_Set;\r
+ }\r
+ else\r
+ {\r
+ TIMx->IMCR &= TIM_IC1S_Reset;\r
+ }\r
+\r
+ /* Channel 2 input selection */\r
+ if(TIM_InitStruct->TIM_IC2Selection == TIM_IC2Selection_TI1)\r
+ {\r
+ TIMx->IMCR |= TIM_IC2S_Set;\r
+ }\r
+ else\r
+ {\r
+ TIMx->IMCR &= TIM_IC2S_Reset;\r
+ }\r
+\r
+ /* Channel 1 polarity */\r
+ if(TIM_InitStruct->TIM_IC1Polarity == TIM_IC1Polarity_Falling)\r
+ {\r
+ TIMx->IMCR |= TIM_IC1P_Set;\r
+ }\r
+ else\r
+ {\r
+ TIMx->IMCR &= TIM_IC1P_Reset;\r
+ }\r
+\r
+ /* Channel 2 polarity */\r
+ if(TIM_InitStruct->TIM_IC2Polarity == TIM_IC2Polarity_Falling)\r
+ {\r
+ TIMx->IMCR |= TIM_IC2P_Set;\r
+ }\r
+ else\r
+ {\r
+ TIMx->IMCR &= TIM_IC2P_Reset;\r
+ }\r
+}\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_uart.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file provides all the UART software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_uart.h"\r
+#include "75x_mrcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* UART LIN Mask */\r
+#define UART_LIN_Disable_Mask 0xFEFF /* LIN Disable Mask */\r
+#define UART_LIN_Enable_Mask 0x0100 /* LIN Enable Mask */\r
+\r
+/* UART Mask */\r
+#define UART_Enable_Mask 0x0001 /* UART Enable Mask */\r
+#define UART_Disable_Mask 0xFFFE /* UART Disable Mask */\r
+\r
+/* UART LoopBack */\r
+#define UART_LoopBack_Disable_Mask 0xFF7F/* LoopBack Disable Mask */\r
+#define UART_LoopBack_Enable_Mask 0x0080/* LoopBack Enable Mask */\r
+\r
+#define UART_WordLength_Mask 0xFF9F /* UART Word Length Mask */\r
+#define UART_Parity_Mask 0xFF79 /* UART Parity Mask */\r
+#define UART_HardwareFlowControl_Mask 0x3FFF /* UART Hardware Flow Control Mask */\r
+#define UART_TxRxFIFOLevel_Mask 0xFFC0 /* UART Tx Rx FIFO Level Mask */\r
+#define UART_LINBreakLength_Mask 0xE1FF /* UART LIN Break Length Mask */\r
+#define UART_BreakChar_Mask 0x0001 /* UART Break Character send Mask */\r
+#define UART_FLAG_Mask 0x1F /* UART Flag Mask */\r
+#define UART_Mode_Mask 0xFCFF /* UART Mode Mask */\r
+#define UART_RTSSET_Mask 0xF7FF /* RTS signal is high */\r
+#define UART_RTSRESET_Mask 0x0800 /* RTS signal is low */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_DeInit\r
+* Description : Deinitializes the UARTx peripheral registers to their default\r
+* reset values.\r
+* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_DeInit(UART_TypeDef* UARTx)\r
+{\r
+ /* Reset the UARTx registers values */\r
+ if(UARTx == UART0)\r
+ {\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART0,ENABLE);\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART0,DISABLE);\r
+ }\r
+ else if(UARTx == UART1)\r
+ {\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART1,ENABLE);\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART1,DISABLE);\r
+ }\r
+ else if(UARTx == UART2)\r
+ {\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART2,ENABLE);\r
+ MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART2,DISABLE);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_Init\r
+* Description : Initializes the UARTx peripheral according to the specified\r
+* parameters in the UART_InitStruct .\r
+* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.\r
+* - UART_InitStruct: pointer to a UART_InitTypeDef structure\r
+* that contains the configuration information for the\r
+* specified UART peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct)\r
+{\r
+\r
+ u32 APBClock = 0;\r
+ u32 IntegerDivider = 0;\r
+ u32 FractionalDivider = 0;\r
+ MRCC_ClocksTypeDef MRCC_ClocksStatus;\r
+ \r
+ /* Clear the WLEN bits */\r
+ UARTx->LCR &= UART_WordLength_Mask;\r
+ /* Set the WLEN bits according to UART_WordLength value */\r
+ UARTx->LCR |= UART_InitStruct->UART_WordLength;\r
+\r
+ /* Choose Stop Bits */\r
+ if(UART_InitStruct->UART_StopBits == UART_StopBits_1)\r
+ {\r
+ /* One Stop Bit */\r
+ UARTx->LCR &= UART_StopBits_1;\r
+ }\r
+ else\r
+ {\r
+ /* Two Stop Bits */\r
+ UARTx->LCR |= UART_StopBits_2;\r
+ }\r
+\r
+ /* Clear SPS, EPS and PEN bits */\r
+ UARTx->LCR &= UART_Parity_Mask;\r
+ /* Set PS, EPS and PEN bits according to UART_Parity value */\r
+ UARTx->LCR |= UART_InitStruct->UART_Parity;\r
+\r
+ /* Configure the BaudRate --------------------------------------------------*/\r
+ /* Get the APB frequency */\r
+ MRCC_GetClocksStatus(&MRCC_ClocksStatus);\r
+ APBClock = MRCC_ClocksStatus.PCLK_Frequency;\r
+ \r
+ /* Determine the integer part */\r
+ IntegerDivider = ((100) * (APBClock) / (16 * (UART_InitStruct->UART_BaudRate)));\r
+ UARTx->IBRD = IntegerDivider / 100; \r
+\r
+ /* Determine the fractional part */\r
+ FractionalDivider = IntegerDivider - (100 * (UARTx->IBRD));\r
+ UARTx->FBRD = ((((FractionalDivider * 64) + 50) / 100));\r
+ \r
+ /* Choose the Hardware Flow Control */\r
+ /* Clear RTSEn and CTSEn bits */\r
+ UARTx->CR &= UART_HardwareFlowControl_Mask;\r
+ /* Set RTSEn and CTSEn bits according to UART_HardwareFlowControl value */\r
+ UARTx->CR |= UART_InitStruct->UART_HardwareFlowControl;\r
+\r
+ /* Configure the UART mode */\r
+ /* Clear TXE and RXE bits */\r
+ UARTx->CR &= UART_Mode_Mask;\r
+ /* Set TXE and RXE bits according to UART_Mode value */\r
+ UARTx->CR |= UART_InitStruct->UART_Mode;\r
+\r
+ /* Enable or disable the FIFOs */\r
+ /* Set the FIFOs Levels */\r
+ if(UART_InitStruct->UART_FIFO == UART_FIFO_Enable)\r
+ {\r
+ /* Enable the FIFOs */\r
+ UARTx->LCR |= UART_FIFO_Enable;\r
+ \r
+ /* Clear TXIFLSEL and RXIFLSEL bits */\r
+ UARTx->IFLS &= UART_TxRxFIFOLevel_Mask;\r
+ \r
+ /* Set RXIFLSEL bits according to UART_RxFIFOLevel value */\r
+ UARTx->IFLS |= (UART_InitStruct->UART_RxFIFOLevel << 3);\r
+ \r
+ /* Set TXIFLSEL bits according to UART_TxFIFOLevel value */\r
+ UARTx->IFLS |= UART_InitStruct->UART_TxFIFOLevel;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the FIFOs */\r
+ UARTx->LCR &= UART_FIFO_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_StructInit\r
+* Description : Fills each UART_InitStruct member with its default value.\r
+* Input : UART_InitStruct: pointer to a UART_InitTypeDef structure which\r
+* will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_StructInit(UART_InitTypeDef* UART_InitStruct)\r
+{\r
+ /* UART_InitStruct members default value */\r
+ UART_InitStruct->UART_WordLength = UART_WordLength_8D;\r
+ UART_InitStruct->UART_StopBits = UART_StopBits_1;\r
+ UART_InitStruct->UART_Parity = UART_Parity_Odd ;\r
+ UART_InitStruct->UART_BaudRate = 9600;\r
+ UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None;\r
+ UART_InitStruct->UART_Mode = UART_Mode_Tx_Rx;\r
+ UART_InitStruct->UART_FIFO = UART_FIFO_Enable;\r
+ UART_InitStruct->UART_TxFIFOLevel = UART_FIFOLevel_1_2;\r
+ UART_InitStruct->UART_RxFIFOLevel = UART_FIFOLevel_1_2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_Cmd\r
+* Description : Enables or disables the specified UART peripheral.\r
+* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral\r
+* - NewState: new state of the UARTx peripheral.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState)\r
+{\r
+ if (NewState == ENABLE)\r
+ {\r
+ /* Enable the selected UART by setting the UARTEN bit in the CR register */\r
+ UARTx->CR |= UART_Enable_Mask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected UART by clearing the UARTEN bit in the CR register */\r
+ UARTx->CR &= UART_Disable_Mask;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_ITConfig\r
+* Description : Enables or disables the specified UART interrupts.\r
+* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral\r
+* - UART_IT: specifies the UART interrupts sources to be \r
+* enabled or disabled. This parameter can be any combination \r
+* of the following values: \r
+* - UART_IT_OverrunError: Overrun Error interrupt\r
+* - UART_IT_BreakError: Break Error interrupt\r
+* - UART_IT_ParityError: Parity Error interrupt\r
+* - UART_IT_FrameError: Frame Error interrupt\r
+* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt\r
+* - UART_IT_Transmit: Transmit interrupt\r
+* - UART_IT_Receive: Receive interrupt\r
+* - UART_IT_CTS: CTS interrupt \r
+* - NewState: new state of the UARTx peripheral.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Enables the selected interrupts */\r
+ UARTx->IMSC |= UART_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disables the selected interrupts */\r
+ UARTx->IMSC &= ~UART_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_DMAConfig\r
+* Description : Configures the UART0 DMA interface.\r
+* Input : - UART0_DMAtransfer : specifies the configuration of DMA request.\r
+* This parameter can be:\r
+* - UART0_DMATransfer_Single: Single DMA transfer\r
+* - UART0_DMATransfer_Burst: Burst DMA transfer\r
+* - UART0_DMAOnError: specifies the DMA on error request.\r
+* This parameter can be:\r
+* - UART0_DMAOnError_Enable: DMA receive request enabled\r
+* when the UART error interrupt is asserted.\r
+* - UART0_DMAOnError_Disable: DMA receive request disabled\r
+* when the UART error interrupt is asserted.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_DMAConfig(u16 UART0_DMATransfer, u16 UART0_DMAOnError)\r
+{\r
+ if(UART0_DMATransfer == UART0_DMATransfer_Single)\r
+ {\r
+ /* Configure the DMA request from the UART0 as single transfer */\r
+ UART0->DMACR &= UART0_DMATransfer_Single;\r
+ }\r
+ else\r
+ {\r
+ UART0->DMACR |= UART0_DMATransfer_Burst;\r
+ }\r
+ \r
+ if(UART0_DMAOnError == UART0_DMAOnError_Enable)\r
+ {\r
+ UART0->DMACR &= UART0_DMAOnError_Enable;\r
+ }\r
+ else\r
+ {\r
+ UART0->DMACR |= UART0_DMAOnError_Disable;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_DMACmd\r
+* Description : Enables or disables the UART0\92s DMA interface.\r
+* Input : - UART0_DMAReq: specifies the DMA request.\r
+* This parameter can be:\r
+* - UART0_DMAReq_Tx: Transmit DMA request\r
+* - UART0_DMAReq_Rx: Receive DMA request\r
+* - NewState: new state of the UART0\92s DMA request.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_DMACmd(u16 UART0_DMAReq, FunctionalState NewState)\r
+{\r
+ if(UART0_DMAReq == UART0_DMAReq_Tx)\r
+ {\r
+ if(NewState == ENABLE)\r
+ {\r
+ UART0->DMACR |= UART0_DMAReq_Tx;\r
+ }\r
+ else\r
+ {\r
+ UART0->DMACR &= ~UART0_DMAReq_Tx;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(NewState == ENABLE)\r
+ {\r
+ UART0->DMACR |= UART0_DMAReq_Rx;\r
+ }\r
+ else\r
+ {\r
+ UART0->DMACR &= ~UART0_DMAReq_Rx;\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_LoopBackConfig\r
+* Description : Enables or disables LoopBack mode in UARTx.\r
+* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral\r
+* - NewState: new state of the UARTx\92s LoopBack mode.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState)\r
+{\r
+ if (NewState == ENABLE)\r
+ {\r
+ /* Enable the LoopBack mode of the specified UART */\r
+ UARTx->CR |= UART_LoopBack_Enable_Mask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the LoopBack mode of the specified UART */\r
+ UARTx->CR &= UART_LoopBack_Disable_Mask;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_LINConfig\r
+* Description : Sets the LIN break length.\r
+* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral.\r
+* - UART_LINBreakLength: Break length value.\r
+* This parameter can be:\r
+* - UART_LINBreakLength_10: 10 low bits\r
+* - UART_LINBreakLength_11: 11 low bits\r
+* - UART_LINBreakLength_12: 12 low bits\r
+* - UART_LINBreakLength_13: 13 low bits\r
+* - UART_LINBreakLength_14: 14 low bits\r
+* - UART_LINBreakLength_15: 15 low bits\r
+* - UART_LINBreakLength_16: 16 low bits\r
+* - UART_LINBreakLength_17: 17 low bits\r
+* - UART_LINBreakLength_18: 18 low bits\r
+* - UART_LINBreakLength_19: 19 low bits\r
+* - UART_LINBreakLength_20: 20 low bits\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_LINConfig(UART_TypeDef* UARTx, u16 UART_LINBreakLength)\r
+{\r
+ /* Clear LBKLEN bits */\r
+ UARTx->LCR &= UART_LINBreakLength_Mask;\r
+\r
+ /* Set LBKLEN bits according to UART_LINBreakLength value */\r
+ UARTx->LCR |= UART_LINBreakLength;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_LINCmd\r
+* Description : Enables or disables LIN master mode in UARTx.\r
+* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral\r
+* - NewState: new state of the UARTx\92s LIN interface. \r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_LINCmd(UART_TypeDef* UARTx, FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Enable the LIN mode of the specified UART */\r
+ UARTx->LCR |= UART_LIN_Enable_Mask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the LIN mode of the specified UART */\r
+ UARTx->LCR &= UART_LIN_Disable_Mask;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_SendData\r
+* Description : Transmits a signle Byte of data through the UARTx peripheral.\r
+* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral.\r
+* - Data: the byte to transmit\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_SendData(UART_TypeDef* UARTx, u8 Data)\r
+{\r
+ /* Transmit one byte */\r
+ UARTx->DR = Data;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_ReceiveData\r
+* Description : Returns the most recent received Byte by the UARTx peripheral.\r
+* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral.\r
+* Output : None\r
+* Return : The received data\r
+*******************************************************************************/\r
+u8 UART_ReceiveData(UART_TypeDef* UARTx)\r
+{\r
+ /* Receive one byte */\r
+ return ((u8)UARTx->DR);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_SendBreak\r
+* Description : Transmits break characters.\r
+* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_SendBreak(UART_TypeDef* UARTx)\r
+{\r
+ /* Send break characters */\r
+ UARTx->BKR |= UART_BreakChar_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_RTSConfig\r
+* Description : Sets or Resets the RTS signal\r
+* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral.\r
+* - RTSState: new state of the RTS signal.\r
+* This parameter can be: RTSSET or RTSRESET\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_RTSConfig(UART_TypeDef* UARTx, UART_RTSTypeDef RTSState)\r
+{\r
+ if(RTSState == RTSRESET)\r
+ {\r
+ UARTx->CR |= UART_RTSRESET_Mask;\r
+ }\r
+ else if(RTSState == RTSSET)\r
+ {\r
+ UARTx->CR &= UART_RTSSET_Mask;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_GetFlagStatus\r
+* Description : Checks whether the specified UART flag is set or not.\r
+* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral\r
+* - UART_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - UART_FLAG_OverrunError: Overrun error flag\r
+* - UART_FLAG_Break: break error flag\r
+* - UART_FLAG_ParityError: parity error flag\r
+* - UART_FLAG_FrameError: frame error flag\r
+* - UART_FLAG_TxFIFOEmpty: Transmit FIFO Empty flag\r
+* - UART_FLAG_RxFIFOFull: Receive FIFO Full flag\r
+* - UART_FLAG_TxFIFOFull: Transmit FIFO Full flag\r
+* - UART_FLAG_RxFIFOEmpty: Receive FIFO Empty flag\r
+* - UART_FLAG_Busy: Busy flag\r
+* - UART_FLAG_CTS: CTS flag\r
+* - UART_RawIT_OverrunError: Overrun Error interrupt flag\r
+* - UART_RawIT_BreakError: Break Error interrupt flag\r
+* - UART_RawIT_ParityError: Parity Error interrupt flag\r
+* - UART_RawIT_FrameError: Frame Error interrupt flag\r
+* - UART_RawIT_ReceiveTimeOut: ReceiveTimeOut interrupt flag\r
+* - UART_RawIT_Transmit: Transmit interrupt flag\r
+* - UART_RawIT_Receive: Receive interrupt flag\r
+* - UART_RawIT_CTS: CTS interrupt flag\r
+* Output : None\r
+* Return : The new state of UART_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG)\r
+{\r
+ u32 UARTReg = 0, FlagPos = 0;\r
+ u32 StatusReg = 0;\r
+\r
+ /* Get the UART register index */\r
+ UARTReg = UART_FLAG >> 5;\r
+\r
+ /* Get the flag position */\r
+ FlagPos = UART_FLAG & UART_FLAG_Mask;\r
+\r
+ if(UARTReg == 1) /* The flag to check is in RSR register */\r
+ {\r
+ StatusReg = UARTx->RSR;\r
+ }\r
+ else if (UARTReg == 2) /* The flag to check is in FR register */\r
+ {\r
+ StatusReg = UARTx->FR;\r
+ }\r
+ else if(UARTReg == 3) /* The flag to check is in RIS register */\r
+ {\r
+ StatusReg = UARTx->RIS;\r
+ }\r
+\r
+ if((StatusReg & (1 << FlagPos))!= RESET)\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_ClearFlag\r
+* Description : Clears the UARTx\92s pending flags.\r
+* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.\r
+* - UART_FLAG: specifies the flag to clear.\r
+* This parameter can be one of the following values:\r
+* - UART_FLAG_OverrunError: Overrun error flag\r
+* - UART_FLAG_Break: break error flag\r
+* - UART_FLAG_ParityError: parity error flag\r
+* - UART_FLAG_FrameError: frame error flag\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_ClearFlag(UART_TypeDef* UARTx, u16 UART_FLAG)\r
+{\r
+ u8 FlagPos = 0;\r
+\r
+ /* Get the flag position */\r
+ FlagPos = UART_FLAG & UART_FLAG_Mask;\r
+\r
+ /* Clear the sepecified flag */\r
+ UARTx->RSR &= ~(1 << FlagPos);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_GetITStatus\r
+* Description : Checks whether the specified UART interrupt has occurred or not.\r
+* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.\r
+* - UART_IT: specifies the interrupt source to check.\r
+* This parameter can be one of the following values:\r
+* - UART_IT_OverrunError: Overrun Error interrupt \r
+* - UART_IT_BreakError: Break Error interrupt \r
+* - UART_IT_ParityError: Parity Error interrupt \r
+* - UART_IT_FrameError: Frame Error interrupt \r
+* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt \r
+* - UART_IT_Transmit: Transmit interrupt \r
+* - UART_IT_Receive: Receive interrupt \r
+* - UART_IT_CTS: CTS interrupt \r
+* Output : None\r
+* Return : The new state of UART_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT)\r
+{\r
+ if((UARTx->MIS & UART_IT) != RESET)\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : UART_ClearITPendingBit\r
+* Description : Clears the UARTx\92s interrupt pending bits.\r
+* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.\r
+* - UART_IT: specifies the interrupt pending bit to clear.\r
+* More than one interrupt can be cleared using the \93|\94 operator.\r
+* This parameter can be:\r
+* - UART_IT_OverrunError: Overrun Error interrupt\r
+* - UART_IT_BreakError: Break Error interrupt\r
+* - UART_IT_ParityError: Parity Error interrupt\r
+* - UART_IT_FrameError: Frame Error interrupt\r
+* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt\r
+* - UART_IT_Transmit: Transmit interrupt\r
+* - UART_IT_Receive: Receive interrupt\r
+* - UART_IT_CTS: CTS interrupt\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT)\r
+{\r
+ /* Clear the specified interrupt */\r
+ UARTx->ICR = UART_IT;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : 75x_wdg.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file provides all the WDG software functions.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "75x_wdg.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Registers reset value */\r
+#define WDG_Preload_Mask 0xFFFF\r
+#define WDG_Prescaler_Mask 0xFF\r
+\r
+/* WDG Start/Stop counter */\r
+#define WDG_Counter_Start_Mask 0x0002\r
+#define WDG_Counter_Stop_Mask 0xFFFD\r
+\r
+/* WDG Sequence */\r
+#define WDG_KeyValue1_Mask 0xA55A\r
+#define WDG_KeyValue2_Mask 0x5AA5\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/******************************************************************************\r
+* Function Name : WDG_DeInit\r
+* Description : Deinitializes the WDG peripheral registers to their default \r
+* reset values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void WDG_DeInit(void)\r
+{\r
+ /* Reset all the WDG registers */\r
+ WDG->CR = 0x0000;\r
+ WDG->PR = 0x00FF;\r
+ WDG->VR = 0xFFFF;\r
+ WDG->CNT = 0xFFFF;\r
+ WDG->SR = 0x0000;\r
+ WDG->MR = 0x0000;\r
+ WDG->KR = 0x0000;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_Init\r
+* Description : Initializes WDG peripheral according to the specified\r
+* parameters in the WDG_InitStruct.\r
+* Input : WDG_InitStruct: pointer to a WDG_InitTypeDef structure that\r
+* contains the configuration information for the WDG peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void WDG_Init(WDG_InitTypeDef* WDG_InitStruct)\r
+{\r
+ /* Configure WDG Prescaler register value */\r
+ WDG->PR = WDG_InitStruct->WDG_Prescaler;\r
+\r
+ /* Configure WDG Pre-load register value */\r
+ WDG->VR = WDG_InitStruct->WDG_Preload ;\r
+ \r
+ if(WDG_InitStruct->WDG_Mode == WDG_Mode_WDG)\r
+ {\r
+ /* Select WDG mode */\r
+ WDG->CR |= WDG_Mode_WDG ;\r
+ }\r
+ else\r
+ {\r
+ /* Select Timer mode */\r
+ WDG->CR &= WDG_Mode_Timer; \r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_StructInit\r
+* Description : Fills each WDG_InitStruct member with its default value.\r
+* Input : WDG_InitStruct : pointer to a WDG_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void WDG_StructInit(WDG_InitTypeDef *WDG_InitStruct)\r
+{\r
+ /* Initialize mode */\r
+ WDG_InitStruct->WDG_Mode = WDG_Mode_Timer;\r
+\r
+ /* Initialize Preload */\r
+ WDG_InitStruct->WDG_Preload = WDG_Preload_Mask ;\r
+\r
+ /* Initialize Prescaler */\r
+ WDG_InitStruct->WDG_Prescaler = WDG_Prescaler_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_Cmd\r
+* Description : Enables or disables the WDG peripheral.\r
+* Input : NewState: new state of the WDG peripheral. \r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void WDG_Cmd(FunctionalState NewState)\r
+{\r
+ if((WDG->CR & WDG_Mode_WDG) == 0)\r
+ {\r
+ /* Timer mode */\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Start timer by setting SC bit in Control register */\r
+ WDG->CR |= WDG_Counter_Start_Mask;\r
+ }\r
+ else \r
+ {\r
+ /* Stop timer by clearing SC bit in Control register */\r
+ WDG->CR &= WDG_Counter_Stop_Mask;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Watchdog mode */\r
+ if(NewState == ENABLE)\r
+ {\r
+ WDG->KR = WDG_KeyValue1_Mask;\r
+ WDG->KR = WDG_KeyValue2_Mask;\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_ITConfig\r
+* Description : Enables or disables the WDG End of Count(EC) interrupt.\r
+* Input : Newstate: new state of the WDG End of Count(EC) interrupt.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void WDG_ITConfig(FunctionalState NewState)\r
+{\r
+ if(NewState == ENABLE)\r
+ {\r
+ /* Enable the End of Count interrupt */\r
+ WDG->MR |= WDG_IT_EC;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the End of Count interrupt */\r
+ WDG->MR &= ~WDG_IT_EC;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_GetCounter\r
+* Description : Gets the WDG\92s current counter value.\r
+* Input : None\r
+* Output : None\r
+* Return : The WDG current counter value\r
+*******************************************************************************/\r
+u16 WDG_GetCounter(void)\r
+{\r
+ return WDG->CNT;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_GetFlagStatus\r
+* Description : Checks whether the WDG End of Count(EC) flag is set or not.\r
+* Input : None\r
+* Output : None\r
+* Return : The new state of WDG End of Count(EC) flag (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus WDG_GetFlagStatus(void)\r
+{\r
+ if((WDG->SR & WDG_FLAG_EC) != RESET )\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_ClearFlag\r
+* Description : Clears the WDG\92s End of Count(EC) pending flag. \r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void WDG_ClearFlag(void)\r
+{\r
+ /* Clear the EC pending bit */\r
+ WDG->SR &= ~WDG_FLAG_EC;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_GetITStatus\r
+* Description : Checks whether the WDG End of Count(EC) interrupt has \r
+* occurred or not.\r
+* Input : None\r
+* Output : None\r
+* Return : The new state of WDG End of Count(EC) interrupt (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus WDG_GetITStatus(void)\r
+{\r
+ if(((WDG->SR & WDG_IT_EC) != RESET )&&((WDG->MR & WDG_IT_EC) != RESET ))\r
+ {\r
+ return SET;\r
+ }\r
+ else\r
+ {\r
+ return RESET;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WDG_ClearITPendingBit\r
+* Description : Clears the WDG's End of Count(EC) interrupt pending bit.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void WDG_ClearITPendingBit(void)\r
+{\r
+ /* Clear the EC pending bit */\r
+ WDG->SR &= ~WDG_IT_EC;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************\r
+* File Name : lcd.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 03/10/2006\r
+* Description : This file includes the LCD driver for GXM12232-2SL liquid\r
+* Crystal Display Module of STR75x-EVAL.\r
+********************************************************************************\r
+* History:\r
+* 07/17/2006 : V1.0\r
+* 03/10/2006 : V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "lcd.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+\r
+ /* Peripherals InitStructure define */\r
+GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+#define LCD_GPIO_Pins 0x3FC00\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+ /* Global variable to set the written text color: used for LCD_Printf */\r
+ TextColorMode_TypeDef TextMode = BlackText;\r
+\r
+ /* ASCII Table: each character is 7 column (7dots large) on two pages (16dots high) */\r
+ /* 7 column character: Two 8bit data to display one column*/\r
+ const u8 AsciiDotsTable[1778] = {\r
+ /* ASCII 0 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 1 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 2 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 3 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 4 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 5 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 6 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 7 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 8 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 9 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 10 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 11 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 12 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 13 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 14 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 15 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 16 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 17 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 18 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 19 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 20 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 21 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 22 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 23 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 24 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 25 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 26 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 27 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00,\r
+ /* ASCII 28 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 29 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 30 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 31 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 32 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 33 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x13,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 34 */ 0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00,\r
+ /* ASCII 35 */ 0x00,0x00,0x35,0x00,0x0f,0x80,0x35,0x60,0x0f,0x80,0x05,0x60,0x00,0x00,\r
+ /* ASCII 36 */ 0x00,0x00,0x0d,0x80,0x0a,0x40,0x3a,0x60,0x06,0x40,0x00,0x00,0x00,0x00,\r
+ /* ASCII 37 */ 0x00,0x00,0x02,0x40,0x02,0xa0,0x0a,0x40,0x15,0x00,0x09,0x00,0x00,0x00,\r
+ /* ASCII 38 */ 0x00,0x00,0x0c,0x00,0x13,0x00,0x14,0x80,0x08,0x80,0x14,0x00,0x00,0x00,\r
+ /* ASCII 39 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 40 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x1f,0x80,0x60,0x60,0x00,0x00,0x00,0x00,\r
+ /* ASCII 41 */ 0x00,0x00,0x00,0x00,0x60,0x60,0x1f,0x80,0x00,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 42 */ 0x00,0x00,0x00,0x40,0x03,0x40,0x00,0xe0,0x03,0x40,0x00,0x40,0x00,0x00,\r
+ /* ASCII 43 */ 0x02,0x00,0x02,0x00,0x02,0x00,0x1f,0xc0,0x02,0x00,0x02,0x00,0x02,0x00,\r
+ /* ASCII 44 */ 0x00,0x00,0x00,0x00,0x60,0x00,0x38,0x00,0x08,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 45 */ 0x00,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x00,0x00,\r
+ /* ASCII 46 */ 0x00,0x00,0x00,0x00,0x18,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 47 */ 0x00,0x00,0x20,0x00,0x18,0x00,0x06,0x00,0x01,0x80,0x00,0x60,0x00,0x00,\r
+ /* ASCII 48 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00,\r
+ /* ASCII 49 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00,\r
+ /* ASCII 50 */ 0x00,0x00,0x18,0x40,0x14,0x20,0x12,0x20,0x11,0x20,0x18,0xc0,0x00,0x00,\r
+ /* ASCII 51 */ 0x00,0x00,0x08,0x40,0x10,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00,\r
+ /* ASCII 52 */ 0x00,0x00,0x06,0x00,0x05,0x00,0x04,0xc0,0x14,0x20,0x1f,0xe0,0x14,0x00,\r
+ /* ASCII 53 */ 0x00,0x00,0x08,0x00,0x11,0xe0,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00,\r
+ /* ASCII 54 */ 0x00,0x00,0x0f,0x80,0x11,0x40,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00,\r
+ /* ASCII 55 */ 0x00,0x00,0x00,0x60,0x00,0x20,0x18,0x20,0x07,0x20,0x00,0xe0,0x00,0x00,\r
+ /* ASCII 56 */ 0x00,0x00,0x0e,0xc0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00,\r
+ /* ASCII 57 */ 0x00,0x00,0x11,0xc0,0x12,0x20,0x12,0x20,0x0a,0x20,0x07,0xc0,0x00,0x00,\r
+ /* ASCII 58 */ 0x00,0x00,0x00,0x00,0x19,0x80,0x19,0x80,0x00,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 59 */ 0x00,0x00,0x00,0x00,0x30,0x00,0x19,0x80,0x09,0x80,0x00,0x00,0x00,0x00,\r
+ /* ASCII 60 */ 0x02,0x00,0x05,0x00,0x05,0x00,0x08,0x80,0x10,0x40,0x10,0x40,0x00,0x00,\r
+ /* ASCII 61 */ 0x00,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x00,0x00,\r
+ /* ASCII 62 */ 0x10,0x40,0x10,0x40,0x08,0x80,0x05,0x00,0x05,0x00,0x02,0x00,0x00,0x00,\r
+ /* ASCII 63 */ 0x00,0x00,0x00,0x00,0x10,0x80,0x14,0x40,0x02,0x40,0x01,0x80,0x00,0x00,\r
+ /* ASCII 64 */ 0x00,0x00,0x1f,0xe0,0x20,0x10,0x23,0x10,0x24,0x90,0x17,0xe0,0x00,0x00,\r
+ /* ASCII 65 */ 0x10,0x00,0x1c,0x00,0x17,0xa0,0x04,0x60,0x17,0x80,0x1c,0x00,0x10,0x00,\r
+ /* ASCII 66 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00,\r
+ /* ASCII 67 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x08,0x60,0x00,0x00,\r
+ /* ASCII 68 */ 0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x08,0x40,0x07,0x80,0x00,0x00,\r
+ /* ASCII 69 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x13,0xa0,0x10,0x20,0x18,0x60,0x00,0x00,\r
+ /* ASCII 70 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x11,0x20,0x03,0xa0,0x00,0x20,0x00,0x60,\r
+ /* ASCII 71 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x12,0x20,0x0e,0x60,0x02,0x00,\r
+ /* ASCII 72 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x01,0x00,0x11,0x20,0x1f,0xe0,0x10,0x20,\r
+ /* ASCII 73 */ 0x00,0x00,0x10,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x00,0x00,\r
+ /* ASCII 74 */ 0x00,0x00,0x0e,0x00,0x10,0x20,0x10,0x20,0x0f,0xe0,0x00,0x20,0x00,0x00,\r
+ /* ASCII 75 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x03,0x00,0x04,0xa0,0x18,0x60,0x10,0x20,\r
+ /* ASCII 76 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x00,0x1c,0x00,0x00,0x00,\r
+ /* ASCII 77 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x03,0x00,0x10,0xe0,0x1f,0xe0,0x10,0x20,\r
+ /* ASCII 78 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x07,0x00,0x18,0x20,0x1f,0xe0,0x00,0x20,\r
+ /* ASCII 79 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00,\r
+ /* ASCII 80 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x01,0xc0,0x00,0x00,\r
+ /* ASCII 81 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x30,0x20,0x30,0x20,0x2f,0xc0,0x00,0x00,\r
+ /* ASCII 82 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x06,0x20,0x09,0xc0,0x10,0x00,\r
+ /* ASCII 83 */ 0x00,0x00,0x18,0xc0,0x09,0x20,0x11,0x20,0x11,0x40,0x0e,0x60,0x00,0x00,\r
+ /* ASCII 84 */ 0x00,0x60,0x00,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x00,0x20,0x00,0x60,\r
+ /* ASCII 85 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x10,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20,\r
+ /* ASCII 86 */ 0x00,0x20,0x00,0xe0,0x07,0x20,0x18,0x00,0x07,0x20,0x00,0xe0,0x00,0x20,\r
+ /* ASCII 87 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x0f,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20,\r
+ /* ASCII 88 */ 0x10,0x20,0x18,0x60,0x04,0x80,0x03,0x00,0x04,0x80,0x18,0x60,0x10,0x20,\r
+ /* ASCII 89 */ 0x00,0x20,0x00,0x60,0x11,0xa0,0x1e,0x00,0x11,0xa0,0x00,0x60,0x00,0x20,\r
+ /* ASCII 90 */ 0x00,0x00,0x18,0x60,0x14,0x20,0x13,0x20,0x10,0xa0,0x18,0x60,0x00,0x00,\r
+ /* ASCII 91 */ 0x00,0x00,0x00,0x00,0x7f,0xe0,0x40,0x20,0x40,0x20,0x00,0x00,0x00,0x00,\r
+ /* ASCII 92 */ 0x00,0x00,0x00,0x20,0x01,0xc0,0x06,0x00,0x38,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 93 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x40,0x20,0x7f,0xe0,0x00,0x00,0x00,0x00,\r
+ /* ASCII 94 */ 0x00,0x00,0x01,0x00,0x00,0x80,0x00,0x60,0x00,0x80,0x01,0x00,0x00,0x00,\r
+ /* ASCII 95 */ 0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,\r
+ /* ASCII 96 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x00,0x00,0x00,\r
+ /* ASCII 97 */ 0x00,0x00,0x0d,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x1f,0x00,0x10,0x00,\r
+ /* ASCII 98 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00,\r
+ /* ASCII 99 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x09,0x80,0x00,0x00,\r
+ /* ASCII 100 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x11,0x20,0x1f,0xe0,0x10,0x00,\r
+ /* ASCII 101 */ 0x00,0x00,0x0f,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x13,0x00,0x00,0x00,\r
+ /* ASCII 102 */ 0x00,0x00,0x10,0x80,0x1f,0xc0,0x10,0xa0,0x10,0xa0,0x10,0xa0,0x00,0x00,\r
+ /* ASCII 103 */ 0x00,0x00,0x0f,0x00,0x50,0x80,0x50,0x80,0x51,0x00,0x3f,0x80,0x00,0x80,\r
+ /* ASCII 104 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00,\r
+ /* ASCII 105 */ 0x00,0x00,0x10,0x80,0x10,0x80,0x1f,0xa0,0x10,0x00,0x10,0x00,0x00,0x00,\r
+ /* ASCII 106 */ 0x00,0x00,0x40,0x80,0x40,0x80,0x40,0xa0,0x3f,0x80,0x00,0x00,0x00,0x00,\r
+ /* ASCII 107 */ 0x10,0x20,0x1f,0xe0,0x02,0x00,0x16,0x80,0x19,0x80,0x10,0x80,0x00,0x00,\r
+ /* ASCII 108 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00,\r
+ /* ASCII 109 */ 0x10,0x80,0x1f,0x80,0x10,0x80,0x1f,0x00,0x10,0x80,0x1f,0x00,0x10,0x00,\r
+ /* ASCII 110 */ 0x10,0x80,0x1f,0x80,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00,\r
+ /* ASCII 111 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00,\r
+ /* ASCII 112 */ 0x40,0x80,0x7f,0x80,0x51,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00,\r
+ /* ASCII 113 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x51,0x00,0x7f,0x80,0x40,0x80,\r
+ /* ASCII 114 */ 0x00,0x00,0x10,0x80,0x1f,0x80,0x11,0x00,0x10,0x80,0x10,0x80,0x00,0x00,\r
+ /* ASCII 115 */ 0x00,0x00,0x19,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x0d,0x80,0x00,0x00,\r
+ /* ASCII 116 */ 0x00,0x00,0x00,0x80,0x0f,0xc0,0x10,0x80,0x10,0x80,0x10,0x80,0x08,0x00,\r
+ /* ASCII 117 */ 0x00,0x80,0x0f,0x80,0x10,0x00,0x10,0x00,0x08,0x80,0x1f,0x80,0x10,0x00,\r
+ /* ASCII 118 */ 0x00,0x80,0x03,0x80,0x0c,0x80,0x10,0x00,0x0c,0x80,0x03,0x80,0x00,0x80,\r
+ /* ASCII 119 */ 0x00,0x80,0x0f,0x80,0x10,0x80,0x0e,0x00,0x10,0x80,0x0f,0x80,0x00,0x80,\r
+ /* ASCII 120 */ 0x10,0x80,0x19,0x80,0x06,0x00,0x06,0x00,0x19,0x80,0x10,0x80,0x00,0x00,\r
+ /* ASCII 121 */ 0x00,0x80,0x41,0x80,0x46,0x80,0x78,0x00,0x4c,0x80,0x03,0x80,0x00,0x80,\r
+ /* ASCII 122 */ 0x00,0x00,0x19,0x80,0x14,0x80,0x12,0x80,0x11,0x80,0x18,0x80,0x00,0x00,\r
+ /* ASCII 123 */ 0x00,0x00,0x00,0x00,0x04,0x00,0x3b,0xc0,0x40,0x20,0x00,0x00,0x00,0x00,\r
+ /* ASCII 124 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 125 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x3b,0xc0,0x04,0x00,0x00,0x00,0x00,0x00,\r
+ /* ASCII 126 */ 0x00,0x00,0x04,0x00,0x02,0x00,0x04,0x00,0x04,0x00,0x02,0x00,0x00,0x00};\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DataLinesConfig\r
+* Description : Configure data lines D0~D7 (P2.10~P2.17) in Input Floating mode\r
+* for read from LCD or in Output Push-Pull mode for write on LCD\r
+* Input : - Mode: specifies the configuration mode for data lines D0~D7\r
+* - Input: configure in Input Floating mode\r
+* - Output: configure in Output Push-Pul mode\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_DataLinesConfig(DataConfigMode_TypeDef Mode)\r
+{\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |\r
+ GPIO_Pin_14 | GPIO_Pin_15 | GPIO_Pin_16 | GPIO_Pin_17;\r
+ if (Mode == Input)\r
+ {\r
+ /* Configure D0~D7 lines (P2.10~2.17) in Input Floating mode */\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;\r
+ }\r
+ else\r
+ {\r
+ /* Configure D0~D7 lines (P2.10~2.17) in Output Push-Pull mode */\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;\r
+ }\r
+ GPIO_Init(GPIO2, &GPIO_InitStructure);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DataLinesWrite\r
+* Description : Write a value on D0~D7 (P2.10~P2.17)\r
+* Input : - GPIOx: GPIO port to write on. It could be\r
+* - PortVal: value to write\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void LCD_DataLinesWrite(GPIO_TypeDef* GPIOx, u32 PortVal)\r
+{\r
+ u32 Tmp = 0;\r
+\r
+ /* Store the PM register value */\r
+ Tmp = GPIO_GetPortMask(GPIOx);\r
+ /* Mask the corresponding GPIO pins */\r
+ GPIO_PinMaskConfig(GPIOx, LCD_GPIO_Pins, DISABLE);\r
+ GPIO_PinMaskConfig(GPIOx, ~LCD_GPIO_Pins, ENABLE);\r
+ /* Write in the hole register */\r
+ GPIO_Write(GPIOx, (PortVal<<10));\r
+\r
+ GPIO_PinMaskConfig(GPIOx, ~LCD_GPIO_Pins, DISABLE);\r
+ /* Return the initial PM register value */\r
+ GPIO_PinMaskConfig(GPIOx, Tmp, ENABLE);\r
+\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_CtrlLinesConfig\r
+* Description : Configure control lines E2, E1, RW, DI (P2.0~P2.3) in\r
+* Output Push-Pull mode.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_CtrlLinesConfig(void)\r
+{\r
+ /* Configure E2, E1, RW, DI lines (P2.0~2.3) in Output Push-Pull mode */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;\r
+ GPIO_Init(GPIO2, &GPIO_InitStructure);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_CtrlLinesWrite\r
+* Description : Set or reset control lines E2, E1, RW, DI (P2.0~P2.3).\r
+* Input : - GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral.\r
+* - CtrlPins: the Control line. This parameter can be:\r
+* - CtrlPin_E2: Enabe clock signal for Slave\r
+* - CtrlPin_E1: Enabe clock signal for Master\r
+* - CtrlPin_RW: Read/Write control line\r
+* - CtrlPin_DI:\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u32 CtrlPins, BitAction BitVal)\r
+{\r
+ /* Set or Reset the control line */\r
+ if(BitVal != Bit_RESET)\r
+ {\r
+ GPIOx->PD |= CtrlPins;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->PD &= ~CtrlPins;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_CheckMasterStatus\r
+* Description : Check whether master LCD is busy or not\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_CheckMasterStatus(void) \r
+{\r
+ u8 MasterStatus = 0;\r
+\r
+ /* Configure Data lines as Input */\r
+ LCD_DataLinesConfig(Input);\r
+ /* Start the master read sequence */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */\r
+ MasterStatus = GPIO_Read(GPIO2);\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */\r
+ \r
+ /* Wait until BF is cleared: D7 line */\r
+ while ((MasterStatus & 0x20000))\r
+ {\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */\r
+ MasterStatus = GPIO_Read(GPIO2);\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_CheckSlaveStatus\r
+* Description : Check whether slave LCD is busy or not\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_CheckSlaveStatus(void) \r
+{\r
+ u8 SlaveStatus = 0;\r
+\r
+ /* Configure Data lines as Input */\r
+ LCD_DataLinesConfig(Input);\r
+ /* Start the slave read sequence */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ \r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */\r
+ SlaveStatus = GPIO_Read(GPIO2);\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */\r
+ \r
+ /* Wait until BF is cleared: D7 line */\r
+ while ((SlaveStatus & 0x20000))\r
+ {\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */\r
+ SlaveStatus = GPIO_Read(GPIO2);\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_SendMasterCmd\r
+* Description : Send one byte command to master LCD.\r
+* Input : - Cmd: the user expected command to send to master LCD\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_SendMasterCmd(u8 Cmd)\r
+{\r
+ /* Check the master status */\r
+ LCD_CheckMasterStatus();\r
+ /* Configure Data lines as Output */\r
+ LCD_DataLinesConfig(Output);\r
+ /* Start the master send command sequence */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */\r
+ /* Write master command */\r
+ LCD_DataLinesWrite(GPIO2, (u32)Cmd);\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_SendSlaveCmd\r
+* Description : Send one byte command to slave LCD\r
+* Input : - Cmd: the user expected command to send to slave LCD.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_SendSlaveCmd(u8 Cmd)\r
+{\r
+ /* Check the slave status */\r
+ LCD_CheckSlaveStatus();\r
+ /* Configure Data lines as Output */\r
+ LCD_DataLinesConfig(Output);\r
+ /* Start the slave send command sequence */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */\r
+ /* Write slave command */\r
+ LCD_DataLinesWrite(GPIO2, (u32)Cmd);\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_SendMasterData\r
+* Description : Display one byte data to master LCD.\r
+* Input : - Data: the user expected data to display on master LCD.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_SendMasterData(u8 Data)\r
+{\r
+ /* Check the master status */\r
+ LCD_CheckMasterStatus();\r
+ /* Configure Data lines as Output */\r
+ LCD_DataLinesConfig(Output);\r
+ /* Start the master send data sequence */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */\r
+ /* Write data to the master */\r
+ LCD_DataLinesWrite(GPIO2, (u32)Data);\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_ReadMasterData\r
+* Description : Read master byte data displayed on master LCD.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+u32 LCD_ReadMasterData(void)\r
+{\r
+ u32 MasterData = 0;\r
+\r
+ /* Check the master status */\r
+ LCD_CheckMasterStatus();\r
+ /* Configure Data lines as Input */\r
+ LCD_DataLinesConfig(Input);\r
+ /* Start the master read data sequence */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */\r
+ /* Read data from the master */\r
+ MasterData = ((GPIO_Read(GPIO2)&0x3FC00)>>10);\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */\r
+ /* Read the master returned data */\r
+ return MasterData;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_SendSlaveData\r
+* Description : Display one byte data to slave LCD.\r
+* Input : - Data: the user expected data to display on slave LCD.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_SendSlaveData(u8 Data)\r
+{\r
+ /* Check the slave status */\r
+ LCD_CheckSlaveStatus();\r
+ /* Configure Data lines as Output */\r
+ LCD_DataLinesConfig(Output);\r
+ /* Start the slave send data sequence */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */\r
+ /* Write data to the slave */\r
+ LCD_DataLinesWrite(GPIO2, (u32)Data);\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_ReadSlaveData\r
+* Description : Read slave byte data displayed on slave LCD.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+u32 LCD_ReadSlaveData(void)\r
+{\r
+ u32 SlaveData = 0;\r
+\r
+ /* Check the slave status */\r
+ LCD_CheckSlaveStatus();\r
+ /* Configure Data lines as Input */\r
+ LCD_DataLinesConfig(Input);\r
+ /* Start the slave read data sequence */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */\r
+ /* Read data from the slave */\r
+ SlaveData = ((GPIO_Read(GPIO2)&0x3FC00)>>10);\r
+ LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */\r
+ /* Read the slave returned data */\r
+ return SlaveData;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_Init\r
+* Description : Initialize master and slave LCD.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_Init(void)\r
+{\r
+ /* Enable GPIO Clock */\r
+ MRCC_PeripheralClockConfig(MRCC_Peripheral_GPIO, ENABLE);\r
+\r
+ /* Configure control lines signals as output mode */\r
+ LCD_CtrlLinesConfig(); \r
+\r
+ /* Master LCD Init */\r
+ LCD_SendMasterCmd(SOFTWARE_RESET);\r
+ LCD_SendMasterCmd(DISPLAY_OFF);\r
+ LCD_SendMasterCmd(DYNAMIC_DRIVE);\r
+ LCD_SendMasterCmd(DUTY_CYCLE);\r
+ LCD_SendMasterCmd(CLOCKWISE_OUTPUT);\r
+ LCD_SendMasterCmd(READ_MODIFY_WRITE_OFF);\r
+ LCD_SendMasterCmd(START_COLUMN); /* Set master column address to 0 */\r
+ LCD_SendMasterCmd(START_LINE); /* Set master display start line to 0 */\r
+ LCD_SendMasterCmd(DISPLAY_ON );\r
+\r
+ /* Slave LCD Init */\r
+ LCD_SendSlaveCmd(SOFTWARE_RESET);\r
+ LCD_SendSlaveCmd(DISPLAY_OFF);\r
+ LCD_SendSlaveCmd(DYNAMIC_DRIVE);\r
+ LCD_SendSlaveCmd(DUTY_CYCLE);\r
+ LCD_SendSlaveCmd(CLOCKWISE_OUTPUT);\r
+ LCD_SendSlaveCmd(READ_MODIFY_WRITE_OFF);\r
+ LCD_SendSlaveCmd(START_COLUMN ); /* Set slave column address to 0 */\r
+ LCD_SendSlaveCmd(START_LINE); /* Set slave display start line to 0 */\r
+ LCD_SendSlaveCmd(DISPLAY_ON);\r
+\r
+ /* Clear LCD */ \r
+ LCD_Clear();\r
+ /* Set current Page to 0 for Master and Slave LCDs */ \r
+ LCD_SetSlavePage(0);\r
+ LCD_SetMasterPage(0);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_SetSlavePage\r
+* Description : Set the display page of slave LCD, the page range is 0 to 3,\r
+* make sure the input will not exceed this range ,otherwise it\r
+* will reach a undecided result.\r
+* Input : - Page: specifies the expected display page of slave LCD\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_SetSlavePage(u8 Page)\r
+{\r
+ /* Set Slave page */\r
+ LCD_SendSlaveCmd(0xB8|Page);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_SetMasterPage\r
+* Description : Set the display page of master LCD, the page range is 0 to 3,\r
+* make sure the input will not exceed this range ,otherwise it\r
+* will reach a undecided result.\r
+* Input : - Page: specifies the expected display page of master LCD\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_SetMasterPage(u8 Page)\r
+{\r
+ /* Set Master page */\r
+ LCD_SendMasterCmd(0xB8|Page);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SetAddress\r
+* Description : Set the display column of slave LCD. Column range is 0 to 61.\r
+* Input : - Address: specifies the expected display column of slave LCD\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_SetSlaveColumn(u8 Address)\r
+{\r
+ /* Set Slave column address */\r
+ LCD_SendSlaveCmd(Address&0x7F);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_SetMasterColumn\r
+* Description : Set the display column of master LCD. Column range is 0 to 61.\r
+* Input : - Address: specifies the expected display column of slave LCD\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_SetMasterColumn(u8 Address)\r
+{\r
+ /* Set Master column address */\r
+ LCD_SendMasterCmd(Address&0x7F);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_SetTextColor\r
+* Description : Set the text color for LCD.\r
+* Input : - TextColor: BlackText: character on black, bottom on white.\r
+* WhiteText: character on white, bottom on black.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_SetTextColor(TextColorMode_TypeDef TextColor)\r
+{\r
+ if(TextColor)\r
+ {\r
+ /* Set White Text color */\r
+ TextMode=WhiteText;\r
+ }\r
+ else\r
+ {\r
+ /* Set Black Text color */\r
+ TextMode=BlackText;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_Clear\r
+* Description : Clear the Master and Slave LCDs display.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_Clear(void)\r
+{\r
+ u8 Page = 0, Column = 0; \r
+\r
+ /* Clear master and slave LCDs page by page */\r
+ for (Page=0; Page<4; Page++)\r
+ {\r
+ /* Set master and slave page by page */\r
+ LCD_SetMasterPage(Page);\r
+ LCD_SetSlavePage(Page);\r
+ /* Set master and slave column address */\r
+ LCD_SetMasterColumn(0);\r
+ LCD_SetSlaveColumn(0);\r
+ /* Send empty data to master and slave column address on the selected page */\r
+ for (Column=0; Column<61; Column++)\r
+ {\r
+ LCD_SendSlaveData(0);\r
+ LCD_SendMasterData(0);\r
+ }\r
+ }\r
+}\r
+ \r
+/*******************************************************************************\r
+* Function Name : LCD_ClearLine\r
+* Description : Clear the selected line of the LCD.\r
+* Input : - Line: the Line to clear.\r
+* - Line1 (Page0&1): clear the first line\r
+* - Line2 (Page2&3): clear the second line\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_ClearLine(u8 Line)\r
+{\r
+ u8 Page = 0, Column = 0; \r
+\r
+ /* Clear the slected master and slave line */\r
+ for (Page=Line; Page<Line+2; Page++)\r
+ {\r
+ /* Set master and slave page by page */\r
+ LCD_SetMasterPage(Page);\r
+ LCD_SetSlavePage(Page);\r
+ /* Set master and slave column address */\r
+ LCD_SetMasterColumn(0);\r
+ LCD_SetSlaveColumn(0);\r
+ /* Send empty data to master and slave column address on the selected page */\r
+ for (Column=0; Column<61; Column++)\r
+ {\r
+ LCD_SendSlaveData(0);\r
+ LCD_SendMasterData(0);\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_ClearMaster\r
+* Description : Clear the master LCD.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_ClearMaster(void)\r
+{\r
+ u8 Page = 0, Column = 0;\r
+ \r
+ /* Clear all master LCD pages */\r
+ for (Page=0; Page<4; Page++)\r
+ {\r
+ /* Set master page by page */\r
+ LCD_SetMasterPage(Page);\r
+ /* Set master column address */\r
+ LCD_SetMasterColumn(0);\r
+ /* Send empty data to master column address on the selected page */\r
+ for (Column=0; Column<61; Column++)\r
+ {\r
+ LCD_SendMasterData(0);\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_ClearSlave\r
+* Description : Clear the slave LCD.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_ClearSlave()\r
+{\r
+ u8 Page = 0, Column = 0; \r
+\r
+ /* Clear all slave LCD pages */\r
+ for (Page=0; Page<4; Page++)\r
+ {\r
+ /* Set slave page by page */\r
+ LCD_SetSlavePage(Page);\r
+ /* Set slave column address */\r
+ LCD_SetSlaveColumn(0);\r
+ /* Send empty data to slave column address on the selected page */\r
+ for (Column=0; Column<61; Column++)\r
+ {\r
+ LCD_SendSlaveData(0);\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DrawChar\r
+* Description : Draw a character in LCD.\r
+* Note:\r
+* the LCD can only display two line character,so page 0 and 1\r
+* is to display the first line, page2 and page 3 is to display\r
+* the second line.\r
+* Input : - Line: the Line where to display the character shape .\r
+* - Line1 (Page0&1): display character on the first line\r
+* - Line2 (Page2&3): display character on the second line\r
+* - Column: start column address.\r
+* - Width: the number of column (dots) of a character width.\r
+* - Bmp: the pointer of the dot matrix data.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_DrawChar(u8 Line, u8 Column, u8 Width, u8 *Bmp)\r
+{\r
+ u8 X = 0, ActualColumn = 0, Window = 0, i = 0;\r
+\r
+ /* Draw the character column by column: width times */\r
+ for(X = Column; X<(Column+Width); X++)\r
+ {\r
+ if(X > 121)\r
+ {\r
+ /* Return if column exceeded 121 */\r
+ return;\r
+ }\r
+ if (X > 60) \r
+ {\r
+ /* To be displayed on slave LCD (Window = 1) */\r
+ Window = 1;\r
+ /* Get the Slave relative start column */\r
+ ActualColumn = X%61;\r
+ }\r
+ else\r
+ { \r
+ /* To be displayed on master LCD (Window = 0) */\r
+ ActualColumn = X;\r
+ }\r
+\r
+ /* Switch window, display the character upper part */\r
+ if (Window)\r
+ {\r
+ /* Display it on slave LCD */\r
+ LCD_SetSlavePage(Line);\r
+ LCD_SetSlaveColumn(ActualColumn);\r
+ LCD_SendSlaveData(Bmp[i]);\r
+ }\r
+ else\r
+ {\r
+ /* Display it on master LCD */\r
+ LCD_SetMasterPage(Line);\r
+ LCD_SetMasterColumn(ActualColumn);\r
+ LCD_SendMasterData(Bmp[i]);\r
+ }\r
+ /* Switch window, diplay the character lower part */\r
+ if (Window)\r
+ {\r
+ /* Display it on slave LCD */\r
+ LCD_SetSlavePage(Line+1);\r
+ LCD_SetSlaveColumn(ActualColumn);\r
+ LCD_SendSlaveData(Bmp[i+1]);\r
+ }\r
+ else\r
+ {\r
+ /* Display it on master LCD */\r
+ LCD_SetMasterPage(Line+1);\r
+ LCD_SetMasterColumn(ActualColumn);\r
+ LCD_SendMasterData(Bmp[i+1]);\r
+ }\r
+ /* Increment by 2 the character table index */\r
+ i+=2;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DisplayChar\r
+* Description : Display one character (7dots large, 16dots high).\r
+* Note:\r
+* the LCD can only display two line character,so page 0 and 1\r
+* is to display the first line, page2 and page 3 is to display\r
+* the second line.\r
+* Input : - Line: the Line where to display the character.\r
+* - Line1 (Page0&1): display character on the first line\r
+* - Line2 (Page2&3): display character on the second line\r
+* - Column: start column address.\r
+* - Ascii: character ascii code.\r
+* - CharMode: BlackText: character on black, bottom on white.\r
+* WhiteText: character on white, bottom on black.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_DisplayChar(u8 Line, u8 Column, u8 Ascii, TextColorMode_TypeDef CharMode)\r
+{\r
+ u8 DotBuffer[14], i = 0;\r
+\r
+ /* Display the character lower and upper 8bit parts (2*7columns) */\r
+ for (i=0;i<14;i++)\r
+ {\r
+ /* Character displayed as white Text on black buttom */\r
+ if(CharMode)\r
+ {\r
+ if(i%2==0)\r
+ {\r
+ DotBuffer[i] = ~AsciiDotsTable[Ascii*14+i+1];\r
+ }\r
+ else\r
+ {\r
+ DotBuffer[i] = ~AsciiDotsTable[Ascii*14+i-1]; \r
+ }\r
+ }\r
+ /* Character displayed as black Text on white buttom */\r
+ else\r
+ {\r
+ if(i%2==0)\r
+ {\r
+ DotBuffer[i] = AsciiDotsTable[Ascii*14+i+1]; \r
+ }\r
+ else\r
+ {\r
+ DotBuffer[i] = AsciiDotsTable[Ascii*14+i-1]; \r
+ }\r
+ }\r
+ }\r
+ /* Display the asc code after conversion */\r
+ LCD_DrawChar(Line, Column, 7, DotBuffer);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_HexToAsciiLow\r
+* Description : This function is used to convert the low nibble of an\r
+* unsigned byte (0-F hex) to ASCII.\r
+* Input : - byte: byte to convert to ASCII.\r
+* Output : None\r
+* Return : ASCII value result of the conversion.\r
+*******************************************************************************/\r
+u8 LCD_HexToAsciiLow(u8 byte)\r
+{\r
+ /* Keep lower nibble only */\r
+ byte = byte & 0x0F;\r
+ /* If the ascii is a number */ \r
+ if (byte <= 0x09)\r
+ {\r
+ /* Add 0x30 to its ascii */\r
+ return(byte + 0x30);\r
+ }\r
+ else\r
+ {\r
+ /* Add 0x37 to its ascii */\r
+ return (byte + 0x37);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_HexToAsciiHigh\r
+* Description : This function is used to convert the high nibble of an\r
+* unsigned byte (0-F hex) to ASCII.\r
+* Input : - byte: byte to convert to ASCII.\r
+* Output : None\r
+* Return : ASCII value result of the conversion.\r
+*******************************************************************************/\r
+u8 LCD_HexToAsciiHigh(u8 byte)\r
+{\r
+ /* Keep upper nibble only */\r
+ byte = byte & 0xF0; \r
+ byte = byte >> 4;\r
+ /* If the ascii is a number */\r
+ if (byte <= 0x09)\r
+ {\r
+ /* Add 0x30 to display its ascii */\r
+ return(byte + 0x30);\r
+ }\r
+ else\r
+ {\r
+ /* Add 0x37 to display its ascii */\r
+ return (byte + 0x37);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DisplayString\r
+* Description : This function is used to display a 17char max string of\r
+* characters on the LCD display on the selected line.\r
+* Note:\r
+* this function is the user interface to use the LCD driver.\r
+* Input : - *ptr: pointer to string to display on LCD.\r
+* - Line: the Line where to display the character.\r
+* - Line1 (Page0&1): display character on the first line\r
+* - Line2 (Page2&3): display character on the second line\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_DisplayString(u8 Line, u8 *ptr, TextColorMode_TypeDef CharMode)\r
+{\r
+ u8 RefColumn = 0, i = 0;\r
+\r
+ /* Send the string character by character on lCD */\r
+ while ((*ptr!=0)&(i<17))\r
+ {\r
+ /* Display one character on LCD */\r
+ LCD_DisplayChar(Line, RefColumn, *ptr, CharMode);\r
+ /* Increment the column position by 7 */\r
+ RefColumn+=7;\r
+ /* Point on the next character */\r
+ ptr++;\r
+ /* Increment the character counter */\r
+ i++;\r
+ /* If we reach the maximum Line character */\r
+ if(i==17)\r
+ {\r
+ LCD_DisplayChar(Line, RefColumn-1, 0x1f, CharMode); /* Add missed columns */\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_Printf\r
+* Description : This function is used to display a string of characters\r
+* on the LCD display.\r
+* Note:\r
+* this function is the user interface to use the LCD driver.\r
+* Input : - *ptr: pointer to string to display on LCD.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_Printf(u8 *ptr, ...)\r
+{\r
+ u8 RefColumn = 0, RefPage = 0, i = 0, c1 = 0;\r
+ u16 var = 0, c2 = 0, c3 = 0, c4 = 0, c5 = 0;\r
+ u32 WordVar = 0;\r
+\r
+ /* Store pointer on LCD_Printf second parameter (String) */\r
+ u8 *var_ptr=(u8 *)(&ptr+1);\r
+\r
+ /* Send String */\r
+ while (*ptr != 0)\r
+ {\r
+ c1 = *ptr;\r
+ /* Limited to AsciiDotsTable code table */\r
+ if(c1 <= 128)\r
+ {\r
+ /* Carriage return */\r
+ if ( *ptr == '\r')\r
+ {\r
+ ptr++;\r
+ RefColumn = 0;\r
+ }\r
+ /* Jump to Line2 */\r
+ else if( *ptr == '\n')\r
+ {\r
+ /* Point on the string to display */\r
+ ptr++;\r
+ /* Clear Line2 */\r
+ LCD_ClearLine(Line2);\r
+ /* Point on first Line2 column */\r
+ RefColumn = 0;\r
+ /* Increment RefPage by 2 */\r
+ RefPage+=2;\r
+ }\r
+ /* Display value on the passed format */\r
+ else if( *ptr == '%')\r
+ {\r
+ ptr++;\r
+ /* Display decimal value */\r
+ if (*ptr == 'd')\r
+ {\r
+ ptr++;\r
+ /* Get the word value to display */\r
+ WordVar = ((*var_ptr)|(*(var_ptr+1)<<8)|(*(var_ptr+2)<<16));\r
+ c1=WordVar/10000;\r
+ c2=(WordVar%10000)/1000;\r
+ c3=(WordVar%1000)/100;\r
+ c4=(WordVar%100)/10;\r
+ c5=(WordVar%10);\r
+ /* Display the ten miles digit */\r
+ if (c1!=0)\r
+ {\r
+ LCD_DisplayChar(RefPage, RefColumn, c1+0x30, TextMode);\r
+ RefColumn+=7;\r
+ }\r
+ /* Display the miles digit */\r
+ if (!((c1==0)&(c2==0)))\r
+ {\r
+ LCD_DisplayChar(RefPage, RefColumn, c2+0x30, TextMode);\r
+ RefColumn+=7;\r
+ }\r
+ /* Display the hundred digit */\r
+ if (!((c1==0)&(c2==0)&(c3==0)))\r
+ {\r
+ LCD_DisplayChar(RefPage, RefColumn, c3+0x30, TextMode);\r
+ RefColumn+=7;\r
+ }\r
+ /* Display the tens digit */\r
+ if (!((c1==0)&(c2==0)&(c3==0)&(c4==0)))\r
+ {\r
+ LCD_DisplayChar(RefPage, RefColumn, c4+0x30, TextMode);\r
+ RefColumn+=7;\r
+ }\r
+ /* Display the rest */\r
+ LCD_DisplayChar(RefPage, RefColumn, c5+0x30, TextMode);\r
+ RefColumn+=7;\r
+ }\r
+ /* Display 16bits Hex value */\r
+ else if (*ptr == 'x')\r
+ {\r
+ ptr++;\r
+ /* Display 8bits MSB */\r
+ var_ptr = var_ptr +1;\r
+ var = *var_ptr;\r
+ c1 = LCD_HexToAsciiHigh(var);\r
+ LCD_DisplayChar(RefPage, RefColumn, c1, TextMode);\r
+ RefColumn+=7;\r
+ c1 = LCD_HexToAsciiLow(var);\r
+ LCD_DisplayChar(RefPage, RefColumn, c1, TextMode);\r
+ RefColumn+=7;\r
+ /* Display 8bits LSB */\r
+ var_ptr = var_ptr -1;\r
+ var = *var_ptr;\r
+ var_ptr = var_ptr +4;\r
+ c1 = LCD_HexToAsciiHigh(var);\r
+ LCD_DisplayChar(RefPage, RefColumn, c1, TextMode);\r
+ RefColumn+=7;\r
+ c1 = LCD_HexToAsciiLow(var);\r
+ LCD_DisplayChar(RefPage, RefColumn, c1, TextMode);\r
+ RefColumn+=7;\r
+ }\r
+ /* Display 32bits Hex value */\r
+ else if (*ptr == 'w')\r
+ {\r
+ ptr++;\r
+ /* Display 16bits MSB */\r
+ var_ptr = var_ptr +3;\r
+ var = *var_ptr;\r
+ c1 = LCD_HexToAsciiHigh(var);\r
+ LCD_DisplayChar(RefPage, RefColumn, c1, TextMode);\r
+ RefColumn+=7;\r
+ c1 = LCD_HexToAsciiLow(var);\r
+ LCD_DisplayChar(RefPage, RefColumn, c1, TextMode);\r
+ RefColumn+=7;\r
+ var_ptr = var_ptr -1;\r
+ var = *var_ptr;\r
+ c1 = LCD_HexToAsciiHigh(var);\r
+ LCD_DisplayChar(RefPage, RefColumn, c1, TextMode);\r
+ RefColumn+=7;\r
+ c1 = LCD_HexToAsciiLow(var);\r
+ LCD_DisplayChar(RefPage, RefColumn, c1, TextMode);\r
+ RefColumn+=7;\r
+ /* Display 16bits LSB */\r
+ var_ptr = var_ptr -1;\r
+ var = *var_ptr;\r
+ var_ptr = var_ptr +4;\r
+ c1 = LCD_HexToAsciiHigh(var);\r
+ LCD_DisplayChar(RefPage, RefColumn, c1, TextMode);\r
+ RefColumn+=7;\r
+ c1 = LCD_HexToAsciiLow(var);\r
+ LCD_DisplayChar(RefPage, RefColumn, c1, TextMode);\r
+ RefColumn+=7;\r
+ var_ptr = var_ptr -5;\r
+ var = *var_ptr;\r
+ var_ptr = var_ptr +4;\r
+ c1 = LCD_HexToAsciiHigh(var);\r
+ LCD_DisplayChar(RefPage, RefColumn, c1, TextMode);\r
+ RefColumn+=7;\r
+ c1 = LCD_HexToAsciiLow(var);\r
+ LCD_DisplayChar(RefPage, RefColumn, c1, TextMode);\r
+ RefColumn+=7;\r
+ }\r
+ else\r
+ {\r
+ /* Display '%' character which is followed by (d, x or w) */\r
+ ptr--;\r
+ c1 = *ptr;\r
+ LCD_DisplayChar(RefPage, RefColumn, c1, TextMode);\r
+ RefColumn+=7;\r
+ ptr++;\r
+ i++;\r
+ if(i==17)\r
+ {\r
+ /* Add missed columns */\r
+ LCD_DisplayChar(RefPage, RefColumn-1, 0x1f, TextMode);\r
+ RefColumn = 0;\r
+ RefPage+=2;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ { \r
+ /* Display characters different from (\r, \n, %) */ \r
+ LCD_DisplayChar(RefPage, RefColumn, c1, TextMode);\r
+ RefColumn+=7;\r
+ ptr++;\r
+ i++;\r
+ if(i==17)\r
+ {\r
+ /* Add missed columns */\r
+ LCD_DisplayChar(RefPage, RefColumn-1, 0x1f, TextMode);\r
+ LCD_ClearLine(Line2);\r
+ RefColumn = 0;\r
+ RefPage+=2;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Display spaces if string doesn't reach the max LCD characters size */\r
+ while(RefColumn<119)\r
+ {\r
+ /* Display Spaces */\r
+ LCD_DisplayChar(RefPage, RefColumn, 0x20, TextMode);\r
+ RefColumn+=7;\r
+ /* Add missed columns */\r
+ LCD_DisplayChar(RefPage, RefColumn, 0x1f, TextMode);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DrawMasterGraphic\r
+* Description : Draw a Graphic image on master LCD.\r
+* Input : - Bmp: the pointer of the dot matrix data.\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void LCD_DrawMasterGraphic(u8 *Bmp)\r
+{\r
+ u8 j = 0, k = 0, ActPage = 0;\r
+\r
+ /* Draw graphic on master: 61 Column *4 Pages */\r
+ while(j<244)\r
+ {\r
+ /* Draw on master page by page */\r
+ LCD_SetMasterPage(ActPage);\r
+ for(k=0; k<61; k++)\r
+ {\r
+ LCD_SetMasterColumn(k);\r
+ LCD_SendMasterData(*Bmp++);\r
+ j++;\r
+ }\r
+ ActPage++;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DrawSlaveGraphic\r
+* Description : Draw a Graphic image on slave LCD.\r
+* Input : - Bmp: the pointer of the dot matrix data.\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void LCD_DrawSlaveGraphic(u8 *Bmp)\r
+{\r
+ u8 j = 0, k = 0, ActPage = 0;\r
+\r
+ /* Draw graphic on slave: 61 Column *4 Pages */\r
+ while(j<244)\r
+ {\r
+ /* Draw on slave page by page */\r
+ LCD_SetSlavePage(ActPage);\r
+ for(k=0; k<61; k++)\r
+ {\r
+ LCD_SetSlaveColumn(k);\r
+ LCD_SendSlaveData(*Bmp++);\r
+ j++;\r
+ }\r
+ ActPage++;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DrawGraphic\r
+* Description : Draw a Graphic image on LCD.\r
+* Input : - Bmp: the pointer of the dot matrix data.\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void LCD_DrawGraphic(u8 *Bmp)\r
+{\r
+ u8 Pos = 0, ActPage = 0;\r
+ u16 j = 0, k = 0;\r
+\r
+ /* Draw graphic on LCD: 122 Column *4 Pages */\r
+ while(j<488)\r
+ {\r
+ if(!Pos)\r
+ {\r
+ /* Draw on master page by page */\r
+ LCD_SetMasterPage(ActPage);\r
+ for(k=0; k<61; k++)\r
+ {\r
+ LCD_SetMasterColumn(k);\r
+ LCD_SendMasterData(*Bmp++);\r
+ j++;\r
+ }\r
+ Pos=1;\r
+ }\r
+ else\r
+ {\r
+ /* Draw on slave page by page */\r
+ LCD_SetSlavePage(ActPage);\r
+ for(k=0; k<61; k++)\r
+ {\r
+ LCD_SetSlaveColumn(k);\r
+ LCD_SendSlaveData(*Bmp++);\r
+ j++;\r
+ }\r
+ ActPage++;\r
+ Pos=0;\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_ScrollGraphic\r
+* Description : Scroll a Graphic image on LCD.\r
+* Input : - Bmp: the pointer of the dot matrix data.\r
+* - nCount: specifies the delay time length.\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void LCD_ScrollGraphic(u8 *Bmp, u32 nCount)\r
+{\r
+ u8 Pos = 0, ActPage = 0;\r
+ u16 j = 0, k = 0;\r
+ u32 Counter = 0;\r
+\r
+ /* Draw graphic on LCD: 122 Column *4 Pages */\r
+ while(j<488)\r
+ {\r
+ if(!Pos)\r
+ {\r
+ /* Draw on master page by page */\r
+ LCD_SetMasterPage(ActPage);\r
+ for(k=0; k<61; k++)\r
+ {\r
+ LCD_SetMasterColumn(k);\r
+ LCD_SendMasterData(*Bmp++);\r
+ Counter = nCount;\r
+ /* Set a delay */\r
+ for(; Counter != 0; Counter--);\r
+ j++;\r
+ }\r
+ Pos=1;\r
+ }\r
+ else\r
+ {\r
+ /* Draw on slave page by page */\r
+ LCD_SetSlavePage(ActPage);\r
+ for(k=0; k<61; k++)\r
+ {\r
+ LCD_SetSlaveColumn(k);\r
+ Counter = nCount;\r
+ /* Set a delay */\r
+ for(; Counter != 0; Counter--);\r
+ LCD_SendSlaveData(*Bmp++);\r
+ j++;\r
+ }\r
+ ActPage++;\r
+ Pos=0;\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DrawPixel\r
+* Description : Draw a Graphic image on slave LCD.\r
+* Input : - XPos: the dot line number of the pixel.\r
+* - 1->61 : displayed on master LCD\r
+* - 62->122: displayed on slave LCD\r
+* - YPos: column address of the pixel from 1->32.\r
+* - Mode: Dot_On: Pixel turned on (black).\r
+* Dot_Off: Pixel turned off (black).\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void LCD_DrawPixel(u8 XPos, u8 YPos, DotMode_TypeDef Mode)\r
+{\r
+ u8 Page = 0, Position = 0;\r
+ u16 Mask = 0;\r
+ u32 MasterDataIn = 0, MasterDataOut = 0, SlaveDataIn = 0, SlaveDataOut = 0;\r
+\r
+ /* Pixel page */\r
+ Page = (XPos-1)/8;\r
+ /* Pixel column */\r
+ Position = (YPos-1)/61; /* 0:Master, 1:Slave */\r
+ /* Mask for the pixel */\r
+ Mask= 1<<((XPos-1)%8);\r
+ /* If Position=0 draw pixel on master LCD */\r
+ if(!Position)\r
+ {\r
+ LCD_SetMasterPage(Page);\r
+ LCD_SetMasterColumn(YPos-1);\r
+ MasterDataIn = LCD_ReadMasterData();\r
+ MasterDataIn = LCD_ReadMasterData();\r
+ LCD_SetMasterColumn(YPos-1);\r
+ if(Mode==Dot_On)\r
+ {\r
+ MasterDataOut = MasterDataIn | Mask;\r
+ }\r
+ else\r
+ {\r
+ MasterDataOut = MasterDataIn & (~Mask);\r
+ }\r
+ LCD_SendMasterData(MasterDataOut);\r
+ }\r
+ /* If Position=1 draw pixel on slave LCD */\r
+ else\r
+ {\r
+ LCD_SetSlavePage(Page);\r
+ LCD_SetSlaveColumn(YPos-62);\r
+ SlaveDataIn = LCD_ReadSlaveData();\r
+ SlaveDataIn = LCD_ReadSlaveData();\r
+ LCD_SetSlaveColumn(YPos-62);\r
+ if(Mode==Dot_On)\r
+ {\r
+ SlaveDataOut = SlaveDataIn | Mask;\r
+ }\r
+ else\r
+ {\r
+ SlaveDataOut = SlaveDataIn & (~Mask);\r
+ }\r
+ LCD_SendSlaveData(SlaveDataOut);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DrawLine\r
+* Description : Draw a line on master and slave LCDs.\r
+* Input : - XPos1: the dot line number of the source point .\r
+* - XPos2: the dot line number of the destination point .\r
+* - YPos1: the dot column number of the source point.\r
+* - YPos2: the dot column number of the destination point.\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void LCD_DrawLine(u8 XPos1, u8 YPos1, u8 XPos2, u8 YPos2)\r
+{\r
+ u8 XPos = 0, YPos = 0;\r
+\r
+ /* Use XPos1, YPos1, XPos2 and YPos2 */\r
+ if((XPos2>=XPos1)&(YPos2>=YPos1))\r
+ {\r
+ for(XPos=XPos1; XPos<=XPos2; XPos++)\r
+ {\r
+ for(YPos=YPos1; YPos<=YPos2; YPos++)\r
+ {\r
+ LCD_DrawPixel(XPos, YPos, Dot_On);\r
+ }\r
+ }\r
+ }\r
+ else if((XPos2<XPos1)&(YPos2>=YPos1))\r
+ {\r
+ for(XPos=XPos2; XPos<=XPos1; XPos++)\r
+ {\r
+ for(YPos=YPos1; YPos<=YPos2; YPos++)\r
+ {\r
+ LCD_DrawPixel(XPos, YPos, Dot_On);\r
+ }\r
+ }\r
+ }\r
+ else if((XPos2>=XPos1)&(YPos2<YPos1))\r
+ {\r
+ for(XPos=XPos1; XPos<=XPos2; XPos++)\r
+ {\r
+ for(YPos=YPos2; YPos<=YPos1; YPos++)\r
+ {\r
+ LCD_DrawPixel(XPos, YPos, Dot_On);\r
+ }\r
+ }\r
+ }\r
+ else /*if((XPos2<XPos1)&(YPos2<YPos1))*/\r
+ {\r
+ for(XPos=XPos2; XPos<=XPos1; XPos++)\r
+ {\r
+ for(YPos=YPos2; YPos<=YPos1; YPos++)\r
+ {\r
+ LCD_DrawPixel(XPos, YPos, Dot_On);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DrawBox\r
+* Description : Draw a Box on master and slave LCDs.\r
+* Input : - XPos: the dot line number of the source point .\r
+* - YPos: the dot column number of the source point.\r
+* - Dx: Box large.\r
+* - Dy: Box width.\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void LCD_DrawBox(u8 XPos, u8 YPos, u8 Dx, u8 Dy)\r
+{\r
+ /* Use XPos, YPos, Dx and Dy */\r
+ LCD_DrawLine(XPos, YPos, XPos, YPos+Dy);\r
+ LCD_DrawLine(XPos, YPos, XPos+Dx, YPos);\r
+ LCD_DrawLine(XPos+Dx, YPos, XPos+Dx, YPos+Dy);\r
+ LCD_DrawLine(XPos, YPos+Dy, XPos+Dx, YPos+Dy);\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE******/\r
+\r
--- /dev/null
+/*\r
+Linker subscript for STR75xFx0 definitions\r
+Copyright RAISONANCE 2005\r
+You can use, modify and distribute thisfile freely, but without any waranty.\r
+*/\r
+\r
+\r
+/* Memory Spaces Definitions */\r
+\r
+MEMORY\r
+{\r
+ FLASH (rx) : ORIGIN = 0x20000000, LENGTH = 128K\r
+ FLASHB1 (rx) : ORIGIN = 0x200C0000, LENGTH = 16K\r
+ RAM (xrw) : ORIGIN = 0x40000000, LENGTH = 16K\r
+ EXTMEMB0 (rx) : ORIGIN = 0x60000000, LENGTH = 16M\r
+ EXTMEMB1 (rx) : ORIGIN = 0x62000000, LENGTH = 16M\r
+ EXTMEMB2 (rx) : ORIGIN = 0x64000000, LENGTH = 16M\r
+ EXTMEMB3 (rx) : ORIGIN = 0x66000000, LENGTH = 16M\r
+}\r
+\r
+/* higher address of the user mode stack */\r
+_estack = 0x40004000;\r
+\r
--- /dev/null
+/*\r
+Default linker script for STR75xFx0\r
+Copyright RAISONANCE S.A.S. 2006\r
+*/\r
+\r
+/* include the common STRxxx sub-script */\r
+INCLUDE "systemfiles/STR75x_COMMON_FreeRTOS.ld"\r
+\r
+/* include the memory spaces definitions sub-script */\r
+INCLUDE "systemfiles/STR75xFx0_DEF_FreeRTOS.ld"\r
+\r
+/* include the sections management sub-script for FLASH mode */\r
+INCLUDE "systemfiles/sections_FLASH_FreeRTOS.ld"\r
+\r
+\r
--- /dev/null
+/*\r
+Common part of the linker scripts for STR75x devices\r
+Copyright RAISONANCE 2006\r
+You can use, modify and distribute this file freely, but without any waranty.\r
+*/\r
+\r
+\r
+/* Registers mapping */\r
+FLASHR_BASE = 0x20100000 ;\r
+FLASHPR_BASE = 0x2010DFB0 ;\r
+CFG_BASE = 0x60000000 ;\r
+MRCC_BASE = 0x60000020 ;\r
+EXTMEM_BASE = 0x80000000 ;\r
+SMI_BASE = 0x90000000 ;\r
+DMA_BASE = 0xFFFFEC00 ;\r
+EIC_BASE = 0xFFFFF800 ;\r
+APB_BASE = 0xFFFF8000 ;\r
+\r
+PROVIDE( _MRCC = MRCC_BASE );\r
+PROVIDE( _CFG = CFG_BASE );\r
+PROVIDE( _SMI = SMI_BASE );\r
+PROVIDE( _DMA = DMA_BASE );\r
+PROVIDE( _EIC = EIC_BASE );\r
+\r
+PROVIDE( _ADC = (APB_BASE + 0x0400) );\r
+PROVIDE( _TB = (APB_BASE + 0x0800) );\r
+PROVIDE( _TIM0 = (APB_BASE + 0x0C00) );\r
+PROVIDE( _TIM1 = (APB_BASE + 0x1000) );\r
+PROVIDE( _TIM2 = (APB_BASE + 0x1400) );\r
+PROVIDE( _PWM = (APB_BASE + 0x1800) );\r
+PROVIDE( _USB = (APB_BASE + 0x2800) ); /* USB registers */\r
+PROVIDE( _WDG = (APB_BASE + 0x3000) );\r
+PROVIDE( _SSP0 = (APB_BASE + 0x3800) );\r
+PROVIDE( _SSP1 = (APB_BASE + 0x3C00) );\r
+PROVIDE( _CAN = (APB_BASE + 0x4400) );\r
+PROVIDE( _I2C = (APB_BASE + 0x4C00) );\r
+PROVIDE( _UART0 = (APB_BASE + 0x5400) );\r
+PROVIDE( _UART1 = (APB_BASE + 0x5800) );\r
+PROVIDE( _UART2 = (APB_BASE + 0x5C00) );\r
+PROVIDE( _GPIO0 = (APB_BASE + 0x6400) );\r
+PROVIDE( _GPIO1 = (APB_BASE + 0x6440) );\r
+PROVIDE( _GPIO2 = (APB_BASE + 0x6480) );\r
+PROVIDE( _RTC = (APB_BASE + 0x7000) );\r
+PROVIDE( _EXTIT = (APB_BASE + 0x7400) );\r
+\r
+/* default stack sizes. \r
+\r
+These are used by the startup in order to allocate stacks for the different modes.\r
+*/\r
+\r
+__SVC_Stack_Size = 400 ;\r
+__IRQ_Stack_Size = 400 ;\r
+__USR_Stack_Size = 4 ;\r
+__FIQ_Stack_Size = 4 ;\r
+__ABT_Stack_Size = 0 ;\r
+__UND_Stack_Size = 0 ;\r
+\r
+__SVC_Stack_Init = _estack ;\r
+__IRQ_Stack_Init = __SVC_Stack_Init - __SVC_Stack_Size ;\r
+__USR_Stack_Init = __IRQ_Stack_Init - __IRQ_Stack_Size ;\r
+__FIQ_Stack_Init = __USR_Stack_Init - __USR_Stack_Size ;\r
+__ABT_Stack_Init = __FIQ_Stack_Init - __FIQ_Stack_Size ;\r
+__UND_Stack_Init = __ABT_Stack_Init - __ABT_Stack_Size ;\r
+\r
+/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/\r
+PROVIDE ( _SVC_Stack_Init = __SVC_Stack_Init ) ;\r
+PROVIDE ( _IRQ_Stack_Init = __IRQ_Stack_Init ) ;\r
+PROVIDE ( _USR_Stack_Init = __USR_Stack_Init ) ;\r
+PROVIDE ( _FIQ_Stack_Init = __FIQ_Stack_Init ) ;\r
+PROVIDE ( _ABT_Stack_Init = __ABT_Stack_Init ) ;\r
+PROVIDE ( _UND_Stack_Init = __UND_Stack_Init ) ;\r
+\r
+/*\r
+the user mode stack is an exception because we want it at the end of the RAM.\r
+therefore, we just check against a minimum.\r
+The value below is the minimum memory required for ALL THE STACKS.\r
+There will be a link error if there is not this amount of RAM free at the end.\r
+*/\r
+_Minimum_Stack_Size = 0xC00 ;\r
+\r
+\r
+\r
+/* default ISR addresses. \r
+\r
+The startup needs these addresses defined from another object file.\r
+In case they are not, these PROVIDEs redirect them to the Reset.\r
+\r
+_start must be defined, usually in the startup.\r
+*/\r
+\r
+PROVIDE( SWI_Handler = _start );\r
+PROVIDE( Undefined_Handler = _start );\r
+PROVIDE( Prefetch_Handler = _start );\r
+PROVIDE( Abort_Handler = _start );\r
+PROVIDE( IRQ_Handler = _start ); /* <-- needed ? */\r
+PROVIDE( FIQ_Handler = _start );\r
+PROVIDE( WAKUP_IRQHandler = _start );\r
+PROVIDE( TIM2_OC2_IRQHandler = _start );\r
+PROVIDE( TIM2_OC1_IRQHandler = _start );\r
+PROVIDE( TIM2_IC12_IRQHandler = _start );\r
+PROVIDE( TIM2_UP_IRQHandler = _start );\r
+PROVIDE( TIM1_OC2_IRQHandler = _start );\r
+PROVIDE( TIM1_OC1_IRQHandler = _start );\r
+PROVIDE( TIM1_IC12_IRQHandler = _start );\r
+PROVIDE( TIM1_UP_IRQHandler = _start );\r
+PROVIDE( TIM0_OC2_IRQHandler = _start );\r
+PROVIDE( TIM0_OC1_IRQHandler = _start );\r
+PROVIDE( TIM0_IC12_IRQHandler = _start );\r
+PROVIDE( TIM0_UP_IRQHandler = _start );\r
+PROVIDE( PWM_OC123_IRQHandler = _start );\r
+PROVIDE( PWM_EM_IRQHandler = _start );\r
+PROVIDE( PWM_UP_IRQHandler = _start );\r
+PROVIDE( I2C_IRQHandler = _start );\r
+PROVIDE( SSP1_IRQHandler = _start );\r
+PROVIDE( SSP0_IRQHandler = _start );\r
+PROVIDE( UART2_IRQHandler = _start );\r
+PROVIDE( UART1_IRQHandler = _start );\r
+PROVIDE( UART0_IRQHandler = _start );\r
+PROVIDE( CAN_IRQHandler = _start );\r
+PROVIDE( USB_LPI_RQHandler = _start );\r
+PROVIDE( USB_HP_IRQHandler = _start );\r
+PROVIDE( ADC_IRQHandler = _start );\r
+PROVIDE( DMA_IRQHandler = _start );\r
+PROVIDE( EXTIT_IRQHandler = _start );\r
+PROVIDE( MRCC_IRQHandler = _start );\r
+PROVIDE( FLASHSMI_IRQHandler = _start );\r
+PROVIDE( RTC_IRQHandler = _start );\r
+PROVIDE( TB_IRQHandler = _start );\r
+PROVIDE( USB_LP_IRQHandler = _start );\r
+PROVIDE( USB_HP_IRQHandler = _start );\r
--- /dev/null
+/*\r
+This is the default Startup for STR75x devices for the GNU toolchain\r
+\r
+It has been designed by ST Microelectronics and modified by Raisonance.\r
+\r
+You can use it, modify it, distribute it freely but without any waranty.\r
+\r
+*/\r
+.extern main\r
+\r
+ \r
+\r
+/*; Depending on Your Application, Disable or Enable the following Defines*/\r
+ /*; --------------------------------------------------------------------------\r
+ ; SMI Bank0 configuration\r
+; ----------------------------------------------------------------------------*/\r
+.set SMI_Bank0_EN, 0 /*; enable access the SMI Bank0 if 1*/\r
+\r
+/*; ----------------------------------------------------------------------------\r
+ ; Memory remapping\r
+; ----------------------------------------------------------------------------*/\r
+.set Remap_SRAM, 0 /* remap SRAM at address 0x00 if 1 */\r
+ \r
+/* ; ----------------------------------------------------------------------------\r
+ ; EIC initialization\r
+ ; ----------------------------------------------------------------------------*/\r
+.set EIC_INIT, 1 /*; Configure and Initialize EIC if 1*/\r
+\r
+\r
+;/* the following are useful for initializing the .data section */\r
+.extern _sidata ;/* start address for the initialization values of the .data section. defined in linker script */\r
+.extern _sdata ;/* start address for the .data section. defined in linker script */\r
+.extern _edata ;/* end address for the .data section. defined in linker script */\r
+\r
+;/* the following are useful for initializing the .bss section */\r
+.extern _sbss ;/* start address for the .bss section. defined in linker script */\r
+.extern _ebss ;/* end address for the .bss section. defined in linker script */\r
+\r
+;/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */\r
+.set Mode_USR, 0x10 ;/* User Mode */\r
+.set Mode_FIQ, 0x11 ;/* FIQ Mode */\r
+.set Mode_IRQ, 0x12 ;/* IRQ Mode */\r
+.set Mode_SVC, 0x13 ;/* Supervisor Mode */\r
+.set Mode_ABT, 0x17 ;/* Abort Mode */\r
+.set Mode_UNDEF, 0x1B ;/* Undefined Mode */\r
+.set Mode_SYS, 0x1F ;/* System Mode */\r
+\r
+.equ I_Bit, 0x80 ;/* when I bit is set, IRQ is disabled */\r
+.equ F_Bit, 0x40 ;/* when F bit is set, FIQ is disabled */\r
+\r
+/*; --- System memory locations */\r
+\r
+;/* init value for the stack pointer. defined in linker script */\r
+.extern _estack\r
+\r
+;/* Stack Sizes. The default values are in the linker script, but they can be overriden. */\r
+.extern _UND_Stack_Init\r
+.extern _SVC_Stack_Init\r
+.extern _ABT_Stack_Init\r
+.extern _FIQ_Stack_Init\r
+.extern _IRQ_Stack_Init\r
+.extern _USR_Stack_Init\r
+\r
+.extern _UND_Stack_Size\r
+.extern _SVC_Stack_Size\r
+.extern _ABT_Stack_Size\r
+.extern _FIQ_Stack_Size\r
+.extern _IRQ_Stack_Size\r
+.extern _USR_Stack_Size\r
+.extern vTaskSwitchContext\r
+.extern ulCriticalNesting\r
+\r
+SVC_Stack = _SVC_Stack_Init /*_estack*/ /*; 32 byte SVC stack at*/\r
+ /*; top of memory */\r
+ \r
+IRQ_Stack = _IRQ_Stack_Init /*SVC_Stack - 32*/ /*; followed by IRQ stack */\r
+USR_Stack = _USR_Stack_Init /*IRQ_Stack-256*/ /*; followed by USR stack */\r
+FIQ_Stack = _FIQ_Stack_Init /*USR_Stack-256*/ /*; followed by FIQ stack*/\r
+ABT_Stack = _ABT_Stack_Init /*FIQ_Stack-64*/ /*; followed by ABT stack */\r
+UNDEF_Stack = _UND_Stack_Init /*ABT_Stack-0*/ /*; followed by UNDEF stack */\r
+\r
+/*; --- System memory locations*/\r
+\r
+/*; MRCC Register*/\r
+MRCC_PCLKEN_Addr = 0x60000030 /*; Peripheral Clock Enable register base address*/\r
+\r
+/*; CFG Register*/\r
+CFG_GLCONF_Addr = 0x60000010 /*; Global Configuration register base address*/\r
+SRAM_mask = 0x0002 /*; to remap RAM at 0x0*/\r
+\r
+/*; GPIO Register*/\r
+GPIOREMAP0R_Addr = 0xFFFFE420\r
+SMI_EN_Mask = 0x00000001\r
+\r
+/*; SMI Register*/\r
+SMI_CR1_Addr = 0x90000000\r
+\r
+/*; --- Stack Addres for each ARM mode*/\r
+/*; add FIQ_Stack, ABT_Stack, UNDEF_Stack here if you need them*/\r
+\r
+\r
+/*; --- EIC Registers offsets*/\r
+EIC_base_addr = 0xFFFFF800 /*; EIC base address*/\r
+ICR_off_addr = 0x00 /*; Interrupt Control register offset*/\r
+CICR_off_addr = 0x04 /*; Current Interrupt Channel Register*/\r
+CIPR_off_addr = 0x08 /*; Current Interrupt Priority Register offset*/\r
+IVR_off_addr = 0x18 /*; Interrupt Vector Register offset*/\r
+FIR_off_addr = 0x1C /*; Fast Interrupt Register offset*/\r
+IER_off_addr = 0x20 /*; Interrupt Enable Register offset*/\r
+IPR_off_addr = 0x40 /*; Interrupt Pending Bit Register offset*/\r
+SIR0_off_addr = 0x60 /*; Source Interrupt Register 0*/\r
+\r
+/***************************************************************************************/\r
+\r
+\r
+.globl _start\r
+.globl _startup\r
+\r
+.text\r
+_startup:\r
+_start:\r
+ LDR PC, Reset_Addr\r
+ LDR PC, Undefined_Addr\r
+ LDR PC, SWI_Addr\r
+ LDR PC, Prefetch_Addr\r
+ LDR PC, Abort_Addr\r
+ NOP /*; Reserved vector*/\r
+ LDR PC, IRQ_Addr\r
+ LDR PC, FIQ_Addr\r
+\r
+\r
+\r
+\r
+\r
+Reset_Addr : .long Reset_Handler\r
+Undefined_Addr : .long UndefinedHandler\r
+SWI_Addr : .long SWIHandler\r
+Prefetch_Addr : .long PrefetchAbortHandler\r
+Abort_Addr : .long DataAbortHandler\r
+ .long 0 /*; Reserved vector*/\r
+IRQ_Addr : .long IRQHandler\r
+FIQ_Addr : .long FIQHandler\r
+\r
+.text\r
+/*;*******************************************************************************\r
+; Peripherals IRQ handlers address table\r
+;********************************************************************************/\r
+\r
+/* execution goes there when an interrupt occurs and there is no associated ISR */\r
+.globl __wrongvector\r
+__wrongvector:\r
+ ldr PC, __wrongvector_Addr \r
+__wrongvector_Addr:\r
+ .long 0\r
+\r
+WAKUP_Addr :.long WAKUPIRQHandler\r
+TIM2_OC2_Addr :.long TIM2_OC2IRQHandler\r
+TIM2_OC1_Addr :.long TIM2_OC1IRQHandler\r
+TIM2_IC12_Addr :.long TIM2_IC12IRQHandler\r
+TIM2_UP_Addr :.long TIM2_UPIRQHandler\r
+TIM1_OC2_Addr :.long TIM1_OC2IRQHandler\r
+TIM1_OC1_Addr :.long TIM1_OC1IRQHandler\r
+TIM1_IC12_Addr :.long TIM1_IC12IRQHandler\r
+TIM1_UP_Addr :.long TIM1_UPIRQHandler\r
+TIM0_OC2_Addr :.long TIM0_OC2IRQHandler\r
+TIM0_OC1_Addr :.long TIM0_OC1IRQHandler\r
+TIM0_IC12_Addr :.long TIM0_IC12IRQHandler\r
+TIM0_UP_Addr :.long TIM0_UPIRQHandler\r
+PWM_OC123_Addr :.long PWM_OC123IRQHandler\r
+PWM_EM_Addr :.long PWM_EMIRQHandler\r
+PWM_UP_Addr :.long PWM_UPIRQHandler\r
+I2C_Addr :.long I2CIRQHandler\r
+SSP1_Addr :.long SSP1IRQHandler\r
+SSP0_Addr :.long SSP0IRQHandler\r
+UART2_Addr :.long UART2IRQHandler\r
+UART1_Addr :.long UART1IRQHandler\r
+UART0_Addr :.long vSerialISR\r
+CAN_Addr :.long CANIRQHandler\r
+USB_LP_Addr :.long USB_LPIRQHandler\r
+USB_HP_Addr :.long USB_HPIRQHandler\r
+ADC_Addr :.long ADCIRQHandler\r
+DMA_Addr :.long DMAIRQHandler\r
+EXTIT_Addr :.long EXTITIRQHandler\r
+MRCC_Addr :.long MRCCIRQHandler\r
+FLASHSMI_Addr :.long FLASHSMIIRQHandler\r
+RTC_Addr :.long RTCIRQHandler\r
+TB_Addr :.long vPortTickISR\r
+\r
+/*;*******************************************************************************\r
+; Exception Handlers\r
+;********************************************************************************/\r
+\r
+\r
+/*;*******************************************************************************\r
+;* FreeRTOS.org macros for saving and restoring a task context\r
+;*******************************************************************************/\r
+\r
+ .macro portSAVE_CONTEXT MACRO\r
+\r
+ /* ; Push R0 as we are going to use the register. */\r
+ STMDB SP!, {R0}\r
+\r
+ /* ; Set R0 to point to the task stack pointer. */\r
+ STMDB SP, {SP}^\r
+ NOP\r
+ SUB SP, SP, #4\r
+ LDMIA SP!, {R0}\r
+\r
+ /* ; Push the return address onto the stack. */\r
+ STMDB R0!, {LR}\r
+\r
+ /* ; Now we have saved LR we can use it instead of R0. */\r
+ MOV LR, R0\r
+\r
+ /* ; Pop R0 so we can save it onto the system mode stack. */\r
+ LDMIA SP!, {R0}\r
+\r
+ /* ; Push all the system mode registers onto the task stack. */\r
+ STMDB LR, {R0-LR}^\r
+ NOP\r
+ SUB LR, LR, #60\r
+\r
+ /* ; Push the SPSR onto the task stack. */\r
+ MRS R0, SPSR\r
+ STMDB LR!, {R0}\r
+\r
+ LDR R0, =ulCriticalNesting \r
+ LDR R0, [R0]\r
+ STMDB LR!, {R0}\r
+\r
+ /* ; Store the new top of stack for the task. */\r
+ LDR R1, =pxCurrentTCB\r
+ LDR R0, [R1]\r
+ STR LR, [R0]\r
+\r
+ .endm\r
+\r
+\r
+ .macro portRESTORE_CONTEXT MACRO\r
+\r
+ /* ; Set the LR to the task stack. */\r
+ LDR R1, =pxCurrentTCB\r
+ LDR R0, [R1]\r
+ LDR LR, [R0]\r
+\r
+ /* ; The critical nesting depth is the first item on the stack. \r
+ ; Load it into the ulCriticalNesting variable. */\r
+ LDR R0, =ulCriticalNesting\r
+ LDMFD LR!, {R1}\r
+ STR R1, [R0]\r
+\r
+ /* ; Get the SPSR from the stack. */\r
+ LDMFD LR!, {R0}\r
+ MSR SPSR_cxsf, R0\r
+\r
+ /* ; Restore all system mode registers for the task. */\r
+ LDMFD LR, {R0-R14}^\r
+ NOP\r
+\r
+ /* ; Restore the return address. */\r
+ LDR LR, [LR, #+60]\r
+\r
+ /* ; And return - correcting the offset in the LR to obtain the \r
+ ; correct address. */\r
+ SUBS PC, LR, #4\r
+ \r
+ .endm\r
+\r
+\r
+\r
+/*;*******************************************************************************\r
+;* Macro Name : SaveContext\r
+;* Description : This macro used to save the context before entering\r
+; an exception handler.\r
+;* Input : The range of registers to store.\r
+;* Output : none\r
+;********************************************************************************/\r
+\r
+ .macro SaveContext $r0,$r12\r
+ STMFD sp!,{r0-r12,lr} /*; Save The workspace plus the current return*/\r
+ /*; address lr_ mode into the stack.*/\r
+ MRS r1,spsr /*; Save the spsr_mode into r1.*/\r
+ STMFD sp!,{r1} /*; Save spsr.*/\r
+ .endm\r
+\r
+/*;*******************************************************************************\r
+;* Macro Name : RestoreContext\r
+;* Description : This macro used to restore the context to return from\r
+; an exception handler and continue the program execution.\r
+;* Input : The range of registers to restore.\r
+;* Output : none\r
+;********************************************************************************/\r
+\r
+ .macro RestoreContext $r0,$r12\r
+ LDMFD sp!,{r1} /*; Restore the saved spsr_mode into r1.*/\r
+ MSR spsr_cxsf,r1 /*; Restore spsr_mode.*/\r
+ LDMFD sp!,{r0-r12,pc}^/*; Return to the instruction following...*/\r
+ /*; ...the exception interrupt.*/\r
+ .endm\r
+\r
+\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : UndefinedHandler\r
+;* Description : This function called when undefined instruction\r
+; exception is entered.\r
+;* Input : none\r
+;* Output : none\r
+;*********************************************************************************/\r
+\r
+UndefinedHandler:\r
+ SaveContext r0,r12 /*; Save the workspace plus the current*/\r
+ /*; return address lr_ und and spsr_und.*/\r
+ BL Undefined_Handler/*; Branch to Undefined_Handler*/\r
+ RestoreContext r0,r12 /*; Return to the instruction following...*/\r
+ /*; ...the undefined instruction.*/\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : SWIHandler\r
+;* Description : This function called when SWI instruction executed.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+\r
+SWIHandler:\r
+ ADD LR, LR, #4\r
+ portSAVE_CONTEXT \r
+ LDR R0, =vTaskSwitchContext\r
+ MOV LR, PC\r
+ BX R0\r
+ portRESTORE_CONTEXT \r
+\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : IRQHandler\r
+;* Description : This function called when IRQ exception is entered.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+\r
+\r
+IRQHandler:\r
+\r
+ portSAVE_CONTEXT /*; Save the context of the current task. */\r
+\r
+ LDR r0, =EIC_base_addr\r
+ LDR r1, =IVR_off_addr\r
+ LDR lr, =ReturnAddress /*; Load the return address. */\r
+ ADD pc,r0,r1 /*; Branch to the IRQ handler. */\r
+ReturnAddress:\r
+ LDR r0, =EIC_base_addr\r
+ LDR r2, [r0, #CICR_off_addr] /*; Get the IRQ channel number. */\r
+ MOV r3,#1\r
+ MOV r3,r3,LSL r2\r
+ STR r3,[r0, #IPR_off_addr] /*; Clear the corresponding IPR bit. */\r
+ \r
+ portRESTORE_CONTEXT /*; Restore the context of the selected task. */\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : PrefetchAbortHandler\r
+;* Description : This function called when Prefetch Abort\r
+; exception is entered.\r
+;* Input : none\r
+;* Output : none\r
+;*********************************************************************************/\r
+\r
+PrefetchAbortHandler:\r
+ NOP\r
+ B PrefetchAbortHandler\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : DataAbortHandler\r
+;* Description : This function is called when Data Abort\r
+; exception is entered.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+\r
+DataAbortHandler:\r
+ NOP\r
+ NOP\r
+ B DataAbortHandler\r
+ /*; ...has generated the data abort exception.*/\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : FIQHandler\r
+;* Description : This function is called when FIQ\r
+;* exception is entered.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+\r
+FIQHandler:\r
+ SUB lr,lr,#4 /*; Update the link register.*/\r
+ SaveContext r0,r7 /*; Save the workspace plus the current*/\r
+ /*; return address lr_ fiq and spsr_fiq.*/\r
+ BL FIQ_Handler /*; Branch to FIQ_Handler.*/\r
+ RestoreContext r0,r7 /*; Restore the context and return to the...*/\r
+ /*; ...program execution.*/\r
+\r
+/*;*******************************************************************************\r
+;* Macro Name : IRQ_to_SYS\r
+;* Description : This macro used to switch form IRQ mode to SYS mode\r
+;* Input : none.\r
+;* Output : none\r
+;*******************************************************************************/\r
+ .macro IRQ_to_SYS\r
+\r
+ MSR cpsr_c,#0x1F\r
+ STMFD sp!,{lr}\r
+ .endm\r
+/*;*******************************************************************************\r
+;* Macro Name : SYS_to_IRQ\r
+;* Description : This macro used to switch from SYS mode to IRQ mode\r
+; then to return to IRQHnadler routine.\r
+;* Input : none.\r
+;* Output : none.\r
+;*******************************************************************************/\r
+ .macro SYS_to_IRQ\r
+ LDMFD sp!,{lr} /*; Restore the link register. */\r
+ MSR cpsr_c,#0xD2 /*; Switch to IRQ mode.*/\r
+ MOV pc,lr /*; Return to IRQHandler routine to clear the*/\r
+ /*; pending bit.*/\r
+ .endm\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : WAKUPIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the WAKUP_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* WAKUP_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+WAKUPIRQHandler:\r
+ IRQ_to_SYS\r
+ BL WAKUP_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : TIM2_OC2IRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the TIM3_OC2_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* TIM2_OC2_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+TIM2_OC2IRQHandler:\r
+ IRQ_to_SYS\r
+ BL TIM2_OC2_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : TIM2_OC1IRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the TIM2_OC1_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* TIM2_OC1_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+TIM2_OC1IRQHandler:\r
+ IRQ_to_SYS\r
+ BL TIM2_OC1_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : TIM2_IC12IRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the TIM2_IC12_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* TIM2_IC12_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+TIM2_IC12IRQHandler:\r
+ IRQ_to_SYS\r
+ BL TIM2_IC12_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : TIM2_UPIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the TIM2_UP_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* TIM3_UP_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+TIM2_UPIRQHandler:\r
+ IRQ_to_SYS\r
+ BL TIM2_UP_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : TIM1_OC2IRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the TIM1_OC2_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* TIM1_OC2_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+TIM1_OC2IRQHandler:\r
+ IRQ_to_SYS\r
+ BL TIM1_OC2_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : TIM1_OC1IRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the TIM1_OC1_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* TIM1_OC1_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+TIM1_OC1IRQHandler:\r
+ IRQ_to_SYS\r
+ BL TIM1_OC1_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : TIM1_IC12IRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the TIM1_IC12_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* TIM1_IC12_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+TIM1_IC12IRQHandler:\r
+ IRQ_to_SYS\r
+ BL TIM1_IC12_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : TIM1_UPIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the TIM1_UP_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* TIM1_UP_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+TIM1_UPIRQHandler:\r
+ IRQ_to_SYS\r
+ BL TIM1_UP_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : TIM0_OC2IRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the TIM0_OC2_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* TIM0_OC2_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+TIM0_OC2IRQHandler:\r
+ IRQ_to_SYS\r
+ BL TIM0_OC2_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : TIM0_OC1IRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the TIM0_OC1_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* TIM0_OC1_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+TIM0_OC1IRQHandler:\r
+ IRQ_to_SYS\r
+ BL TIM0_OC1_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : TIM0_IC12IRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the TIM0_IC12_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* TIM0_IC12_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+TIM0_IC12IRQHandler:\r
+ IRQ_to_SYS\r
+ BL TIM0_IC12_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : TIM0_UPIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the TIM0_UP_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* TIM0_UP_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+TIM0_UPIRQHandler:\r
+ IRQ_to_SYS\r
+ BL TIM0_UP_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : PWM_OC123IRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the PWM_OC123_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* PWM_OC123_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+PWM_OC123IRQHandler:\r
+ IRQ_to_SYS\r
+ BL PWM_OC123_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : PWM_EMIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the PWM_EM_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* PWM_EM_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+PWM_EMIRQHandler:\r
+ IRQ_to_SYS\r
+ BL PWM_EM_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : PWM_UPIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the PWM_UP_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* PWM_UP_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+PWM_UPIRQHandler:\r
+ IRQ_to_SYS\r
+ BL PWM_UP_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : I2CIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the I2C_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* I2C_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+I2CIRQHandler:\r
+ IRQ_to_SYS\r
+ BL I2C_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : SSP1IRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the SSP1_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* SSP1_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+SSP1IRQHandler:\r
+ IRQ_to_SYS\r
+ BL SSP1_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : SSP0IRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the SSP0_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* SSP0_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+SSP0IRQHandler:\r
+ IRQ_to_SYS\r
+ BL SSP0_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : UART2IRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the UART2_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* UART2_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+UART2IRQHandler:\r
+ IRQ_to_SYS\r
+ BL UART2_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : UART1IRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the UART1_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* UART1_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;*******************************************************************************/\r
+UART1IRQHandler:\r
+ IRQ_to_SYS\r
+ BL UART1_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : UART0IRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the UART0_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* UART0_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+UART0IRQHandler:\r
+ IRQ_to_SYS\r
+ BL UART0_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : CANIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the CAN_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* CAN_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+CANIRQHandler:\r
+ IRQ_to_SYS\r
+ BL CAN_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : USB_LPIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the USB_LP_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* USB_LP_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+USB_LPIRQHandler:\r
+ IRQ_to_SYS\r
+ BL USB_LP_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : USB_HPIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the USB_HP_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* USB_HP_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+USB_HPIRQHandler:\r
+ IRQ_to_SYS\r
+ BL USB_HP_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : ADCIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the ADC_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* ADC_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+ADCIRQHandler:\r
+ IRQ_to_SYS\r
+ BL ADC_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : DMAIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the DMA_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* DMA_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+DMAIRQHandler:\r
+ IRQ_to_SYS\r
+ BL DMA_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : EXTITIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the EXTIT_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* EXTIT_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+EXTITIRQHandler:\r
+ IRQ_to_SYS\r
+ BL EXTIT_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : MRCCIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the MRCC_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* MRCC_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+MRCCIRQHandler:\r
+ IRQ_to_SYS\r
+ BL MRCC_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : FLASHSMIIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the FLASHSMI_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* FLASHSMI_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+FLASHSMIIRQHandler:\r
+ IRQ_to_SYS\r
+ BL FLASHSMI_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : RTCIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the RTC_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* RTC_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+RTCIRQHandler:\r
+ IRQ_to_SYS\r
+ BL RTC_IRQHandler\r
+ SYS_to_IRQ\r
+\r
+/*;*******************************************************************************\r
+;* Function Name : TBIRQHandler\r
+;* Description : This function used to switch to SYS mode before entering\r
+;* the TB_IRQHandler function located in 75x_it.c.\r
+;* Then to return to IRQ mode after the\r
+;* TB_IRQHandler function termination.\r
+;* Input : none\r
+;* Output : none\r
+;********************************************************************************/\r
+TBIRQHandler:\r
+ IRQ_to_SYS\r
+ BL TB_IRQHandler\r
+ SYS_to_IRQ\r
+/*;**********************************************************************************/\r
+\r
+Reset_Handler:\r
+ LDR pc, =NextInst\r
+\r
+NextInst:\r
+/*; Reset all Peripheral Clocks*/\r
+/*; This is usefull only when using debugger to Reset\Run the application*/\r
+\r
+ .if SMI_Bank0_EN\r
+ LDR r0, =0x01000000 /*; Disable peripherals clock (except GPIO)*/\r
+ .else\r
+ LDR r0, =0x00000000 /*; Disable peripherals clock*/\r
+ .endif\r
+ LDR r1, =MRCC_PCLKEN_Addr\r
+ STR r0, [r1]\r
+\r
+ .if SMI_Bank0_EN\r
+ LDR r0, =0x1875623F /*; Peripherals kept under reset (except GPIO)*/\r
+ .else\r
+ LDR r0, =0x1975623F /*; Peripherals kept under reset*/\r
+ .endif \r
+ \r
+ STR r0, [r1,#4] \r
+ MOV r0, #0\r
+ NOP /*; Wait*/\r
+ NOP\r
+ NOP\r
+ NOP\r
+ STR r0, [r1,#4] /*; Disable peripherals reset*/\r
+\r
+/*; Initialize stack pointer registers\r
+ ; Enter each mode in turn and set up the stack pointer*/\r
+\r
+\r
+\r
+ MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit /*; No interrupts*/\r
+ ldr sp, =FIQ_Stack\r
+\r
+ MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit /*; No interrupts*/\r
+ ldr sp, =IRQ_Stack\r
+\r
+ MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit /*; No interrupts*/\r
+ ldr sp, =ABT_Stack\r
+\r
+ MSR CPSR_c, #Mode_UNDEF|I_Bit|F_Bit /*; No interrupts*/\r
+ ldr sp, =UNDEF_Stack\r
+\r
+ MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit /*; No interrupts*/\r
+ ldr sp, =_estack\r
+\r
+/*; ------------------------------------------------------------------------------\r
+; Description : Enable SMI Bank0: enable GPIOs clock in MRCC_PCLKEN register, \r
+; enable SMI alternate function in GPIO_REMAP register and enable \r
+; Bank0 in SMI_CR1 register.\r
+; ------------------------------------------------------------------------------*/\r
+ .if SMI_Bank0_EN\r
+ MOV r0, #0x01000000\r
+ LDR r1, =MRCC_PCLKEN_Addr\r
+ STR r0, [r1] /*; Enable GPIOs clock*/\r
+\r
+ LDR r1, =GPIOREMAP0R_Addr\r
+ MOV r0, #SMI_EN_Mask\r
+ LDR r2, [r1]\r
+ ORR r2, r2, r0\r
+ STR r2, [r1] /*; Enable SMI alternate function */\r
+\r
+ LDR r0, =0x251 /*; SMI Bank0 enabled, Prescaler = 2, Deselect Time = 5*/\r
+ LDR r1, =SMI_CR1_Addr\r
+ STR r0, [r1] /*; Configure CR1 register */\r
+ LDR r0, =0x00\r
+ STR r0, [r1,#4] /*; Reset CR2 register */\r
+ .endif\r
+\r
+/*; ----------------------------------------------------------------------------\r
+; Description : Remapping SRAM at address 0x00 after the application has \r
+; started executing. \r
+; ----------------------------------------------------------------------------*/\r
+ .if Remap_SRAM\r
+ MOV r0, #SRAM_mask\r
+ LDR r1, =CFG_GLCONF_Addr\r
+ LDR r2, [r1] /*; Read GLCONF Register*/\r
+ BIC r2, r2, #0x03 /*; Reset the SW_BOOT bits*/\r
+ ORR r2, r2, r0 /*; Change the SW_BOOT bits*/\r
+ STR r2, [r1] /*; Write GLCONF Register*/\r
+ .endif\r
+\r
+/*;-------------------------------------------------------------------------------\r
+;Description : Initialize the EIC as following :\r
+; - IRQ disabled\r
+; - FIQ disabled\r
+; - IVR contains the load PC opcode\r
+; - All channels are disabled\r
+; - All channels priority equal to 0\r
+; - All SIR registers contains offset to the related IRQ table entry\r
+;-------------------------------------------------------------------------------*/\r
+ .if EIC_INIT\r
+ LDR r3, =EIC_base_addr\r
+ LDR r4, =0x00000000\r
+ STR r4, [r3, #ICR_off_addr] /*; Disable FIQ and IRQ*/\r
+ STR r4, [r3, #IER_off_addr] /*; Disable all interrupts channels*/\r
+\r
+ LDR r4, =0xFFFFFFFF\r
+ STR r4, [r3, #IPR_off_addr] /*; Clear all IRQ pending bits*/\r
+\r
+ LDR r4, =0x18\r
+ STR r4, [r3, #FIR_off_addr] /*; Disable FIQ channels and clear FIQ pending bits*/\r
+\r
+ LDR r4, =0x00000000\r
+ STR r4, [r3, #CIPR_off_addr] /*; Reset the current priority register*/\r
+\r
+ LDR r4, =0xE59F0000 /*; Write the LDR pc,pc,#offset..*/\r
+ STR r4, [r3, #IVR_off_addr] /*; ..instruction code in IVR[31:16]*/\r
+\r
+\r
+ LDR r2,= 32 /*; 32 Channel to initialize*/\r
+ LDR r0, =WAKUP_Addr /*; Read the address of the IRQs address table*/\r
+ LDR r1, =0x00000FFF\r
+ AND r0,r0,r1\r
+ LDR r5,=SIR0_off_addr /*; Read SIR0 address*/\r
+ SUB r4,r0,#8 /*; subtract 8 for prefetch*/\r
+ LDR r1, =0xF7E8 /*; add the offset to the 0x00 address..*/\r
+ /*; ..(IVR address + 7E8 = 0x00)*/\r
+ /*; 0xF7E8 used to complete the LDR pc,offset opcode*/\r
+ ADD r1,r4,r1 /*; compute the jump offset*/\r
+EIC_INI:\r
+ MOV r4, r1, LSL #16 /*; Left shift the result*/\r
+ STR r4, [r3, r5] /*; Store the result in SIRx register*/\r
+ ADD r1, r1, #4 /*; Next IRQ address*/\r
+ ADD r5, r5, #4 /*; Next SIR*/\r
+ SUBS r2, r2, #1 /*; Decrement the number of SIR registers to initialize*/\r
+ BNE EIC_INI /*; If more then continue*/\r
+\r
+ .endif\r
+\r
+\r
+\r
+\r
+\r
+ /* ;copy the initial values for .data section from FLASH to RAM */\r
+ ldr R1, =_sidata\r
+ ldr R2, =_sdata\r
+ ldr R3, =_edata\r
+_reset_inidata_loop:\r
+ cmp R2, R3\r
+ ldrlO R0, [R1], #4\r
+ strlO R0, [R2], #4\r
+ blO _reset_inidata_loop\r
+\r
+ ;/* Clear the .bss section */\r
+ mov r0,#0 ;/* get a zero */\r
+ ldr r1,=_sbss ;/* point to bss start */\r
+ ldr r2,=_ebss ;/* point to bss end */\r
+_reset_inibss_loop:\r
+ cmp r1,r2 ;/* check if some data remains to clear */\r
+ strlo r0,[r1],#4 ;/* clear 4 bytes */\r
+ blo _reset_inibss_loop ;/* loop until done */\r
+\r
+/************************************************************************************************/\r
+\r
+/*; --- Now enter the C code */\r
+ B main /*; Note : use B not BL, because an application will*/\r
+ /*; never return this way*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+Common part of the linker scripts for STR71x devices in FLASH mode\r
+(that is, the FLASH is seen at 0)\r
+Copyright RAISONANCE 2005\r
+You can use, modify and distribute thisfile freely, but without any waranty.\r
+*/\r
+\r
+\r
+\r
+/* Sections Definitions */\r
+\r
+SECTIONS\r
+{\r
+ /* the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */\r
+ .flashtext :\r
+ {\r
+ . = ALIGN(4);\r
+ *(.flashtext) /* Startup code */\r
+ . = ALIGN(4);\r
+ } >FLASH\r
+ \r
+ \r
+ /* the program code is stored in the .text section, which goes to Flash */\r
+ .text :\r
+ {\r
+ . = ALIGN(4);\r
+ \r
+ *(.text) /* remaining code */\r
+ *(.rodata) /* read-only data (constants) */\r
+ *(.rodata*)\r
+ *(.glue_7)\r
+ *(.glue_7t)\r
+\r
+ . = ALIGN(4);\r
+ _etext = .;\r
+ /* This is used by the startup in order to initialize the .data secion */\r
+ _sidata = _etext;\r
+ } >FLASH\r
+ \r
+ \r
+\r
+ /* This is the initialized data section\r
+ The program executes knowing that the data is in the RAM\r
+ but the loader puts the initial values in the FLASH (inidata).\r
+ It is one task of the startup to copy the initial values from FLASH to RAM. */\r
+ .data : AT ( _sidata )\r
+ {\r
+ . = ALIGN(4);\r
+ /* This is used by the startup in order to initialize the .data secion */\r
+ _sdata = . ;\r
+ \r
+ *(.data)\r
+\r
+ . = ALIGN(4);\r
+ /* This is used by the startup in order to initialize the .data secion */\r
+ _edata = . ;\r
+ } >RAM\r
+ \r
+ \r
+\r
+ /* This is the uninitialized data section */\r
+ .bss :\r
+ {\r
+ . = ALIGN(4);\r
+ /* This is used by the startup in order to initialize the .bss secion */\r
+ _sbss = .;\r
+ \r
+ *(.bss)\r
+ *(COMMON)\r
+ \r
+ . = ALIGN(4);\r
+ /* This is used by the startup in order to initialize the .bss secion */\r
+ _ebss = . ;\r
+ } >RAM\r
+ \r
+ PROVIDE ( end = _ebss );\r
+ PROVIDE ( _end = _ebss );\r
+ \r
+ /* This is the user stack section \r
+ This is just to check that there is enough RAM left for the User mode stack\r
+ It should generate an error if it's full.\r
+ */\r
+ ._usrstack :\r
+ {\r
+ . = ALIGN(4);\r
+ _susrstack = . ;\r
+ \r
+ . = . + _Minimum_Stack_Size ;\r
+ \r
+ . = ALIGN(4);\r
+ _eusrstack = . ;\r
+ } >RAM\r
+ \r
+\r
+ \r
+ /* this is the FLASH Bank1 */\r
+ /* the C or assembly source must explicitly place the code or data there\r
+ using the "section" attribute */\r
+ .b1text :\r
+ {\r
+ *(.b1text) /* remaining code */\r
+ *(.b1rodata) /* read-only data (constants) */\r
+ *(.b1rodata*)\r
+ } >FLASHB1\r
+ \r
+ /* this is the EXTMEM */\r
+ /* the C or assembly source must explicitly place the code or data there\r
+ using the "section" attribute */\r
+ \r
+ /* EXTMEM Bank0 */\r
+ .eb0text :\r
+ {\r
+ *(.eb0text) /* remaining code */\r
+ *(.eb0rodata) /* read-only data (constants) */\r
+ *(.eb0rodata*)\r
+ } >EXTMEMB0\r
+ \r
+ /* EXTMEM Bank1 */\r
+ .eb1text :\r
+ {\r
+ *(.eb1text) /* remaining code */\r
+ *(.eb1rodata) /* read-only data (constants) */\r
+ *(.eb1rodata*)\r
+ } >EXTMEMB1\r
+ \r
+ /* EXTMEM Bank2 */\r
+ .eb2text :\r
+ {\r
+ *(.eb2text) /* remaining code */\r
+ *(.eb2rodata) /* read-only data (constants) */\r
+ *(.eb2rodata*)\r
+ } >EXTMEMB2\r
+ \r
+ /* EXTMEM Bank0 */\r
+ .eb3text :\r
+ {\r
+ *(.eb3text) /* remaining code */\r
+ *(.eb3rodata) /* read-only data (constants) */\r
+ *(.eb3rodata*)\r
+ } >EXTMEMB3\r
+ \r
+ \r
+ \r
+ /* after that it's only debugging information. */\r
+ \r
+ /* remove the debugging information from the standard libraries */\r
+ DISCARD :\r
+ {\r
+ libc.a ( * )\r
+ libm.a ( * )\r
+ libgcc.a ( * )\r
+ }\r
+\r
+ /* Stabs debugging sections. */\r
+ .stab 0 : { *(.stab) }\r
+ .stabstr 0 : { *(.stabstr) }\r
+ .stab.excl 0 : { *(.stab.excl) }\r
+ .stab.exclstr 0 : { *(.stab.exclstr) }\r
+ .stab.index 0 : { *(.stab.index) }\r
+ .stab.indexstr 0 : { *(.stab.indexstr) }\r
+ .comment 0 : { *(.comment) }\r
+ /* DWARF debug sections.\r
+ Symbols in the DWARF debugging sections are relative to the beginning\r
+ of the section so we begin them at 0. */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the demo application tasks.\r
+ *\r
+ * In addition to the standard demo tasks there are two tasks defined within\r
+ * this file:\r
+ *\r
+ * 1 - The check task\r
+ * The 'check' task is responsible for ensuring that all the standard demo\r
+ * tasks are executing as expected. It only executes every three seconds, but\r
+ * has the highest priority within the system so is guaranteed to get execution\r
+ * time. Any errors discovered by the check task are latched until the\r
+ * processor is reset. At the end of each cycle the check task sends either\r
+ * a pass or fail message to the 'print' task for display on the LCD.\r
+ *\r
+ * 2 - The print task\r
+ * The print task is the LCD 'gatekeeper'. That is, it is the only task that\r
+ * should access the LCD directly so is always guaranteed exclusive (and\r
+ * therefore consistent) access. The print task simply blocks on a queue\r
+ * to wait for messages from other tasks wishing to display text on the LCD.\r
+ * When a message arrives it displays its contents on the LCD then blocks to\r
+ * wait again.\r
+ */\r
+\r
+/* ST includes. */\r
+#include "lcd.h"\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "Task.h"\r
+#include "Queue.h"\r
+\r
+/* Demo application includes. */\r
+#include "ParTest.h"\r
+#include "flash.h"\r
+#include "integer.h"\r
+#include "blocktim.h"\r
+#include "BlockQ.h"\r
+#include "comtest2.h"\r
+#include "dynamic.h"\r
+\r
+/* Demo application task priorities. */\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* How often should we check the other tasks? */\r
+#define mainCHECK_TASK_CYCLE_TIME ( 3000 )\r
+\r
+/* The maximum offset into the pass and fail strings sent to the LCD. An\r
+offset is used a simple method of using a different column each time a message\r
+is written to the LCD. */\r
+#define mainMAX_WRITE_COLUMN ( 14 )\r
+\r
+/* Baud rate used by the comtest tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( 19200 )\r
+\r
+/* The LED used by the comtest tasks. See the comtest.c file for more\r
+information. */\r
+#define mainCOM_TEST_LED ( 3 )\r
+\r
+/* The number of messages that can be queued for display on the LCD at any one\r
+time. */\r
+#define mainLCD_QUEUE_LENGTH ( 2 )\r
+\r
+/* The time to wait when sending to mainLCD_QUEUE_LENGTH. */\r
+#define mainNO_DELAY ( 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The type that is posted to the LCD queue. */\r
+typedef struct LCD_MESSAGE\r
+{\r
+ unsigned portCHAR *pucString; /* Points to the string to be displayed. */\r
+ unsigned portCHAR ucLine; /* The line of the LCD that should be used. */\r
+} LCDMessage;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The task that executes at the highest priority and checks the operation of\r
+ * all the other tasks in the system. See the description at the top of the\r
+ * file.\r
+ */\r
+static void vCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * ST provided routine to configure the processor.\r
+ */\r
+static void prvSetupHardware(void);\r
+\r
+/*\r
+ * The only task that should access the LCD. Other tasks wanting to write\r
+ * to the LCD should send a message of type LCDMessage containing the\r
+ * information to display to the print task. The print task simply blocks\r
+ * waiting for the arrival of such messages, displays the message, then blocks\r
+ * again.\r
+ */\r
+static void vPrintTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to communicate with the LCD print task. */\r
+static xQueueHandle xLCDQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Create all the demo application tasks, then start the scheduler. */\r
+int main( void )\r
+{\r
+ /* Perform any hardware setup necessary. */\r
+ prvSetupHardware();\r
+ vParTestInitialise();\r
+\r
+ /* Create the queue used to communicate with the LCD print task. */\r
+ xLCDQueue = xQueueCreate( mainLCD_QUEUE_LENGTH, sizeof( LCDMessage ) ); \r
+ \r
+ /* Create the standard demo application tasks. See the WEB documentation\r
+ for more information on these tasks. */\r
+ vCreateBlockTimeTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+ vStartDynamicPriorityTasks();\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ \r
+ /* Create the tasks defined within this file. */\r
+ xTaskCreate( vPrintTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+ \r
+ vTaskStartScheduler();\r
+ \r
+ /* Execution will only reach here if there was insufficient heap to\r
+ start the scheduler. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCheckTask( void *pvParameters )\r
+{\r
+static unsigned portLONG ulErrorDetected = pdFALSE; \r
+portTickType xLastExecutionTime;\r
+unsigned portCHAR *ucErrorMessage = ( unsigned portCHAR * )" FAIL";\r
+unsigned portCHAR *ucSuccessMessage = ( unsigned portCHAR * )" PASS";\r
+unsigned portBASE_TYPE uxColumn = mainMAX_WRITE_COLUMN;\r
+LCDMessage xMessage;\r
+\r
+ /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
+ works correctly. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time for the next cycle. */\r
+ vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_CYCLE_TIME );\r
+\r
+ /* Has an error been found in any of the standard demo tasks? */\r
+ \r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorDetected = pdTRUE;\r
+ }\r
+\r
+ if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorDetected = pdTRUE;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorDetected = pdTRUE;\r
+ }\r
+ \r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorDetected = pdTRUE;\r
+ } \r
+ \r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorDetected = pdTRUE;\r
+ } \r
+ \r
+ /* Calculate the LCD line on which we would like the message to\r
+ be displayed. The column variable is used for convenience as\r
+ it is incremented each cycle anyway. */\r
+ xMessage.ucLine = ( unsigned portCHAR ) ( uxColumn & 0x01 );\r
+\r
+ /* The message displayed depends on whether an error was found or\r
+ not. Any discovered error is latched. Here the column variable\r
+ is used as an index into the text string as a simple way of moving\r
+ the text from column to column. */ \r
+ if( ulErrorDetected == pdFALSE )\r
+ {\r
+ xMessage.pucString = ucSuccessMessage + uxColumn;\r
+ }\r
+ else\r
+ {\r
+ xMessage.pucString = ucErrorMessage + uxColumn; \r
+ } \r
+\r
+ /* Send the message to the print task for display. */\r
+ xQueueSend( xLCDQueue, ( void * ) &xMessage, mainNO_DELAY );\r
+ \r
+ /* Make sure the message is printed in a different column the next\r
+ time around. */\r
+ uxColumn--;\r
+ if( uxColumn == 0 )\r
+ {\r
+ uxColumn = mainMAX_WRITE_COLUMN;\r
+ }\r
+ }\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vPrintTask( void *pvParameters )\r
+{\r
+LCDMessage xMessage;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until a message arrives. */\r
+ while( xQueueReceive( xLCDQueue, ( void * ) &xMessage, portMAX_DELAY ) != pdPASS );\r
+ \r
+ /* The message contains the text to display, and the line on which the\r
+ text should be displayed. */\r
+ LCD_Clear();\r
+ LCD_DisplayString( xMessage.ucLine, xMessage.pucString, BlackText );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware(void)\r
+{\r
+ErrorStatus OSC4MStartUpStatus01; \r
+\r
+ /* ST provided routine. */\r
+\r
+ /* MRCC system reset */\r
+ MRCC_DeInit();\r
+ \r
+ /* Wait for OSC4M start-up */\r
+ OSC4MStartUpStatus01 = MRCC_WaitForOSC4MStartUp();\r
+ \r
+ if(OSC4MStartUpStatus01 == SUCCESS)\r
+ {\r
+ /* Set HCLK to 60MHz */\r
+ MRCC_HCLKConfig(MRCC_CKSYS_Div1);\r
+ \r
+ /* Set CKTIM to 60MHz */\r
+ MRCC_CKTIMConfig(MRCC_HCLK_Div1);\r
+ \r
+ /* Set PCLK to 30MHz */\r
+ MRCC_PCLKConfig(MRCC_CKTIM_Div2);\r
+ \r
+ /* Enable Flash Burst mode */\r
+ CFG_FLASHBurstConfig(CFG_FLASHBurst_Enable);\r
+ \r
+ /* Set CK_SYS to 60 MHz */\r
+ MRCC_CKSYSConfig(MRCC_CKSYS_OSC4MPLL, MRCC_PLL_Mul_15);\r
+ }\r
+ \r
+ /* GPIO pins optimized for 3V3 operation */\r
+ MRCC_IOVoltageRangeConfig(MRCC_IOVoltageRange_3V3);\r
+ \r
+ /* GPIO clock source enable */\r
+ MRCC_PeripheralClockConfig(MRCC_Peripheral_GPIO, ENABLE);\r
+ \r
+ /* EXTIT clock source enable */\r
+ MRCC_PeripheralClockConfig(MRCC_Peripheral_EXTIT, ENABLE);\r
+ /* TB clock source enable */\r
+ MRCC_PeripheralClockConfig(MRCC_Peripheral_TB, ENABLE);\r
+ \r
+ /* Initialize the demonstration menu */\r
+ LCD_Init();\r
+ \r
+ LCD_DisplayString(Line1, ( unsigned portCHAR * ) "www.FreeRTOS.org", BlackText);\r
+ LCD_DisplayString(Line2, ( unsigned portCHAR * ) " STR750 Demo ", BlackText);\r
+ \r
+ EIC_IRQCmd(ENABLE);\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+RIDE Project File\r
+File Version=3\r
+[BN]\r
+Build=BN746-ST7-ARM-80C51-P1-STR750\r
+[Ref]\r
+Ref=11\r
+[Type]\r
+Type=0\r
+[Environment]\r
+Begin Group CompEdit\r
+EditCodeCoverage=0\r
+TestMakeDate=1\r
+Promptrebuild=0\r
+DebugMessage=1000\r
+Promptdirtyoptions=0\r
+Prompttoreloadfiles=0\r
+Promptsucsorfail=0\r
+Promptenddebug=1\r
+Promptsave=0\r
+End Group CompEdit\r
+Begin Group Edit\r
+DocExts=*.pdf;*.htm;*.doc\r
+DocInChild=1\r
+InsertSpace=0\r
+Showinfo=1\r
+Showtool=1\r
+Showpath=1\r
+Promptbeforedelete=0\r
+Oemtoascii=0\r
+Decalage=4\r
+Undonumber=10\r
+TabStop=4\r
+End Group Edit\r
+Begin Group Font\r
+Height=12\r
+Name=courier new\r
+Default=1\r
+End Group Font\r
+Begin Group Colors\r
+Data=14745599\r
+Code=15658705\r
+ColorBackground=1\r
+Error=255\r
+String=16711680\r
+Operator=8421504\r
+Key=0\r
+Comment=8421376\r
+Control=32768\r
+Numeric=16711680\r
+Identifier=8388608\r
+Highlight=1\r
+End Group Colors\r
+End Options Environment\r
+\r
+[Directories]\r
+Begin Group Directories\r
+Source=\r
+LibOpti=c:\devtools\RIDE\Lib\CCLib\r
+List=\r
+Object=\r
+Lib=.;%RIDEDIR%\lib\STRX\r
+Include=..\..\Source\include;.\STLibrary\inc;..\common\include;.;%RIDEDIR%\lib\STRX\include\r
+End Group Directories\r
+End Options Directories\r
+\r
+[Targets]\r
+Number=1\r
+\r
+Name=ARM\r
+DllName=..\..\..\..\..\DEVTOOLS\RIDE\BIN\targetarm.dll\r
+Begin Group ARM\r
+HBAddr=400000\r
+FlashMap=0\r
+Interwork=1\r
+ThumbMode=0\r
+BootMode=0\r
+MicroIndex=0\r
+MicroName=STR750FV0\r
+LaunchMode=0\r
+End Group ARM\r
+\r
+\r
+[Magics]\r
+Number=0\r
+\r
+\r
+[Nets]\r
+Nb Nets=0\r
+\r
+[Tools]\r
+Number=5\r
+\r
+Path=..\..\..\..\..\DEVTOOLS\RIDE\BIN\aarmv32.dll\r
+Name=AS-ARM\r
+SrcExt=*.s\r
+ObjExt=*.o\r
+Target Translate=0\r
+Begin Options AS-ARM\r
+Begin Group General\r
+More=\r
+Warning=0\r
+Labels=0\r
+Dwarf2=0\r
+BigEndian=0\r
+LittleEndian=1\r
+Thumb=0\r
+End Group General\r
+End Options AS-ARM\r
+\r
+Path=..\..\..\..\..\DEVTOOLS\RIDE\BIN\ccomp51.dll\r
+Name=CodeCompressor51\r
+SrcExt=\r
+ObjExt=\r
+Target Translate=2\r
+Begin Options CodeCompressor51\r
+Begin Group Save\r
+SaveBIN=0\r
+SaveHEX=0\r
+SaveOMF=0\r
+End Group Save\r
+Begin Group Peephole\r
+Valid=1\r
+Peephole=%RIDEDIR%\EXAMPLES\8051\PEEP51.RPS\r
+End Group Peephole\r
+Begin Group Factorization\r
+MaxFactoDeep=?\r
+MaxFactoSz=?\r
+MaxFactoNr=?\r
+ConfirFacto=1\r
+End Group Factorization\r
+Begin Group Inlining\r
+MaxPostBlockNr=?\r
+ConfirmPostBlock=0\r
+MaxInlineNr=?\r
+ConfirmInline=1\r
+MaxPreBlockNr=?\r
+ConfirmPreBlock=0\r
+End Group Inlining\r
+Begin Group General\r
+ModeDos=0\r
+More=\r
+StandaloneAnchored=0\r
+StandaloneAsk=0\r
+StandaloneDiscard=1\r
+NewCode=0\r
+SameCode=1\r
+LogFile=0\r
+VerboseLevel=1\r
+Verbose=0\r
+ModeInteractive=0\r
+Add2Project=1\r
+AutoPeep=1\r
+AutoFacto=1\r
+AutoInline=1\r
+ModeAuto=1\r
+End Group General\r
+End Options CodeCompressor51\r
+\r
+Path=..\..\..\..\..\DEVTOOLS\RIDE\BIN\carmv32.dll\r
+Name=GCC-ARM\r
+SrcExt=*.c;*.h\r
+ObjExt=*.o\r
+Target Translate=0\r
+Begin Options GCC-ARM\r
+Begin Group More\r
+More=-fomit-frame-pointer\r
+End Group More\r
+Begin Group Warnings\r
+Warnunused=1\r
+Warnswitch=1\r
+Warnshad=1\r
+Supress=0\r
+Warnall=1\r
+Pedantic=0\r
+End Group Warnings\r
+Begin Group Optimisations\r
+Size=4\r
+Optimlevel=0\r
+Inlinefunc=0\r
+Noinlining=0\r
+Allow=0\r
+End Group Optimisations\r
+Begin Group Code\r
+Packstruct=0\r
+Volatileg=0\r
+Volatile=0\r
+Shortdouble=0\r
+Shortenum=0\r
+End Group Code\r
+Begin Group Debug\r
+Temp=0\r
+Debug=1\r
+End Group Debug\r
+Begin Group Defines\r
+Defines=STR75X_GCC;THUMB_INTERWORK\r
+End Group Defines\r
+Begin Group Dialect\r
+Signedchar=0\r
+Traditional=0\r
+Ansi=0\r
+End Group Dialect\r
+Begin Group Specific_Options\r
+Interwork=1\r
+BigEndian=0\r
+APCS=0\r
+LittleEndian=1\r
+Thumb=1\r
+End Group Specific_Options\r
+End Options GCC-ARM\r
+\r
+Path=..\..\..\..\..\DEVTOOLS\RIDE\BIN\larmv32.dll\r
+Name=LD-ARM\r
+SrcExt=*.o\r
+ObjExt=*.elf\r
+Target Translate=1\r
+Begin Options LD-ARM\r
+Begin Group General\r
+More=\r
+Script=./systemfiles/STR75xFx0_FLASH_FreeRTOS.ld\r
+Startup=./systemfiles/crt0_str75x_freertos.o\r
+Lim16K=1\r
+DefScript=0\r
+DefStartup=0\r
+IO=0\r
+NoFloatPrint=0\r
+SmallPrint=0\r
+STR7Lib=0\r
+Mathlib=1\r
+Clib=1\r
+Norom=0\r
+Once=0\r
+IndCalls=1\r
+Map=1\r
+End Group General\r
+End Options LD-ARM\r
+\r
+Path=..\..\..\..\..\DEVTOOLS\RIDE\BIN\libmanarm.dll\r
+Name=LIBMANARM\r
+SrcExt=\r
+ObjExt=\r
+Target Translate=0\r
+Begin Options LIBMANARM\r
+End Options LIBMANARM\r
+\r
+\r
+[Nodes]\r
+App Number=1\r
+Name=rtosdemo.elf\r
+Type=0\r
+Tool Ref=LD-ARM\r
+Info Code=38036\r
+Info XData=0\r
+Info Data=13256\r
+Target Ref=ARM\r
+Format Ref=ELF-ARM\r
+Use Local=0\r
+Begin Group ARM\r
+HBAddr=400000\r
+FlashMap=0\r
+Interwork=1\r
+ThumbMode=0\r
+BootMode=0\r
+MicroIndex=0\r
+MicroName=STR750FV0\r
+LaunchMode=0\r
+End Group ARM\r
+Nb Nodes=4\r
+Node Begin\r
+Relative Path=rtos source\r
+Type=2\r
+Tool Ref=\r
+Format Ref=\r
+Nb Dep=0\r
+Info Code=0\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=0\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=5\r
+Node Begin\r
+Relative Path=..\..\source\portable\gcc\str75x\portisr.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=22\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\Source\include\task.h\r
+Dependance=c:\e\dev\freertos\Source\include\list.h\r
+Info Code=264\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=4\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=1\r
+Begin Options GCC-ARM\r
+Begin Group More\r
+More=-fomit-frame-pointer\r
+End Group More\r
+Begin Group Warnings\r
+Warnunused=1\r
+Warnswitch=1\r
+Warnshad=1\r
+Supress=0\r
+Warnall=1\r
+Pedantic=0\r
+End Group Warnings\r
+Begin Group Optimisations\r
+Size=4\r
+Optimlevel=0\r
+Inlinefunc=0\r
+Noinlining=0\r
+Allow=0\r
+End Group Optimisations\r
+Begin Group Code\r
+Packstruct=0\r
+Volatileg=0\r
+Volatile=0\r
+Shortdouble=0\r
+Shortenum=0\r
+End Group Code\r
+Begin Group Debug\r
+Temp=0\r
+Debug=1\r
+End Group Debug\r
+Begin Group Defines\r
+Defines=STR75X_GCC;THUMB_INTERWORK\r
+End Group Defines\r
+Begin Group Dialect\r
+Signedchar=0\r
+Traditional=0\r
+Ansi=0\r
+End Group Dialect\r
+Begin Group Specific_Options\r
+Interwork=1\r
+BigEndian=0\r
+APCS=0\r
+LittleEndian=1\r
+Thumb=0\r
+End Group Specific_Options\r
+End Options GCC-ARM\r
+Begin Options Directories\r
+Begin Group Directories\r
+Source=\r
+LibOpti=c:\devtools\RIDE\Lib\CCLib\r
+List=\r
+Object=\r
+Lib=.;%RIDEDIR%\lib\STRX\r
+Include=..\..\Source\include;.\STLibrary\inc;..\common\include;.;%RIDEDIR%\lib\STRX\include\r
+End Group Directories\r
+End Options Directories\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573212\r
+Node End\r
+Node Begin\r
+Relative Path=..\..\source\portable\gcc\str75x\port.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=24\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\Source\include\task.h\r
+Dependance=c:\e\dev\freertos\Source\include\list.h\r
+Info Code=544\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=0\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573211\r
+Node End\r
+Node Begin\r
+Relative Path=..\..\source\list.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=32\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\newlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\config.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\ieeefp.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\reent.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\_types.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\lock.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\alloca.h\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\Source\include\list.h\r
+Info Code=444\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=0\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573939\r
+Node End\r
+Node Begin\r
+Relative Path=..\..\source\queue.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=36\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\newlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\config.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\ieeefp.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\reent.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\_types.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\lock.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\alloca.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\string.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\string.h\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\Source\include\task.h\r
+Dependance=c:\e\dev\freertos\Source\include\list.h\r
+Dependance=c:\e\dev\freertos\Source\include\croutine.h\r
+Info Code=1832\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=0\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573939\r
+Node End\r
+Node Begin\r
+Relative Path=..\..\source\tasks.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=45\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\stdio.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\newlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\config.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\ieeefp.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stdarg.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\reent.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\_types.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\lock.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\types.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\_types.h\r
+Dependance=c:\devtools\gnuarm\lib\gcc\arm-elf\4.0.2\include\limits.h\r
+Dependance=c:\devtools\gnuarm\lib\gcc\arm-elf\4.0.2\include\syslimits.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\limits.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\types.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\features.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\stdio.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\alloca.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\string.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\string.h\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\Source\include\task.h\r
+Dependance=c:\e\dev\freertos\Source\include\list.h\r
+Info Code=3708\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=240\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573938\r
+Node End\r
+MakeDate=0\r
+Node End\r
+Node Begin\r
+Relative Path=demo source\r
+Type=2\r
+Tool Ref=\r
+Format Ref=\r
+Nb Dep=0\r
+Info Code=0\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=0\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=12\r
+Node Begin\r
+Relative Path=serial\serialisr.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=22\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\Source\include\queue.h\r
+Info Code=448\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=12\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=1\r
+Begin Options GCC-ARM\r
+Begin Group More\r
+More=-fomit-frame-pointer\r
+End Group More\r
+Begin Group Warnings\r
+Warnunused=1\r
+Warnswitch=1\r
+Warnshad=1\r
+Supress=0\r
+Warnall=1\r
+Pedantic=0\r
+End Group Warnings\r
+Begin Group Optimisations\r
+Size=4\r
+Optimlevel=0\r
+Inlinefunc=0\r
+Noinlining=0\r
+Allow=0\r
+End Group Optimisations\r
+Begin Group Code\r
+Packstruct=0\r
+Volatileg=0\r
+Volatile=0\r
+Shortdouble=0\r
+Shortenum=0\r
+End Group Code\r
+Begin Group Debug\r
+Temp=0\r
+Debug=1\r
+End Group Debug\r
+Begin Group Defines\r
+Defines=STR75X_GCC;THUMB_INTERWORK\r
+End Group Defines\r
+Begin Group Dialect\r
+Signedchar=0\r
+Traditional=0\r
+Ansi=0\r
+End Group Dialect\r
+Begin Group Specific_Options\r
+Interwork=1\r
+BigEndian=0\r
+APCS=0\r
+LittleEndian=1\r
+Thumb=0\r
+End Group Specific_Options\r
+End Options GCC-ARM\r
+Begin Options Directories\r
+Begin Group Directories\r
+Source=\r
+LibOpti=c:\devtools\RIDE\Lib\CCLib\r
+List=\r
+Object=\r
+Lib=.;%RIDEDIR%\lib\STRX\r
+Include=..\..\Source\include;.\STLibrary\inc;..\common\include;.;%RIDEDIR%\lib\STRX\include\r
+End Group Directories\r
+End Options Directories\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573938\r
+Node End\r
+Node Begin\r
+Relative Path=..\common\minimal\dynamic.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=36\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\newlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\config.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\ieeefp.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\reent.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\_types.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\lock.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\alloca.h\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\Source\include\task.h\r
+Dependance=c:\e\dev\freertos\Source\include\list.h\r
+Dependance=c:\e\dev\freertos\Source\include\semphr.h\r
+Dependance=c:\e\dev\freertos\Source\include\queue.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\dynamic.h\r
+Info Code=892\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=80\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573938\r
+Node End\r
+Node Begin\r
+Relative Path=partest\partest.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=23\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_GPIO.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\partest.h\r
+Info Code=500\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=48\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573938\r
+Node End\r
+Node Begin\r
+Relative Path=serial\serial.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=26\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\Source\include\queue.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\serial.h\r
+Info Code=604\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=12\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573937\r
+Node End\r
+Node Begin\r
+Relative Path=stlibrary\src\lcd.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=15\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\lcd.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Info Code=9930\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=1782\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573937\r
+Node End\r
+Node Begin\r
+Relative Path=..\..\source\portable\memmang\heap_1.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=33\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\newlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\config.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\ieeefp.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\reent.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\_types.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\lock.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\alloca.h\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\Source\include\task.h\r
+Dependance=c:\e\dev\freertos\Source\include\list.h\r
+Info Code=164\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=12808\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573937\r
+Node End\r
+Node Begin\r
+Relative Path=..\common\minimal\integer.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=34\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\newlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\config.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\ieeefp.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\reent.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\_types.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\lock.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\alloca.h\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\Source\include\task.h\r
+Dependance=c:\e\dev\freertos\Source\include\list.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\integer.h\r
+Info Code=356\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=12\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573936\r
+Node End\r
+Node Begin\r
+Relative Path=..\common\minimal\blockq.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=35\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\newlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\config.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\ieeefp.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\reent.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\_types.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\lock.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\alloca.h\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\Source\include\task.h\r
+Dependance=c:\e\dev\freertos\Source\include\list.h\r
+Dependance=c:\e\dev\freertos\Source\include\queue.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\BlockQ.h\r
+Info Code=1084\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=72\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573936\r
+Node End\r
+Node Begin\r
+Relative Path=..\common\minimal\blocktim.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=23\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\Source\include\task.h\r
+Dependance=c:\e\dev\freertos\Source\include\list.h\r
+Dependance=c:\e\dev\freertos\Source\include\queue.h\r
+Info Code=1324\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=48\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573936\r
+Node End\r
+Node Begin\r
+Relative Path=..\common\minimal\comtest.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=36\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\newlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\config.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\ieeefp.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\reent.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\_types.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\lock.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\alloca.h\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\Source\include\task.h\r
+Dependance=c:\e\dev\freertos\Source\include\list.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\serial.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\comtest.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\partest.h\r
+Info Code=592\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=28\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573935\r
+Node End\r
+Node Begin\r
+Relative Path=..\common\minimal\flash.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=35\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\newlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\config.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\ieeefp.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\reent.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\_ansi.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\_types.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\sys\lock.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\machine\stdlib.h\r
+Dependance=c:\devtools\gnuarm\arm-elf\sys-include\alloca.h\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\Source\include\task.h\r
+Dependance=c:\e\dev\freertos\Source\include\list.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\partest.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\flash.h\r
+Info Code=236\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=12\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573935\r
+Node End\r
+Node Begin\r
+Relative Path=main.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=32\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\lcd.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\Source\include\FreeRTOS.h\r
+Dependance=c:\devtools\RIDE\lib\STRX\include\stddef.h\r
+Dependance=c:\e\dev\freertos\Source\include\projdefs.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\FreeRTOSConfig.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\Source\include\portable.h\r
+Dependance=c:\e\dev\freertos\Source\portable\GCC\STR75x\portmacro.h\r
+Dependance=c:\e\dev\freertos\Source\include\Task.h\r
+Dependance=c:\e\dev\freertos\Source\include\list.h\r
+Dependance=c:\e\dev\freertos\Source\include\Queue.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\ParTest.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\flash.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\integer.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\blocktim.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\BlockQ.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\comtest2.h\r
+Dependance=c:\e\dev\freertos\demo\common\include\dynamic.h\r
+Info Code=712\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=96\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573102\r
+Node End\r
+MakeDate=0\r
+Node End\r
+Node Begin\r
+Relative Path=system files\r
+Type=2\r
+Tool Ref=\r
+Format Ref=\r
+Nb Dep=0\r
+Info Code=0\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=0\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=1\r
+Node Begin\r
+Relative Path=systemfiles\crt0_str75x_freertos.s\r
+Type=0\r
+Tool Ref=AS-ARM\r
+Format Ref=\r
+Nb Dep=0\r
+Info Code=1684\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=0\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573211\r
+Node End\r
+MakeDate=0\r
+Node End\r
+Node Begin\r
+Relative Path=library source\r
+Type=2\r
+Tool Ref=\r
+Format Ref=\r
+Nb Dep=0\r
+Info Code=0\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=0\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=8\r
+Node Begin\r
+Relative Path=stlibrary\src\75x_uart.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=6\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\stlibrary\src\75x_uart.c\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Info Code=2096\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=0\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573934\r
+Node End\r
+Node Begin\r
+Relative Path=stlibrary\src\75x_lib.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=15\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\stlibrary\src\75x_lib.c\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_lib.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tim.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_pwm.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_wdg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_uart.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_extit.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Info Code=0\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=0\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573934\r
+Node End\r
+Node Begin\r
+Relative Path=stlibrary\src\75x_it.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=0\r
+Info Code=148\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=0\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573934\r
+Node End\r
+Node Begin\r
+Relative Path=stlibrary\src\75x_gpio.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=6\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\stlibrary\src\75x_gpio.c\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_gpio.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Info Code=1336\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=36\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573934\r
+Node End\r
+Node Begin\r
+Relative Path=stlibrary\src\75x_eic.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=5\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\stlibrary\src\75x_eic.c\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_eic.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Info Code=576\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=0\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573933\r
+Node End\r
+Node Begin\r
+Relative Path=stlibrary\src\75x_cfg.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=5\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\stlibrary\src\75x_cfg.c\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_cfg.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Info Code=224\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=0\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573933\r
+Node End\r
+Node Begin\r
+Relative Path=stlibrary\src\75x_mrcc.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=5\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\stlibrary\src\75x_mrcc.c\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Info Code=5028\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=0\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573933\r
+Node End\r
+Node Begin\r
+Relative Path=stlibrary\src\75x_tb.c\r
+Type=0\r
+Tool Ref=GCC-ARM\r
+Format Ref=\r
+Nb Dep=5\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_tb.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_map.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_conf.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_type.h\r
+Dependance=c:\e\dev\freertos\demo\arm7_str75x_gcc\STLibrary\inc\75x_mrcc.h\r
+Info Code=1240\r
+Info Const=0\r
+Info XData=0\r
+Info PData=0\r
+Info Data=0\r
+Info IData=0\r
+Info Bit=0\r
+Use Local=0\r
+Do Link=1\r
+Do Translate=1\r
+Do Load=0\r
+Nb Nodes=0\r
+MakeDate=-953573932\r
+Node End\r
+MakeDate=0\r
+Node End\r
+Do Translate=1\r
+PostLinker Ref=\r
+\r
+\r
+[Desktop Files]\r
+Nb Desktop Files=7\r
+c:\e\dev\freertos\demo\common\minimal\integer.c (110,115-893,490) 164\r
+\r
+c:\e\dev\freertos\source\portable\gcc\str75x\port.c (73,117-776,476) 148\r
+\r
+c:\e\dev\freertos\demo\arm7_str75x_gcc\main.c (0,0-796,597) 144\r
+\r
+c:\e\dev\freertos\source\portable\gcc\str75x\portisr.c (0,0-944,520) 101\r
+\r
+c:\e\dev\freertos\source\tasks.c (0,0-944,499) 1412\r
+\r
+c:\e\dev\freertos\demo\arm7_str75x_gcc\systemfiles\crt0_str75x_freertos.s (88,92-871,451) 187\r
+\r
+c:\e\dev\freertos\source\include\portable.h (110,115-893,490) 116\r
+\r
+\r
+[Closed Files]\r
+Nb Closed Files=5\r
+c:\e\dev\freertos\source\list.c (0,0-0,0) 0\r
+\r
+c:\e\dev\freertos\demo\arm7_str75x_gcc\stlibrary\src\75x_it.c (0,0-0,0) 0\r
+\r
+c:\e\dev\freertos\demo\common\minimal\integer.c (0,0-0,0) 0\r
+\r
+c:\e\dev\freertos\source\portable\gcc\str75x\port.c (0,0-0,0) 0\r
+\r
+c:\e\dev\freertos\demo\arm7_str75x_gcc\systemfiles\crt0_str75x_freertos.s (0,0-0,0) 0\r
+\r
+\r
+[Dim Views]\r
+Nb Dim Views=13\r
+0 (0,0-0,0)\r
+1 (0,0-0,0)\r
+2 (0,0-0,0)\r
+3 (0,0-0,0)\r
+4 (76,125-823,634)\r
+5 (553,156-783,399)\r
+6 (220,230-941,725)\r
+7 (0,0-0,0)\r
+8 (0,0-0,0)\r
+9 (0,0-0,0)\r
+10 (0,0-0,0)\r
+11 (0,0-0,0)\r
+12 (0,0-0,0)\r
+\r
+[DebugTool]\r
+Debug=\r
+\r
+[Project Rect]\r
+(0,0-0,0)\r
+\r
+[LastSel]\r
+LastAOF=c:\e\dev\freertos\demo\arm7_str75x_gcc\rtosdemo.elf\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*\r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.\r
+*/\r
+\r
+/* Library includes. */\r
+#include "75x_uart.h"\r
+#include "75x_gpio.h"\r
+#include "75x_eic.h"\r
+#include "75x_mrcc.h"\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. */\r
+static xQueueHandle xRxedChars;\r
+static xQueueHandle xCharsForTx;\r
+\r
+static volatile portBASE_TYPE xQueueEmpty = pdTRUE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The interrupt service routine - called from the assembly entry point. */\r
+void vSerialISR( void );\r
+void vConfigureQueues( xQueueHandle xQForRx, xQueueHandle xQForTx, volatile portBASE_TYPE *pxEmptyFlag );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See the serial2.h header file.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+xComPortHandle xReturn;\r
+UART_InitTypeDef UART_InitStructure;\r
+GPIO_InitTypeDef GPIO_InitStructure;\r
+EIC_IRQInitTypeDef EIC_IRQInitStructure; \r
+\r
+ /* Create the queues used to hold Rx and Tx characters. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ /* If the queues were created correctly then setup the serial port\r
+ hardware. */\r
+ if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )\r
+ {\r
+ \r
+ vConfigureQueues( xRxedChars, xCharsForTx, &xQueueEmpty );\r
+ \r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Enable the UART0 Clock. */\r
+ MRCC_PeripheralClockConfig( MRCC_Peripheral_UART0, ENABLE );\r
+ \r
+ /* Configure the UART0_Tx as alternate function */\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;\r
+ GPIO_Init(GPIO0, &GPIO_InitStructure);\r
+ \r
+ /* Configure the UART0_Rx as input floating */\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;\r
+ GPIO_Init(GPIO0, &GPIO_InitStructure);\r
+ \r
+ /* Configure UART0. */\r
+ UART_InitStructure.UART_WordLength = UART_WordLength_8D;\r
+ UART_InitStructure.UART_StopBits = UART_StopBits_1;\r
+ UART_InitStructure.UART_Parity = UART_Parity_No;\r
+ UART_InitStructure.UART_BaudRate = ulWantedBaud;\r
+ UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None;\r
+ UART_InitStructure.UART_Mode = UART_Mode_Tx_Rx;\r
+ UART_InitStructure.UART_TxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */\r
+ UART_InitStructure.UART_RxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */\r
+ UART_Init(UART0, &UART_InitStructure);\r
+\r
+ /* Enable the UART0 */\r
+ UART_Cmd(UART0, ENABLE);\r
+\r
+ /* Configure the IEC for the UART interrupts. */ \r
+ EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;\r
+ EIC_IRQInitStructure.EIC_IRQChannel = UART0_IRQChannel;\r
+ EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;\r
+ EIC_IRQInit(&EIC_IRQInitStructure);\r
+ \r
+ xQueueEmpty = pdTRUE;\r
+ UART_ITConfig( UART0, UART_IT_Transmit | UART_IT_Receive, ENABLE );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ xReturn = ( xComPortHandle ) 0;\r
+ }\r
+\r
+ /* This demo file only supports a single port but we have to return\r
+ something to comply with the standard demo header file. */\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports one port. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+signed portCHAR *pxNext;\r
+\r
+ /* A couple of parameters that this port does not use. */\r
+ ( void ) usStringLength;\r
+ ( void ) pxPort;\r
+\r
+ /* NOTE: This implementation does not handle the queue being full as no\r
+ block time is used! */\r
+\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+\r
+ /* Send each character in the string, one at a time. */\r
+ pxNext = ( signed portCHAR * ) pcString;\r
+ while( *pxNext )\r
+ {\r
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+ pxNext++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+portBASE_TYPE xReturn;\r
+\r
+ /* Place the character in the queue of characters to be transmitted. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ if( xQueueEmpty == pdTRUE )\r
+ {\r
+ UART0->DR = cOutChar;\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ xReturn = pdFAIL;\r
+ } \r
+ else\r
+ {\r
+ xReturn = pdPASS; \r
+ }\r
+ }\r
+ \r
+ xQueueEmpty = pdFALSE;\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ /* Not supported as not required by the demo application. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+ \r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Library includes. */\r
+#include "75x_uart.h"\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+\r
+static xQueueHandle xRxedChars;\r
+static xQueueHandle xCharsForTx;\r
+static portBASE_TYPE volatile *pxQueueEmpty;\r
+\r
+void vConfigureQueues( xQueueHandle xQForRx, xQueueHandle xQForTx, portBASE_TYPE volatile *pxEmptyFlag )\r
+{\r
+ xRxedChars = xQForRx;\r
+ xCharsForTx = xQForTx;\r
+ pxQueueEmpty = pxEmptyFlag;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialISR( void )\r
+{\r
+signed portCHAR cChar;\r
+portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE;\r
+\r
+ do\r
+ {\r
+ if( UART0->MIS & UART_IT_Transmit )\r
+ {\r
+ /* The interrupt was caused by the THR becoming empty. Are there any\r
+ more characters to transmit? */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )\r
+ {\r
+ /* A character was retrieved from the queue so can be sent to the\r
+ THR now. */\r
+ UART0->DR = cChar;\r
+ }\r
+ else\r
+ {\r
+ *pxQueueEmpty = pdTRUE; \r
+ } \r
+\r
+ UART_ClearITPendingBit( UART0, UART_IT_Transmit );\r
+ }\r
+ \r
+ if( UART0->MIS & UART_IT_Receive )\r
+ {\r
+ /* The interrupt was caused by a character being received. Grab the\r
+ character from the RHR and place it in the queue of received\r
+ characters. */\r
+ cChar = UART0->DR;\r
+ xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost );\r
+ UART_ClearITPendingBit( UART0, UART_IT_Receive );\r
+ }\r
+ } while( UART0->MIS );\r
+\r
+ /* If a task was woken by either a character being received or a character\r
+ being transmitted then we may need to switch to another task. */\r
+ portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) );\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ST STR75x ARM7\r
+ * port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Library includes. */\r
+#include "75x_tb.h"\r
+#include "75x_eic.h"\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Constants required to setup the initial stack. */\r
+#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */\r
+#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )\r
+#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )\r
+\r
+/* Constants required to handle critical sections. */\r
+#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )\r
+\r
+/* Prescale used on the timer clock when calculating the tick period. */\r
+#define portPRESCALE 20\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Setup the watchdog to generate the tick interrupts. */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Initialise the stack of a task to look exactly as if a call to\r
+ * portSAVE_CONTEXT had been called.\r
+ *\r
+ * See header file for description.\r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+portSTACK_TYPE *pxOriginalTOS;\r
+\r
+ pxOriginalTOS = pxTopOfStack;\r
+\r
+ /* Setup the initial stack of the task. The stack is set exactly as\r
+ expected by the portRESTORE_CONTEXT() macro. */\r
+\r
+ /* First on the stack is the return address - which in this case is the\r
+ start of the task. The offset is added to make the return address appear\r
+ as it would within an IRQ ISR. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; \r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */\r
+ pxTopOfStack--; \r
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */\r
+ pxTopOfStack--; \r
+\r
+ /* When the task starts is will expect to find the function parameter in\r
+ R0. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+\r
+ /* The status register is set for system mode, with interrupts enabled. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;\r
+\r
+ #ifdef THUMB_INTERWORK\r
+ {\r
+ /* We want the task to start in thumb mode. */\r
+ *pxTopOfStack |= portTHUMB_MODE_BIT;\r
+ }\r
+ #endif\r
+\r
+ pxTopOfStack--;\r
+\r
+ /* Interrupt flags cannot always be stored on the stack and will\r
+ instead be stored in a variable, which is then saved as part of the\r
+ tasks context. */\r
+ *pxTopOfStack = portNO_CRITICAL_NESTING;\r
+\r
+ return pxTopOfStack; \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+extern void vPortISRStartFirstTask( void );\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Start the first task. */\r
+ vPortISRStartFirstTask(); \r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the ARM port will require this function as there\r
+ is nothing to return to. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+EIC_IRQInitTypeDef EIC_IRQInitStructure; \r
+TB_InitTypeDef TB_InitStructure;\r
+\r
+ /* Setup the EIC for the TB. */\r
+ EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;\r
+ EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;\r
+ EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;\r
+ EIC_IRQInit(&EIC_IRQInitStructure);\r
+ \r
+ /* Setup the TB for the generation of the tick interrupt. */\r
+ TB_InitStructure.TB_Mode = TB_Mode_Timing;\r
+ TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;\r
+ TB_InitStructure.TB_Prescaler = portPRESCALE;\r
+ TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / ( portPRESCALE + 1 ) ) / configTICK_RATE_HZ ) + 1;\r
+ TB_Init(&TB_InitStructure);\r
+ \r
+ /* Enable TB Update interrupt */\r
+ TB_ITConfig(TB_IT_Update, ENABLE);\r
+\r
+ /* Clear TB Update interrupt pending bit */\r
+ TB_ClearITPendingBit(TB_IT_Update);\r
+\r
+ /* Enable TB */\r
+ TB_Cmd(ENABLE);\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Components that can be compiled to either ARM or THUMB mode are\r
+ * contained in port.c The ISR routines, which can only be compiled\r
+ * to ARM mode, are contained in this file.\r
+ *----------------------------------------------------------*/\r
+\r
+/*\r
+*/\r
+\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Constants required to handle interrupts. */\r
+#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )\r
+#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )\r
+\r
+/* Constants required to handle critical sections. */\r
+#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )\r
+\r
+volatile unsigned portLONG ulCriticalNesting = 9999UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * The scheduler can only be started from ARM mode, hence the inclusion of this\r
+ * function here.\r
+ */\r
+void vPortISRStartFirstTask( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortISRStartFirstTask( void )\r
+{\r
+ /* Simply start the scheduler. This is included here as it can only be\r
+ called from ARM mode. */\r
+ asm volatile ( \\r
+ "LDR R0, =pxCurrentTCB \n\t" \\r
+ "LDR R0, [R0] \n\t" \\r
+ "LDR LR, [R0] \n\t" \\r
+ \\r
+ /* The critical nesting depth is the first item on the stack. */ \\r
+ /* Load it into the ulCriticalNesting variable. */ \\r
+ "LDR R0, =ulCriticalNesting \n\t" \\r
+ "LDMFD LR!, {R1} \n\t" \\r
+ "STR R1, [R0] \n\t" \\r
+ \\r
+ /* Get the SPSR from the stack. */ \\r
+ "LDMFD LR!, {R0} \n\t" \\r
+ "MSR SPSR, R0 \n\t" \\r
+ \\r
+ /* Restore all system mode registers for the task. */ \\r
+ "LDMFD LR, {R0-R14}^ \n\t" \\r
+ "NOP \n\t" \\r
+ \\r
+ /* Restore the return address. */ \\r
+ "LDR LR, [LR, #+60] \n\t" \\r
+ \\r
+ /* And return - correcting the offset in the LR to obtain the */ \\r
+ /* correct address. */ \\r
+ "SUBS PC, LR, #4 \n\t" \\r
+ ); \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The preemptive scheduler is defined as "naked" as the full context is\r
+saved on entry as part of the context switch. */\r
+void vPortTickISR( void )\r
+{\r
+ /* Increment the RTOS tick count, then look for the highest priority \r
+ task that is ready to run. */\r
+ vTaskIncrementTick();\r
+ \r
+ #if configUSE_PREEMPTION == 1\r
+ vTaskSwitchContext();\r
+ #endif\r
+ \r
+ /* Ready for the next interrupt. */\r
+ TB_ClearITPendingBit( TB_IT_Update ); \r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The interrupt management utilities can only be called from ARM mode. When\r
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to\r
+ * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then\r
+ * the utilities are defined as macros in portmacro.h - as per other ports.\r
+ */\r
+#ifdef THUMB_INTERWORK\r
+\r
+ void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+ void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+\r
+ void vPortDisableInterruptsFromThumb( void )\r
+ {\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */\r
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */\r
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */\r
+ "BX R14" ); /* Return back to thumb. */\r
+ }\r
+ \r
+ void vPortEnableInterruptsFromThumb( void )\r
+ {\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \r
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */\r
+ "BX R14" ); /* Return back to thumb. */\r
+ }\r
+\r
+#endif /* THUMB_INTERWORK */\r
+\r
+/* The code generated by the GCC compiler uses the stack in different ways at\r
+different optimisation levels. The interrupt flags can therefore not always\r
+be saved to the stack. Instead the critical section nesting level is stored\r
+in a variable, which is then saved as part of the stack context. */\r
+void vPortEnterCritical( void )\r
+{\r
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */\r
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */\r
+ "LDMIA SP!, {R0}" ); /* Pop R0. */\r
+\r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed \r
+ directly. Increment ulCriticalNesting to keep a count of how many times\r
+ portENTER_CRITICAL() has been called. */\r
+ ulCriticalNesting++;\r
+}\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Decrement the nesting count as we are leaving a critical section. */\r
+ ulCriticalNesting--;\r
+\r
+ /* If the nesting level has reached zero then interrupts should be\r
+ re-enabled. */\r
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Enable interrupts as per portEXIT_CRITICAL(). */\r
+ asm volatile ( \r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \r
+ "LDMIA SP!, {R0}" ); /* Pop R0. */\r
+ }\r
+ }\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned portLONG\r
+#define portBASE_TYPE portLONG\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Hardware specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portBYTE_ALIGNMENT 4\r
+#define portYIELD() asm volatile ( "SWI 0" )\r
+#define portNOP() asm volatile ( "NOP" )\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Critical section handling. */\r
+/*\r
+ * The interrupt management utilities can only be called from ARM mode. When\r
+ * THUMB_INTERWORK is defined the utilities are defined as functions in \r
+ * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not \r
+ * defined then the utilities are defined as macros here - as per other ports.\r
+ */\r
+\r
+#ifdef THUMB_INTERWORK\r
+\r
+ extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+ extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));\r
+\r
+ #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()\r
+ #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()\r
+ \r
+#else\r
+\r
+ #define portDISABLE_INTERRUPTS() \\r
+ asm volatile ( \\r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \\r
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \\r
+ "LDMIA SP!, {R0} " ) /* Pop R0. */\r
+ \r
+ #define portENABLE_INTERRUPTS() \\r
+ asm volatile ( \\r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \\r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \\r
+ "LDMIA SP!, {R0} " ) /* Pop R0. */\r
+\r
+#endif /* THUMB_INTERWORK */\r
+\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+\r
+#define portENTER_CRITICAL() vPortEnterCritical();\r
+#define portEXIT_CRITICAL() vPortExitCritical();\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Task utilities. */\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \\r
+{ \\r
+extern void vTaskSwitchContext( void ); \\r
+ \\r
+ if( xSwitchRequired ) \\r
+ { \\r
+ vTaskSwitchContext(); \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Compiler specifics */\r
+#define inline\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
+\r
projects / freertos / commitdiff