* Function to start the first task executing - written in asm code as direct\r
* access to registers is required. \r
*/\r
-static void prvStartFirstTask( void ) __attribute__((naked));\r
+extern void prvStartFirstTask( void );\r
\r
/*\r
* Software interrupt handler. Performs the actual context switch (saving and\r
static void prvYieldHandler( void );\r
\r
/*\r
- * The entry point for the software interrupt handler. This is the function\r
- * that calls the inline asm function prvYieldHandler(). It is installed in \r
- * the vector table, but the code that installs it is in prvYieldHandler rather\r
- * than using a #pragma.\r
+ * The tick ISR handler. The peripheral used is configured by the application\r
+ * via a hook/callback function.\r
*/\r
-void vSoftwareInterruptISR( void );\r
+void vTickISR( void ) __attribute__((interrupt));\r
\r
/*-----------------------------------------------------------*/\r
\r
-/* This is accessed by the inline assembler functions so is file scope for\r
-convenience. */\r
extern void *pxCurrentTCB;\r
-extern void vTaskSwitchContext( void );\r
\r
/*-----------------------------------------------------------*/\r
\r
\r
/* Ensure the software interrupt is set to the kernel priority. */\r
_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;\r
- \r
+\r
/* Start the first task. */\r
prvStartFirstTask();\r
}\r
\r
- /* Just to make sure the function is not optimised away. */\r
- ( void ) vSoftwareInterruptISR();\r
-\r
/* Should not get here. */\r
return pdFAIL;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-static void prvStartFirstTask( void )\r
-{\r
- __asm\r
- ( \r
- /* When starting the scheduler there is nothing that needs moving to the\r
- interrupt stack because the function is not called from an interrupt.\r
- Just ensure the current stack is the user stack. */\r
- "SETPSW U \n" \\r
-\r
- /* Obtain the location of the stack associated with which ever task \r
- pxCurrentTCB is currently pointing to. */\r
- "MOV.L #_pxCurrentTCB, R15 \n" \\r
- "MOV.L [R15], R15 \n" \\r
- "MOV.L [R15], R0 \n" \\r
-\r
- /* Restore the registers from the stack of the task pointed to by \r
- pxCurrentTCB. */\r
- "POP R15 \n" \\r
- \r
- /* Accumulator low 32 bits. */\r
- "MVTACLO R15 \n" \\r
- "POP R15 \n" \\r
- \r
- /* Accumulator high 32 bits. */\r
- "MVTACHI R15 \n" \\r
- "POP R15 \n" \\r
- \r
- /* Floating point status word. */\r
- "MVTC R15, FPSW \n" \\r
- \r
- /* R1 to R15 - R0 is not included as it is the SP. */\r
- "POPM R1-R15 \n" \\r
- \r
- /* This pops the remaining registers. */\r
- "RTE \n" \\r
- "NOP \n" \\r
- "NOP \n"\r
- );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
void vTickISR( void )\r
{\r
+ /* Re-enable interrupts. */\r
+ __asm volatile( "SETPSW I" );\r
+ \r
/* Increment the tick, and perform any processing the new tick value\r
necessitates. */\r
- vTaskIncrementTick();\r
+ vTaskIncrementTick(); \r
\r
/* Only select a new task if the preemptive scheduler is being used. */\r
#if( configUSE_PREEMPTION == 1 )\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vSoftwareInterruptISR( void )\r
-{\r
-// prvYieldHandler();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-#if 0\r
-#pragma inline_asm prvYieldHandler\r
-static void prvYieldHandler( void )\r
-{\r
- /* Install as the software interrupt handler. */\r
- .RVECTOR _VECT( _ICU_SWINT ), _vSoftwareInterruptISR\r
-\r
- /* Re-enable interrupts. */\r
- SETPSW I\r
-\r
- /* Move the data that was automatically pushed onto the interrupt stack when\r
- the interrupt occurred from the interrupt stack to the user stack. \r
- \r
- R15 is saved before it is clobbered. */\r
- PUSH.L R15\r
- \r
- /* Read the user stack pointer. */\r
- MVFC USP, R15\r
- \r
- /* Move the address down to the data being moved. */\r
- SUB #12, R15\r
- MVTC R15, USP\r
- \r
- /* Copy the data across. */\r
- MOV.L [ R0 ], [ R15 ] ; R15\r
- MOV.L 4[ R0 ], 4[ R15 ] ; PC\r
- MOV.L 8[ R0 ], 8[ R15 ] ; PSW\r
-\r
- /* Move the interrupt stack pointer to its new correct position. */\r
- ADD #12, R0\r
- \r
- /* All the rest of the registers are saved directly to the user stack. */\r
- SETPSW U\r
-\r
- /* Save the rest of the general registers (R15 has been saved already). */\r
- PUSHM R1-R14\r
- \r
- /* Save the FPSW and accumulator. */\r
- MVFC FPSW, R15\r
- PUSH.L R15\r
- MVFACHI R15\r
- PUSH.L R15\r
- MVFACMI R15 ; Middle order word.\r
- SHLL #16, R15 ; Shifted left as it is restored to the low order word.\r
- PUSH.L R15\r
-\r
- /* Save the stack pointer to the TCB. */\r
- MOV.L #_pxCurrentTCB, R15\r
- MOV.L [ R15 ], R15\r
- MOV.L R0, [ R15 ]\r
- \r
- /* Ensure the interrupt mask is set to the syscall priority while the kernel\r
- structures are being accessed. */\r
- MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
-\r
- /* Select the next task to run. */\r
- BSR.A _vTaskSwitchContext\r
-\r
- /* Reset the interrupt mask as no more data structure access is required. */\r
- MVTIPL #configKERNEL_INTERRUPT_PRIORITY\r
-\r
- /* Load the stack pointer of the task that is now selected as the Running\r
- state task from its TCB. */\r
- MOV.L #_pxCurrentTCB,R15\r
- MOV.L [ R15 ], R15\r
- MOV.L [ R15 ], R0\r
-\r
- /* Restore the context of the new task. The PSW (Program Status Word) and\r
- PC will be popped by the RTE instruction. */\r
- POP R15\r
- MVTACLO R15\r
- POP R15\r
- MVTACHI R15\r
- POP R15\r
- MVTC R15,FPSW\r
- POPM R1-R15\r
- RTE\r
- NOP\r
- NOP\r
-}\r
-#endif\r
-/*-----------------------------------------------------------*/\r
-\r
void vPortEndScheduler( void )\r
{\r
/* Not implemented as there is nothing to return to. */\r
- \r
- /* The following line is just to prevent the symbol getting optimised away. */\r
- ( void ) vTaskSwitchContext();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-unsigned long ulPortGetIPL( void )\r
-{\r
- __asm( \r
- "MVFC PSW, R1 \n" \\r
- "SHLR #28, R1 \n" \\r
- "RTS "\r
- );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vPortSetIPL( unsigned long ulNewIPL )\r
-{\r
- __asm( \r
- "MVFC PSW, R5 \n" \\r
- "SHLL #28, R1 \n" \\r
- "AND #-0F000001H, R5 \n" \\r
- "OR R1, R5 \n" \\r
- "MVTC R5, PSW \n" \\r
- "RTS "\r
- );\r
}\r
/*-----------------------------------------------------------*/\r
\r
--- /dev/null
+/*\r
+ FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * If you are: *\r
+ * *\r
+ * + New to FreeRTOS, *\r
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *\r
+ * + Looking for basic training, *\r
+ * + Wanting to improve your FreeRTOS skills and productivity *\r
+ * *\r
+ * then take a look at the FreeRTOS eBook *\r
+ * *\r
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * A pdf reference manual is also available. Both are usually delivered *\r
+ * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+ * and 8pm GMT (although please allow up to 24 hours in case of *\r
+ * exceptional circumstances). Thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+ a combined work that includes FreeRTOS without being obliged to provide the\r
+ source code for proprietary components outside of the FreeRTOS kernel.\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public \r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it \r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained \r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+ .list\r
+ .section .text\r
+ .global _prvStartFirstTask\r
+ .global _vSoftwareInterruptISR\r
+ .global _ulPortGetIPL\r
+ .global _vPortSetIPL\r
+ \r
+ .extern _pxCurrentTCB\r
+\r
+ .align 4\r
+ \r
+_prvStartFirstTask:\r
+\r
+ /* When starting the scheduler there is nothing that needs moving to the\r
+ interrupt stack because the function is not called from an interrupt.\r
+ Just ensure the current stack is the user stack. */\r
+ SETPSW U \r
+\r
+ /* Obtain the location of the stack associated with which ever task \r
+ pxCurrentTCB is currently pointing to. */\r
+ MOV.L #_pxCurrentTCB, R15 \r
+ MOV.L [R15], R15 \r
+ MOV.L [R15], R0 \r
+\r
+ /* Restore the registers from the stack of the task pointed to by \r
+ pxCurrentTCB. */\r
+ POP R15 \r
+ \r
+ /* Accumulator low 32 bits. */\r
+ MVTACLO R15 \r
+ POP R15 \r
+ \r
+ /* Accumulator high 32 bits. */\r
+ MVTACHI R15 \r
+ POP R15 \r
+ \r
+ /* Floating point status word. */\r
+ MVTC R15, FPSW \r
+ \r
+ /* R1 to R15 - R0 is not included as it is the SP. */\r
+ POPM R1-R15 \r
+ \r
+ /* This pops the remaining registers. */\r
+ RTE \r
+ NOP \r
+ NOP \r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ .align 4\r
+_vSoftwareInterruptISR:\r
+\r
+ /* Re-enable interrupts. */\r
+ SETPSW I\r
+\r
+ /* Move the data that was automatically pushed onto the interrupt stack when\r
+ the interrupt occurred from the interrupt stack to the user stack. \r
+ \r
+ R15 is saved before it is clobbered. */\r
+ PUSH.L R15 \r
+ \r
+ /* Read the user stack pointer. */\r
+ MVFC USP, R15 \r
+ \r
+ /* Move the address down to the data being moved. */\r
+ SUB #12, R15 \r
+ MVTC R15, USP \r
+ \r
+ /* Copy the data across, R15, then PC, then PSW. */\r
+ MOV.L [ R0 ], [ R15 ] \r
+ MOV.L 4[ R0 ], 4[ R15 ] \r
+ MOV.L 8[ R0 ], 8[ R15 ] \r
+\r
+ /* Move the interrupt stack pointer to its new correct position. */\r
+ ADD #12, R0 \r
+ \r
+ /* All the rest of the registers are saved directly to the user stack. */\r
+ SETPSW U \r
+\r
+ /* Save the rest of the general registers (R15 has been saved already). */\r
+ PUSHM R1-R14 \r
+ \r
+ /* Save the FPSW and accumulator. */\r
+ MVFC FPSW, R15 \r
+ PUSH.L R15 \r
+ MVFACHI R15 \r
+ PUSH.L R15 \r
+ \r
+ /* Middle word. */\r
+ MVFACMI R15 \r
+ \r
+ /* Shifted left as it is restored to the low order word. */\r
+ SHLL #16, R15 \r
+ PUSH.L R15 \r
+\r
+ /* Save the stack pointer to the TCB. */\r
+ MOV.L #_pxCurrentTCB, R15 \r
+ MOV.L [ R15 ], R15 \r
+ MOV.L R0, [ R15 ] \r
+ \r
+ /* Ensure the interrupt mask is set to the syscall priority while the kernel\r
+ structures are being accessed. */\r
+ MVTIPL #4 \r
+\r
+ /* Select the next task to run. */\r
+ BSR.A _vTaskSwitchContext \r
+\r
+ /* Reset the interrupt mask as no more data structure access is required. */\r
+ MVTIPL #1 \r
+\r
+ /* Load the stack pointer of the task that is now selected as the Running\r
+ state task from its TCB. */\r
+ MOV.L #_pxCurrentTCB,R15 \r
+ MOV.L [ R15 ], R15 \r
+ MOV.L [ R15 ], R0 \r
+\r
+ /* Restore the context of the new task. The PSW (Program Status Word) and\r
+ PC will be popped by the RTE instruction. */\r
+ POP R15 \r
+ MVTACLO R15 \r
+ POP R15 \r
+ MVTACHI R15 \r
+ POP R15 \r
+ MVTC R15, FPSW \r
+ POPM R1-R15 \r
+ RTE \r
+ NOP \r
+ NOP \r
+ \r
+ /*:: i(configMAX_SYSCALL_INTERRUPT_PRIORITY), i(configKERNEL_INTERRUPT_PRIORITY)*/\r
+/*-----------------------------------------------------------*/\r
+\r
+ .align 4\r
+ \r
+_ulPortGetIPL:\r
+\r
+ MVFC PSW, R1\r
+ SHLR #24, R1\r
+ RTS \r
+/*-----------------------------------------------------------*/\r
+\r
+ .align 4\r
+ \r
+_vPortSetIPL:\r
+\r
+ MVFC PSW, R5\r
+ SHLL #24, R1 \r
+ AND #-0F000001H, R5 \r
+ OR R1, R5 \r
+ MVTC R5, PSW \r
+ RTS \r
+\r
+ .end\r
#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */\r
#define portSTACK_GROWTH -1\r
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
-#define portNOP() __asm( "NOP" )\r
+#define portNOP() __asm volatile( "NOP" )\r
\r
/* The location of the software interrupt register. Software interrupts use\r
vector 27. */\r
* These macros should be called directly, but through the taskENTER_CRITICAL()\r
* and taskEXIT_CRITICAL() macros.\r
*/\r
-#define portENABLE_INTERRUPTS() __asm ( "MVTIPL #0" );\r
-#define portDISABLE_INTERRUPTS() __asm ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" );\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )\r
\r
/* Critical nesting counts are stored in the TCB. */\r
#define portCRITICAL_NESTING_IN_TCB ( 1 )\r
#define portEXIT_CRITICAL() vTaskExitCritical();\r
\r
/* As this port allows interrupt nesting... */\r
-unsigned long ulPortGetIPL( void ) __attribute__((naked));\r
-void vPortSetIPL( unsigned long ulNewIPL ) __attribute__((naked));\r
+unsigned long ulPortGetIPL( void );\r
+void vPortSetIPL( unsigned long ulNewIPL );\r
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()\r
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )\r
\r
projects / freertos / commitdiff