Duane Ellis <openocd@duaneellis.com> - script commands for stm32

git-svn-id: svn://svn.berlios.de/openocd/trunk@842 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/src/Makefile.am b/src/Makefile.am
index 793d020ae31b4acdb1d4390789c04d219f28dbb0..3080839c747c3cbd15e92a98e3762e78f4239227 100644 (file)
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -79,18 +79,20 @@ openocd_LDADD = $(top_builddir)/src/xsvf/libxsvf.a \
        $(FTDI2232LIB) $(FTD2XXLIB) $(MINGWLDADD) $(LIBUSB)
 
 nobase_dist_pkglib_DATA = \
-       tcl/bitsbytes.tcl  \
-       tcl/chip/atmel/at91/aic.tcl  \
-       tcl/chip/atmel/at91/at91sam7x128.tcl  \
-       tcl/chip/atmel/at91/at91sam7x256.tcl  \
-       tcl/chip/atmel/at91/pmc.tcl  \
-       tcl/chip/atmel/at91/rtt.tcl  \
-       tcl/chip/atmel/at91/usarts.tcl  \
-       tcl/cpu/arm/arm7tdmi.tcl  \
-       tcl/cpu/arm/arm920.tcl  \
-       tcl/cpu/arm/arm946.tcl  \
-       tcl/cpu/arm/arm966.tcl  \
-       tcl/memory.tcl  \
-       tcl/mmr_helpers.tcl  \
-       tcl/readable.tcl  
-
+       tcl/bitsbytes.tcl                       \
+       tcl/chip/atmel/at91/aic.tcl             \
+       tcl/chip/atmel/at91/at91sam7x128.tcl    \
+       tcl/chip/atmel/at91/at91sam7x256.tcl    \
+       tcl/chip/atmel/at91/pmc.tcl             \
+       tcl/chip/atmel/at91/rtt.tcl             \
+       tcl/chip/atmel/at91/usarts.tcl          \
+       tcl/chip/st/stm32/stm32.tcl             \
+       tcl/chip/st/stm32/stm32_rcc.tcl         \
+       tcl/chip/st/stm32/stm32_regs.tcl        \
+       tcl/cpu/arm/arm7tdmi.tcl                \
+       tcl/cpu/arm/arm920.tcl                  \
+       tcl/cpu/arm/arm946.tcl                  \
+       tcl/cpu/arm/arm966.tcl                  \
+       tcl/memory.tcl                          \
+       tcl/mmr_helpers.tcl                     \
+       tcl/readable.tcl

diff --git a/src/tcl/chip/st/stm32/stm32.tcl b/src/tcl/chip/st/stm32/stm32.tcl
new file mode 100644 (file)
index 0000000..4d3096a
--- /dev/null
+++ b/src/tcl/chip/st/stm32/stm32.tcl
@@ -0,0 +1,7 @@
+source [find tcl/bitsbytes.tcl]\r
+source [find tcl/cpu/arm/cortex_m3.tcl]\r
+source [find tcl/memory.tcl]\r
+source [find tcl/mmr_helpers.tcl]\r
+\r
+source [find tcl/chip/st/stm32/stm32_regs.tcl]\r
+source [find tcl/chip/st/stm32/stm32_rcc.tcl]\r

diff --git a/src/tcl/chip/st/stm32/stm32_rcc.tcl b/src/tcl/chip/st/stm32/stm32_rcc.tcl
new file mode 100644 (file)
index 0000000..756ebc6
--- /dev/null
+++ b/src/tcl/chip/st/stm32/stm32_rcc.tcl
@@ -0,0 +1,290 @@
+\r
+set RCC_CR            [expr $RCC_BASE + 0x00]\r
+set RCC_CFGR          [expr $RCC_BASE + 0x04]\r
+set RCC_CIR           [expr $RCC_BASE + 0x08]\r
+set RCC_APB2RSTR      [expr $RCC_BASE + 0x0c]\r
+set RCC_APB1RSTR      [expr $RCC_BASE + 0x10]\r
+set RCC_AHBENR        [expr $RCC_BASE + 0x14]\r
+set RCC_APB2ENR       [expr $RCC_BASE + 0x18]\r
+set RCC_APB1ENR       [expr $RCC_BASE + 0x1c]\r
+set RCC_BDCR          [expr $RCC_BASE + 0x20]\r
+set RCC_CSR           [expr $RCC_BASE + 0x24]\r
+\r
+\r
+proc show_RCC_CR { } {\r
+    if [ catch { set val [show_mmr32_reg RCC_CR] } msg ] {\r
+       error $msg\r
+    }\r
+\r
+    show_mmr_bitfield  0  0 $val HSI      { OFF ON } \r
+    show_mmr_bitfield  1  1 $val HSIRDY   { NOTRDY RDY  }\r
+    show_mmr_bitfield  7  3 $val HSITRIM  { _NUMBER_ }\r
+    show_mmr_bitfield 15  8 $val HSICAL   { _NUMBER_ }\r
+    show_mmr_bitfield 16 16 $val HSEON    { OFF ON }\r
+    show_mmr_bitfield 17 17 $val HSERDY   { NOTRDY RDY  }\r
+    show_mmr_bitfield 18 18 $val HSEBYP   { NOTBYPASSED BYPASSED }\r
+    show_mmr_bitfield 19 19 $val CSSON    { OFF ON }\r
+    show_mmr_bitfield 24 24 $val PLLON    { OFF ON }\r
+    show_mmr_bitfield 25 25 $val PLLRDY   { NOTRDY RDY }\r
+}    \r
+       \r
+proc show_RCC_CFGR { } {\r
+    if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] {\r
+       error $msg\r
+    }\r
+\r
+\r
+    show_mmr_bitfield  1  0 $val  SW     { HSI HSE PLL ILLEGAL }\r
+    show_mmr_bitfield  3  2 $val  SWS    { HSI HSE PLL ILLEGAL }\r
+    show_mmr_bitfield  7  4 $val  HPRE   { sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_2 sysclk_div_4 sysclk_div_8 sysclk_div_16 sysclk_div_64 sysclk_div_128 sysclk_div_256 sysclk_div_512 }\r
+    show_mmr_bitfield 10  8 $val  PPRE1  { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }\r
+    show_mmr_bitfield 13 11 $val  PPRE2  { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }\r
+    show_mmr_bitfield 15 14 $val  ADCPRE { pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div2 pclk2_div4 pclk2_div8 pclk2_div16 }\r
+    show_mmr_bitfield 16 16 $val  PLLSRC { HSI_div_2 HSE }\r
+    show_mmr_bitfield 17 17 $val  PLLXTPRE { hse_div1 hse_div2 }\r
+    show_mmr_bitfield 21 18 $val  PLLMUL { x2 x3 x4 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16 }\r
+    show_mmr_bitfield 22 22 $val  USBPRE { div1 div1_5 }\r
+    show_mmr_bitfield 26 24 $val  MCO    { none none none none SysClk HSI HSE PLL_div2 }\r
+}\r
+\r
+    \r
+proc show_RCC_CIR { } {\r
+    if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] {\r
+       error $msg\r
+    }\r
+ \r
+}\r
+\r
+proc show_RCC_APB2RSTR { } {\r
+    if [ catch { set val [ show_mmr32_reg RCC_APB2RSTR] } msg ] {\r
+       error $msg\r
+    }\r
+    for { set x 0 } { $x < 32 } { incr x } {\r
+       set bits($x) xxx\r
+    }\r
+    set bits(15) adc3\r
+    set bits(14) usart1\r
+    set bits(13) tim8\r
+    set bits(12) spi1\r
+    set bits(11) tim1\r
+    set bits(10) adc2\r
+    set bits(9) adc1\r
+    set bits(8) iopg\r
+    set bits(7) iopf\r
+    set bits(6) iope\r
+    set bits(5) iopd\r
+    set bits(4) iopc\r
+    set bits(3) iopb\r
+    set bits(2) iopa\r
+    set bits(1) xxx\r
+    set bits(0) afio\r
+    show_mmr32_bits bits $val\r
+}\r
+\r
+proc show_RCC_APB1RSTR { } {\r
+    if [ catch { set val [ show_mmr32_reg RCC_APB1RSTR] } msg ] {\r
+       error $msg\r
+    }\r
+    set bits(31) xxx\r
+    set bits(30) xxx\r
+    set bits(29) dac\r
+    set bits(28) pwr\r
+    set bits(27) bkp\r
+    set bits(26) xxx\r
+    set bits(25) can\r
+    set bits(24) xxx\r
+    set bits(23) usb\r
+    set bits(22) i2c2\r
+    set bits(21) i2c1\r
+    set bits(20) uart5\r
+    set bits(19) uart4\r
+    set bits(18) uart3\r
+    set bits(17) uart2\r
+    set bits(16) xxx\r
+    set bits(15) spi3\r
+    set bits(14) spi2\r
+    set bits(13) xxx\r
+    set bits(12) xxx\r
+    set bits(11) wwdg\r
+    set bits(10) xxx \r
+    set bits(9) xxx\r
+    set bits(8) xxx\r
+    set bits(7) xxx\r
+    set bits(6) xxx\r
+    set bits(5) tim7\r
+    set bits(4) tim6\r
+    set bits(3) tim5\r
+    set bits(2) tim4\r
+    set bits(1) tim3\r
+    set bits(0) tim2\r
+    show_mmr32_bits bits $val\r
+    \r
+}\r
+\r
+proc show_RCC_AHBENR   { } {\r
+    if [ catch { set val [ show_mmr32_reg RCC_AHBENR  ] } msg ] {\r
+       error $msg\r
+    }\r
+    set bits(31) xxx\r
+    set bits(30) xxx\r
+    set bits(29) xxx\r
+    set bits(28) xxx\r
+    set bits(27) xxx\r
+    set bits(26) xxx\r
+    set bits(25) xxx\r
+    set bits(24) xxx\r
+    set bits(23) xxx\r
+    set bits(22) xxx\r
+    set bits(21) xxx\r
+    set bits(20) xxx\r
+    set bits(19) xxx\r
+    set bits(18) xxx\r
+    set bits(17) xxx\r
+    set bits(16) xxx\r
+    set bits(15) xxx  \r
+    set bits(14) xxx\r
+    set bits(13) xxx\r
+    set bits(12) xxx\r
+    set bits(11) xxx\r
+    set bits(10) sdio\r
+    set bits(9) xxx\r
+    set bits(8) fsmc\r
+    set bits(7) xxx\r
+    set bits(6) crce\r
+    set bits(5) xxx\r
+    set bits(4) flitf\r
+    set bits(3) xxx\r
+    set bits(2) sram\r
+    set bits(1) dma2\r
+    set bits(0) dma1\r
+    show_mmr32_bits bits $val\r
+}\r
+\r
+proc show_RCC_APB2ENR  { } {\r
+    if [ catch { set val [ show_mmr32_reg RCC_APB2ENR ] } msg ] {\r
+       error $msg\r
+    }\r
+    set bits(31) xxx\r
+    set bits(30) xxx\r
+    set bits(29) xxx\r
+    set bits(28) xxx\r
+    set bits(27) xxx\r
+    set bits(26) xxx\r
+    set bits(25) xxx\r
+    set bits(24) xxx\r
+    set bits(23) xxx\r
+    set bits(22) xxx\r
+    set bits(21) xxx\r
+    set bits(20) xxx\r
+    set bits(19) xxx\r
+    set bits(18) xxx\r
+    set bits(17) xxx\r
+    set bits(16) xxx\r
+    set bits(15) adc3  \r
+    set bits(14) usart1\r
+    set bits(13) tim8\r
+    set bits(12) spi1\r
+    set bits(11) tim1\r
+    set bits(10) adc2\r
+    set bits(9) adc1\r
+    set bits(8) iopg\r
+    set bits(7) iopf\r
+    set bits(6) iope\r
+    set bits(5) iopd\r
+    set bits(4) iopc\r
+    set bits(3) iopb\r
+    set bits(2) iopa\r
+    set bits(1) xxx\r
+    set bits(0) afio\r
+    show_mmr32_bits bits $val\r
+\r
+}\r
+\r
+proc show_RCC_APB1ENR  { } {\r
+    if [ catch { set val [ show_mmr32_reg RCC_APB1ENR ] } msg ] {\r
+       error $msg\r
+    }\r
+    set bits(31) xxx\r
+    set bits(30) xxx\r
+    set bits(29) dac\r
+    set bits(28) pwr\r
+    set bits(27) bkp\r
+    set bits(26) xxx\r
+    set bits(25) can\r
+    set bits(24) xxx\r
+    set bits(23) usb\r
+    set bits(22) i2c2\r
+    set bits(21) i2c1\r
+    set bits(20) usart5\r
+    set bits(19) usart4\r
+    set bits(18) usart3\r
+    set bits(17) usart2\r
+    set bits(16) xxx\r
+    set bits(15) spi3\r
+    set bits(14) spi2\r
+    set bits(13) xxx\r
+    set bits(12) xxx\r
+    set bits(11) wwdg\r
+    set bits(10) xxx\r
+    set bits(9) xxx\r
+    set bits(8) xxx\r
+    set bits(7) xxx\r
+    set bits(6) xxx\r
+    set bits(5) tim7\r
+    set bits(4) tim6\r
+    set bits(3) tim5\r
+    set bits(2) tim4\r
+    set bits(1) tim3\r
+    set bits(0) tim2\r
+    show_mmr32_bits bits $val\r
+}\r
+\r
+proc show_RCC_BDCR     { } {\r
+    if [ catch { set val [ show_mmr32_reg RCC_BDCR    ] } msg ] {\r
+       error $msg\r
+    }\r
+    for { set x 0 } { $x < 32 } { incr x } {\r
+       set bits($x) xxx\r
+    }\r
+    set bits(0) lseon\r
+    set bits(1) lserdy\r
+    set bits(2) lsebyp\r
+    set bits(8) rtcsel0\r
+    set bits(9) rtcsel1\r
+    set bits(15) rtcen\r
+    set bits(16) bdrst\r
+    show_mmr32_bits bits $val\r
+}\r
+\r
+proc show_RCC_CSR      { } {\r
+    if [ catch { set val [ show_mmr32_reg RCC_CSR     ] } msg ] {\r
+       error $msg\r
+    }\r
+    for { set x 0 } { $x < 32 } { incr x } {\r
+       set bits($x) xxx\r
+    }\r
+    set bits(0) lsion\r
+    set bits(1) lsirdy\r
+    set bits(24) rmvf\r
+    set bits(26) pin\r
+    set bits(27) por\r
+    set bits(28) sft\r
+    set bits(29) iwdg\r
+    set bits(30) wwdg\r
+    set bits(31) lpwr\r
+    show_mmr32_bits bits $val\r
+}\r
+\r
+proc show_RCC { } {\r
+\r
+    show_RCC_CR\r
+    show_RCC_CFGR\r
+    show_RCC_CIR\r
+    show_RCC_APB2RSTR\r
+    show_RCC_APB1RSTR\r
+    show_RCC_AHBENR\r
+    show_RCC_APB2ENR\r
+    show_RCC_APB1ENR\r
+    show_RCC_BDCR\r
+    show_RCC_CSR\r
+}\r

diff --git a/src/tcl/chip/st/stm32/stm32_regs.tcl b/src/tcl/chip/st/stm32/stm32_regs.tcl
new file mode 100644 (file)
index 0000000..936d2f3
--- /dev/null
+++ b/src/tcl/chip/st/stm32/stm32_regs.tcl
@@ -0,0 +1,95 @@
+# /* Peripheral and SRAM base address in the alias region */\r
+set PERIPH_BB_BASE        0x42000000\r
+set SRAM_BB_BASE          0x22000000\r
+\r
+# /*Peripheral and SRAM base address in the bit-band region */\r
+set SRAM_BASE             0x20000000\r
+set PERIPH_BASE           0x40000000\r
+\r
+# /*FSMC registers base address */\r
+set FSMC_R_BASE           0xA0000000\r
+\r
+# /*Peripheral memory map */\r
+set APB1PERIPH_BASE       [set PERIPH_BASE]\r
+set APB2PERIPH_BASE       [expr $PERIPH_BASE + 0x10000]\r
+set AHBPERIPH_BASE        [expr $PERIPH_BASE + 0x20000]\r
+\r
+set TIM2_BASE             [expr $APB1PERIPH_BASE + 0x0000]\r
+set TIM3_BASE             [expr $APB1PERIPH_BASE + 0x0400]\r
+set TIM4_BASE             [expr $APB1PERIPH_BASE + 0x0800]\r
+set TIM5_BASE             [expr $APB1PERIPH_BASE + 0x0C00]\r
+set TIM6_BASE             [expr $APB1PERIPH_BASE + 0x1000]\r
+set TIM7_BASE             [expr $APB1PERIPH_BASE + 0x1400]\r
+set RTC_BASE              [expr $APB1PERIPH_BASE + 0x2800]\r
+set WWDG_BASE             [expr $APB1PERIPH_BASE + 0x2C00]\r
+set IWDG_BASE             [expr $APB1PERIPH_BASE + 0x3000]\r
+set SPI2_BASE             [expr $APB1PERIPH_BASE + 0x3800]\r
+set SPI3_BASE             [expr $APB1PERIPH_BASE + 0x3C00]\r
+set USART2_BASE           [expr $APB1PERIPH_BASE + 0x4400]\r
+set USART3_BASE           [expr $APB1PERIPH_BASE + 0x4800]\r
+set UART4_BASE            [expr $APB1PERIPH_BASE + 0x4C00]\r
+set UART5_BASE            [expr $APB1PERIPH_BASE + 0x5000]\r
+set I2C1_BASE             [expr $APB1PERIPH_BASE + 0x5400]\r
+set I2C2_BASE             [expr $APB1PERIPH_BASE + 0x5800]\r
+set CAN_BASE              [expr $APB1PERIPH_BASE + 0x6400]\r
+set BKP_BASE              [expr $APB1PERIPH_BASE + 0x6C00]\r
+set PWR_BASE              [expr $APB1PERIPH_BASE + 0x7000]\r
+set DAC_BASE              [expr $APB1PERIPH_BASE + 0x7400]\r
+\r
+set AFIO_BASE             [expr $APB2PERIPH_BASE + 0x0000]\r
+set EXTI_BASE             [expr $APB2PERIPH_BASE + 0x0400]\r
+set GPIOA_BASE            [expr $APB2PERIPH_BASE + 0x0800]\r
+set GPIOB_BASE            [expr $APB2PERIPH_BASE + 0x0C00]\r
+set GPIOC_BASE            [expr $APB2PERIPH_BASE + 0x1000]\r
+set GPIOD_BASE            [expr $APB2PERIPH_BASE + 0x1400]\r
+set GPIOE_BASE            [expr $APB2PERIPH_BASE + 0x1800]\r
+set GPIOF_BASE            [expr $APB2PERIPH_BASE + 0x1C00]\r
+set GPIOG_BASE            [expr $APB2PERIPH_BASE + 0x2000]\r
+set ADC1_BASE             [expr $APB2PERIPH_BASE + 0x2400]\r
+set ADC2_BASE             [expr $APB2PERIPH_BASE + 0x2800]\r
+set TIM1_BASE             [expr $APB2PERIPH_BASE + 0x2C00]\r
+set SPI1_BASE             [expr $APB2PERIPH_BASE + 0x3000]\r
+set TIM8_BASE             [expr $APB2PERIPH_BASE + 0x3400]\r
+set USART1_BASE           [expr $APB2PERIPH_BASE + 0x3800]\r
+set ADC3_BASE             [expr $APB2PERIPH_BASE + 0x3C00]\r
+\r
+set SDIO_BASE             [expr $PERIPH_BASE + 0x18000]\r
+\r
+set DMA1_BASE             [expr $AHBPERIPH_BASE + 0x0000]\r
+set DMA1_Channel1_BASE    [expr $AHBPERIPH_BASE + 0x0008]\r
+set DMA1_Channel2_BASE    [expr $AHBPERIPH_BASE + 0x001C]\r
+set DMA1_Channel3_BASE    [expr $AHBPERIPH_BASE + 0x0030]\r
+set DMA1_Channel4_BASE    [expr $AHBPERIPH_BASE + 0x0044]\r
+set DMA1_Channel5_BASE    [expr $AHBPERIPH_BASE + 0x0058]\r
+set DMA1_Channel6_BASE    [expr $AHBPERIPH_BASE + 0x006C]\r
+set DMA1_Channel7_BASE    [expr $AHBPERIPH_BASE + 0x0080]\r
+set DMA2_BASE             [expr $AHBPERIPH_BASE + 0x0400]\r
+set DMA2_Channel1_BASE    [expr $AHBPERIPH_BASE + 0x0408]\r
+set DMA2_Channel2_BASE    [expr $AHBPERIPH_BASE + 0x041C]\r
+set DMA2_Channel3_BASE    [expr $AHBPERIPH_BASE + 0x0430]\r
+set DMA2_Channel4_BASE    [expr $AHBPERIPH_BASE + 0x0444]\r
+set DMA2_Channel5_BASE    [expr $AHBPERIPH_BASE + 0x0458]\r
+set RCC_BASE              [expr $AHBPERIPH_BASE + 0x1000]\r
+set CRC_BASE              [expr $AHBPERIPH_BASE + 0x3000]\r
+\r
+# /*Flash registers base address */\r
+set FLASH_R_BASE          [expr $AHBPERIPH_BASE + 0x2000]\r
+# /*Flash Option Bytes base address */\r
+set OB_BASE               0x1FFFF800\r
+\r
+# /*FSMC Bankx registers base address */\r
+set FSMC_Bank1_R_BASE     [expr $FSMC_R_BASE + 0x0000]\r
+set FSMC_Bank1E_R_BASE    [expr $FSMC_R_BASE + 0x0104]\r
+set FSMC_Bank2_R_BASE     [expr $FSMC_R_BASE + 0x0060]\r
+set FSMC_Bank3_R_BASE     [expr $FSMC_R_BASE + 0x0080]\r
+set FSMC_Bank4_R_BASE     [expr $FSMC_R_BASE + 0x00A0]\r
+\r
+# /*Debug MCU registers base address */\r
+set DBGMCU_BASE           0xE0042000\r
+\r
+# /*System Control Space memory map */\r
+set SCS_BASE              0xE000E000\r
+\r
+set SysTick_BASE          [expr $SCS_BASE + 0x0010]\r
+set NVIC_BASE             [expr $SCS_BASE + 0x0100]\r
+set SCB_BASE              [expr $SCS_BASE + 0x0D00]\r

diff --git a/src/tcl/mmr_helpers.tcl b/src/tcl/mmr_helpers.tcl
index 5dac48a8fda3a4378cded28b1c2823bb77e6fb7f..ea2210ac4a6f99728e07d4b3a5c3ab48855eba55 100644 (file)
--- a/src/tcl/mmr_helpers.tcl
+++ b/src/tcl/mmr_helpers.tcl
@@ -13,7 +13,7 @@ proc show_mmr32_reg { NAME } {
     set a [set [set NAME]]
 
     if ![catch { set v [memread32 $a] } msg ] {
-       puts [format "%10s: (0x%08x): 0x%08x" $NAME $a $v]
+       puts [format "%15s: (0x%08x): 0x%08x" $NAME $a $v]
 
        # Was a helper defined?
        set fn show_${NAME}_helper
@@ -36,7 +36,7 @@ proc show_mmr32_bits { NAMES VAL } {
 
     upvar $NAMES MYNAMES
 
-    set w 0
+    set w 5
     foreach {IDX N} $MYNAMES {
        set l [string length $N]
        if { $l > $w } { set w $l }
@@ -57,3 +57,16 @@ proc show_mmr32_bits { NAMES VAL } {
        puts ""
     }
 }
+
+
+proc show_mmr_bitfield { MSB LSB VAL FIELDNAME FIELDVALUES } {
+    set width [expr (($MSB - $LSB + 1) + 7) / 4]
+    set nval [show_normalize_bitfield $VAL $MSB $LSB ]
+    set name0 [lindex $FIELDVALUES 0 ]
+    if [ string compare $name0 _NUMBER_ ] {
+       set sval [lindex $FIELDVALUES $nval]
+    } else {
+       set sval ""
+    }
+    puts [format "%-15s: %d (0x%0*x) %s" $FIELDNAME $nval $width $nval $sval ]
+}