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#define configUSE_PREEMPTION 1\r
#define configUSE_IDLE_HOOK 1\r
#define configUSE_TICK_HOOK 1\r
-#define configCPU_CLOCK_HZ ( ( unsigned long ) ( SYS_CLK_FREQ ) )\r
-//#define configCPU_CLOCK_HZ ( ( unsigned long ) ( SYS_CLK_FREQ / 100 ) ) /*_RB_ Seems to be a factor of 100 between machine timer frequency and CPU frequency. */\r
+//#define configCPU_CLOCK_HZ ( ( unsigned long ) ( SYS_CLK_FREQ ) )\r
+#define configCPU_CLOCK_HZ ( ( unsigned long ) ( SYS_CLK_FREQ / 100 ) ) /*_RB_ Seems to be a factor of 100 between machine timer frequency and CPU frequency. */\r
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )\r
#define configMAX_PRIORITIES ( 5 )\r
-#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 200 ) /* Can be as low as 60 but some of the demo tasks that use this constant require it to be higher. */\r
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 300 * 1024 ) )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 150 ) /* Can be as low as 60 but some of the demo tasks that use this constant require it to be higher. */\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 280 * 1024 ) )\r
#define configMAX_TASK_NAME_LEN ( 16 )\r
#define configUSE_TRACE_FACILITY 0\r
#define configUSE_16_BIT_TICKS 0\r
\r
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0\r
\r
-#define handle_m_ext_interrupt vPortHandleInterrupt\r
-\r
\r
#endif /* FREERTOS_CONFIG_H */\r
+++ /dev/null
-## FreeRTOS port for Mi-V Soft Processor\r
-\r
-### HW Platform and FPGA design:\r
-This project is tested on following hardware platforms:\r
-\r
-RISCV-Creative-Board\r
-- [RISC-V Creative board Mi-V Sample Design](https://github.com/RISCV-on-Microsemi-FPGA/RISC-V-Creative-Board/tree/master/Programming_The_Target_Device/PROC_SUBSYSTEM_MIV_RV32IMA_BaseDesign)\r
-\r
-PolarFire-Eval-Kit\r
-- [PolarFire Eval Kit RISC-V Sample Design](https://github.com/RISCV-on-Microsemi-FPGA/PolarFire-Eval-Kit/tree/master/Programming_The_Target_Device/MIV_RV32IMA_L1_AHB_BaseDesign)\r
-\r
-SmartFusion2-Advanced-Dev-Kit\r
-- [SmartFusion2 Advanced Development Kit RISC-V Sample Design](https://github.com/RISCV-on-Microsemi-FPGA/SmartFusion2-Advanced-Dev-Kit/tree/master/Programming_The_Target_Device/PROC_SUBSYSTEM_BaseDesign)\r
-\r
-### How to run the FreeRTOS RISC-V port:\r
-To know how to use the SoftConsole workspace, please refer the [Readme.md](https://github.com/RISCV-on-Microsemi-FPGA/SoftConsole/blob/master/README.md)\r
-\r
-The miv-rv32im-freertos-port-test is a self contained project. This project demonstrates \r
-the FreeRTOS running with Microsemi RISC-V processor. This project creates two \r
-tasks and runs them at regular intervals.\r
- \r
-This example project requires USB-UART interface to be connected to a host PC. \r
-The host PC must connect to the serial port using a terminal emulator such as \r
-TeraTerm or PuTTY configured as follows:\r
- \r
- - 115200 baud\r
- - 8 data bits\r
- - 1 stop bit\r
- - no parity\r
- - no flow control\r
- \r
-The ./hw_platform.h file contains the design related information that is required \r
-for this project. If you update the design, the hw_platform.h must be updated \r
-accordingly.\r
-\r
-### FreeRTOS Configurations\r
-You must configure the FreeRTOS as per your applications need. Please read and modify FreeRTOSConfig.h.\r
-E.g. You must set configCPU_CLOCK_HZ parameter in FreeRTOSConfig.h according to the hardware platform \r
-design that you are using. \r
-\r
-The RISC-V creative board design uses 66Mhz processor clock. The PolarFire Eval Kit design uses 50Mhz processor clock. The SmartFusion2 Adv. Development kit design uses 83Mhz processor clock.\r
-\r
-### Microsemi SoftConsole Toolchain\r
-To know more please refer: [SoftConsole](https://github.com/RISCV-on-Microsemi-FPGA/SoftConsole)\r
-\r
-### Documentation for Microsemi RISC-V processor, SoftConsole toochain, Debug Tools, FPGA design etc.\r
-To know more please refer: [Documentation](https://github.com/RISCV-on-Microsemi-FPGA/Documentation)\r
- \r