]> git.sur5r.net Git - freertos/commitdiff
First LPC17xx demo added.
authorrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Thu, 28 May 2009 11:48:32 +0000 (11:48 +0000)
committerrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Thu, 28 May 2009 11:48:32 +0000 (11:48 +0000)
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@733 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

80 files changed:
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.lock [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.core/.log [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.core/shareddefaults.xml [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.make.core/.log [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.make.core/RTOSDemo.sc [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.make.ui/dialog_settings.xml [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.projects/RTOSDemo/.indexes/history.index [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.projects/RTOSDemo/.indexes/properties.index [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.projects/RTOSDemo/.markers [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.root/8.tree [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.crt.quickstart.prefs [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.crt.trueview.prefs [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-RTOSDemo.prefs [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.debug.core/.launches/RTOSDemo.launch [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/version.ini [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/.cproject [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/.project [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/FreeRTOSConfig.h [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/LCD/portlcd.c [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/LCD/portlcd.h [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/LPC17xx.h [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/LPC17xx_defs.h [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/Makefile [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/core_cm3.h [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/cr_startup_nxp_cm3.c [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/main.c [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/printf-stdarg.c [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/rtosdemo_lpc1766.ld [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/syscalls.c [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/system_LPC17xx.h [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/clock-arch.h [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/emac.c [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/emac.h [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/http-strings [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/http-strings.c [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/http-strings.h [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-cgi.c [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-cgi.h [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs.c [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs.h [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/404.html [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/index.html [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/index.shtml [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/io.shtml [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/runtime.shtml [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/stats.shtml [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/tcp.shtml [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fsdata.c [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fsdata.h [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd.c [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd.h [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/makefsdata [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/makestrings [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/uIP_Task.c [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/uip-conf.h [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/webserver.h [new file with mode: 0644]
Demo/CORTEX_LPC1766_GCC_RedSuite/import.log [new file with mode: 0644]

diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.lock b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.lock
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diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.core/shareddefaults.xml b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.core/shareddefaults.xml
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diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.make.core/RTOSDemo.sc b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.make.core/RTOSDemo.sc
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+<definedSymbol symbol="__REGISTER_PREFIX__"/>\r
+<definedSymbol symbol="__USER_LABEL_PREFIX__"/>\r
+<definedSymbol symbol="__VERSION__=&quot;4.3.2&quot;"/>\r
+<definedSymbol symbol="__GNUC_GNU_INLINE__=1"/>\r
+<definedSymbol symbol="__NO_INLINE__=1"/>\r
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+<definedSymbol symbol="__SIZEOF_SHORT__=2"/>\r
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+<definedSymbol symbol="__arm__=1"/>\r
+<definedSymbol symbol="__APCS_32__=1"/>\r
+<definedSymbol symbol="__ARMEL__=1"/>\r
+<definedSymbol symbol="__SOFTFP__=1"/>\r
+<definedSymbol symbol="__VFP_FP__=1"/>\r
+<definedSymbol symbol="__THUMB_INTERWORK__=1"/>\r
+<definedSymbol symbol="__ARM_ARCH_4T__=1"/>\r
+<definedSymbol symbol="__ARM_EABI__=1"/>\r
+<definedSymbol symbol="__GXX_TYPEINFO_EQUALITY_INLINE=0"/>\r
+<definedSymbol symbol="__ELF__=1"/>\r
+<definedSymbol symbol="__USES_INITFINI__=1"/>\r
+</collector>\r
+</instance>\r
+</scannerInfo>\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c
new file mode 100644 (file)
index 0000000..8b13789
--- /dev/null
@@ -0,0 +1 @@
+
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp
new file mode 100644 (file)
index 0000000..8b13789
--- /dev/null
@@ -0,0 +1 @@
+
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.make.ui/dialog_settings.xml b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.make.ui/dialog_settings.xml
new file mode 100644 (file)
index 0000000..9e62c4b
--- /dev/null
@@ -0,0 +1,5 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<section name="Workbench">\r
+       <section name="org.eclipse.cdt.internal.ui.MakeView">\r
+       </section>\r
+</section>\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml
new file mode 100644 (file)
index 0000000..53d5db4
--- /dev/null
@@ -0,0 +1,5 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<section name="Workbench">\r
+       <section name="completion_proposal_size">\r
+       </section>\r
+</section>\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.projects/RTOSDemo/.indexes/history.index b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.projects/RTOSDemo/.indexes/history.index
new file mode 100644 (file)
index 0000000..ccacdf3
Binary files /dev/null and b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.projects/RTOSDemo/.indexes/history.index differ
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.projects/RTOSDemo/.indexes/properties.index b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.projects/RTOSDemo/.indexes/properties.index
new file mode 100644 (file)
index 0000000..d5cd77d
Binary files /dev/null and b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.projects/RTOSDemo/.indexes/properties.index differ
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.projects/RTOSDemo/.markers b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.projects/RTOSDemo/.markers
new file mode 100644 (file)
index 0000000..0901dab
Binary files /dev/null and b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.projects/RTOSDemo/.markers differ
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version
new file mode 100644 (file)
index 0000000..25cb955
--- /dev/null
@@ -0,0 +1 @@
+\ 2
\ No newline at end of file
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index
new file mode 100644 (file)
index 0000000..c3c633a
Binary files /dev/null and b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index differ
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version
new file mode 100644 (file)
index 0000000..6b2aaa7
--- /dev/null
@@ -0,0 +1 @@
+\ 1
\ No newline at end of file
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.root/8.tree b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.root/8.tree
new file mode 100644 (file)
index 0000000..f2bb446
Binary files /dev/null and b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.root/8.tree differ
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources
new file mode 100644 (file)
index 0000000..83c0fc5
Binary files /dev/null and b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources differ
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.crt.quickstart.prefs b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.crt.quickstart.prefs
new file mode 100644 (file)
index 0000000..69fbd4f
--- /dev/null
@@ -0,0 +1,3 @@
+#Wed May 27 16:01:22 BST 2009\r
+quickstart.hideview=true\r
+eclipse.preferences.version=1\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.crt.trueview.prefs b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.crt.trueview.prefs
new file mode 100644 (file)
index 0000000..4f4d89d
--- /dev/null
@@ -0,0 +1,3 @@
+#Thu May 28 12:41:58 BST 2009\r
+eclipse.preferences.version=1\r
+pref_state_memento.com.crt.trueview.views.CRTRegisterViewer=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<VariablesViewMemento/>\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-RTOSDemo.prefs b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-RTOSDemo.prefs
new file mode 100644 (file)
index 0000000..d5377d8
--- /dev/null
@@ -0,0 +1,3 @@
+#Wed May 27 15:06:36 BST 2009\r
+eclipse.preferences.version=1\r
+indexer/preferenceScope=0\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs
new file mode 100644 (file)
index 0000000..72c7478
--- /dev/null
@@ -0,0 +1,3 @@
+#Wed May 27 15:04:52 BST 2009\r
+org.eclipse.cdt.debug.core.cDebug.common_source_containers=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<sourceLookupDirector>\r\n<sourceContainers duplicates\="false"/>\r\n</sourceLookupDirector>\r\n\r
+eclipse.preferences.version=1\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs
new file mode 100644 (file)
index 0000000..18dcfbd
--- /dev/null
@@ -0,0 +1,4 @@
+#Wed May 27 15:28:54 BST 2009\r
+eclipse.preferences.version=1\r
+org.eclipse.debug.ui.DebugView.org.eclipse.cdt.debug.ui.cDebug.show_full_paths=true\r
+org.eclipse.debug.ui.BreakpointView.org.eclipse.cdt.debug.ui.cDebug.show_full_paths=true\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644 (file)
index 0000000..5244cfb
--- /dev/null
@@ -0,0 +1,3 @@
+#Thu May 28 12:28:43 BST 2009\r
+properties/RTOSDemo.null.1399204152/com.crt.advproject.toolchain.exe.debug.2098365516=\#\r\n\#Thu May 28 12\:28\:43 BST 2009\r\ncom.crt.advproject.link.cpp.exe.debug.2062658134\=\\\#\\r\\n\\\#Thu May 28 12\\\:28\\\:43 BST 2009\\r\\nrebuildState\\\=false\\r\\n\r\ncom.crt.advproject.gas.exe.debug.1140174366\=\\\#\\r\\n\\\#Thu May 28 12\\\:28\\\:43 BST 2009\\r\\nrebuildState\\\=false\\r\\n\r\ncom.crt.advproject.gcc.exe.debug.1597927690\=\\\#\\r\\n\\\#Thu May 28 12\\\:28\\\:43 BST 2009\\r\\nrebuildState\\\=false\\r\\n\r\ncom.crt.advproject.toolchain.exe.debug.2098365516\=\\\#\\r\\n\\\#Thu May 28 12\\\:28\\\:43 BST 2009\\r\\nrcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\ncom.crt.advproject.cpp.exe.debug.687684684\=\\\#\\r\\n\\\#Thu May 28 12\\\:28\\\:43 BST 2009\\r\\nrebuildState\\\=false\\r\\n\r\ncom.crt.advproject.link.exe.debug.964550531\=\\\#\\r\\n\\\#Thu May 28 12\\\:28\\\:43 BST 2009\\r\\nrebuildState\\\=false\\r\\n\r\ncom.crt.advproject.toolchain.exe.debug.1041945523\=\\\#\\r\\n\\\#Thu May 28 12\\\:28\\\:43 BST 2009\\r\\nrebuildState\\\=false\\r\\n\r\n\r
+eclipse.preferences.version=1\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs
new file mode 100644 (file)
index 0000000..246e957
--- /dev/null
@@ -0,0 +1,4 @@
+#Wed May 27 16:01:22 BST 2009\r
+useAnnotationsPrefPage=true\r
+eclipse.preferences.version=1\r
+useQuickDiffPrefPage=true\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs
new file mode 100644 (file)
index 0000000..e2a1213
--- /dev/null
@@ -0,0 +1,5 @@
+#Wed May 27 16:37:46 BST 2009\r
+version=1\r
+eclipse.preferences.version=1\r
+pathvariable.FREERTOS_ROOT=C\:/E/Dev/FreeRTOS/WorkingCopy3\r
+description.autobuilding=false\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs
new file mode 100644 (file)
index 0000000..567715c
--- /dev/null
@@ -0,0 +1,6 @@
+#Wed May 27 15:29:53 BST 2009\r
+org.eclipse.debug.ui.switch_perspective_on_suspend=always\r
+eclipse.preferences.version=1\r
+preferredDetailPanes=DefaultDetailPane\:DefaultDetailPane|\r
+org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<launchPerspectives/>\r\n\r
+org.eclipse.debug.ui.user_view_bindings=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<viewBindings>\r\n<view id\="org.eclipse.debug.ui.RegisterView">\r\n<perspective id\="org.eclipse.debug.ui.DebugPerspective" userAction\="closed"/>\r\n</view>\r\n</viewBindings>\r\n\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs
new file mode 100644 (file)
index 0000000..f6ac8b1
--- /dev/null
@@ -0,0 +1,3 @@
+#Wed May 27 16:01:22 BST 2009\r
+eclipse.preferences.version=1\r
+overviewRuler_migration=migrated_3.1\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs
new file mode 100644 (file)
index 0000000..bb9ddf9
--- /dev/null
@@ -0,0 +1,4 @@
+#Thu May 28 12:42:16 BST 2009\r
+eclipse.preferences.version=1\r
+tipsAndTricks=true\r
+platformState=1243510925814\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs
new file mode 100644 (file)
index 0000000..9c7c976
--- /dev/null
@@ -0,0 +1,3 @@
+#Thu May 28 11:49:01 BST 2009\r
+eclipse.preferences.version=1\r
+org.eclipse.ui.commands=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<org.eclipse.ui.commands>\r\n<keyBinding commandId\="org.eclipse.debug.ui.commands.ToggleBreakpoint" contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F9"/>\r\n<keyBinding contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="CTRL+SHIFT+B"/>\r\n<keyBinding contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F11"/>\r\n<keyBinding commandId\="org.eclipse.debug.ui.commands.StepOver" contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F10"/>\r\n<keyBinding contextId\="org.eclipse.debug.ui.debugging" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F6"/>\r\n<keyBinding commandId\="org.eclipse.debug.ui.commands.StepInto" contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F11"/>\r\n<keyBinding contextId\="org.eclipse.debug.ui.debugging" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F5"/>\r\n<keyBinding commandId\="org.eclipse.ui.edit.findNext" contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F3"/>\r\n<keyBinding contextId\="org.eclipse.ui.textEditorScope" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="CTRL+K"/>\r\n<keyBinding commandId\="org.eclipse.ui.project.buildAll" contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F7"/>\r\n<keyBinding contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="CTRL+B"/>\r\n<keyBinding contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="CTRL+Z"/>\r\n<keyBinding commandId\="org.eclipse.ui.edit.undo" contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="ALT+BS"/>\r\n</org.eclipse.ui.commands>\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.debug.core/.launches/RTOSDemo.launch b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.debug.core/.launches/RTOSDemo.launch
new file mode 100644 (file)
index 0000000..63125f6
--- /dev/null
@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<launchConfiguration type="com.crt.ctrlcenter.idleNative2">\r
+<stringAttribute key=".gdbinit" value=""/>\r
+<stringAttribute key="com.crt.ctrlcenter.targetbase" value="NXP LPC17xx (*)"/>\r
+<stringAttribute key="com.crt.ctrlcenter.targetconfig" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#13;&#10;&lt;config chipvendor=&quot;NXP&quot; genname=&quot;NXP LPC17xx (*)&quot; id=&quot;config.gdb.stub&quot;&gt;&lt;parameters&gt;&lt;param default=&quot;true&quot; description=&quot;when True, executable image will be loaded into the target&quot; name=&quot;Load image&quot; type=&quot;boolean&quot; value=&quot;true&quot; var=&quot;load&quot;&gt;&lt;enum value=&quot;true&quot;/&gt;&#13;&#10;&lt;enum value=&quot;false&quot;/&gt;&#13;&#10;&lt;/param&gt;&#13;&#10;&lt;param default=&quot;cont&quot; description=&quot;Run, continue or (nothing)&quot; name=&quot;Run/Continue image&quot; value=&quot;cont&quot; var=&quot;run&quot;&gt;&lt;enum value=&quot;run&quot;/&gt;&#13;&#10;&lt;enum value=&quot;cont&quot;/&gt;&#13;&#10;&lt;enum value=&quot;&quot;/&gt;&#13;&#10;&lt;/param&gt;&#13;&#10;&lt;param default=&quot;off&quot; description=&quot;If on is specified, make the debugger treat unknown memory as non-existent and refuse \naccesses to such memory. If off is specified, treat the memory as RAM&quot; name=&quot;Memory Access Checking&quot; value=&quot;off&quot; var=&quot;mem.access&quot;&gt;&lt;enum value=&quot;on&quot;/&gt;&#13;&#10;&lt;enum value=&quot;off&quot;/&gt;&#13;&#10;&lt;/param&gt;&#13;&#10;&lt;param default=&quot;nochange&quot; description=&quot;choose the disconnect behavior for the target&quot; name=&quot;Disconnect behavior&quot; value=&quot;nochange&quot; var=&quot;ondisconnect&quot;&gt;&lt;enum value=&quot;nochange&quot;/&gt;&#13;&#10;&lt;enum value=&quot;stop&quot;/&gt;&#13;&#10;&lt;enum value=&quot;cont&quot;/&gt;&#13;&#10;&lt;enum value=&quot;run_cont&quot;/&gt;&#13;&#10;&lt;/param&gt;&#13;&#10;&lt;param default=&quot;2&quot; description=&quot;Set stub debug level (1-4)&quot; name=&quot;Debug Level &quot; value=&quot;2&quot; var=&quot;debug.level&quot;/&gt;&#13;&#10;&lt;param default=&quot;true&quot; description=&quot;Enable Red Trace&quot; name=&quot;Enable Red Trace &quot; value=&quot;true&quot; var=&quot;swv.enable&quot;&gt;&lt;enum value=&quot;true&quot;/&gt;&#13;&#10;&lt;enum value=&quot;false&quot;/&gt;&#13;&#10;&lt;/param&gt;&#13;&#10;&lt;param description=&quot;Enter as XTAL[,PLL]. PLL is optional. Values are in kHz&quot; name=&quot;Crystal (XTAL) frequency and PLL value&quot; type=&quot;nullString&quot; value=&quot;4000&quot; var=&quot;xtal.hz&quot;/&gt;&#13;&#10;&lt;param default=&quot;false&quot; description=&quot;Vector catch&quot; name=&quot;Vector catch&quot; value=&quot;false&quot; var=&quot;vector.catch&quot;&gt;&lt;enum value=&quot;True&quot;/&gt;&#13;&#10;&lt;enum value=&quot;False&quot;/&gt;&#13;&#10;&lt;/param&gt;&#13;&#10;&lt;param default=&quot;Auto&quot; description=&quot;Enablement of semihosting support&quot; name=&quot;Semihosting support&quot; value=&quot;Auto&quot; var=&quot;internal.semihost&quot;&gt;&lt;enum value=&quot;On&quot;/&gt;&#13;&#10;&lt;enum value=&quot;Off&quot;/&gt;&#13;&#10;&lt;enum value=&quot;Auto&quot;/&gt;&#13;&#10;&lt;/param&gt;&#13;&#10;&lt;/parameters&gt;&#13;&#10;&lt;script emulators=&quot;${gdb.stub} -mi -info-emu&quot; silent=&quot;false&quot; swv=&quot;true&quot; type=&quot;init&quot;&gt;set remotetimeout 60000&amp;#x0A;target extended-remote | ${gdb.stub} -g -mi -${debug.level:2} ${-c+speed:$null} ${-p+package:$null} ${-e+emulator:$null} ${vector.catch?-vc:}&amp;#x0A;set mem inaccessible-by-default ${mem.access}&amp;#x0A;mon ondisconnect ${ondisconnect}&amp;#x0A;${load}&lt;/script&gt;&#13;&#10;&lt;script silent=&quot;false&quot; type=&quot;run&quot;&gt;${run}&lt;/script&gt;&#13;&#10;&lt;/config&gt;&#10;"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.GDB_INIT" value=""/>\r
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="com.crt.ctrlcenter.cmdfactory"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.crt.ctrlcenter.CRTEmbeddedCDebugger"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>\r
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>\r
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>\r
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="bin/RTOSDemo.axf"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RTOSDemo"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.crt.advproject.toolchain.exe.debug.2098365516"/>\r
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">\r
+<listEntry value="/RTOSDemo"/>\r
+</listAttribute>\r
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">\r
+<listEntry value="4"/>\r
+</listAttribute>\r
+</launchConfiguration>\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml
new file mode 100644 (file)
index 0000000..eac6bd1
--- /dev/null
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<section name="Workbench">\r
+       <section name="org.eclipse.debug.ui.LAUNCH_CONFIGURATIONS_DIALOG_SECTION">\r
+               <item value="821" key="DIALOG_WIDTH"/>\r
+               <item value="89" key="DIALOG_Y_ORIGIN"/>\r
+               <item value=", com.crt.ctrlcenter.idleNative2, " key="org.eclipse.debug.ui.EXPANDED_NODES"/>\r
+               <item value="444" key="DIALOG_X_ORIGIN"/>\r
+               <item value="725" key="DIALOG_HEIGHT"/>\r
+               <item value="237" key="org.eclipse.debug.ui.DIALOG_SASH_WEIGHTS_1"/>\r
+               <item value="762" key="org.eclipse.debug.ui.DIALOG_SASH_WEIGHTS_2"/>\r
+               <item value="1|Tahoma|8.25|0|WINDOWS|1|-11|0|0|0|400|0|0|0|1|0|0|0|0|Tahoma" key="DIALOG_FONT_NAME"/>\r
+       </section>\r
+</section>\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml
new file mode 100644 (file)
index 0000000..6f7cf71
--- /dev/null
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<launchHistory>\r
+<launchGroup id="org.eclipse.ui.externaltools.launchGroup">\r
+<mruHistory/>\r
+<favorites/>\r
+</launchGroup>\r
+<launchGroup id="org.eclipse.debug.ui.launchGroup.profile">\r
+<mruHistory/>\r
+<favorites/>\r
+</launchGroup>\r
+<launchGroup id="org.eclipse.debug.ui.launchGroup.debug">\r
+<mruHistory>\r
+<launch memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;launchConfiguration local=&quot;true&quot; path=&quot;RTOSDemo.launch&quot;/&gt;&#13;&#10;"/>\r
+</mruHistory>\r
+<favorites/>\r
+</launchGroup>\r
+<launchGroup id="org.eclipse.debug.ui.launchGroup.run">\r
+<mruHistory>\r
+<launch memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;launchConfiguration local=&quot;true&quot; path=&quot;RTOSDemo.launch&quot;/&gt;&#13;&#10;"/>\r
+</mruHistory>\r
+<favorites/>\r
+</launchGroup>\r
+</launchHistory>\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml
new file mode 100644 (file)
index 0000000..430e86d
--- /dev/null
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<section name="Workbench">\r
+       <list key="installedFeatures">\r
+               <item value="com.crt.red_suite.feature:2.0.4.200905280812"/>\r
+               <item value="org.eclipse.cdt:4.0.3.200802251018"/>\r
+               <item value="org.eclipse.cvs:1.0.2.r33x_r20080129-7C79_B_GLJwq3I9ZCD8L_"/>\r
+               <item value="org.eclipse.platform:3.3.3.r33x_r20080129-_19UEl7Ezk_gXF1kouft"/>\r
+               <item value="org.eclipse.rcp:3.3.3.r33x_r20080129-8y8eE9UEUWI6qujeED0xT7bc"/>\r
+       </list>\r
+       <section name="ResourceNavigator">\r
+               <item value="RTOSDemo" key="ResourceWorkingSetFilter.STORE_WORKING_SET"/>\r
+               <item value="1" key="ResourceViewer.STORE_SORT_TYPE"/>\r
+       </section>\r
+       <section name="org.eclipse.ui.views.problem">\r
+       </section>\r
+       <section name="CleanDialogSettings">\r
+               <item value="443" key="DIALOG_WIDTH"/>\r
+               <item value="true" key="BUILD_NOW"/>\r
+               <item value="265" key="DIALOG_Y_ORIGIN"/>\r
+               <item value="619" key="DIALOG_X_ORIGIN"/>\r
+               <item value="390" key="DIALOG_HEIGHT"/>\r
+               <item value="false" key="TOGGLE_SELECTED"/>\r
+       </section>\r
+</section>\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml
new file mode 100644 (file)
index 0000000..a640472
--- /dev/null
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<section name="Workbench">\r
+       <section name="org.eclipse.ui.texteditor.FindReplaceDialog_dialogBounds">\r
+               <item value="243" key="DIALOG_WIDTH"/>\r
+               <item value="279" key="DIALOG_Y_ORIGIN"/>\r
+               <item value="355" key="DIALOG_HEIGHT"/>\r
+               <item value="723" key="DIALOG_X_ORIGIN"/>\r
+               <item value="1|Tahoma|8.25|0|WINDOWS|1|-11|0|0|0|400|0|0|0|1|0|0|0|0|Tahoma" key="DIALOG_FONT_NAME"/>\r
+       </section>\r
+       <section name="org.eclipse.ui.texteditor.FindReplaceDialog">\r
+               <item value="false" key="wrap"/>\r
+               <item value="false" key="isRegEx"/>\r
+               <item value="false" key="casesensitive"/>\r
+               <item value="false" key="incremental"/>\r
+               <item value="false" key="wholeword"/>\r
+               <item value="LINKER_SCRIPT" key="selection"/>\r
+               <list key="findhistory">\r
+                       <item value="LINKER_SCRIPT"/>\r
+                       <item value="LINKER_FLAGS"/>\r
+                       <item value="prvIdleTask"/>\r
+                       <item value="reset"/>\r
+               </list>\r
+               <list key="replacehistory">\r
+               </list>\r
+       </section>\r
+</section>\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml
new file mode 100644 (file)
index 0000000..42b28b5
--- /dev/null
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<section name="Workbench">\r
+       <section name="WorkbenchPreferenceDialogSettings">\r
+               <item value="158" key="DIALOG_Y_ORIGIN"/>\r
+               <item value="531" key="DIALOG_X_ORIGIN"/>\r
+       </section>\r
+       <section name="org.eclipse.ui.preferences.keysPreferencePage">\r
+               <item value="true" key="uncategorizedFilter"/>\r
+               <item value="true" key="showAllField"/>\r
+               <item value="true" key="internalFilter"/>\r
+               <item value="true" key="showAllConvert"/>\r
+               <item value="true" key="actionSetFilter"/>\r
+       </section>\r
+</section>\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml b/Demo/CORTEX_LPC1766_GCC_RedSuite/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml
new file mode 100644 (file)
index 0000000..562058c
--- /dev/null
@@ -0,0 +1,501 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<workbench progressCount="20" version="2.0">\r
+<workbenchAdvisor/>\r
+<window height="768" maximized="true" width="1024" x="198" y="198">\r
+<fastViewData fastViewLocation="1024"/>\r
+<perspectiveBar>\r
+<itemSize x="160"/>\r
+</perspectiveBar>\r
+<coolbarLayout locked="0">\r
+<coolItem id="group.file" itemType="typeGroupMarker"/>\r
+<coolItem id="org.eclipse.ui.workbench.file" itemType="typeToolBarContribution" x="130" y="22"/>\r
+<coolItem id="additions" itemType="typeGroupMarker"/>\r
+<coolItem id="org.eclipse.cdt.ui.CElementCreationActionSet" itemType="typeToolBarContribution" x="161" y="22"/>\r
+<coolItem id="org.eclipse.cdt.ui.buildConfigActionSet" itemType="typeToolBarContribution" x="85" y="22"/>\r
+<coolItem id="org.eclipse.debug.ui.launchActionSet" itemType="typeToolBarContribution" x="156" y="22"/>\r
+<coolItem id="org.eclipse.search.searchActionSet" itemType="typeToolBarContribution" x="61" y="22"/>\r
+<coolItem id="org.eclipse.ui.edit.text.actionSet.presentation" itemType="typeToolBarContribution" x="61" y="22"/>\r
+<coolItem id="group.nav" itemType="typeGroupMarker"/>\r
+<coolItem id="org.eclipse.ui.workbench.navigate" itemType="typeToolBarContribution" x="185" y="22"/>\r
+<coolItem id="group.editor" itemType="typeGroupMarker"/>\r
+<coolItem id="org.eclipse.cdt.ui.editor.CEditor" itemType="typeToolBarContribution" x="-1" y="-1"/>\r
+<coolItem id="org.eclipse.ui.DefaultTextEditor" itemType="typePlaceholder" x="-1" y="-1"/>\r
+<coolItem id="org.eclipse.cdt.make.editor" itemType="typePlaceholder" x="-1" y="-1"/>\r
+<coolItem id="group.help" itemType="typeGroupMarker"/>\r
+<coolItem id="org.eclipse.ui.workbench.help" itemType="typeToolBarContribution" x="-1" y="-1"/>\r
+</coolbarLayout>\r
+<page aggregateWorkingSetId="Aggregate for window 1243434303954" focus="true" label="Workspace - C/C++">\r
+<editors>\r
+<editorArea activeWorkbook="DefaultEditorWorkbook">\r
+<info part="DefaultEditorWorkbook">\r
+<folder appearance="1" expanded="2">\r
+<presentation id="org.eclipse.ui.internal.presentations.r33.WorkbenchPresentationFactory_33">\r
+<part id="0"/>\r
+</presentation>\r
+</folder>\r
+</info>\r
+</editorArea>\r
+<editor activePart="true" focus="true" id="org.eclipse.cdt.ui.editor.CEditor" name="main.c" partName="main.c" path="C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/main.c" title="main.c" tooltip="RTOSDemo/main.c" workbook="DefaultEditorWorkbook">\r
+<input factoryID="org.eclipse.ui.part.FileEditorInputFactory" path="/RTOSDemo/main.c"/>\r
+<editorState selectionHPixel="0" selectionLength="0" selectionOffset="0"/>\r
+</editor>\r
+</editors>\r
+<views>\r
+<view id="com.crt.config.browserview.BrowserView" partName="Datasheet browser">\r
+<viewState/>\r
+</view>\r
+<view id="com.crt.quickstart.views.QuickstartView" partName="Quickstart Panel">\r
+<viewState/>\r
+</view>\r
+<view id="org.eclipse.ui.views.PropertySheet" partName="Properties"/>\r
+<view id="org.eclipse.ui.views.ResourceNavigator" partName="Navigator">\r
+<viewState LINK_NAVIGATOR_TO_EDITOR="0" sorter="1">\r
+<filters>\r
+<filter element=".*" isEnabled="false"/>\r
+</filters>\r
+<expanded>\r
+<element path="/RTOSDemo"/>\r
+</expanded>\r
+<selection>\r
+<element path="/RTOSDemo/Makefile"/>\r
+</selection>\r
+</viewState>\r
+</view>\r
+<view id="org.eclipse.debug.ui.DebugView" partName="Debug">\r
+<viewState/>\r
+</view>\r
+<view id="org.eclipse.ui.views.ProblemView" partName="Problems">\r
+<viewState columnWidth0="253" columnWidth1="78" columnWidth2="153" columnWidth3="63" columnWidth4="0" horizontalPosition="0" verticalPosition="0">\r
+<columnOrder columnOrderIndex="0"/>\r
+<columnOrder columnOrderIndex="1"/>\r
+<columnOrder columnOrderIndex="2"/>\r
+<columnOrder columnOrderIndex="3"/>\r
+<columnOrder columnOrderIndex="4"/>\r
+</viewState>\r
+</view>\r
+<view id="org.eclipse.ui.console.ConsoleView" partName="Console">\r
+<viewState/>\r
+</view>\r
+<view id="org.eclipse.debug.ui.BreakpointView" partName="Breakpoints">\r
+<viewState>\r
+<isTrackingSelection value="false"/>\r
+</viewState>\r
+</view>\r
+<view id="org.eclipse.debug.ui.VariableView" partName="Variables">\r
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new file mode 100644 (file)
index 0000000..a62b03c
--- /dev/null
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new file mode 100644 (file)
index 0000000..c51ff74
--- /dev/null
@@ -0,0 +1 @@
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new file mode 100644 (file)
index 0000000..ee4155d
--- /dev/null
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+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">\r
+<buildOutputProvider>\r
+<openAction enabled="true" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+<parser enabled="true"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
+<buildOutputProvider>\r
+<openAction enabled="true" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="makefileGenerator">\r
+<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>\r
+<parser enabled="true"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">\r
+<buildOutputProvider>\r
+<openAction enabled="true" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+<parser enabled="true"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
+<buildOutputProvider>\r
+<openAction enabled="true" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
+<parser enabled="true"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">\r
+<buildOutputProvider>\r
+<openAction enabled="true" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
+<parser enabled="true"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">\r
+<buildOutputProvider>\r
+<openAction enabled="true" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+<parser enabled="true"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
+<buildOutputProvider>\r
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+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
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+</scannerInfoProvider>\r
+</profile>\r
+</scannerConfigBuildInfo>\r
+<scannerConfigBuildInfo instanceId="com.crt.advproject.toolchain.exe.debug.2098365516;com.crt.advproject.toolchain.exe.debug.2098365516.1413142671;com.crt.advproject.gcc.exe.debug.1597927690;com.crt.advproject.compiler.input.1388998656">\r
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+</profile>\r
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+<buildOutputProvider>\r
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+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
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+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">\r
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+<openAction enabled="true" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="makefileGenerator">\r
+<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>\r
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+</profile>\r
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+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+<parser enabled="true"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">\r
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+<openAction enabled="true" filePath=""/>\r
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+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
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+<openAction enabled="true" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
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+</buildOutputProvider>\r
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+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>\r
+<parser enabled="true"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">\r
+<buildOutputProvider>\r
+<openAction enabled="true" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>\r
+<parser enabled="true"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">\r
+<buildOutputProvider>\r
+<openAction enabled="true" filePath=""/>\r
+<parser enabled="true"/>\r
+</buildOutputProvider>\r
+<scannerInfoProvider id="specsFile">\r
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>\r
+<parser enabled="true"/>\r
+</scannerInfoProvider>\r
+</profile>\r
+</scannerConfigBuildInfo>\r
+</storageModule>\r
+</cconfiguration>\r
+</storageModule>\r
+<storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+<project id="RTOSDemo.null.1399204152" name="RTOSDemo"/>\r
+</storageModule>\r
+</cproject>\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/.project b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/.project
new file mode 100644 (file)
index 0000000..f1e030b
--- /dev/null
@@ -0,0 +1,94 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+       <name>RTOSDemo</name>\r
+       <comment></comment>\r
+       <projects>\r
+       </projects>\r
+       <buildSpec>\r
+               <buildCommand>\r
+                       <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
+                       <triggers>clean,full,incremental,</triggers>\r
+                       <arguments>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>\r
+                                       <value>clean</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>?name?</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.append_environment</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildCommand</key>\r
+                                       <value>make</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.contents</key>\r
+                                       <value>org.eclipse.cdt.make.core.activeConfigSettings</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+                                       <value>false</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildArguments</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.fullBuildTarget</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.autoBuildTarget</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                       </arguments>\r
+               </buildCommand>\r
+               <buildCommand>\r
+                       <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+                       <arguments>\r
+                       </arguments>\r
+               </buildCommand>\r
+       </buildSpec>\r
+       <natures>\r
+               <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+               <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+               <nature>org.eclipse.cdt.core.cnature</nature>\r
+       </natures>\r
+       <linkedResources>\r
+               <link>\r
+                       <name>uIP</name>\r
+                       <type>2</type>\r
+                       <locationURI>FREERTOS_ROOT/Demo/Common/ethernet/uIP/uip-1.0/uip</locationURI>\r
+               </link>\r
+               <link>\r
+                       <name>FreeRTOS</name>\r
+                       <type>2</type>\r
+                       <locationURI>FREERTOS_ROOT/Source</locationURI>\r
+               </link>\r
+               <link>\r
+                       <name>CommonDemoTasks</name>\r
+                       <type>2</type>\r
+                       <location>C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/Common/Minimal</location>\r
+               </link>\r
+       </linkedResources>\r
+</projectDescription>\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/FreeRTOSConfig.h b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/FreeRTOSConfig.h
new file mode 100644 (file)
index 0000000..a92a5ba
--- /dev/null
@@ -0,0 +1,136 @@
+/*\r
+       FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify\r
+       it under the terms of the GNU General Public License as published by\r
+       the Free Software Foundation; either version 2 of the License, or\r
+       (at your option) any later version.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful,\r
+       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+       GNU General Public License for more details.\r
+\r
+       You should have received a copy of the GNU General Public License\r
+       along with FreeRTOS.org; if not, write to the Free Software\r
+       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+       A special exception to the GPL can be applied should you wish to distribute\r
+       a combined work that includes FreeRTOS.org, without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section\r
+       of http://www.FreeRTOS.org for full details of how and when the exception\r
+       can be applied.\r
+\r
+    ***************************************************************************\r
+    ***************************************************************************\r
+    *                                                                         *\r
+    * SAVE TIME AND MONEY!  We can port FreeRTOS.org to your own hardware,    *\r
+    * and even write all or part of your application on your behalf.          *\r
+    * See http://www.OpenRTOS.com for details of the services we provide to   *\r
+    * expedite your project.                                                  *\r
+    *                                                                         *\r
+    ***************************************************************************\r
+    ***************************************************************************\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and \r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety \r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting, \r
+       licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION           1\r
+#define configUSE_IDLE_HOOK                    0\r
+#define configUSE_TICK_HOOK                    0\r
+#define configCPU_CLOCK_HZ                     ( ( unsigned portLONG ) 72000000 )\r
+#define configTICK_RATE_HZ                     ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE       ( ( unsigned portSHORT ) 70 )\r
+#define configTOTAL_HEAP_SIZE          ( ( size_t ) ( 19 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN                ( 12 )\r
+#define configUSE_TRACE_FACILITY       1\r
+#define configUSE_16_BIT_TICKS         0\r
+#define configIDLE_SHOULD_YIELD                0\r
+#define configUSE_CO_ROUTINES          0\r
+#define configUSE_MUTEXES                      1\r
+\r
+#define configUSE_COUNTING_SEMAPHORES  0\r
+#define configUSE_ALTERNATIVE_API              0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES            1\r
+#define configQUEUE_REGISTRY_SIZE              10\r
+#define configGENERATE_RUN_TIME_STATS  1\r
+\r
+#define configMAX_PRIORITIES                   ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet                       1\r
+#define INCLUDE_uxTaskPriorityGet                      1\r
+#define INCLUDE_vTaskDelete                                    1\r
+#define INCLUDE_vTaskCleanUpResources          0\r
+#define INCLUDE_vTaskSuspend                           1\r
+#define INCLUDE_vTaskDelayUntil                                1\r
+#define INCLUDE_vTaskDelay                                     1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark    1\r
+\r
+\r
+/* Use the system definition, if there is one */\r
+#ifdef __NVIC_PRIO_BITS\r
+       #define configPRIO_BITS       __NVIC_PRIO_BITS\r
+#else\r
+       #define configPRIO_BITS       5        /* 32 priority levels */\r
+#endif\r
+\r
+/* The lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY        ( 31 << (8 - configPRIO_BITS) )\r
+/* Priority 5, or 160 as only the top three bits are implemented. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY   ( 5 << (8 - configPRIO_BITS) )\r
+\r
+\r
+#define TMR0_BASE_ADDR         0x40004000\r
+#define T0TCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))\r
+#define T0CTCR         (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))\r
+#define T0PR           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))\r
+#define T0TC           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))\r
+#define TCR_COUNT_RESET        ( 0x02 )\r
+#define TCR_COUNT_ENABLE ( 0x01 )\r
+#define CTCR_CTM_TIMER ( 0x00 )\r
+\r
+#define _PCLKSEL0       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8))\r
+\r
+extern void vConfigureTimerForRunTimeStats( void );\r
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats()\r
+#define portGET_RUN_TIME_COUNTER_VALUE() T0TC\r
+\r
+typedef struct\r
+{\r
+       long xColumn;\r
+       char *pcMessage;\r
+} xLCDMessage;\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/LCD/portlcd.c b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/LCD/portlcd.c
new file mode 100644 (file)
index 0000000..cfaf4a8
--- /dev/null
@@ -0,0 +1,394 @@
+/*****************************************************************************\r
+ *\r
+ * Project          : lwIP Web\r
+ * Subproject       : \r
+ * Name             : portlcd.c\r
+ * Function         : Routines for LCD\r
+ * Designer         : K. Sterckx\r
+ * Creation date    : 22/01/2007\r
+ * Compiler         : GNU ARM\r
+ * Processor        : LPC2368\r
+ * Last update      :\r
+ * Last updated by  :\r
+ * History          : \r
+ *  based on example code from NXP\r
+ *\r
+ ************************************************************************\r
+ *\r
+ *  This code is used to place text on the LCD.\r
+ *\r
+ ************************************************************************/\r
+\r
+#include "portlcd.h"\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Hardware library includes. */\r
+#include "LPC17xx_defs.h"\r
+\r
+/* Please note, on old MCB2300 board, the LCD_E bit is p1.30, on the new board\r
+it's p1.31, please check the schematic carefully, and change LCD_CTRL and LCD_E \r
+accordingly if you have a different board. */\r
+\r
+/* LCD IO definitions */\r
+#define LCD_E     0x80000000            /* Enable control pin                */\r
+#define LCD_RW    0x20000000            /* Read/Write control pin            */\r
+#define LCD_RS    0x10000000            /* Data/Instruction control          */\r
+#define LCD_CTRL  0xB0000000            /* Control lines mask                */\r
+#define LCD_DATA  0x0F000000            /* Data lines mask                   */\r
+\r
+/* Local variables */\r
+static unsigned int lcd_ptr;\r
+\r
+/* 8 user defined characters to be loaded into CGRAM (used for bargraph) */\r
+static const unsigned char UserFont[8][8] = {\r
+       { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },\r
+       { 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10 },\r
+       { 0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18 },\r
+       { 0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C },\r
+       { 0x1E,0x1E,0x1E,0x1E,0x1E,0x1E,0x1E,0x1E },\r
+       { 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F },\r
+       { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },\r
+       { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }\r
+};\r
+\r
+/* Local Function Prototypes */\r
+static void     lcd_write( unsigned int c );\r
+static void     lcd_write_4bit( unsigned int c );\r
+static unsigned int lcd_read_stat( void );\r
+static void     lcd_write_cmd( unsigned int c );\r
+static void     lcd_write_data( unsigned int d );\r
+static void     lcd_wait_busy( void );\r
+\r
+\r
+/******************************************************************************\r
+** Function name:  lcd_write_4bit\r
+**\r
+** Descriptions:\r
+**\r
+** parameters:     four bits to write\r
+** Returned value: None\r
+** \r
+******************************************************************************/\r
+static void lcd_write_4bit(unsigned int c)\r
+{\r
+       /* Write a 4-bit command to LCD controller. */\r
+       FIO1DIR |= LCD_DATA | LCD_CTRL;\r
+       FIO1CLR  = LCD_RW   | LCD_DATA;\r
+       FIO1SET  = (c & 0xF) << 24;\r
+       FIO1SET  = LCD_E;\r
+       vTaskDelay(0);\r
+       FIO1CLR  = LCD_E;\r
+       vTaskDelay(0);\r
+       return;\r
+}\r
+\r
+/******************************************************************************\r
+** Function name: lcd_write\r
+**\r
+** Descriptions:\r
+**\r
+** parameters:     word to write\r
+** Returned value: None\r
+** \r
+******************************************************************************/\r
+static void lcd_write(unsigned int c)\r
+{\r
+       /* Write data/command to LCD controller. */\r
+       lcd_write_4bit (c >> 4);\r
+       lcd_write_4bit (c);\r
+       return;\r
+}\r
+\r
+/******************************************************************************\r
+** Function name: lcd_read_stat\r
+**\r
+** Descriptions:\r
+**\r
+** parameters:     None\r
+** Returned value: status\r
+** \r
+******************************************************************************/\r
+static unsigned int lcd_read_stat(void)\r
+{\r
+       /* Read status of LCD controller (ST7066) */\r
+       unsigned int stat;\r
+\r
+       FIO1DIR &= ~LCD_DATA;\r
+       FIO1CLR  = LCD_RS;\r
+       FIO1SET  = LCD_RW;\r
+       vTaskDelay( 0 );\r
+       FIO1SET  = LCD_E;\r
+       vTaskDelay( 0 );\r
+       stat    = (FIO1PIN >> 20) & 0xF0;\r
+       FIO1CLR  = LCD_E;\r
+       vTaskDelay( 0 );\r
+       FIO1SET  = LCD_E;\r
+       vTaskDelay( 0 );\r
+       stat   |= (FIO1PIN >> 24) & 0xF;\r
+       FIO1CLR  = LCD_E;\r
+       return (stat);\r
+}\r
+\r
+/******************************************************************************\r
+** Function name: lcd_wait_busy\r
+**\r
+** Descriptions:\r
+**\r
+** parameters:     None\r
+** Returned value: None\r
+** \r
+******************************************************************************/\r
+static void lcd_wait_busy(void)\r
+{\r
+       /* Wait until LCD controller (ST7066) is busy. */\r
+       unsigned int stat;\r
+\r
+       do\r
+       {\r
+               stat = lcd_read_stat();\r
+       }\r
+       while (stat & 0x80); /* Wait for busy flag */\r
+\r
+       return;\r
+}\r
+\r
+/******************************************************************************\r
+** Function name: lcd_write_cmd\r
+**\r
+** Descriptions:\r
+**\r
+** parameters:     command word\r
+** Returned value: None\r
+** \r
+******************************************************************************/\r
+static void lcd_write_cmd(unsigned int c)\r
+{\r
+       /* Write command to LCD controller. */\r
+       lcd_wait_busy();\r
+       FIO1CLR = LCD_RS;\r
+       lcd_write(c);\r
+       return;\r
+}\r
+\r
+/******************************************************************************\r
+** Function name: lcd_write_data\r
+**\r
+** Descriptions:\r
+**\r
+** parameters:     data word\r
+** Returned value: None\r
+** \r
+******************************************************************************/\r
+static void lcd_write_data(unsigned int d)\r
+{\r
+       /* Write data to LCD controller. */\r
+       lcd_wait_busy();\r
+       FIO1SET = LCD_RS;\r
+       lcd_write(d);\r
+       return;\r
+}\r
+\r
+/******************************************************************************\r
+** Function name: LCD_init\r
+**\r
+** Descriptions:\r
+**\r
+** parameters:     None\r
+** Returned value: None\r
+** \r
+******************************************************************************/\r
+void LCD_init(void)\r
+{\r
+       /* Initialize the ST7066 LCD controller to 4-bit mode. */\r
+       PINSEL3 = 0x00000000;\r
+#if USE_FIO\r
+       SCS |= 0x00000001;/* set GPIOx to use Fast I/O */\r
+#endif\r
+       FIO1DIR |= LCD_CTRL | LCD_DATA;\r
+       FIO1CLR  = LCD_RW   | LCD_RS   | LCD_DATA;\r
+\r
+       lcd_write_4bit(0x3);                /* Select 4-bit interface            */\r
+       vTaskDelay(100);\r
+       lcd_write_4bit(0x3);\r
+       vTaskDelay(100);\r
+       lcd_write_4bit(0x3);\r
+       lcd_write_4bit(0x2);\r
+\r
+       lcd_write_cmd(0x28);                /* 2 lines, 5x8 character matrix     */\r
+       lcd_write_cmd(0x0e);                /* Display ctrl:Disp/Curs/Blnk=ON    */\r
+       lcd_write_cmd(0x06);                /* Entry mode: Move right, no shift  */\r
+\r
+       LCD_load( (unsigned char *)&UserFont, sizeof (UserFont) );\r
+       LCD_cls();\r
+       return;\r
+}\r
+\r
+/******************************************************************************\r
+** Function name: LCD_load\r
+**\r
+** Descriptions:\r
+**\r
+** parameters:     pointer to the buffer and counter\r
+** Returned value: None\r
+** \r
+******************************************************************************/\r
+void LCD_load(unsigned char *fp, unsigned int cnt)\r
+{\r
+       /* Load user-specific characters into CGRAM */\r
+       unsigned int i;\r
+\r
+       lcd_write_cmd( 0x40 );                /* Set CGRAM address counter to 0    */\r
+       for (i = 0; i < cnt; i++, fp++)  \r
+       {\r
+               lcd_write_data( *fp );\r
+       }\r
+       return;\r
+}\r
+\r
+/******************************************************************************\r
+** Function name: LCD_gotoxy\r
+**\r
+** Descriptions:\r
+**\r
+** parameters:     pixel X and Y\r
+** Returned value: None\r
+** \r
+******************************************************************************/\r
+void LCD_gotoxy(unsigned int x, unsigned int y)\r
+{\r
+       /* Set cursor position on LCD display. Left corner: 1,1, right: 16,2 */\r
+       unsigned int c;\r
+\r
+       c = --x;\r
+       if (--y) \r
+       {\r
+               c |= 0x40;\r
+       }\r
+       lcd_write_cmd (c | 0x80);\r
+       lcd_ptr = y*16 + x;\r
+       return;\r
+}\r
+\r
+/******************************************************************************\r
+** Function name: LCD_cls\r
+**\r
+** Descriptions:\r
+**\r
+** parameters:     None\r
+** Returned value: None\r
+** \r
+******************************************************************************/\r
+void LCD_cls(void)\r
+{\r
+       /* Clear LCD display, move cursor to home position. */\r
+       lcd_write_cmd (0x01);\r
+       LCD_gotoxy (1,1);\r
+       return;\r
+}\r
+\r
+/******************************************************************************\r
+** Function name: LCD_cur_off\r
+**\r
+** Descriptions:\r
+**\r
+** parameters:     None\r
+** Returned value: None\r
+** \r
+******************************************************************************/\r
+void LCD_cur_off(void)\r
+{\r
+       /* Switch off LCD cursor. */\r
+       lcd_write_cmd(0x0c);\r
+       return;\r
+}\r
+\r
+\r
+/******************************************************************************\r
+** Function name: LCD_on\r
+**\r
+** Descriptions:\r
+**\r
+** parameters:     None\r
+** Returned value: None\r
+** \r
+******************************************************************************/\r
+void LCD_on(void)\r
+{\r
+       /* Switch on LCD and enable cursor. */\r
+       lcd_write_cmd (0x0e);\r
+       return;\r
+}\r
+\r
+/******************************************************************************\r
+** Function name: LCD_putc\r
+**\r
+** Descriptions:\r
+**\r
+** parameters:     unsigned char character\r
+** Returned value: None\r
+** \r
+******************************************************************************/\r
+void LCD_putc(unsigned char c)\r
+{ \r
+       /* Print a character to LCD at current cursor position. */\r
+       if (lcd_ptr == 16) \r
+       {\r
+               lcd_write_cmd (0xc0);\r
+       }\r
+       lcd_write_data(c);\r
+       lcd_ptr++;\r
+       return;\r
+}\r
+\r
+/******************************************************************************\r
+** Function name: LCD_puts\r
+**\r
+** Descriptions:\r
+**\r
+** parameters:     pointer to the buffer\r
+** Returned value: None\r
+** \r
+******************************************************************************/\r
+void LCD_puts(char *sp)\r
+{\r
+       /* Print a string to LCD display. */\r
+       while (*sp) \r
+       {\r
+               LCD_putc (*sp++);\r
+       }\r
+       return;\r
+}\r
+\r
+/******************************************************************************\r
+** Function name: LCD_bargraph\r
+**\r
+** Descriptions:\r
+**\r
+** parameters:     value and size\r
+** Returned value: None\r
+** \r
+******************************************************************************/\r
+void LCD_bargraph(unsigned int val, unsigned int size)\r
+{\r
+       /* Print a bargraph to LCD display.  */\r
+       /* - val:  value 0..100 %            */\r
+       /* - size: size of bargraph 1..16    */\r
+       unsigned int i;\r
+\r
+       val = val * size / 20;               /* Display matrix 5 x 8 pixels       */\r
+       for (i = 0; i < size; i++) \r
+       {\r
+               if (val > 5) \r
+               {\r
+                       LCD_putc(5);\r
+                       val -= 5;\r
+               }\r
+               else\r
+               {\r
+                       LCD_putc(val);\r
+                       break;\r
+               }\r
+       }\r
+       return;\r
+}\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/LCD/portlcd.h b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/LCD/portlcd.h
new file mode 100644 (file)
index 0000000..7696253
--- /dev/null
@@ -0,0 +1,31 @@
+/*****************************************************************************\r
+ *   rtc.h:  Header file for NXP LPC23xx/24xx Family Microprocessors\r
+ *\r
+ *   Copyright(C) 2006, NXP Semiconductor\r
+ *   All rights reserved.\r
+ *\r
+ *   History\r
+ *   2006.07.13  ver 1.00    Prelimnary version, first Release\r
+ *\r
+******************************************************************************/\r
+#ifndef __PORTLCD_H \r
+#define __PORTLCD_H\r
+\r
+extern void LCD_init(void);\r
+extern void LCD_load(unsigned char *fp, unsigned int cnt);\r
+extern void LCD_gotoxy(unsigned int x, unsigned int y);\r
+extern void LCD_cls(void);\r
+extern void LCD_cur_off(void);\r
+extern void LCD_on(void);\r
+extern void LCD_putc(unsigned char c);\r
+extern void LCD_puts(char *sp);\r
+extern void LCD_bargraph(unsigned int val, unsigned int size);\r
+\r
+extern void LCD_putnibble(unsigned char nibble);\r
+extern void LCD_puthexbyte(unsigned char abyte);\r
+\r
+\r
+#endif /* end __PORTLCD_H */\r
+/*****************************************************************************\r
+**                            End Of File\r
+******************************************************************************/\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/LPC17xx.h b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/LPC17xx.h
new file mode 100644 (file)
index 0000000..e7c8279
--- /dev/null
@@ -0,0 +1,938 @@
+/******************************************************************************\r
+ * @file:    LPC17xx.h\r
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for \r
+ *           NXP LPC17xx Device Series \r
+ * @version: V1.1\r
+ * @date:    14th May 2009\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2008 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3 \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __LPC17xx_H__\r
+#define __LPC17xx_H__\r
+\r
+/*\r
+ * ==========================================================================\r
+ * ---------- Interrupt Number Definition -----------------------------------\r
+ * ==========================================================================\r
+ */\r
+\r
+typedef enum IRQn\r
+{\r
+/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/\r
+  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */\r
+  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */\r
+  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */\r
+  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */\r
+  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */\r
+  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */\r
+  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */\r
+  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */\r
+\r
+/******  LPC17xx Specific Interrupt Numbers *******************************************************/\r
+  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */\r
+  TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */\r
+  TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */\r
+  TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */\r
+  TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */\r
+  UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */\r
+  UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */\r
+  UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */\r
+  UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */\r
+  PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */\r
+  I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */\r
+  I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */\r
+  I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */\r
+  SPI_IRQn                      = 13,       /*!< SPI Interrupt                                    */\r
+  SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */\r
+  SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */\r
+  PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */\r
+  RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */\r
+  EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */\r
+  EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */\r
+  EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */\r
+  EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */\r
+  ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */\r
+  BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */\r
+  USB_IRQn                      = 24,       /*!< USB Interrupt                                    */\r
+  CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */\r
+  DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */\r
+  I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */\r
+  ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */\r
+  RIT_IRQn                      = 29,       /*!< Repetitive Interrupt Timer Interrupt             */\r
+  MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */\r
+  QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */\r
+  PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */\r
+} IRQn_Type;\r
+\r
+\r
+/*\r
+ * ==========================================================================\r
+ * ----------- Processor and Core Peripheral Section ------------------------\r
+ * ==========================================================================\r
+ */\r
+\r
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */\r
+#define __MPU_PRESENT             1         /*!< MPU present or not                               */\r
+#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */\r
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */\r
+\r
+\r
+#include "core_cm3.h"                    /* Cortex-M3 processor and core peripherals           */\r
+#include "system_LPC17xx.h"                 /* System Header                                      */\r
+\r
+\r
+\r
+/**\r
+ * Initialize the system clock\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * @brief  Setup the microcontroller system.\r
+ *         Initialize the System and update the SystemFrequency variable.\r
+ */\r
+extern void SystemInit (void);\r
+\r
+\r
+/******************************************************************************/\r
+/*                Device Specific Peripheral registers structures             */\r
+/******************************************************************************/\r
+\r
+//#pragma anon_unions\r
+\r
+/*------------- System Control (SC) ------------------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t FLASHCFG;               /* Flash Accelerator Module           */\r
+       uint32_t RESERVED0[31];\r
+  __IO uint32_t PLL0CON;                /* Clocking and Power Control         */\r
+  __IO uint32_t PLL0CFG;\r
+  __I  uint32_t PLL0STAT;\r
+  __O  uint32_t PLL0FEED;\r
+       uint32_t RESERVED1[4];\r
+  __IO uint32_t PLL1CON;\r
+  __IO uint32_t PLL1CFG;\r
+  __I  uint32_t PLL1STAT;\r
+  __O  uint32_t PLL1FEED;\r
+       uint32_t RESERVED2[4];\r
+  __IO uint32_t PCON;\r
+  __IO uint32_t PCONP;\r
+       uint32_t RESERVED3[15];\r
+  __IO uint32_t CCLKCFG;\r
+  __IO uint32_t USBCLKCFG;\r
+  __IO uint32_t CLKSRCSEL;\r
+       uint32_t RESERVED4[12];\r
+  __IO uint32_t EXTINT;                 /* External Interrupts                */\r
+       uint32_t RESERVED5;\r
+  __IO uint32_t EXTMODE;\r
+  __IO uint32_t EXTPOLAR;\r
+       uint32_t RESERVED6[12];\r
+  __IO uint32_t RSID;                   /* Reset                              */\r
+       uint32_t RESERVED7[7];\r
+  __IO uint32_t SCS;                    /* Syscon Miscellaneous Registers     */\r
+  __IO uint32_t IRCTRIM;                /* Clock Dividers                     */\r
+  __IO uint32_t PCLKSEL0;\r
+  __IO uint32_t PCLKSEL1;\r
+       uint32_t RESERVED8[4];\r
+  __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */\r
+       uint32_t RESERVED9;\r
+  __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */\r
+ } SC_TypeDef;\r
+\r
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t PINSEL0;\r
+  __IO uint32_t PINSEL1;\r
+  __IO uint32_t PINSEL2;\r
+  __IO uint32_t PINSEL3;\r
+  __IO uint32_t PINSEL4;\r
+  __IO uint32_t PINSEL5;\r
+  __IO uint32_t PINSEL6;\r
+  __IO uint32_t PINSEL7;\r
+  __IO uint32_t PINSEL8;\r
+  __IO uint32_t PINSEL9;\r
+  __IO uint32_t PINSEL10;\r
+       uint32_t RESERVED0[5];\r
+  __IO uint32_t PINMODE0;\r
+  __IO uint32_t PINMODE1;\r
+  __IO uint32_t PINMODE2;\r
+  __IO uint32_t PINMODE3;\r
+  __IO uint32_t PINMODE4;\r
+  __IO uint32_t PINMODE5;\r
+  __IO uint32_t PINMODE6;\r
+  __IO uint32_t PINMODE7;\r
+  __IO uint32_t PINMODE8;\r
+  __IO uint32_t PINMODE9;\r
+  __IO uint32_t PINMODE_OD0;\r
+  __IO uint32_t PINMODE_OD1;\r
+  __IO uint32_t PINMODE_OD2;\r
+  __IO uint32_t PINMODE_OD3;\r
+  __IO uint32_t PINMODE_OD4;\r
+} PINCON_TypeDef;\r
+\r
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t FIODIR;\r
+       uint32_t RESERVED0[3];\r
+  __IO uint32_t FIOMASK;\r
+  __IO uint32_t FIOPIN;\r
+  __IO uint32_t FIOSET;\r
+  __O  uint32_t FIOCLR;\r
+} GPIO_TypeDef;\r
+\r
+typedef struct\r
+{\r
+  __I  uint32_t IntStatus;\r
+  __I  uint32_t IO0IntStatR;\r
+  __I  uint32_t IO0IntStatF;\r
+  __O  uint32_t IO0IntClr;\r
+  __IO uint32_t IO0IntEnR;\r
+  __IO uint32_t IO0IntEnF;\r
+       uint32_t RESERVED0[3];\r
+  __I  uint32_t IO2IntStatR;\r
+  __I  uint32_t IO2IntStatF;\r
+  __O  uint32_t IO2IntClr;\r
+  __IO uint32_t IO2IntEnR;\r
+  __IO uint32_t IO2IntEnF;\r
+} GPIOINT_TypeDef;\r
+\r
+/*------------- Timer (TIM) --------------------------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t IR;\r
+  __IO uint32_t TCR;\r
+  __IO uint32_t TC;\r
+  __IO uint32_t PR;\r
+  __IO uint32_t PC;\r
+  __IO uint32_t MCR;\r
+  __IO uint32_t MR0;\r
+  __IO uint32_t MR1;\r
+  __IO uint32_t MR2;\r
+  __IO uint32_t MR3;\r
+  __IO uint32_t CCR;\r
+  __I  uint32_t CR0;\r
+  __I  uint32_t CR1;\r
+       uint32_t RESERVED0[2];\r
+  __IO uint32_t EMR;\r
+       uint32_t RESERVED1[24];\r
+  __IO uint32_t CTCR;\r
+} TIM_TypeDef;\r
+\r
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t IR;\r
+  __IO uint32_t TCR;\r
+  __IO uint32_t TC;\r
+  __IO uint32_t PR;\r
+  __IO uint32_t PC;\r
+  __IO uint32_t MCR;\r
+  __IO uint32_t MR0;\r
+  __IO uint32_t MR1;\r
+  __IO uint32_t MR2;\r
+  __IO uint32_t MR3;\r
+  __IO uint32_t CCR;\r
+  __I  uint32_t CR0;\r
+  __I  uint32_t CR1;\r
+  __I  uint32_t CR2;\r
+  __I  uint32_t CR3;\r
+  __IO uint32_t MR4;\r
+  __IO uint32_t MR5;\r
+  __IO uint32_t MR6;\r
+  __IO uint32_t PCR;\r
+  __IO uint32_t LER;\r
+       uint32_t RESERVED0[7];\r
+  __IO uint32_t CTCR;\r
+} PWM_TypeDef;\r
+\r
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/\r
+typedef struct\r
+{\r
+  union {\r
+  __I  uint8_t  RBR;\r
+  __O  uint8_t  THR;\r
+  __IO uint8_t  DLL;\r
+       uint32_t RESERVED0;\r
+  };\r
+  union {\r
+  __IO uint8_t  DLM;\r
+  __IO uint32_t IER;\r
+  };\r
+  union {\r
+  __I  uint32_t IIR;\r
+  __O  uint8_t  FCR;\r
+  };\r
+  __IO uint8_t  LCR;\r
+       uint8_t  RESERVED1[7];\r
+  __IO uint8_t  LSR;\r
+       uint8_t  RESERVED2[7];\r
+  __IO uint8_t  SCR;\r
+       uint8_t  RESERVED3[3];\r
+  __IO uint32_t ACR;\r
+  __IO uint8_t  ICR;\r
+       uint8_t  RESERVED4[3];\r
+  __IO uint8_t  FDR;\r
+       uint8_t  RESERVED5[7];\r
+  __IO uint8_t  TER;\r
+       uint8_t  RESERVED6[27];\r
+  __IO uint8_t  RS485CTRL;\r
+       uint8_t  RESERVED7[3];\r
+  __IO uint8_t  ADRMATCH;\r
+} UART_TypeDef;\r
+\r
+typedef struct\r
+{\r
+  union {\r
+  __I  uint8_t  RBR;\r
+  __O  uint8_t  THR;\r
+  __IO uint8_t  DLL;\r
+       uint32_t RESERVED0;\r
+  };\r
+  union {\r
+  __IO uint8_t  DLM;\r
+  __IO uint32_t IER;\r
+  };\r
+  union {\r
+  __I  uint32_t IIR;\r
+  __O  uint8_t  FCR;\r
+  };\r
+  __IO uint8_t  LCR;\r
+       uint8_t  RESERVED1[3];\r
+  __IO uint8_t  MCR;\r
+       uint8_t  RESERVED2[3];\r
+  __IO uint8_t  LSR;\r
+       uint8_t  RESERVED3[3];\r
+  __IO uint8_t  MSR;\r
+       uint8_t  RESERVED4[3];\r
+  __IO uint8_t  SCR;\r
+       uint8_t  RESERVED5[3];\r
+  __IO uint32_t ACR;\r
+       uint32_t RESERVED6;\r
+  __IO uint32_t FDR;\r
+       uint32_t RESERVED7;\r
+  __IO uint8_t  TER;\r
+       uint8_t  RESERVED8[27];\r
+  __IO uint8_t  RS485CTRL;\r
+       uint8_t  RESERVED9[3];\r
+  __IO uint8_t  ADRMATCH;\r
+       uint8_t  RESERVED10[3];\r
+  __IO uint8_t  RS485DLY;\r
+} UART1_TypeDef;\r
+\r
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t SPCR;\r
+  __I  uint32_t SPSR;\r
+  __IO uint32_t SPDR;\r
+  __IO uint32_t SPCCR;\r
+       uint32_t RESERVED0[3];\r
+  __IO uint32_t SPINT;\r
+} SPI_TypeDef;\r
+\r
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t CR0;\r
+  __IO uint32_t CR1;\r
+  __IO uint32_t DR;\r
+  __I  uint32_t SR;\r
+  __IO uint32_t CPSR;\r
+  __IO uint32_t IMSC;\r
+  __IO uint32_t RIS;\r
+  __IO uint32_t MIS;\r
+  __IO uint32_t ICR;\r
+  __IO uint32_t DMACR;\r
+} SSP_TypeDef;\r
+\r
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t I2CONSET;\r
+  __I  uint32_t I2STAT;\r
+  __IO uint32_t I2DAT;\r
+  __IO uint32_t I2ADR0;\r
+  __IO uint32_t I2SCLH;\r
+  __IO uint32_t I2SCLL;\r
+  __O  uint32_t I2CONCLR;\r
+  __IO uint32_t MMCTRL;\r
+  __IO uint32_t I2ADR1;\r
+  __IO uint32_t I2ADR2;\r
+  __IO uint32_t I2ADR3;\r
+  __I  uint32_t I2DATA_BUFFER;\r
+  __IO uint32_t I2MASK0;\r
+  __IO uint32_t I2MASK1;\r
+  __IO uint32_t I2MASK2;\r
+  __IO uint32_t I2MASK3;\r
+} I2C_TypeDef;\r
+\r
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t I2SDAO;\r
+  __I  uint32_t I2SDAI;\r
+  __O  uint32_t I2STXFIFO;\r
+  __I  uint32_t I2SRXFIFO;\r
+  __I  uint32_t I2SSTATE;\r
+  __IO uint32_t I2SDMA1;\r
+  __IO uint32_t I2SDMA2;\r
+  __IO uint32_t I2SIRQ;\r
+  __IO uint32_t I2STXRATE;\r
+  __IO uint32_t I2SRXRATE;\r
+  __IO uint32_t I2STXBITRATE;\r
+  __IO uint32_t I2SRXBITRATE;\r
+  __IO uint32_t I2STXMODE;\r
+  __IO uint32_t I2SRXMODE;\r
+} I2S_TypeDef;\r
+\r
+/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t RICOMPVAL;\r
+  __IO uint32_t RIMASK;\r
+  __IO uint8_t  RICTRL;\r
+       uint8_t  RESERVED0[3];\r
+  __IO uint32_t RICOUNTER;\r
+} RIT_TypeDef;\r
+\r
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint8_t  ILR;\r
+       uint8_t  RESERVED0[3];\r
+  __IO uint8_t  CCR;\r
+       uint8_t  RESERVED1[3];\r
+  __IO uint8_t  CIIR;\r
+       uint8_t  RESERVED2[3];\r
+  __IO uint8_t  AMR;\r
+       uint8_t  RESERVED3[3];\r
+  __I  uint32_t CTIME0;\r
+  __I  uint32_t CTIME1;\r
+  __I  uint32_t CTIME2;\r
+  __IO uint8_t  SEC;\r
+       uint8_t  RESERVED4[3];\r
+  __IO uint8_t  MIN;\r
+       uint8_t  RESERVED5[3];\r
+  __IO uint8_t  HOUR;\r
+       uint8_t  RESERVED6[3];\r
+  __IO uint8_t  DOM;\r
+       uint8_t  RESERVED7[3];\r
+  __IO uint8_t  DOW;\r
+       uint8_t  RESERVED8[3];\r
+  __IO uint16_t DOY;\r
+       uint16_t RESERVED9;\r
+  __IO uint8_t  MONTH;\r
+       uint8_t  RESERVED10[3];\r
+  __IO uint16_t YEAR;\r
+       uint16_t RESERVED11;\r
+  __IO uint32_t CALIBRATION;\r
+  __IO uint32_t GPREG0;\r
+  __IO uint32_t GPREG1;\r
+  __IO uint32_t GPREG2;\r
+  __IO uint32_t GPREG3;\r
+  __IO uint32_t GPREG4;\r
+  __IO uint8_t  WAKEUPDIS;\r
+       uint8_t  RESERVED12[3];\r
+  __IO uint8_t  PWRCTRL;\r
+       uint8_t  RESERVED13[3];\r
+  __IO uint8_t  ALSEC;\r
+       uint8_t  RESERVED14[3];\r
+  __IO uint8_t  ALMIN;\r
+       uint8_t  RESERVED15[3];\r
+  __IO uint8_t  ALHOUR;\r
+       uint8_t  RESERVED16[3];\r
+  __IO uint8_t  ALDOM;\r
+       uint8_t  RESERVED17[3];\r
+  __IO uint8_t  ALDOW;\r
+       uint8_t  RESERVED18[3];\r
+  __IO uint16_t ALDOY;\r
+       uint16_t RESERVED19;\r
+  __IO uint8_t  ALMON;\r
+       uint8_t  RESERVED20[3];\r
+  __IO uint16_t ALYEAR;\r
+       uint16_t RESERVED21;\r
+} RTC_TypeDef;\r
+\r
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint8_t  WDMOD;\r
+       uint8_t  RESERVED0[3];\r
+  __IO uint32_t WDTC;\r
+  __O  uint8_t  WDFEED;\r
+       uint8_t  RESERVED1[3];\r
+  __I  uint32_t WDTV;\r
+  __IO uint32_t WDCLKSEL;\r
+} WDT_TypeDef;\r
+\r
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t ADCR;\r
+  __IO uint32_t ADGDR;\r
+       uint32_t RESERVED0;\r
+  __IO uint32_t ADINTEN;\r
+  __I  uint32_t ADDR0;\r
+  __I  uint32_t ADDR1;\r
+  __I  uint32_t ADDR2;\r
+  __I  uint32_t ADDR3;\r
+  __I  uint32_t ADDR4;\r
+  __I  uint32_t ADDR5;\r
+  __I  uint32_t ADDR6;\r
+  __I  uint32_t ADDR7;\r
+  __I  uint32_t ADSTAT;\r
+  __IO uint32_t ADTRM;\r
+} ADC_TypeDef;\r
+\r
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t DACR;\r
+  __IO uint32_t DACCTRL;\r
+  __IO uint16_t DACCNTVAL;\r
+} DAC_TypeDef;\r
+\r
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/\r
+typedef struct\r
+{\r
+  __I  uint32_t MCCON;\r
+  __O  uint32_t MCCON_SET;\r
+  __O  uint32_t MCCON_CLR;\r
+  __I  uint32_t MCCAPCON;\r
+  __O  uint32_t MCCAPCON_SET;\r
+  __O  uint32_t MCCAPCON_CLR;\r
+  __IO uint32_t MCTIM0;\r
+  __IO uint32_t MCTIM1;\r
+  __IO uint32_t MCTIM2;\r
+  __IO uint32_t MCPER0;\r
+  __IO uint32_t MCPER1;\r
+  __IO uint32_t MCPER2;\r
+  __IO uint32_t MCPW0;\r
+  __IO uint32_t MCPW1;\r
+  __IO uint32_t MCPW2;\r
+  __IO uint32_t MCDEADTIME;\r
+  __IO uint32_t MCCCP;\r
+  __IO uint32_t MCCR0;\r
+  __IO uint32_t MCCR1;\r
+  __IO uint32_t MCCR2;\r
+  __I  uint32_t MCINTEN;\r
+  __O  uint32_t MCINTEN_SET;\r
+  __O  uint32_t MCINTEN_CLR;\r
+  __I  uint32_t MCCNTCON;\r
+  __O  uint32_t MCCNTCON_SET;\r
+  __O  uint32_t MCCNTCON_CLR;\r
+  __I  uint32_t MCINTFLAG;\r
+  __O  uint32_t MCINTFLAG_SET;\r
+  __O  uint32_t MCINTFLAG_CLR;\r
+  __O  uint32_t MCCAP_CLR;\r
+} MCPWM_TypeDef;\r
+\r
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/\r
+typedef struct\r
+{\r
+  __O  uint32_t QEICON;\r
+  __I  uint32_t QEISTAT;\r
+  __IO uint32_t QEICONF;\r
+  __I  uint32_t QEIPOS;\r
+  __IO uint32_t QEIMAXPOS;\r
+  __IO uint32_t CMPOS0;\r
+  __IO uint32_t CMPOS1;\r
+  __IO uint32_t CMPOS2;\r
+  __I  uint32_t INXCNT;\r
+  __IO uint32_t INXCMP;\r
+  __IO uint32_t QEILOAD;\r
+  __I  uint32_t QEITIME;\r
+  __I  uint32_t QEIVEL;\r
+  __I  uint32_t QEICAP;\r
+  __IO uint32_t VELCOMP;\r
+  __IO uint32_t FILTER;\r
+       uint32_t RESERVED0[998];\r
+  __O  uint32_t QEIIEC;\r
+  __O  uint32_t QEIIES;\r
+  __I  uint32_t QEIINTSTAT;\r
+  __I  uint32_t QEIIE;\r
+  __O  uint32_t QEICLR;\r
+  __O  uint32_t QEISET;\r
+} QEI_TypeDef;\r
+\r
+/*------------- Controller Area Network (CAN) --------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t mask[512];              /* ID Masks                           */\r
+} CANAF_RAM_TypeDef;\r
+\r
+typedef struct                          /* Acceptance Filter Registers        */\r
+{\r
+  __IO uint32_t AFMR;\r
+  __IO uint32_t SFF_sa;\r
+  __IO uint32_t SFF_GRP_sa;\r
+  __IO uint32_t EFF_sa;\r
+  __IO uint32_t EFF_GRP_sa;\r
+  __IO uint32_t ENDofTable;\r
+  __I  uint32_t LUTerrAd;\r
+  __I  uint32_t LUTerr;\r
+} CANAF_TypeDef;\r
+\r
+typedef struct                          /* Central Registers                  */\r
+{\r
+  __I  uint32_t CANTxSR;\r
+  __I  uint32_t CANRxSR;\r
+  __I  uint32_t CANMSR;\r
+} CANCR_TypeDef;\r
+\r
+typedef struct                          /* Controller Registers               */\r
+{\r
+  __IO uint32_t MOD;\r
+  __O  uint32_t CMR;\r
+  __IO uint32_t GSR;\r
+  __I  uint32_t ICR;\r
+  __IO uint32_t IER;\r
+  __IO uint32_t BTR;\r
+  __IO uint32_t EWL;\r
+  __I  uint32_t SR;\r
+  __IO uint32_t RFS;\r
+  __IO uint32_t RID;\r
+  __IO uint32_t RDA;\r
+  __IO uint32_t RDB;\r
+  __IO uint32_t TFI1;\r
+  __IO uint32_t TID1;\r
+  __IO uint32_t TDA1;\r
+  __IO uint32_t TDB1;\r
+  __IO uint32_t TFI2;\r
+  __IO uint32_t TID2;\r
+  __IO uint32_t TDA2;\r
+  __IO uint32_t TDB2;\r
+  __IO uint32_t TFI3;\r
+  __IO uint32_t TID3;\r
+  __IO uint32_t TDA3;\r
+  __IO uint32_t TDB3;\r
+} CAN_TypeDef;\r
+\r
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/\r
+typedef struct                          /* Common Registers                   */\r
+{\r
+  __I  uint32_t DMACIntStat;\r
+  __I  uint32_t DMACIntTCStat;\r
+  __O  uint32_t DMACIntTCClear;\r
+  __I  uint32_t DMACIntErrStat;\r
+  __O  uint32_t DMACIntErrClr;\r
+  __I  uint32_t DMACRawIntTCStat;\r
+  __I  uint32_t DMACRawIntErrStat;\r
+  __I  uint32_t DMACEnbldChns;\r
+  __IO uint32_t DMACSoftBReq;\r
+  __IO uint32_t DMACSoftSReq;\r
+  __IO uint32_t DMACSoftLBReq;\r
+  __IO uint32_t DMACSoftLSReq;\r
+  __IO uint32_t DMACConfig;\r
+  __IO uint32_t DMACSync;\r
+} GPDMA_TypeDef;\r
+\r
+typedef struct                          /* Channel Registers                  */\r
+{\r
+  __IO uint32_t DMACCSrcAddr;\r
+  __IO uint32_t DMACCDestAddr;\r
+  __IO uint32_t DMACCLLI;\r
+  __IO uint32_t DMACCControl;\r
+  __IO uint32_t DMACCConfig;\r
+} GPDMACH_TypeDef;\r
+\r
+/*------------- Universal Serial Bus (USB) -----------------------------------*/\r
+typedef struct\r
+{\r
+  __I  uint32_t HcRevision;             /* USB Host Registers                 */\r
+  __IO uint32_t HcControl;\r
+  __IO uint32_t HcCommandStatus;\r
+  __IO uint32_t HcInterruptStatus;\r
+  __IO uint32_t HcInterruptEnable;\r
+  __IO uint32_t HcInterruptDisable;\r
+  __IO uint32_t HcHCCA;\r
+  __I  uint32_t HcPeriodCurrentED;\r
+  __IO uint32_t HcControlHeadED;\r
+  __IO uint32_t HcControlCurrentED;\r
+  __IO uint32_t HcBulkHeadED;\r
+  __IO uint32_t HcBulkCurrentED;\r
+  __I  uint32_t HcDoneHead;\r
+  __IO uint32_t HcFmInterval;\r
+  __I  uint32_t HcFmRemaining;\r
+  __I  uint32_t HcFmNumber;\r
+  __IO uint32_t HcPeriodicStart;\r
+  __IO uint32_t HcLSTreshold;\r
+  __IO uint32_t HcRhDescriptorA;\r
+  __IO uint32_t HcRhDescriptorB;\r
+  __IO uint32_t HcRhStatus;\r
+  __IO uint32_t HcRhPortStatus1;\r
+  __IO uint32_t HcRhPortStatus2;\r
+       uint32_t RESERVED0[40];\r
+  __I  uint32_t Module_ID;\r
+\r
+  __I  uint32_t OTGIntSt;               /* USB On-The-Go Registers            */\r
+  __IO uint32_t OTGIntEn;\r
+  __O  uint32_t OTGIntSet;\r
+  __O  uint32_t OTGIntClr;\r
+  __IO uint32_t OTGStCtrl;\r
+  __IO uint32_t OTGTmr;\r
+       uint32_t RESERVED1[58];\r
+\r
+  __I  uint32_t USBDevIntSt;            /* USB Device Interrupt Registers     */\r
+  __IO uint32_t USBDevIntEn;\r
+  __O  uint32_t USBDevIntClr;\r
+  __O  uint32_t USBDevIntSet;\r
+\r
+  __O  uint32_t USBCmdCode;             /* USB Device SIE Command Registers   */\r
+  __I  uint32_t USBCmdData;\r
+\r
+  __I  uint32_t USBRxData;              /* USB Device Transfer Registers      */\r
+  __O  uint32_t USBTxData;\r
+  __I  uint32_t USBRxPLen;\r
+  __O  uint32_t USBTxPLen;\r
+  __IO uint32_t USBCtrl;\r
+  __O  uint32_t USBDevIntPri;\r
+\r
+  __I  uint32_t USBEpIntSt;             /* USB Device Endpoint Interrupt Regs */\r
+  __IO uint32_t USBEpIntEn;\r
+  __O  uint32_t USBEpIntClr;\r
+  __O  uint32_t USBEpIntSet;\r
+  __O  uint32_t USBEpIntPri;\r
+\r
+  __IO uint32_t USBReEp;                /* USB Device Endpoint Realization Reg*/\r
+  __O  uint32_t USBEpInd;\r
+  __IO uint32_t USBMaxPSize;\r
+\r
+  __I  uint32_t USBDMARSt;              /* USB Device DMA Registers           */\r
+  __O  uint32_t USBDMARClr;\r
+  __O  uint32_t USBDMARSet;\r
+       uint32_t RESERVED2[9];\r
+  __IO uint32_t USBUDCAH;\r
+  __I  uint32_t USBEpDMASt;\r
+  __O  uint32_t USBEpDMAEn;\r
+  __O  uint32_t USBEpDMADis;\r
+  __I  uint32_t USBDMAIntSt;\r
+  __IO uint32_t USBDMAIntEn;\r
+       uint32_t RESERVED3[2];\r
+  __I  uint32_t USBEoTIntSt;\r
+  __O  uint32_t USBEoTIntClr;\r
+  __O  uint32_t USBEoTIntSet;\r
+  __I  uint32_t USBNDDRIntSt;\r
+  __O  uint32_t USBNDDRIntClr;\r
+  __O  uint32_t USBNDDRIntSet;\r
+  __I  uint32_t USBSysErrIntSt;\r
+  __O  uint32_t USBSysErrIntClr;\r
+  __O  uint32_t USBSysErrIntSet;\r
+       uint32_t RESERVED4[15];\r
+\r
+  __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */\r
+  __O  uint32_t I2C_WO;\r
+  __I  uint32_t I2C_STS;\r
+  __IO uint32_t I2C_CTL;\r
+  __IO uint32_t I2C_CLKHI;\r
+  __O  uint32_t I2C_CLKLO;\r
+       uint32_t RESERVED5[823];\r
+\r
+  union {\r
+  __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */\r
+  __IO uint32_t OTGClkCtrl;\r
+  };\r
+  union {\r
+  __I  uint32_t USBClkSt;\r
+  __I  uint32_t OTGClkSt;\r
+  };\r
+} USB_TypeDef;\r
+\r
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t MAC1;                   /* MAC Registers                      */\r
+  __IO uint32_t MAC2;\r
+  __IO uint32_t IPGT;\r
+  __IO uint32_t IPGR;\r
+  __IO uint32_t CLRT;\r
+  __IO uint32_t MAXF;\r
+  __IO uint32_t SUPP;\r
+  __IO uint32_t TEST;\r
+  __IO uint32_t MCFG;\r
+  __IO uint32_t MCMD;\r
+  __IO uint32_t MADR;\r
+  __O  uint32_t MWTD;\r
+  __I  uint32_t MRDD;\r
+  __I  uint32_t MIND;\r
+       uint32_t RESERVED0[2];\r
+  __IO uint32_t SA0;\r
+  __IO uint32_t SA1;\r
+  __IO uint32_t SA2;\r
+       uint32_t RESERVED1[45];\r
+  __IO uint32_t Command;                /* Control Registers                  */\r
+  __I  uint32_t Status;\r
+  __IO uint32_t RxDescriptor;\r
+  __IO uint32_t RxStatus;\r
+  __IO uint32_t RxDescriptorNumber;\r
+  __I  uint32_t RxProduceIndex;\r
+  __IO uint32_t RxConsumeIndex;\r
+  __IO uint32_t TxDescriptor;\r
+  __IO uint32_t TxStatus;\r
+  __IO uint32_t TxDescriptorNumber;\r
+  __IO uint32_t TxProduceIndex;\r
+  __I  uint32_t TxConsumeIndex;\r
+       uint32_t RESERVED2[10];\r
+  __I  uint32_t TSV0;\r
+  __I  uint32_t TSV1;\r
+  __I  uint32_t RSV;\r
+       uint32_t RESERVED3[3];\r
+  __IO uint32_t FlowControlCounter;\r
+  __I  uint32_t FlowControlStatus;\r
+       uint32_t RESERVED4[34];\r
+  __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */\r
+  __IO uint32_t RxFilterWoLStatus;\r
+  __IO uint32_t RxFilterWoLClear;\r
+       uint32_t RESERVED5;\r
+  __IO uint32_t HashFilterL;\r
+  __IO uint32_t HashFilterH;\r
+       uint32_t RESERVED6[882];\r
+  __I  uint32_t IntStatus;              /* Module Control Registers           */\r
+  __IO uint32_t IntEnable;\r
+  __O  uint32_t IntClear;\r
+  __O  uint32_t IntSet;\r
+       uint32_t RESERVED7;\r
+  __IO uint32_t PowerDown;\r
+       uint32_t RESERVED8;\r
+  __IO uint32_t Module_ID;\r
+} EMAC_TypeDef;\r
+\r
+//#pragma no_anon_unions\r
+\r
+\r
+/******************************************************************************/\r
+/*                         Peripheral memory map                              */\r
+/******************************************************************************/\r
+/* Base addresses                                                             */\r
+#define FLASH_BASE            (0x00000000UL)\r
+#define RAM_BASE              (0x10000000UL)\r
+#define GPIO_BASE             (0x2009C000UL)\r
+#define APB0_BASE             (0x40000000UL)\r
+#define APB1_BASE             (0x40080000UL)\r
+#define AHB_BASE              (0x50000000UL)\r
+#define CM3_BASE              (0xE0000000UL)\r
+\r
+/* APB0 peripherals                                                           */\r
+#define WDT_BASE              (APB0_BASE + 0x00000)\r
+#define TIM0_BASE             (APB0_BASE + 0x04000)\r
+#define TIM1_BASE             (APB0_BASE + 0x08000)\r
+#define UART0_BASE            (APB0_BASE + 0x0C000)\r
+#define UART1_BASE            (APB0_BASE + 0x10000)\r
+#define PWM1_BASE             (APB0_BASE + 0x18000)\r
+#define I2C0_BASE             (APB0_BASE + 0x1C000)\r
+#define SPI_BASE              (APB0_BASE + 0x20000)\r
+#define RTC_BASE              (APB0_BASE + 0x24000)\r
+#define GPIOINT_BASE          (APB0_BASE + 0x28080)\r
+#define PINCON_BASE           (APB0_BASE + 0x2C000)\r
+#define SSP1_BASE             (APB0_BASE + 0x30000)\r
+#define ADC_BASE              (APB0_BASE + 0x34000)\r
+#define CANAF_RAM_BASE        (APB0_BASE + 0x38000)\r
+#define CANAF_BASE            (APB0_BASE + 0x3C000)\r
+#define CANCR_BASE            (APB0_BASE + 0x40000)\r
+#define CAN1_BASE             (APB0_BASE + 0x44000)\r
+#define CAN2_BASE             (APB0_BASE + 0x48000)\r
+#define I2C1_BASE             (APB0_BASE + 0x5C000)\r
+\r
+/* APB1 peripherals                                                           */\r
+#define SSP0_BASE             (APB1_BASE + 0x08000)\r
+#define DAC_BASE              (APB1_BASE + 0x0C000)\r
+#define TIM2_BASE             (APB1_BASE + 0x10000)\r
+#define TIM3_BASE             (APB1_BASE + 0x14000)\r
+#define UART2_BASE            (APB1_BASE + 0x18000)\r
+#define UART3_BASE            (APB1_BASE + 0x1C000)\r
+#define I2C2_BASE             (APB1_BASE + 0x20000)\r
+#define I2S_BASE              (APB1_BASE + 0x28000)\r
+#define RIT_BASE              (APB1_BASE + 0x30000)\r
+#define MCPWM_BASE            (APB1_BASE + 0x38000)\r
+#define QEI_BASE              (APB1_BASE + 0x3C000)\r
+#define SC_BASE               (APB1_BASE + 0x7C000)\r
+\r
+/* AHB peripherals                                                            */\r
+#define EMAC_BASE             (AHB_BASE  + 0x00000)\r
+#define GPDMA_BASE            (AHB_BASE  + 0x04000)\r
+#define GPDMACH0_BASE         (AHB_BASE  + 0x04100)\r
+#define GPDMACH1_BASE         (AHB_BASE  + 0x04120)\r
+#define GPDMACH2_BASE         (AHB_BASE  + 0x04140)\r
+#define GPDMACH3_BASE         (AHB_BASE  + 0x04160)\r
+#define GPDMACH4_BASE         (AHB_BASE  + 0x04180)\r
+#define GPDMACH5_BASE         (AHB_BASE  + 0x041A0)\r
+#define GPDMACH6_BASE         (AHB_BASE  + 0x041C0)\r
+#define GPDMACH7_BASE         (AHB_BASE  + 0x041E0)\r
+#define USB_BASE              (AHB_BASE  + 0x0C000)\r
+\r
+/* GPIOs                                                                      */\r
+#define GPIO0_BASE            (GPIO_BASE + 0x00000)\r
+#define GPIO1_BASE            (GPIO_BASE + 0x00020)\r
+#define GPIO2_BASE            (GPIO_BASE + 0x00040)\r
+#define GPIO3_BASE            (GPIO_BASE + 0x00060)\r
+#define GPIO4_BASE            (GPIO_BASE + 0x00080)\r
+\r
+\r
+/******************************************************************************/\r
+/*                         Peripheral declaration                             */\r
+/******************************************************************************/\r
+#define SC                    ((       SC_TypeDef *)        SC_BASE)\r
+#define GPIO0                 ((     GPIO_TypeDef *)     GPIO0_BASE)\r
+#define GPIO1                 ((     GPIO_TypeDef *)     GPIO1_BASE)\r
+#define GPIO2                 ((     GPIO_TypeDef *)     GPIO2_BASE)\r
+#define GPIO3                 ((     GPIO_TypeDef *)     GPIO3_BASE)\r
+#define GPIO4                 ((     GPIO_TypeDef *)     GPIO4_BASE)\r
+#define WDT                   ((      WDT_TypeDef *)       WDT_BASE)\r
+#define TIM0                  ((      TIM_TypeDef *)      TIM0_BASE)\r
+#define TIM1                  ((      TIM_TypeDef *)      TIM1_BASE)\r
+#define TIM2                  ((      TIM_TypeDef *)      TIM2_BASE)\r
+#define TIM3                  ((      TIM_TypeDef *)      TIM3_BASE)\r
+#define RIT                   ((      RIT_TypeDef *)       RIT_BASE)\r
+#define UART0                 ((     UART_TypeDef *)     UART0_BASE)\r
+#define UART1                 ((    UART1_TypeDef *)     UART1_BASE)\r
+#define UART2                 ((     UART_TypeDef *)     UART2_BASE)\r
+#define UART3                 ((     UART_TypeDef *)     UART3_BASE)\r
+#define PWM1                  ((      PWM_TypeDef *)      PWM1_BASE)\r
+#define I2C0                  ((      I2C_TypeDef *)      I2C0_BASE)\r
+#define I2C1                  ((      I2C_TypeDef *)      I2C1_BASE)\r
+#define I2C2                  ((      I2C_TypeDef *)      I2C2_BASE)\r
+#define I2S                   ((      I2S_TypeDef *)       I2S_BASE)\r
+#define SPI                   ((      SPI_TypeDef *)       SPI_BASE)\r
+#define RTC                   ((      RTC_TypeDef *)       RTC_BASE)\r
+#define GPIOINT               ((  GPIOINT_TypeDef *)   GPIOINT_BASE)\r
+#define PINCON                ((   PINCON_TypeDef *)    PINCON_BASE)\r
+#define SSP0                  ((      SSP_TypeDef *)      SSP0_BASE)\r
+#define SSP1                  ((      SSP_TypeDef *)      SSP1_BASE)\r
+#define ADC                   ((      ADC_TypeDef *)       ADC_BASE)\r
+#define DAC                   ((      DAC_TypeDef *)       DAC_BASE)\r
+#define CANAF_RAM             ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE)\r
+#define CANAF                 ((    CANAF_TypeDef *)     CANAF_BASE)\r
+#define CANCR                 ((    CANCR_TypeDef *)     CANCR_BASE)\r
+#define CAN1                  ((      CAN_TypeDef *)      CAN1_BASE)\r
+#define CAN2                  ((      CAN_TypeDef *)      CAN2_BASE)\r
+#define MCPWM                 ((    MCPWM_TypeDef *)     MCPWM_BASE)\r
+#define QEI                   ((      QEI_TypeDef *)       QEI_BASE)\r
+#define EMAC                  ((     EMAC_TypeDef *)      EMAC_BASE)\r
+#define GPDMA                 ((    GPDMA_TypeDef *)     GPDMA_BASE)\r
+#define GPDMACH0              ((  GPDMACH_TypeDef *)  GPDMACH0_BASE)\r
+#define GPDMACH1              ((  GPDMACH_TypeDef *)  GPDMACH1_BASE)\r
+#define GPDMACH2              ((  GPDMACH_TypeDef *)  GPDMACH2_BASE)\r
+#define GPDMACH3              ((  GPDMACH_TypeDef *)  GPDMACH3_BASE)\r
+#define GPDMACH4              ((  GPDMACH_TypeDef *)  GPDMACH4_BASE)\r
+#define GPDMACH5              ((  GPDMACH_TypeDef *)  GPDMACH5_BASE)\r
+#define GPDMACH6              ((  GPDMACH_TypeDef *)  GPDMACH6_BASE)\r
+#define GPDMACH7              ((  GPDMACH_TypeDef *)  GPDMACH7_BASE)\r
+#define USB                   ((      USB_TypeDef *)       USB_BASE)\r
+\r
+#endif  // __LPC17xx_H__\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/LPC17xx_defs.h b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/LPC17xx_defs.h
new file mode 100644 (file)
index 0000000..bdc0c8f
--- /dev/null
@@ -0,0 +1,1508 @@
+/******************************************************************************\r
+ *   LPC17xx.h:  Header file for NXP LPC17xx Cortex-M3 Family Microprocessors\r
+ *   The header file is the super set of all hardware definitions of the \r
+ *   peripherals for the LPC17xx/24xx microprocessor.\r
+ *\r
+ *   Copyright(C) 2006-2008, NXP Semiconductor\r
+ *   All rights reserved.\r
+ *\r
+ *   History\r
+ *\r
+******************************************************************************/\r
+\r
+#ifndef __LPC17xx_H\r
+#define __LPC17xx_H\r
+\r
+//#include "sysdefs.h"\r
+\r
+#define SRAM_BASE_LOCAL       ((unsigned long)0x10000000)   // 32 Kb\r
+#define SRAM_BASE_AHB         ((unsigned long)0x20000000)      // 32 Kb\r
+\r
+/* System Control Space memory map */\r
+#define SCS_BASE              ((unsigned long)0xE000E000)\r
+\r
+#define SysTick_BASE          (SCS_BASE + 0x0010)\r
+#define NVIC_BASE             (SCS_BASE + 0x0100)\r
+#define CM3_PERIPH_BASE_ADDR  (SCS_BASE + 0x0D00)\r
+\r
+typedef struct\r
+{\r
+  unsigned long CPUID;\r
+  unsigned long IRQControlState;\r
+  unsigned long ExceptionTableOffset;\r
+  unsigned long AIRC;\r
+  unsigned long SysCtrl;\r
+  unsigned long ConfigCtrl;\r
+  unsigned long SystemPriority[3];\r
+  unsigned long SysHandlerCtrl;\r
+  unsigned long ConfigFaultStatus;\r
+  unsigned long HardFaultStatus;\r
+  unsigned long DebugFaultStatus;\r
+  unsigned long MemoryManageFaultAddr;\r
+  unsigned long BusFaultAddr;\r
+} CM3_t;\r
+\r
+/* Vector Table Base Address */\r
+#define NVIC_VectorTable_RAM          SRAM_BASE_AHB\r
+#define NVIC_VectorTable_FLASH        ((unsigned long)0x00000000)\r
+\r
+#define IS_NVIC_VECTORTBL(TABLE_BASE) ((TABLE_BASE == NVIC_VectorTable_RAM) || \\r
+                                       (TABLE_BASE == NVIC_VectorTable_FLASH))\r
+                                  \r
+/* Pin Connect Block */\r
+#define PINSEL_BASE_ADDR       0x4002C000\r
+#define PINSEL0        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00))\r
+#define PINSEL1        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04))\r
+#define PINSEL2        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08))\r
+#define PINSEL3        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x0C))\r
+#define PINSEL4        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x10))\r
+#define PINSEL5        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14))\r
+#define PINSEL6        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x18))\r
+#define PINSEL7        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x1C))\r
+#define PINSEL8        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x20))\r
+#define PINSEL9        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x24))\r
+#define PINSEL10       (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x28))\r
+\r
+#define PINMODE0        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x40))\r
+#define PINMODE1        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x44))\r
+#define PINMODE2        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x48))\r
+#define PINMODE3        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x4C))\r
+#define PINMODE4        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x50))\r
+#define PINMODE5        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x54))\r
+#define PINMODE6        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x58))\r
+#define PINMODE7        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x5C))\r
+#define PINMODE8        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x60))\r
+#define PINMODE9        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64))\r
+\r
+/* Open drain mode control */\r
+#define PINMODE_OD0     (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x68))\r
+#define PINMODE_OD1     (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x6C))\r
+#define PINMODE_OD2     (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x70))\r
+#define PINMODE_OD3     (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x74))\r
+#define PINMODE_OD4     (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x78))\r
+
+#define PINSEL0_P00_GPIO      ((unsigned int) 0x00000000)
+#define PINSEL0_P00_TXD0      ((unsigned int) 0x00000001)
+#define PINSEL0_P00_PWM1      ((unsigned int) 0x00000002)
+#define PINSEL0_P00_RSVD3     ((unsigned int) 0x00000003)
+#define PINSEL0_P00_MASK      ((unsigned int) 0x00000003)
+
+#define PINSEL0_P01_GPIO      ((unsigned int) 0x00000000)
+#define PINSEL0_P01_RXD0      ((unsigned int) 0x00000004)
+#define PINSEL0_P01_PWM3      ((unsigned int) 0x00000008)
+#define PINSEL0_P01_EINT0     ((unsigned int) 0x0000000C)
+#define PINSEL0_P01_MASK      ((unsigned int) 0x0000000C)
+
+#define PINSEL0_P02_GPIO      ((unsigned int) 0x00000000)
+#define PINSEL0_P02_SCL0      ((unsigned int) 0x00000010)
+#define PINSEL0_P02_CAP00     ((unsigned int) 0x00000020)
+#define PINSEL0_P02_RSVD3     ((unsigned int) 0x00000030)
+#define PINSEL0_P02_MASK      ((unsigned int) 0x00000030)
+
+#define PINSEL0_P03_GPIO      ((unsigned int) 0x00000000)
+#define PINSEL0_P03_SDA0      ((unsigned int) 0x00000040)
+#define PINSEL0_P03_MAT00     ((unsigned int) 0x00000080)
+#define PINSEL0_P03_EINT1     ((unsigned int) 0x000000C0)
+#define PINSEL0_P03_MASK      ((unsigned int) 0x000000C0)
+
+#define PINSEL0_P04_GPIO      ((unsigned int) 0x00000000)
+#define PINSEL0_P04_SCK0      ((unsigned int) 0x00000100)
+#define PINSEL0_P04_CAP01     ((unsigned int) 0x00000200)
+#define PINSEL0_P04_RSVD3     ((unsigned int) 0x00000300)
+#define PINSEL0_P04_MASK      ((unsigned int) 0x00000300)
+
+#define PINSEL0_P05_GPIO      ((unsigned int) 0x00000000)
+#define PINSEL0_P05_MISO0     ((unsigned int) 0x00000400)
+#define PINSEL0_P05_MAT01     ((unsigned int) 0x00000800)
+#define PINSEL0_P05_AD06      ((unsigned int) 0x00000C00)
+#define PINSEL0_P05_MASK      ((unsigned int) 0x00000C00)
+
+#define PINSEL0_P06_GPIO      ((unsigned int) 0x00000000)
+#define PINSEL0_P06_MOSI0     ((unsigned int) 0x00001000)
+#define PINSEL0_P06_CAP02     ((unsigned int) 0x00002000)
+#define PINSEL0_P06_AD10      ((unsigned int) 0x00003000)
+#define PINSEL0_P06_MASK      ((unsigned int) 0x00003000)
+
+#define PINSEL0_P07_GPIO      ((unsigned int) 0x00000000)
+#define PINSEL0_P07_SSEL0     ((unsigned int) 0x00004000)
+#define PINSEL0_P07_PWM2      ((unsigned int) 0x00008000)
+#define PINSEL0_P07_EINT2     ((unsigned int) 0x0000C000)
+#define PINSEL0_P07_MASK      ((unsigned int) 0x0000C000)
+
+#define PINSEL0_P08_GPIO      ((unsigned int) 0x00000000)
+#define PINSEL0_P08_TXD1      ((unsigned int) 0x00010000)
+#define PINSEL0_P08_PWM4      ((unsigned int) 0x00020000)
+#define PINSEL0_P08_AD11      ((unsigned int) 0x00030000)
+#define PINSEL0_P08_MASK      ((unsigned int) 0x00030000)
+
+#define PINSEL0_P09_GPIO      ((unsigned int) 0x00000000)
+#define PINSEL0_P09_RXD1      ((unsigned int) 0x00040000)
+#define PINSEL0_P09_PWM6      ((unsigned int) 0x00080000)
+#define PINSEL0_P09_EINT3     ((unsigned int) 0x000C0000)
+#define PINSEL0_P09_MASK      ((unsigned int) 0x000C0000)
+
+#define PINSEL0_P010_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL0_P010_RTS1     ((unsigned int) 0x00100000)
+#define PINSEL0_P010_CAP10    ((unsigned int) 0x00200000)
+#define PINSEL0_P010_AD12     ((unsigned int) 0x00300000)
+#define PINSEL0_P010_MASK     ((unsigned int) 0x00300000)
+
+#define PINSEL0_P011_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL0_P011_CTS1     ((unsigned int) 0x00400000)
+#define PINSEL0_P011_CAP11    ((unsigned int) 0x00800000)
+#define PINSEL0_P011_SCL1     ((unsigned int) 0x00C00000)
+#define PINSEL0_P011_MASK     ((unsigned int) 0x00C00000)
+
+#define PINSEL0_P012_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL0_P012_DSR1     ((unsigned int) 0x01000000)
+#define PINSEL0_P012_MAT10    ((unsigned int) 0x02000000)
+#define PINSEL0_P012_AD13     ((unsigned int) 0x03000000)
+#define PINSEL0_P012_MASK     ((unsigned int) 0x03000000)
+
+#define PINSEL0_P013_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL0_P013_DTR1     ((unsigned int) 0x04000000)
+#define PINSEL0_P013_MAT11    ((unsigned int) 0x08000000)
+#define PINSEL0_P013_AD14     ((unsigned int) 0x0C000000)
+#define PINSEL0_P013_MASK     ((unsigned int) 0x0C000000)
+
+#define PINSEL0_P014_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL0_P014_DCD1     ((unsigned int) 0x10000000)
+#define PINSEL0_P014_EINT1    ((unsigned int) 0x20000000)
+#define PINSEL0_P014_SDA1     ((unsigned int) 0x30000000)
+#define PINSEL0_P014_MASK     ((unsigned int) 0x30000000)
+
+#define PINSEL0_P015_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL0_P015_RI1      ((unsigned int) 0x40000000)
+#define PINSEL0_P015_EINT2    ((unsigned int) 0x80000000)
+#define PINSEL0_P015_AD15     ((unsigned int) 0xC0000000)
+#define PINSEL0_P015_MASK     ((unsigned int) 0xC0000000)
+
+#define PINSEL1_P016_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL1_P016_EINT0    ((unsigned int) 0x00000001)
+#define PINSEL1_P016_MAT02    ((unsigned int) 0x00000002)
+#define PINSEL1_P016_CAP02    ((unsigned int) 0x00000003)
+#define PINSEL1_P016_MASK     ((unsigned int) 0x00000003)
+
+#define PINSEL1_P017_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL1_P017_CAP12    ((unsigned int) 0x00000004)
+#define PINSEL1_P017_SCK1     ((unsigned int) 0x00000008)
+#define PINSEL1_P017_MAT12    ((unsigned int) 0x0000000c)
+#define PINSEL1_P017_MASK     ((unsigned int) 0x0000000c)
+
+#define PINSEL1_P018_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL1_P018_CAP13    ((unsigned int) 0x00000010)
+#define PINSEL1_P018_MISO1    ((unsigned int) 0x00000020)
+#define PINSEL1_P018_MAT13    ((unsigned int) 0x00000030)
+#define PINSEL1_P018_MASK     ((unsigned int) 0x00000030)
+
+#define PINSEL1_P019_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL1_P019_MAT12    ((unsigned int) 0x00000040)
+#define PINSEL1_P019_MOSI1    ((unsigned int) 0x00000080)
+#define PINSEL1_P019_CAP12    ((unsigned int) 0x000000c0)
+
+#define PINSEL1_P020_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL1_P020_MAT13    ((unsigned int) 0x00000100)
+#define PINSEL1_P020_SSEL1    ((unsigned int) 0x00000200)
+#define PINSEL1_P020_EINT3    ((unsigned int) 0x00000300)
+#define PINSEL1_P020_MASK     ((unsigned int) 0x00000300)
+
+#define PINSEL1_P021_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL1_P021_PWM5     ((unsigned int) 0x00000400)
+#define PINSEL1_P021_AD16     ((unsigned int) 0x00000800)
+#define PINSEL1_P021_CAP13    ((unsigned int) 0x00000c00)
+#define PINSEL1_P021_MASK     ((unsigned int) 0x00000c00)
+
+#define PINSEL1_P022_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL1_P022_AD17     ((unsigned int) 0x00001000)
+#define PINSEL1_P022_CAP00    ((unsigned int) 0x00002000)
+#define PINSEL1_P022_MAT00    ((unsigned int) 0x00003000)
+#define PINSEL1_P022_MASK     ((unsigned int) 0x00003000)
+
+#define PINSEL1_P023_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL1_P023_VBUS     ((unsigned int) 0x00004000)
+#define PINSEL1_P023_RSVD2    ((unsigned int) 0x00008000)
+#define PINSEL1_P023_RSVD3    ((unsigned int) 0x0000c000)
+#define PINSEL1_P023_MASK     ((unsigned int) 0x0000c000)
+
+#define PINSEL1_P024_RSVD0    ((unsigned int) 0x00000000)
+#define PINSEL1_P024_RSVD1    ((unsigned int) 0x00010000)
+#define PINSEL1_P024_RSVD2    ((unsigned int) 0x00020000)
+#define PINSEL1_P024_RSVD3    ((unsigned int) 0x00030000)
+#define PINSEL1_P024_MASK     ((unsigned int) 0x00030000)
+
+#define PINSEL1_P025_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL1_P025_AD04     ((unsigned int) 0x00040000)
+#define PINSEL1_P025_AOUT     ((unsigned int) 0x00080000)
+#define PINSEL1_P025_RSVD3    ((unsigned int) 0x000c0000)
+#define PINSEL1_P025_MASK     ((unsigned int) 0x000c0000)
+
+#define PINSEL1_P026_RSVD0    ((unsigned int) 0x00000000)
+#define PINSEL1_P026_RSVD1    ((unsigned int) 0x00100000)
+#define PINSEL1_P026_RSVD2    ((unsigned int) 0x00200000)
+#define PINSEL1_P026_RSVD3    ((unsigned int) 0x00300000)
+#define PINSEL1_P026_MASK     ((unsigned int) 0x00300000)
+
+#define PINSEL1_P027_RSVD0    ((unsigned int) 0x00000000)
+#define PINSEL1_P027_RSVD1    ((unsigned int) 0x00400000)
+#define PINSEL1_P027_RSVD2    ((unsigned int) 0x00800000)
+#define PINSEL1_P027_RSVD3    ((unsigned int) 0x00c00000)
+#define PINSEL1_P027_MASK     ((unsigned int) 0x00c00000)
+
+#define PINSEL1_P028_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL1_P028_AD01     ((unsigned int) 0x01000000)
+#define PINSEL1_P028_CAP02    ((unsigned int) 0x02000000)
+#define PINSEL1_P028_MAT02    ((unsigned int) 0x03000000)
+#define PINSEL1_P028_MASK     ((unsigned int) 0x03000000)
+
+#define PINSEL1_P029_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL1_P029_AD02     ((unsigned int) 0x04000000)
+#define PINSEL1_P029_CAP03    ((unsigned int) 0x08000000)
+#define PINSEL1_P029_MAT03    ((unsigned int) 0x0c000000)
+#define PINSEL1_P029_MASK     ((unsigned int) 0x0c000000)
+
+#define PINSEL1_P030_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL1_P030_AD03     ((unsigned int) 0x10000000)
+#define PINSEL1_P030_EINT3    ((unsigned int) 0x20000000)
+#define PINSEL1_P030_CAP00    ((unsigned int) 0x30000000)
+#define PINSEL1_P030_MASK     ((unsigned int) 0x30000000)
+
+#define PINSEL1_P031_GPIO     ((unsigned int) 0x00000000)
+#define PINSEL1_P031_UPLED    ((unsigned int) 0x40000000)
+#define PINSEL1_P031_CONNECT  ((unsigned int) 0x80000000)
+#define PINSEL1_P031_RSVD3    ((unsigned int) 0xc0000000)
+#define PINSEL1_P031_MASK     ((unsigned int) 0xc0000000)
+
+#define PINSEL2_P13626_GPIO   ((unsigned int) 0x00000000) 
+#define PINSEL2_P13626_DEBUG  ((unsigned int) 0x00000004) 
+#define PINSEL2_P13626_MASK   ((unsigned int) 0x00000004)
+
+#define PINSEL2_P12516_GPIO   ((unsigned int) 0x00000000) 
+#define PINSEL2_P12516_TRACE  ((unsigned int) 0x00000008) 
+#define PINSEL2_P12516_MASK   ((unsigned int) 0x00000008)
+\r
+/* General Purpose Input/Output (GPIO) */\r
+/* Fast I/O setup */\r
+\r
+#define FIO_BASE_ADDR          0x50014000\r
+\r
+#define FIO0DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) \r
+#define FIO0MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10))\r
+#define FIO0PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14))\r
+#define FIO0SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18))\r
+#define FIO0CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C))\r
+\r
+#ifdef LPC1766_UM_DEFS\r
+/* Fast GPIO Register Access */\r
+#define FIO0SET0          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))\r
+#define FIO0SET1          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x39))\r
+#define FIO0SET2          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3A))\r
+#define FIO0SET3          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3B))\r
+#define FIO0SETL          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))\r
+#define FIO0SETU          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3A))\r
+#endif\r
+\r
+#define FIO1DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) \r
+#define FIO1MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30))\r
+#define FIO1PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34))\r
+#define FIO1SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))\r
+#define FIO1CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C))\r
+\r
+#ifdef LPC1766_UM_DEFS\r
+/* Fast GPIO Register Access */\r
+#define FIO1SET0          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78))\r
+#define FIO1SET1          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x79))\r
+#define FIO1SET2          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7A))\r
+#define FIO1SET3          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7B))\r
+#define FIO1SETL          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78))\r
+#define FIO1SETU          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7A))\r
+#endif\r
+\r
+#define FIO2DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) \r
+#define FIO2MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50))\r
+#define FIO2PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54))\r
+#define FIO2SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58))\r
+#define FIO2CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C))\r
+\r
+#ifdef LPC1766_UM_DEFS\r
+/* Fast GPIO Register Access */\r
+#define FIO2SET0          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xB8))\r
+#define FIO2SET1          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xB9))\r
+#define FIO2SET2          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xBA))\r
+#define FIO2SET3          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xBB))\r
+#define FIO2SETL          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xB8))\r
+#define FIO2SETU          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xBA))\r
+#endif\r
+\r
+#define FIO3DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) \r
+#define FIO3MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70))\r
+#define FIO3PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74))\r
+#define FIO3SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78))\r
+#define FIO3CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C))\r
+\r
+#ifdef LPC1766_UM_DEFS\r
+/* Fast GPIO Register Access */\r
+#define FIO3SET0          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xF8))\r
+#define FIO3SET1          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xF9))\r
+#define FIO3SET2          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xFA))\r
+#define FIO3SET3          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xFB))\r
+#define FIO3SETL          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xF8))\r
+#define FIO3SETU          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xFA))\r
+#endif\r
+\r
+#define FIO4DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) \r
+#define FIO4MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90))\r
+#define FIO4PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94))\r
+#define FIO4SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98))\r
+#define FIO4CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C))\r
+\r
+#ifdef LPC1766_UM_DEFS\r
+/* Fast GPIO Register Access */\r
+#define FIO4SET0          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x138))\r
+#define FIO4SET1          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x139))\r
+#define FIO4SET2          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x13A))\r
+#define FIO0SET3          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3B))\r
+#define FIO4SET3          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x13B))\r
+#define FIO4SETL          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x138))\r
+#define FIO4SETU          (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x13A))\r
+#endif\r
+\r
+/* General Purpose Input/Output (GPIO) */\r
+#define GPIO_BASE_ADDR         0x40028000\r
+#define IOPIN0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))\r
+#define IOSET0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))\r
+#define IODIR0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))\r
+#define IOCLR0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C))\r
+#define IOPIN1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))\r
+#define IOSET1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))\r
+#define IODIR1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))\r
+#define IOCLR1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))\r
+
+#define GPIO_IO_P0      ((unsigned int) 0x00000001)
+#define GPIO_IO_P1      ((unsigned int) 0x00000002)
+#define GPIO_IO_P2      ((unsigned int) 0x00000004)
+#define GPIO_IO_P3      ((unsigned int) 0x00000008)
+#define GPIO_IO_P4      ((unsigned int) 0x00000010)
+#define GPIO_IO_P5      ((unsigned int) 0x00000020)
+#define GPIO_IO_P6      ((unsigned int) 0x00000040)
+#define GPIO_IO_P7      ((unsigned int) 0x00000080)
+#define GPIO_IO_P8      ((unsigned int) 0x00000100)
+#define GPIO_IO_P9      ((unsigned int) 0x00000200)
+#define GPIO_IO_P10     ((unsigned int) 0x00000400)
+#define GPIO_IO_P11     ((unsigned int) 0x00000800)
+#define GPIO_IO_P12     ((unsigned int) 0x00001000)
+#define GPIO_IO_P13     ((unsigned int) 0x00002000)
+#define GPIO_IO_P14     ((unsigned int) 0x00004000)
+#define GPIO_IO_P15     ((unsigned int) 0x00008000)
+#define GPIO_IO_P16     ((unsigned int) 0x00010000)
+#define GPIO_IO_P17     ((unsigned int) 0x00020000)
+#define GPIO_IO_P18     ((unsigned int) 0x00040000)
+#define GPIO_IO_P19     ((unsigned int) 0x00080000)
+#define GPIO_IO_P20     ((unsigned int) 0x00100000)
+#define GPIO_IO_P21     ((unsigned int) 0x00200000)
+#define GPIO_IO_P22     ((unsigned int) 0x00400000)
+#define GPIO_IO_P23     ((unsigned int) 0x00800000)
+#define GPIO_IO_P24     ((unsigned int) 0x01000000)
+#define GPIO_IO_P25     ((unsigned int) 0x02000000)
+#define GPIO_IO_P26     ((unsigned int) 0x04000000)
+#define GPIO_IO_P27     ((unsigned int) 0x08000000)
+#define GPIO_IO_P28     ((unsigned int) 0x10000000)
+#define GPIO_IO_P29     ((unsigned int) 0x20000000)
+#define GPIO_IO_P30     ((unsigned int) 0x40000000)
+#define GPIO_IO_P31     ((unsigned int) 0x80000000)
+#define GPIO_IO_JTAG    ((unsigned int) 0x003E0000)\r
+\r
+/* GPIO Interrupt Registers */\r
+#define IO0_INT_EN_R    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) \r
+#define IO0_INT_EN_F    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94))\r
+#define IO0_INT_STAT_R  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84))\r
+#define IO0_INT_STAT_F  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88))\r
+#define IO0_INT_CLR     (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C))\r
+\r
+#define IO2_INT_EN_R    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) \r
+#define IO2_INT_EN_F    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4))\r
+#define IO2_INT_STAT_R  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4))\r
+#define IO2_INT_STAT_F  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8))\r
+#define IO2_INT_CLR     (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xAC))\r
+\r
+#define IO_INT_STAT     (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80))\r
+\r
+#define PARTCFG_BASE_ADDR              0x3FFF8000\r
+#define PARTCFG        (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) \r
+\r
+/* System Control Block(SCB) modules include Memory Accelerator Module,\r
+Phase Locked Loop, VPB divider, Power Control, External Interrupt, \r
+Reset, and Code Security/Debugging */\r
+#define SCB_BASE_ADDR   0x400FC000\r
+\r
+/* Memory Accelerator Module */\r
+\r
+/* Phase Locked Loop (PLL0) */\r
+#define PLL0CON        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080))\r
+#define PLL0CFG        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084))\r
+#define PLL0STAT       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088))\r
+#define PLL0FEED       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C))\r
+\r
+/* Phase Locked Loop (PLL1) */\r
+#define PLL1CON        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A0))\r
+#define PLL1CFG        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A4))\r
+#define PLL1STAT       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A8))\r
+#define PLL1FEED       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0AC))\r
+
+#define PLLCON_PLLE     0x00000001
+#define PLLCON_PLLC     0x00000002
+#define PLLCON_MASK     0x00000003\r
+\r
+#define PLLCFG_MUL1     0x00000000
+#define PLLCFG_MUL2     0x00000001
+#define PLLCFG_MUL3     0x00000002
+#define PLLCFG_MUL4     0x00000003
+#define PLLCFG_MUL5     0x00000004
+#define PLLCFG_MUL6     0x00000005
+#define PLLCFG_MUL7     0x00000006
+#define PLLCFG_MUL8     0x00000007
+#define PLLCFG_MUL9     0x00000008
+#define PLLCFG_MUL10    0x00000009
+#define PLLCFG_MUL11    0x0000000A
+#define PLLCFG_MUL12    0x0000000B
+#define PLLCFG_MUL13    0x0000000C
+#define PLLCFG_MUL14    0x0000000D
+#define PLLCFG_MUL15    0x0000000E
+#define PLLCFG_MUL16    0x0000000F
+#define PLLCFG_MUL17    0x00000010
+#define PLLCFG_MUL18    0x00000011
+#define PLLCFG_MUL19    0x00000012
+#define PLLCFG_MUL20    0x00000013
+#define PLLCFG_MUL21    0x00000014
+#define PLLCFG_MUL22    0x00000015
+#define PLLCFG_MUL23    0x00000016
+#define PLLCFG_MUL24    0x00000017
+#define PLLCFG_MUL25    0x00000018
+#define PLLCFG_MUL26    0x00000019
+#define PLLCFG_MUL27    0x0000001A
+#define PLLCFG_MUL28    0x0000001B
+#define PLLCFG_MUL29    0x0000001C
+#define PLLCFG_MUL30    0x0000001D
+#define PLLCFG_MUL31    0x0000001E
+#define PLLCFG_MUL32    0x0000001F\r
+#define PLLCFG_MUL33    0x00000020\r
+#define PLLCFG_MUL34    0x00000021\r
+#define PLLCFG_MUL35    0x00000022\r
+#define PLLCFG_MUL36    0x00000023\r
+
+#define PLLCFG_DIV1     0x00000000
+#define PLLCFG_DIV2     0x00010000\r
+#define PLLCFG_DIV3     0x00020000
+#define PLLCFG_DIV4     0x00030000\r
+#define PLLCFG_DIV5     0x00040000\r
+#define PLLCFG_DIV6     0x00050000\r
+#define PLLCFG_DIV7     0x00060000
+#define PLLCFG_DIV8     0x00070000\r
+#define PLLCFG_DIV9     0x00080000\r
+#define PLLCFG_DIV10    0x00090000
+#define PLLCFG_MASK            0x00FF7FFF\r
+\r
+#define PLLSTAT_MSEL_MASK      0x00007FFF\r
+#define PLLSTAT_NSEL_MASK      0x00FF0000\r
+
+#define PLLSTAT_PLLE   (1 << 24)
+#define PLLSTAT_PLLC   (1 << 25)
+#define PLLSTAT_PLOCK  (1 << 26)\r
+
+#define PLLFEED_FEED1   0x000000AA
+#define PLLFEED_FEED2   0x00000055\r
+\r
+/* Power Control */\r
+#define PCON           (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0))\r
+#define PCONP          (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4))\r
+
+#define PCON_IDL        0x00000001
+#define PCON_PD         0x00000002
+#define PCON_PDBOD      0x00000004
+#define PCON_BODPDM     0x00000008
+#define PCON_BOGD       0x00000010
+#define PCON_BORD       0x00000020
+#define PCON_MASK       0x0000003F
+
+#define PCONP_PCTIM0    0x00000002
+#define PCONP_PCTIM1    0x00000004
+#define PCONP_PCUART0   0x00000008
+#define PCONP_PCUART1   0x00000010
+#define PCONP_PCPWM1    0x00000040
+#define PCONP_PCI2C0    0x00000080
+#define PCONP_PCSPI     0x00000100
+#define PCONP_PCRTC     0x00000200
+#define PCONP_PCSSP1    0x00000400\r
+#define PCONP_PCAD      0x00001000\r
+#define PCONP_PCCAN1    0x00002000\r
+#define PCONP_PCCAN2    0x00004000\r
+#define PCONP_PCGPIO    0x00008000\r
+#define PCONP_PCRIT     0x00010000\r
+#define PCONP_PCMCPWM   0x00020000\r
+#define PCONP_PCQEI     0x00040000
+#define PCONP_PCI2C1    0x00080000\r
+#define PCONP_PCSSP0    0x00200000\r
+#define PCONP_PCTIM2    0x00400000\r
+#define PCONP_PCTIM3    0x00800000\r
+#define PCONP_PCUART2   0x01000000\r
+#define PCONP_PCUART3   0x02000000\r
+#define PCONP_PCI2C2    0x04000000\r
+#define PCONP_PCI2S     0x08000000\r
+#define PCONP_PCGPDMA   0x20000000\r
+#define PCONP_PCENET    0x40000000\r
+#define PCONP_PCUSB     0x80000000\r
+#define PCONP_MASK      0x801817BE
+\r
+// Each peripheral clock source uses 2 bits
+#define PCLK_25         0x0                            // divide by 4
+#define PCLK_100        0x1                            // divide by 1
+#define PCLK_50         0x2                            // divide by 2
+#define PCLK_RSVD       0x3                            // divide by 8*
+#define PCLK_MASK       0x3
+
+#define EXTINT_EINT0    0x00000001
+#define EXTINT_EINT1    0x00000002
+#define EXTINT_EINT2    0x00000004
+#define EXTINT_EINT3    0x00000008
+#define EXTINT_MASK     0x0000000F
+
+#define INTWAKE_EINT0   0x00000001
+#define INTWAKE_EINT1   0x00000002
+#define INTWAKE_EINT2   0x00000004
+#define INTWAKE_EINT3   0x00000008
+#define INTWAKE_USB     0x00000020
+#define INTWAKE_BOD     0x00004000
+#define INTWAKE_RTC     0x00008000
+#define INTWAKE_MASK    0x0000C02F
+
+#define EXTMODE_EINT0   0x00000001
+#define EXTMODE_EINT1   0x00000002
+#define EXTMODE_EINT2   0x00000004
+#define EXTMODE_EINT3   0x00000008
+#define EXTMODE_MASK    0x0000000F
+
+#define EXTPOLAR_EINT0  0x00000001
+#define EXTPOLAR_EINT1  0x00000002
+#define EXTPOLAR_EINT2  0x00000004
+#define EXTPOLAR_EINT3  0x00000008
+#define EXTPOLAR_MASK   0x0000000F
+
+#define RSIR_POR        0x00000001
+#define RSIR_EXTR       0x00000002
+#define RSIR_WDTR       0x00000004
+#define RSIR_BODR       0x00000008
+#define RSIR_MASK       0x0000000F
+
+#define SCS_GPIO0M      0x00000001
+#define SCS_GPIO1M      0x00000002
+#define SCS_MASK        0x00000003\r
+\r
+/* Clock Divider */\r
+// #define APBDIV         (*(volatile unsigned long *)(BASE_ADDR + 0x100))\r
+#define CCLKCFG        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104))\r
+#define USBCLKCFG      (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108))\r
+#define CLKSRCSEL      (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C))\r
+#define PCLKSEL0       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8))\r
+#define PCLKSEL1       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC))\r
+       \r
+/* External Interrupts */\r
+#define EXTINT         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140))\r
+#define INTWAKE        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144))\r
+#define EXTMODE        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148))\r
+#define EXTPOLAR       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C))\r
+\r
+/* Reset, reset source identification */\r
+#define RSIR           (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))\r
+\r
+/* RSID, code security protection */\r
+#define CSPR           (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184))\r
+\r
+/* AHB configuration */\r
+#define AHBCFG1        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188))\r
+#define AHBCFG2        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C))\r
+\r
+/* System Controls and Status */\r
+#define SCS            (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))    \r
+\r
+/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers \r
+are for LPC24xx only. */\r
+#define STATIC_MEM0_BASE               0x80000000\r
+#define STATIC_MEM1_BASE               0x81000000\r
+#define STATIC_MEM2_BASE               0x82000000\r
+#define STATIC_MEM3_BASE               0x83000000\r
+\r
+#define DYNAMIC_MEM0_BASE              0xA0000000\r
+#define DYNAMIC_MEM1_BASE              0xB0000000\r
+#define DYNAMIC_MEM2_BASE              0xC0000000\r
+#define DYNAMIC_MEM3_BASE              0xD0000000\r
+\r
+/* External Memory Controller (EMC) */\r
+#define EMC_BASE_ADDR          0xFFE08000\r
+#define EMC_CTRL       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000))\r
+#define EMC_STAT       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004))\r
+#define EMC_CONFIG     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008))\r
+\r
+/* Dynamic RAM access registers */\r
+#define EMC_DYN_CTRL     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020))\r
+#define EMC_DYN_RFSH     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024))\r
+#define EMC_DYN_RD_CFG   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028))\r
+#define EMC_DYN_RP       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030))\r
+#define EMC_DYN_RAS      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034))\r
+#define EMC_DYN_SREX     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038))\r
+#define EMC_DYN_APR      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C))\r
+#define EMC_DYN_DAL      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040))\r
+#define EMC_DYN_WR       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044))\r
+#define EMC_DYN_RC       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048))\r
+#define EMC_DYN_RFC      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C))\r
+#define EMC_DYN_XSR      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050))\r
+#define EMC_DYN_RRD      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054))\r
+#define EMC_DYN_MRD      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058))\r
+\r
+#define EMC_DYN_CFG0     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100))\r
+#define EMC_DYN_RASCAS0  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104))\r
+#define EMC_DYN_CFG1     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x120))\r
+#define EMC_DYN_RASCAS1  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x124))\r
+#define EMC_DYN_CFG2     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140))\r
+#define EMC_DYN_RASCAS2  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144))\r
+#define EMC_DYN_CFG3     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160))\r
+#define EMC_DYN_RASCAS3  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164))\r
+\r
+/* static RAM access registers */\r
+#define EMC_STA_CFG0      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200))\r
+#define EMC_STA_WAITWEN0  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204))\r
+#define EMC_STA_WAITOEN0  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208))\r
+#define EMC_STA_WAITRD0   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C))\r
+#define EMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210))\r
+#define EMC_STA_WAITWR0   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214))\r
+#define EMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218))\r
+\r
+#define EMC_STA_CFG1      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220))\r
+#define EMC_STA_WAITWEN1  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224))\r
+#define EMC_STA_WAITOEN1  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228))\r
+#define EMC_STA_WAITRD1   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C))\r
+#define EMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230))\r
+#define EMC_STA_WAITWR1   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234))\r
+#define EMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238))\r
+\r
+#define EMC_STA_CFG2      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240))\r
+#define EMC_STA_WAITWEN2  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244))\r
+#define EMC_STA_WAITOEN2  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248))\r
+#define EMC_STA_WAITRD2   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C))\r
+#define EMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250))\r
+#define EMC_STA_WAITWR2   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254))\r
+#define EMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258))\r
+\r
+#define EMC_STA_CFG3      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260))\r
+#define EMC_STA_WAITWEN3  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264))\r
+#define EMC_STA_WAITOEN3  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268))\r
+#define EMC_STA_WAITRD3   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C))\r
+#define EMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270))\r
+#define EMC_STA_WAITWR3   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274))\r
+#define EMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278))\r
+\r
+#define EMC_STA_EXT_WAIT  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880))\r
+\r
+/* Timer 0 */\r
+#define TMR0_BASE_ADDR         0x40004000\r
+#define T0IR           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))\r
+#define T0TCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))\r
+#define T0TC           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))\r
+#define T0PR           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))\r
+#define T0PC           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))\r
+#define T0MCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))\r
+#define T0MR0          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))\r
+#define T0MR1          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C))\r
+#define T0MR2          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20))\r
+#define T0MR3          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24))\r
+#define T0CCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28))\r
+#define T0CR0          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C))\r
+#define T0CR1          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30))\r
+#define T0CR2          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34))\r
+#define T0CR3          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38))\r
+#define T0EMR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C))\r
+#define T0CTCR         (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))\r
+\r
+/* Timer 1 */\r
+#define TMR1_BASE_ADDR         0x40008000\r
+#define T1IR           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))\r
+#define T1TCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))\r
+#define T1TC           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))\r
+#define T1PR           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C))\r
+#define T1PC           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10))\r
+#define T1MCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14))\r
+#define T1MR0          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18))\r
+#define T1MR1          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C))\r
+#define T1MR2          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20))\r
+#define T1MR3          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24))\r
+#define T1CCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28))\r
+#define T1CR0          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C))\r
+#define T1CR1          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30))\r
+#define T1CR2          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34))\r
+#define T1CR3          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38))\r
+#define T1EMR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C))\r
+#define T1CTCR         (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))\r
+\r
+/* Timer 2 */\r
+#define TMR2_BASE_ADDR         0x40090000\r
+#define T2IR           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00))\r
+#define T2TCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04))\r
+#define T2TC           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08))\r
+#define T2PR           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C))\r
+#define T2PC           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10))\r
+#define T2MCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14))\r
+#define T2MR0          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18))\r
+#define T2MR1          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C))\r
+#define T2MR2          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20))\r
+#define T2MR3          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24))\r
+#define T2CCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28))\r
+#define T2CR0          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C))\r
+#define T2CR1          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30))\r
+#define T2CR2          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34))\r
+#define T2CR3          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38))\r
+#define T2EMR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C))\r
+#define T2CTCR         (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70))\r
+\r
+/* Timer 3 */\r
+#define TMR3_BASE_ADDR         0x40094000\r
+#define T3IR           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00))\r
+#define T3TCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04))\r
+#define T3TC           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08))\r
+#define T3PR           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C))\r
+#define T3PC           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10))\r
+#define T3MCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14))\r
+#define T3MR0          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18))\r
+#define T3MR1          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C))\r
+#define T3MR2          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20))\r
+#define T3MR3          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24))\r
+#define T3CCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28))\r
+#define T3CR0          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C))\r
+#define T3CR1          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30))\r
+#define T3CR2          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34))\r
+#define T3CR3          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38))\r
+#define T3EMR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C))\r
+#define T3CTCR         (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70))\r
+
+#define T_IR_MR0            0x00000001
+#define T_IR_MR1            0x00000002
+#define T_IR_MR2            0x00000004
+#define T_IR_MR3            0x00000008
+#define T_IR_CR0            0x00000010
+#define T_IR_CR1            0x00000020
+#define T_IR_CR2            0x00000040
+#define T_IR_CR3            0x00000080
+#define T_IR_MASK           0x000000FF
+
+#define T_TCR_CE            0x00000001
+#define T_TCR_CR            0x00000002
+
+#define T_CTCR_MODE_PCLK    0x00000000
+#define T_CTCR_MODE_CAPRISE 0x00000001
+#define T_CTCR_MODE_CAPFALL 0x00000002
+#define T_CTCR_MODE_CAPBOTH 0x00000003
+#define T_CTCR_MODE_MASK    0x00000003
+#define T_CTCR_CIS_CAPN0    0x00000000
+#define T_CTCR_CIS_CAPN1    0x00000004
+#define T_CTCR_CIS_CAPN2    0x00000008
+#define T_CTCR_CIS_CAPN3    0x0000000C
+#define T_CTCR_CIS_MASK     0x0000000C
+
+#define T_MCR_MR0I          0x00000001
+#define T_MCR_MR0R          0x00000002
+#define T_MCR_MR0S          0x00000004
+#define T_MCR_MR1I          0x00000008
+#define T_MCR_MR1R          0x00000010
+#define T_MCR_MR1S          0x00000020
+#define T_MCR_MR2I          0x00000040
+#define T_MCR_MR2R          0x00000080
+#define T_MCR_MR2S          0x00000100
+#define T_MCR_MR3I          0x00000200
+#define T_MCR_MR3R          0x00000400
+#define T_MCR_MR3S          0x00000800
+
+#define T_CCR_CAP0RE        0x00000001
+#define T_CCR_CAP0FE        0x00000002
+#define T_CCR_CAP0I         0x00000004
+#define T_CCR_CAP1RE        0x00000008
+#define T_CCR_CAP1FE        0x00000010
+#define T_CCR_CAP1I         0x00000020
+#define T_CCR_CAP2RE        0x00000040
+#define T_CCR_CAP2FE        0x00000080
+#define T_CCR_CAP2I         0x00000100
+#define T_CCR_CAP3RE        0x00000200
+#define T_CCR_CAP3FE        0x00000400
+#define T_CCR_CAP3I         0x00000800
+
+#define T_EMR_EM0           0x00000001
+#define T_EMR_EM1           0x00000002
+#define T_EMR_EM2           0x00000004
+#define T_EMR_EM3           0x00000008
+#define T_EMR_EMC0_NONE     0x00000000
+#define T_EMR_EMC0_CLEAR    0x00000010
+#define T_EMR_EMC0_SET      0x00000020
+#define T_EMR_EMC0_TOGGLE   0x00000030
+#define T_EMR_EMC0_MASK     0x00000030
+#define T_EMR_EMC1_NONE     0x00000000
+#define T_EMR_EMC1_CLEAR    0x00000040
+#define T_EMR_EMC1_SET      0x00000080
+#define T_EMR_EMC1_TOGGLE   0x000000C0
+#define T_EMR_EMC1_MASK     0x000000C0
+#define T_EMR_EMC2_NONE     0x00000000
+#define T_EMR_EMC2_CLEAR    0x00000100
+#define T_EMR_EMC2_SET      0x00000200
+#define T_EMR_EMC2_TOGGLE   0x00000300
+#define T_EMR_EMC2_MASK     0x00000300
+#define T_EMR_EMC3_NONE     0x00000000
+#define T_EMR_EMC3_CLEAR    0x00000400
+#define T_EMR_EMC3_SET      0x00000800
+#define T_EMR_EMC3_TOGGLE   0x00000C00
+#define T_EMR_EMC3_MASK     0x00000C00
+\r
+/* Pulse Width Modulator (PWM1) */\r
+#define PWM1_BASE_ADDR         0x40018000\r
+#define PWM1IR          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00))\r
+#define PWM1TCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04))\r
+#define PWM1TC          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08))\r
+#define PWM1PR          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C))\r
+#define PWM1PC          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10))\r
+#define PWM1MCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14))\r
+#define PWM1MR0         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18))\r
+#define PWM1MR1         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C))\r
+#define PWM1MR2         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20))\r
+#define PWM1MR3         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24))\r
+#define PWM1CCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28))\r
+#define PWM1CR0         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C))\r
+#define PWM1CR1         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30))\r
+#define PWM1CR2         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34))\r
+#define PWM1CR3         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38))\r
+#define PWM1EMR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x3C))\r
+#define PWM1MR4         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40))\r
+#define PWM1MR5         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44))\r
+#define PWM1MR6         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48))\r
+#define PWM1PCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C))\r
+#define PWM1LER         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50))\r
+#define PWM1CTCR        (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70))\r
+\r
+/* Universal Asynchronous Receiver Transmitter 0 (UART0) */\r
+#define UART0_BASE_ADDR                0x4000C000\r
+#define U0RBR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))\r
+#define U0THR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))\r
+#define U0DLL          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))\r
+#define U0DLM          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))\r
+#define U0IER          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))\r
+#define U0IIR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))\r
+#define U0FCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))\r
+#define U0LCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C))\r
+#define U0LSR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14))\r
+#define U0SCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C))\r
+#define U0ACR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20))\r
+#define U0ICR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x24))\r
+#define U0FDR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28))\r
+#define U0TER          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30))\r
+
+#define UART0_RBR       U0RBR
+#define UART0_THR       U0THR
+#define UART0_IER       U0IER
+#define UART0_IIR       U0IIR
+#define UART0_FCR       U0FCR
+#define UART0_LCR       U0LCR
+#define UART0_LSR       U0LSR
+#define UART0_SCR       U0SCR
+#define UART0_ACR       U0ACR
+#define UART0_FDR       U0FDR
+#define UART0_TER       U0TER
+#define UART0_DLL       U0DLL
+#define UART0_DLM       U0DLM\r
+\r
+/* Universal Asynchronous Receiver Transmitter 1 (UART1) */\r
+#define UART1_BASE_ADDR                0x40010000\r
+#define U1RBR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))\r
+#define U1THR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))\r
+#define U1DLL          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))\r
+#define U1DLM          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))\r
+#define U1IER          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))\r
+#define U1IIR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))\r
+#define U1FCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))\r
+#define U1LCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C))\r
+#define U1MCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10))\r
+#define U1LSR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14))\r
+#define U1MSR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18))\r
+#define U1SCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C))\r
+#define U1ACR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20))\r
+#define U1FDR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28))\r
+#define U1TER          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30))\r
+
+#define UART1_RBR       U1RBR
+#define UART1_THR       U1THR
+#define UART1_IER       U1IER
+#define UART1_IIR       U1IIR
+#define UART1_FCR       U1FCR
+#define UART1_LCR       U1LCR
+#define UART1_LSR       U1LSR
+#define UART1_SCR       U1SCR
+#define UART1_ACR       U1ACR
+#define UART1_FDR       U1FDR
+#define UART1_TER       U1TER
+#define UART1_DLL       U1DLL
+#define UART1_DLM       U1DLM
+#define UART1_MCR       U1MCR
+#define UART1_MSR       U1MSR\r
+\r
+/* Universal Asynchronous Receiver Transmitter 2 (UART2) */\r
+#define UART2_BASE_ADDR                0x40098000\r
+#define U2RBR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))\r
+#define U2THR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))\r
+#define U2DLL          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))\r
+#define U2DLM          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))\r
+#define U2IER          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))\r
+#define U2IIR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))\r
+#define U2FCR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))\r
+#define U2LCR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C))\r
+#define U2LSR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14))\r
+#define U2SCR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C))\r
+#define U2ACR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20))\r
+#define U2ICR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x24))\r
+#define U2FDR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28))\r
+#define U2TER          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30))\r
+\r
+/* Universal Asynchronous Receiver Transmitter 3 (UART3) */\r
+#define UART3_BASE_ADDR                0x4009C000\r
+#define U3RBR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))\r
+#define U3THR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))\r
+#define U3DLL          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))\r
+#define U3DLM          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))\r
+#define U3IER          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))\r
+#define U3IIR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))\r
+#define U3FCR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))\r
+#define U3LCR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C))\r
+#define U3LSR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14))\r
+#define U3SCR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C))\r
+#define U3ACR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20))\r
+#define U3ICR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24))\r
+#define U3FDR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28))\r
+#define U3TER          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30))\r
+
+#define UART_LCR_DLAB   0x00000080
+#define UART_LCR_NOPAR  0x00000000
+#define UART_LCR_1STOP  0x00000000
+#define UART_LCR_8BITS  0x00000003
+#define UART_IER_EI     0x00000003
+#define UART_FCR_EN     0x00000001
+#define UART_FCR_CLR    0x00000006\r
+\r
+/* I2C Interface 0 */\r
+#define I2C0_BASE_ADDR         0x4001C000\r
+#define I20CONSET      (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))\r
+#define I20STAT        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))\r
+#define I20DAT         (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))\r
+#define I20ADR         (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C))\r
+#define I20SCLH        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10))\r
+#define I20SCLL        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14))\r
+#define I20CONCLR      (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18))\r
+\r
+/* I2C Interface 1 */\r
+#define I2C1_BASE_ADDR         0x4005C000\r
+#define I21CONSET      (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))\r
+#define I21STAT        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))\r
+#define I21DAT         (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))\r
+#define I21ADR         (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C))\r
+#define I21SCLH        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10))\r
+#define I21SCLL        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14))\r
+#define I21CONCLR      (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18))\r
+\r
+/* I2C Interface 2 */\r
+#define I2C2_BASE_ADDR         0x400A000\r
+#define I22CONSET      (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00))\r
+#define I22STAT        (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04))\r
+#define I22DAT         (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08))\r
+#define I22ADR         (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C))\r
+#define I22SCLH        (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10))\r
+#define I22SCLL        (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14))\r
+#define I22CONCLR      (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18))\r
+\r
+/* SPI0 (Serial Peripheral Interface 0) */\r
+#define SPI0_BASE_ADDR         0x40020000\r
+#define S0SPCR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00))\r
+#define S0SPSR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04))\r
+#define S0SPDR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08))\r
+#define S0SPCCR        (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C))\r
+#define S0SPINT        (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C))\r
+\r
+/* SSP0 Controller */\r
+#define SSP0_BASE_ADDR         0x40088000\r
+#define SSP0CR0        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00))\r
+#define SSP0CR1        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04))\r
+#define SSP0DR         (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08))\r
+#define SSP0SR         (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C))\r
+#define SSP0CPSR       (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10))\r
+#define SSP0IMSC       (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14))\r
+#define SSP0RIS        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18))\r
+#define SSP0MIS        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C))\r
+#define SSP0ICR        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20))\r
+#define SSP0DMACR      (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24))\r
+\r
+/* SSP1 Controller */\r
+#define SSP1_BASE_ADDR         0x40030000\r
+#define SSP1CR0        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00))\r
+#define SSP1CR1        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04))\r
+#define SSP1DR         (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08))\r
+#define SSP1SR         (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C))\r
+#define SSP1CPSR       (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10))\r
+#define SSP1IMSC       (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14))\r
+#define SSP1RIS        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18))\r
+#define SSP1MIS        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C))\r
+#define SSP1ICR        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20))\r
+#define SSP1DMACR      (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24))\r
+\r
+/* Real Time Clock */\r
+#define RTC_BASE_ADDR          0x40024000\r
+#define RTC_ILR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))\r
+#define RTC_CTC         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04))\r
+#define RTC_CCR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))\r
+#define RTC_CIIR        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C))\r
+#define RTC_AMR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10))\r
+#define RTC_CTIME0      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14))\r
+#define RTC_CTIME1      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18))\r
+#define RTC_CTIME2      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C))\r
+\r
+#define RTC_SEC         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20))\r
+#define RTC_MIN         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24))\r
+#define RTC_HOUR        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28))\r
+#define RTC_DOM         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C))\r
+#define RTC_DOW         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30))\r
+#define RTC_DOY         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34))\r
+#define RTC_MONTH       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38))\r
+#define RTC_YEAR        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C))\r
+\r
+#define RTC_CISS        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40))\r
+#define RTC_GPREG0      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x44))\r
+#define RTC_GPREG1      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x48))\r
+#define RTC_GPREG2      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x4C))\r
+#define RTC_GPREG3      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x50))\r
+#define RTC_GPREG4      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x54))\r
+#define RTC_WAKEUPDIS   (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x58))\r
+#define RTC_PWRCTRL     (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x5C))\r
+\r
+#define RTC_ALSEC       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60))\r
+#define RTC_ALMIN       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64))\r
+#define RTC_ALHOUR      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68))\r
+#define RTC_ALDOM       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C))\r
+#define RTC_ALDOW       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70))\r
+#define RTC_ALDOY       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74))\r
+#define RTC_ALMON       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78))\r
+#define RTC_ALYEAR      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C))\r
+#define RTC_PREINT      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80))\r
+#define RTC_PREFRAC     (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84))\r
+\r
+#define RTC_ILR_RTCCIF  0x00000001
+#define RTC_ILR_RTCALF  0x00000002
+#define RTC_ILR_MASK    0x00000003
+
+#define RTC_CCR_CLKEN   0x00000001
+#define RTC_CCR_CTCRST  0x00000002
+#define RTC_CCR_TEST    0x0000000c
+#define RTC_CCR_CLKSRC  0x00000010
+
+#define RTC_CIIR_IMSEC  0x00000001
+#define RTC_CIIR_IMMIN  0x00000002
+#define RTC_CIIR_IMHOUR 0x00000004
+#define RTC_CIIR_IMDOM  0x00000008
+#define RTC_CIIR_IMDOW  0x00000010
+#define RTC_CIIR_IMDOY  0x00000020
+#define RTC_CIIR_IMMON  0x00000040
+#define RTC_CIIR_IMYEAR 0x00000080
+#define RTC_CIIR_IMMASK 0x000000FF
+
+#define RTC_AMR_AMRSEC  0x00000001
+#define RTC_AMR_AMRMIN  0x00000002
+#define RTC_AMR_AMRHOUR 0x00000004
+#define RTC_AMR_AMRDOM  0x00000008
+#define RTC_AMR_AMRDOW  0x00000010
+#define RTC_AMR_AMRDOY  0x00000020
+#define RTC_AMR_AMRMON  0x00000040
+#define RTC_AMR_AMRYEAR 0x00000080
+#define RTC_AMR_AMRMASK 0x000000FF
+
+typedef struct __attribute__ ((packed)) 
+{
+  union
+  {
+    struct
+    {
+      unsigned int counter   : 14;
+      unsigned int rsvd15_31 : 18;
+    };
+
+    unsigned int i;
+  };
+}
+rtcCTC_t;
+
+typedef struct __attribute__ ((packed)) 
+{
+  union
+  {
+    struct 
+    {
+      unsigned int seconds   : 6;
+      unsigned int rsvd7_6   : 2;
+      unsigned int minutes   : 6;
+      unsigned int rsvd14_15 : 2;
+      unsigned int hours     : 5;
+      unsigned int rsvd21_23 : 3;
+      unsigned int dow       : 3;
+      unsigned int rsvd27_31 : 5;
+    };
+
+    unsigned int i;
+  };
+}
+rtcCTIME0_t;
+
+typedef struct __attribute__ ((packed)) 
+{
+  union
+  {
+    struct
+    {
+      unsigned int dom       : 5;
+      unsigned int rsvd5_7   : 3;
+      unsigned int month     : 4;
+      unsigned int rsvd12_15 : 4;
+      unsigned int year      : 12;
+      unsigned int rsvd28_31 : 4;
+    };
+
+    unsigned int i;
+  };
+}
+rtcCTIME1_t;
+
+typedef struct __attribute__ ((packed)) 
+{
+  union
+  {
+    struct 
+    {
+      unsigned int doy       : 12;
+      unsigned int rsvd12_31 : 20;
+    };
+
+    unsigned int i;
+  };
+}
+rtcCTIME2_t;
+\r
+/* A/D Converter 0 (AD0) */\r
+#define AD0_BASE_ADDR          0x40034000\r
+#define AD0CR          (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))\r
+#define AD0GDR         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))\r
+#define AD0INTEN       (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C))\r
+#define AD0DR0         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10))\r
+#define AD0DR1         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14))\r
+#define AD0DR2         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18))\r
+#define AD0DR3         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C))\r
+#define AD0DR4         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20))\r
+#define AD0DR5         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24))\r
+#define AD0DR6         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28))\r
+#define AD0DR7         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C))\r
+#define AD0STAT        (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30))\r
+\r
+/* D/A Converter */\r
+#define DAC_BASE_ADDR          0x4008C000\r
+#define DACR           (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00))\r
+\r
+/* Watchdog */\r
+#define WDG_BASE_ADDR          0x40000000\r
+#define WDMOD          (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00))\r
+#define WDTC           (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04))\r
+#define WDFEED         (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08))\r
+#define WDTV           (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C))\r
+#define WDCLKSEL       (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10))\r
+\r
+/* CAN CONTROLLERS AND ACCEPTANCE FILTER */\r
+#define CAN_ACCEPT_BASE_ADDR           0x4003C000\r
+#define CAN_AFMR               (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00))      \r
+#define CAN_SFF_SA             (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04))      \r
+#define CAN_SFF_GRP_SA         (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08))\r
+#define CAN_EFF_SA             (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C))\r
+#define CAN_EFF_GRP_SA         (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10))      \r
+#define CAN_EOT                (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14))\r
+#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18))     \r
+#define CAN_LUT_ERR    (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C))\r
+\r
+#define CAN_CENTRAL_BASE_ADDR          0xE0040000      \r
+#define CAN_TX_SR      (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00))     \r
+#define CAN_RX_SR      (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04))     \r
+#define CAN_MSR        (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08))\r
+\r
+#define CAN1_BASE_ADDR         0x40044000\r
+#define CAN1MOD        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00))    \r
+#define CAN1CMR        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04))    \r
+#define CAN1GSR        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08))    \r
+#define CAN1ICR        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C))    \r
+#define CAN1IER        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10))\r
+#define CAN1BTR        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14))    \r
+#define CAN1EWL        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18))    \r
+#define CAN1SR                 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C))    \r
+#define CAN1RFS        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20))    \r
+#define CAN1RID        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24))\r
+#define CAN1RDA        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28))    \r
+#define CAN1RDB        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C))\r
+       \r
+#define CAN1TFI1       (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30))    \r
+#define CAN1TID1       (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34))    \r
+#define CAN1TDA1       (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38))\r
+#define CAN1TDB1       (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C))    \r
+#define CAN1TFI2       (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40))    \r
+#define CAN1TID2       (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44))    \r
+#define CAN1TDA2       (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48))    \r
+#define CAN1TDB2       (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C))\r
+#define CAN1TFI3       (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50))    \r
+#define CAN1TID3       (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54))    \r
+#define CAN1TDA3       (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58))    \r
+#define CAN1TDB3       (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C))\r
+\r
+#define CAN2_BASE_ADDR         0x40048000\r
+#define CAN2MOD        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00))    \r
+#define CAN2CMR        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04))    \r
+#define CAN2GSR        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08))    \r
+#define CAN2ICR        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C))    \r
+#define CAN2IER        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10))\r
+#define CAN2BTR        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14))    \r
+#define CAN2EWL        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18))    \r
+#define CAN2SR                 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C))    \r
+#define CAN2RFS        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20))    \r
+#define CAN2RID        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24))\r
+#define CAN2RDA        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28))    \r
+#define CAN2RDB        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C))\r
+       \r
+#define CAN2TFI1       (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30))    \r
+#define CAN2TID1       (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34))    \r
+#define CAN2TDA1       (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38))\r
+#define CAN2TDB1       (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C))    \r
+#define CAN2TFI2       (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40))    \r
+#define CAN2TID2       (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44))    \r
+#define CAN2TDA2       (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48))    \r
+#define CAN2TDB2       (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C))\r
+#define CAN2TFI3       (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50))    \r
+#define CAN2TID3       (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54))    \r
+#define CAN2TDA3       (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58))    \r
+#define CAN2TDB3       (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C))\r
+\r
+/* I2S Interface Controller (I2S) */\r
+#define I2S_BASE_ADDR          0x400A8000\r
+#define I2S_DAO        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00))\r
+#define I2S_DAI        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04))\r
+#define I2S_TX_FIFO    (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08))\r
+#define I2S_RX_FIFO    (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C))\r
+#define I2S_STATE      (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10))\r
+#define I2S_DMA1       (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14))\r
+#define I2S_DMA2       (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18))\r
+#define I2S_IRQ        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C))\r
+#define I2S_TXRATE     (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20))\r
+#define I2S_RXRATE     (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24))\r
+\r
+/* General-purpose DMA Controller */\r
+#define DMA_BASE_ADDR          0x50004000\r
+#define GPDMA_INT_STAT         (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000))\r
+#define GPDMA_INT_TCSTAT       (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004))\r
+#define GPDMA_INT_TCCLR        (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008))\r
+#define GPDMA_INT_ERR_STAT     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C))\r
+#define GPDMA_INT_ERR_CLR      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010))\r
+#define GPDMA_RAW_INT_TCSTAT   (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014))\r
+#define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018))\r
+#define GPDMA_ENABLED_CHNS     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C))\r
+#define GPDMA_SOFT_BREQ        (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020))\r
+#define GPDMA_SOFT_SREQ        (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024))\r
+#define GPDMA_SOFT_LBREQ       (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028))\r
+#define GPDMA_SOFT_LSREQ       (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C))\r
+#define GPDMA_CONFIG           (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030))\r
+#define GPDMA_SYNC             (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034))\r
+\r
+/* DMA channel 0 registers */\r
+#define GPDMA_CH0_SRC      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100))\r
+#define GPDMA_CH0_DEST     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104))\r
+#define GPDMA_CH0_LLI      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108))\r
+#define GPDMA_CH0_CTRL     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C))\r
+#define GPDMA_CH0_CFG      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110))\r
+\r
+/* DMA channel 1 registers */\r
+#define GPDMA_CH1_SRC      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120))\r
+#define GPDMA_CH1_DEST     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124))\r
+#define GPDMA_CH1_LLI      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128))\r
+#define GPDMA_CH1_CTRL     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C))\r
+#define GPDMA_CH1_CFG      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130))\r
+\r
+\r
+/* USB Controller */\r
+#define USB_INT_BASE_ADDR      0x400FC1C0\r
+#define USB_BASE_ADDR          0x5000C200              /* USB Base Address */\r
+\r
+#define USB_INT_STAT    (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00))\r
+\r
+/* USB Device Interrupt Registers */\r
+#define DEV_INT_STAT    (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00))\r
+#define DEV_INT_EN      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04))\r
+#define DEV_INT_CLR     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08))\r
+#define DEV_INT_SET     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C))\r
+#define DEV_INT_PRIO    (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C))\r
+\r
+/* USB Device Endpoint Interrupt Registers */\r
+#define EP_INT_STAT     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30))\r
+#define EP_INT_EN       (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34))\r
+#define EP_INT_CLR      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38))\r
+#define EP_INT_SET      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C))\r
+#define EP_INT_PRIO     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40))\r
+\r
+/* USB Device Endpoint Realization Registers */\r
+#define REALIZE_EP      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44))\r
+#define EP_INDEX        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48))\r
+#define MAXPACKET_SIZE  (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C))\r
+\r
+/* USB Device Command Reagisters */\r
+#define CMD_CODE        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10))\r
+#define CMD_DATA        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14))\r
+\r
+/* USB Device Data Transfer Registers */\r
+#define RX_DATA         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18))\r
+#define TX_DATA         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C))\r
+#define RX_PLENGTH      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20))\r
+#define TX_PLENGTH      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24))\r
+#define USB_CTRL        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28))\r
+\r
+/* USB Device DMA Registers */\r
+#define DMA_REQ_STAT        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50))\r
+#define DMA_REQ_CLR         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54))\r
+#define DMA_REQ_SET         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58))\r
+#define UDCA_HEAD           (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80))\r
+#define EP_DMA_STAT         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84))\r
+#define EP_DMA_EN           (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88))\r
+#define EP_DMA_DIS          (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C))\r
+#define DMA_INT_STAT        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90))\r
+#define DMA_INT_EN          (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94))\r
+#define EOT_INT_STAT        (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0))\r
+#define EOT_INT_CLR         (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4))\r
+#define EOT_INT_SET         (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8))\r
+#define NDD_REQ_INT_STAT    (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC))\r
+#define NDD_REQ_INT_CLR     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0))\r
+#define NDD_REQ_INT_SET     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4))\r
+#define SYS_ERR_INT_STAT    (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8))\r
+#define SYS_ERR_INT_CLR     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC))\r
+#define SYS_ERR_INT_SET     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0))\r
+\r
+/* USB Host and OTG registers are for LPC24xx only */\r
+/* USB Host Controller */\r
+#define USBHC_BASE_ADDR                0x5000C000\r
+#define HC_REVISION         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00))\r
+#define HC_CONTROL          (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04))\r
+#define HC_CMD_STAT         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08))\r
+#define HC_INT_STAT         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C))\r
+#define HC_INT_EN           (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10))\r
+#define HC_INT_DIS          (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14))\r
+#define HC_HCCA             (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18))\r
+#define HC_PERIOD_CUR_ED    (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C))\r
+#define HC_CTRL_HEAD_ED     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20))\r
+#define HC_CTRL_CUR_ED      (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24))\r
+#define HC_BULK_HEAD_ED     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x28))\r
+#define HC_BULK_CUR_ED      (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x2C))\r
+#define HC_DONE_HEAD        (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x30))\r
+#define HC_FM_INTERVAL      (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x34))\r
+#define HC_FM_REMAINING     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x38))\r
+#define HC_FM_NUMBER        (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x3C))\r
+#define HC_PERIOD_START     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x40))\r
+#define HC_LS_THRHLD        (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x44))\r
+#define HC_RH_DESCA         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x48))\r
+#define HC_RH_DESCB         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x4C))\r
+#define HC_RH_STAT          (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x50))\r
+#define HC_RH_PORT_STAT1    (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x54))\r
+#define HC_RH_PORT_STAT2    (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58))\r
+\r
+/* USB OTG Controller */\r
+#define USBOTG_BASE_ADDR        0x5000C100\r
+#define OTG_INT_STAT        (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00))\r
+#define OTG_INT_EN          (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04))\r
+#define OTG_INT_SET         (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08))\r
+#define OTG_INT_CLR         (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C))\r
+/* On LPC17xx, the name is USBPortSel */ \r
+#define OTG_STAT_CTRL       (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10))\r
+#define OTG_TIMER           (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14))\r
+\r
+#define USBOTG_I2C_BASE_ADDR   0x5000C300\r
+#define OTG_I2C_RX          (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))\r
+#define OTG_I2C_TX          (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))\r
+#define OTG_I2C_STS         (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04))\r
+#define OTG_I2C_CTL         (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x08))\r
+#define OTG_I2C_CLKHI       (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C))\r
+#define OTG_I2C_CLKLO       (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10))\r
+\r
+/* On LPC17xx, the names are USBClkCtrl and USBClkSt */\r
+#define USBOTG_CLK_BASE_ADDR   0x5000CFF0\r
+#define OTG_CLK_CTRL        (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04))\r
+#define OTG_CLK_STAT        (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08))\r
+\r
+/* Note: below three register name convention is for LPC17xx USB device only, match\r
+with the spec. update in USB Device Section. */ \r
+#define USBPortSel          (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10))\r
+#define USBClkCtrl          (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04))\r
+#define USBClkSt            (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08))\r
+\r
+/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */\r
+#define MAC_BASE_ADDR          0x50000000\r
+#define MAC_MAC1            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */\r
+#define MAC_MAC2            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */\r
+#define MAC_IPGT            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */\r
+#define MAC_IPGR            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */\r
+#define MAC_CLRT            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */\r
+#define MAC_MAXF            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */\r
+#define MAC_SUPP            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */\r
+#define MAC_TEST            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */\r
+#define MAC_MCFG            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */\r
+#define MAC_MCMD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */\r
+#define MAC_MADR            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */\r
+#define MAC_MWTD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */\r
+#define MAC_MRDD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */\r
+#define MAC_MIND            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */\r
+\r
+#define MAC_SA0             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */\r
+#define MAC_SA1             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */\r
+#define MAC_SA2             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */\r
+\r
+#define MAC_COMMAND         (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */\r
+#define MAC_STATUS          (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */\r
+#define MAC_RXDESCRIPTOR    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */\r
+#define MAC_RXSTATUS        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */\r
+#define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */\r
+#define MAC_RXPRODUCEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */\r
+#define MAC_RXCONSUMEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */\r
+#define MAC_TXDESCRIPTOR    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */\r
+#define MAC_TXSTATUS        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */\r
+#define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */\r
+#define MAC_TXPRODUCEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */\r
+#define MAC_TXCONSUMEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */\r
+\r
+#define MAC_TSV0            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */\r
+#define MAC_TSV1            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */\r
+#define MAC_RSV             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */\r
+\r
+#define MAC_FLOWCONTROLCNT  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */\r
+#define MAC_FLOWCONTROLSTS  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */\r
+\r
+#define MAC_RXFILTERCTRL    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */\r
+#define MAC_RXFILTERWOLSTS  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */\r
+#define MAC_RXFILTERWOLCLR  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */\r
+\r
+#define MAC_HASHFILTERL     (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */\r
+#define MAC_HASHFILTERH     (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */\r
+\r
+#define MAC_INTSTATUS       (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */\r
+#define MAC_INTENABLE       (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg  */\r
+#define MAC_INTCLEAR        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */\r
+#define MAC_INTSET          (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */\r
+\r
+#define MAC_POWERDOWN       (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */\r
+#define MAC_MODULEID        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */\r
+\r
+\r
+#define FLASHCFG                       (*(volatile unsigned long * ) (0x400F C000))\r
+\r
+#endif  // __LPC17xx_H\r
+\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/Makefile b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/Makefile
new file mode 100644 (file)
index 0000000..dedc053
--- /dev/null
@@ -0,0 +1,207 @@
+#/*\r
+#      FreeRTOS.org V5.2.0 - Copyright (C) 2003-2009 Richard Barry.\r
+#\r
+#      This file is part of the FreeRTOS.org distribution.\r
+#\r
+#      FreeRTOS.org is free software; you can redistribute it and/or modify it \r
+#      under the terms of the GNU General Public License (version 2) as published\r
+#      by the Free Software Foundation and modified by the FreeRTOS exception.\r
+#\r
+#      FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT\r
+#      ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or \r
+#      FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for \r
+#      more details.\r
+#\r
+#      You should have received a copy of the GNU General Public License along \r
+#      with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59 \r
+#      Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
+#\r
+#      A special exception to the GPL is included to allow you to distribute a \r
+#      combined work that includes FreeRTOS.org without being obliged to provide\r
+#      the source code for any proprietary components.  See the licensing section\r
+#      of http://www.FreeRTOS.org for full details.\r
+#\r
+#\r
+#      ***************************************************************************\r
+#      *                                                                         *\r
+#      * Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *\r
+#      *                                                                         *\r
+#      * This is a concise, step by step, 'hands on' guide that describes both   *\r
+#      * general multitasking concepts and FreeRTOS specifics. It presents and   *\r
+#      * explains numerous examples that are written using the FreeRTOS API.     *\r
+#      * Full source code for all the examples is provided in an accompanying    *\r
+#      * .zip file.                                                              *\r
+#      *                                                                         *\r
+#      ***************************************************************************\r
+#\r
+#      1 tab == 4 spaces!\r
+#\r
+#      Please ensure to read the configuration and relevant port sections of the\r
+#      online documentation.\r
+#\r
+#      http://www.FreeRTOS.org - Documentation, latest information, license and\r
+#      contact details.\r
+#\r
+#      http://www.SafeRTOS.com - A version that is certified for use in safety\r
+#      critical systems.\r
+#\r
+#      http://www.OpenRTOS.com - Commercial support, development, porting,\r
+#      licensing and training services.\r
+#*/\r
+\r
+RM := rm -rf\r
+\r
+# Set the optimisation level - this should be set to 0, 1, 2, 3 or s (s for size).\r
+OPTIM=0\r
+\r
+# Set the debug level\r
+DEBUG=-g3\r
+\r
+###############################################################################\r
+# List the directories that contain files to be built.\r
+###############################################################################\r
+\r
+# These two directories contain the FreeRTOS.org kernel source files.\r
+FREERTOS_SOURCE_DIR=./../../../Source\r
+PORT_SOURCE_DIR=./../../../Source/portable/GCC/ARM_CM3\r
+\r
+# This directory contains the standard demo files that get included in every\r
+# FreeRTOS.org demo.  They define tasks that demonstrate the API usage and \r
+# test the FreeRTOS.org port.\r
+COMMON_DEMO_SOURCE_DIR=./../../Common/Minimal\r
+\r
+# The uIP stack source files.\r
+uIP_ROOT_DIR=./../../Common/ethernet/uIP/uip-1.0/uip\r
+\r
+VPATH=         $(FREERTOS_SOURCE_DIR) : \\r
+                       $(PORT_SOURCE_DIR) : \\r
+                       $(COMMON_DEMO_SOURCE_DIR) : \\r
+                       $(FREERTOS_SOURCE_DIR)/portable/MemMang : \\r
+                       $(uIP_ROOT_DIR) : \\r
+                       . : \\r
+                       ./webserver : \\r
+                       ./LCD\r
+\r
+\r
+###############################################################################\r
+# Define a few constants to be used during the build.\r
+###############################################################################\r
+\r
+OUTPUT_DIR=./bin\r
+OUTPUT_FILENAME=RTOSDemo.axf\r
+CC=arm-none-eabi-gcc\r
+OBJCOPY=arm-none-eabi-objcopy\r
+LINKER_SCRIPT=rtosdemo_lpc1766.ld\r
+\r
+###############################################################################\r
+# List the files to include in the build.  These files will be located from the\r
+# VPATH defined above.\r
+###############################################################################\r
+\r
+# The FreeRTOS.org source files.\r
+FreeRTOS_OBJS=                 $(OUTPUT_DIR)/port.o \\r
+                                               $(OUTPUT_DIR)/list.o \\r
+                                               $(OUTPUT_DIR)/tasks.o \\r
+                                               $(OUTPUT_DIR)/queue.o \\r
+                                               $(OUTPUT_DIR)/heap_2.o\r
+\r
+# The demo app source files.\r
+Demo_OBJS=                             $(OUTPUT_DIR)/main.o \\r
+                                               $(OUTPUT_DIR)/BlockQ.o \\r
+                                               $(OUTPUT_DIR)/death.o \\r
+                                               $(OUTPUT_DIR)/integer.o \\r
+                                               $(OUTPUT_DIR)/PollQ.o \\r
+                                               $(OUTPUT_DIR)/semtest.o \\r
+                                               $(OUTPUT_DIR)/GenQTest.o \\r
+                                               $(OUTPUT_DIR)/QPeek.o \\r
+                                               $(OUTPUT_DIR)/recmutex.o \\r
+                                               $(OUTPUT_DIR)/portlcd.o \\r
+                                               $(OUTPUT_DIR)/blocktim.o \\r
+                                               $(OUTPUT_DIR)/printf-stdarg.o \\r
+                                               $(OUTPUT_DIR)/cr_startup_nxp_cm3.o \\r
+                                               $(OUTPUT_DIR)/syscalls.o # This is just a dummy.\r
+                                               \r
+# The TCP/IP and WEB server files.\r
+WEB_OBJS=                              $(OUTPUT_DIR)/uip_arp.o \\r
+                                               $(OUTPUT_DIR)/psock.o \\r
+                                               $(OUTPUT_DIR)/timer.o \\r
+                                               $(OUTPUT_DIR)/uip.o \\r
+                                               $(OUTPUT_DIR)/uIP_Task.o \\r
+                                               $(OUTPUT_DIR)/emac.o \\r
+                                               $(OUTPUT_DIR)/httpd.o \\r
+                                               $(OUTPUT_DIR)/httpd-cgi.o \\r
+                                               $(OUTPUT_DIR)/httpd-fs.o \\r
+                                               $(OUTPUT_DIR)/http-strings.o\r
+\r
+\r
+\r
+OBJS = $(FreeRTOS_OBJS) $(Demo_OBJS) $(WEB_OBJS)\r
+                       \r
+C_DEPS = $(OBJS:.o=.d)\r
+\r
+INCLUDE_PATHS= -I"$(FREERTOS_SOURCE_DIR)/include" \\r
+                               -I"include" \\r
+                               -I"$(COMMON_DEMO_SOURCE_DIR)/../include" \\r
+                               -I"$(PORT_SOURCE_DIR)" \\r
+                               -I"$(uIP_ROOT_DIR)" \\r
+                               -I./LCD \\r
+                               -I./webserver \\r
+                               -I.\r
+\r
+CFLAGS=                $(INCLUDE_PATHS) \\r
+                       -O$(OPTIM) \\r
+                       -mthumb \\r
+                       -mcpu=cortex-m3 \\r
+                       -fno-builtin \\r
+                       -D PACK_STRUCT_END=__attribute\(\(packed\)\) \\r
+                       -D ALIGN_STRUCT_END=__attribute\(\(aligned\(4\)\)\)     \\r
+                       -fno-strict-aliasing \\r
+                       $(DEBUG) \\r
+                       -Wall \\r
+                       -c \\r
+                       -ffunction-sections \\r
+                       -fdata-sections \\r
+                       -fmessage-length=0 \\r
+                       -funsigned-char \\r
+                       -Wextra \\r
+                       -MMD \\r
+                       -MP \\r
+                       -MF"$(@:%.o=%.d)" \\r
+                       -MT"$(@:%.o=%.d)"\r
+\r
+ASFLAGS=       \r
+\r
+LIBS=\r
+\r
+# Add inputs and outputs from these tool invocations to the build variables \r
+\r
+# All Target\r
+all: $(OUTPUT_DIR)/$(OUTPUT_FILENAME)\r
+\r
+# Tool invocations \r
+$(OUTPUT_DIR)/$(OUTPUT_FILENAME): $(OBJS)\r
+       $(CC) -nostdlib -mthumb -nostartfiles --no-gc-sections -Xlinker -Map=$(OUTPUT_DIR)/output.map -mcpu=$(CPU) -T $(LINKER_SCRIPT) -o"$(OUTPUT_DIR)/$(OUTPUT_FILENAME)"  $(OBJS) $(USER_OBJS) $(LIBS)\r
+\r
+$(OUTPUT_DIR)/%.o: %.c Makefile FreeRTOSConfig.h\r
+       $(CC) $(CFLAGS) -o"$@" "$<"\r
+\r
+$(OUTPUT_DIR)/%.o: %.S\r
+       $(AS) $(ASFLAGS) -o"$@" "$<"\r
+\r
+# Other Targets\r
+clean:\r
+       -$(RM) $(OBJS) $(C_DEPS) $(EXECUTABLES) $(OUTPUT_DIR)/$(OUTPUT_FILENAME)\r
+       -@echo ' '\r
+\r
+#\r
+# The rule to create the target directory\r
+#\r
+$(OUTPUT_DIR):\r
+       @mkdir $(OUTPUT_DIR)\r
+\r
+\r
+.PHONY: all clean dependents\r
+.SECONDARY: post-build\r
+\r
+-include $(wildcard $(OUTPUT_DIR)/*.d) __dummy__\r
+\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/core_cm3.h b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/core_cm3.h
new file mode 100644 (file)
index 0000000..b6f9696
--- /dev/null
@@ -0,0 +1,1367 @@
+/******************************************************************************\r
+ * @file:    core_cm3.h\r
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version: V1.20\r
+ * @date:    22. May 2009\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CM3_CORE_H__\r
+#define __CM3_CORE_H__\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB   (0x20)                                                       /*!< [15:0]  CMSIS HAL sub version  */\r
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */\r
+\r
+#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */\r
+\r
+/**\r
+ *  Lint configuration \n\r
+ *  ----------------------- \n\r
+ *\r
+ *  The following Lint messages will be suppressed and not shown: \n\r
+ *  \n\r
+ *    --- Error 10: --- \n\r
+ *    register uint32_t __regBasePri         __asm("basepri"); \n\r
+ *    Error 10: Expecting ';' \n\r
+ *     \n\r
+ *    --- Error 530: --- \n\r
+ *    return(__regBasePri); \n\r
+ *    Warning 530: Symbol '__regBasePri' (line 264) not initialized \n\r
+ *     \n\r
+ *    --- Error 550: --- \n\r
+ *      __regBasePri = (basePri & 0x1ff); \n\r
+ *    } \n\r
+ *    Warning 550: Symbol '__regBasePri' (line 271) not accessed \n\r
+ *     \n\r
+ *    --- Error 754: --- \n\r
+ *    uint32_t RESERVED0[24]; \n\r
+ *    Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n\r
+ *     \n\r
+ *    --- Error 750: --- \n\r
+ *    #define __CM3_CORE_H__ \n\r
+ *    Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n\r
+ *     \n\r
+ *    --- Error 528: --- \n\r
+ *    static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
+ *    Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n\r
+ *     \n\r
+ *    --- Error 751: --- \n\r
+ *    } InterruptType_Type; \n\r
+ *    Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n\r
+ * \n\r
+ * \n\r
+ *    Note:  To re-enable a Message, insert a space before 'lint' * \n\r
+ *\r
+ */\r
+\r
+/*lint -save */\r
+/*lint -e10  */\r
+/*lint -e530 */\r
+/*lint -e550 */\r
+/*lint -e754 */\r
+/*lint -e750 */\r
+/*lint -e528 */\r
+/*lint -e751 */\r
+\r
+\r
+#include <stdint.h>                           /* Include standard types */\r
+\r
+#if defined (__ICCARM__)\r
+  #include <intrinsics.h>                     /* IAR Intrinsics   */\r
+#endif\r
+\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+\r
+\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+\r
+#ifdef __cplusplus\r
+#define     __I     volatile                  /*!< defines 'read only' permissions      */\r
+#else\r
+#define     __I     volatile const            /*!< defines 'read only' permissions      */\r
+#endif\r
+#define     __O     volatile                  /*!< defines 'write only' permissions     */\r
+#define     __IO    volatile                  /*!< defines 'read / write' permissions   */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+ ******************************************************************************/\r
+\r
+\r
+/* System Reset */\r
+#define NVIC_VECTRESET              0         /*!< Vector Reset Bit             */\r
+#define NVIC_SYSRESETREQ            2         /*!< System Reset Request         */\r
+#define NVIC_AIRCR_VECTKEY    (0x5FA << 16)   /*!< AIRCR Key for write access   */\r
+#define NVIC_AIRCR_ENDIANESS        15        /*!< Endianess                    */\r
+\r
+/* Core Debug */\r
+#define CoreDebug_DEMCR_TRCENA (1 << 24)      /*!< DEMCR TRCENA enable          */\r
+#define ITM_TCR_ITMENA              1         /*!< ITM enable                   */\r
+\r
+\r
+\r
+\r
+/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */\r
+typedef struct\r
+{\r
+  __IO uint32_t ISER[8];                      /*!< Interrupt Set Enable Register            */\r
+       uint32_t RESERVED0[24];\r
+  __IO uint32_t ICER[8];                      /*!< Interrupt Clear Enable Register          */\r
+       uint32_t RSERVED1[24];\r
+  __IO uint32_t ISPR[8];                      /*!< Interrupt Set Pending Register           */\r
+       uint32_t RESERVED2[24];\r
+  __IO uint32_t ICPR[8];                      /*!< Interrupt Clear Pending Register         */\r
+       uint32_t RESERVED3[24];\r
+  __IO uint32_t IABR[8];                      /*!< Interrupt Active bit Register            */\r
+       uint32_t RESERVED4[56];\r
+  __IO uint8_t  IP[240];                      /*!< Interrupt Priority Register, 8Bit wide   */\r
+       uint32_t RESERVED5[644];\r
+  __O  uint32_t STIR;                         /*!< Software Trigger Interrupt Register      */\r
+}  NVIC_Type;\r
+\r
+\r
+/* memory mapping struct for System Control Block */\r
+typedef struct\r
+{\r
+  __I  uint32_t CPUID;                        /*!< CPU ID Base Register                                     */\r
+  __IO uint32_t ICSR;                         /*!< Interrupt Control State Register                         */\r
+  __IO uint32_t VTOR;                         /*!< Vector Table Offset Register                             */\r
+  __IO uint32_t AIRCR;                        /*!< Application Interrupt / Reset Control Register           */\r
+  __IO uint32_t SCR;                          /*!< System Control Register                                  */\r
+  __IO uint32_t CCR;                          /*!< Configuration Control Register                           */\r
+  __IO uint8_t  SHP[12];                      /*!< System Handlers Priority Registers (4-7, 8-11, 12-15)    */\r
+  __IO uint32_t SHCSR;                        /*!< System Handler Control and State Register                */\r
+  __IO uint32_t CFSR;                         /*!< Configurable Fault Status Register                       */\r
+  __IO uint32_t HFSR;                         /*!< Hard Fault Status Register                               */\r
+  __IO uint32_t DFSR;                         /*!< Debug Fault Status Register                              */\r
+  __IO uint32_t MMFAR;                        /*!< Mem Manage Address Register                              */\r
+  __IO uint32_t BFAR;                         /*!< Bus Fault Address Register                               */\r
+  __IO uint32_t AFSR;                         /*!< Auxiliary Fault Status Register                          */\r
+  __I  uint32_t PFR[2];                       /*!< Processor Feature Register                               */\r
+  __I  uint32_t DFR;                          /*!< Debug Feature Register                                   */\r
+  __I  uint32_t ADR;                          /*!< Auxiliary Feature Register                               */\r
+  __I  uint32_t MMFR[4];                      /*!< Memory Model Feature Register                            */\r
+  __I  uint32_t ISAR[5];                      /*!< ISA Feature Register                                     */\r
+} SCB_Type;\r
+\r
+\r
+/* memory mapping struct for SysTick */\r
+typedef struct\r
+{\r
+  __IO uint32_t CTRL;                         /*!< SysTick Control and Status Register */\r
+  __IO uint32_t LOAD;                         /*!< SysTick Reload Value Register       */\r
+  __IO uint32_t VAL;                          /*!< SysTick Current Value Register      */\r
+  __I  uint32_t CALIB;                        /*!< SysTick Calibration Register        */\r
+} SysTick_Type;\r
+\r
+\r
+/* memory mapping structur for ITM */\r
+typedef struct\r
+{\r
+  __O  union  \r
+  {\r
+    __O  uint8_t    u8;                       /*!< ITM Stimulus Port 8-bit               */\r
+    __O  uint16_t   u16;                      /*!< ITM Stimulus Port 16-bit              */\r
+    __O  uint32_t   u32;                      /*!< ITM Stimulus Port 32-bit              */\r
+  }  PORT [32];                               /*!< ITM Stimulus Port Registers           */\r
+       uint32_t RESERVED0[864];\r
+  __IO uint32_t TER;                          /*!< ITM Trace Enable Register             */\r
+       uint32_t RESERVED1[15];\r
+  __IO uint32_t TPR;                          /*!< ITM Trace Privilege Register          */\r
+       uint32_t RESERVED2[15];\r
+  __IO uint32_t TCR;                          /*!< ITM Trace Control Register            */\r
+       uint32_t RESERVED3[29];\r
+  __IO uint32_t IWR;                          /*!< ITM Integration Write Register        */\r
+  __IO uint32_t IRR;                          /*!< ITM Integration Read Register         */\r
+  __IO uint32_t IMCR;                         /*!< ITM Integration Mode Control Register */\r
+       uint32_t RESERVED4[43];\r
+  __IO uint32_t LAR;                          /*!< ITM Lock Access Register              */\r
+  __IO uint32_t LSR;                          /*!< ITM Lock Status Register              */\r
+       uint32_t RESERVED5[6];\r
+  __I  uint32_t PID4;                         /*!< ITM Product ID Registers              */\r
+  __I  uint32_t PID5;\r
+  __I  uint32_t PID6;\r
+  __I  uint32_t PID7;\r
+  __I  uint32_t PID0;\r
+  __I  uint32_t PID1;\r
+  __I  uint32_t PID2;\r
+  __I  uint32_t PID3;\r
+  __I  uint32_t CID0;\r
+  __I  uint32_t CID1;\r
+  __I  uint32_t CID2;\r
+  __I  uint32_t CID3;\r
+} ITM_Type;\r
+\r
+\r
+/* memory mapped struct for Interrupt Type */\r
+typedef struct\r
+{\r
+       uint32_t RESERVED0;\r
+  __I  uint32_t ICTR;                         /*!< Interrupt Control Type Register  */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+  __IO uint32_t ACTLR;                        /*!< Auxiliary Control Register       */\r
+#else\r
+       uint32_t RESERVED1;\r
+#endif\r
+} InterruptType_Type;\r
+\r
+\r
+/* Memory Protection Unit */\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+typedef struct\r
+{\r
+  __I  uint32_t TYPE;                         /*!< MPU Type Register                               */\r
+  __IO uint32_t CTRL;                         /*!< MPU Control Register                            */\r
+  __IO uint32_t RNR;                          /*!< MPU Region RNRber Register                      */\r
+  __IO uint32_t RBAR;                         /*!< MPU Region Base Address Register                */\r
+  __IO uint32_t RASR;                         /*!< MPU Region Attribute and Size Register          */\r
+  __IO uint32_t RBAR_A1;                      /*!< MPU Alias 1 Region Base Address Register        */\r
+  __IO uint32_t RASR_A1;                      /*!< MPU Alias 1 Region Attribute and Size Register  */\r
+  __IO uint32_t RBAR_A2;                      /*!< MPU Alias 2 Region Base Address Register        */\r
+  __IO uint32_t RASR_A2;                      /*!< MPU Alias 2 Region Attribute and Size Register  */\r
+  __IO uint32_t RBAR_A3;                      /*!< MPU Alias 3 Region Base Address Register        */\r
+  __IO uint32_t RASR_A3;                      /*!< MPU Alias 3 Region Attribute and Size Register  */\r
+} MPU_Type;\r
+#endif\r
+\r
+\r
+/* Core Debug Register */\r
+typedef struct\r
+{\r
+  __IO uint32_t DHCSR;                        /*!< Debug Halting Control and Status Register       */\r
+  __O  uint32_t DCRSR;                        /*!< Debug Core Register Selector Register           */\r
+  __IO uint32_t DCRDR;                        /*!< Debug Core Register Data Register               */\r
+  __IO uint32_t DEMCR;                        /*!< Debug Exception and Monitor Control Register    */\r
+} CoreDebug_Type;\r
+\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address    */\r
+#define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                     */\r
+#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address              */\r
+#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address                 */\r
+#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                    */\r
+#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address    */\r
+\r
+#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register              */\r
+#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct             */\r
+#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct         */\r
+#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct            */\r
+#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct             */\r
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct      */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+  #define MPU_BASE          (SCS_BASE +  0x0D90)                      /*!< Memory Protection Unit               */\r
+  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit               */\r
+#endif\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+\r
+#if defined ( __CC_ARM   )\r
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */\r
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler           */\r
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined   (  __GNUC__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */\r
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */\r
+\r
+#elif defined   (  __TASKING__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler          */\r
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler       */\r
+\r
+#endif\r
+\r
+\r
+/* ###################  Compiler specific Intrinsics  ########################### */\r
+\r
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#define __enable_fault_irq                __enable_fiq\r
+#define __disable_fault_irq               __disable_fiq\r
+\r
+#define __NOP                             __nop\r
+#define __WFI                             __wfi\r
+#define __WFE                             __wfe\r
+#define __SEV                             __sev\r
+#define __ISB()                           __isb(0)\r
+#define __DSB()                           __dsb(0)\r
+#define __DMB()                           __dmb(0)\r
+#define __REV                             __rev\r
+#define __RBIT                            __rbit\r
+#define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))\r
+#define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))\r
+#define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))\r
+#define __STREXB(value, ptr)              __strex(value, ptr)\r
+#define __STREXH(value, ptr)              __strex(value, ptr)\r
+#define __STREXW(value, ptr)              __strex(value, ptr)\r
+\r
+\r
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
+/* intrinsic void __enable_irq();     */\r
+/* intrinsic void __disable_irq();    */\r
+\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/*\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param  int16_t value to reverse\r
+ * @return int32_t reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief  Remove the exclusive lock created by ldrex\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+extern void __CLREX(void);\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+ * \r
+ * @param  none\r
+ * @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+#else  /* (__ARMCC_VERSION >= 400000)  */\r
+\r
+\r
+/**\r
+ * @brief  Remove the exclusive lock created by ldrex\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+#define __CLREX                           __clrex\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+static __INLINE uint32_t  __get_BASEPRI(void)\r
+{\r
+  register uint32_t __regBasePri         __ASM("basepri");\r
+  return(__regBasePri);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+  register uint32_t __regBasePri         __ASM("basepri");\r
+  __regBasePri = (basePri & 0x1ff);\r
+}\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+  register uint32_t __regPriMask         __ASM("primask");\r
+  return(__regPriMask);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  register uint32_t __regPriMask         __ASM("primask");\r
+  __regPriMask = (priMask);\r
+}\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+  register uint32_t __regFaultMask       __ASM("faultmask");\r
+  return(__regFaultMask);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  register uint32_t __regFaultMask       __ASM("faultmask");\r
+  __regFaultMask = (faultMask & 1);\r
+}\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+ * \r
+ * @param  none\r
+ * @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+  register uint32_t __regControl         __ASM("control");\r
+  return(__regControl);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+  register uint32_t __regControl         __ASM("control");\r
+  __regControl = control;\r
+}\r
+\r
+#endif /* __ARMCC_VERSION  */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */\r
+#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */\r
+\r
+static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }\r
+\r
+#define __NOP                                     __no_operation()          /*!< no operation intrinsic in IAR Compiler */ \r
+static __INLINE  void __WFI()                     { __ASM ("wfi"); }\r
+static __INLINE  void __WFE()                     { __ASM ("wfe"); }\r
+static __INLINE  void __SEV()                     { __ASM ("sev"); }\r
+static __INLINE  void __CLREX()                   { __ASM ("clrex"); }\r
+\r
+/* intrinsic void __ISB(void)                                     */\r
+/* intrinsic void __DSB(void)                                     */\r
+/* intrinsic void __DMB(void)                                     */\r
+/* intrinsic void __set_PRIMASK();                                */\r
+/* intrinsic void __get_PRIMASK();                                */\r
+/* intrinsic void __set_FAULTMASK();                              */\r
+/* intrinsic void __get_FAULTMASK();                              */\r
+/* intrinsic uint32_t __REV(uint32_t value);                      */\r
+/* intrinsic uint32_t __REVSH(uint32_t value);                    */\r
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
+/* intrinsic unsigned long __LDREX(unsigned long *);              */\r
+\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief  Reverse bit order of value\r
+ *\r
+ * @param  uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint8_t* address\r
+ * @return uint8_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint16_t* address\r
+ * @return uint16_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint32_t* address\r
+ * @return uint32_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint8_t *address\r
+ * @param  uint8_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint16_t *address\r
+ * @param  uint16_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint32_t *address\r
+ * @param  uint32_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }\r
+static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }\r
+\r
+static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }\r
+\r
+static __INLINE void __NOP()                      { __ASM volatile ("nop"); }\r
+static __INLINE void __WFI()                      { __ASM volatile ("wfi"); }\r
+static __INLINE void __WFE()                      { __ASM volatile ("wfe"); }\r
+static __INLINE void __SEV()                      { __ASM volatile ("sev"); }\r
+static __INLINE void __ISB()                      { __ASM volatile ("isb"); }\r
+static __INLINE void __DSB()                      { __ASM volatile ("dsb"); }\r
+static __INLINE void __DMB()                      { __ASM volatile ("dmb"); }\r
+static __INLINE void __CLREX()                    { __ASM volatile ("clrex"); }\r
+\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+extern uint32_t  __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+* \r
+*  @param  none\r
+*  @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+/**\r
+ * @brief  Reverse byte order in integer value\r
+ *\r
+ * @param  uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+extern uint32_t __REV(uint32_t value);\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/*\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param  int16_t value to reverse\r
+ * @return int32_t reversed value\r
+ *\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+/**\r
+ * @brief  Reverse bit order of value\r
+ *\r
+ * @param  uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint8_t* address\r
+ * @return uint8_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint16_t* address\r
+ * @return uint16_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint32_t* address\r
+ * @return uint32_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint8_t *address\r
+ * @param  uint8_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint16_t *address\r
+ * @param  uint16_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint32_t *address\r
+ * @param  uint32_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+\r
+\r
+/**\r
+ * @brief  Set the Priority Grouping in NVIC Interrupt Controller\r
+ *\r
+ * @param  uint32_t priority_grouping is priority grouping field\r
+ * @return none \r
+ *\r
+ * Set the priority grouping field using the required unlock sequence.\r
+ * The parameter priority_grouping is assigned to the field \r
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+  uint32_t reg_value;\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */\r
+  \r
+  reg_value  = SCB->AIRCR;                                                    /* read old register configuration    */\r
+  reg_value &= ~((0xFFFFU << 16) | (0x0F << 8));                              /* clear bits to change               */\r
+  reg_value  = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8)));  /* Insert write key and priorty group */\r
+  SCB->AIRCR = reg_value;\r
+}\r
+\r
+/**\r
+ * @brief  Get the Priority Grouping from NVIC Interrupt Controller\r
+ *\r
+ * @param  none\r
+ * @return uint32_t   priority grouping field \r
+ *\r
+ * Get the priority grouping from NVIC Interrupt Controller.\r
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+  return ((SCB->AIRCR >> 8) & 0x07);                                          /* read priority grouping field */\r
+}\r
+\r
+/**\r
+ * @brief  Enable Interrupt in NVIC Interrupt Controller\r
+ *\r
+ * @param  IRQn_Type IRQn specifies the interrupt number\r
+ * @return none \r
+ *\r
+ * Enable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief  Disable the interrupt line for external interrupt specified\r
+ * \r
+ * @param  IRQn_Type IRQn is the positive number of the external interrupt\r
+ * @return none\r
+ * \r
+ * Disable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief  Read the interrupt pending bit for a device specific interrupt source\r
+ * \r
+ * @param  IRQn_Type IRQn is the number of the device specifc interrupt\r
+ * @return uint32_t 1 if pending interrupt else 0\r
+ *\r
+ * Read the pending register in NVIC and return 1 if its status is pending, \r
+ * otherwise it returns 0\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+/**\r
+ * @brief  Set the pending bit for an external interrupt\r
+ * \r
+ * @param  IRQn_Type IRQn is the Number of the interrupt\r
+ * @return none\r
+ *\r
+ * Set the pending bit for the specified interrupt.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+/**\r
+ * @brief  Clear the pending bit for an external interrupt\r
+ *\r
+ * @param  IRQn_Type IRQn is the Number of the interrupt\r
+ * @return none\r
+ *\r
+ * Clear the pending bit for the specified interrupt. \r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+/**\r
+ * @brief  Read the active bit for an external interrupt\r
+ *\r
+ * @param  IRQn_Type  IRQn is the Number of the interrupt\r
+ * @return uint32_t   1 if active else 0\r
+ *\r
+ * Read the active register in NVIC and returns 1 if its status is active, \r
+ * otherwise it returns 0.\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+/**\r
+ * @brief  Set the priority for an interrupt\r
+ *\r
+ * @param  IRQn_Type IRQn is the Number of the interrupt\r
+ * @param  priority is the priority for the interrupt\r
+ * @return none\r
+ *\r
+ * Set the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt. \n\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if(IRQn < 0) {\r
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+  else {\r
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts      */\r
+}\r
+\r
+/**\r
+ * @brief  Read the priority for an interrupt\r
+ *\r
+ * @param  IRQn_Type IRQn is the Number of the interrupt\r
+ * @return uint32_t  priority is the priority for the interrupt\r
+ *\r
+ * Read the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * The returned priority value is automatically aligned to the implemented\r
+ * priority bits of the microcontroller.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if(IRQn < 0) {\r
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M3 system interrupts */\r
+  else {\r
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */\r
+}\r
+\r
+\r
+/**\r
+ * @brief  Encode the priority for an interrupt\r
+ *\r
+ * @param  uint32_t PriorityGroup   is the used priority group\r
+ * @param  uint32_t PreemptPriority is the preemptive priority value (starting from 0)\r
+ * @param  uint32_t SubPriority     is the sub priority value (starting from 0)\r
+ * @return uint32_t                    the priority for the interrupt\r
+ *\r
+ * Encode the priority for an interrupt with the given priority group,\r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The returned priority value can be used for NVIC_SetPriority(...) function\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
\r
+  return (\r
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))\r
+         );\r
+}\r
+\r
+\r
+/**\r
+ * @brief  Decode the priority of an interrupt\r
+ *\r
+ * @param  uint32_t   Priority       the priority for the interrupt\r
+ * @param  uint32_t   PrioGroup   is the used priority group\r
+ * @param  uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)\r
+ * @param  uint32_t* pSubPrio     is the sub priority value (starting from 0)\r
+ * @return none\r
+ *\r
+ * Decode an interrupt priority value with the given priority group to \r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The priority value can be retrieved with NVIC_GetPriority(...) function\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+  \r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);\r
+}\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+\r
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
+\r
+/* SysTick constants */\r
+#define SYSTICK_ENABLE              0                                          /* Config-Bit to start or stop the SysTick Timer                         */\r
+#define SYSTICK_TICKINT             1                                          /* Config-Bit to enable or disable the SysTick interrupt                 */\r
+#define SYSTICK_CLKSOURCE           2                                          /* Clocksource has the offset 2 in SysTick Control and Status Register   */\r
+#define SYSTICK_MAXCOUNT       ((1<<24) -1)                                    /* SysTick MaxCount                                                      */\r
+\r
+/**\r
+ * @brief  Initialize and start the SysTick counter and its interrupt.\r
+ *\r
+ * @param  uint32_t ticks is the number of ticks between two interrupts\r
+ * @return  none\r
+ *\r
+ * Initialise the system tick timer and its interrupt and start the\r
+ * system tick timer / counter in free running mode to generate \r
+ * periodical interrupts.\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{ \r
+  if (ticks > SYSTICK_MAXCOUNT)  return (1);                                             /* Reload value impossible */\r
+\r
+  SysTick->LOAD  =  (ticks & SYSTICK_MAXCOUNT) - 1;                                      /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);                            /* set Priority for Cortex-M0 System Interrupts */\r
+  SysTick->VAL   =  (0x00);                                                              /* Load the SysTick Counter Value */\r
+  SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0);                                                                            /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+/* ##################################    Reset function  ############################################ */\r
+\r
+/**\r
+ * @brief  Initiate a system reset request.\r
+ *\r
+ * @param   none\r
+ * @return  none\r
+ *\r
+ * Initialize a system reset request to reset the MCU\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+  SCB->AIRCR  = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */\r
+  __DSB();                                                                             /* Ensure completion of memory access */              \r
+  while(1);                                                                            /* wait until reset */\r
+}\r
+\r
+\r
+/* ##################################    Debug Output  function  ############################################ */\r
+\r
+\r
+/**\r
+ * @brief  Outputs a character via the ITM channel 0\r
+ *\r
+ * @param   uint32_t character to output\r
+ * @return  uint32_t input character\r
+ *\r
+ * The function outputs a character via the ITM channel 0. \r
+ * The function returns when no debugger is connected that has booked the output.  \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+  if (ch == '\n') ITM_SendChar('\r');\r
+  \r
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &&\r
+      (ITM->TCR & ITM_TCR_ITMENA)                  &&\r
+      (ITM->TER & (1UL << 0))  ) \r
+  {\r
+    while (ITM->PORT[0].u32 == 0);\r
+    ITM->PORT[0].u8 = (uint8_t) ch;\r
+  }  \r
+  return (ch);\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CM3_CORE_H__ */\r
+\r
+/*lint -restore */\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/cr_startup_nxp_cm3.c b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/cr_startup_nxp_cm3.c
new file mode 100644 (file)
index 0000000..73367c6
--- /dev/null
@@ -0,0 +1,313 @@
+//*****************************************************************************\r
+//   +--+       \r
+//   | ++----+   \r
+//   +-++    |  \r
+//     |     |  \r
+//   +-+--+  |   \r
+//   | +--+--+  \r
+//   +----+    Copyright (c) 2009 Code Red Technologies Ltd. \r
+//\r
+// cr_startup.c - Startup code for use with Code Red tools on NXP LPC17 family\r
+//\r
+// Software License Agreement\r
+// \r
+// The software is owned by Code Red Technologies and/or its suppliers, and is \r
+// protected under applicable copyright laws.  All rights are reserved.  Any \r
+// use in violation of the foregoing restrictions may subject the user to criminal \r
+// sanctions under applicable laws, as well as to civil liability for the breach \r
+// of the terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+//*****************************************************************************\r
+#define WEAK __attribute__ ((weak))\r
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))\r
+\r
+//*****************************************************************************\r
+//\r
+// Forward declaration of the default handlers.\r
+//\r
+//*****************************************************************************\r
+void Reset_Handler(void);\r
+void ResetISR(void) ALIAS(Reset_Handler);\r
+static void NMI_Handler(void);\r
+static void HardFault_Handler(void);\r
+static void MemManage_Handler(void);\r
+static void BusFault_Handler(void);\r
+static void UsageFault_Handler(void);\r
+static void DebugMon_Handler(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// Forward declaration of the specific IRQ handlers. These are aliased\r
+// to the IntDefaultHandler, which is a 'forever' loop. When the application\r
+// defines a handler (with the same name), this will automatically take \r
+// precedence over these weak definitions\r
+//\r
+//*****************************************************************************\r
+void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void EINT3_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void USB_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+\r
+extern void xPortSysTickHandler(void);\r
+extern void xPortPendSVHandler(void);\r
+extern void vPortSVCHandler( void );\r
+extern void vEMAC_ISR( void );\r
+\r
+\r
+\r
+//*****************************************************************************\r
+//\r
+// The entry point for the C++ library startup\r
+//\r
+//*****************************************************************************\r
+extern WEAK void __libc_init_array(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// The entry point for the application.\r
+// __main() is the entry point for redlib based applications\r
+// main() is the entry point for newlib based applications\r
+//\r
+//*****************************************************************************\r
+extern WEAK void __main(void);\r
+extern WEAK void main(void);\r
+//*****************************************************************************\r
+//\r
+// External declaration for the pointer to the stack top from the Linker Script\r
+//\r
+//*****************************************************************************\r
+extern void _vStackTop;\r
+\r
+//*****************************************************************************\r
+//\r
+// The vector table.\r
+// This relies on the linker script to place at correct location in memory.\r
+//\r
+//*****************************************************************************\r
+__attribute__ ((section(".isr_vector")))\r
+void (* const g_pfnVectors[])(void) =\r
+{\r
+       // Core Level - CM3\r
+       (void *)&_vStackTop,                                    // The initial stack pointer\r
+       Reset_Handler,                                                  // The reset handler\r
+       NMI_Handler,                                                    // The NMI handler\r
+       HardFault_Handler,                                              // The hard fault handler\r
+       MemManage_Handler,                                              // The MPU fault handler\r
+       BusFault_Handler,                                               // The bus fault handler\r
+       UsageFault_Handler,                                             // The usage fault handler\r
+       0,                                                                              // Reserved\r
+       0,                                                                              // Reserved\r
+       0,                                                                              // Reserved\r
+       0,                                                                              // Reserved\r
+           vPortSVCHandler,                        // SVCall handler\r
+       DebugMon_Handler,                                               // Debug monitor handler\r
+       0,                                                                              // Reserved\r
+           xPortPendSVHandler,                     // The PendSV handler\r
+           xPortSysTickHandler,                    // The SysTick handler\r
+\r
+       // Chip Level - LPC17\r
+       WDT_IRQHandler,                                                 // 16, 0x40 - WDT\r
+       TIMER0_IRQHandler,                                              // 17, 0x44 - TIMER0\r
+       TIMER1_IRQHandler,                                              // 18, 0x48 - TIMER1\r
+       TIMER2_IRQHandler,                                              // 19, 0x4c - TIMER2\r
+       TIMER3_IRQHandler,                                              // 20, 0x50 - TIMER3\r
+       UART0_IRQHandler,                                               // 21, 0x54 - UART0\r
+       UART1_IRQHandler,                                               // 22, 0x58 - UART1\r
+       UART2_IRQHandler,                                               // 23, 0x5c - UART2\r
+       UART3_IRQHandler,                                               // 24, 0x60 - UART3\r
+       PWM1_IRQHandler,                                                // 25, 0x64 - PWM1\r
+       I2C0_IRQHandler,                                                // 26, 0x68 - I2C0\r
+       I2C1_IRQHandler,                                                // 27, 0x6c - I2C1\r
+       I2C2_IRQHandler,                                                // 28, 0x70 - I2C2\r
+       SPI_IRQHandler,                                                 // 29, 0x74 - SPI\r
+       SSP0_IRQHandler,                                                // 30, 0x78 - SSP0\r
+       SSP1_IRQHandler,                                                // 31, 0x7c - SSP1\r
+       PLL0_IRQHandler,                                                // 32, 0x80 - PLL0 (Main PLL)\r
+       RTC_IRQHandler,                                                 // 33, 0x84 - RTC\r
+       EINT0_IRQHandler,                                               // 34, 0x88 - EINT0\r
+       EINT1_IRQHandler,                                               // 35, 0x8c - EINT1\r
+       EINT2_IRQHandler,                                               // 36, 0x90 - EINT2\r
+       EINT3_IRQHandler,                                               // 37, 0x94 - EINT3\r
+       ADC_IRQHandler,                                                 // 38, 0x98 - ADC\r
+       BOD_IRQHandler,                                                 // 39, 0x9c - BOD\r
+       USB_IRQHandler,                                                 // 40, 0xA0 - USB\r
+       CAN_IRQHandler,                                                 // 41, 0xa4 - CAN\r
+       DMA_IRQHandler,                                                 // 42, 0xa8 - GP DMA\r
+       I2S_IRQHandler,                                                 // 43, 0xac - I2S\r
+           vEMAC_ISR,                                  // Ethernet.\r
+       RIT_IRQHandler,                                                 // 45, 0xb4 - RITINT\r
+       MCPWM_IRQHandler,                                               // 46, 0xb8 - Motor Control PWM\r
+       QEI_IRQHandler,                                                 // 47, 0xbc - Quadrature Encoder\r
+       PLL1_IRQHandler,                                                // 48, 0xc0 - PLL1 (USB PLL)\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are constructs created by the linker, indicating where the\r
+// the "data" and "bss" segments reside in memory.  The initializers for the\r
+// for the "data" segment resides immediately following the "text" segment.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long _etext;\r
+extern unsigned long _data;\r
+extern unsigned long _edata;\r
+extern unsigned long _bss;\r
+extern unsigned long _ebss;\r
+\r
+//*****************************************************************************\r
+// Reset entry point for your code.\r
+// Sets up a simple runtime environment and initializes the C/C++\r
+// library.\r
+//\r
+//*****************************************************************************\r
+void Reset_Handler(void)\r
+{\r
+    unsigned long *pulSrc, *pulDest;\r
+\r
+    //\r
+    // Copy the data segment initializers from flash to SRAM.\r
+    //\r
+    pulSrc = &_etext;\r
+    for(pulDest = &_data; pulDest < &_edata; )\r
+    {\r
+        *pulDest++ = *pulSrc++;\r
+    }\r
+\r
+    //\r
+    // Zero fill the bss segment.  This is done with inline assembly since this\r
+    // will clear the value of pulDest if it is not kept in a register.\r
+    //\r
+    __asm("    ldr     r0, =_bss\n"\r
+          "    ldr     r1, =_ebss\n"\r
+          "    mov     r2, #0\n"\r
+          "    .thumb_func\n"\r
+          "zero_loop:\n"\r
+          "        cmp     r0, r1\n"\r
+          "        it      lt\n"\r
+          "        strlt   r2, [r0], #4\n"\r
+          "        blt     zero_loop");\r
+\r
+    //\r
+    // Call C++ library initilisation, if present\r
+    //\r
+       if (__libc_init_array)\r
+               __libc_init_array() ;\r
+\r
+       //\r
+       // Call the application's entry point.\r
+       // __main() is the entry point for redlib based applications (which calls main())\r
+       // main() is the entry point for newlib based applications\r
+       //\r
+       if (__main)\r
+               __main() ;\r
+       else\r
+               main() ;\r
+\r
+       //\r
+       // main() shouldn't return, but if it does, we'll just enter an infinite loop \r
+       //\r
+       while (1) {\r
+               ;\r
+       }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a NMI.  This\r
+// simply enters an infinite loop, preserving the system state for examination\r
+// by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void NMI_Handler(void)\r
+{\r
+    while(1)\r
+    {\r
+    }\r
+}\r
+\r
+static void HardFault_Handler(void)\r
+{\r
+    while(0)\r
+    {\r
+    }\r
+}\r
+\r
+static void MemManage_Handler(void)\r
+{\r
+    while(1)\r
+    {\r
+    }\r
+}\r
+\r
+static void BusFault_Handler(void)\r
+{\r
+    while(1)\r
+    {\r
+    }\r
+}\r
+\r
+static void UsageFault_Handler(void)\r
+{\r
+    while(1)\r
+    {\r
+    }\r
+}\r
+\r
+static void DebugMon_Handler(void)\r
+{\r
+    while(1)\r
+    {\r
+    }\r
+}\r
+\r
+\r
+//*****************************************************************************\r
+//\r
+// Processor ends up here if an unexpected interrupt occurs or a handler\r
+// is not present in the application code.\r
+//\r
+//*****************************************************************************\r
+static void IntDefaultHandler(void)\r
+{\r
+    //\r
+    // Go into an infinite loop.\r
+    //\r
+    while(1)\r
+    {\r
+    }\r
+}\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/main.c b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/main.c
new file mode 100644 (file)
index 0000000..1eeff86
--- /dev/null
@@ -0,0 +1,316 @@
+/*\r
+       FreeRTOS.org V5.2.0 - Copyright (C) 2003-2009 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify it \r
+       under the terms of the GNU General Public License (version 2) as published\r
+       by the Free Software Foundation and modified by the FreeRTOS exception.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT\r
+       ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or \r
+       FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for \r
+       more details.\r
+\r
+       You should have received a copy of the GNU General Public License along \r
+       with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59 \r
+       Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
+\r
+       A special exception to the GPL is included to allow you to distribute a \r
+       combined work that includes FreeRTOS.org without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section\r
+       of http://www.FreeRTOS.org for full details.\r
+\r
+\r
+       ***************************************************************************\r
+       *                                                                         *\r
+       * Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *\r
+       *                                                                         *\r
+       * This is a concise, step by step, 'hands on' guide that describes both   *\r
+       * general multitasking concepts and FreeRTOS specifics. It presents and   *\r
+       * explains numerous examples that are written using the FreeRTOS API.     *\r
+       * Full source code for all the examples is provided in an accompanying    *\r
+       * .zip file.                                                              *\r
+       *                                                                         *\r
+       ***************************************************************************\r
+\r
+       1 tab == 4 spaces!\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
+       licensing and training services.\r
+*/\r
+\r
+\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Hardware library includes. */\r
+#include "LPC17xx_defs.h"\r
+\r
+\r
+#define NUM_LEDS       8\r
+\r
+/* Demo app includes. */\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "integer.h"\r
+#include "blocktim.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "semtest.h"\r
+#include "PollQ.h"\r
+#include "GenQTest.h"\r
+#include "QPeek.h"\r
+#include "recmutex.h"\r
+#include "lcd/portlcd.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The time between cycles of the 'check' functionality (defined within the\r
+tick hook. */\r
+#define mainCHECK_DELAY                                                ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+\r
+/* Task priorities. */\r
+#define mainQUEUE_POLL_PRIORITY                                ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY                                ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY                          ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY                           ( tskIDLE_PRIORITY + 2 )\r
+#define mainCREATOR_TASK_PRIORITY           ( tskIDLE_PRIORITY + 3 )\r
+#define mainINTEGER_TASK_PRIORITY           ( tskIDLE_PRIORITY )\r
+#define mainGEN_QUEUE_TASK_PRIORITY                    ( tskIDLE_PRIORITY )\r
+\r
+/* The period of the system clock in nano seconds.  This is used to calculate\r
+the jitter time in nano seconds. */\r
+#define mainNS_PER_CLOCK                                       ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) )\r
+\r
+#define mainBASIC_WEB_STACK_SIZE            ( configMINIMAL_STACK_SIZE * 4 )\r
+#define mainQUEUE_SIZE                                         ( 3 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Configure the hardware for the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Simply toggles the indicated LED.\r
+ */\r
+static void vToggleLED( unsigned portBASE_TYPE uxLED );\r
+\r
+/*\r
+ * Very simple task that toggles an LED.\r
+ */\r
+static void vLEDTask( void *pvParameters );\r
+\r
+/* \r
+ * The task that handles the uIP stack.  All TCP/IP processing is performed in\r
+ * this task.\r
+ */\r
+extern void vuIP_Task( void *pvParameters );\r
+\r
+static void vLCDTask( void *pvParameters );\r
+\r
+/* The queue used to send messages to the LCD task. */\r
+xQueueHandle xLCDQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+long l;\r
+\r
+       prvSetupHardware();\r
+\r
+       /* Start the standard demo tasks. */\r
+       vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+    vCreateBlockTimeTasks();\r
+    vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+    vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+    vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );\r
+    vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+    vStartQueuePeekTasks();\r
+    vStartRecursiveMutexTasks();\r
+\r
+       /* Start 8 tasks, each of which toggles a different LED at a different rate. */\r
+       for( l = 0; l < NUM_LEDS; l++ )\r
+       {\r
+               xTaskCreate( vLEDTask, (signed char *) "LED", configMINIMAL_STACK_SIZE, ( void * ) l, tskIDLE_PRIORITY+1, NULL );\r
+       }\r
+    \r
+       /* Create the uIP task.  This uses the lwIP RTOS abstraction layer.*/\r
+    xTaskCreate( vuIP_Task, ( signed char * ) "uIP", mainBASIC_WEB_STACK_SIZE, ( void * ) NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
+       \r
+       /* Create the queue used by the LCD task.  Messages for display on the LCD\r
+       are received via this queue. */\r
+       xLCDQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( xLCDMessage ) );\r
+\r
+       /* Start the tasks defined within this file/specific to this demo. */\r
+       xTaskCreate( vLCDTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
+    \r
+       /* The suicide tasks must be created last as they need to know how many\r
+       tasks were running prior to their creation in order to ascertain whether\r
+       or not the correct/expected number of tasks are running at any given time. */\r
+    vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+    /* Start the scheduler. */\r
+       vTaskStartScheduler();\r
+\r
+    /* Will only get here if there was insufficient memory to create the idle\r
+    task. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vLEDTask( void *pvParameters ) \r
+{\r
+/* The LED to toggle is passed in as the task paramter. */\r
+long lLED = ( long ) pvParameters;\r
+unsigned long ulLEDToToggle = 1 << lLED;\r
+\r
+/* Calculate a delay period based on the LED number. */\r
+unsigned long ulDelayPeriod = 100 * ( lLED + 1 );\r
+\r
+       for( ;; )\r
+       {\r
+               vTaskDelay( ulDelayPeriod );\r
+               vToggleLED( ulLEDToToggle );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+       if( FIO2PIN & uxLED )\r
+       {\r
+               FIO2CLR = uxLED;\r
+       }\r
+       else\r
+       {\r
+               FIO2SET = uxLED;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetupHardware( void )\r
+{\r
+       PCONP = 0;                                                      /* Disable peripherals power. */\r
+       PCONP = PCONP_PCGPIO;                           /* Enable GPIO power. */\r
+       PINSEL10 = 0;                                           /* Disable TPIU. */\r
+       \r
+       PLL0CON &= ~PLLCON_PLLC;                        /* Disconnect the main PLL. */\r
+       PLL0FEED = PLLFEED_FEED1;\r
+       PLL0FEED = PLLFEED_FEED2;\r
+       while ((PLL0STAT & PLLSTAT_PLLC) != 0); \r
+       \r
+       PLL0CON &= ~PLLCON_PLLE;                        /* Turn off the main PLL. */\r
+       PLL0FEED = PLLFEED_FEED1;\r
+       PLL0FEED = PLLFEED_FEED2;\r
+       while ((PLL0STAT & PLLSTAT_PLLE) != 0);    \r
+       \r
+       CCLKCFG = 0;                                            /* No CPU clock divider. */\r
+       SCS = 0x20;                                                     /* OSCEN. */\r
+       while ((SCS & 0x40) == 0);\r
+       \r
+       CLKSRCSEL = 1;                                          /* Use main oscillator. */\r
+       PLL0CFG = (PLLCFG_MUL16 | PLLCFG_DIV1);\r
+       \r
+       PLL0FEED = PLLFEED_FEED1;\r
+       PLL0FEED = PLLFEED_FEED2;  \r
+       \r
+       /*  Activate the PLL by turning it on then feeding the correct \r
+       sequence of bytes. */\r
+       PLL0CON  = PLLCON_PLLE;\r
+       PLL0FEED = PLLFEED_FEED1;\r
+       PLL0FEED = PLLFEED_FEED2;\r
+       \r
+       CCLKCFG = 5;                                            /* 6x CPU clock divider (72 MHz) */\r
+       \r
+       /*  Wait for the PLL to lock. */\r
+       while ((PLL0STAT & PLLSTAT_PLOCK) == 0);\r
+       \r
+       /*  Connect the PLL. */\r
+       PLL0CON  = PLLCON_PLLC | PLLCON_PLLE;\r
+       PLL0FEED = PLLFEED_FEED1;\r
+       PLL0FEED = PLLFEED_FEED2;\r
+       \r
+       /*  Setup the peripheral bus to be the same as the PLL output (72 MHz). */\r
+       PCLKSEL0 = 0x05555555;\r
+\r
+       /* Configure LED GPIOs as outputs. */\r
+       FIO2DIR  = 0xff;\r
+       FIO2CLR  = 0xff;\r
+       FIO2MASK = 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )\r
+{\r
+       ( void ) pxTask;\r
+       ( void ) pcTaskName;\r
+       \r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vConfigureTimerForRunTimeStats( void )\r
+{\r
+       PCONP |= 0x02UL;\r
+       _PCLKSEL0 = (_PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2);\r
+       \r
+       /* Reset Timer 0 */\r
+       T0TCR = TCR_COUNT_RESET;\r
+       \r
+       /* Just count up. */\r
+       T0CTCR = CTCR_CTM_TIMER;\r
+\r
+       /* Prescale to a frequency that is good enough to get a decent resolution,\r
+       but not too fast so as to overflow all the time. */\r
+       T0PR =  ( configCPU_CLOCK_HZ / 10000UL ) - 1UL;\r
+\r
+       /* Start the counter. */\r
+       T0TCR = TCR_COUNT_ENABLE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vLCDTask( void *pvParameters )\r
+{\r
+xLCDMessage xMessage;\r
+\r
+       ( void ) pvParameters;\r
+\r
+       /* Initialise the LCD and display a startup message. */\r
+       LCD_init();\r
+       LCD_cur_off();\r
+    LCD_cls();    \r
+    LCD_gotoxy( 1, 1 );\r
+    LCD_puts( "www.FreeRTOS.org" );\r
+\r
+       for( ;; )\r
+       {\r
+               /* Wait for a message to arrive that requires displaying. */\r
+               while( xQueueReceive( xLCDQueue, &xMessage, portMAX_DELAY ) != pdPASS );\r
+               \r
+               /* Display the message.  Print each message to a different position. */\r
+               LCD_cls();\r
+               LCD_gotoxy( ( xMessage.xColumn & 0x07 ) + 1, ( xMessage.xColumn & 0x01 ) + 1 );\r
+               LCD_puts( xMessage.pcMessage );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/printf-stdarg.c b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/printf-stdarg.c
new file mode 100644 (file)
index 0000000..f6139dc
--- /dev/null
@@ -0,0 +1,293 @@
+/*\r
+       Copyright 2001, 2002 Georges Menie (www.menie.org)\r
+       stdarg version contributed by Christian Ettinger\r
+\r
+    This program is free software; you can redistribute it and/or modify\r
+    it under the terms of the GNU Lesser General Public License as published by\r
+    the Free Software Foundation; either version 2 of the License, or\r
+    (at your option) any later version.\r
+\r
+    This program is distributed in the hope that it will be useful,\r
+    but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+    GNU Lesser General Public License for more details.\r
+\r
+    You should have received a copy of the GNU Lesser General Public License\r
+    along with this program; if not, write to the Free Software\r
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+*/\r
+\r
+/*\r
+       putchar is the only external dependency for this file,\r
+       if you have a working putchar, leave it commented out.\r
+       If not, uncomment the define below and\r
+       replace outbyte(c) by your own function call.\r
+\r
+*/\r
+\r
+#define putchar(c) c\r
+\r
+#include <stdarg.h>\r
+\r
+static void printchar(char **str, int c)\r
+{\r
+       //extern int putchar(int c);\r
+       \r
+       if (str) {\r
+               **str = (char)c;\r
+               ++(*str);\r
+       }\r
+       else\r
+       { \r
+               (void)putchar(c);\r
+       }\r
+}\r
+\r
+#define PAD_RIGHT 1\r
+#define PAD_ZERO 2\r
+\r
+static int prints(char **out, const char *string, int width, int pad)\r
+{\r
+       register int pc = 0, padchar = ' ';\r
+\r
+       if (width > 0) {\r
+               register int len = 0;\r
+               register const char *ptr;\r
+               for (ptr = string; *ptr; ++ptr) ++len;\r
+               if (len >= width) width = 0;\r
+               else width -= len;\r
+               if (pad & PAD_ZERO) padchar = '0';\r
+       }\r
+       if (!(pad & PAD_RIGHT)) {\r
+               for ( ; width > 0; --width) {\r
+                       printchar (out, padchar);\r
+                       ++pc;\r
+               }\r
+       }\r
+       for ( ; *string ; ++string) {\r
+               printchar (out, *string);\r
+               ++pc;\r
+       }\r
+       for ( ; width > 0; --width) {\r
+               printchar (out, padchar);\r
+               ++pc;\r
+       }\r
+\r
+       return pc;\r
+}\r
+\r
+/* the following should be enough for 32 bit int */\r
+#define PRINT_BUF_LEN 12\r
+\r
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)\r
+{\r
+       char print_buf[PRINT_BUF_LEN];\r
+       register char *s;\r
+       register int t, neg = 0, pc = 0;\r
+       register unsigned int u = (unsigned int)i;\r
+\r
+       if (i == 0) {\r
+               print_buf[0] = '0';\r
+               print_buf[1] = '\0';\r
+               return prints (out, print_buf, width, pad);\r
+       }\r
+\r
+       if (sg && b == 10 && i < 0) {\r
+               neg = 1;\r
+               u = (unsigned int)-i;\r
+       }\r
+\r
+       s = print_buf + PRINT_BUF_LEN-1;\r
+       *s = '\0';\r
+\r
+       while (u) {\r
+               t = (int)u % b;\r
+               if( t >= 10 )\r
+                       t += letbase - '0' - 10;\r
+               *--s = (char)(t + '0');\r
+               u /= b;\r
+       }\r
+\r
+       if (neg) {\r
+               if( width && (pad & PAD_ZERO) ) {\r
+                       printchar (out, '-');\r
+                       ++pc;\r
+                       --width;\r
+               }\r
+               else {\r
+                       *--s = '-';\r
+               }\r
+       }\r
+\r
+       return pc + prints (out, s, width, pad);\r
+}\r
+\r
+static int print( char **out, const char *format, va_list args )\r
+{\r
+       register int width, pad;\r
+       register int pc = 0;\r
+       char scr[2];\r
+\r
+       for (; *format != 0; ++format) {\r
+               if (*format == '%') {\r
+                       ++format;\r
+                       width = pad = 0;\r
+                       if (*format == '\0') break;\r
+                       if (*format == '%') goto out;\r
+                       if (*format == '-') {\r
+                               ++format;\r
+                               pad = PAD_RIGHT;\r
+                       }\r
+                       while (*format == '0') {\r
+                               ++format;\r
+                               pad |= PAD_ZERO;\r
+                       }\r
+                       for ( ; *format >= '0' && *format <= '9'; ++format) {\r
+                               width *= 10;\r
+                               width += *format - '0';\r
+                       }\r
+                       if( *format == 's' ) {\r
+                               register char *s = (char *)va_arg( args, int );\r
+                               pc += prints (out, s?s:"(null)", width, pad);\r
+                               continue;\r
+                       }\r
+                       if( *format == 'd' ) {\r
+                               pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'x' ) {\r
+                               pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'X' ) {\r
+                               pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'u' ) {\r
+                               pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'c' ) {\r
+                               /* char are converted to int then pushed on the stack */\r
+                               scr[0] = (char)va_arg( args, int );\r
+                               scr[1] = '\0';\r
+                               pc += prints (out, scr, width, pad);\r
+                               continue;\r
+                       }\r
+               }\r
+               else {\r
+               out:\r
+                       printchar (out, *format);\r
+                       ++pc;\r
+               }\r
+       }\r
+       if (out) **out = '\0';\r
+       va_end( args );\r
+       return pc;\r
+}\r
+\r
+int printf(const char *format, ...)\r
+{\r
+        va_list args;\r
+        \r
+        va_start( args, format );\r
+        return print( 0, format, args );\r
+}\r
+\r
+int sprintf(char *out, const char *format, ...)\r
+{\r
+        va_list args;\r
+        \r
+        va_start( args, format );\r
+        return print( &out, format, args );\r
+}\r
+\r
+\r
+int snprintf( char *buf, unsigned int count, const char *format, ... )\r
+{\r
+        va_list args;\r
+        \r
+        ( void ) count;\r
+        \r
+        va_start( args, format );\r
+        return print( &buf, format, args );\r
+}\r
+\r
+\r
+#ifdef TEST_PRINTF\r
+int main(void)\r
+{\r
+       char *ptr = "Hello world!";\r
+       char *np = 0;\r
+       int i = 5;\r
+       unsigned int bs = sizeof(int)*8;\r
+       int mi;\r
+       char buf[80];\r
+\r
+       mi = (1 << (bs-1)) + 1;\r
+       printf("%s\n", ptr);\r
+       printf("printf test\n");\r
+       printf("%s is null pointer\n", np);\r
+       printf("%d = 5\n", i);\r
+       printf("%d = - max int\n", mi);\r
+       printf("char %c = 'a'\n", 'a');\r
+       printf("hex %x = ff\n", 0xff);\r
+       printf("hex %02x = 00\n", 0);\r
+       printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);\r
+       printf("%d %s(s)%", 0, "message");\r
+       printf("\n");\r
+       printf("%d %s(s) with %%\n", 0, "message");\r
+       sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);\r
+       sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);\r
+       sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);\r
+       sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);\r
+       sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);\r
+       sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);\r
+       sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);\r
+       sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);\r
+\r
+       return 0;\r
+}\r
+\r
+/*\r
+ * if you compile this file with\r
+ *   gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c\r
+ * you will get a normal warning:\r
+ *   printf.c:214: warning: spurious trailing `%' in format\r
+ * this line is testing an invalid % at the end of the format string.\r
+ *\r
+ * this should display (on 32bit int machine) :\r
+ *\r
+ * Hello world!\r
+ * printf test\r
+ * (null) is null pointer\r
+ * 5 = 5\r
+ * -2147483647 = - max int\r
+ * char a = 'a'\r
+ * hex ff = ff\r
+ * hex 00 = 00\r
+ * signed -3 = unsigned 4294967293 = hex fffffffd\r
+ * 0 message(s)\r
+ * 0 message(s) with %\r
+ * justif: "left      "\r
+ * justif: "     right"\r
+ *  3: 0003 zero padded\r
+ *  3: 3    left justif.\r
+ *  3:    3 right justif.\r
+ * -3: -003 zero padded\r
+ * -3: -3   left justif.\r
+ * -3:   -3 right justif.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/* To keep linker happy. */\r
+int    write( int i, char* c, int n)\r
+{\r
+       (void)i;\r
+       (void)n;\r
+       (void)c;\r
+       return 0;\r
+}\r
+\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/rtosdemo_lpc1766.ld b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/rtosdemo_lpc1766.ld
new file mode 100644 (file)
index 0000000..58f561e
--- /dev/null
@@ -0,0 +1,56 @@
+/*\r
+ * GENERATED FILE - DO NOT EDIT\r
+ * (C) Code Red Technologies Ltd, 2008-9    \r
+ * Generated C linker script file for LPC1766 \r
+ * (created from nxp_cm3_c.ld (v2.0.0 (200903141830)) on Mon May 25 20:29:07 BST 2009)\r
+*/\r
+\r
+GROUP(libgcc.a libc.a)\r
+\r
+MEMORY\r
+{\r
+     FLASH (rx) : ORIGIN = 0x0 LENGTH = 0x40000\r
+     SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000\r
+}\r
+\r
+_vRamTop = 0x10000000 + 0x8000;\r
+\r
+ENTRY(ResetISR)\r
+\r
+SECTIONS\r
+{\r
+       .text :\r
+       {\r
+               KEEP(*(.isr_vector))\r
+               *(.text*)\r
+               *(.rodata*)\r
+\r
+       } > FLASH\r
+\r
+\r
+       __exidx_end = .;\r
+       _etext = .;\r
+               \r
+       .data : AT (__exidx_end)\r
+       {\r
+               _data = .;\r
+               *(.data*)\r
+               _edata = .;\r
+       } > SRAM\r
+\r
+       /* zero initialized data */\r
+       .bss :\r
+       {\r
+               _bss = .;\r
+               *(.bss*)\r
+               _ebss = .;\r
+       } > SRAM\r
+       \r
+\r
+/*\r
+       Note: (ref: M0000066)\r
+       Moving the stack down by 16 is to work around a GDB bug.\r
+       This space can be reclaimed for Production Builds.\r
+*/     \r
+       _vStackTop = _vRamTop - 16;\r
+}\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/syscalls.c b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/syscalls.c
new file mode 100644 (file)
index 0000000..3053cfa
--- /dev/null
@@ -0,0 +1,82 @@
+/* Don't need anything here. */
+
+#include <stdlib.h>
+#include <sys/stat.h>
+
+int _read_r (struct _reent *r, int file, char * ptr, int len)
+{
+       ( void ) r;
+       ( void ) file;
+       ( void ) ptr;
+       ( void ) len;
+       return -1;
+}
+
+/***************************************************************************/
+
+int _lseek_r (struct _reent *r, int file, int ptr, int dir)
+{
+       ( void ) r;
+       ( void ) file;
+       ( void ) ptr;
+       ( void ) dir;
+       
+       return 0;
+}
+
+/***************************************************************************/
+
+int _write_r (struct _reent *r, int file, char * ptr, int len)
+{  
+       ( void ) r;
+       ( void ) file;
+       ( void ) ptr;
+       ( void ) len;
+       
+       return 0;
+}
+
+/***************************************************************************/
+
+int _close_r (struct _reent *r, int file)
+{
+       ( void ) r;
+       ( void ) file;
+
+       return 0;
+}
+
+/***************************************************************************/
+
+caddr_t _sbrk_r (struct _reent *r, int incr)
+{
+       ( void ) r;
+       ( void ) incr;
+       
+       return 0;
+}
+
+/***************************************************************************/
+
+int _fstat_r (struct _reent *r, int file, struct stat * st)
+{
+       ( void ) r;
+       ( void ) file;
+       ( void ) st;
+       
+       return 0;
+}
+
+/***************************************************************************/
+
+int _isatty_r(struct _reent *r, int fd)
+{
+       ( void ) r;
+       ( void ) fd;
+       
+       return 0;
+}
+
+
+
+
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/system_LPC17xx.h b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/system_LPC17xx.h
new file mode 100644 (file)
index 0000000..a5c9727
--- /dev/null
@@ -0,0 +1,40 @@
+/******************************************************************************\r
+ * @file:    system_LPC17xx.h\r
+ * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File\r
+ *           for the NXP LPC17xx Device Series \r
+ * @version: V1.0\r
+ * @date:    25. Nov. 2008\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2008 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3 \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __SYSTEM_LPC17xx_H\r
+#define __SYSTEM_LPC17xx_H\r
+\r
+extern uint32_t SystemFrequency;    /*!< System Clock Frequency (Core Clock)  */\r
+\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * @brief  Setup the microcontroller system.\r
+ *         Initialize the System and update the SystemFrequency variable.\r
+ */\r
+extern void SystemInit (void);\r
+#endif\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/clock-arch.h b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/clock-arch.h
new file mode 100644 (file)
index 0000000..cde657b
--- /dev/null
@@ -0,0 +1,42 @@
+/*\r
+ * Copyright (c) 2006, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ *    may be used to endorse or promote products derived from this software\r
+ *    without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $\r
+ */\r
+\r
+#ifndef __CLOCK_ARCH_H__\r
+#define __CLOCK_ARCH_H__\r
+\r
+#include "FreeRTOS.h"\r
+\r
+typedef unsigned long clock_time_t;\r
+#define CLOCK_CONF_SECOND configTICK_RATE_HZ\r
+\r
+#endif /* __CLOCK_ARCH_H__ */\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/emac.c b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/emac.c
new file mode 100644 (file)
index 0000000..91a353a
--- /dev/null
@@ -0,0 +1,426 @@
+/******************************************************************\r
+ *****                                                        *****\r
+ *****  Name: cs8900.c                                        *****\r
+ *****  Ver.: 1.0                                             *****\r
+ *****  Date: 07/05/2001                                      *****\r
+ *****  Auth: Andreas Dannenberg                              *****\r
+ *****        HTWK Leipzig                                    *****\r
+ *****        university of applied sciences                  *****\r
+ *****        Germany                                         *****\r
+ *****  Func: ethernet packet-driver for use with LAN-        *****\r
+ *****        controller CS8900 from Crystal/Cirrus Logic     *****\r
+ *****                                                        *****\r
+ *****  Keil: Module modified for use with Philips            *****\r
+ *****        LPC2378 EMAC Ethernet controller                *****\r
+ *****                                                        *****\r
+ ******************************************************************/\r
+\r
+/* Adapted from file originally written by Andreas Dannenberg.  Supplied with permission. */\r
+\r
+#include "FreeRTOS.h"\r
+#include "semphr.h" \r
+#include "task.h"\r
+#include "emac.h"\r
+#include "LPC17xx_defs.h"\r
+\r
+#define configPINSEL2_VALUE    0x50150105\r
+\r
+/* The semaphore used to wake the uIP task when data arives. */\r
+xSemaphoreHandle xEMACSemaphore = NULL;\r
+\r
+static unsigned short *rptr;\r
+static unsigned short *tptr;\r
+\r
+// easyWEB internal function\r
+// help function to swap the byte order of a WORD\r
+\r
+static unsigned short SwapBytes(unsigned short Data)\r
+{\r
+  return (Data >> 8) | (Data << 8);\r
+}\r
+\r
+// Keil: function added to write PHY\r
+void write_PHY (int PhyReg, int Value)\r
+{\r
+  unsigned int tout;\r
+\r
+  MAC_MADR = DP83848C_DEF_ADR | PhyReg;\r
+  MAC_MWTD = Value;\r
+\r
+  /* Wait utill operation completed */\r
+  tout = 0;\r
+  for (tout = 0; tout < MII_WR_TOUT; tout++) {\r
+    if ((MAC_MIND & MIND_BUSY) == 0) {\r
+      break;\r
+    }\r
+  }\r
+}\r
+\r
+\r
+// Keil: function added to read PHY\r
+unsigned short read_PHY (unsigned char PhyReg) \r
+{\r
+  unsigned int tout;\r
+\r
+  MAC_MADR = DP83848C_DEF_ADR | PhyReg;\r
+  MAC_MCMD = MCMD_READ;\r
+\r
+  /* Wait until operation completed */\r
+  tout = 0;\r
+  for (tout = 0; tout < MII_RD_TOUT; tout++) {\r
+    if ((MAC_MIND & MIND_BUSY) == 0) {\r
+      break;\r
+    }\r
+  }\r
+  MAC_MCMD = 0;\r
+  return (MAC_MRDD);\r
+}\r
+\r
+\r
+// Keil: function added to initialize Rx Descriptors\r
+void rx_descr_init (void)\r
+{\r
+  unsigned int i;\r
+\r
+  for (i = 0; i < NUM_RX_FRAG; i++) {\r
+    RX_DESC_PACKET(i)  = RX_BUF(i);\r
+    RX_DESC_CTRL(i)    = RCTRL_INT | (ETH_FRAG_SIZE-1);\r
+    RX_STAT_INFO(i)    = 0;\r
+    RX_STAT_HASHCRC(i) = 0;\r
+  }\r
+\r
+  /* Set EMAC Receive Descriptor Registers. */\r
+  MAC_RXDESCRIPTOR    = RX_DESC_BASE;\r
+  MAC_RXSTATUS        = RX_STAT_BASE;\r
+  MAC_RXDESCRIPTORNUM = NUM_RX_FRAG-1;\r
+\r
+  /* Rx Descriptors Point to 0 */\r
+  MAC_RXCONSUMEINDEX  = 0;\r
+}\r
+\r
+\r
+// Keil: function added to initialize Tx Descriptors\r
+void tx_descr_init (void) {\r
+  unsigned int i;\r
+\r
+  for (i = 0; i < NUM_TX_FRAG; i++) {\r
+    TX_DESC_PACKET(i) = TX_BUF(i);\r
+    TX_DESC_CTRL(i)   = 0;\r
+    TX_STAT_INFO(i)   = 0;\r
+  }\r
+\r
+  /* Set EMAC Transmit Descriptor Registers. */\r
+  MAC_TXDESCRIPTOR    = TX_DESC_BASE;\r
+  MAC_TXSTATUS        = TX_STAT_BASE;\r
+  MAC_TXDESCRIPTORNUM = NUM_TX_FRAG-1;\r
+\r
+  /* Tx Descriptors Point to 0 */\r
+  MAC_TXPRODUCEINDEX  = 0;\r
+}\r
+\r
+\r
+// configure port-pins for use with LAN-controller,\r
+// reset it and send the configuration-sequence\r
+\r
+portBASE_TYPE Init_EMAC(void)\r
+{\r
+portBASE_TYPE xReturn = pdPASS;\r
+\r
+// Keil: function modified to access the EMAC\r
+// Initializes the EMAC ethernet controller\r
+  volatile unsigned int regv,tout,id1,id2;\r
+\r
+  /* Enable P1 Ethernet Pins. */\r
+  PINSEL2 = configPINSEL2_VALUE;\r
+  PINSEL3 = (PINSEL3 & ~0x0000000F) | 0x00000005;\r
+\r
+  /* Power Up the EMAC controller. */\r
+  PCONP |= 0x40000000;\r
+  vTaskDelay( 1 );\r
+\r
+  /* Reset all EMAC internal modules. */\r
+  MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;\r
+  MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES;\r
+\r
+  /* A short delay after reset. */\r
+  vTaskDelay( 1 );\r
+\r
+  /* Initialize MAC control registers. */\r
+  MAC_MAC1 = MAC1_PASS_ALL;\r
+  MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;\r
+  MAC_MAXF = ETH_MAX_FLEN;\r
+  MAC_CLRT = CLRT_DEF;\r
+  MAC_IPGR = IPGR_DEF;\r
+\r
+  /* Enable Reduced MII interface. */\r
+  MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM;\r
+\r
+  /* Reset Reduced MII Logic. */\r
+  MAC_SUPP = SUPP_RES_RMII;\r
+  MAC_SUPP = 0;\r
+\r
+  /* Put the DP83848C in reset mode */\r
+  write_PHY (PHY_REG_BMCR, 0x8000);\r
+  write_PHY (PHY_REG_BMCR, 0x8000);\r
+\r
+  /* Wait for hardware reset to end. */\r
+  for (tout = 0; tout < 100; tout++) {\r
+    vTaskDelay( 10 );\r
+    regv = read_PHY (PHY_REG_BMCR);\r
+    if (!(regv & 0x8000)) {\r
+      /* Reset complete */\r
+      break;\r
+    }\r
+  }\r
+\r
+  /* Check if this is a DP83848C PHY. */\r
+  id1 = read_PHY (PHY_REG_IDR1);\r
+  id2 = read_PHY (PHY_REG_IDR2);\r
+  if (((id1 << 16) | (id2 & 0xFFF0)) == DP83848C_ID) {\r
+    /* Configure the PHY device */\r
+\r
+    /* Use autonegotiation about the link speed. */\r
+    write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);\r
+    /* Wait to complete Auto_Negotiation. */\r
+    for (tout = 0; tout < 10; tout++) {\r
+      vTaskDelay( 100 );\r
+      regv = read_PHY (PHY_REG_BMSR);\r
+      if (regv & 0x0020) {\r
+        /* Autonegotiation Complete. */\r
+        break;\r
+      }\r
+    }\r
+  }\r
+  else\r
+  {\r
+    xReturn = pdFAIL;\r
+  }\r
+\r
+  /* Check the link status. */\r
+  if( xReturn == pdPASS )\r
+  {\r
+    xReturn = pdFAIL;\r
+    for (tout = 0; tout < 10; tout++) {\r
+      vTaskDelay( 100 );\r
+      regv = read_PHY (PHY_REG_STS);\r
+      if (regv & 0x0001) {\r
+        /* Link is on. */\r
+        xReturn = pdPASS;\r
+        break;\r
+      }\r
+    }\r
+  }\r
+\r
+  if( xReturn == pdPASS )\r
+  {\r
+    /* Configure Full/Half Duplex mode. */\r
+    if (regv & 0x0004) {\r
+      /* Full duplex is enabled. */\r
+      MAC_MAC2    |= MAC2_FULL_DUP;\r
+      MAC_COMMAND |= CR_FULL_DUP;\r
+      MAC_IPGT     = IPGT_FULL_DUP;\r
+    }\r
+    else {\r
+      /* Half duplex mode. */\r
+      MAC_IPGT = IPGT_HALF_DUP;\r
+    }\r
+\r
+    /* Configure 100MBit/10MBit mode. */\r
+    if (regv & 0x0002) {\r
+      /* 10MBit mode. */\r
+      MAC_SUPP = 0;\r
+    }\r
+    else {\r
+      /* 100MBit mode. */\r
+      MAC_SUPP = SUPP_SPEED;\r
+    }\r
+\r
+    /* Set the Ethernet MAC Address registers */\r
+    MAC_SA0 = (emacETHADDR0 << 8) | emacETHADDR1;\r
+    MAC_SA1 = (emacETHADDR2 << 8) | emacETHADDR3;\r
+    MAC_SA2 = (emacETHADDR4 << 8) | emacETHADDR5;\r
+\r
+    /* Initialize Tx and Rx DMA Descriptors */\r
+    rx_descr_init ();\r
+    tx_descr_init ();\r
+\r
+    /* Receive Broadcast and Perfect Match Packets */\r
+    MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;\r
+\r
+    /* Create the semaphore used ot wake the uIP task. */\r
+    vSemaphoreCreateBinary( xEMACSemaphore );\r
+\r
+    /* Reset all interrupts */\r
+    MAC_INTCLEAR  = 0xFFFF;\r
+\r
+    /* Enable receive and transmit mode of MAC Ethernet core */\r
+    MAC_COMMAND  |= (CR_RX_EN | CR_TX_EN);\r
+    MAC_MAC1     |= MAC1_REC_EN;\r
+  }\r
+\r
+  return xReturn;\r
+}\r
+\r
+\r
+// reads a word in little-endian byte order from RX_BUFFER\r
+\r
+unsigned short ReadFrame_EMAC(void)\r
+{\r
+  return (*rptr++);\r
+}\r
+\r
+// reads a word in big-endian byte order from RX_FRAME_PORT\r
+// (useful to avoid permanent byte-swapping while reading\r
+// TCP/IP-data)\r
+\r
+unsigned short ReadFrameBE_EMAC(void)\r
+{\r
+  unsigned short ReturnValue;\r
+\r
+  ReturnValue = SwapBytes (*rptr++);\r
+  return (ReturnValue);\r
+}\r
+\r
+\r
+// copies bytes from frame port to MCU-memory\r
+// NOTES: * an odd number of byte may only be transfered\r
+//          if the frame is read to the end!\r
+//        * MCU-memory MUST start at word-boundary\r
+\r
+void CopyFromFrame_EMAC(void *Dest, unsigned short Size)\r
+{\r
+  unsigned short * piDest;                       // Keil: Pointer added to correct expression\r
+\r
+  piDest = Dest;                                 // Keil: Line added\r
+  while (Size > 1) {\r
+    *piDest++ = ReadFrame_EMAC();\r
+    Size -= 2;\r
+  }\r
+  \r
+  if (Size) {                                         // check for leftover byte...\r
+    *(unsigned char *)piDest = (char)ReadFrame_EMAC();// the LAN-Controller will return 0\r
+  }                                                   // for the highbyte\r
+}\r
+\r
+// does a dummy read on frame-I/O-port\r
+// NOTE: only an even number of bytes is read!\r
+\r
+void DummyReadFrame_EMAC(unsigned short Size)    // discards an EVEN number of bytes\r
+{                                                // from RX-fifo\r
+  while (Size > 1) {\r
+    ReadFrame_EMAC();\r
+    Size -= 2;\r
+  }\r
+}\r
+\r
+// Reads the length of the received ethernet frame and checks if the \r
+// destination address is a broadcast message or not\r
+// returns the frame length\r
+unsigned short StartReadFrame(void) {\r
+  unsigned short RxLen;\r
+  unsigned int idx;\r
+\r
+  idx = MAC_RXCONSUMEINDEX;\r
+  RxLen = (RX_STAT_INFO(idx) & RINFO_SIZE) - 3;\r
+  rptr = (unsigned short *)RX_DESC_PACKET(idx);\r
+  return(RxLen);\r
+}\r
+\r
+void EndReadFrame(void) {\r
+  unsigned int idx;\r
+\r
+  /* DMA free packet. */\r
+  idx = MAC_RXCONSUMEINDEX;\r
+\r
+  if (++idx == NUM_RX_FRAG)\r
+    idx = 0;\r
+\r
+  MAC_RXCONSUMEINDEX = idx;\r
+}\r
+\r
+unsigned int CheckFrameReceived(void) {             // Packet received ?\r
+\r
+  if (MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX)     // more packets received ?\r
+    return(1);\r
+  else \r
+    return(0);\r
+}\r
+\r
+unsigned int uiGetEMACRxData( unsigned char *ucBuffer )\r
+{\r
+unsigned int uiLen = 0;\r
+\r
+    if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX )\r
+    {\r
+        uiLen = StartReadFrame();\r
+        CopyFromFrame_EMAC( ucBuffer, uiLen );\r
+        EndReadFrame();\r
+    }\r
+\r
+    return uiLen;\r
+}\r
+\r
+// requests space in EMAC memory for storing an outgoing frame\r
+\r
+void RequestSend(void)\r
+{\r
+  unsigned int idx;\r
+\r
+  idx  = MAC_TXPRODUCEINDEX;\r
+  tptr = (unsigned short *)TX_DESC_PACKET(idx);\r
+}\r
+\r
+// check if ethernet controller is ready to accept the\r
+// frame we want to send\r
+\r
+unsigned int Rdy4Tx(void)\r
+{\r
+  return (1);   // the ethernet controller transmits much faster\r
+}               // than the CPU can load its buffers\r
+\r
+\r
+// writes a word in little-endian byte order to TX_BUFFER\r
+void WriteFrame_EMAC(unsigned short Data)\r
+{\r
+  *tptr++ = Data;\r
+}\r
+\r
+// copies bytes from MCU-memory to frame port\r
+// NOTES: * an odd number of byte may only be transfered\r
+//          if the frame is written to the end!\r
+//        * MCU-memory MUST start at word-boundary\r
+\r
+void CopyToFrame_EMAC(void *Source, unsigned int Size)\r
+{\r
+  unsigned short * piSource;\r
+\r
+  piSource = Source;\r
+  Size = (Size + 1) & 0xFFFE;    // round Size up to next even number\r
+  while (Size > 0) {\r
+    WriteFrame_EMAC(*piSource++);\r
+    Size -= 2;\r
+  }\r
+}\r
+\r
+void DoSend_EMAC(unsigned short FrameSize)\r
+{\r
+  unsigned int idx;\r
+\r
+  idx = MAC_TXPRODUCEINDEX;\r
+  TX_DESC_CTRL(idx) = FrameSize | TCTRL_LAST;\r
+  if (++idx == NUM_TX_FRAG) idx = 0;\r
+  MAC_TXPRODUCEINDEX = idx;\r
+}\r
+\r
+void vEMAC_ISR( void )\r
+{\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+    /* Clear the interrupt. */\r
+    MAC_INTCLEAR = 0xffff;\r
+\r
+    /* Ensure the uIP task is not blocked as data has arrived. */\r
+    xSemaphoreGiveFromISR( xEMACSemaphore, &xHigherPriorityTaskWoken );\r
+\r
+    portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/emac.h b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/emac.h
new file mode 100644 (file)
index 0000000..3fd5dc3
--- /dev/null
@@ -0,0 +1,324 @@
+/*----------------------------------------------------------------------------\r
+ *      LPC2378 Ethernet Definitions\r
+ *----------------------------------------------------------------------------\r
+ *      Name:    EMAC.H\r
+ *      Purpose: Philips LPC2378 EMAC hardware definitions\r
+ *----------------------------------------------------------------------------\r
+ *      Copyright (c) 2006 KEIL - An ARM Company. All rights reserved.\r
+ *---------------------------------------------------------------------------*/\r
+#ifndef __EMAC_H\r
+#define __EMAC_H\r
+\r
+/* MAC address definition.  The MAC address must be unique on the network. */\r
+#define emacETHADDR0 0\r
+#define emacETHADDR1 0xbd\r
+#define emacETHADDR2 0x33\r
+#define emacETHADDR3 0x02\r
+#define emacETHADDR4 0x64\r
+#define emacETHADDR5 0x24\r
+\r
+\r
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */\r
+#define NUM_RX_FRAG         4           /* Num.of RX Fragments 4*1536= 6.0kB */\r
+#define NUM_TX_FRAG         2           /* Num.of TX Fragments 2*1536= 3.0kB */\r
+#define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */\r
+\r
+#define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */\r
+\r
+/* EMAC variables located in 16K Ethernet SRAM */\r
+//extern unsigned char xEthDescriptors[];\r
+#define RX_DESC_BASE        (0x20000000UL)\r
+#define RX_STAT_BASE        (RX_DESC_BASE + NUM_RX_FRAG*8)\r
+#define TX_DESC_BASE        (RX_STAT_BASE + NUM_RX_FRAG*8)\r
+#define TX_STAT_BASE        (TX_DESC_BASE + NUM_TX_FRAG*8)\r
+#define RX_BUF_BASE         (TX_STAT_BASE + NUM_TX_FRAG*4)\r
+#define TX_BUF_BASE         (RX_BUF_BASE  + NUM_RX_FRAG*ETH_FRAG_SIZE)\r
+#define TX_BUF_END                     (TX_BUF_BASE  + NUM_TX_FRAG*ETH_FRAG_SIZE)\r
+\r
+/* RX and TX descriptor and status definitions. */\r
+#define RX_DESC_PACKET(i)   (*(unsigned int *)(RX_DESC_BASE   + 8*i))\r
+#define RX_DESC_CTRL(i)     (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))\r
+#define RX_STAT_INFO(i)     (*(unsigned int *)(RX_STAT_BASE   + 8*i))\r
+#define RX_STAT_HASHCRC(i)  (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))\r
+#define TX_DESC_PACKET(i)   (*(unsigned int *)(TX_DESC_BASE   + 8*i))\r
+#define TX_DESC_CTRL(i)     (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))\r
+#define TX_STAT_INFO(i)     (*(unsigned int *)(TX_STAT_BASE   + 4*i))\r
+#define RX_BUF(i)           (RX_BUF_BASE + ETH_FRAG_SIZE*i)\r
+#define TX_BUF(i)           (TX_BUF_BASE + ETH_FRAG_SIZE*i)\r
+\r
+/* MAC Configuration Register 1 */\r
+#define MAC1_REC_EN         0x00000001  /* Receive Enable                    */\r
+#define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */\r
+#define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */\r
+#define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */\r
+#define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */\r
+#define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */\r
+#define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */\r
+#define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */\r
+#define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */\r
+#define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */\r
+#define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */\r
+\r
+/* MAC Configuration Register 2 */\r
+#define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */\r
+#define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */\r
+#define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */\r
+#define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */\r
+#define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */\r
+#define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */\r
+#define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */\r
+#define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */\r
+#define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */\r
+#define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */\r
+#undef  MAC2_NO_BACKOFF /* Remove compiler warning. */\r
+#define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */\r
+#define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */\r
+#define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */\r
+\r
+/* Back-to-Back Inter-Packet-Gap Register */\r
+#define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */\r
+#define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */\r
+\r
+/* Non Back-to-Back Inter-Packet-Gap Register */\r
+#define IPGR_DEF            0x00000012  /* Recommended value                 */\r
+\r
+/* Collision Window/Retry Register */\r
+#define CLRT_DEF            0x0000370F  /* Default value                     */\r
+\r
+/* PHY Support Register */\r
+#undef SUPP_SPEED   /* Remove compiler warning. */\r
+#define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */\r
+#define SUPP_RES_RMII       0x00000800  /* Reset Reduced MII Logic           */\r
+\r
+/* Test Register */\r
+#define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */\r
+#define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */\r
+#define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */\r
+\r
+/* MII Management Configuration Register */\r
+#define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */\r
+#define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */\r
+#define MCFG_CLK_SEL        0x0000001C  /* Clock Select Mask                 */\r
+#define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */\r
+\r
+/* MII Management Command Register */\r
+#undef MCMD_READ   /* Remove compiler warning. */\r
+#define MCMD_READ           0x00000001  /* MII Read                          */\r
+#undef MCMD_SCAN /* Remove compiler warning. */\r
+#define MCMD_SCAN           0x00000002  /* MII Scan continuously             */\r
+\r
+#define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */\r
+#define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */\r
+\r
+/* MII Management Address Register */\r
+#define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */\r
+#define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */\r
+\r
+/* MII Management Indicators Register */\r
+#undef MIND_BUSY   /* Remove compiler warning. */\r
+#define MIND_BUSY           0x00000001  /* MII is Busy                       */\r
+#define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */\r
+#define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */\r
+#define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */\r
+\r
+/* Command Register */\r
+#define CR_RX_EN            0x00000001  /* Enable Receive                    */\r
+#define CR_TX_EN            0x00000002  /* Enable Transmit                   */\r
+#define CR_REG_RES          0x00000008  /* Reset Host Registers              */\r
+#define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */\r
+#define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */\r
+#define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */\r
+#define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */\r
+#define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */\r
+#define CR_RMII             0x00000200  /* Reduced MII Interface             */\r
+#define CR_FULL_DUP         0x00000400  /* Full Duplex                       */\r
+\r
+/* Status Register */\r
+#define SR_RX_EN            0x00000001  /* Enable Receive                    */\r
+#define SR_TX_EN            0x00000002  /* Enable Transmit                   */\r
+\r
+/* Transmit Status Vector 0 Register */\r
+#define TSV0_CRC_ERR        0x00000001  /* CRC error                         */\r
+#define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */\r
+#define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */\r
+#define TSV0_DONE           0x00000008  /* Tramsmission Completed            */\r
+#define TSV0_MCAST          0x00000010  /* Multicast Destination             */\r
+#define TSV0_BCAST          0x00000020  /* Broadcast Destination             */\r
+#define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */\r
+#define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */\r
+#define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */\r
+#define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */\r
+#define TSV0_GIANT          0x00000400  /* Giant Frame                       */\r
+#define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */\r
+#define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */\r
+#define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */\r
+#define TSV0_PAUSE          0x20000000  /* Pause Frame                       */\r
+#define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */\r
+#define TSV0_VLAN           0x80000000  /* VLAN Frame                        */\r
+\r
+/* Transmit Status Vector 1 Register */\r
+#define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */\r
+#define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */\r
+\r
+/* Receive Status Vector Register */\r
+#define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */\r
+#define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */\r
+#define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */\r
+#define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */\r
+#define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */\r
+#define RSV_CRC_ERR         0x00100000  /* CRC Error                         */\r
+#define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */\r
+#define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */\r
+#define RSV_REC_OK          0x00800000  /* Frame Received OK                 */\r
+#define RSV_MCAST           0x01000000  /* Multicast Frame                   */\r
+#define RSV_BCAST           0x02000000  /* Broadcast Frame                   */\r
+#define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */\r
+#define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */\r
+#define RSV_PAUSE           0x10000000  /* Pause Frame                       */\r
+#define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */\r
+#define RSV_VLAN            0x40000000  /* VLAN Frame                        */\r
+\r
+/* Flow Control Counter Register */\r
+#define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */\r
+#define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */\r
+\r
+/* Flow Control Status Register */\r
+#define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */\r
+\r
+/* Receive Filter Control Register */\r
+#define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */\r
+#define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */\r
+#define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */\r
+#define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */\r
+#define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/\r
+#define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */\r
+#define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */\r
+#define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */\r
+\r
+/* Receive Filter WoL Status/Clear Registers */\r
+#define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */\r
+#define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */\r
+#define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */\r
+#define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */\r
+#define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */\r
+#define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */\r
+#define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */\r
+#define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */\r
+\r
+/* Interrupt Status/Enable/Clear/Set Registers */\r
+#define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */\r
+#define INT_RX_ERR          0x00000002  /* Receive Error                     */\r
+#define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */\r
+#define INT_RX_DONE         0x00000008  /* Receive Done                      */\r
+#define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */\r
+#define INT_TX_ERR          0x00000020  /* Transmit Error                    */\r
+#define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */\r
+#define INT_TX_DONE         0x00000080  /* Transmit Done                     */\r
+#define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */\r
+#define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */\r
+\r
+/* Power Down Register */\r
+#define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */\r
+\r
+/* RX Descriptor Control Word */\r
+#define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */\r
+#define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */\r
+\r
+/* RX Status Hash CRC Word */\r
+#define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */\r
+#define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */\r
+\r
+/* RX Status Information Word */\r
+#define RINFO_SIZE          0x000007FF  /* Data size in bytes                */\r
+#define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */\r
+#define RINFO_VLAN          0x00080000  /* VLAN Frame                        */\r
+#define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */\r
+#define RINFO_MCAST         0x00200000  /* Multicast Frame                   */\r
+#define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */\r
+#define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */\r
+#define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */\r
+#define RINFO_LEN_ERR       0x02000000  /* Length Error                      */\r
+#define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */\r
+#define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */\r
+#define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */\r
+#define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */\r
+#define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */\r
+#define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */\r
+\r
+#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | \\r
+                            RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)\r
+\r
+/* TX Descriptor Control Word */\r
+#define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */\r
+#define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */\r
+#define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */\r
+#define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */\r
+#define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */\r
+#define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */\r
+#define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */\r
+\r
+/* TX Status Information Word */\r
+#define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */\r
+#define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */\r
+#define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */\r
+#define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */\r
+#define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */\r
+#define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */\r
+#define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */\r
+#define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */\r
+\r
+/* DP83848C PHY Registers */\r
+#define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */\r
+#define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */\r
+#define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */\r
+#define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */\r
+#define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */\r
+#define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */\r
+#define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */\r
+#define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */\r
+\r
+/* PHY Extended Registers */\r
+#define PHY_REG_STS         0x10        /* Status Register                   */\r
+#define PHY_REG_MICR        0x11        /* MII Interrupt Control Register    */\r
+#define PHY_REG_MISR        0x12        /* MII Interrupt Status Register     */\r
+#define PHY_REG_FCSCR       0x14        /* False Carrier Sense Counter       */\r
+#define PHY_REG_RECR        0x15        /* Receive Error Counter             */\r
+#define PHY_REG_PCSR        0x16        /* PCS Sublayer Config. and Status   */\r
+#define PHY_REG_RBR         0x17        /* RMII and Bypass Register          */\r
+#define PHY_REG_LEDCR       0x18        /* LED Direct Control Register       */\r
+#define PHY_REG_PHYCR       0x19        /* PHY Control Register              */\r
+#define PHY_REG_10BTSCR     0x1A        /* 10Base-T Status/Control Register  */\r
+#define PHY_REG_CDCTRL1     0x1B        /* CD Test Control and BIST Extens.  */\r
+#define PHY_REG_EDCR        0x1D        /* Energy Detect Control Register    */\r
+\r
+#define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */\r
+#define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */\r
+#define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */\r
+#define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */\r
+#define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */\r
+\r
+#define DP83848C_DEF_ADR    0x0100      /* Default PHY device address        */\r
+#define DP83848C_ID         0x20005C90  /* PHY Identifier                    */\r
+\r
+// prototypes\r
+portBASE_TYPE  Init_EMAC(void);\r
+unsigned short         ReadFrameBE_EMAC(void);\r
+void                   CopyToFrame_EMAC(void *Source, unsigned int Size);\r
+void                   CopyFromFrame_EMAC(void *Dest, unsigned short Size);\r
+void                   DummyReadFrame_EMAC(unsigned short Size);\r
+unsigned short         StartReadFrame(void);\r
+void                   EndReadFrame(void);\r
+unsigned int           CheckFrameReceived(void);\r
+void                   RequestSend(void);\r
+unsigned int           Rdy4Tx(void);\r
+void                   DoSend_EMAC(unsigned short FrameSize);\r
+void                   vEMACWaitForInput( void );\r
+unsigned int   uiGetEMACRxData( unsigned char *ucBuffer );\r
+\r
+\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * end of file\r
+ *---------------------------------------------------------------------------*/\r
+\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/http-strings b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/http-strings
new file mode 100644 (file)
index 0000000..0d3c30c
--- /dev/null
@@ -0,0 +1,35 @@
+http_http "http://"\r
+http_200 "200 "\r
+http_301 "301 "\r
+http_302 "302 "\r
+http_get "GET "\r
+http_10 "HTTP/1.0"\r
+http_11 "HTTP/1.1"\r
+http_content_type "content-type: "\r
+http_texthtml "text/html"\r
+http_location "location: "\r
+http_host "host: "\r
+http_crnl "\r\n"\r
+http_index_html "/index.html"\r
+http_404_html "/404.html"\r
+http_referer "Referer:"\r
+http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"\r
+http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"\r
+http_content_type_plain "Content-type: text/plain\r\n\r\n"\r
+http_content_type_html "Content-type: text/html\r\n\r\n"\r
+http_content_type_css  "Content-type: text/css\r\n\r\n"\r
+http_content_type_text "Content-type: text/text\r\n\r\n"\r
+http_content_type_png  "Content-type: image/png\r\n\r\n"\r
+http_content_type_gif  "Content-type: image/gif\r\n\r\n"\r
+http_content_type_jpg  "Content-type: image/jpeg\r\n\r\n"\r
+http_content_type_binary "Content-type: application/octet-stream\r\n\r\n"\r
+http_html ".html"\r
+http_shtml ".shtml"\r
+http_htm ".htm"\r
+http_css ".css"\r
+http_png ".png"\r
+http_gif ".gif"\r
+http_jpg ".jpg"\r
+http_text ".txt"\r
+http_txt ".txt"\r
+\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/http-strings.c b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/http-strings.c
new file mode 100644 (file)
index 0000000..ef7a41c
--- /dev/null
@@ -0,0 +1,102 @@
+const char http_http[8] = \r
+/* "http://" */\r
+{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, };\r
+const char http_200[5] = \r
+/* "200 " */\r
+{0x32, 0x30, 0x30, 0x20, };\r
+const char http_301[5] = \r
+/* "301 " */\r
+{0x33, 0x30, 0x31, 0x20, };\r
+const char http_302[5] = \r
+/* "302 " */\r
+{0x33, 0x30, 0x32, 0x20, };\r
+const char http_get[5] = \r
+/* "GET " */\r
+{0x47, 0x45, 0x54, 0x20, };\r
+const char http_10[9] = \r
+/* "HTTP/1.0" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, };\r
+const char http_11[9] = \r
+/* "HTTP/1.1" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, };\r
+const char http_content_type[15] = \r
+/* "content-type: " */\r
+{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, };\r
+const char http_texthtml[10] = \r
+/* "text/html" */\r
+{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_location[11] = \r
+/* "location: " */\r
+{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, };\r
+const char http_host[7] = \r
+/* "host: " */\r
+{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, };\r
+const char http_crnl[3] = \r
+/* "\r\n" */\r
+{0xd, 0xa, };\r
+const char http_index_html[12] = \r
+/* "/index.html" */\r
+{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_404_html[10] = \r
+/* "/404.html" */\r
+{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_referer[9] = \r
+/* "Referer:" */\r
+{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, };\r
+const char http_header_200[84] = \r
+/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };\r
+const char http_header_404[91] = \r
+/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };\r
+const char http_content_type_plain[29] = \r
+/* "Content-type: text/plain\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_html[28] = \r
+/* "Content-type: text/html\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_css [27] = \r
+/* "Content-type: text/css\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_text[28] = \r
+/* "Content-type: text/text\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_png [28] = \r
+/* "Content-type: image/png\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_gif [28] = \r
+/* "Content-type: image/gif\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_jpg [29] = \r
+/* "Content-type: image/jpeg\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_binary[43] = \r
+/* "Content-type: application/octet-stream\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_html[6] = \r
+/* ".html" */\r
+{0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_shtml[7] = \r
+/* ".shtml" */\r
+{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_htm[5] = \r
+/* ".htm" */\r
+{0x2e, 0x68, 0x74, 0x6d, };\r
+const char http_css[5] = \r
+/* ".css" */\r
+{0x2e, 0x63, 0x73, 0x73, };\r
+const char http_png[5] = \r
+/* ".png" */\r
+{0x2e, 0x70, 0x6e, 0x67, };\r
+const char http_gif[5] = \r
+/* ".gif" */\r
+{0x2e, 0x67, 0x69, 0x66, };\r
+const char http_jpg[5] = \r
+/* ".jpg" */\r
+{0x2e, 0x6a, 0x70, 0x67, };\r
+const char http_text[5] = \r
+/* ".txt" */\r
+{0x2e, 0x74, 0x78, 0x74, };\r
+const char http_txt[5] = \r
+/* ".txt" */\r
+{0x2e, 0x74, 0x78, 0x74, };\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/http-strings.h b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/http-strings.h
new file mode 100644 (file)
index 0000000..acbe7e1
--- /dev/null
@@ -0,0 +1,34 @@
+extern const char http_http[8];\r
+extern const char http_200[5];\r
+extern const char http_301[5];\r
+extern const char http_302[5];\r
+extern const char http_get[5];\r
+extern const char http_10[9];\r
+extern const char http_11[9];\r
+extern const char http_content_type[15];\r
+extern const char http_texthtml[10];\r
+extern const char http_location[11];\r
+extern const char http_host[7];\r
+extern const char http_crnl[3];\r
+extern const char http_index_html[12];\r
+extern const char http_404_html[10];\r
+extern const char http_referer[9];\r
+extern const char http_header_200[84];\r
+extern const char http_header_404[91];\r
+extern const char http_content_type_plain[29];\r
+extern const char http_content_type_html[28];\r
+extern const char http_content_type_css [27];\r
+extern const char http_content_type_text[28];\r
+extern const char http_content_type_png [28];\r
+extern const char http_content_type_gif [28];\r
+extern const char http_content_type_jpg [29];\r
+extern const char http_content_type_binary[43];\r
+extern const char http_html[6];\r
+extern const char http_shtml[7];\r
+extern const char http_htm[5];\r
+extern const char http_css[5];\r
+extern const char http_png[5];\r
+extern const char http_gif[5];\r
+extern const char http_jpg[5];\r
+extern const char http_text[5];\r
+extern const char http_txt[5];\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-cgi.c b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-cgi.c
new file mode 100644 (file)
index 0000000..2eb3dfc
--- /dev/null
@@ -0,0 +1,311 @@
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *         Web server script interface\r
+ * \author\r
+ *         Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2006, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ *    products derived from this software without specific prior\r
+ *    written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $\r
+ *\r
+ */\r
+\r
+#include "uip.h"\r
+#include "psock.h"\r
+#include "httpd.h"\r
+#include "httpd-cgi.h"\r
+#include "httpd-fs.h"\r
+\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+HTTPD_CGI_CALL(file, "file-stats", file_stats);\r
+HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats);\r
+HTTPD_CGI_CALL(net, "net-stats", net_stats);\r
+HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats );\r
+HTTPD_CGI_CALL(run, "run-time", run_time );\r
+HTTPD_CGI_CALL(io, "led-io", led_io );\r
+\r
+\r
+static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &run, &io, NULL };\r
+\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(nullfunction(struct httpd_state *s, char *ptr))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+  ( void ) ptr;\r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+httpd_cgifunction\r
+httpd_cgi(char *name)\r
+{\r
+  const struct httpd_cgi_call **f;\r
+\r
+  /* Find the matching name in the table, return the function. */\r
+  for(f = calls; *f != NULL; ++f) {\r
+    if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) {\r
+      return (*f)->function;\r
+    }\r
+  }\r
+  return nullfunction;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_file_stats(void *arg)\r
+{\r
+  char *f = (char *)arg;\r
+  return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f));\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(file_stats(struct httpd_state *s, char *ptr))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+\r
+  PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1);\r
+  \r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static const char closed[] =   /*  "CLOSED",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0};\r
+static const char syn_rcvd[] = /*  "SYN-RCVD",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56,\r
+ 0x44,  0};\r
+static const char syn_sent[] = /*  "SYN-SENT",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e,\r
+ 0x54,  0};\r
+static const char established[] = /*  "ESTABLISHED",*/\r
+{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48,\r
+ 0x45, 0x44, 0};\r
+static const char fin_wait_1[] = /*  "FIN-WAIT-1",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,\r
+ 0x54, 0x2d, 0x31, 0};\r
+static const char fin_wait_2[] = /*  "FIN-WAIT-2",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,\r
+ 0x54, 0x2d, 0x32, 0};\r
+static const char closing[] = /*  "CLOSING",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x49,\r
+ 0x4e, 0x47, 0};\r
+static const char time_wait[] = /*  "TIME-WAIT,"*/\r
+{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41,\r
+ 0x49, 0x54, 0};\r
+static const char last_ack[] = /*  "LAST-ACK"*/\r
+{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43,\r
+ 0x4b, 0};\r
+\r
+static const char *states[] = {\r
+  closed,\r
+  syn_rcvd,\r
+  syn_sent,\r
+  established,\r
+  fin_wait_1,\r
+  fin_wait_2,\r
+  closing,\r
+  time_wait,\r
+  last_ack};\r
+  \r
+\r
+static unsigned short\r
+generate_tcp_stats(void *arg)\r
+{\r
+  struct uip_conn *conn;\r
+  struct httpd_state *s = (struct httpd_state *)arg;\r
+    \r
+  conn = &uip_conns[s->count];\r
+  return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE,\r
+                "<tr><td>%d</td><td>%u.%u.%u.%u:%u</td><td>%s</td><td>%u</td><td>%u</td><td>%c %c</td></tr>\r\n",\r
+                htons(conn->lport),\r
+                htons(conn->ripaddr[0]) >> 8,\r
+                htons(conn->ripaddr[0]) & 0xff,\r
+                htons(conn->ripaddr[1]) >> 8,\r
+                htons(conn->ripaddr[1]) & 0xff,\r
+                htons(conn->rport),\r
+                states[conn->tcpstateflags & UIP_TS_MASK],\r
+                conn->nrtx,\r
+                conn->timer,\r
+                (uip_outstanding(conn))? '*':' ',\r
+                (uip_stopped(conn))? '!':' ');\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr))\r
+{\r
+  \r
+  PSOCK_BEGIN(&s->sout);\r
+  ( void ) ptr;\r
+  for(s->count = 0; s->count < UIP_CONNS; ++s->count) {\r
+    if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) {\r
+      PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s);\r
+    }\r
+  }\r
+\r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_net_stats(void *arg)\r
+{\r
+  struct httpd_state *s = (struct httpd_state *)arg;\r
+  return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE,\r
+                 "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]);\r
+}\r
+\r
+static\r
+PT_THREAD(net_stats(struct httpd_state *s, char *ptr))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+\r
+  ( void ) ptr;\r
+#if UIP_STATISTICS\r
+\r
+  for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t);\r
+      ++s->count) {\r
+    PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s);\r
+  }\r
+  \r
+#endif /* UIP_STATISTICS */\r
+  \r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+extern void vTaskList( signed char *pcWriteBuffer );\r
+static char cCountBuf[ 32 ];\r
+long lRefreshCount = 0;\r
+static unsigned short\r
+generate_rtos_stats(void *arg)\r
+{\r
+       ( void ) arg;\r
+       lRefreshCount++;\r
+       sprintf( cCountBuf, "<p><br>Refresh count = %d", (int)lRefreshCount );\r
+    vTaskList( uip_appdata );\r
+       strcat( uip_appdata, cCountBuf );\r
+  \r
+       return strlen( uip_appdata );\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+\r
+static\r
+PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+  ( void ) ptr;\r
+  PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL);  \r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+char *pcStatus[ 3 ];\r
+unsigned long ulString;\r
+extern unsigned long uxParTextGetLED( unsigned long uxLED );\r
+\r
+static unsigned short generate_io_state( void *arg )\r
+{\r
+       ( void ) arg;\r
+       \r
+//     for( ulString = 0; ulString < 3; ulString++ )\r
+//     {\r
+//             if( uxParTextGetLED( ulString + 5 ) )\r
+//             {\r
+//                     pcStatus[ ulString ] = "checked";\r
+//             }\r
+//             else\r
+//             {\r
+//                     pcStatus[ ulString ] = "";\r
+//             }\r
+//     }\r
+\r
+       sprintf( uip_appdata,\r
+               "<input type=\"checkbox\" name=\"LED0\" value=\"1\" %s>LED 2.5,"\\r
+               "<input type=\"checkbox\" name=\"LED1\" value=\"1\" %s>LED 2.6,"\\r
+               "<input type=\"checkbox\" name=\"LED2\" value=\"1\" %s>LED 2.7"\\r
+               "<p>"\\r
+               "<input type=\"text\" name=\"LCD\" value=\"Enter LCD text\" size=\"16\">",\r
+               pcStatus[ 0 ], \r
+               pcStatus[ 1 ], \r
+               pcStatus[ 2 ] );\r
+\r
+       return strlen( uip_appdata );\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+extern void vTaskGetRunTimeStats( signed char *pcWriteBuffer );\r
+static unsigned short\r
+generate_runtime_stats(void *arg)\r
+{\r
+       ( void ) arg;\r
+       lRefreshCount++;\r
+       sprintf( cCountBuf, "<p><br>Refresh count = %d", (int)lRefreshCount );\r
+    vTaskGetRunTimeStats( uip_appdata );\r
+       strcat( uip_appdata, cCountBuf );\r
+\r
+       return strlen( uip_appdata );\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+\r
+static\r
+PT_THREAD(run_time(struct httpd_state *s, char *ptr))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+  ( void ) ptr;\r
+  PSOCK_GENERATOR_SEND(&s->sout, generate_runtime_stats, NULL);\r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+\r
+static PT_THREAD(led_io(struct httpd_state *s, char *ptr))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+  ( void ) ptr;\r
+  PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL);\r
+  PSOCK_END(&s->sout);\r
+}\r
+\r
+/** @} */\r
+\r
+\r
+\r
+\r
+\r
+\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-cgi.h b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-cgi.h
new file mode 100644 (file)
index 0000000..7ae9283
--- /dev/null
@@ -0,0 +1,84 @@
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *         Web server script interface header file\r
+ * \author\r
+ *         Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ *    products derived from this software without specific prior\r
+ *    written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __HTTPD_CGI_H__\r
+#define __HTTPD_CGI_H__\r
+\r
+#include "psock.h"\r
+#include "httpd.h"\r
+\r
+typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *));\r
+\r
+httpd_cgifunction httpd_cgi(char *name);\r
+\r
+struct httpd_cgi_call {\r
+  const char *name;\r
+  const httpd_cgifunction function;\r
+};\r
+\r
+/**\r
+ * \brief      HTTPD CGI function declaration\r
+ * \param name The C variable name of the function\r
+ * \param str  The string name of the function, used in the script file\r
+ * \param function A pointer to the function that implements it\r
+ *\r
+ *             This macro is used for declaring a HTTPD CGI\r
+ *             function. This function is then added to the list of\r
+ *             HTTPD CGI functions with the httpd_cgi_add() function.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define HTTPD_CGI_CALL(name, str, function) \\r
+static PT_THREAD(function(struct httpd_state *, char *)); \\r
+static const struct httpd_cgi_call name = {str, function}\r
+\r
+void httpd_cgi_init(void);\r
+#endif /* __HTTPD_CGI_H__ */\r
+\r
+/** @} */\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs.c b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs.c
new file mode 100644 (file)
index 0000000..dc4aef0
--- /dev/null
@@ -0,0 +1,132 @@
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ *    may be used to endorse or promote products derived from this software\r
+ *    without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+\r
+#include "httpd.h"\r
+#include "httpd-fs.h"\r
+#include "httpd-fsdata.h"\r
+\r
+#ifndef NULL\r
+#define NULL 0\r
+#endif /* NULL */\r
+\r
+#include "httpd-fsdata.c"\r
+\r
+#if HTTPD_FS_STATISTICS\r
+static u16_t count[HTTPD_FS_NUMFILES];\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+static u8_t\r
+httpd_fs_strcmp(const char *str1, const char *str2)\r
+{\r
+  u8_t i;\r
+  i = 0;\r
+ loop:\r
+\r
+  if(str2[i] == 0 ||\r
+     str1[i] == '\r' ||\r
+     str1[i] == '\n') {\r
+    return 0;\r
+  }\r
+\r
+  if(str1[i] != str2[i]) {\r
+    return 1;\r
+  }\r
+\r
+\r
+  ++i;\r
+  goto loop;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+int\r
+httpd_fs_open(const char *name, struct httpd_fs_file *file)\r
+{\r
+#if HTTPD_FS_STATISTICS\r
+  u16_t i = 0;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+  struct httpd_fsdata_file_noconst *f;\r
+\r
+  for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;\r
+      f != NULL;\r
+      f = (struct httpd_fsdata_file_noconst *)f->next) {\r
+\r
+    if(httpd_fs_strcmp(name, f->name) == 0) {\r
+      file->data = f->data;\r
+      file->len = f->len;\r
+#if HTTPD_FS_STATISTICS\r
+      ++count[i];\r
+#endif /* HTTPD_FS_STATISTICS */\r
+      return 1;\r
+    }\r
+#if HTTPD_FS_STATISTICS\r
+    ++i;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+  }\r
+  return 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+httpd_fs_init(void)\r
+{\r
+#if HTTPD_FS_STATISTICS\r
+  u16_t i;\r
+  for(i = 0; i < HTTPD_FS_NUMFILES; i++) {\r
+    count[i] = 0;\r
+  }\r
+#endif /* HTTPD_FS_STATISTICS */\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+#if HTTPD_FS_STATISTICS\r
+u16_t httpd_fs_count\r
+(char *name)\r
+{\r
+  struct httpd_fsdata_file_noconst *f;\r
+  u16_t i;\r
+\r
+  i = 0;\r
+  for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;\r
+      f != NULL;\r
+      f = (struct httpd_fsdata_file_noconst *)f->next) {\r
+\r
+    if(httpd_fs_strcmp(name, f->name) == 0) {\r
+      return count[i];\r
+    }\r
+    ++i;\r
+  }\r
+  return 0;\r
+}\r
+#endif /* HTTPD_FS_STATISTICS */\r
+/*-----------------------------------------------------------------------------------*/\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs.h b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs.h
new file mode 100644 (file)
index 0000000..b594eea
--- /dev/null
@@ -0,0 +1,57 @@
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ *    may be used to endorse or promote products derived from this software\r
+ *    without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+#ifndef __HTTPD_FS_H__\r
+#define __HTTPD_FS_H__\r
+\r
+#define HTTPD_FS_STATISTICS 1\r
+\r
+struct httpd_fs_file {\r
+  char *data;\r
+  int len;\r
+};\r
+\r
+/* file must be allocated by caller and will be filled in\r
+   by the function. */\r
+int httpd_fs_open(const char *name, struct httpd_fs_file *file);\r
+\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+u16_t httpd_fs_count(char *name);\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+void httpd_fs_init(void);\r
+\r
+#endif /* __HTTPD_FS_H__ */\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/404.html b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/404.html
new file mode 100644 (file)
index 0000000..43e7f4c
--- /dev/null
@@ -0,0 +1,8 @@
+<html>\r
+  <body bgcolor="white">\r
+    <center>\r
+      <h1>404 - file not found</h1>\r
+      <h3>Go <a href="/">here</a> instead.</h3>\r
+    </center>\r
+  </body>\r
+</html>
\ No newline at end of file
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/index.html b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/index.html
new file mode 100644 (file)
index 0000000..4937dc6
--- /dev/null
@@ -0,0 +1,13 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+  <head>\r
+    <title>FreeRTOS.org uIP WEB server demo</title>\r
+  </head>\r
+  <BODY onLoad="window.setTimeout(&quot;location.href='index.shtml'&quot;,100)">\r
+<font face="arial">\r
+Loading index.shtml.  Click <a href="index.shtml">here</a> if not automatically redirected.\r
+</font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/index.shtml b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/index.shtml
new file mode 100644 (file)
index 0000000..29d242c
--- /dev/null
@@ -0,0 +1,20 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+  <head>\r
+    <title>FreeRTOS.org uIP WEB server demo</title>\r
+  </head>\r
+  <BODY onLoad="window.setTimeout(&quot;location.href='index.shtml'&quot;,2000)">\r
+<font face="arial">\r
+<a href="index.shtml">Task Stats</a> <b>|</b> <a href="runtime.shtml">Run Time Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br><p>\r
+<h2>Task statistics</h2>\r
+Page will refresh every 2 seconds.<p>\r
+<font face="courier"><pre>Task          State  Priority  Stack #<br>************************************************<br>\r
+%! rtos-stats\r
+</pre></font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/io.shtml b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/io.shtml
new file mode 100644 (file)
index 0000000..fd0697d
--- /dev/null
@@ -0,0 +1,28 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+  <head>\r
+    <title>FreeRTOS.org uIP WEB server demo</title>\r
+  </head>\r
+  <BODY>\r
+<font face="arial">\r
+<a href="index.shtml">Task Stats</a> <b>|</b> <a href="runtime.shtml">Run Time Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<b>LED and LCD IO</b><br>\r
+\r
+<p>\r
+\r
+Use the check box to turn on or off the LED, enter text to display on the OLED display, then click "Update IO".\r
+\r
+\r
+<p>\r
+<form name="aForm" action="/io.shtml" method="get">\r
+%! led-io\r
+<p>\r
+<input type="submit" value="Update IO">\r
+</form>\r
+<br><p>\r
+</font>\r
+</body>\r
+</html>\r
+\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/runtime.shtml b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/runtime.shtml
new file mode 100644 (file)
index 0000000..67cae46
--- /dev/null
@@ -0,0 +1,20 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+  <head>\r
+    <title>FreeRTOS.org uIP WEB server demo</title>\r
+  </head>\r
+  <BODY onLoad="window.setTimeout(&quot;location.href='runtime.shtml'&quot;,2000)">\r
+<font face="arial">\r
+<a href="index.shtml">Task Stats</a> <b>|</b> <a href="runtime.shtml">Run Time Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br><p>\r
+<h2>Run-time statistics</h2>\r
+Page will refresh every 2 seconds.<p>\r
+<font face="courier"><pre>Task            Abs Time      % Time<br>****************************************<br>\r
+%! run-time\r
+</pre></font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/stats.shtml b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/stats.shtml
new file mode 100644 (file)
index 0000000..d95a693
--- /dev/null
@@ -0,0 +1,41 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+  <head>\r
+    <title>FreeRTOS.org uIP WEB server demo</title>\r
+  </head>\r
+  <BODY>\r
+<font face="arial">\r
+<a href="index.shtml">Task Stats</a> <b>|</b> <a href="runtime.shtml">Run Time Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br><p>\r
+<h2>Network statistics</h2>\r
+<table width="300" border="0">\r
+<tr><td align="left"><font face="courier"><pre>\r
+IP           Packets dropped\r
+             Packets received\r
+             Packets sent\r
+IP errors    IP version/header length\r
+             IP length, high byte\r
+             IP length, low byte\r
+             IP fragments\r
+             Header checksum\r
+             Wrong protocol\r
+ICMP        Packets dropped\r
+             Packets received\r
+             Packets sent\r
+             Type errors\r
+TCP          Packets dropped\r
+             Packets received\r
+             Packets sent\r
+             Checksum errors\r
+             Data packets without ACKs\r
+             Resets\r
+             Retransmissions\r
+            No connection avaliable\r
+            Connection attempts to closed ports\r
+</pre></font></td><td><pre>%! net-stats\r
+</pre></table>\r
+</font>\r
+</body>\r
+</html>\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/tcp.shtml b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fs/tcp.shtml
new file mode 100644 (file)
index 0000000..4105367
--- /dev/null
@@ -0,0 +1,21 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+  <head>\r
+    <title>FreeRTOS.org uIP WEB server demo</title>\r
+  </head>\r
+  <BODY>\r
+<font face="arial">\r
+<a href="index.shtml">Task Stats</a> <b>|</b> <a href="runtime.shtml">Run Time Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br>\r
+<h2>Network connections</h2>\r
+<p>\r
+<table>\r
+<tr><th>Local</th><th>Remote</th><th>State</th><th>Retransmissions</th><th>Timer</th><th>Flags</th></tr>\r
+%! tcp-connections\r
+</pre></font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fsdata.c b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fsdata.c
new file mode 100644 (file)
index 0000000..fe254f6
--- /dev/null
@@ -0,0 +1,557 @@
+static const char data_404_html[] = {\r
+       /* /404.html */\r
+       0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,\r
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+       0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x69, 0x6e, 0x73, 0x74, 0x65, \r
+       0x61, 0x64, 0x2e, 0x3c, 0x2f, 0x68, 0x33, 0x3e, 0xa, 0x20, \r
+       0x20, 0x20, 0x20, 0x3c, 0x2f, 0x63, 0x65, 0x6e, 0x74, 0x65, \r
+       0x72, 0x3e, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x62, 0x6f, 0x64, \r
+       0x79, 0x3e, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+0};\r
+\r
+static const char data_index_html[] = {\r
+       /* /index.html */\r
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+       0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0xa, 0};\r
+\r
+static const char data_index_shtml[] = {\r
+       /* /index.shtml */\r
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+\r
+static const char data_io_shtml[] = {\r
+       /* /io.shtml */\r
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+\r
+static const char data_runtime_shtml[] = {\r
+       /* /runtime.shtml */\r
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+\r
+static const char data_stats_shtml[] = {\r
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+\r
+static const char data_tcp_shtml[] = {\r
+       /* /tcp.shtml */\r
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+       0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x48, 0x6f, 0x6d, 0x65, \r
+       0x70, 0x61, 0x67, 0x65, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, \r
+       0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, \r
+       0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6f, 0x2e, \r
+       0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x49, 0x4f, 0x3c, \r
+       0x2f, 0x61, 0x3e, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x70, \r
+       0x3e, 0xa, 0x3c, 0x68, 0x72, 0x3e, 0xa, 0x3c, 0x62, 0x72, \r
+       0x3e, 0xa, 0x3c, 0x68, 0x32, 0x3e, 0x4e, 0x65, 0x74, 0x77, \r
+       0x6f, 0x72, 0x6b, 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, \r
+       0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, \r
+       0xa, 0x3c, 0x70, 0x3e, 0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, \r
+       0x65, 0x3e, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x68, \r
+       0x3e, 0x4c, 0x6f, 0x63, 0x61, 0x6c, 0x3c, 0x2f, 0x74, 0x68, \r
+       0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x6d, 0x6f, 0x74, \r
+       0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, \r
+       0x53, 0x74, 0x61, 0x74, 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, \r
+       0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x74, 0x72, 0x61, 0x6e, \r
+       0x73, 0x6d, 0x69, 0x73, 0x73, 0x69, 0x6f, 0x6e, 0x73, 0x3c, \r
+       0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x54, 0x69, \r
+       0x6d, 0x65, 0x72, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, \r
+       0x68, 0x3e, 0x46, 0x6c, 0x61, 0x67, 0x73, 0x3c, 0x2f, 0x74, \r
+       0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xa, 0x25, 0x21, \r
+       0x20, 0x74, 0x63, 0x70, 0x2d, 0x63, 0x6f, 0x6e, 0x6e, 0x65, \r
+       0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0xa, 0x3c, 0x2f, 0x70, \r
+       0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, \r
+       0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xa, 0x3c, \r
+       0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xa, 0x3c, 0x2f, 0x68, \r
+       0x74, 0x6d, 0x6c, 0x3e, 0xa, 0xa, 0};\r
+\r
+const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10, 0}};\r
+\r
+const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12, 0}};\r
+\r
+const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13, 0}};\r
+\r
+const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10, 0}};\r
+\r
+const struct httpd_fsdata_file file_runtime_shtml[] = {{file_io_shtml, data_runtime_shtml, data_runtime_shtml + 15, sizeof(data_runtime_shtml) - 15, 0}};\r
+\r
+const struct httpd_fsdata_file file_stats_shtml[] = {{file_runtime_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13, 0}};\r
+\r
+const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11, 0}};\r
+\r
+#define HTTPD_FS_ROOT file_tcp_shtml\r
+\r
+#define HTTPD_FS_NUMFILES 7\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fsdata.h b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd-fsdata.h
new file mode 100644 (file)
index 0000000..52d35c2
--- /dev/null
@@ -0,0 +1,64 @@
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ *    may be used to endorse or promote products derived from this software\r
+ *    without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+#ifndef __HTTPD_FSDATA_H__\r
+#define __HTTPD_FSDATA_H__\r
+\r
+#include "uip.h"\r
+\r
+struct httpd_fsdata_file {\r
+  const struct httpd_fsdata_file *next;\r
+  const char *name;\r
+  const char *data;\r
+  const int len;\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+  u16_t count;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+};\r
+\r
+struct httpd_fsdata_file_noconst {\r
+  struct httpd_fsdata_file *next;\r
+  char *name;\r
+  char *data;\r
+  int len;\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+  u16_t count;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+};\r
+\r
+#endif /* __HTTPD_FSDATA_H__ */\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd.c b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd.c
new file mode 100644 (file)
index 0000000..644cf16
--- /dev/null
@@ -0,0 +1,346 @@
+/**\r
+ * \addtogroup apps\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \defgroup httpd Web server\r
+ * @{\r
+ * The uIP web server is a very simplistic implementation of an HTTP\r
+ * server. It can serve web pages and files from a read-only ROM\r
+ * filesystem, and provides a very small scripting language.\r
+\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *         Web server\r
+ * \author\r
+ *         Adam Dunkels <adam@sics.se>\r
+ */\r
+\r
+\r
+/*\r
+ * Copyright (c) 2004, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ *    may be used to endorse or promote products derived from this software\r
+ *    without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ */\r
+\r
+#include "uip.h"\r
+#include "httpd.h"\r
+#include "httpd-fs.h"\r
+#include "httpd-cgi.h"\r
+#include "http-strings.h"\r
+\r
+#include <string.h>\r
+\r
+#define STATE_WAITING 0\r
+#define STATE_OUTPUT  1\r
+\r
+#define ISO_nl      0x0a\r
+#define ISO_space   0x20\r
+#define ISO_bang    0x21\r
+#define ISO_percent 0x25\r
+#define ISO_period  0x2e\r
+#define ISO_slash   0x2f\r
+#define ISO_colon   0x3a\r
+\r
+\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_part_of_file(void *state)\r
+{\r
+  struct httpd_state *s = (struct httpd_state *)state;\r
+\r
+  if(s->file.len > uip_mss()) {\r
+    s->len = uip_mss();\r
+  } else {\r
+    s->len = s->file.len;\r
+  }\r
+  memcpy(uip_appdata, s->file.data, s->len);\r
+  \r
+  return s->len;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_file(struct httpd_state *s))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+  \r
+  do {\r
+    PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s);\r
+    s->file.len -= s->len;\r
+    s->file.data += s->len;\r
+  } while(s->file.len > 0);\r
+      \r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_part_of_file(struct httpd_state *s))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+\r
+  PSOCK_SEND(&s->sout, s->file.data, s->len);\r
+  \r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static void\r
+next_scriptstate(struct httpd_state *s)\r
+{\r
+  char *p;\r
+  p = strchr(s->scriptptr, ISO_nl) + 1;\r
+  s->scriptlen -= (unsigned short)(p - s->scriptptr);\r
+  s->scriptptr = p;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_script(struct httpd_state *s))\r
+{\r
+  char *ptr;\r
+  \r
+  PT_BEGIN(&s->scriptpt);\r
+\r
+\r
+  while(s->file.len > 0) {\r
+\r
+    /* Check if we should start executing a script. */\r
+    if(*s->file.data == ISO_percent &&\r
+       *(s->file.data + 1) == ISO_bang) {\r
+      s->scriptptr = s->file.data + 3;\r
+      s->scriptlen = s->file.len - 3;\r
+      if(*(s->scriptptr - 1) == ISO_colon) {\r
+       httpd_fs_open(s->scriptptr + 1, &s->file);\r
+       PT_WAIT_THREAD(&s->scriptpt, send_file(s));\r
+      } else {\r
+       PT_WAIT_THREAD(&s->scriptpt,\r
+                      httpd_cgi(s->scriptptr)(s, s->scriptptr));\r
+      }\r
+      next_scriptstate(s);\r
+      \r
+      /* The script is over, so we reset the pointers and continue\r
+        sending the rest of the file. */\r
+      s->file.data = s->scriptptr;\r
+      s->file.len = s->scriptlen;\r
+    } else {\r
+      /* See if we find the start of script marker in the block of HTML\r
+        to be sent. */\r
+\r
+      if(s->file.len > uip_mss()) {\r
+       s->len = uip_mss();\r
+      } else {\r
+       s->len = s->file.len;\r
+      }\r
+\r
+      if(*s->file.data == ISO_percent) {\r
+       ptr = strchr(s->file.data + 1, ISO_percent);\r
+      } else {\r
+       ptr = strchr(s->file.data, ISO_percent);\r
+      }\r
+      if(ptr != NULL &&\r
+        ptr != s->file.data) {\r
+       s->len = (int)(ptr - s->file.data);\r
+       if(s->len >= uip_mss()) {\r
+         s->len = uip_mss();\r
+       }\r
+      }\r
+      PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s));\r
+      s->file.data += s->len;\r
+      s->file.len -= s->len;\r
+      \r
+    }\r
+  }\r
+  \r
+  PT_END(&s->scriptpt);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr))\r
+{\r
+  char *ptr;\r
+\r
+  PSOCK_BEGIN(&s->sout);\r
+\r
+  PSOCK_SEND_STR(&s->sout, statushdr);\r
+\r
+  ptr = strrchr(s->filename, ISO_period);\r
+  if(ptr == NULL) {\r
+    PSOCK_SEND_STR(&s->sout, http_content_type_binary);\r
+  } else if(strncmp(http_html, ptr, 5) == 0 ||\r
+           strncmp(http_shtml, ptr, 6) == 0) {\r
+    PSOCK_SEND_STR(&s->sout, http_content_type_html);\r
+  } else if(strncmp(http_css, ptr, 4) == 0) {\r
+    PSOCK_SEND_STR(&s->sout, http_content_type_css);\r
+  } else if(strncmp(http_png, ptr, 4) == 0) {\r
+    PSOCK_SEND_STR(&s->sout, http_content_type_png);\r
+  } else if(strncmp(http_gif, ptr, 4) == 0) {\r
+    PSOCK_SEND_STR(&s->sout, http_content_type_gif);\r
+  } else if(strncmp(http_jpg, ptr, 4) == 0) {\r
+    PSOCK_SEND_STR(&s->sout, http_content_type_jpg);\r
+  } else {\r
+    PSOCK_SEND_STR(&s->sout, http_content_type_plain);\r
+  }\r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_output(struct httpd_state *s))\r
+{\r
+  char *ptr;\r
+  \r
+  PT_BEGIN(&s->outputpt);\r
\r
+  if(!httpd_fs_open(s->filename, &s->file)) {\r
+    httpd_fs_open(http_404_html, &s->file);\r
+    strcpy(s->filename, http_404_html);\r
+    PT_WAIT_THREAD(&s->outputpt,\r
+                  send_headers(s,\r
+                  http_header_404));\r
+    PT_WAIT_THREAD(&s->outputpt,\r
+                  send_file(s));\r
+  } else {\r
+    PT_WAIT_THREAD(&s->outputpt,\r
+                  send_headers(s,\r
+                  http_header_200));\r
+    ptr = strchr(s->filename, ISO_period);\r
+    if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) {\r
+      PT_INIT(&s->scriptpt);\r
+      PT_WAIT_THREAD(&s->outputpt, handle_script(s));\r
+    } else {\r
+      PT_WAIT_THREAD(&s->outputpt,\r
+                    send_file(s));\r
+    }\r
+  }\r
+  PSOCK_CLOSE(&s->sout);\r
+  PT_END(&s->outputpt);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_input(struct httpd_state *s))\r
+{\r
+  PSOCK_BEGIN(&s->sin);\r
+\r
+  PSOCK_READTO(&s->sin, ISO_space);\r
+\r
+  \r
+  if(strncmp(s->inputbuf, http_get, 4) != 0) {\r
+    PSOCK_CLOSE_EXIT(&s->sin);\r
+  }\r
+  PSOCK_READTO(&s->sin, ISO_space);\r
+\r
+  if(s->inputbuf[0] != ISO_slash) {\r
+    PSOCK_CLOSE_EXIT(&s->sin);\r
+  }\r
+\r
+  if(s->inputbuf[1] == ISO_space) {\r
+    strncpy(s->filename, http_index_html, sizeof(s->filename));\r
+  } else {\r
+\r
+    s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0;\r
+\r
+    /* Process any form input being sent to the server. */\r
+    {\r
+        extern void vApplicationProcessFormInput( char *pcInputString, long xInputLength );\r
+        vApplicationProcessFormInput( s->inputbuf, PSOCK_DATALEN(&s->sin) );\r
+    }\r
+\r
+    strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename));\r
+  }\r
+\r
+  /*  httpd_log_file(uip_conn->ripaddr, s->filename);*/\r
+  \r
+  s->state = STATE_OUTPUT;\r
+\r
+  while(1) {\r
+    PSOCK_READTO(&s->sin, ISO_nl);\r
+\r
+    if(strncmp(s->inputbuf, http_referer, 8) == 0) {\r
+      s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0;\r
+      /*      httpd_log(&s->inputbuf[9]);*/\r
+    }\r
+  }\r
+  \r
+  PSOCK_END(&s->sin);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static void\r
+handle_connection(struct httpd_state *s)\r
+{\r
+  handle_input(s);\r
+  if(s->state == STATE_OUTPUT) {\r
+    handle_output(s);\r
+  }\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+void\r
+httpd_appcall(void)\r
+{\r
+  struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate);\r
+\r
+  if(uip_closed() || uip_aborted() || uip_timedout()) {\r
+  } else if(uip_connected()) {\r
+    PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1);\r
+    PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1);\r
+    PT_INIT(&s->outputpt);\r
+    s->state = STATE_WAITING;\r
+    /*    timer_set(&s->timer, CLOCK_SECOND * 100);*/\r
+    s->timer = 0;\r
+    handle_connection(s);\r
+  } else if(s != NULL) {\r
+    if(uip_poll()) {\r
+      ++s->timer;\r
+      if(s->timer >= 20) {\r
+       uip_abort();\r
+      }\r
+    } else {\r
+      s->timer = 0;\r
+    }\r
+    handle_connection(s);\r
+  } else {\r
+    uip_abort();\r
+  }\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+/**\r
+ * \brief      Initialize the web server\r
+ *\r
+ *             This function initializes the web server and should be\r
+ *             called at system boot-up.\r
+ */\r
+void\r
+httpd_init(void)\r
+{\r
+  uip_listen(HTONS(80));\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+/** @} */\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd.h b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/httpd.h
new file mode 100644 (file)
index 0000000..7f7a666
--- /dev/null
@@ -0,0 +1,62 @@
+/*\r
+ * Copyright (c) 2001-2005, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ *    products derived from this software without specific prior\r
+ *    written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __HTTPD_H__\r
+#define __HTTPD_H__\r
+\r
+#include "psock.h"\r
+#include "httpd-fs.h"\r
+\r
+struct httpd_state {\r
+  unsigned char timer;\r
+  struct psock sin, sout;\r
+  struct pt outputpt, scriptpt;\r
+  char inputbuf[50];\r
+  char filename[20];\r
+  char state;\r
+  struct httpd_fs_file file;\r
+  int len;\r
+  char *scriptptr;\r
+  int scriptlen;\r
+  \r
+  unsigned short count;\r
+};\r
+\r
+void httpd_init(void);\r
+void httpd_appcall(void);\r
+\r
+void httpd_log(char *msg);\r
+void httpd_log_file(u16_t *requester, char *file);\r
+\r
+#endif /* __HTTPD_H__ */\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/makefsdata b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/makefsdata
new file mode 100644 (file)
index 0000000..8d2715a
--- /dev/null
@@ -0,0 +1,78 @@
+#!/usr/bin/perl\r
+\r
+open(OUTPUT, "> httpd-fsdata.c");\r
+\r
+chdir("httpd-fs");\r
+\r
+opendir(DIR, ".");\r
+@files =  grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);\r
+closedir(DIR);\r
+\r
+foreach $file (@files) {  \r
+   \r
+    if(-d $file && $file !~ /^\./) {\r
+       print "Processing directory $file\n";\r
+       opendir(DIR, $file);\r
+       @newfiles =  grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);\r
+       closedir(DIR);\r
+       printf "Adding files @newfiles\n";\r
+       @files = (@files, map { $_ = "$file/$_" } @newfiles);\r
+       next;\r
+    }\r
+}\r
+\r
+foreach $file (@files) {\r
+    if(-f $file) {\r
+       \r
+       print "Adding file $file\n";\r
+       \r
+       open(FILE, $file) || die "Could not open file $file\n";\r
+\r
+       $file =~ s-^-/-;\r
+       $fvar = $file;\r
+       $fvar =~ s-/-_-g;\r
+       $fvar =~ s-\.-_-g;\r
+       # for AVR, add PROGMEM here\r
+       print(OUTPUT "static const unsigned char data".$fvar."[] = {\n");\r
+       print(OUTPUT "\t/* $file */\n\t");\r
+       for($j = 0; $j < length($file); $j++) {\r
+           printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1)));\r
+       }\r
+       printf(OUTPUT "0,\n");\r
+       \r
+       \r
+       $i = 0;        \r
+       while(read(FILE, $data, 1)) {\r
+           if($i == 0) {\r
+               print(OUTPUT "\t");\r
+           }\r
+           printf(OUTPUT "%#02x, ", unpack("C", $data));\r
+           $i++;\r
+           if($i == 10) {\r
+               print(OUTPUT "\n");\r
+               $i = 0;\r
+           }\r
+       }\r
+       print(OUTPUT "0};\n\n");\r
+       close(FILE);\r
+       push(@fvars, $fvar);\r
+       push(@pfiles, $file);\r
+    }\r
+}\r
+\r
+for($i = 0; $i < @fvars; $i++) {\r
+    $file = $pfiles[$i];\r
+    $fvar = $fvars[$i];\r
+\r
+    if($i == 0) {\r
+        $prevfile = "NULL";\r
+    } else {\r
+        $prevfile = "file" . $fvars[$i - 1];\r
+    }\r
+    print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, ");\r
+    print(OUTPUT "data$fvar + ". (length($file) + 1) .", ");\r
+    print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n");\r
+}\r
+\r
+print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n");\r
+print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n");\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/makestrings b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/makestrings
new file mode 100644 (file)
index 0000000..8a13c6d
--- /dev/null
@@ -0,0 +1,40 @@
+#!/usr/bin/perl\r
+\r
+\r
+sub stringify {\r
+  my $name = shift(@_);\r
+  open(OUTPUTC, "> $name.c");\r
+  open(OUTPUTH, "> $name.h");\r
+  \r
+  open(FILE, "$name");\r
+  \r
+  while(<FILE>) {\r
+    if(/(.+) "(.+)"/) {\r
+      $var = $1;\r
+      $data = $2;\r
+      \r
+      $datan = $data;\r
+      $datan =~ s/\\r/\r/g;\r
+      $datan =~ s/\\n/\n/g;\r
+      $datan =~ s/\\01/\01/g;      \r
+      $datan =~ s/\\0/\0/g;\r
+      \r
+      printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1);\r
+      printf(OUTPUTC "/* \"$data\" */\n");\r
+      printf(OUTPUTC "{");\r
+      for($j = 0; $j < length($datan); $j++) {\r
+       printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1)));\r
+      }\r
+      printf(OUTPUTC "};\n");\r
+      \r
+      printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1);\r
+      \r
+    }\r
+  }\r
+  close(OUTPUTC);\r
+  close(OUTPUTH);\r
+}\r
+stringify("http-strings");\r
+\r
+exit 0;\r
+\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/uIP_Task.c b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/uIP_Task.c
new file mode 100644 (file)
index 0000000..7f98cad
--- /dev/null
@@ -0,0 +1,357 @@
+/*\r
+       FreeRTOS.org V5.2.0 - Copyright (C) 2003-2009 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify it \r
+       under the terms of the GNU General Public License (version 2) as published\r
+       by the Free Software Foundation and modified by the FreeRTOS exception.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT\r
+       ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or \r
+       FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for \r
+       more details.\r
+\r
+       You should have received a copy of the GNU General Public License along \r
+       with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59 \r
+       Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
+\r
+       A special exception to the GPL is included to allow you to distribute a \r
+       combined work that includes FreeRTOS.org without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section\r
+       of http://www.FreeRTOS.org for full details.\r
+\r
+\r
+       ***************************************************************************\r
+       *                                                                         *\r
+       * Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *\r
+       *                                                                         *\r
+       * This is a concise, step by step, 'hands on' guide that describes both   *\r
+       * general multitasking concepts and FreeRTOS specifics. It presents and   *\r
+       * explains numerous examples that are written using the FreeRTOS API.     *\r
+       * Full source code for all the examples is provided in an accompanying    *\r
+       * .zip file.                                                              *\r
+       *                                                                         *\r
+       ***************************************************************************\r
+\r
+       1 tab == 4 spaces!\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
+       licensing and training services.\r
+*/\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* uip includes. */\r
+#include "uip.h"\r
+#include "uip_arp.h"\r
+#include "httpd.h"\r
+#include "timer.h"\r
+#include "clock-arch.h"\r
+\r
+/* Demo includes. */\r
+#include "emac.h"\r
+//#include "partest.h"\r
+\r
+//#include "LPC17xx_defs.h"\r
+#include "LPC17xx.h"\r
+#include "core_cm3.h"\r
+/*-----------------------------------------------------------*/\r
+\r
+/* MAC address configuration. */\r
+#define uipMAC_ADDR0   0x00\r
+#define uipMAC_ADDR1   0x12\r
+#define uipMAC_ADDR2   0x13\r
+#define uipMAC_ADDR3   0x10\r
+#define uipMAC_ADDR4   0x15\r
+#define uipMAC_ADDR5   0x11\r
+\r
+/* IP address configuration. */\r
+#define uipIP_ADDR0            192\r
+#define uipIP_ADDR1            168\r
+#define uipIP_ADDR2            0\r
+#define uipIP_ADDR3            200     \r
+\r
+/* How long to wait before attempting to connect the MAC again. */\r
+#define uipINIT_WAIT    100\r
+\r
+/* Shortcut to the header within the Rx buffer. */\r
+#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ])\r
+\r
+/* Standard constant. */\r
+#define uipTOTAL_FRAME_HEADER_SIZE     54\r
+\r
+\r
+#define MAC_INTENABLE       (*(volatile unsigned long *)(EMAC_BASE + 0xFE4)) /* Interrupt enable reg  */\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Send the uIP buffer to the MAC. \r
+ */\r
+static void prvENET_Send(void);\r
+\r
+/*\r
+ * Setup the MAC address in the MAC itself, and in the uIP stack.\r
+ */\r
+static void prvSetMACAddress( void );\r
+\r
+/*\r
+ * Port functions required by the uIP stack.\r
+ */\r
+void clock_init( void );\r
+clock_time_t clock_time( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The semaphore used by the ISR to wake the uIP task. */\r
+extern xSemaphoreHandle xEMACSemaphore;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void clock_init(void)\r
+{\r
+       /* This is done when the scheduler starts. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+clock_time_t clock_time( void )\r
+{\r
+       return xTaskGetTickCount();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vuIP_Task( void *pvParameters )\r
+{\r
+portBASE_TYPE i;\r
+uip_ipaddr_t xIPAddr;\r
+struct timer periodic_timer, arp_timer;\r
+extern void ( vEMAC_ISR_Wrapper )( void );\r
+\r
+       ( void ) pvParameters;\r
+\r
+       /* Create the semaphore used by the ISR to wake this task. */\r
+       vSemaphoreCreateBinary( xEMACSemaphore );\r
+       \r
+       /* Initialise the uIP stack. */\r
+       timer_set( &periodic_timer, configTICK_RATE_HZ / 2 );\r
+       timer_set( &arp_timer, configTICK_RATE_HZ * 10 );\r
+       uip_init();\r
+       uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 );\r
+       uip_sethostaddr( xIPAddr );\r
+       httpd_init();\r
+\r
+       /* Initialise the MAC. */\r
+       while( Init_EMAC() != pdPASS )\r
+    {\r
+        vTaskDelay( uipINIT_WAIT );\r
+    }\r
+\r
+       portENTER_CRITICAL();\r
+       {\r
+               MAC_INTENABLE = INT_RX_DONE;\r
+               /* set the interrupt priority */\r
+               NVIC_SetPriority(ENET_IRQn, 255/*configMAX_SYSCALL_INTERRUPT_PRIORITY*/);\r
+               /* enable the interrupt */\r
+               NVIC_EnableIRQ(ENET_IRQn);\r
+               prvSetMACAddress();\r
+       }\r
+       portEXIT_CRITICAL();\r
+       \r
+\r
+       for( ;; )\r
+       {\r
+               /* Is there received data ready to be processed? */\r
+               uip_len = uiGetEMACRxData( uip_buf );\r
+               \r
+               if( uip_len > 0 )\r
+               {\r
+                       /* Standard uIP loop taken from the uIP manual. */\r
+                       if( xHeader->type == htons( UIP_ETHTYPE_IP ) )\r
+                       {\r
+                               uip_arp_ipin();\r
+                               uip_input();\r
+\r
+                               /* If the above function invocation resulted in data that \r
+                               should be sent out on the network, the global variable \r
+                               uip_len is set to a value > 0. */\r
+                               if( uip_len > 0 )\r
+                               {\r
+                                       uip_arp_out();\r
+                                       prvENET_Send();\r
+                               }\r
+                       }\r
+                       else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) )\r
+                       {\r
+                               uip_arp_arpin();\r
+\r
+                               /* If the above function invocation resulted in data that \r
+                               should be sent out on the network, the global variable \r
+                               uip_len is set to a value > 0. */\r
+                               if( uip_len > 0 )\r
+                               {\r
+                                       prvENET_Send();\r
+                               }\r
+                       }\r
+               }\r
+               else\r
+               {\r
+                       if( timer_expired( &periodic_timer ) )\r
+                       {\r
+                               timer_reset( &periodic_timer );\r
+                               for( i = 0; i < UIP_CONNS; i++ )\r
+                               {\r
+                                       uip_periodic( i );\r
+       \r
+                                       /* If the above function invocation resulted in data that \r
+                                       should be sent out on the network, the global variable \r
+                                       uip_len is set to a value > 0. */\r
+                                       if( uip_len > 0 )\r
+                                       {\r
+                                               uip_arp_out();\r
+                                               prvENET_Send();\r
+                                       }\r
+                               }       \r
+       \r
+                               /* Call the ARP timer function every 10 seconds. */\r
+                               if( timer_expired( &arp_timer ) )\r
+                               {\r
+                                       timer_reset( &arp_timer );\r
+                                       uip_arp_timer();\r
+                               }\r
+                       }\r
+                       else\r
+                       {                       \r
+                               /* We did not receive a packet, and there was no periodic\r
+                               processing to perform.  Block for a fixed period.  If a packet\r
+                               is received during this period we will be woken by the ISR\r
+                               giving us the Semaphore. */\r
+                               xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 );                       \r
+                       }\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvENET_Send(void)\r
+{\r
+    RequestSend();\r
+\r
+    /* Copy the header into the Tx buffer. */\r
+    CopyToFrame_EMAC( uip_buf, uipTOTAL_FRAME_HEADER_SIZE );\r
+    if( uip_len > uipTOTAL_FRAME_HEADER_SIZE )\r
+    {\r
+        CopyToFrame_EMAC( uip_appdata, ( uip_len - uipTOTAL_FRAME_HEADER_SIZE ) );\r
+    }\r
+\r
+    DoSend_EMAC( uip_len );\r
+    \r
+    RequestSend();\r
+\r
+    /* Copy the header into the Tx buffer. */\r
+    CopyToFrame_EMAC( uip_buf, uipTOTAL_FRAME_HEADER_SIZE );\r
+    if( uip_len > uipTOTAL_FRAME_HEADER_SIZE )\r
+    {\r
+        CopyToFrame_EMAC( uip_appdata, ( uip_len - uipTOTAL_FRAME_HEADER_SIZE ) );\r
+    }\r
+\r
+    DoSend_EMAC( uip_len );    \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetMACAddress( void )\r
+{\r
+struct uip_eth_addr xAddr;\r
+\r
+       /* Configure the MAC address in the uIP stack. */\r
+       xAddr.addr[ 0 ] = uipMAC_ADDR0;\r
+       xAddr.addr[ 1 ] = uipMAC_ADDR1;\r
+       xAddr.addr[ 2 ] = uipMAC_ADDR2;\r
+       xAddr.addr[ 3 ] = uipMAC_ADDR3;\r
+       xAddr.addr[ 4 ] = uipMAC_ADDR4;\r
+       xAddr.addr[ 5 ] = uipMAC_ADDR5;\r
+       uip_setethaddr( xAddr );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationProcessFormInput( portCHAR *pcInputString, portBASE_TYPE xInputLength )\r
+{\r
+char *c, *pcText;\r
+static portCHAR cMessageForDisplay[ 32 ];\r
+extern xQueueHandle xLCDQueue;\r
+//xLCDMessage xLCDMessage;\r
+\r
+       /* Process the form input sent by the IO page of the served HTML. */\r
+\r
+       c = strstr( pcInputString, "?" );\r
+    if( c )\r
+    {\r
+               /* Turn LED's on or off in accordance with the check box status. */\r
+               if( strstr( c, "LED0=1" ) != NULL )\r
+               {\r
+//                     vParTestSetLED( 5, 0 );\r
+               }\r
+               else\r
+               {\r
+//                     vParTestSetLED( 5, 1 );\r
+               }               \r
+               \r
+               if( strstr( c, "LED1=1" ) != NULL )\r
+               {\r
+//                     vParTestSetLED( 6, 0 );\r
+               }\r
+               else\r
+               {\r
+//                     vParTestSetLED( 6, 1 );\r
+               }               \r
+\r
+               if( strstr( c, "LED2=1" ) != NULL )\r
+               {\r
+//                     vParTestSetLED( 7, 0 );\r
+               }\r
+               else\r
+               {\r
+//                     vParTestSetLED( 7, 1 );\r
+               }\r
+\r
+               /* Find the start of the text to be displayed on the LCD. */\r
+        pcText = strstr( c, "LCD=" );\r
+        pcText += strlen( "LCD=" );\r
+\r
+        /* Terminate the file name for further processing within uIP. */\r
+        *c = 0x00;\r
+\r
+        /* Terminate the LCD string. */\r
+        c = strstr( pcText, " " );\r
+        if( c != NULL )\r
+        {\r
+            *c = 0x00;\r
+        }\r
+\r
+        /* Add required spaces. */\r
+        while( ( c = strstr( pcText, "+" ) ) != NULL )\r
+        {\r
+            *c = ' ';\r
+        }\r
+    \r
+        /* Write the message to the LCD. */\r
+//             strcpy( cMessageForDisplay, pcText );\r
+//             xLCDMessage.xColumn = 0;\r
+//             xLCDMessage.pcMessage = cMessageForDisplay;\r
+//        xQueueSend( xLCDQueue, &xLCDMessage, portMAX_DELAY );\r
+    }\r
+}\r
+\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/uip-conf.h b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/uip-conf.h
new file mode 100644 (file)
index 0000000..3e6f7f3
--- /dev/null
@@ -0,0 +1,157 @@
+/**\r
+ * \addtogroup uipopt\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Project-specific configuration options\r
+ * @{\r
+ *\r
+ * uIP has a number of configuration options that can be overridden\r
+ * for each project. These are kept in a project-specific uip-conf.h\r
+ * file and all configuration names have the prefix UIP_CONF.\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2006, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ *    may be used to endorse or promote products derived from this software\r
+ *    without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *         An example uIP configuration file\r
+ * \author\r
+ *         Adam Dunkels <adam@sics.se>\r
+ */\r
+\r
+#ifndef __UIP_CONF_H__\r
+#define __UIP_CONF_H__\r
+\r
+#include <stdint.h>\r
+\r
+/**\r
+ * 8 bit datatype\r
+ *\r
+ * This typedef defines the 8-bit type used throughout uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef uint8_t u8_t;\r
+\r
+/**\r
+ * 16 bit datatype\r
+ *\r
+ * This typedef defines the 16-bit type used throughout uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef uint16_t u16_t;\r
+\r
+/**\r
+ * Statistics datatype\r
+ *\r
+ * This typedef defines the dataype used for keeping statistics in\r
+ * uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef unsigned short uip_stats_t;\r
+\r
+/**\r
+ * Maximum number of TCP connections.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_MAX_CONNECTIONS 40\r
+\r
+/**\r
+ * Maximum number of listening TCP ports.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_MAX_LISTENPORTS 40\r
+\r
+/**\r
+ * uIP buffer size.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_BUFFER_SIZE     1480\r
+\r
+/**\r
+ * CPU byte order.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_BYTE_ORDER      LITTLE_ENDIAN\r
+\r
+/**\r
+ * Logging on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_LOGGING         0\r
+\r
+/**\r
+ * UDP support on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_UDP             0\r
+\r
+/**\r
+ * UDP checksums on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_UDP_CHECKSUMS   1\r
+\r
+/**\r
+ * uIP statistics on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_STATISTICS      1\r
+\r
+/* Here we include the header file for the application(s) we use in\r
+   our project. */\r
+/*#include "smtp.h"*/\r
+/*#include "hello-world.h"*/\r
+/*#include "telnetd.h"*/\r
+#include "webserver.h"\r
+/*#include "dhcpc.h"*/\r
+/*#include "resolv.h"*/\r
+/*#include "webclient.h"*/\r
+\r
+#endif /* __UIP_CONF_H__ */\r
+\r
+/** @} */\r
+/** @} */\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/webserver.h b/Demo/CORTEX_LPC1766_GCC_RedSuite/RTOSDemo/webserver/webserver.h
new file mode 100644 (file)
index 0000000..1acb290
--- /dev/null
@@ -0,0 +1,49 @@
+/*\r
+ * Copyright (c) 2002, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above\r
+ *    copyright notice, this list of conditions and the following\r
+ *    disclaimer in the documentation and/or other materials provided\r
+ *    with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ *    products derived from this software without specific prior\r
+ *    written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+#ifndef __WEBSERVER_H__\r
+#define __WEBSERVER_H__\r
+\r
+#include "httpd.h"\r
+\r
+typedef struct httpd_state uip_tcp_appstate_t;\r
+/* UIP_APPCALL: the name of the application function. This function\r
+   must return void and take no arguments (i.e., C type "void\r
+   appfunc(void)"). */\r
+#ifndef UIP_APPCALL\r
+#define UIP_APPCALL     httpd_appcall\r
+#endif\r
+\r
+\r
+#endif /* __WEBSERVER_H__ */\r
diff --git a/Demo/CORTEX_LPC1766_GCC_RedSuite/import.log b/Demo/CORTEX_LPC1766_GCC_RedSuite/import.log
new file mode 100644 (file)
index 0000000..88d96d1
--- /dev/null
@@ -0,0 +1 @@
+No build errors\r