{CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL},
{CFI_MFR_FUJITSU, 0x226b, cfi_fixup_non_cfi, NULL},
{CFI_MFR_AMIC, 0xb31a, cfi_fixup_non_cfi, NULL},
+ {CFI_MFR_MX, 0x225b, cfi_fixup_non_cfi, NULL},
{0, 0, NULL, NULL}
};
{CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
{CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
+ {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
{CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
{0, 0, NULL, NULL}
};
#define CFI_MFR_ST 0x0020 /* STMicroelectronics */
#define CFI_MFR_AMIC 0x0037
#define CFI_MFR_SST 0x00BF
+#define CFI_MFR_MX 0x00C2
#define CFI_MFR_ANY 0xffff
#define CFI_ID_ANY 0xffff
0x00000000
}
},
+ {
+ .mfr = CFI_MFR_MX,
+ .id = 0x225b, /* MX29LV800B */
+ .pri_id = 0x02,
+ .dev_size = 0x14, /* 2^20 = 1MB */
+ .interface_desc = 0x2, /* x8 or x16 device with nBYTE */
+ .max_buf_write_size = 0x0,
+ .num_erase_regions = 4,
+ .erase_region_info =
+ {
+ 0x00400000, /* 1x 16KB */
+ 0x00200001, /* 2x 8KB */
+ 0x00800000, /* 1x 32KB */
+ 0x0100000e, /* 15x 64KB */
+ 0x00000000
+ }
+ },
{
.mfr = 0,
.id = 0,