--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file misc.h\r
+ * @author MCD Application Team\r
+ * @version V3.0.0\r
+ * @date 04/06/2009\r
+ * @brief This file contains all the functions prototypes for the \r
+ * miscellaneous firmware library functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __MISC_H\r
+#define __MISC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup MISC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MISC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief NVIC Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint8_t NVIC_IRQChannel;\r
+ uint8_t NVIC_IRQChannelPreemptionPriority;\r
+ uint8_t NVIC_IRQChannelSubPriority;\r
+ FunctionalState NVIC_IRQChannelCmd;\r
+} NVIC_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup Vector_Table_Base \r
+ * @{\r
+ */\r
+\r
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)\r
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)\r
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \\r
+ ((VECTTAB) == NVIC_VectTab_FLASH))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup System_Low_Power \r
+ * @{\r
+ */\r
+\r
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)\r
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)\r
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)\r
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\r
+ ((LP) == NVIC_LP_SLEEPDEEP) || \\r
+ ((LP) == NVIC_LP_SLEEPONEXIT))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Preemption_Priority_Group \r
+ * @{\r
+ */\r
+\r
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /* 0 bits for pre-emption priority\r
+ 4 bits for subpriority */\r
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /* 1 bits for pre-emption priority\r
+ 3 bits for subpriority */\r
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /* 2 bits for pre-emption priority\r
+ 2 bits for subpriority */\r
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /* 3 bits for pre-emption priority\r
+ 1 bits for subpriority */\r
+#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /* 4 bits for pre-emption priority\r
+ 0 bits for subpriority */\r
+\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \\r
+ ((GROUP) == NVIC_PriorityGroup_1) || \\r
+ ((GROUP) == NVIC_PriorityGroup_2) || \\r
+ ((GROUP) == NVIC_PriorityGroup_3) || \\r
+ ((GROUP) == NVIC_PriorityGroup_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SysTick_clock_source \r
+ * @{\r
+ */\r
+\r
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)\r
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\r
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);\r
+\r
+#endif /* __MISC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_crc.h\r
+ * @author MCD Application Team\r
+ * @version V3.0.0\r
+ * @date 04/06/2009\r
+ * @brief This file contains all the functions prototypes for the CRC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_CRC_H\r
+#define __STM32F10x_CRC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void CRC_ResetDR(void);\r
+uint32_t CRC_CalcCRC(uint32_t Data);\r
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);\r
+uint32_t CRC_GetCRC(void);\r
+void CRC_SetIDRegister(uint8_t IDValue);\r
+uint8_t CRC_GetIDRegister(void);\r
+\r
+#endif /* __STM32F10x_CRC_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dac.h\r
+ * @author MCD Application Team\r
+ * @version V3.0.0\r
+ * @date 04/06/2009\r
+ * @brief This file contains all the functions prototypes for the DAC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_DAC_H\r
+#define __STM32F10x_DAC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DAC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief DAC Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DAC_Trigger;\r
+ uint32_t DAC_WaveGeneration;\r
+ uint32_t DAC_LFSRUnmask_TriangleAmplitude;\r
+ uint32_t DAC_OutputBuffer; \r
+}DAC_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC_trigger_selection \r
+ * @{\r
+ */\r
+\r
+#define DAC_Trigger_None ((uint32_t)0x00000000)\r
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004)\r
+#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C)\r
+#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014)\r
+#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C)\r
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024)\r
+#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C)\r
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034)\r
+#define DAC_Trigger_Software ((uint32_t)0x0000003C)\r
+\r
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \\r
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T8_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T5_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \\r
+ ((TRIGGER) == DAC_Trigger_Software))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_wave_generation \r
+ * @{\r
+ */\r
+\r
+#define DAC_WaveGeneration_None ((uint32_t)0x00000000)\r
+#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)\r
+#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)\r
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \\r
+ ((WAVE) == DAC_WaveGeneration_Noise) || \\r
+ ((WAVE) == DAC_WaveGeneration_Triangle))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_noise_wave_generation_mask_triangle_wave_generation_max_amplitude \r
+ * @{\r
+ */\r
+\r
+#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000)\r
+#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100)\r
+#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200)\r
+#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300)\r
+#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400)\r
+#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500)\r
+#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600)\r
+#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700)\r
+#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800)\r
+#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900)\r
+#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00)\r
+#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00)\r
+#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000)\r
+#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100)\r
+#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200)\r
+#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300)\r
+#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400)\r
+#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500)\r
+#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600)\r
+#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700)\r
+#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800)\r
+#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900)\r
+#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00)\r
+#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00)\r
+\r
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_3) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_7) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_15) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_31) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_63) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_127) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_255) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_511) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_4095))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_output_buffer \r
+ * @{\r
+ */\r
+\r
+#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)\r
+#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)\r
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \\r
+ ((STATE) == DAC_OutputBuffer_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Channel_selection \r
+ * @{\r
+ */\r
+\r
+#define DAC_Channel_1 ((uint32_t)0x00000000)\r
+#define DAC_Channel_2 ((uint32_t)0x00000010)\r
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \\r
+ ((CHANNEL) == DAC_Channel_2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data_alignement \r
+ * @{\r
+ */\r
+\r
+#define DAC_Align_12b_R ((uint32_t)0x00000000)\r
+#define DAC_Align_12b_L ((uint32_t)0x00000004)\r
+#define DAC_Align_8b_R ((uint32_t)0x00000008)\r
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \\r
+ ((ALIGN) == DAC_Align_12b_L) || \\r
+ ((ALIGN) == DAC_Align_8b_R))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_wave_generation \r
+ * @{\r
+ */\r
+\r
+#define DAC_Wave_Noise ((uint32_t)0x00000040)\r
+#define DAC_Wave_Triangle ((uint32_t)0x00000080)\r
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \\r
+ ((WAVE) == DAC_Wave_Triangle))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data \r
+ * @{\r
+ */\r
+\r
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void DAC_DeInit(void);\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);\r
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);\r
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);\r
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);\r
+\r
+#endif /*__STM32F10x_DAC_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dbgmcu.h\r
+ * @author MCD Application Team\r
+ * @version V3.0.0\r
+ * @date 04/06/2009\r
+ * @brief This file contains all the functions prototypes for the DBGMCU \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_DBGMCU_H\r
+#define __STM32F10x_DBGMCU_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DBGMCU\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DBGMCU_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define DBGMCU_SLEEP ((uint32_t)0x00000001)\r
+#define DBGMCU_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_STANDBY ((uint32_t)0x00000004)\r
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)\r
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)\r
+#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)\r
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)\r
+#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)\r
+#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)\r
+#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)\r
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)\r
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)\r
+#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)\r
+#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)\r
+#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)\r
+#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)\r
+\r
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFE000F8) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DBGMCU_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+uint32_t DBGMCU_GetREVID(void);\r
+uint32_t DBGMCU_GetDEVID(void);\r
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+\r
+#endif /* __STM32F10x_DBGMCU_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_flash.h\r
+ * @author MCD Application Team\r
+ * @version V3.0.0\r
+ * @date 04/06/2009\r
+ * @brief This file contains all the functions prototypes for the FLASH \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_FLASH_H\r
+#define __STM32F10x_FLASH_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief FLASH Status \r
+ */\r
+\r
+typedef enum\r
+{ \r
+ FLASH_BUSY = 1,\r
+ FLASH_ERROR_PG,\r
+ FLASH_ERROR_WRP,\r
+ FLASH_COMPLETE,\r
+ FLASH_TIMEOUT\r
+}FLASH_Status;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup Flash_Latency \r
+ * @{\r
+ */\r
+\r
+#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */\r
+#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */\r
+#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */\r
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \\r
+ ((LATENCY) == FLASH_Latency_1) || \\r
+ ((LATENCY) == FLASH_Latency_2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Half_Cycle_Enable_Disable \r
+ * @{\r
+ */\r
+\r
+#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /* FLASH Half Cycle Enable */\r
+#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /* FLASH Half Cycle Disable */\r
+#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \\r
+ ((STATE) == FLASH_HalfCycleAccess_Disable)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Prefetch_Buffer_Enable_Disable \r
+ * @{\r
+ */\r
+\r
+#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /* FLASH Prefetch Buffer Enable */\r
+#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /* FLASH Prefetch Buffer Disable */\r
+#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \\r
+ ((STATE) == FLASH_PrefetchBuffer_Disable)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_Write_Protection \r
+ * @{\r
+ */\r
+\r
+/* Values to be used with STM32F10Xxx Medium-density devices: FLASH memory density\r
+ ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */\r
+#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */\r
+#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */\r
+#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */\r
+#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */\r
+#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */\r
+#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */\r
+#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */\r
+#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */\r
+#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */\r
+#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */\r
+#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */\r
+#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */\r
+#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */\r
+#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */\r
+#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */\r
+#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */\r
+#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /* Write protection of page 64 to 67 */\r
+#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /* Write protection of page 68 to 71 */\r
+#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /* Write protection of page 72 to 75 */\r
+#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /* Write protection of page 76 to 79 */\r
+#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /* Write protection of page 80 to 83 */\r
+#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /* Write protection of page 84 to 87 */\r
+#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /* Write protection of page 88 to 91 */\r
+#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /* Write protection of page 92 to 95 */\r
+#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /* Write protection of page 96 to 99 */\r
+#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /* Write protection of page 100 to 103 */\r
+#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /* Write protection of page 104 to 107 */\r
+#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /* Write protection of page 108 to 111 */\r
+#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /* Write protection of page 112 to 115 */\r
+#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /* Write protection of page 115 to 119 */\r
+#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /* Write protection of page 120 to 123 */\r
+#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /* Write protection of page 124 to 127 */\r
+\r
+/* Values to be used with STM32F10Xxx High-density devices: FLASH memory density\r
+ ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */\r
+#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */\r
+#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */\r
+#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */\r
+#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */\r
+#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */\r
+#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */\r
+#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */\r
+#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */\r
+#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */\r
+#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */\r
+#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */\r
+#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */\r
+#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */\r
+#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */\r
+#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */\r
+#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */\r
+#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */\r
+#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */\r
+#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */\r
+#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */\r
+#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */\r
+#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */\r
+#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */\r
+#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */\r
+#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */\r
+#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */\r
+#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */\r
+#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */\r
+#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */\r
+#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */\r
+#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */\r
+#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */\r
+#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */\r
+\r
+#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))\r
+\r
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF))\r
+\r
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_IWatchdog \r
+ * @{\r
+ */\r
+\r
+#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */\r
+#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */\r
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_nRST_STOP \r
+ * @{\r
+ */\r
+\r
+#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */\r
+#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */\r
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_nRST_STDBY \r
+ * @{\r
+ */\r
+\r
+#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */\r
+#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */\r
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Interrupts \r
+ * @{\r
+ */\r
+\r
+#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */\r
+#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */\r
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Flags \r
+ * @{\r
+ */\r
+\r
+#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */\r
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */\r
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */\r
+#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */\r
+#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */\r
+ \r
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))\r
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \\r
+ ((FLAG) == FLASH_FLAG_OPTERR))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void FLASH_SetLatency(uint32_t FLASH_Latency);\r
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);\r
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);\r
+void FLASH_Unlock(void);\r
+void FLASH_Lock(void);\r
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
+FLASH_Status FLASH_EraseAllPages(void);\r
+FLASH_Status FLASH_EraseOptionBytes(void);\r
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);\r
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);\r
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);\r
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);\r
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);\r
+uint32_t FLASH_GetUserOptionByte(void);\r
+uint32_t FLASH_GetWriteProtectionOptionByte(void);\r
+FlagStatus FLASH_GetReadOutProtectionStatus(void);\r
+FlagStatus FLASH_GetPrefetchBufferStatus(void);\r
+void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState);\r
+FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG);\r
+void FLASH_ClearFlag(uint16_t FLASH_FLAG);\r
+FLASH_Status FLASH_GetStatus(void);\r
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);\r
+\r
+#endif /* __STM32F10x_FLASH_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_fsmc.h\r
+ * @author MCD Application Team\r
+ * @version V3.0.0\r
+ * @date 04/06/2009\r
+ * @brief This file contains all the functions prototypes for the FSMC \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_FSMC_H\r
+#define __STM32F10x_FSMC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FSMC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief Timing parameters For NOR/SRAM Banks \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_AddressSetupTime;\r
+ uint32_t FSMC_AddressHoldTime;\r
+ uint32_t FSMC_DataSetupTime;\r
+ uint32_t FSMC_BusTurnAroundDuration;\r
+ uint32_t FSMC_CLKDivision;\r
+ uint32_t FSMC_DataLatency;\r
+ uint32_t FSMC_AccessMode;\r
+}FSMC_NORSRAMTimingInitTypeDef;\r
+\r
+/** \r
+ * @brief FSMC NOR/SRAM Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_Bank;\r
+ uint32_t FSMC_DataAddressMux;\r
+ uint32_t FSMC_MemoryType;\r
+ uint32_t FSMC_MemoryDataWidth;\r
+ uint32_t FSMC_BurstAccessMode;\r
+ uint32_t FSMC_WaitSignalPolarity;\r
+ uint32_t FSMC_WrapMode;\r
+ uint32_t FSMC_WaitSignalActive;\r
+ uint32_t FSMC_WriteOperation;\r
+ uint32_t FSMC_WaitSignal;\r
+ uint32_t FSMC_ExtendedMode;\r
+ uint32_t FSMC_WriteBurst; \r
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;/* Timing Parameters for write and read access if the ExtendedMode is not used*/\r
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;/* Timing Parameters for write access if the ExtendedMode is used*/\r
+}FSMC_NORSRAMInitTypeDef;\r
+\r
+/** \r
+ * @brief Timing parameters For FSMC NAND and PCCARD Banks\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_SetupTime;\r
+ uint32_t FSMC_WaitSetupTime;\r
+ uint32_t FSMC_HoldSetupTime;\r
+ uint32_t FSMC_HiZSetupTime;\r
+}FSMC_NAND_PCCARDTimingInitTypeDef;\r
+\r
+/** \r
+ * @brief FSMC NAND Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_Bank;\r
+ uint32_t FSMC_Waitfeature;\r
+ uint32_t FSMC_MemoryDataWidth;\r
+ uint32_t FSMC_ECC;\r
+ uint32_t FSMC_ECCPageSize;\r
+ uint32_t FSMC_TCLRSetupTime;\r
+ uint32_t FSMC_TARSetupTime; \r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */ \r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;/* FSMC Attribute Space Timing */\r
+}FSMC_NANDInitTypeDef;\r
+\r
+/** \r
+ * @brief FSMC PCCARD Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_Waitfeature;\r
+ uint32_t FSMC_TCLRSetupTime;\r
+ uint32_t FSMC_TARSetupTime; \r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /* FSMC IO Space Timing */\r
+}FSMC_PCCARDInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_Banks_definitions \r
+ * @{\r
+ */\r
+\r
+#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)\r
+#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)\r
+#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)\r
+#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)\r
+#define FSMC_Bank2_NAND ((uint32_t)0x00000010)\r
+#define FSMC_Bank3_NAND ((uint32_t)0x00000100)\r
+#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)\r
+\r
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM2) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM3) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM4))\r
+\r
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
+ ((BANK) == FSMC_Bank3_NAND))\r
+\r
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
+ ((BANK) == FSMC_Bank3_NAND) || \\r
+ ((BANK) == FSMC_Bank4_PCCARD))\r
+\r
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
+ ((BANK) == FSMC_Bank3_NAND) || \\r
+ ((BANK) == FSMC_Bank4_PCCARD))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup NOR_SRAM_Banks \r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing \r
+ * @{\r
+ */\r
+\r
+#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)\r
+#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)\r
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \\r
+ ((MUX) == FSMC_DataAddressMux_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Memory_Type \r
+ * @{\r
+ */\r
+\r
+#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)\r
+#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)\r
+#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)\r
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \\r
+ ((MEMORY) == FSMC_MemoryType_PSRAM)|| \\r
+ ((MEMORY) == FSMC_MemoryType_NOR))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Width \r
+ * @{\r
+ */\r
+\r
+#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)\r
+#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)\r
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \\r
+ ((WIDTH) == FSMC_MemoryDataWidth_16b))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Burst_Access_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) \r
+#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)\r
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \\r
+ ((STATE) == FSMC_BurstAccessMode_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Signal_Polarity \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)\r
+#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)\r
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \\r
+ ((POLARITY) == FSMC_WaitSignalPolarity_High)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wrap_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) \r
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \\r
+ ((MODE) == FSMC_WrapMode_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Timing \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)\r
+#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) \r
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \\r
+ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Write_Operation \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)\r
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \\r
+ ((OPERATION) == FSMC_WriteOperation_Enable))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Signal \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) \r
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \\r
+ ((SIGNAL) == FSMC_WaitSignal_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Extended_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)\r
+#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)\r
+\r
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \\r
+ ((MODE) == FSMC_ExtendedMode_Enable)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Write_Burst \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) \r
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \\r
+ ((BURST) == FSMC_WriteBurst_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Address_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Address_Hold_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Bus_Turn_around_Duration \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_CLK_Division \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Latency \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Access_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_AccessMode_A ((uint32_t)0x00000000)\r
+#define FSMC_AccessMode_B ((uint32_t)0x10000000) \r
+#define FSMC_AccessMode_C ((uint32_t)0x20000000)\r
+#define FSMC_AccessMode_D ((uint32_t)0x30000000)\r
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \\r
+ ((MODE) == FSMC_AccessMode_B) || \\r
+ ((MODE) == FSMC_AccessMode_C) || \\r
+ ((MODE) == FSMC_AccessMode_D)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup NAND_and_PCCARD_Banks \r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_feature \r
+ * @{\r
+ */\r
+\r
+#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)\r
+#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)\r
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \\r
+ ((FEATURE) == FSMC_Waitfeature_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Memory_Data_Width \r
+ * @{\r
+ */ \r
+#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)\r
+#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)\r
+#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \\r
+ ((WIDTH) == FSMC_MemoryDataWidth_16b))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_ECC \r
+ * @{\r
+ */\r
+\r
+#define FSMC_ECC_Disable ((uint32_t)0x00000000)\r
+#define FSMC_ECC_Enable ((uint32_t)0x00000040)\r
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \\r
+ ((STATE) == FSMC_ECC_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_ECC_Page_Size \r
+ * @{\r
+ */\r
+\r
+#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)\r
+#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)\r
+#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)\r
+#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)\r
+#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)\r
+#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)\r
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_512Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_8192Bytes))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_TCLR_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_TAR_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Hold_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_HiZ_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Interrupt_sources \r
+ * @{\r
+ */\r
+\r
+#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)\r
+#define FSMC_IT_Level ((uint32_t)0x00000010)\r
+#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)\r
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))\r
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \\r
+ ((IT) == FSMC_IT_Level) || \\r
+ ((IT) == FSMC_IT_FallingEdge)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Flags \r
+ * @{\r
+ */\r
+\r
+#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)\r
+#define FSMC_FLAG_Level ((uint32_t)0x00000002)\r
+#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)\r
+#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)\r
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \\r
+ ((FLAG) == FSMC_FLAG_Level) || \\r
+ ((FLAG) == FSMC_FLAG_FallingEdge) || \\r
+ ((FLAG) == FSMC_FLAG_FEMPT))\r
+\r
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);\r
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);\r
+void FSMC_PCCARDDeInit(void);\r
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
+void FSMC_PCCARDCmd(FunctionalState NewState);\r
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);\r
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);\r
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r
+\r
+#endif /*__STM32F10x_FSMC_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_sdio.h\r
+ * @author MCD Application Team\r
+ * @version V3.0.0\r
+ * @date 04/06/2009\r
+ * @brief This file contains all the functions prototypes for the SDIO \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_SDIO_H\r
+#define __STM32F10x_SDIO_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SDIO\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDIO_Exported_Types\r
+ * @{\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint8_t SDIO_ClockDiv;\r
+ uint32_t SDIO_ClockEdge;\r
+ uint32_t SDIO_ClockBypass;\r
+ uint32_t SDIO_ClockPowerSave;\r
+ uint32_t SDIO_BusWide;\r
+ uint32_t SDIO_HardwareFlowControl;\r
+} SDIO_InitTypeDef;\r
+\r
+typedef struct\r
+{\r
+ uint32_t SDIO_Argument;\r
+ uint32_t SDIO_CmdIndex;\r
+ uint32_t SDIO_Response;\r
+ uint32_t SDIO_Wait;\r
+ uint32_t SDIO_CPSM;\r
+} SDIO_CmdInitTypeDef;\r
+\r
+typedef struct\r
+{\r
+ uint32_t SDIO_DataTimeOut;\r
+ uint32_t SDIO_DataLength;\r
+ uint32_t SDIO_DataBlockSize;\r
+ uint32_t SDIO_TransferDir;\r
+ uint32_t SDIO_TransferMode;\r
+ uint32_t SDIO_DPSM;\r
+} SDIO_DataInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDIO_Clock_Edge \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)\r
+#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)\r
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \\r
+ ((EDGE) == SDIO_ClockEdge_Falling))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Clock_Bypass \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)\r
+#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) \r
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \\r
+ ((BYPASS) == SDIO_ClockBypass_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Clock_Power_Save_ \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)\r
+#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) \r
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \\r
+ ((SAVE) == SDIO_ClockPowerSave_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Bus_Wide \r
+ * @{\r
+ */\r
+\r
+#define SDIO_BusWide_1b ((uint32_t)0x00000000)\r
+#define SDIO_BusWide_4b ((uint32_t)0x00000800)\r
+#define SDIO_BusWide_8b ((uint32_t)0x00001000)\r
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \\r
+ ((WIDE) == SDIO_BusWide_8b))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Hardware_Flow_Control_ \r
+ * @{\r
+ */\r
+\r
+#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)\r
+#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)\r
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \\r
+ ((CONTROL) == SDIO_HardwareFlowControl_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Power_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_PowerState_OFF ((uint32_t)0x00000000)\r
+#define SDIO_PowerState_ON ((uint32_t)0x00000003)\r
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup SDIO_Interrupt_soucres \r
+ * @{\r
+ */\r
+\r
+#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)\r
+#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)\r
+#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)\r
+#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)\r
+#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)\r
+#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)\r
+#define SDIO_IT_CMDREND ((uint32_t)0x00000040)\r
+#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)\r
+#define SDIO_IT_DATAEND ((uint32_t)0x00000100)\r
+#define SDIO_IT_STBITERR ((uint32_t)0x00000200)\r
+#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)\r
+#define SDIO_IT_CMDACT ((uint32_t)0x00000800)\r
+#define SDIO_IT_TXACT ((uint32_t)0x00001000)\r
+#define SDIO_IT_RXACT ((uint32_t)0x00002000)\r
+#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)\r
+#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)\r
+#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)\r
+#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)\r
+#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)\r
+#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)\r
+#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)\r
+#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)\r
+#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)\r
+#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)\r
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Command_Index_ \r
+ * @{\r
+ */\r
+\r
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Response_Type \r
+ * @{\r
+ */\r
+\r
+#define SDIO_Response_No ((uint32_t)0x00000000)\r
+#define SDIO_Response_Short ((uint32_t)0x00000040)\r
+#define SDIO_Response_Long ((uint32_t)0x000000C0)\r
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \\r
+ ((RESPONSE) == SDIO_Response_Short) || \\r
+ ((RESPONSE) == SDIO_Response_Long))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Wait_Interrupt_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_Wait_No ((uint32_t)0x00000000) /* SDIO No Wait, TimeOut is enabled */\r
+#define SDIO_Wait_IT ((uint32_t)0x00000100) /* SDIO Wait Interrupt Request */\r
+#define SDIO_Wait_Pend ((uint32_t)0x00000200) /* SDIO Wait End of transfer */\r
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \\r
+ ((WAIT) == SDIO_Wait_Pend))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_CPSM_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_CPSM_Disable ((uint32_t)0x00000000)\r
+#define SDIO_CPSM_Enable ((uint32_t)0x00000400)\r
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Response_Registers \r
+ * @{\r
+ */\r
+\r
+#define SDIO_RESP1 ((uint32_t)0x00000000)\r
+#define SDIO_RESP2 ((uint32_t)0x00000004)\r
+#define SDIO_RESP3 ((uint32_t)0x00000008)\r
+#define SDIO_RESP4 ((uint32_t)0x0000000C)\r
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \\r
+ ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Data_Length \r
+ * @{\r
+ */\r
+\r
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Data_Block_Size \r
+ * @{\r
+ */\r
+\r
+#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)\r
+#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)\r
+#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)\r
+#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)\r
+#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)\r
+#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)\r
+#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)\r
+#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)\r
+#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)\r
+#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)\r
+#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)\r
+#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)\r
+#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)\r
+#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)\r
+#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)\r
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_2b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_4b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_8b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_16b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_32b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_64b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_128b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_256b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_512b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_1024b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_2048b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_4096b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_8192b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_16384b)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Transfer_Direction \r
+ * @{\r
+ */\r
+\r
+#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)\r
+#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)\r
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \\r
+ ((DIR) == SDIO_TransferDir_ToSDIO))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Transfer_Type \r
+ * @{\r
+ */\r
+\r
+#define SDIO_TransferMode_Block ((uint32_t)0x00000000)\r
+#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)\r
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \\r
+ ((MODE) == SDIO_TransferMode_Block))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_DPSM_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_DPSM_Disable ((uint32_t)0x00000000)\r
+#define SDIO_DPSM_Enable ((uint32_t)0x00000001)\r
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Flags \r
+ * @{\r
+ */\r
+\r
+#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)\r
+#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)\r
+#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)\r
+#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)\r
+#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)\r
+#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)\r
+#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)\r
+#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)\r
+#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)\r
+#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)\r
+#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)\r
+#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)\r
+#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)\r
+#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)\r
+#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)\r
+#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)\r
+#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)\r
+#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)\r
+#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)\r
+#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)\r
+#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)\r
+#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)\r
+#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)\r
+#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)\r
+#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \\r
+ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \\r
+ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \\r
+ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \\r
+ ((FLAG) == SDIO_FLAG_TXUNDERR) || \\r
+ ((FLAG) == SDIO_FLAG_RXOVERR) || \\r
+ ((FLAG) == SDIO_FLAG_CMDREND) || \\r
+ ((FLAG) == SDIO_FLAG_CMDSENT) || \\r
+ ((FLAG) == SDIO_FLAG_DATAEND) || \\r
+ ((FLAG) == SDIO_FLAG_STBITERR) || \\r
+ ((FLAG) == SDIO_FLAG_DBCKEND) || \\r
+ ((FLAG) == SDIO_FLAG_CMDACT) || \\r
+ ((FLAG) == SDIO_FLAG_TXACT) || \\r
+ ((FLAG) == SDIO_FLAG_RXACT) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOF) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOF) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOE) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOE) || \\r
+ ((FLAG) == SDIO_FLAG_TXDAVL) || \\r
+ ((FLAG) == SDIO_FLAG_RXDAVL) || \\r
+ ((FLAG) == SDIO_FLAG_SDIOIT) || \\r
+ ((FLAG) == SDIO_FLAG_CEATAEND))\r
+\r
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))\r
+\r
+#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \\r
+ ((IT) == SDIO_IT_DCRCFAIL) || \\r
+ ((IT) == SDIO_IT_CTIMEOUT) || \\r
+ ((IT) == SDIO_IT_DTIMEOUT) || \\r
+ ((IT) == SDIO_IT_TXUNDERR) || \\r
+ ((IT) == SDIO_IT_RXOVERR) || \\r
+ ((IT) == SDIO_IT_CMDREND) || \\r
+ ((IT) == SDIO_IT_CMDSENT) || \\r
+ ((IT) == SDIO_IT_DATAEND) || \\r
+ ((IT) == SDIO_IT_STBITERR) || \\r
+ ((IT) == SDIO_IT_DBCKEND) || \\r
+ ((IT) == SDIO_IT_CMDACT) || \\r
+ ((IT) == SDIO_IT_TXACT) || \\r
+ ((IT) == SDIO_IT_RXACT) || \\r
+ ((IT) == SDIO_IT_TXFIFOHE) || \\r
+ ((IT) == SDIO_IT_RXFIFOHF) || \\r
+ ((IT) == SDIO_IT_TXFIFOF) || \\r
+ ((IT) == SDIO_IT_RXFIFOF) || \\r
+ ((IT) == SDIO_IT_TXFIFOE) || \\r
+ ((IT) == SDIO_IT_RXFIFOE) || \\r
+ ((IT) == SDIO_IT_TXDAVL) || \\r
+ ((IT) == SDIO_IT_RXDAVL) || \\r
+ ((IT) == SDIO_IT_SDIOIT) || \\r
+ ((IT) == SDIO_IT_CEATAEND))\r
+\r
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Read_Wait_Mode \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)\r
+#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)\r
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \\r
+ ((MODE) == SDIO_ReadWaitMode_DATA2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void SDIO_DeInit(void);\r
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);\r
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);\r
+void SDIO_ClockCmd(FunctionalState NewState);\r
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);\r
+uint32_t SDIO_GetPowerState(void);\r
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);\r
+void SDIO_DMACmd(FunctionalState NewState);\r
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);\r
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);\r
+uint8_t SDIO_GetCommandResponse(void);\r
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);\r
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
+uint32_t SDIO_GetDataCounter(void);\r
+uint32_t SDIO_ReadData(void);\r
+void SDIO_WriteData(uint32_t Data);\r
+uint32_t SDIO_GetFIFOCount(void);\r
+void SDIO_StartSDIOReadWait(FunctionalState NewState);\r
+void SDIO_StopSDIOReadWait(FunctionalState NewState);\r
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);\r
+void SDIO_SetSDIOOperation(FunctionalState NewState);\r
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);\r
+void SDIO_CommandCompletionCmd(FunctionalState NewState);\r
+void SDIO_CEATAITCmd(FunctionalState NewState);\r
+void SDIO_SendCEATACmd(FunctionalState NewState);\r
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);\r
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);\r
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);\r
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);\r
+\r
+#endif /* __STM32F10x_SDIO_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32fxxx_eth.h\r
+* Author : MCD Application Team\r
+* Version : V0.0.1\r
+* Date : 12/17/2008\r
+* Desciption : This file contains all the functions prototypes for the\r
+* ETHERNET firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32FXXX_ETH_H\r
+#define __STM32FXXX_ETH_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32fxxx_eth_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* ETHERNET MAC Init structure definition */\r
+typedef struct {\r
+ /* MAC ----------------------------------*/\r
+ u32 ETH_AutoNegotiation; /* Selects or not the AutoNegotiation with the external PHY */\r
+ u32 ETH_Watchdog; /* Enable/disable Watchdog timer */\r
+ u32 ETH_Jabber; /* Enable/disable Jabber timer */\r
+ u32 ETH_JumboFrame; /* Enable/disable Jumbo frame */\r
+ u32 ETH_InterFrameGap; /* Selects minimum IFG between frames during transmission */\r
+ u32 ETH_CarrierSense; /* Enable/disable Carrier Sense */\r
+ u32 ETH_Speed; /* Indicates the Ethernet speed: 10/100 Mbps */\r
+ u32 ETH_ReceiveOwn; /* Enable/disable the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */\r
+ u32 ETH_LoopbackMode; /* Enable/disable internal MAC MII Loopback mode */\r
+ u32 ETH_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */\r
+ u32 ETH_ChecksumOffload; /* Enable/disable the calculation of complement sum of all received Ethernet frame payloads */\r
+ u32 ETH_RetryTransmission; /* Enable/disable the MAC attempt retries transmission, based on the settings of BL, when a colision occurs (Half-Duplex mode) */\r
+ u32 ETH_AutomaticPadCRCStrip; /* Enable/disable Automatic MAC Pad/CRC Stripping */\r
+ u32 ETH_BackOffLimit; /* Selects the BackOff limit value */\r
+ u32 ETH_DeferralCheck; /* Enable/disable deferral check function (Half-Duplex mode) */\r
+ u32 ETH_ReceiveAll; /* Enable/disable all frames reception by the MAC (No fitering)*/\r
+ u32 ETH_SourceAddrFilter; /* Selects EnableNormal/EnableInverse/disable Source Address Filter comparison */\r
+ u32 ETH_PassControlFrames; /* Selects None/All/FilterPass of all control frames (including unicast and multicast PAUSE frames) */\r
+ u32 ETH_BroadcastFramesReception; /* Enable/disable reception of Broadcast Frames */\r
+ u32 ETH_DestinationAddrFilter; /* Selects EnableNormal/EnableInverse destination filter for both unicast and multicast frames */\r
+ u32 ETH_PromiscuousMode; /* Enable/disable Promiscuous Mode */\r
+ u32 ETH_MulticastFramesFilter; /* Selects the Multicast Frames filter: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter */\r
+ u32 ETH_UnicastFramesFilter; /* Selects the Unicast Frames filter: HashTableFilter/PerfectFilter/PerfectHashTableFilter */\r
+ u32 ETH_HashTableHigh; /* This field contains the higher 32 bits of Hash table. */\r
+ u32 ETH_HashTableLow; /* This field contains the lower 32 bits of Hash table. */\r
+ u32 ETH_PauseTime; /* This field holds the value to be used in the Pause Time field in the transmit control frame */\r
+ u32 ETH_ZeroQuantaPause; /* Enable/disable the automatic generation of Zero-Quanta Pause Control frames */\r
+ u32 ETH_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */\r
+ u32 ETH_UnicastPauseFrameDetect; /* Enable/disable MAC to detect the Pause frames (with MAC Address0 unicast address and unique multicast address) */\r
+ u32 ETH_ReceiveFlowControl; /* Enable/disable the MAC to decode the received Pause frame and disable its transmitter for a specified (Pause Time) time */\r
+ u32 ETH_TransmitFlowControl; /* Enable/disable the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) */\r
+ u32 ETH_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering */\r
+ u32 ETH_VLANTagIdentifier; /* VLAN tag identifier for receive frames */\r
+\r
+ /* DMA --------------------------*/\r
+ u32 ETH_DropTCPIPChecksumErrorFrame; /* Enable/disable Dropping of TCP/IP Checksum Error Frames */\r
+ u32 ETH_ReceiveStoreForward; /* Enable/disable Receive store and forward */\r
+ u32 ETH_FlushReceivedFrame; /* Enable/disable flushing of received frames */\r
+ u32 ETH_TransmitStoreForward; /* Enable/disable Transmit store and forward */\r
+ u32 ETH_TransmitThresholdControl; /* Selects the Transmit Threshold Control */\r
+ u32 ETH_ForwardErrorFrames; /* Enable/disable forward to DMA of all frames except runt error frames */\r
+ u32 ETH_ForwardUndersizedGoodFrames; /* Enable/disable Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) */\r
+ u32 ETH_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO */\r
+ u32 ETH_SecondFrameOperate; /* Enable/disable the DMA process of a second frame of Transmit data even before status for first frame is obtained */\r
+ u32 ETH_AddressAlignedBeats; /* Enable/disable Address Aligned Beats */\r
+ u32 ETH_FixedBurst; /* Enable/disable the AHB Master interface fixed burst transfers */\r
+ u32 ETH_RxDMABurstLength; /* Indicate the maximum number of beats to be transferred in one Rx DMA transaction */\r
+ u32 ETH_TxDMABurstLength; /* Indicate the maximum number of beats to be transferred in one Tx DMA transaction */\r
+ u32 ETH_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained descriptors (Ring mode) */\r
+ u32 ETH_DMAArbitration; /* Selects DMA Tx/Rx arbitration */\r
+}ETH_InitTypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* DMA descriptors types */\r
+/*----------------------------------------------------------------------------*/\r
+/* ETHERNET DMA Desciptors data structure definition */\r
+typedef struct {\r
+ volatile u32 Status; /* Status */\r
+ volatile u32 ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */\r
+ volatile u32 Buffer1Addr; /* Buffer1 address pointer */\r
+ volatile u32 Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */\r
+} ETH_DMADESCTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* ETHERNET Frames defines */\r
+/*----------------------------------------------------------------------------*/\r
+/* ENET Buffers setting */\r
+#define ETH_MAX_PACKET_SIZE 1520 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */\r
+#define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */\r
+#define ETH_CRC 4 /* Ethernet CRC */\r
+#define ETH_EXTRA 2 /* Extra bytes in some cases */\r
+#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */\r
+#define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */\r
+#define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */\r
+#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */\r
+\r
+/*--------------------------------------------------------*/\r
+/* Ethernet DMA descriptors registers bits definition */\r
+/*--------------------------------------------------------*/\r
+/* DMA Tx Desciptor ---------------------------------------------------------*/\r
+/*-----------------------------------------------------------------------------------------------\r
+ TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES2 | Buffer1 Address [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |\r
+ ----------------------------------------------------------------------------------------------*/\r
+\r
+/* Bit definition of TDES0 register: DMA Tx descriptor status register */\r
+#define ETH_DMATxDesc_OWN (0x80000000UL) /* OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMATxDesc_IC ((u32)0x40000000) /* Interrupt on Completion */\r
+#define ETH_DMATxDesc_LS ((u32)0x20000000) /* Last Segment */\r
+#define ETH_DMATxDesc_FS ((u32)0x10000000) /* First Segment */\r
+#define ETH_DMATxDesc_DC ((u32)0x08000000) /* Disable CRC */\r
+#define ETH_DMATxDesc_DP ((u32)0x04000000) /* Disable Padding */\r
+#define ETH_DMATxDesc_TTSE ((u32)0x02000000) /* Transmit Time Stamp Enable */\r
+#define ETH_DMATxDesc_CIC ((u32)0x00C00000) /* Checksum Insertion Control: 4 cases */\r
+ #define ETH_DMATxDesc_CIC_ByPass ((u32)0x00000000) /* Do Nothing: Checksum Engine is bypassed */\r
+ #define ETH_DMATxDesc_CIC_IPV4Header ((u32)0x00400000) /* IPV4 header Checksum Insertion */\r
+ #define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((u32)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */\r
+ #define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((u32)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */\r
+#define ETH_DMATxDesc_TER ((u32)0x00200000) /* Transmit End of Ring */\r
+#define ETH_DMATxDesc_TCH ((u32)0x00100000) /* Second Address Chained */\r
+#define ETH_DMATxDesc_TTSS ((u32)0x00020000) /* Tx Time Stamp Status */\r
+#define ETH_DMATxDesc_IHE ((u32)0x00010000) /* IP Header Error */\r
+#define ETH_DMATxDesc_ES ((u32)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */\r
+#define ETH_DMATxDesc_JT ((u32)0x00004000) /* Jabber Timeout */\r
+#define ETH_DMATxDesc_FF ((u32)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */\r
+#define ETH_DMATxDesc_PCE ((u32)0x00001000) /* Payload Checksum Error */\r
+#define ETH_DMATxDesc_LCA ((u32)0x00000800) /* Loss of Carrier: carrier lost during tramsmission */\r
+#define ETH_DMATxDesc_NC ((u32)0x00000400) /* No Carrier: no carrier signal from the tranceiver */\r
+#define ETH_DMATxDesc_LCO ((u32)0x00000200) /* Late Collision: transmission aborted due to collision */\r
+#define ETH_DMATxDesc_EC ((u32)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */\r
+#define ETH_DMATxDesc_VF ((u32)0x00000080) /* VLAN Frame */\r
+#define ETH_DMATxDesc_CC ((u32)0x00000078) /* Collision Count */\r
+#define ETH_DMATxDesc_ED ((u32)0x00000004) /* Excessive Deferral */\r
+#define ETH_DMATxDesc_UF ((u32)0x00000002) /* Underflow Error: late data arrival from the memory */\r
+#define ETH_DMATxDesc_DB ((u32)0x00000001) /* Deferred Bit */\r
+\r
+/* Bit definition of TDES1 register */\r
+#define ETH_DMATxDesc_TBS2 ((u32)0x1FFF0000) /* Transmit Buffer2 Size */\r
+#define ETH_DMATxDesc_TBS1 ((u32)0x00001FFF) /* Transmit Buffer1 Size */\r
+\r
+/* Bit definition of TDES2 register */\r
+#define ETH_DMATxDesc_B1AP ((u32)0xFFFFFFFF) /* Buffer1 Address Pointer */\r
+\r
+/* Bit definition of TDES3 register */\r
+#define ETH_DMATxDesc_B2AP ((u32)0xFFFFFFFF) /* Buffer2 Address Pointer */\r
+\r
+/* DMA Rx descriptor ---------------------------------------------------------*/\r
+/*---------------------------------------------------------------------------------------------------------------------\r
+ RDES0 | OWN(31) | Status [30:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES2 | Buffer1 Address [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |\r
+ --------------------------------------------------------------------------------------------------------------------*/\r
+\r
+/* Bit definition of RDES0 register: DMA Rx descriptor status register */\r
+#define ETH_DMARxDesc_OWN ((u32)0x80000000) /* OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMARxDesc_AFM ((u32)0x40000000) /* DA Filter Fail for the rx frame */\r
+#define ETH_DMARxDesc_FL ((u32)0x3FFF0000) /* Receive descriptor frame length */\r
+#define ETH_DMARxDesc_ES ((u32)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */\r
+#define ETH_DMARxDesc_DE ((u32)0x00004000) /* Desciptor error: no more descriptors for receive frame */\r
+#define ETH_DMARxDesc_SAF ((u32)0x00002000) /* SA Filter Fail for the received frame */\r
+#define ETH_DMARxDesc_LE ((u32)0x00001000) /* Frame size not matching with length field */\r
+#define ETH_DMARxDesc_OE ((u32)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */\r
+#define ETH_DMARxDesc_VLAN ((u32)0x00000400) /* VLAN Tag: received frame is a VLAN frame */\r
+#define ETH_DMARxDesc_FS ((u32)0x00000200) /* First descriptor of the frame */\r
+#define ETH_DMARxDesc_LS ((u32)0x00000100) /* Last descriptor of the frame */\r
+#define ETH_DMARxDesc_IPV4HCE ((u32)0x00000080) /* IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error */\r
+#define ETH_DMARxDesc_RxLongFrame ((u32)0x00000080) /* (Giant Frame)Rx - frame is longer than 1518/1522 */\r
+#define ETH_DMARxDesc_LC ((u32)0x00000040) /* Late collision occurred during reception */\r
+#define ETH_DMARxDesc_FT ((u32)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */\r
+#define ETH_DMARxDesc_RWT ((u32)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */\r
+#define ETH_DMARxDesc_RE ((u32)0x00000008) /* Receive error: error reported by MII interface */\r
+#define ETH_DMARxDesc_DBE ((u32)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */\r
+#define ETH_DMARxDesc_CE ((u32)0x00000002) /* CRC error */\r
+#define ETH_DMARxDesc_MAMPCE ((u32)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */\r
+\r
+/* Bit definition of RDES1 register */\r
+#define ETH_DMARxDesc_DIC ((u32)0x80000000) /* Disable Interrupt on Completion */\r
+#define ETH_DMARxDesc_RBS2 ((u32)0x1FFF0000) /* Receive Buffer2 Size */\r
+#define ETH_DMARxDesc_RER ((u32)0x00008000) /* Receive End of Ring */\r
+#define ETH_DMARxDesc_RCH ((u32)0x00004000) /* Second Address Chained */\r
+#define ETH_DMARxDesc_RBS1 ((u32)0x00001FFF) /* Receive Buffer1 Size */\r
+\r
+/* Bit definition of RDES2 register */\r
+#define ETH_DMARxDesc_B1AP ((u32)0xFFFFFFFF) /* Buffer1 Address Pointer */\r
+\r
+/* Bit definition of RDES3 register */\r
+#define ETH_DMARxDesc_B2AP ((u32)0xFFFFFFFF) /* Buffer2 Address Pointer */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Desciption of common PHY registers */\r
+/*----------------------------------------------------------------------------*/\r
+/* PHY Read/write Timeouts */\r
+#define PHY_READ_TO ((u32)0x0004FFFF)\r
+#define PHY_WRITE_TO ((u32)0x0004FFFF)\r
+\r
+/* PHY Reset Delay */\r
+#define PHY_ResetDelay ((u32)0x000FFFFF)\r
+\r
+/* PHY Config Delay */\r
+#define PHY_ConfigDelay ((u32)0x00FFFFFF)\r
+\r
+/* PHY Register address */\r
+#define PHY_BCR 0 /* Tranceiver Basic Control Register */\r
+#define PHY_BSR 1 /* Tranceiver Basic Status Register */\r
+\r
+/* PHY basic Control register */\r
+#define PHY_Reset ((u16)0x8000) /* PHY Reset */\r
+#define PHY_Loopback ((u16)0x4000) /* Select loop-back mode */\r
+#define PHY_FULLDUPLEX_100M ((u16)0x2100) /* Set the full-duplex mode at 100 Mb/s */\r
+#define PHY_HALFDUPLEX_100M ((u16)0x2000) /* Set the half-duplex mode at 100 Mb/s */\r
+#define PHY_FULLDUPLEX_10M ((u16)0x0100) /* Set the full-duplex mode at 10 Mb/s */\r
+#define PHY_HALFDUPLEX_10M ((u16)0x0000) /* Set the half-duplex mode at 10 Mb/s */\r
+#define PHY_AutoNegotiation ((u16)0x1000) /* Enable auto-negotiation function */\r
+#define PHY_Restart_AutoNegotiation ((u16)0x0200) /* Restart auto-negotiation function */\r
+#define PHY_Powerdown ((u16)0x0800) /* Select the power down mode */\r
+#define PHY_Isolate ((u16)0x0400) /* Isolate PHY from MII */\r
+\r
+/* PHY basic status register */\r
+#define PHY_AutoNego_Complete ((u16)0x0020) /* Auto-Negotioation process completed */\r
+#define PHY_Linked_Status ((u16)0x0004) /* Valid link established */\r
+#define PHY_Jabber_detection ((u16)0x0002) /* Jabber condition detected */\r
+\r
+/* The PHY status register value change from a PHY to another so the user have to update\r
+ this value depending on the used external PHY */\r
+/* For LAN8700 */\r
+//#define PHY_SR 31 /* Tranceiver Status Register */\r
+/* For DP83848 */\r
+#define PHY_SR 16 /* Tranceiver Status Register */\r
+\r
+/* PHY status register */\r
+/* The Speed and Duplex mask values change from a PHY to another so the user have to update\r
+ this value depending on the used external PHY */\r
+/* For LAN8700 */\r
+//#define PHY_Speed_Status ((u16)0x0004) /* Configured information of Speed: 10Mbps */\r
+//#define PHY_Duplex_Status ((u16)0x0010) /* Configured information of Duplex: Full-duplex */\r
+/* For DP83848 */\r
+#define PHY_Speed_Status ((u16)0x0002) /* Configured information of Speed: 10Mbps */\r
+#define PHY_Duplex_Status ((u16)0x0004) /* Configured information of Duplex: Full-duplex */\r
+\r
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)\r
+#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \\r
+ ((REG) == PHY_BSR) || \\r
+ ((REG) == PHY_SR))\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* MAC defines */\r
+/*----------------------------------------------------------------------------*/\r
+/* ETHERNET AutoNegotiation --------------------------------------------------*/\r
+#define ETH_AutoNegotiation_Enable ((u32)0x00000001)\r
+#define ETH_AutoNegotiation_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \\r
+ ((CMD) == ETH_AutoNegotiation_Disable))\r
+\r
+/* ETHERNET watchdog ---------------------------------------------------------*/\r
+#define ETH_Watchdog_Enable ((u32)0x00000000)\r
+#define ETH_Watchdog_Disable ((u32)0x00800000)\r
+\r
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \\r
+ ((CMD) == ETH_Watchdog_Disable))\r
+\r
+/* ETHERNET Jabber -----------------------------------------------------------*/\r
+#define ETH_Jabber_Enable ((u32)0x00000000)\r
+#define ETH_Jabber_Disable ((u32)0x00400000)\r
+\r
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \\r
+ ((CMD) == ETH_Jabber_Disable))\r
+\r
+/* ETHERNET Jumbo Frame ------------------------------------------------------*/\r
+#define ETH_JumboFrame_Enable ((u32)0x00100000)\r
+#define ETH_JumboFrame_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_JUMBO_FRAME(CMD) (((CMD) == ETH_JumboFrame_Enable) || \\r
+ ((CMD) == ETH_JumboFrame_Disable))\r
+\r
+/* ETHERNET Inter Frame Gap --------------------------------------------------*/\r
+#define ETH_InterFrameGap_96Bit ((u32)0x00000000) /* minimum IFG between frames during transmission is 96Bit */\r
+#define ETH_InterFrameGap_88Bit ((u32)0x00020000) /* minimum IFG between frames during transmission is 88Bit */\r
+#define ETH_InterFrameGap_80Bit ((u32)0x00040000) /* minimum IFG between frames during transmission is 80Bit */\r
+#define ETH_InterFrameGap_72Bit ((u32)0x00060000) /* minimum IFG between frames during transmission is 72Bit */\r
+#define ETH_InterFrameGap_64Bit ((u32)0x00080000) /* minimum IFG between frames during transmission is 64Bit */\r
+#define ETH_InterFrameGap_56Bit ((u32)0x000A0000) /* minimum IFG between frames during transmission is 56Bit */\r
+#define ETH_InterFrameGap_48Bit ((u32)0x000C0000) /* minimum IFG between frames during transmission is 48Bit */\r
+#define ETH_InterFrameGap_40Bit ((u32)0x000E0000) /* minimum IFG between frames during transmission is 40Bit */\r
+\r
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_88Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_80Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_72Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_64Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_56Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_48Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_40Bit))\r
+\r
+/* ETHERNET Carrier Sense ----------------------------------------------------*/\r
+#define ETH_CarrierSense_Enable ((u32)0x00000000)\r
+#define ETH_CarrierSense_Disable ((u32)0x00010000)\r
+\r
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \\r
+ ((CMD) == ETH_CarrierSense_Disable))\r
+\r
+/* ETHERNET Speed ------------------------------------------------------------*/\r
+#define ETH_Speed_10M ((u32)0x00000000)\r
+#define ETH_Speed_100M ((u32)0x00004000)\r
+\r
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \\r
+ ((SPEED) == ETH_Speed_100M))\r
+\r
+/* ETHERNET Receive Own ------------------------------------------------------*/\r
+#define ETH_ReceiveOwn_Enable ((u32)0x00000000)\r
+#define ETH_ReceiveOwn_Disable ((u32)0x00002000)\r
+\r
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \\r
+ ((CMD) == ETH_ReceiveOwn_Disable))\r
+\r
+/* ETHERNET Loop back Mode ---------------------------------------------------*/\r
+#define ETH_LoopbackMode_Enable ((u32)0x00001000)\r
+#define ETH_LoopbackMode_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \\r
+ ((CMD) == ETH_LoopbackMode_Disable))\r
+\r
+/* ETHERNET Duplex mode ------------------------------------------------------*/\r
+#define ETH_Mode_FullDuplex ((u32)0x00000800)\r
+#define ETH_Mode_HalfDuplex ((u32)0x00000000)\r
+\r
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \\r
+ ((MODE) == ETH_Mode_HalfDuplex))\r
+\r
+/* ETHERNET Checksum Offload -------------------------------------------------*/\r
+#define ETH_ChecksumOffload_Enable ((u32)0x00000400)\r
+#define ETH_ChecksumOffload_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \\r
+ ((CMD) == ETH_ChecksumOffload_Disable))\r
+\r
+/* ETHERNET Retry Transmission -----------------------------------------------*/\r
+#define ETH_RetryTransmission_Enable ((u32)0x00000000)\r
+#define ETH_RetryTransmission_Disable ((u32)0x00000200)\r
+\r
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \\r
+ ((CMD) == ETH_RetryTransmission_Disable))\r
+\r
+/* ETHERNET Automatic Pad/CRC Strip ------------------------------------------*/\r
+#define ETH_AutomaticPadCRCStrip_Enable ((u32)0x00000080)\r
+#define ETH_AutomaticPadCRCStrip_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \\r
+ ((CMD) == ETH_AutomaticPadCRCStrip_Disable))\r
+\r
+/* ETHERNET Back-Off limit ---------------------------------------------------*/\r
+#define ETH_BackOffLimit_10 ((u32)0x00000000)\r
+#define ETH_BackOffLimit_8 ((u32)0x00000020)\r
+#define ETH_BackOffLimit_4 ((u32)0x00000040)\r
+#define ETH_BackOffLimit_1 ((u32)0x00000060)\r
+\r
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \\r
+ ((LIMIT) == ETH_BackOffLimit_8) || \\r
+ ((LIMIT) == ETH_BackOffLimit_4) || \\r
+ ((LIMIT) == ETH_BackOffLimit_1))\r
+\r
+/* ETHERNET Deferral Check ---------------------------------------------------*/\r
+#define ETH_DeferralCheck_Enable ((u32)0x00000010)\r
+#define ETH_DeferralCheck_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \\r
+ ((CMD) == ETH_DeferralCheck_Disable))\r
+\r
+/* ETHERNET Receive All ------------------------------------------------------*/\r
+#define ETH_ReceiveAll_Enable ((u32)0x80000000)\r
+#define ETH_ReceiveAll_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \\r
+ ((CMD) == ETH_ReceiveAll_Disable))\r
+\r
+/* ETHERNET Source Addr Filter ------------------------------------------------*/\r
+#define ETH_SourceAddrFilter_Normal_Enable ((u32)0x00000200)\r
+#define ETH_SourceAddrFilter_Inverse_Enable ((u32)0x00000300)\r
+#define ETH_SourceAddrFilter_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \\r
+ ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \\r
+ ((CMD) == ETH_SourceAddrFilter_Disable))\r
+\r
+/* ETHERNET Pass Control Frames ----------------------------------------------*/\r
+#define ETH_PassControlFrames_BlockAll ((u32)0x00000040) /* MAC filters all control frames from reaching the application */\r
+#define ETH_PassControlFrames_ForwardAll ((u32)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */\r
+#define ETH_PassControlFrames_ForwardPassedAddrFilter ((u32)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */\r
+\r
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \\r
+ ((PASS) == ETH_PassControlFrames_ForwardAll) || \\r
+ ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter))\r
+\r
+/* ETHERNET Broadcast Frames Reception ---------------------------------------*/\r
+#define ETH_BroadcastFramesReception_Enable ((u32)0x00000000)\r
+#define ETH_BroadcastFramesReception_Disable ((u32)0x00000020)\r
+\r
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \\r
+ ((CMD) == ETH_BroadcastFramesReception_Disable))\r
+\r
+/* ETHERNET Destination Addr Filter ------------------------------------------*/\r
+#define ETH_DestinationAddrFilter_Normal ((u32)0x00000000)\r
+#define ETH_DestinationAddrFilter_Inverse ((u32)0x00000008)\r
+\r
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \\r
+ ((FILTER) == ETH_DestinationAddrFilter_Inverse))\r
+\r
+/* ETHERNET Promiscuous Mode -------------------------------------------------*/\r
+#define ETH_PromiscuousMode_Enable ((u32)0x00000001)\r
+#define ETH_PromiscuousMode_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \\r
+ ((CMD) == ETH_PromiscuousMode_Disable))\r
+\r
+/* ETHERNET multicast frames filter --------------------------------------------*/\r
+#define ETH_MulticastFramesFilter_PerfectHashTable ((u32)0x00000404)\r
+#define ETH_MulticastFramesFilter_HashTable ((u32)0x00000004)\r
+#define ETH_MulticastFramesFilter_Perfect ((u32)0x00000000)\r
+#define ETH_MulticastFramesFilter_None ((u32)0x00000010)\r
+\r
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \\r
+ ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \\r
+ ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \\r
+ ((FILTER) == ETH_MulticastFramesFilter_None))\r
+\r
+/* ETHERNET unicast frames filter --------------------------------------------*/\r
+#define ETH_UnicastFramesFilter_PerfectHashTable ((u32)0x00000402)\r
+#define ETH_UnicastFramesFilter_HashTable ((u32)0x00000002)\r
+#define ETH_UnicastFramesFilter_Perfect ((u32)0x00000000)\r
+\r
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \\r
+ ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \\r
+ ((FILTER) == ETH_UnicastFramesFilter_Perfect))\r
+\r
+/* ETHERNET Pause Time ------------------------------------------------*/\r
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)\r
+\r
+/* ETHERNET Zero Quanta Pause ------------------------------------------------*/\r
+#define ETH_ZeroQuantaPause_Enable ((u32)0x00000000)\r
+#define ETH_ZeroQuantaPause_Disable ((u32)0x00000080)\r
+\r
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \\r
+ ((CMD) == ETH_ZeroQuantaPause_Disable))\r
+\r
+/* ETHERNET Pause Low Threshold ----------------------------------------------*/\r
+#define ETH_PauseLowThreshold_Minus4 ((u32)0x00000000) /* Pause time minus 4 slot times */\r
+#define ETH_PauseLowThreshold_Minus28 ((u32)0x00000010) /* Pause time minus 28 slot times */\r
+#define ETH_PauseLowThreshold_Minus144 ((u32)0x00000020) /* Pause time minus 144 slot times */\r
+#define ETH_PauseLowThreshold_Minus256 ((u32)0x00000030) /* Pause time minus 256 slot times */\r
+\r
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \\r
+ ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \\r
+ ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \\r
+ ((THRESHOLD) == ETH_PauseLowThreshold_Minus256))\r
+\r
+/* ETHERNET Unicast Pause Frame Detect ---------------------------------------*/\r
+#define ETH_UnicastPauseFrameDetect_Enable ((u32)0x00000008)\r
+#define ETH_UnicastPauseFrameDetect_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \\r
+ ((CMD) == ETH_UnicastPauseFrameDetect_Disable))\r
+\r
+/* ETHERNET Receive Flow Control ---------------------------------------------*/\r
+#define ETH_ReceiveFlowControl_Enable ((u32)0x00000004)\r
+#define ETH_ReceiveFlowControl_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \\r
+ ((CMD) == ETH_ReceiveFlowControl_Disable))\r
+\r
+/* ETHERNET Transmit Flow Control --------------------------------------------*/\r
+#define ETH_TransmitFlowControl_Enable ((u32)0x00000002)\r
+#define ETH_TransmitFlowControl_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \\r
+ ((CMD) == ETH_TransmitFlowControl_Disable))\r
+\r
+/* ETHERNET VLAN Tag Comparison ----------------------------------------------*/\r
+#define ETH_VLANTagComparison_12Bit ((u32)0x00010000)\r
+#define ETH_VLANTagComparison_16Bit ((u32)0x00000000)\r
+\r
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \\r
+ ((COMPARISON) == ETH_VLANTagComparison_16Bit))\r
+\r
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)\r
+\r
+/* ETHERNET MAC Flags ---------------------------------------------------*/\r
+#define ETH_MAC_FLAG_TST ((u32)0x00000200) /* Time stamp trigger flag (on MAC) */\r
+#define ETH_MAC_FLAG_MMCT ((u32)0x00000040) /* MMC transmit flag */\r
+#define ETH_MAC_FLAG_MMCR ((u32)0x00000020) /* MMC receive flag */\r
+#define ETH_MAC_FLAG_MMC ((u32)0x00000010) /* MMC flag (on MAC) */\r
+#define ETH_MAC_FLAG_PMT ((u32)0x00000008) /* PMT flag (on MAC) */\r
+\r
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \\r
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \\r
+ ((FLAG) == ETH_MAC_FLAG_PMT))\r
+\r
+/* ETHERNET MAC Interrupts ---------------------------------------------------*/\r
+#define ETH_MAC_IT_TST ((u32)0x00000200) /* Time stamp trigger interrupt (on MAC) */\r
+#define ETH_MAC_IT_MMCT ((u32)0x00000040) /* MMC transmit interrupt */\r
+#define ETH_MAC_IT_MMCR ((u32)0x00000020) /* MMC receive interrupt */\r
+#define ETH_MAC_IT_MMC ((u32)0x00000010) /* MMC interrupt (on MAC) */\r
+#define ETH_MAC_IT_PMT ((u32)0x00000008) /* PMT interrupt (on MAC) */\r
+\r
+#define IS_ETH_MAC_IT(IT) ((((IT) & (u32)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \\r
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \\r
+ ((IT) == ETH_MAC_IT_PMT))\r
+\r
+/* ETHERNET MAC addresses ----------------------------------------------------*/\r
+#define ETH_MAC_Address0 ((u32)0x00000000)\r
+#define ETH_MAC_Address1 ((u32)0x00000008)\r
+#define ETH_MAC_Address2 ((u32)0x00000010)\r
+#define ETH_MAC_Address3 ((u32)0x00000018)\r
+\r
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \\r
+ ((ADDRESS) == ETH_MAC_Address1) || \\r
+ ((ADDRESS) == ETH_MAC_Address2) || \\r
+ ((ADDRESS) == ETH_MAC_Address3))\r
+\r
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \\r
+ ((ADDRESS) == ETH_MAC_Address2) || \\r
+ ((ADDRESS) == ETH_MAC_Address3))\r
+\r
+/* ETHERNET MAC addresses filter: SA/DA filed of received frames ------------*/\r
+#define ETH_MAC_AddressFilter_SA ((u32)0x00000000)\r
+#define ETH_MAC_AddressFilter_DA ((u32)0x00000008)\r
+\r
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \\r
+ ((FILTER) == ETH_MAC_AddressFilter_DA))\r
+\r
+/* ETHERNET MAC addresses filter: Mask bytes ---------------------------------*/\r
+#define ETH_MAC_AddressMask_Byte6 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+#define ETH_MAC_AddressMask_Byte5 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+#define ETH_MAC_AddressMask_Byte4 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+#define ETH_MAC_AddressMask_Byte3 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+#define ETH_MAC_AddressMask_Byte2 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+#define ETH_MAC_AddressMask_Byte1 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */\r
+\r
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \\r
+ ((MASK) == ETH_MAC_AddressMask_Byte5) || \\r
+ ((MASK) == ETH_MAC_AddressMask_Byte4) || \\r
+ ((MASK) == ETH_MAC_AddressMask_Byte3) || \\r
+ ((MASK) == ETH_MAC_AddressMask_Byte2) || \\r
+ ((MASK) == ETH_MAC_AddressMask_Byte1))\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Ethernet DMA Desciptors defines */\r
+/*----------------------------------------------------------------------------*/\r
+/* ETHERNET DMA Tx descriptor flags --------------------------------------------------------*/\r
+#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \\r
+ ((FLAG) == ETH_DMATxDesc_IC) || \\r
+ ((FLAG) == ETH_DMATxDesc_LS) || \\r
+ ((FLAG) == ETH_DMATxDesc_FS) || \\r
+ ((FLAG) == ETH_DMATxDesc_DC) || \\r
+ ((FLAG) == ETH_DMATxDesc_DP) || \\r
+ ((FLAG) == ETH_DMATxDesc_TTSE) || \\r
+ ((FLAG) == ETH_DMATxDesc_TER) || \\r
+ ((FLAG) == ETH_DMATxDesc_TCH) || \\r
+ ((FLAG) == ETH_DMATxDesc_TTSS) || \\r
+ ((FLAG) == ETH_DMATxDesc_IHE) || \\r
+ ((FLAG) == ETH_DMATxDesc_ES) || \\r
+ ((FLAG) == ETH_DMATxDesc_JT) || \\r
+ ((FLAG) == ETH_DMATxDesc_FF) || \\r
+ ((FLAG) == ETH_DMATxDesc_PCE) || \\r
+ ((FLAG) == ETH_DMATxDesc_LCA) || \\r
+ ((FLAG) == ETH_DMATxDesc_NC) || \\r
+ ((FLAG) == ETH_DMATxDesc_LCO) || \\r
+ ((FLAG) == ETH_DMATxDesc_EC) || \\r
+ ((FLAG) == ETH_DMATxDesc_VF) || \\r
+ ((FLAG) == ETH_DMATxDesc_CC) || \\r
+ ((FLAG) == ETH_DMATxDesc_ED) || \\r
+ ((FLAG) == ETH_DMATxDesc_UF) || \\r
+ ((FLAG) == ETH_DMATxDesc_DB))\r
+\r
+/* ETHERNET DMA Tx descriptor segment ----------------------------------------*/\r
+#define ETH_DMATxDesc_LastSegment ((u32)0x40000000) /* Last Segment */\r
+#define ETH_DMATxDesc_FirstSegment ((u32)0x20000000) /* First Segment */\r
+\r
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \\r
+ ((SEGMENT) == ETH_DMATxDesc_FirstSegment))\r
+\r
+/* ETHERNET DMA Tx descriptor Checksum Insertion Control --------------------*/\r
+#define ETH_DMATxDesc_ChecksumByPass ((u32)0x00000000) /* Checksum engine bypass */\r
+#define ETH_DMATxDesc_ChecksumIPV4Header ((u32)0x00400000) /* IPv4 header checksum insertion */\r
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((u32)0x00800000) /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */\r
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((u32)0x00C00000) /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */\r
+\r
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \\r
+ ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \\r
+ ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \\r
+ ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull))\r
+\r
+/* ETHERNET DMA Tx Desciptor buffer size */\r
+#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)\r
+\r
+/* ETHERNET DMA Rx descriptor flags --------------------------------------------------------*/\r
+#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \\r
+ ((FLAG) == ETH_DMARxDesc_AFM) || \\r
+ ((FLAG) == ETH_DMARxDesc_ES) || \\r
+ ((FLAG) == ETH_DMARxDesc_DE) || \\r
+ ((FLAG) == ETH_DMARxDesc_SAF) || \\r
+ ((FLAG) == ETH_DMARxDesc_LE) || \\r
+ ((FLAG) == ETH_DMARxDesc_OE) || \\r
+ ((FLAG) == ETH_DMARxDesc_VLAN) || \\r
+ ((FLAG) == ETH_DMARxDesc_FS) || \\r
+ ((FLAG) == ETH_DMARxDesc_LS) || \\r
+ ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \\r
+ ((FLAG) == ETH_DMARxDesc_RxLongFrame) || \\r
+ ((FLAG) == ETH_DMARxDesc_LC) || \\r
+ ((FLAG) == ETH_DMARxDesc_FT) || \\r
+ ((FLAG) == ETH_DMARxDesc_RWT) || \\r
+ ((FLAG) == ETH_DMARxDesc_RE) || \\r
+ ((FLAG) == ETH_DMARxDesc_DBE) || \\r
+ ((FLAG) == ETH_DMARxDesc_CE) || \\r
+ ((FLAG) == ETH_DMARxDesc_MAMPCE))\r
+\r
+/* ETHERNET DMA Rx descriptor buffers ---------------------------------------*/\r
+#define ETH_DMARxDesc_Buffer1 ((u32)0x00000000) /* DMA Rx Desc Buffer1 */\r
+#define ETH_DMARxDesc_Buffer2 ((u32)0x00000001) /* DMA Rx Desc Buffer2 */\r
+\r
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \\r
+ ((BUFFER) == ETH_DMARxDesc_Buffer2))\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Ethernet DMA defines */\r
+/*----------------------------------------------------------------------------*/\r
+/* ETHERNET Drop TCP/IP Checksum Error Frame ---------------------------------*/\r
+#define ETH_DropTCPIPChecksumErrorFrame_Enable ((u32)0x00000000)\r
+#define ETH_DropTCPIPChecksumErrorFrame_Disable ((u32)0x04000000)\r
+\r
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \\r
+ ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable))\r
+\r
+/* ETHERNET Receive Store Forward --------------------------------------------*/\r
+#define ETH_ReceiveStoreForward_Enable ((u32)0x02000000)\r
+#define ETH_ReceiveStoreForward_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \\r
+ ((CMD) == ETH_ReceiveStoreForward_Disable))\r
+\r
+/* ETHERNET Flush Received Frame ---------------------------------------------*/\r
+#define ETH_FlushReceivedFrame_Enable ((u32)0x00000000)\r
+#define ETH_FlushReceivedFrame_Disable ((u32)0x01000000)\r
+\r
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \\r
+ ((CMD) == ETH_FlushReceivedFrame_Disable))\r
+\r
+/* ETHERNET Transmit Store Forward -------------------------------------------*/\r
+#define ETH_TransmitStoreForward_Enable ((u32)0x00200000)\r
+#define ETH_TransmitStoreForward_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \\r
+ ((CMD) == ETH_TransmitStoreForward_Disable))\r
+\r
+/* ETHERNET Transmit Threshold Control ---------------------------------------*/\r
+#define ETH_TransmitThresholdControl_64Bytes ((u32)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+#define ETH_TransmitThresholdControl_128Bytes ((u32)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+#define ETH_TransmitThresholdControl_192Bytes ((u32)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+#define ETH_TransmitThresholdControl_256Bytes ((u32)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+#define ETH_TransmitThresholdControl_40Bytes ((u32)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+#define ETH_TransmitThresholdControl_32Bytes ((u32)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+#define ETH_TransmitThresholdControl_24Bytes ((u32)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+#define ETH_TransmitThresholdControl_16Bytes ((u32)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+\r
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes))\r
+\r
+/* ETHERNET Forward Error Frames ---------------------------------------------*/\r
+#define ETH_ForwardErrorFrames_Enable ((u32)0x00000080)\r
+#define ETH_ForwardErrorFrames_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \\r
+ ((CMD) == ETH_ForwardErrorFrames_Disable))\r
+\r
+/* ETHERNET Forward Undersized Good Frames -----------------------------------*/\r
+#define ETH_ForwardUndersizedGoodFrames_Enable ((u32)0x00000040)\r
+#define ETH_ForwardUndersizedGoodFrames_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \\r
+ ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable))\r
+\r
+/* ETHERNET Receive Threshold Control ----------------------------------------*/\r
+#define ETH_ReceiveThresholdControl_64Bytes ((u32)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */\r
+#define ETH_ReceiveThresholdControl_32Bytes ((u32)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */\r
+#define ETH_ReceiveThresholdControl_96Bytes ((u32)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */\r
+#define ETH_ReceiveThresholdControl_128Bytes ((u32)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */\r
+\r
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \\r
+ ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \\r
+ ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \\r
+ ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes))\r
+\r
+/* ETHERNET Second Frame Operate ---------------------------------------------*/\r
+#define ETH_SecondFrameOperate_Enable ((u32)0x00000004)\r
+#define ETH_SecondFrameOperate_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \\r
+ ((CMD) == ETH_SecondFrameOperate_Disable))\r
+\r
+/* ETHERNET Address Aligned Beats --------------------------------------------*/\r
+#define ETH_AddressAlignedBeats_Enable ((u32)0x02000000)\r
+#define ETH_AddressAlignedBeats_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \\r
+ ((CMD) == ETH_AddressAlignedBeats_Disable))\r
+\r
+/* ETHERNET Fixed Burst ------------------------------------------------------*/\r
+#define ETH_FixedBurst_Enable ((u32)0x00010000)\r
+#define ETH_FixedBurst_Disable ((u32)0x00000000)\r
+\r
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \\r
+ ((CMD) == ETH_FixedBurst_Disable))\r
+\r
+/* ETHERNET Rx DMA Burst Length ----------------------------------------------*/\r
+#define ETH_RxDMABurstLength_1Beat ((u32)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+#define ETH_RxDMABurstLength_2Beat ((u32)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+#define ETH_RxDMABurstLength_4Beat ((u32)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RxDMABurstLength_8Beat ((u32)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RxDMABurstLength_16Beat ((u32)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RxDMABurstLength_32Beat ((u32)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+\r
+#define ETH_RxDMABurstLength_4xPBL_4Beat ((u32)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RxDMABurstLength_4xPBL_8Beat ((u32)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RxDMABurstLength_4xPBL_16Beat ((u32)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RxDMABurstLength_4xPBL_32Beat ((u32)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+#define ETH_RxDMABurstLength_4xPBL_64Beat ((u32)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+#define ETH_RxDMABurstLength_4xPBL_128Beat ((u32)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */\r
+\r
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat))\r
+\r
+/* ETHERNET Tx DMA Burst Length ----------------------------------------------*/\r
+#define ETH_TxDMABurstLength_1Beat ((u32)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+#define ETH_TxDMABurstLength_2Beat ((u32)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+#define ETH_TxDMABurstLength_4Beat ((u32)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TxDMABurstLength_8Beat ((u32)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TxDMABurstLength_16Beat ((u32)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TxDMABurstLength_32Beat ((u32)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+\r
+#define ETH_TxDMABurstLength_4xPBL_4Beat ((u32)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TxDMABurstLength_4xPBL_8Beat ((u32)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TxDMABurstLength_4xPBL_16Beat ((u32)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TxDMABurstLength_4xPBL_32Beat ((u32)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+#define ETH_TxDMABurstLength_4xPBL_64Beat ((u32)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+#define ETH_TxDMABurstLength_4xPBL_128Beat ((u32)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+\r
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat))\r
+\r
+/* ETHERNET DMA Desciptor SkipLength */\r
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)\r
+\r
+/* ETHERNET DMA Arbitration --------------------------------------------------*/\r
+#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((u32)0x00000000)\r
+#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((u32)0x00004000)\r
+#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((u32)0x00008000)\r
+#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((u32)0x0000C000)\r
+#define ETH_DMAArbitration_RxPriorTx ((u32)0x00000002)\r
+\r
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \\r
+ ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \\r
+ ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \\r
+ ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \\r
+ ((RATIO) == ETH_DMAArbitration_RxPriorTx))\r
+\r
+/* ETHERNET DMA Flags ---------------------------------------------------*/\r
+#define ETH_DMA_FLAG_TST ((u32)0x20000000) /* Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_PMT ((u32)0x10000000) /* PMT interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_MMC ((u32)0x08000000) /* MMC interrupt (on DMA) */\r
+\r
+#define ETH_DMA_FLAG_DataTransferError ((u32)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMA_FLAG_ReadWriteError ((u32)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */\r
+#define ETH_DMA_FLAG_AccessError ((u32)0x02000000) /* Error bits 0-data buffer, 1-desc. access */\r
+#define ETH_DMA_FLAG_NIS ((u32)0x00010000) /* Normal interrupt summary flag */\r
+#define ETH_DMA_FLAG_AIS ((u32)0x00008000) /* Abnormal interrupt summary flag */\r
+#define ETH_DMA_FLAG_ER ((u32)0x00004000) /* Early receive flag */\r
+#define ETH_DMA_FLAG_FBE ((u32)0x00002000) /* Fatal bus error flag */\r
+#define ETH_DMA_FLAG_ET ((u32)0x00000400) /* Early transmit flag */\r
+#define ETH_DMA_FLAG_RWT ((u32)0x00000200) /* Receive watchdog timeout flag */\r
+#define ETH_DMA_FLAG_RPS ((u32)0x00000100) /* Receive process stopped flag */\r
+#define ETH_DMA_FLAG_RBU ((u32)0x00000080) /* Receive buffer unavailable flag */\r
+#define ETH_DMA_FLAG_R ((u32)0x00000040) /* Receive flag */\r
+#define ETH_DMA_FLAG_TU ((u32)0x00000020) /* Underflow flag */\r
+#define ETH_DMA_FLAG_RO ((u32)0x00000010) /* Overflow flag */\r
+#define ETH_DMA_FLAG_TJT ((u32)0x00000008) /* Transmit jabber timeout flag */\r
+#define ETH_DMA_FLAG_TBU ((u32)0x00000004) /* Transmit buffer unavailable flag */\r
+#define ETH_DMA_FLAG_TPS ((u32)0x00000002) /* Transmit process stopped flag */\r
+#define ETH_DMA_FLAG_T ((u32)0x00000001) /* Transmit flag */\r
+\r
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (u32)0xFFFE1800) == 0x00) && ((FLAG) != 0x00))\r
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \\r
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_T))\r
+\r
+/* ETHERNET DMA Interrupts ---------------------------------------------------*/\r
+#define ETH_DMA_IT_TST ((u32)0x20000000) /* Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_IT_PMT ((u32)0x10000000) /* PMT interrupt (on DMA) */\r
+#define ETH_DMA_IT_MMC ((u32)0x08000000) /* MMC interrupt (on DMA) */\r
+\r
+#define ETH_DMA_IT_NIS ((u32)0x00010000) /* Normal interrupt summary */\r
+#define ETH_DMA_IT_AIS ((u32)0x00008000) /* Abnormal interrupt summary */\r
+#define ETH_DMA_IT_ER ((u32)0x00004000) /* Early receive interrupt */\r
+#define ETH_DMA_IT_FBE ((u32)0x00002000) /* Fatal bus error interrupt */\r
+#define ETH_DMA_IT_ET ((u32)0x00000400) /* Early transmit interrupt */\r
+#define ETH_DMA_IT_RWT ((u32)0x00000200) /* Receive watchdog timeout interrupt */\r
+#define ETH_DMA_IT_RPS ((u32)0x00000100) /* Receive process stopped interrupt */\r
+#define ETH_DMA_IT_RBU ((u32)0x00000080) /* Receive buffer unavailable interrupt */\r
+#define ETH_DMA_IT_R ((u32)0x00000040) /* Receive interrupt */\r
+#define ETH_DMA_IT_TU ((u32)0x00000020) /* Underflow interrupt */\r
+#define ETH_DMA_IT_RO ((u32)0x00000010) /* Overflow interrupt */\r
+#define ETH_DMA_IT_TJT ((u32)0x00000008) /* Transmit jabber timeout interrupt */\r
+#define ETH_DMA_IT_TBU ((u32)0x00000004) /* Transmit buffer unavailable interrupt */\r
+#define ETH_DMA_IT_TPS ((u32)0x00000002) /* Transmit process stopped interrupt */\r
+#define ETH_DMA_IT_T ((u32)0x00000001) /* Transmit interrupt */\r
+\r
+#define IS_ETH_DMA_IT(IT) ((((IT) & (u32)0xFFFE1800) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \\r
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \\r
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \\r
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \\r
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \\r
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \\r
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \\r
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \\r
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))\r
+\r
+/* ETHERNET DMA transmit process state --------------------------------------------------------*/\r
+#define ETH_DMA_TransmitProcess_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Tx Command issued */\r
+#define ETH_DMA_TransmitProcess_Fetching ((u32)0x00100000) /* Running - fetching the Tx descriptor */\r
+#define ETH_DMA_TransmitProcess_Waiting ((u32)0x00200000) /* Running - waiting for status */\r
+#define ETH_DMA_TransmitProcess_Reading ((u32)0x00300000) /* Running - reading the data from host memory */\r
+#define ETH_DMA_TransmitProcess_Suspended ((u32)0x00600000) /* Suspended - Tx Desciptor unavailabe */\r
+#define ETH_DMA_TransmitProcess_Closing ((u32)0x00700000) /* Running - closing Rx descriptor */\r
+\r
+/* ETHERNET DMA receive process state --------------------------------------------------------*/\r
+#define ETH_DMA_ReceiveProcess_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Rx Command issued */\r
+#define ETH_DMA_ReceiveProcess_Fetching ((u32)0x00020000) /* Running - fetching the Rx descriptor */\r
+#define ETH_DMA_ReceiveProcess_Waiting ((u32)0x00060000) /* Running - waiting for packet */\r
+#define ETH_DMA_ReceiveProcess_Suspended ((u32)0x00080000) /* Suspended - Rx Desciptor unavailable */\r
+#define ETH_DMA_ReceiveProcess_Closing ((u32)0x000A0000) /* Running - closing descriptor */\r
+#define ETH_DMA_ReceiveProcess_Queuing ((u32)0x000E0000) /* Running - queuing the recieve frame into host memory */\r
+\r
+/* ETHERNET DMA overflow --------------------------------------------------------*/\r
+#define ETH_DMA_Overflow_RxFIFOCounter ((u32)0x10000000) /* Overflow bit for FIFO overflow counter */\r
+#define ETH_DMA_Overflow_MissedFrameCounter ((u32)0x00010000) /* Overflow bit for missed frame counter */\r
+\r
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \\r
+ ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter))\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Ethernet PMT defines */\r
+/*----------------------------------------------------------------------------*/\r
+/* ETHERNET PMT Flags --------------------------------------------------------*/\r
+#define ETH_PMT_FLAG_WUFFRPR ((u32)0x80000000) /* Wake-Up Frame Filter Register Poniter Reset */\r
+#define ETH_PMT_FLAG_WUFR ((u32)0x00000040) /* Wake-Up Frame Received */\r
+#define ETH_PMT_FLAG_MPR ((u32)0x00000020) /* Magic Packet Received */\r
+\r
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \\r
+ ((FLAG) == ETH_PMT_FLAG_MPR))\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Ethernet MMC defines */\r
+/*----------------------------------------------------------------------------*/\r
+/* ETHERNET MMC Tx Interrupts */\r
+#define ETH_MMC_IT_TGF ((u32)0x00200000) /* When Tx good frame counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFMSC ((u32)0x00008000) /* When Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFSC ((u32)0x00004000) /* When Tx good single col counter reaches half the maximum value */\r
+\r
+/* ETHERNET MMC Rx Interrupts */\r
+#define ETH_MMC_IT_RGUF ((u32)0x10020000) /* When Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFAE ((u32)0x10000040) /* When Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFCE ((u32)0x10000020) /* When Rx crc error counter reaches half the maximum value */\r
+\r
+#define IS_ETH_MMC_IT(IT) (((((IT) & (u32)0xFFDF3FFF) == 0x00) || (((IT) & (u32)0xEFFDFF9F) == 0x00)) && \\r
+ ((IT) != 0x00))\r
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \\r
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \\r
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))\r
+\r
+/* ETHERNET MMC Registers */\r
+#define ETH_MMCCR ((u32)0x00000100) /* MMC CR register */\r
+#define ETH_MMCRIR ((u32)0x00000104) /* MMC RIR register */\r
+#define ETH_MMCTIR ((u32)0x00000108) /* MMC TIR register */\r
+#define ETH_MMCRIMR ((u32)0x0000010C) /* MMC RIMR register */\r
+#define ETH_MMCTIMR ((u32)0x00000110) /* MMC TIMR register */\r
+#define ETH_MMCTGFSCCR ((u32)0x0000014C) /* MMC TGFSCCR register */\r
+#define ETH_MMCTGFMSCCR ((u32)0x00000150) /* MMC TGFMSCCR register */\r
+#define ETH_MMCTGFCR ((u32)0x00000168) /* MMC TGFCR register */\r
+#define ETH_MMCRFCECR ((u32)0x00000194) /* MMC RFCECR register */\r
+#define ETH_MMCRFAECR ((u32)0x00000198) /* MMC RFAECR register */\r
+#define ETH_MMCRGUFCR ((u32)0x000001C4) /* MMC RGUFCR register */\r
+\r
+/* ETHERNET MMC registers */\r
+#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \\r
+ ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \\r
+ ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \\r
+ ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \\r
+ ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \\r
+ ((REG) == ETH_MMCRGUFCR))\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Ethernet PTP defines */\r
+/*----------------------------------------------------------------------------*/\r
+/* ETHERNET PTP time update method -------------------------------------------*/\r
+#define ETH_PTP_FineUpdate ((u32)0x00000001) /* Fine Update method */\r
+#define ETH_PTP_CoarseUpdate ((u32)0x00000000) /* Coarse Update method */\r
+\r
+#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \\r
+ ((UPDATE) == ETH_PTP_CoarseUpdate))\r
+\r
+/* ETHERNET PTP Flags --------------------------------------------------------*/\r
+#define ETH_PTP_FLAG_TSARU ((u32)0x00000020) /* Addend Register Update */\r
+#define ETH_PTP_FLAG_TSITE ((u32)0x00000010) /* Time Stamp Interrupt Trigger */\r
+#define ETH_PTP_FLAG_TSSTU ((u32)0x00000008) /* Time Stamp Update */\r
+#define ETH_PTP_FLAG_TSSTI ((u32)0x00000004) /* Time Stamp Initialize */\r
+\r
+#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \\r
+ ((FLAG) == ETH_PTP_FLAG_TSITE) || \\r
+ ((FLAG) == ETH_PTP_FLAG_TSSTU) || \\r
+ ((FLAG) == ETH_PTP_FLAG_TSSTI))\r
+\r
+/* ETHERNET PTP subsecond increment */\r
+#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF)\r
+\r
+/* ETHERNET PTP time sign ----------------------------------------------------*/\r
+#define ETH_PTP_PositiveTime ((u32)0x00000000) /* Positive time value */\r
+#define ETH_PTP_NegativeTime ((u32)0x80000000) /* Negative time value */\r
+\r
+#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \\r
+ ((SIGN) == ETH_PTP_NegativeTime))\r
+\r
+/* ETHERNET PTP time stamp low update */\r
+#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF)\r
+\r
+/* ETHERNET PTP registers */\r
+#define ETH_PTPTSCR ((u32)0x00000700) /* PTP TSCR register */\r
+#define ETH_PTPSSIR ((u32)0x00000704) /* PTP SSIR register */\r
+#define ETH_PTPTSHR ((u32)0x00000708) /* PTP TSHR register */\r
+#define ETH_PTPTSLR ((u32)0x0000070C) /* PTP TSLR register */\r
+#define ETH_PTPTSHUR ((u32)0x00000710) /* PTP TSHUR register */\r
+#define ETH_PTPTSLUR ((u32)0x00000714) /* PTP TSLUR register */\r
+#define ETH_PTPTSAR ((u32)0x00000718) /* PTP TSAR register */\r
+#define ETH_PTPTTHR ((u32)0x0000071C) /* PTP TTHR register */\r
+#define ETH_PTPTTLR ((u32)0x00000720) /* PTP TTLR register */\r
+\r
+#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \\r
+ ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \\r
+ ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \\r
+ ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \\r
+ ((REG) == ETH_PTPTTLR))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void ETH_DeInit(void);\r
+u32 ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress);\r
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);\r
+void ETH_SoftwareReset(void);\r
+FlagStatus ETH_GetSoftwareResetStatus(void);\r
+void ETH_Start(void);\r
+u32 ETH_HandleTxPkt(u32 addr, u16 FrameLength);\r
+u32 ETH_HandleRxPkt(u32 addr);\r
+\r
+\r
+u32 ETH_GetRxPktSize(void);\r
+void ETH_DropRxPkt(void);\r
+\r
+/*--------------------------------- PHY ------------------------------------*/\r
+u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg);\r
+u32 ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue);\r
+u32 ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState);\r
+/*--------------------------------- MAC ------------------------------------*/\r
+void ETH_MACTransmissionCmd(FunctionalState NewState);\r
+void ETH_MACReceptionCmd(FunctionalState NewState);\r
+FlagStatus ETH_GetFlowControlBusyStatus(void);\r
+void ETH_InitiatePauseControlFrame(void);\r
+void ETH_BackPressureActivationCmd(FunctionalState NewState);\r
+FlagStatus ETH_GetMACFlagStatus(u32 ETH_MAC_FLAG);\r
+ITStatus ETH_GetMACITStatus(u32 ETH_MAC_IT);\r
+void ETH_MACITConfig(u32 ETH_MAC_IT, FunctionalState NewState);\r
+void ETH_MACAddressConfig(u32 MacAddr, u8 *Addr);\r
+void ETH_GetMACAddress(u32 MacAddr, u8 *Addr);\r
+void ETH_MACAddressPerfectFilterCmd(u32 MacAddr, FunctionalState NewState);\r
+void ETH_MACAddressFilterConfig(u32 MacAddr, u32 Filter);\r
+void ETH_MACAddressMaskBytesFilterConfig(u32 MacAddr, u32 MaskByte);\r
+/*----------------------- DMA Tx/Rx descriptors ----------------------------*/\r
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, u32 TxBuffCount);\r
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, u32 TxBuffCount);\r
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, u32 ETH_DMATxDescFlag);\r
+u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);\r
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);\r
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_FrameSegment);\r
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_Checksum);\r
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 BufferSize1, u32 BufferSize2);\r
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, u32 RxBuffCount);\r
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, u32 RxBuffCount);\r
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, u32 ETH_DMARxDescFlag);\r
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);\r
+u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);\r
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);\r
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);\r
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);\r
+u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, u32 DMARxDesc_Buffer);\r
+/*--------------------------------- DMA ------------------------------------*/\r
+FlagStatus ETH_GetDMAFlagStatus(u32 ETH_DMA_FLAG);\r
+void ETH_DMAClearFlag(u32 ETH_DMA_FLAG);\r
+ITStatus ETH_GetDMAITStatus(u32 ETH_DMA_IT);\r
+void ETH_DMAClearITPendingBit(u32 ETH_DMA_IT);\r
+u32 ETH_GetTransmitProcessState(void);\r
+u32 ETH_GetReceiveProcessState(void);\r
+void ETH_FlushTransmitFIFO(void);\r
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void);\r
+void ETH_DMATransmissionCmd(FunctionalState NewState);\r
+void ETH_DMAReceptionCmd(FunctionalState NewState);\r
+void ETH_DMAITConfig(u32 ETH_DMA_IT, FunctionalState NewState);\r
+FlagStatus ETH_GetDMAOverflowStatus(u32 ETH_DMA_Overflow);\r
+u32 ETH_GetRxOverflowMissedFrameCounter(void);\r
+u32 ETH_GetBufferUnavailableMissedFrameCounter(void);\r
+u32 ETH_GetCurrentTxDescStartAddress(void);\r
+u32 ETH_GetCurrentRxDescStartAddress(void);\r
+u32 ETH_GetCurrentTxBufferAddress(void);\r
+u32 ETH_GetCurrentRxBufferAddress(void);\r
+void ETH_ResumeDMATransmission(void);\r
+void ETH_ResumeDMAReception(void);\r
+/*--------------------------------- PMT ------------------------------------*/\r
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void);\r
+void ETH_SetWakeUpFrameFilterRegister(u32 *Buffer);\r
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);\r
+FlagStatus ETH_GetPMTFlagStatus(u32 ETH_PMT_FLAG);\r
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);\r
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState);\r
+void ETH_PowerDownCmd(FunctionalState NewState);\r
+/*--------------------------------- MMC ------------------------------------*/\r
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState);\r
+void ETH_MMCResetOnReadCmd(FunctionalState NewState);\r
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState);\r
+void ETH_MMCCountersReset(void);\r
+void ETH_MMCITConfig(u32 ETH_MMC_IT, FunctionalState NewState);\r
+ITStatus ETH_GetMMCITStatus(u32 ETH_MMC_IT);\r
+u32 ETH_GetMMCRegister(u32 ETH_MMCReg);\r
+/*--------------------------------- PTP ------------------------------------*/\r
+u32 ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, u32 *PTPTxTab);\r
+u32 ETH_HandlePTPRxPkt(u8 *ppkt, u32 *PTPRxTab);\r
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, u32 TxBuffCount);\r
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, u32 RxBuffCount);\r
+void ETH_EnablePTPTimeStampAddend(void);\r
+void ETH_EnablePTPTimeStampInterruptTrigger(void);\r
+void ETH_EnablePTPTimeStampUpdate(void);\r
+void ETH_InitializePTPTimeStamp(void);\r
+void ETH_PTPUpdateMethodConfig(u32 UpdateMethod);\r
+void ETH_PTPTimeStampCmd(FunctionalState NewState);\r
+FlagStatus ETH_GetPTPFlagStatus(u32 ETH_PTP_FLAG);\r
+void ETH_SetPTPSubSecondIncrement(u32 SubSecondValue);\r
+void ETH_SetPTPTimeStampUpdate(u32 Sign, u32 SecondValue, u32 SubSecondValue);\r
+void ETH_SetPTPTimeStampAddend(u32 Value);\r
+void ETH_SetPTPTargetTime(u32 HighValue, u32 LowValue);\r
+u32 ETH_GetPTPRegister(u32 ETH_PTPReg);\r
+\r
+#endif /* __STM32FXXX_ETH_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f_eth_conf.h\r
+* Author : MCD Application Team\r
+* Version : VX.Y.Z\r
+* Date : mm/dd/2008\r
+* Description : ETHERNET firmware library configuration file.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F_ETH_CONF_H\r
+#define __STM32F_ETH_CONF_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_type.h"\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Uncomment the line below to compile the ETHERNET firmware library in DEBUG mode,\r
+ this will expanse the "assert_param" macro in the firmware library code (see \r
+ "Exported macro" section below) */\r
+/*#define ETH_DEBUG 1*/\r
+\r
+/* Comment the line below to disable the specific peripheral inclusion */\r
+/************************************* ETHERNET *******************************/\r
+#define _ETH_MAC\r
+//#define _ETH_PTP\r
+//#define _ETH_MMC\r
+#define _ETH_DMA\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef ETH_DEBUG\r
+/*******************************************************************************\r
+* Macro Name : eth_assert_param\r
+* Description : The eth_assert_param macro is used for ethernet function's parameters\r
+* check.\r
+* It is used only if the ethernet library is compiled in DEBUG mode. \r
+* Input : - expr: If expr is false, it calls assert_failed function\r
+* which reports the name of the source file and the source\r
+* line number of the call that failed. \r
+* If expr is true, it returns no value.\r
+* Return : None\r
+*******************************************************************************/ \r
+ #define eth_assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+ void assert_failed(u8* file, u32 line);\r
+#else\r
+ #define eth_assert_param(expr) ((void)0)\r
+#endif /* ETH_DEBUG */\r
+\r
+#endif /* __STM32F_ETH_CONF_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32fxxx_eth_lib.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.2\r
+* Date : 07/11/2008\r
+* Description : This file includes the peripherals header files in the\r
+* user application.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32FXXX_ETH_LIB_H\r
+#define __STM32FXXX_ETH_LIB_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32fxxx_eth_map.h"\r
+\r
+#ifdef _ETH_MAC\r
+//RP_Modif\r
+ #include "ipport.h"\r
+ #include "netbuf.h"\r
+ #include "stm32fxxx_eth.h"\r
+#endif /*_ETH_MAC */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void eth_debug(void);\r
+\r
+#endif /* __STM32FXXX_ETH_LIB_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32fxxx_eth_map.h\r
+* Author : MCD Application Team\r
+* Version : VX.Y.Z\r
+* Date : mm/dd/2008\r
+* Description : This file contains all ETHERNET peripheral register's\r
+* definitions and memory mapping.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32FXXX_ETH_MAP_H\r
+#define __STM32FXXX_ETH_MAP_H\r
+\r
+#ifndef EXT\r
+ #define EXT extern\r
+#endif /* EXT */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+\r
+#include "stm32fxxx_eth_conf.h"\r
+#include "stm32f10x_type.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/******************************************************************************/\r
+/* Ethernet Peripheral registers structures */\r
+/******************************************************************************/\r
+\r
+typedef struct\r
+{\r
+ vu32 MACCR;\r
+ vu32 MACFFR;\r
+ vu32 MACHTHR;\r
+ vu32 MACHTLR;\r
+ vu32 MACMIIAR;\r
+ vu32 MACMIIDR;\r
+ vu32 MACFCR;\r
+ vu32 MACVLANTR;\r
+ vu32 RESERVED0[2];\r
+ vu32 MACRWUFFR;\r
+ vu32 MACPMTCSR;\r
+ vu32 RESERVED1[2];\r
+ vu32 MACSR;\r
+ vu32 MACIMR;\r
+ vu32 MACA0HR;\r
+ vu32 MACA0LR;\r
+ vu32 MACA1HR;\r
+ vu32 MACA1LR;\r
+ vu32 MACA2HR;\r
+ vu32 MACA2LR;\r
+ vu32 MACA3HR;\r
+ vu32 MACA3LR;\r
+} ETH_MAC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 MMCCR;\r
+ vu32 MMCRIR;\r
+ vu32 MMCTIR;\r
+ vu32 MMCRIMR;\r
+ vu32 MMCTIMR;\r
+ vu32 RESERVED0[14];\r
+ vu32 MMCTGFSCCR;\r
+ vu32 MMCTGFMSCCR;\r
+ vu32 RESERVED1[5];\r
+ vu32 MMCTGFCR;\r
+ vu32 RESERVED2[10];\r
+ vu32 MMCRFCECR;\r
+ vu32 MMCRFAER;\r
+ vu32 RESERVED3[10];\r
+ vu32 MMCRGUFCR;\r
+} ETH_MMC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 PTPTSCR;\r
+ vu32 PTPSSIR;\r
+ vu32 PTPTSHR;\r
+ vu32 PTPTSLR;\r
+ vu32 PTPTSHUR;\r
+ vu32 PTPTSLUR;\r
+ vu32 PTPTSAR;\r
+ vu32 PTPTTHR;\r
+ vu32 PTPTTLR;\r
+} ETH_PTP_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 DMABMR;\r
+ vu32 DMATPDR;\r
+ vu32 DMARPDR;\r
+ vu32 DMARDLAR;\r
+ vu32 DMATDLAR;\r
+ vu32 DMASR;\r
+ vu32 DMAOMR;\r
+ vu32 DMAIER;\r
+ vu32 DMAMFBOCR;\r
+ vu32 RESERVED0[9];\r
+ vu32 DMACHTDR;\r
+ vu32 DMACHRDR;\r
+ vu32 DMACHTBAR;\r
+ vu32 DMACHRBAR;\r
+} ETH_DMA_TypeDef;\r
+\r
+/******************************************************************************/\r
+/* Ethernet MAC Registers bits definitions */\r
+/******************************************************************************/\r
+//#define IPNAME_REGNAME_BITNAME /* BIT MASK */\r
+\r
+/* Bit definition for Ethernet MAC Control Register register */\r
+#define ETH_MACCR_WD ((u32)0x00800000) /* Watchdog disable */\r
+#define ETH_MACCR_JD ((u32)0x00400000) /* Jabber disable */\r
+#define ETH_MACCR_JFE ((u32)0x00100000) /* Jumbo frame enable */\r
+#define ETH_MACCR_IFG ((u32)0x000E0000) /* Inter-frame gap */\r
+ #define ETH_MACCR_IFG_96Bit ((u32)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */\r
+ #define ETH_MACCR_IFG_88Bit ((u32)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */\r
+ #define ETH_MACCR_IFG_80Bit ((u32)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */\r
+ #define ETH_MACCR_IFG_72Bit ((u32)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */\r
+ #define ETH_MACCR_IFG_64Bit ((u32)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */\r
+ #define ETH_MACCR_IFG_56Bit ((u32)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */\r
+ #define ETH_MACCR_IFG_48Bit ((u32)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */\r
+ #define ETH_MACCR_IFG_40Bit ((u32)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */\r
+#define ETH_MACCR_CSD ((u32)0x00010000) /* Carrier sense disable (during transmission) */\r
+#define ETH_MACCR_FES ((u32)0x00004000) /* Fast ethernet speed */\r
+#define ETH_MACCR_ROD ((u32)0x00002000) /* Receive own disable */\r
+#define ETH_MACCR_LM ((u32)0x00001000) /* loopback mode */\r
+#define ETH_MACCR_DM ((u32)0x00000800) /* Duplex mode */\r
+#define ETH_MACCR_IPCO ((u32)0x00000400) /* IP Checksum offload */\r
+#define ETH_MACCR_RD ((u32)0x00000200) /* Retry disable */\r
+#define ETH_MACCR_APCS ((u32)0x00000080) /* Automatic Pad/CRC stripping */\r
+#define ETH_MACCR_BL ((u32)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling\r
+ a transmission attempt during retries after a collision: 0 =< r <2^k */\r
+ #define ETH_MACCR_BL_10 ((u32)0x00000000) /* k = min (n, 10) */\r
+ #define ETH_MACCR_BL_8 ((u32)0x00000020) /* k = min (n, 8) */\r
+ #define ETH_MACCR_BL_4 ((u32)0x00000040) /* k = min (n, 4) */\r
+ #define ETH_MACCR_BL_1 ((u32)0x00000060) /* k = min (n, 1) */\r
+#define ETH_MACCR_DC ((u32)0x00000010) /* Defferal check */\r
+#define ETH_MACCR_TE ((u32)0x00000008) /* Transmitter enable */\r
+#define ETH_MACCR_RE ((u32)0x00000004) /* Receiver enable */\r
+\r
+/* Bit definition for Ethernet MAC Frame Filter Register */\r
+#define ETH_MACFFR_RA ((u32)0x80000000) /* Receive all */\r
+#define ETH_MACFFR_HPF ((u32)0x00000400) /* Hash or perfect filter */\r
+#define ETH_MACFFR_SAF ((u32)0x00000200) /* Source address filter enable */\r
+#define ETH_MACFFR_SAIF ((u32)0x00000100) /* SA inverse filtering */\r
+#define ETH_MACFFR_PCF ((u32)0x000000C0) /* Pass control frames: 3 cases */\r
+ #define ETH_MACFFR_PCF_BlockAll ((u32)0x00000040) /* MAC filters all control frames from reaching the application */\r
+ #define ETH_MACFFR_PCF_ForwardAll ((u32)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */\r
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((u32)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */\r
+#define ETH_MACFFR_BFD ((u32)0x00000020) /* Broadcast frame disable */\r
+#define ETH_MACFFR_PAM ((u32)0x00000010) /* Pass all mutlicast */\r
+#define ETH_MACFFR_DAIF ((u32)0x00000008) /* DA Inverse filtering */\r
+#define ETH_MACFFR_HM ((u32)0x00000004) /* Hash multicast */\r
+#define ETH_MACFFR_HU ((u32)0x00000002) /* Hash unicast */\r
+#define ETH_MACFFR_PM ((u32)0x00000001) /* Promiscuous mode */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table High Register */\r
+#define ETH_MACHTHR_HTH ((u32)0xFFFFFFFF) /* Hash table high */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table Low Register */\r
+#define ETH_MACHTLR_HTL ((u32)0xFFFFFFFF) /* Hash table low */\r
+\r
+/* Bit definition for Ethernet MAC MII Address Register */\r
+#define ETH_MACMIIAR_PA ((u32)0x0000F800) /* Physical layer address */\r
+#define ETH_MACMIIAR_MR ((u32)0x000007C0) /* MII register in the selected PHY */\r
+#define ETH_MACMIIAR_CR ((u32)0x0000001C) /* CR clock range: 6 cases */\r
+ #define ETH_MACMIIAR_CR_Div42 ((u32)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */\r
+ #define ETH_MACMIIAR_CR_Div16 ((u32)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */\r
+ #define ETH_MACMIIAR_CR_Div26 ((u32)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */\r
+#define ETH_MACMIIAR_MW ((u32)0x00000002) /* MII write */\r
+#define ETH_MACMIIAR_MB ((u32)0x00000001) /* MII busy */\r
+\r
+/* Bit definition for Ethernet MAC MII Data Register */\r
+#define ETH_MACMIIDR_MD ((u32)0x0000FFFF) /* MII data: read/write data from/to PHY */\r
+\r
+/* Bit definition for Ethernet MAC Flow Control Register */\r
+#define ETH_MACFCR_PT ((u32)0xFFFF0000) /* Pause time */\r
+#define ETH_MACFCR_ZQPD ((u32)0x00000080) /* Zero-quanta pause disable */\r
+#define ETH_MACFCR_PLT ((u32)0x00000030) /* Pause low threshold: 4 cases */\r
+ #define ETH_MACFCR_PLT_Minus4 ((u32)0x00000000) /* Pause time minus 4 slot times */\r
+ #define ETH_MACFCR_PLT_Minus28 ((u32)0x00000010) /* Pause time minus 28 slot times */\r
+ #define ETH_MACFCR_PLT_Minus144 ((u32)0x00000020) /* Pause time minus 144 slot times */\r
+ #define ETH_MACFCR_PLT_Minus256 ((u32)0x00000030) /* Pause time minus 256 slot times */\r
+#define ETH_MACFCR_UPFD ((u32)0x00000008) /* Unicast pause frame detect */\r
+#define ETH_MACFCR_RFCE ((u32)0x00000004) /* Receive flow control enable */\r
+#define ETH_MACFCR_TFCE ((u32)0x00000002) /* Transmit flow control enable */\r
+#define ETH_MACFCR_FCBBPA ((u32)0x00000001) /* Flow control busy/backpressure activate */\r
+\r
+/* Bit definition for Ethernet MAC VLAN Tag Register */\r
+#define ETH_MACVLANTR_VLANTC ((u32)0x00010000) /* 12-bit VLAN tag comparison */\r
+#define ETH_MACVLANTR_VLANTI ((u32)0x0000FFFF) /* VLAN tag identifier (for receive frames) */\r
+\r
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */\r
+#define ETH_MACRWUFFR_D ((u32)0xFFFFFFFF) /* Wake-up frame filter register data */\r
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\r
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\r
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\r
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\r
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\r
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\r
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -\r
+ RSVD - Filter1 Command - RSVD - Filter0 Command\r
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\r
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\r
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\r
+\r
+/* Bit definition for Ethernet MAC PMT Control and Status Register */\r
+#define ETH_MACPMTCSR_WFFRPR ((u32)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */\r
+#define ETH_MACPMTCSR_GU ((u32)0x00000200) /* Global Unicast */\r
+#define ETH_MACPMTCSR_WFR ((u32)0x00000040) /* Wake-Up Frame Received */\r
+#define ETH_MACPMTCSR_MPR ((u32)0x00000020) /* Magic Packet Received */\r
+#define ETH_MACPMTCSR_WFE ((u32)0x00000004) /* Wake-Up Frame Enable */\r
+#define ETH_MACPMTCSR_MPE ((u32)0x00000002) /* Magic Packet Enable */\r
+#define ETH_MACPMTCSR_PD ((u32)0x00000001) /* Power Down */\r
+\r
+/* Bit definition for Ethernet MAC Status Register */\r
+#define ETH_MACSR_TSTS ((u32)0x00000200) /* Time stamp trigger status */\r
+#define ETH_MACSR_MMCTS ((u32)0x00000040) /* MMC transmit status */\r
+#define ETH_MACSR_MMMCRS ((u32)0x00000020) /* MMC receive status */\r
+#define ETH_MACSR_MMCS ((u32)0x00000010) /* MMC status */\r
+#define ETH_MACSR_PMTS ((u32)0x00000008) /* PMT status */\r
+\r
+/* Bit definition for Ethernet MAC Interrupt Mask Register */\r
+#define ETH_MACIMR_TSTIM ((u32)0x00000200) /* Time stamp trigger interrupt mask */\r
+#define ETH_MACIMR_PMTIM ((u32)0x00000008) /* PMT interrupt mask */\r
+\r
+/* Bit definition for Ethernet MAC Address0 High Register */\r
+#define ETH_MACA0HR_MACA0H ((u32)0x0000FFFF) /* MAC address0 high */\r
+\r
+/* Bit definition for Ethernet MAC Address0 Low Register */\r
+#define ETH_MACA0LR_MACA0L ((u32)0xFFFFFFFF) /* MAC address0 low */\r
+\r
+/* Bit definition for Ethernet MAC Address1 High Register */\r
+#define ETH_MACA1HR_AE ((u32)0x80000000) /* Address enable */\r
+#define ETH_MACA1HR_SA ((u32)0x40000000) /* Source address */\r
+#define ETH_MACA1HR_MBC ((u32)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r
+ #define ETH_MACA1HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA1HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA1HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA1HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA1HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA1HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [7:0] */\r
+#define ETH_MACA1HR_MACA1H ((u32)0x0000FFFF) /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address1 Low Register */\r
+#define ETH_MACA1LR_MACA1L ((u32)0xFFFFFFFF) /* MAC address1 low */\r
+\r
+/* Bit definition for Ethernet MAC Address2 High Register */\r
+#define ETH_MACA2HR_AE ((u32)0x80000000) /* Address enable */\r
+#define ETH_MACA2HR_SA ((u32)0x40000000) /* Source address */\r
+#define ETH_MACA2HR_MBC ((u32)0x3F000000) /* Mask byte control */\r
+ #define ETH_MACA2HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA2HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA2HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA2HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA2HR_MACA2H ((u32)0x0000FFFF) /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address2 Low Register */\r
+#define ETH_MACA2LR_MACA2L ((u32)0xFFFFFFFF) /* MAC address2 low */\r
+\r
+/* Bit definition for Ethernet MAC Address3 High Register */\r
+#define ETH_MACA3HR_AE ((u32)0x80000000) /* Address enable */\r
+#define ETH_MACA3HR_SA ((u32)0x40000000) /* Source address */\r
+#define ETH_MACA3HR_MBC ((u32)0x3F000000) /* Mask byte control */\r
+ #define ETH_MACA2HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA2HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA2HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA2HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA3HR_MACA3H ((u32)0x0000FFFF) /* MAC address3 high */\r
+\r
+/* Bit definition for Ethernet MAC Address3 Low Register */\r
+#define ETH_MACA3LR_MACA3L ((u32)0xFFFFFFFF) /* MAC address3 low */\r
+\r
+/******************************************************************************/\r
+/* Ethernet MMC Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet MMC Contol Register */\r
+#define ETH_MMCCR_MCF ((u32)0x00000008) /* MMC Counter Freeze */\r
+#define ETH_MMCCR_ROR ((u32)0x00000004) /* Reset on Read */\r
+#define ETH_MMCCR_CSR ((u32)0x00000002) /* Counter Stop Rollover */\r
+#define ETH_MMCCR_CR ((u32)0x00000001) /* Counters Reset */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Register */\r
+#define ETH_MMCRIR_RGUFS ((u32)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFAES ((u32)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFCES ((u32)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */\r
+#define ETH_MMCTIR_TGFS ((u32)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFMSCS ((u32)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFSCS ((u32)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\r
+#define ETH_MMCRIMR_RGUFM ((u32)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFAEM ((u32)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFCEM ((u32)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\r
+#define ETH_MMCTIMR_TGFM ((u32)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFMSCM ((u32)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFSCM ((u32)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\r
+#define ETH_MMCTGFSCCR_TGFSCC ((u32)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\r
+#define ETH_MMCTGFMSCCR_TGFMSCC ((u32)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\r
+#define ETH_MMCTGFCR_TGFC ((u32)0xFFFFFFFF) /* Number of good frames transmitted. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\r
+#define ETH_MMCRFCECR_RFCEC ((u32)0xFFFFFFFF) /* Number of frames received with CRC error. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\r
+#define ETH_MMCRFAECR_RFAEC ((u32)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */\r
+\r
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\r
+#define ETH_MMCRGUFCR_RGUFC ((u32)0xFFFFFFFF) /* Number of good unicast frames received. */\r
+\r
+/******************************************************************************/\r
+/* Ethernet PTP Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */\r
+#define ETH_PTPTSCR_TSARU ((u32)0x00000020) /* Addend register update */\r
+#define ETH_PTPTSCR_TSITE ((u32)0x00000010) /* Time stamp interrupt trigger enable */\r
+#define ETH_PTPTSCR_TSSTU ((u32)0x00000008) /* Time stamp update */\r
+#define ETH_PTPTSCR_TSSTI ((u32)0x00000004) /* Time stamp initialize */\r
+#define ETH_PTPTSCR_TSFCU ((u32)0x00000002) /* Time stamp fine or coarse update */\r
+#define ETH_PTPTSCR_TSE ((u32)0x00000001) /* Time stamp enable */\r
+\r
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */\r
+#define ETH_PTPSSIR_STSSI ((u32)0x000000FF) /* System time Sub-second increment value */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Register */\r
+#define ETH_PTPTSHR_STS ((u32)0xFFFFFFFF) /* System Time second */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Register */\r
+#define ETH_PTPTSLR_STPNS ((u32)0x80000000) /* System Time Positive or negative time */\r
+#define ETH_PTPTSLR_STSS ((u32)0x7FFFFFFF) /* System Time sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */\r
+#define ETH_PTPTSHUR_TSUS ((u32)0xFFFFFFFF) /* Time stamp update seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\r
+#define ETH_PTPTSLUR_TSUPNS ((u32)0x80000000) /* Time stamp update Positive or negative time */\r
+#define ETH_PTPTSLUR_TSUSS ((u32)0x7FFFFFFF) /* Time stamp update sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */\r
+#define ETH_PTPTSAR_TSA ((u32)0xFFFFFFFF) /* Time stamp addend */\r
+\r
+/* Bit definition for Ethernet PTP Target Time High Register */\r
+#define ETH_PTPTTHR_TTSH ((u32)0xFFFFFFFF) /* Target time stamp high */\r
+\r
+/* Bit definition for Ethernet PTP Target Time Low Register */\r
+#define ETH_PTPTTLR_TTSL ((u32)0xFFFFFFFF) /* Target time stamp low */\r
+\r
+/******************************************************************************/\r
+/* Ethernet DMA Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet DMA Bus Mode Register */\r
+#define ETH_DMABMR_AAB ((u32)0x02000000) /* Address-Aligned beats */\r
+#define ETH_DMABMR_FPM ((u32)0x01000000) /* 4xPBL mode */\r
+#define ETH_DMABMR_USP ((u32)0x00800000) /* Use separate PBL */\r
+#define ETH_DMABMR_RDP ((u32)0x007E0000) /* RxDMA PBL */\r
+ /* Values to be confirmed: maybe they are inversed */\r
+ #define ETH_DMABMR_RDP_1Beat ((u32)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+ #define ETH_DMABMR_RDP_2Beat ((u32)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+ #define ETH_DMABMR_RDP_4Beat ((u32)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+ #define ETH_DMABMR_RDP_8Beat ((u32)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+ #define ETH_DMABMR_RDP_16Beat ((u32)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+ #define ETH_DMABMR_RDP_32Beat ((u32)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+ #define ETH_DMABMR_RDP_4xPBL_4Beat ((u32)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+ #define ETH_DMABMR_RDP_4xPBL_8Beat ((u32)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+ #define ETH_DMABMR_RDP_4xPBL_16Beat ((u32)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+ #define ETH_DMABMR_RDP_4xPBL_32Beat ((u32)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+ #define ETH_DMABMR_RDP_4xPBL_64Beat ((u32)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+ #define ETH_DMABMR_RDP_4xPBL_128Beat ((u32)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */\r
+#define ETH_DMABMR_FB ((u32)0x00010000) /* Fixed Burst */\r
+#define ETH_DMABMR_RTPR ((u32)0x0000C000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_1_1 ((u32)0x00000000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_2_1 ((u32)0x00004000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_3_1 ((u32)0x00008000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_4_1 ((u32)0x0000C000) /* Rx Tx priority ratio */\r
+#define ETH_DMABMR_PBL ((u32)0x00003F00) /* Programmable burst length */\r
+ /* Values to be confirmed: maybe they are inversed */\r
+ #define ETH_DMABMR_PBL_1Beat ((u32)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+ #define ETH_DMABMR_PBL_2Beat ((u32)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+ #define ETH_DMABMR_PBL_4Beat ((u32)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+ #define ETH_DMABMR_PBL_8Beat ((u32)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+ #define ETH_DMABMR_PBL_16Beat ((u32)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+ #define ETH_DMABMR_PBL_32Beat ((u32)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+ #define ETH_DMABMR_PBL_4xPBL_4Beat ((u32)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+ #define ETH_DMABMR_PBL_4xPBL_8Beat ((u32)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+ #define ETH_DMABMR_PBL_4xPBL_16Beat ((u32)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+ #define ETH_DMABMR_PBL_4xPBL_32Beat ((u32)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+ #define ETH_DMABMR_PBL_4xPBL_64Beat ((u32)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+ #define ETH_DMABMR_PBL_4xPBL_128Beat ((u32)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+#define ETH_DMABMR_DSL ((u32)0x0000007C) /* Descriptor Skip Length */\r
+#define ETH_DMABMR_DA ((u32)0x00000002) /* DMA arbitration scheme */\r
+#define ETH_DMABMR_SR ((u32)0x00000001) /* Software reset */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\r
+#define ETH_DMATPDR_TPD ((u32)0xFFFFFFFF) /* Transmit poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */\r
+#define ETH_DMARPDR_RPD ((u32)0xFFFFFFFF) /* Receive poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\r
+#define ETH_DMARDLAR_SRL ((u32)0xFFFFFFFF) /* Start of receive list */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\r
+#define ETH_DMATDLAR_STL ((u32)0xFFFFFFFF) /* Start of transmit list */\r
+\r
+/* Bit definition for Ethernet DMA Status Register */\r
+#define ETH_DMASR_TSTS ((u32)0x20000000) /* Time-stamp trigger status */\r
+#define ETH_DMASR_PMTS ((u32)0x10000000) /* PMT status */\r
+#define ETH_DMASR_MMCS ((u32)0x08000000) /* MMC status */\r
+#define ETH_DMASR_EBS ((u32)0x03800000) /* Error bits status */\r
+ /* combination with EBS[2:0] for GetFlagStatus function */\r
+ #define ETH_DMASR_EBS_DescAccess ((u32)0x02000000) /* Error bits 0-data buffer, 1-desc. access */\r
+ #define ETH_DMASR_EBS_ReadTransf ((u32)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */\r
+ #define ETH_DMASR_EBS_DataTransfTx ((u32)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMASR_TPS ((u32)0x00700000) /* Transmit process state */\r
+ #define ETH_DMASR_TPS_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Tx Command issued */\r
+ #define ETH_DMASR_TPS_Fetching ((u32)0x00100000) /* Running - fetching the Tx descriptor */\r
+ #define ETH_DMASR_TPS_Waiting ((u32)0x00200000) /* Running - waiting for status */\r
+ #define ETH_DMASR_TPS_Reading ((u32)0x00300000) /* Running - reading the data from host memory */\r
+ #define ETH_DMASR_TPS_Suspended ((u32)0x00600000) /* Suspended - Tx Descriptor unavailabe */\r
+ #define ETH_DMASR_TPS_Closing ((u32)0x00700000) /* Running - closing Rx descriptor */\r
+#define ETH_DMASR_RPS ((u32)0x000E0000) /* Receive process state */\r
+ #define ETH_DMASR_RPS_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Rx Command issued */\r
+ #define ETH_DMASR_RPS_Fetching ((u32)0x00020000) /* Running - fetching the Rx descriptor */\r
+ #define ETH_DMASR_RPS_Waiting ((u32)0x00060000) /* Running - waiting for packet */\r
+ #define ETH_DMASR_RPS_Suspended ((u32)0x00080000) /* Suspended - Rx Descriptor unavailable */\r
+ #define ETH_DMASR_RPS_Closing ((u32)0x000A0000) /* Running - closing descriptor */\r
+ #define ETH_DMASR_RPS_Queuing ((u32)0x000E0000) /* Running - queuing the recieve frame into host memory */\r
+#define ETH_DMASR_NIS ((u32)0x00010000) /* Normal interrupt summary */\r
+#define ETH_DMASR_AIS ((u32)0x00008000) /* Abnormal interrupt summary */\r
+#define ETH_DMASR_ERS ((u32)0x00004000) /* Early receive status */\r
+#define ETH_DMASR_FBES ((u32)0x00002000) /* Fatal bus error status */\r
+#define ETH_DMASR_ETS ((u32)0x00000400) /* Early transmit status */\r
+#define ETH_DMASR_RWTS ((u32)0x00000200) /* Receive watchdog timeout status */\r
+#define ETH_DMASR_RPSS ((u32)0x00000100) /* Receive process stopped status */\r
+#define ETH_DMASR_RBUS ((u32)0x00000080) /* Receive buffer unavailable status */\r
+#define ETH_DMASR_RS ((u32)0x00000040) /* Receive status */\r
+#define ETH_DMASR_TUS ((u32)0x00000020) /* Transmit underflow status */\r
+#define ETH_DMASR_ROS ((u32)0x00000010) /* Receive overflow status */\r
+#define ETH_DMASR_TJTS ((u32)0x00000008) /* Transmit jabber timeout status */\r
+#define ETH_DMASR_TBUS ((u32)0x00000004) /* Transmit buffer unavailable status */\r
+#define ETH_DMASR_TPSS ((u32)0x00000002) /* Transmit process stopped status */\r
+#define ETH_DMASR_TS ((u32)0x00000001) /* Transmit status */\r
+\r
+/* Bit definition for Ethernet DMA Operation Mode Register */\r
+#define ETH_DMAOMR_DTCEFD ((u32)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */\r
+#define ETH_DMAOMR_RSF ((u32)0x02000000) /* Receive store and forward */\r
+#define ETH_DMAOMR_DFRF ((u32)0x01000000) /* Disable flushing of received frames */\r
+#define ETH_DMAOMR_TSF ((u32)0x00200000) /* Transmit store and forward */\r
+#define ETH_DMAOMR_FTF ((u32)0x00100000) /* Flush transmit FIFO */\r
+#define ETH_DMAOMR_TTC ((u32)0x0001C000) /* Transmit threshold control */\r
+ #define ETH_DMAOMR_TTC_64Bytes ((u32)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+ #define ETH_DMAOMR_TTC_128Bytes ((u32)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+ #define ETH_DMAOMR_TTC_192Bytes ((u32)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+ #define ETH_DMAOMR_TTC_256Bytes ((u32)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+ #define ETH_DMAOMR_TTC_40Bytes ((u32)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+ #define ETH_DMAOMR_TTC_32Bytes ((u32)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+ #define ETH_DMAOMR_TTC_24Bytes ((u32)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+ #define ETH_DMAOMR_TTC_16Bytes ((u32)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+#define ETH_DMAOMR_ST ((u32)0x00002000) /* Start/stop transmission command */\r
+#define ETH_DMAOMR_FEF ((u32)0x00000080) /* Forward error frames */\r
+#define ETH_DMAOMR_FUGF ((u32)0x00000040) /* Forward undersized good frames */\r
+#define ETH_DMAOMR_RTC ((u32)0x00000018) /* receive threshold control */\r
+ #define ETH_DMAOMR_RTC_64Bytes ((u32)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */\r
+ #define ETH_DMAOMR_RTC_32Bytes ((u32)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */\r
+ #define ETH_DMAOMR_RTC_96Bytes ((u32)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */\r
+ #define ETH_DMAOMR_RTC_128Bytes ((u32)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */\r
+#define ETH_DMAOMR_OSF ((u32)0x00000004) /* operate on second frame */\r
+#define ETH_DMAOMR_SR ((u32)0x00000002) /* Start/stop receive */\r
+\r
+/* Bit definition for Ethernet DMA Interrupt Enable Register */\r
+#define ETH_DMAIER_NISE ((u32)0x00010000) /* Normal interrupt summary enable */\r
+#define ETH_DMAIER_AISE ((u32)0x00008000) /* Abnormal interrupt summary enable */\r
+#define ETH_DMAIER_ERIE ((u32)0x00004000) /* Early receive interrupt enable */\r
+#define ETH_DMAIER_FBEIE ((u32)0x00002000) /* Fatal bus error interrupt enable */\r
+#define ETH_DMAIER_ETIE ((u32)0x00000400) /* Early transmit interrupt enable */\r
+#define ETH_DMAIER_RWTIE ((u32)0x00000200) /* Receive watchdog timeout interrupt enable */\r
+#define ETH_DMAIER_RPSIE ((u32)0x00000100) /* Receive process stopped interrupt enable */\r
+#define ETH_DMAIER_RBUIE ((u32)0x00000080) /* Receive buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_RIE ((u32)0x00000040) /* Receive interrupt enable */\r
+#define ETH_DMAIER_TUIE ((u32)0x00000020) /* Transmit Underflow interrupt enable */\r
+#define ETH_DMAIER_ROIE ((u32)0x00000010) /* Receive Overflow interrupt enable */\r
+#define ETH_DMAIER_TJTIE ((u32)0x00000008) /* Transmit jabber timeout interrupt enable */\r
+#define ETH_DMAIER_TBUIE ((u32)0x00000004) /* Transmit buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_TPSIE ((u32)0x00000002) /* Transmit process stopped interrupt enable */\r
+#define ETH_DMAIER_TIE ((u32)0x00000001) /* Transmit interrupt enable */\r
+\r
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\r
+#define ETH_DMAMFBOCR_OFOC ((u32)0x10000000) /* Overflow bit for FIFO overflow counter */\r
+#define ETH_DMAMFBOCR_MFA ((u32)0x0FFE0000) /* Number of frames missed by the application */\r
+#define ETH_DMAMFBOCR_OMFC ((u32)0x00010000) /* Overflow bit for missed frame counter */\r
+#define ETH_DMAMFBOCR_MFC ((u32)0x0000FFFF) /* Number of frames missed by the controller */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\r
+#define ETH_DMACHTDR_HTDAP ((u32)0xFFFFFFFF) /* Host transmit descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\r
+#define ETH_DMACHRDR_HRDAP ((u32)0xFFFFFFFF) /* Host receive descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\r
+#define ETH_DMACHTBAR_HTBAP ((u32)0xFFFFFFFF) /* Host transmit buffer address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\r
+#define ETH_DMACHRBAR_HRBAP ((u32)0xFFFFFFFF) /* Host receive buffer address pointer */\r
+\r
+/******************************************************************************/\r
+/* Macros */\r
+/******************************************************************************/\r
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
+#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
+\r
+/******************************************************************************/\r
+/* Peripheral memory map */\r
+/******************************************************************************/\r
+/* ETHERNET registers base address */\r
+#define ETH_BASE ((u32)0x40028000)\r
+#define ETH_MAC_BASE (ETH_BASE)\r
+#define ETH_MMC_BASE (ETH_BASE + 0x0100)\r
+#define ETH_PTP_BASE (ETH_BASE + 0x0700)\r
+#define ETH_DMA_BASE (ETH_BASE + 0x1000)\r
+\r
+/******************************************************************************/\r
+/* Peripheral declaration */\r
+/******************************************************************************/\r
+\r
+/*------------------------ Non Debug Mode ------------------------------------*/\r
+#ifndef ETH_DEBUG\r
+#ifdef _ETH_MAC\r
+ #define ETH_MAC ((ETH_MAC_TypeDef *) ETH_MAC_BASE)\r
+#endif /*_ETH_MAC */\r
+\r
+#ifdef _ETH_MMC\r
+ #define ETH_MMC ((ETH_MMC_TypeDef *) ETH_MMC_BASE)\r
+#endif /*_ETH_MMC */\r
+\r
+#ifdef _ETH_PTP\r
+ #define ETH_PTP ((ETH_PTP_TypeDef *) ETH_PTP_BASE)\r
+#endif /*_ETH_PTP */\r
+\r
+#ifdef _ETH_DMA\r
+ #define ETH_DMA ((ETH_DMA_TypeDef *) ETH_DMA_BASE)\r
+#endif /*_ETH_DMA */\r
+\r
+/*------------------------ Debug Mode ----------------------------------------*/\r
+#else /* ETH_DEBUG */\r
+#ifdef _ETH_MAC\r
+ EXT ETH_MAC_TypeDef *ETH_MAC;\r
+#endif /*_ETH_MAC */\r
+\r
+#ifdef _ETH_MMC\r
+ EXT ETH_MMC_TypeDef *ETH_MMC;\r
+#endif /*_ETH_MMC */\r
+\r
+#ifdef _ETH_PTP\r
+ EXT ETH_PTP_TypeDef *ETH_PTP;\r
+#endif /*_ETH_PTP */\r
+\r
+#ifdef _ETH_DMA\r
+ EXT ETH_DMA_TypeDef *ETH_DMA;\r
+#endif /*_ETH_DMA */\r
+\r
+#endif /* ETH_DEBUG */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+#endif /* __STM32FXXX_ETH_MAP_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
projects / freertos / commitdiff