#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )\r
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40960 ) )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 22800 ) )\r
#define configMAX_TASK_NAME_LEN ( 10 )\r
#define configUSE_TRACE_FACILITY 1\r
#define configUSE_16_BIT_TICKS 0\r
#define xPortPendSVHandler PendSV_Handler\r
#define xPortSysTickHandler SysTick_Handler\r
\r
+\r
+/* Demo application specific settings. */\r
+#if defined( PART_XMC4500 )\r
+ /* Hardware includes. */\r
+ #include "XMC4500.h"\r
+ #include "System_XMC4500.h"\r
+\r
+ /* Configure pin P3.9 for the LED. */\r
+ #define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 )\r
+ /* To toggle the single LED */\r
+ #define configTOGGLE_LED() ( PORT3->OMR = 0x02000200 )\r
+#elif defined( PART_XMC4400 )\r
+ /* Hardware includes. */\r
+ #include "XMC4400.h"\r
+ #include "System_XMC4200.h"\r
+\r
+ /* Configure pin P5.2 for the LED. */\r
+ #define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 )\r
+ /* To toggle the single LED */\r
+ #define configTOGGLE_LED() ( PORT5->OMR = 0x00040004 )\r
+#elif defined( PART_XMC4200 )\r
+ /* Hardware includes. */\r
+ #include "XMC4200.h"\r
+ #include "System_XMC4200.h"\r
+\r
+ /* Configure pin P2.1 for the LED. */\r
+ #define configCONFIGURE_LED() PORT2->IOCR0 = 0x00008000; PORT2->HWSEL &= ~0x0000000cUL\r
+ /* To toggle the single LED */\r
+ #define configTOGGLE_LED() ( PORT2->OMR = 0x00020002 )\r
+#else\r
+ #error Part number not specified in project options\r
+#endif\r
+\r
+\r
#endif /* FREERTOS_CONFIG_H */\r
\r
</DaveTm>
<Target>
- <TargetName>RTOSDemo</TargetName>
+ <TargetName>RTOSDemo - XMC4500</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
- <IsCurrentTarget>1</IsCurrentTarget>
+ <IsCurrentTarget>0</IsCurrentTarget>
</OPTFL>
- <CpuCode>0</CpuCode>
+ <CpuCode>255</CpuCode>
<Books>
<Book>
<Number>0</Number>
<Title>Data Sheet</Title>
- <Path>DATASHTS\Infineon\comming.pdf</Path>
+ <Path>DATASHTS\Infineon\XMC4500\xmc4500_ds.pdf</Path>
</Book>
<Book>
<Number>1</Number>
<Title>User Manual</Title>
- <Path>DATASHTS\Infineon\comming.pdf</Path>
+ <Path>DATASHTS\Infineon\XMC4500\xmc4500_um.pdf</Path>
+ </Book>
+ <Book>
+ <Number>2</Number>
+ <Title>Technical Reference Manual</Title>
+ <Path>datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF</Path>
+ </Book>
+ <Book>
+ <Number>3</Number>
+ <Title>Generic User Guide</Title>
+ <Path>datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF</Path>
</Book>
</Books>
<DllOpt>
<SimDllName>SARMCM3.DLL</SimDllName>
- <SimDllArguments>-MPU</SimDllArguments>
- <SimDlgDllName>DARMP1.DLL</SimDlgDllName>
- <SimDlgDllArguments>-pLPC1785</SimDlgDllArguments>
+ <SimDllArguments>-MPU -REMAP</SimDllArguments>
+ <SimDlgDllName>DCM.DLL</SimDlgDllName>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments>-MPU</TargetDllArguments>
- <TargetDlgDllName>TARMP1.DLL</TargetDlgDllName>
- <TargetDlgDllArguments>-pLPC1785</TargetDlgDllArguments>
+ <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOpt>
<DebugOpt>
<uSim>0</uSim>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<nTsel>1</nTsel>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
- <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(350=-1,-1,-1,-1,0)(250=-1,-1,-1,-1,0)(270=-1,-1,-1,-1,0)(314=-1,-1,-1,-1,0)(292=-1,-1,-1,-1,0)(303=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(410=-1,-1,-1,-1,0)(320=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(362=-1,-1,-1,-1,0)(363=-1,-1,-1,-1,0)(364=-1,-1,-1,-1,0)(365=-1,-1,-1,-1,0)(366=-1,-1,-1,-1,0)(367=-1,-1,-1,-1,0)(332=-1,-1,-1,-1,0)(333=-1,-1,-1,-1,0)(334=-1,-1,-1,-1,0)(335=-1,-1,-1,-1,0)(336=-1,-1,-1,-1,0)(337=-1,-1,-1,-1,0)(345=-1,-1,-1,-1,0)(346=-1,-1,-1,-1,0)(390=-1,-1,-1,-1,0)(381=-1,-1,-1,-1,0)(382=-1,-1,-1,-1,0)(383=-1,-1,-1,-1,0)(384=-1,-1,-1,-1,0)(385=-1,-1,-1,-1,0)(197=-1,-1,-1,-1,0)(198=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(192=-1,-1,-1,-1,0)(261=-1,-1,-1,-1,0)(262=-1,-1,-1,-1,0)(263=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(141=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(400=-1,-1,-1,-1,0)(370=-1,-1,-1,-1,0)(280=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)</Name>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=120,149,354,683,0)(1012=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
- <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+ <Name>(105=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
- <Name>-UM1129BUE -O142 -S9 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(001DB083) -L01(8) -TO16 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN2 -FF0XMC4500 -FS0C000000 -FL0100000 -FF1XMC4500c -FS18000000 -FL1100000</Name>
+ <Name>-UM0356BUE -O751 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO16 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN2 -FC800 -FD20000000 -FF0XMC4500_1024 -FF1XMC4500c_1024 -FL0100000 -FL1100000 -FS0C000000 -FS18000000</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
- <Breakpoint>
- <Bp>
+ <Breakpoint/>
+ <WatchWindow1>
+ <Ww>
+ <count>0</count>
+ <WinNumber>1</WinNumber>
+ <ItemText>xTickCount</ItemText>
+ </Ww>
+ </WatchWindow1>
+ <MemoryWindow1>
+ <Mm>
+ <WinNumber>1</WinNumber>
+ <SubType>5</SubType>
+ <ItemText>0x0C000000</ItemText>
+ </Mm>
+ </MemoryWindow1>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>RTOSDemo - XMC4400</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <Books>
+ <Book>
<Number>0</Number>
- <Type>0</Type>
- <LineNumber>244</LineNumber>
- <EnabledFlag>1</EnabledFlag>
- <Address>201327524</Address>
- <ByteObject>0</ByteObject>
- <ManyObjects>0</ManyObjects>
- <SizeOfObject>0</SizeOfObject>
- <BreakByAccess>0</BreakByAccess>
- <BreakIfRCount>1</BreakIfRCount>
- <Filename></Filename>
- <ExecCommand></ExecCommand>
- <Expression>\\RTOSDemo\RegTest.c\244</Expression>
- </Bp>
- <Bp>
+ <Title>Data Sheet</Title>
+ <Path>DATASHTS\Infineon\XMC4400\xmc4400_ds.pdf</Path>
+ </Book>
+ <Book>
<Number>1</Number>
- <Type>0</Type>
- <LineNumber>61</LineNumber>
- <EnabledFlag>1</EnabledFlag>
- <Address>201327124</Address>
- <ByteObject>0</ByteObject>
- <ManyObjects>0</ManyObjects>
- <SizeOfObject>0</SizeOfObject>
- <BreakByAccess>0</BreakByAccess>
- <BreakIfRCount>1</BreakIfRCount>
- <Filename></Filename>
- <ExecCommand></ExecCommand>
- <Expression>\\RTOSDemo\RegTest.c\61</Expression>
- </Bp>
- </Breakpoint>
+ <Title>User Manual</Title>
+ <Path>DATASHTS\Infineon\XMC4400\xmc4400_ds.pdf</Path>
+ </Book>
+ <Book>
+ <Number>2</Number>
+ <Title>Technical Reference Manual</Title>
+ <Path>datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF</Path>
+ </Book>
+ <Book>
+ <Number>3</Number>
+ <Title>Generic User Guide</Title>
+ <Path>datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF</Path>
+ </Book>
+ </Books>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments>-MPU -REMAP</SimDllArguments>
+ <SimDlgDllName>DCM.DLL</SimDlgDllName>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments>-MPU</TargetDllArguments>
+ <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>7</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>Segger\JL2CM3.dll</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>JL2CM3</Key>
+ <Name>-U591000334 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8009 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC4200_4100_256 -FS0C000000 -FL040000</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(350=-1,-1,-1,-1,0)(250=-1,-1,-1,-1,0)(270=-1,-1,-1,-1,0)(314=-1,-1,-1,-1,0)(292=-1,-1,-1,-1,0)(303=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(410=-1,-1,-1,-1,0)(320=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(362=-1,-1,-1,-1,0)(363=-1,-1,-1,-1,0)(364=-1,-1,-1,-1,0)(365=-1,-1,-1,-1,0)(366=-1,-1,-1,-1,0)(367=-1,-1,-1,-1,0)(332=-1,-1,-1,-1,0)(333=-1,-1,-1,-1,0)(334=-1,-1,-1,-1,0)(335=-1,-1,-1,-1,0)(336=-1,-1,-1,-1,0)(337=-1,-1,-1,-1,0)(345=-1,-1,-1,-1,0)(346=-1,-1,-1,-1,0)(390=-1,-1,-1,-1,0)(381=-1,-1,-1,-1,0)(382=-1,-1,-1,-1,0)(383=-1,-1,-1,-1,0)(384=-1,-1,-1,-1,0)(385=-1,-1,-1,-1,0)(197=-1,-1,-1,-1,0)(198=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(192=-1,-1,-1,-1,0)(199=-1,-1,-1,-1,0)(261=-1,-1,-1,-1,0)(262=-1,-1,-1,-1,0)(263=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(141=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(400=-1,-1,-1,-1,0)(370=-1,-1,-1,-1,0)(280=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGTARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGUARM</Key>
+ <Name>/</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ULP2CM3</Key>
+ <Name>-UP1048084 -O143 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(001DB083) -L01(8) -TO18 -TC10000000 -TP28 -TDX0 -TDD0 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN2 -FF0XMC4500 -FS0C000000 -FL0100000 -FF1XMC4500c -FS18000000 -FL1100000</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name> -FN2 -FC800 -FD20000000 -FF0XMC4400_512 -FF1XMC4400c_512 -FL080000 -FL180000 -FS0C000000 -FS18000000</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
<MemoryWindow1>
<Mm>
<WinNumber>1</WinNumber>
<ItemText>0x0C000000</ItemText>
</Mm>
</MemoryWindow1>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <SystemViewers>
+ <Entry>
+ <Name>System Viewer\PORT2</Name>
+ <WinId>35905</WinId>
+ </Entry>
+ </SystemViewers>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>RTOSDemo - XMC4200</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <Books>
+ <Book>
+ <Number>0</Number>
+ <Title>Data Sheet</Title>
+ <Path>DATASHTS\Infineon\XMC4200-4100\XMC4200-4100_ds.pdf</Path>
+ </Book>
+ <Book>
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- <MDIGroup>
- <Size>100</Size>
- <ActiveTab>2</ActiveTab>
- <Documents>
- <Doc>
- <Name>.\main_blinky.c</Name>
- <ColumnNumber>0</ColumnNumber>
- <TopLine>53</TopLine>
- <CurrentLine>53</CurrentLine>
- </Doc>
- <Doc>
- <Name>.\main_full.c</Name>
- <ColumnNumber>0</ColumnNumber>
- <TopLine>50</TopLine>
- <CurrentLine>54</CurrentLine>
- </Doc>
- <Doc>
- <Name>.\main.c</Name>
- <ColumnNumber>44</ColumnNumber>
- <TopLine>64</TopLine>
- <CurrentLine>90</CurrentLine>
- </Doc>
- </Documents>
- </MDIGroup>
- </MDIGroups>
-
</ProjectOpt>
<Targets>
<Target>
- <TargetName>RTOSDemo</TargetName>
+ <TargetName>RTOSDemo - XMC4500</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<TargetCommonOption>
- <Device>XMC4500</Device>
+ <Device>XMC4500-1024</Device>
<Vendor>Infineon</Vendor>
- <Cpu>IRAM(0x10000000-0x1000FFFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x0C000000-0x0C0FFFFF) IROM2(0x08000000-0x080FFFFF) CLOCK(12000000) CPUTYPE("Cortex-M4")</Cpu>
+ <Cpu>IRAM(0x20000000-0x2000FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x0C000000-0x0C0FFFFF) IROM2(0x08000000-0x080FFFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile>"STARTUP\Infineon\XMC4500\startup_XMC4500.s" ("Infineon XMC4500 Startup Code")</StartupFile>
- <FlashDriverDll>UL2CM3(-FD10000000 -FC800 -FN2 -FF0XMC4500 -FS0C000000 -FL0100000 -FF1XMC4500c -FS18000000 -FL1100000)</FlashDriverDll>
- <DeviceId>0</DeviceId>
- <RegisterFile>XMC4500.H</RegisterFile>
+ <FlashDriverDll>UL2CM3(-FD20000000 -FC800 -FN2 -FF0XMC4500_1024 -FS0C000000 -FL0100000 -FF1XMC4500c_1024 -FS18000000 -FL1100000)</FlashDriverDll>
+ <DeviceId>6264</DeviceId>
+ <RegisterFile>XMC4500.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
- <SimDllArguments>-MPU</SimDllArguments>
- <SimDlgDll>DARMP1.DLL</SimDlgDll>
- <SimDlgDllArguments>-pLPC1785</SimDlgDllArguments>
+ <SimDllArguments>-MPU -REMAP</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments>-MPU</TargetDllArguments>
- <TargetDlgDll>TARMP1.DLL</TargetDlgDll>
- <TargetDlgDllArguments>-pLPC1785</TargetDlgDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>1</TargetSelection>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
+ <bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
- <Flash3>"" ()</Flash3>
+ <Flash3></Flash3>
<Flash4></Flash4>
</Utilities>
<TargetArmAds>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
- <RvdsVP>0</RvdsVP>
+ <RvdsVP>2</RvdsVP>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>1</hadIROM2>
<StupSel>8</StupSel>
</Ocm6>
<IRAM>
<Type>0</Type>
- <StartAddress>0x10000000</StartAddress>
+ <StartAddress>0x20000000</StartAddress>
<Size>0x10000</Size>
</IRAM>
<IROM>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
- <StartAddress>0x10000000</StartAddress>
+ <StartAddress>0x20000000</StartAddress>
<Size>0x10000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
- <StartAddress>0x20000000</StartAddress>
+ <StartAddress>0x10000000</StartAddress>
<Size>0x10000</Size>
</OCR_RVCT10>
</OnChipMemories>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
<VariousControls>
<MiscControls>--cpu Cortex-M4.fp --no_allow_fpreg_for_nonfpdata</MiscControls>
<Define>rvkdm PART_XMC4500</Define>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<FileType>1</FileType>
<FilePath>.\System_XMC4500.c</FilePath>
</File>
+ <File>
+ <FileName>startup_XMC4200.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_XMC4200.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Aads>
+ <interw>2</interw>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <thumb>2</thumb>
+ <SplitLS>2</SplitLS>
+ <SwStkChk>2</SwStkChk>
+ <NoWarn>2</NoWarn>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>system_XMC4200.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\system_XMC4200.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>system_XMC4400.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\system_XMC4400.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>startup_XMC4400.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_XMC4400.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Aads>
+ <interw>2</interw>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <thumb>2</thumb>
+ <SplitLS>2</SplitLS>
+ <SwStkChk>2</SwStkChk>
+ <NoWarn>2</NoWarn>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ </FileArmAds>
+ </FileOption>
+ </File>
</Files>
</Group>
<Group>
<FilePath>..\..\Source\tasks.c</FilePath>
</File>
<File>
- <FileName>heap_2.c</FileName>
+ <FileName>port.c</FileName>
<FileType>1</FileType>
- <FilePath>..\..\Source\portable\MemMang\heap_2.c</FilePath>
+ <FilePath>..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath>
</File>
<File>
- <FileName>port.c</FileName>
+ <FileName>heap_4.c</FileName>
<FileType>1</FileType>
- <FilePath>..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath>
+ <FilePath>..\..\Source\portable\MemMang\heap_4.c</FilePath>
</File>
</Files>
</Group>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\sp_flop.c</FilePath>
</File>
- <File>
- <FileName>BlockQ.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\Common\Minimal\BlockQ.c</FilePath>
- </File>
<File>
<FileName>blocktim.c</FileName>
<FileType>1</FileType>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\countsem.c</FilePath>
</File>
- <File>
- <FileName>death.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\Common\Minimal\death.c</FilePath>
- </File>
<File>
<FileName>dynamic.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\GenQTest.c</FilePath>
</File>
<File>
- <FileName>integer.c</FileName>
+ <FileName>recmutex.c</FileName>
<FileType>1</FileType>
- <FilePath>..\Common\Minimal\integer.c</FilePath>
+ <FilePath>..\Common\Minimal\recmutex.c</FilePath>
</File>
- <File>
- <FileName>PollQ.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\Common\Minimal\PollQ.c</FilePath>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>RTOSDemo - XMC4400</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>XMC4400-512</Device>
+ <Vendor>Infineon</Vendor>
+ <Cpu>IRAM(0x20000000-0x20007FFF) IRAM2(0x1FFFC000-0x1FFFFFFF) IROM(0x0C000000-0x0C07FFFF) IROM2(0x08000000-0x0807FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile>"STARTUP\Infineon\XMC4400\startup_XMC4400.s" ("Infineon XMC4400 Startup Code")</StartupFile>
+ <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN2 -FF0XMC4400_512 -FS0C000000 -FL080000 -FF1XMC4400c_512 -FS18000000 -FL180000)</FlashDriverDll>
+ <DeviceId>6644</DeviceId>
+ <RegisterFile>XMC4400.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>SFD\Infineon\XMC4400\xmc4400.SFR</SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath>Infineon\XMC4400\</RegisterFilePath>
+ <DBRegisterFilePath>Infineon\XMC4400\</DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\Flash\</OutputDirectory>
+ <OutputName>RTOSDemo</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments>-MPU -REMAP</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments>-MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>7</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>Segger\JL2CM3.dll</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4096</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M4"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>1</hadIRAM2>
+ <hadIROM2>1</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>0</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x8000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0xc000000</StartAddress>
+ <Size>0x80000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0xc000000</StartAddress>
+ <Size>0x80000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x8000000</StartAddress>
+ <Size>0x80000</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x8000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x1fffc000</StartAddress>
+ <Size>0x4000</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <VariousControls>
+ <MiscControls>--cpu Cortex-M4.fp --no_allow_fpreg_for_nonfpdata</MiscControls>
+ <Define>rvkdm PART_XMC4400</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\CORTEX_M4F_Infineon_XMC4500_Keil;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F;..\Common\include</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x0C000000</TextAddressRange>
+ <DataAddressRange>0x10000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc>--entry=Reset_Handler</Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_XMC4500.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_XMC4500.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Aads>
+ <interw>2</interw>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <thumb>2</thumb>
+ <SplitLS>2</SplitLS>
+ <SwStkChk>2</SwStkChk>
+ <NoWarn>2</NoWarn>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>System_XMC4500.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\System_XMC4500.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>startup_XMC4200.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_XMC4200.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Aads>
+ <interw>2</interw>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <thumb>2</thumb>
+ <SplitLS>2</SplitLS>
+ <SwStkChk>2</SwStkChk>
+ <NoWarn>2</NoWarn>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>system_XMC4200.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\system_XMC4200.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>system_XMC4400.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\system_XMC4400.c</FilePath>
+ </File>
+ <File>
+ <FileName>startup_XMC4400.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_XMC4400.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Demo_Source</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ <File>
+ <FileName>FreeRTOSConfig.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\FreeRTOSConfig.h</FilePath>
+ </File>
+ <File>
+ <FileName>RegTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\RegTest.c</FilePath>
+ </File>
+ <File>
+ <FileName>main_full.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main_full.c</FilePath>
+ </File>
+ <File>
+ <FileName>main_blinky.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main_blinky.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>FreeRTOS_Source</GroupName>
+ <Files>
+ <File>
+ <FileName>timers.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\timers.c</FilePath>
+ </File>
+ <File>
+ <FileName>list.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\list.c</FilePath>
+ </File>
+ <File>
+ <FileName>queue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\queue.c</FilePath>
+ </File>
+ <File>
+ <FileName>tasks.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\tasks.c</FilePath>
+ </File>
+ <File>
+ <FileName>port.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath>
+ </File>
+ <File>
+ <FileName>heap_4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\MemMang\heap_4.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Common_Demo_Source</GroupName>
+ <Files>
+ <File>
+ <FileName>semtest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\semtest.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_flop.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\sp_flop.c</FilePath>
+ </File>
+ <File>
+ <FileName>blocktim.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\blocktim.c</FilePath>
+ </File>
+ <File>
+ <FileName>countsem.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\countsem.c</FilePath>
+ </File>
+ <File>
+ <FileName>dynamic.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\dynamic.c</FilePath>
+ </File>
+ <File>
+ <FileName>GenQTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\GenQTest.c</FilePath>
+ </File>
+ <File>
+ <FileName>recmutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\recmutex.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>RTOSDemo - XMC4200</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>XMC4200-256</Device>
+ <Vendor>Infineon</Vendor>
+ <Cpu>IRAM(0x20000000-0x20005FFF) IRAM2(0x1FFFE000-0x1FFFFFFF) IROM(0x0C000000-0x0C03FFFF) IROM2(0x08000000-0x0803FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile>"STARTUP\Infineon\XMC4200-4100\startup_XMC4200.s" ("Infineon XMC4200/4100 Startup Code")</StartupFile>
+ <FlashDriverDll>UL2CM3(-FD20000000 -FC800 -FN2 -FF0XMC4200_4100_256 -FS0C000000 -FL040000 -FF1XMC4200_4100c_256 -FS18000000 -FL140000)</FlashDriverDll>
+ <DeviceId>6705</DeviceId>
+ <RegisterFile>XMC4200.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>SFD\Infineon\XMC4200-4100\xmc4200.SFR</SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath>Infineon\XMC4200-4100\</RegisterFilePath>
+ <DBRegisterFilePath>Infineon\XMC4200-4100\</DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\Flash\</OutputDirectory>
+ <OutputName>RTOSDemo</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments>-MPU -REMAP</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments>-MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>7</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>Segger\JL2CM3.dll</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4096</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M4"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>1</hadIRAM2>
+ <hadIROM2>1</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>0</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x6000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0xc000000</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0xc000000</StartAddress>
+ <Size>0x40000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x8000000</StartAddress>
+ <Size>0x40000</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x6000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x1fffe000</StartAddress>
+ <Size>0x2000</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <VariousControls>
+ <MiscControls>--cpu Cortex-M4.fp --no_allow_fpreg_for_nonfpdata</MiscControls>
+ <Define>rvkdm PART_XMC4200</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\CORTEX_M4F_Infineon_XMC4500_Keil;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F;..\Common\include</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x0C000000</TextAddressRange>
+ <DataAddressRange>0x10000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc>--entry=Reset_Handler</Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_XMC4500.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_XMC4500.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Aads>
+ <interw>2</interw>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <thumb>2</thumb>
+ <SplitLS>2</SplitLS>
+ <SwStkChk>2</SwStkChk>
+ <NoWarn>2</NoWarn>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>System_XMC4500.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\System_XMC4500.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>startup_XMC4200.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_XMC4200.s</FilePath>
+ </File>
+ <File>
+ <FileName>system_XMC4200.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\system_XMC4200.c</FilePath>
+ </File>
+ <File>
+ <FileName>system_XMC4400.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\system_XMC4400.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>startup_XMC4400.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_XMC4400.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Aads>
+ <interw>2</interw>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <thumb>2</thumb>
+ <SplitLS>2</SplitLS>
+ <SwStkChk>2</SwStkChk>
+ <NoWarn>2</NoWarn>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Demo_Source</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ <File>
+ <FileName>FreeRTOSConfig.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\FreeRTOSConfig.h</FilePath>
+ </File>
+ <File>
+ <FileName>RegTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\RegTest.c</FilePath>
+ </File>
+ <File>
+ <FileName>main_full.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main_full.c</FilePath>
+ </File>
+ <File>
+ <FileName>main_blinky.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main_blinky.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>FreeRTOS_Source</GroupName>
+ <Files>
+ <File>
+ <FileName>timers.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\timers.c</FilePath>
+ </File>
+ <File>
+ <FileName>list.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\list.c</FilePath>
+ </File>
+ <File>
+ <FileName>queue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\queue.c</FilePath>
+ </File>
+ <File>
+ <FileName>tasks.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\tasks.c</FilePath>
+ </File>
+ <File>
+ <FileName>port.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath>
+ </File>
+ <File>
+ <FileName>heap_4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\MemMang\heap_4.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Common_Demo_Source</GroupName>
+ <Files>
+ <File>
+ <FileName>semtest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\semtest.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_flop.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\sp_flop.c</FilePath>
+ </File>
+ <File>
+ <FileName>blocktim.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\blocktim.c</FilePath>
+ </File>
+ <File>
+ <FileName>countsem.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\countsem.c</FilePath>
+ </File>
+ <File>
+ <FileName>dynamic.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\dynamic.c</FilePath>
+ </File>
+ <File>
+ <FileName>GenQTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\GenQTest.c</FilePath>
</File>
<File>
<FileName>recmutex.c</FileName>
-/******************************************************************************\r
+/**************************************************************************//**\r
* @file system_XMC4500.c\r
- * @brief Device specific initialization for the XMC4500-Series according to CMSIS\r
- * @version V2.2\r
- * @date 20. January 2012\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
+ * for the Infineon XMC4500 Device Series\r
+ * @version V3.0.1 Alpha\r
+ * @date 17. September 2012\r
*\r
* @note\r
- * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.\r
-\r
+ * Copyright (C) 2011 ARM Limited. All rights reserved.\r
*\r
* @par\r
- * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon\92s microcontrollers. \r
- * This file can be freely distributed within development tools that are supporting such microcontrollers. \r
-\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
*\r
* @par\r
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
*\r
- *\r
******************************************************************************/\r
\r
-#include "System_XMC4500.h"\r
+#include "system_XMC4500.h"\r
#include <XMC4500.h>\r
\r
-/*----------------------------------------------------------------------------\r
- Define clocks is located in System_XMC4500.h\r
- *----------------------------------------------------------------------------*/\r
-\r
/*----------------------------------------------------------------------------\r
Clock Variable definitions\r
*----------------------------------------------------------------------------*/\r
/*!< System Clock Frequency (Core Clock)*/\r
-uint32_t SystemCoreClock = CLOCK_OSC_HP;\r
+uint32_t SystemCoreClock;\r
+\r
+/* clock definitions, do not modify! */\r
+#define SCU_CLOCK_CRYSTAL 1\r
+#define SCU_CLOCK_BACK_UP_FACTORY 2\r
+#define SCU_CLOCK_BACK_UP_AUTOMATIC 3\r
+\r
+\r
+#define HIB_CLOCK_FOSI 1\r
+#define HIB_CLOCK_OSCULP 2\r
+\r
+\r
\r
-/*----------------------------------------------------------------------------\r
- Keil pragma to prevent warnings\r
- *----------------------------------------------------------------------------*/\r
-#if defined(__ARMCC_VERSION)\r
-#pragma diag_suppress 177\r
-#endif\r
\r
/*\r
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
//\r
// <e> Main Clock Configuration\r
// <o1.0..1> CPU clock divider\r
-// <0=> fCPU = fSYS \r
+// <0=> fCPU = fSYS\r
// <1=> fCPU = fSYS / 2\r
// <o2.0..1> Peripheral Bus clock divider\r
// <0=> fPB = fCPU\r
// <1=> fCCU = fCPU / 2\r
//\r
// </e>\r
-// \r
+//\r
*/\r
\r
#define SCU_CLOCK_SETUP 1\r
#define SCU_CPUCLKCR_DIV 0x00000000\r
#define SCU_PBCLKCR_DIV 0x00000000\r
#define SCU_CCUCLKCR_DIV 0x00000000\r
-\r
-\r
+/* not avalible in config wizzard*/\r
+/*\r
+* mandatory clock parameters **************************************************\r
+*\r
+* source for clock generation\r
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)\r
+*\r
+**************************************************************************************/\r
+// Selection of imput lock for PLL\r
+/*************************************************************************************/\r
+#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC\r
+\r
+/*************************************************************************************/\r
+// Standby clock selection for Backup clock source trimming\r
+/*************************************************************************************/\r
+#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP\r
+//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI\r
+\r
+/*************************************************************************************/\r
+// Global clock parameters\r
+/*************************************************************************************/\r
+#define CLOCK_FSYS 120000000\r
+#define CLOCK_CRYSTAL_FREQUENCY 12000000\r
+#define CLOCK_BACK_UP 24000000\r
+\r
+/*************************************************************************************/\r
+/* OSC_HP setup parameters */\r
+/*************************************************************************************/\r
+#define SCU_OSC_HP_MODE 0xF0\r
+#define SCU_OSCHPWDGDIV 2\r
+\r
+/*************************************************************************************/\r
+/* MAIN PLL setup parameters */\r
+/*************************************************************************************/\r
+//Divider settings for external crystal @ 12 MHz\r
+/*************************************************************************************/\r
+#define SCU_PLL_K1DIV 1\r
+#define SCU_PLL_K2DIV 3\r
+#define SCU_PLL_PDIV 1\r
+#define SCU_PLL_NDIV 79\r
+\r
+/*************************************************************************************/\r
+//Divider settings for use of backup clock source trimmed\r
+/*************************************************************************************/\r
+//#define SCU_PLL_K1DIV 1\r
+//#define SCU_PLL_K2DIV 3\r
+//#define SCU_PLL_PDIV 3\r
+//#define SCU_PLL_NDIV 79\r
+/*************************************************************************************/\r
\r
/*--------------------- USB CLOCK Configuration ---------------------------\r
//\r
// <e> USB Clock Configuration\r
//\r
// </e>\r
-// \r
+//\r
*/\r
\r
#define SCU_USB_CLOCK_SETUP 0\r
+/* not avalible in config wizzard*/\r
+#define SCU_USBPLL_PDIV 0\r
+#define SCU_USBPLL_NDIV 31\r
+#define SCU_USBDIV 3\r
+\r
+/*--------------------- Flash Wait State Configuration -------------------------------\r
+//\r
+// <e> Flash Wait State Configuration\r
+// <o1.0..3> Flash Wait State\r
+// <0=> 3 WS\r
+// <1=> 4 WS\r
+// <2=> 5 WS\r
+// <3=> 6 WS\r
+// </e>\r
+//\r
+*/\r
+\r
+#define PMU_FLASH 1\r
+#define PMU_FLASH_WS 0x00000000\r
\r
\r
/*--------------------- CLOCKOUT Configuration -------------------------------\r
// <e> Clock OUT Configuration\r
// <o1.0..1> Clockout Source Selection\r
// <0=> System Clock\r
-// <2=> USB Clock\r
+// <2=> Divided value of USB PLL output\r
// <3=> Divided value of PLL Clock\r
-// <o2.0..1> Clockout Pin Selection\r
+// <o2.0..4> Clockout divider <1-10><#-1>\r
+// <o3.0..1> Clockout Pin Selection\r
// <0=> P1.15\r
// <1=> P0.8\r
-// \r
+//\r
//\r
// </e>\r
-// \r
+//\r
*/\r
\r
-#define SCU_CLOCKOUT_SETUP 0 // recommended to keep disabled\r
-#define SCU_CLOCKOUT_SOURCE 0x00000000\r
-#define SCU_CLOCKOUT_PIN 0x00000000\r
+#define SCU_CLOCKOUT_SETUP 0\r
+#define SCU_CLOCKOUT_SOURCE 0x00000003\r
+#define SCU_CLOCKOUT_DIV 0x00000009\r
+#define SCU_CLOCKOUT_PIN 0x00000001\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+#if SCU_CLOCK_SETUP\r
+uint32_t SystemCoreClock = CLOCK_FSYS;\r
+#else\r
+uint32_t SystemCoreClock = CLOCK_BACK_UP;\r
+#endif\r
\r
/*----------------------------------------------------------------------------\r
static functions declarations\r
#endif\r
\r
#if (SCU_USB_CLOCK_SETUP == 1)\r
-static void USBClockSetup(void);\r
+static int USBClockSetup(void);\r
#endif\r
\r
+\r
/**\r
* @brief Setup the microcontroller system.\r
- * Initialize the PLL and update the \r
+ * Initialize the PLL and update the\r
* SystemCoreClock variable.\r
* @param None\r
* @retval None\r
*/\r
void SystemInit(void)\r
{\r
-/* Setup the WDT */\r
-#if (WDT_SETUP == 1)\r
-WDT->CTR &= ~WDTENB_nVal; \r
-#endif\r
+int temp;\r
\r
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */\r
(3UL << 11*2) ); /* set CP11 Full Access */\r
#endif\r
\r
-/* Disable branch prediction - PCON.PBS = 1 */\r
-PREF->PCON |= (PREF_PCON_PBS_Msk);\r
-\r
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */\r
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);\r
\r
+/* Setup the WDT */\r
+#if WDT_SETUP\r
+\r
+WDT->CTR &= ~WDTENB_nVal;\r
+\r
+#endif\r
+\r
+/* Setup the Flash Wait State */\r
+#if PMU_FLASH\r
+temp = FLASH0->FCON;\r
+temp &= ~FLASH_FCON_WSPFLASH_Msk;\r
+temp |= PMU_FLASH_WS+3;\r
+FLASH0->FCON = temp;\r
+#endif\r
+\r
+\r
/* Setup the clockout */\r
-/* README README README README README README README README README README */\r
-/*\r
- * Please use the CLOCKOUT feature with diligence. Use this only if you know\r
- * what you are doing.\r
- *\r
- * You must be aware that the settings below can potentially be in conflict\r
- * with DAVE code generation engine preferences.\r
- *\r
- * Even worse, the setting below configures the ports as output ports while in\r
- * reality, the board on which this chip is mounted may have a source driving\r
- * the ports.\r
- *\r
- * So use this feature only when you are absolutely sure that the port must \r
- * indeed be configured as an output AND you are NOT linking this startup code\r
- * with code that was generated by DAVE code engine.\r
- */\r
-#if (SCU_CLOCKOUT_SETUP == 1)\r
+#if SCU_CLOCKOUT_SETUP\r
+\r
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;\r
+/*set PLL div for clkout */\r
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;\r
\r
if (SCU_CLOCKOUT_PIN) {\r
- PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */\r
- PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
- }\r
-else PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */\r
+ PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */\r
+ PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
+ //PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */\r
+ }\r
+else {\r
+ PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */\r
+ //PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */\r
+ }\r
+\r
#endif\r
\r
-/* Setup the System clock */ \r
-#if (SCU_CLOCK_SETUP == 1)\r
+\r
+/* Setup the System clock */\r
+#if SCU_CLOCK_SETUP\r
SystemClockSetup();\r
#endif\r
\r
-/* Setup the USB PL */ \r
-#if (SCU_USB_CLOCK_SETUP == 1)\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
+/* Setup the USB PL */\r
+#if SCU_USB_CLOCK_SETUP\r
USBClockSetup();\r
#endif\r
\r
+\r
+\r
}\r
\r
\r
/**\r
* @brief Update SystemCoreClock according to Clock Register Values\r
- * @note - \r
+ * @note -\r
* @param None\r
* @retval None\r
*/\r
void SystemCoreClockUpdate(void)\r
{\r
+unsigned int PDIV;\r
+unsigned int NDIV;\r
+unsigned int K2DIV;\r
+unsigned int long VCO;\r
+\r
\r
/*----------------------------------------------------------------------------\r
Clock Variable definitions\r
*----------------------------------------------------------------------------*/\r
-SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/\r
+if (SCU_CLK->SYSCLKCR == 0x00010000)\r
+{\r
+ if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){\r
+ /* check if PLL is locked */\r
+ /* read back divider settings */\r
+ PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;\r
+ NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;\r
+ K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;\r
+\r
+ if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){\r
+ /* the selected clock is the Backup clock fofi */\r
+ VCO = (CLOCK_BACK_UP/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+\r
+ }\r
+ else\r
+ {\r
+ /* the selected clock is the PLL external oscillator */\r
+ VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+ }\r
+\r
+\r
+ }\r
+}\r
+else\r
+{\r
+SystemCoreClock = CLOCK_BACK_UP;\r
+}\r
+\r
\r
}\r
\r
\r
/**\r
* @brief -\r
- * @note - \r
+ * @note -\r
* @param None\r
* @retval None\r
*/\r
#if (SCU_CLOCK_SETUP == 1)\r
static int SystemClockSetup(void)\r
{\r
-/* enable PLL first */\r
- SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | \r
- SCU_PLL_PLLCON0_PLLPWD_Msk);\r
-\r
-/* Enable OSC_HP */\r
- if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
- {\r
- /* Enable the OSC_HP*/\r
- SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); \r
- /* Setup OSC WDG devider */\r
- SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16); \r
- /* Select external OSC as PLL input */\r
- SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
- /* Restart OSC Watchdog */\r
- SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
-\r
- do \r
- {\r
- ; /* here a timeout need to be added */\r
- }while(!( (SCU_PLL->PLLSTAT) & \r
- (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |\r
- SCU_PLL_PLLSTAT_PLLSP_Msk)\r
- )\r
- ); \r
-\r
- }\r
-\r
-/* Setup Main PLL */\r
- /* Select FOFI as system clock */\r
- if(SCU_CLK->SYSCLKCR != 0X000000)\r
- SCU_CLK->SYSCLKCR = 0x00000000; /*Select FOFI*/\r
-\r
- /* Go to bypass the Main PLL */\r
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+int temp;\r
+unsigned int long VCO;\r
+int stepping_K2DIV;\r
\r
- /* disconnect OSC_HP to PLL */\r
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
+/* this weak function enables DAVE3 clock App usage */\r
+if(AllowPLLInitByStartup()){\r
\r
- /* Setup devider settings for main PLL */\r
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | \r
- (PLL_K2DIV_STEP_1<<16) | (PLL_PDIV<<24));\r
-\r
- /* we may have to set OSCDISCDIS */\r
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+/* enable PLL first */\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
\r
- /* connect OSC_HP to PLL */\r
- SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
+}\r
\r
- /* restart PLL Lock detection */\r
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
+/* Enable OSC_HP if not already on*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use external crystal for PLL clock input */\r
+ /********************************************************************************************************************/\r
\r
- /* wait for PLL Lock */\r
- while (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk));\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
+ /* setup OSC WDG devider */\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);\r
+ /* select external OSC as PLL input */\r
+ SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ /* restart OSC Watchdog */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;\r
+\r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ do\r
+ {\r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));\r
\r
- /* Go back to the Main PLL */\r
- SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
\r
- /*********************************************************\r
- here we need to setup the system clock divider\r
- *********************************************************/\r
+ }\r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use factory trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+\r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use automatic trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* check for HIB Domain enabled */\r
+ if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)\r
+ SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/\r
+\r
+ /* check for HIB Domain is not in reset state */\r
+ if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)\r
+ SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/\r
+\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+\r
+ if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fOSI as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ }\r
+ else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fULP as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ /*check OSCUL if running correct*/\r
+ if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)\r
+ {\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);\r
+\r
+ SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/\r
+ /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/\r
+ /* select OSCUL clock for RTC*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*enable OSCULP WDG Alarm Enable*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*wait now for clock is stable */\r
+ do\r
+ {\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ }\r
+ while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);\r
+\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ }\r
+ // now OSCULP is running and can be used\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+ }\r
+ }\r
\r
- SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
- SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; \r
- SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
+ /********************************************************************************************************************/\r
+ /* Setup and look the main PLL */\r
+ /********************************************************************************************************************/\r
+\r
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){\r
+ /* Systen is still running from internal clock */\r
+ /* select FOFI as system clock */\r
+ if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/\r
+\r
+\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+ stepping_K2DIV = (VCO/24000000)-1;\r
+ /* Go to bypass the Main PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ /* disconnect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ /* we may have to set OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+ /* connect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* restart PLL Lock detection */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
+ /* wait for PLL Lock */\r
+ /* setup time out loop */\r
+ /* Timeout for wait loo ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+\r
+ while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+\r
+ if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)\r
+ {\r
+ /* Go back to the Main PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ }\r
+ else return(0);\r
+\r
+\r
+ /*********************************************************\r
+ here we need to setup the system clock divider\r
+ *********************************************************/\r
+\r
+ SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
+ SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;\r
+ SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
+\r
+\r
+ /* Switch system clock to PLL */\r
+ SCU_CLK->SYSCLKCR |= 0x00010000;\r
+\r
+ /* we may have to reset OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+\r
+\r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+\r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /*********************************************************/\r
+\r
+ /*********************************************************\r
+ here the ramp up of the system clock starts FSys < 60MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 60000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+ stepping_K2DIV = (VCO/60000000)-1;\r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+\r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+\r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
\r
- /* Switch system clock to PLL */\r
- SCU_CLK->SYSCLKCR |= 0x00010000; \r
- \r
/*********************************************************\r
- here the ramp up of the system clock starts\r
- *********************************************************/\r
- /* Delay for next K2 step ~50µs */\r
- /********************************/\r
- /* Set reload register */\r
- SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
-\r
- /* Load the SysTick Counter Value */\r
- SysTick->VAL = 0; \r
-\r
- /* Enable SysTick IRQ and SysTick Timer */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_ENABLE_Msk; \r
- \r
- /* wait for ~50µs */\r
- while (SysTick->VAL >= 100); \r
-\r
- /* Stop SysTick Timer */\r
- SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; \r
- /********************************/\r
-\r
- /* Setup devider settings for main PLL */\r
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | \r
- (PLL_K2DIV_STEP_2<<16) | (PLL_PDIV<<24));\r
-\r
- /* Delay for next K2 step ~50µs */\r
- /********************************/\r
- SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
-\r
- /* Load the SysTick Counter Value */\r
- SysTick->VAL = 0;\r
-\r
- /* Enable SysTick IRQ and SysTick Timer */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;\r
- \r
- /* Wait for ~50µs */\r
- while (SysTick->VAL >= 100); \r
-\r
- /* Stop SysTick Timer */\r
- SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; \r
- /********************************/\r
-\r
- /* Setup devider settings for main PLL */\r
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | \r
- (PLL_K2DIV_STEP_3<<16) | (PLL_PDIV<<24));\r
-\r
- /* Delay for next K2 step ~50µs */\r
- /********************************/\r
- SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
-\r
- /* Load the SysTick Counter Value */\r
- SysTick->VAL = 0; \r
-\r
- /* Enable SysTick IRQ and SysTick Timer */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;\r
- \r
- /* Wait for ~50µs */\r
- while (SysTick->VAL >= 100); \r
-\r
- /* Stop SysTick Timer */\r
- SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; \r
- /********************************/\r
-\r
- /* Setup devider settings for main PLL */\r
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV<<16) | \r
- (PLL_PDIV<<24));\r
-\r
- /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
- SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | \r
- SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; \r
-\r
+ here the ramp up of the system clock starts FSys < 90MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 90000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+ stepping_K2DIV = (VCO/90000000)-1;\r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+\r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+\r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ }\r
+ }/* end this weak function enables DAVE3 clock App usage */\r
return(1);\r
\r
}\r
\r
/**\r
* @brief -\r
- * @note - \r
+ * @note -\r
* @param None\r
* @retval None\r
*/\r
-#if(SCU_USB_CLOCK_SETUP == 1)\r
-static void USBClockSetup(void)\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void)\r
{\r
-/* enable PLL first */\r
- SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | \r
- SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
+/* this weak function enables DAVE3 clock App usage */\r
+if(AllowPLLInitByStartup()){\r
+\r
+ /* check if PLL is switched on */\r
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
+}\r
\r
/* check and if not already running enable OSC_HP */\r
- if(!((SCU_PLL->PLLSTAT) & \r
- (SCU_PLL_PLLSTAT_PLLHV_Msk | \r
- SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)))\r
- {\r
- if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
- {\r
- \r
- SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); /*enable the OSC_HP*/\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ /* check if Main PLL is switched on for OSC WD*/\r
+ if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+ }\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
/* setup OSC WDG devider */\r
- SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16); \r
- /* select external OSC as PLL input */\r
- SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);\r
/* restart OSC Watchdog */\r
- SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
- \r
- do \r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;\r
+\r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ do\r
{\r
- ; /* here a timeout need to be added */\r
- }while(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | \r
- SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk))); \r
- \r
- }\r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));\r
+\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
+\r
}\r
\r
\r
/* disconnect OSC_FI to PLL */\r
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
/* Setup devider settings for main PLL */\r
- SCU_PLL->USBPLLCON = ((USBPLL_NDIV<<8) | (USBPLL_PDIV<<24));\r
+ SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));\r
+ /* Setup USBDIV settings USB clock */\r
+ SCU_CLK->USBCLKCR = SCU_USBDIV;\r
/* we may have to set OSCDISCDIS */\r
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
/* connect OSC_FI to PLL */\r
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
/* wait for PLL Lock */\r
while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
- }\r
+\r
+ }/* end this weak function enables DAVE3 clock App usage */\r
+ return(1);\r
+\r
+}\r
#endif\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_XMC4500.h\r
+ * @brief Header file for the XMC4500-Series systeminit\r
+ * \r
+ * @version V1.6\r
+ * @date 23. October 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon\92s microcontrollers. \r
+ * This file can be freely distributed within development tools that are supporting such microcontrollers. \r
+\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __SYSTEM_XMC4500_H\r
+#define __SYSTEM_XMC4500_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System.\r
+ */\r
+extern void SystemInit (void);\r
+\r
+\r
+/**\r
+ * Update SystemCoreClock variable\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Updates the SystemCoreClock with current core Clock\r
+ * retrieved from cpu registers.\r
+ */\r
+extern void SystemCoreClockUpdate (void);\r
+\r
+/* this weak function enables DAVE3 clock App usage */ \r
+extern uint32_t AllowPLLInitByStartup(void); \r
+\r
+\r
+/* clock definitions, do not modify! */\r
+#define SCU_CLOCK_CRYSTAL 1\r
+\r
+ \r
+ \r
+/* \r
+ * mandatory clock parameters ************************************************** \r
+ */ \r
+/* source for clock generation \r
+ * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) \r
+ * mandatory for old system_xmc4500.c files - please do not remove!!! \r
+ **************************************************************************************/ \r
+ \r
+#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL\r
+#define CLOCK_OSC_HP 24000000\r
+#define CLOCK_BACK_UP 24000000 \r
+#define CLOCK_CRYSTAL_FREQUENCY 12000000 \r
+#define SYSTEM_FREQUENCY 120000000 \r
+ \r
+/* OSC_HP setup parameters */ \r
+#define OSC_HP_MODE 0 \r
+#define OSCHPWDGDIV 2\r
+ \r
+/* MAIN PLL setup parameters */ \r
+ \r
+ \r
+#define PLL_K1DIV 1 \r
+#define PLL_K2DIV 3 \r
+#define PLL_PDIV 1 \r
+#define PLL_NDIV 79\r
+ \r
+ \r
+ \r
+#define PLL_K2DIV_STEP_1 19 //PLL output is 24Mhz \r
+#define PLL_K2DIV_STEP_2 7 //PLL output to 60Mhz \r
+#define PLL_K2DIV_STEP_3 4 //PLL output to 96Mhz \r
+ \r
+ \r
+ \r
+#define USBPLL_PDIV 1 \r
+#define USBPLL_NDIV 15 \r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif\r
#include "FreeRTOS.h"\r
#include "task.h"\r
\r
-/* Hardware includes. */\r
-#include "XMC4500.h"\r
-#include "System_XMC4500.h"\r
-\r
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
or 0 to run the more comprehensive test and demo application. */\r
-#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0\r
\r
/*-----------------------------------------------------------*/\r
\r
{\r
extern void SystemCoreClockUpdate( void );\r
\r
- /* Ensure SystemCoreClock variable is set. */\r
- SystemCoreClockUpdate();\r
-\r
- /* Configure pin P3.9 for the LED. */\r
- PORT3->IOCR8 = 0x00008000;\r
-\r
/* Ensure all priority bits are assigned as preemption priority bits. */\r
NVIC_SetPriorityGrouping( 0 );\r
}\r
#include "task.h"\r
#include "semphr.h"\r
\r
-/* Hardware includes. */\r
-#include "XMC4500.h"\r
-#include "System_XMC4500.h"\r
-\r
/* Priorities at which the tasks are created. */\r
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )\r
#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )\r
\r
-/* To toggle the single LED */\r
-#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 )\r
-\r
/*-----------------------------------------------------------*/\r
\r
/*\r
*/\r
void main_blinky( void );\r
\r
-/*\r
- * The hardware only has a single LED. Simply toggle it.\r
- */\r
-extern void vMainToggleLED( void );\r
-\r
/*-----------------------------------------------------------*/\r
\r
/* The queue used by both tasks. */\r
is it the expected value? If it is, toggle the LED. */\r
if( ulReceivedValue == 100UL )\r
{\r
- mainTOGGLE_LED();\r
+ configTOGGLE_LED();\r
ulReceivedValue = 0U;\r
}\r
}\r
#include "recmutex.h"\r
#include "death.h"\r
\r
-/* Hardware includes. */\r
-#include "XMC4500.h"\r
-#include "System_XMC4500.h"\r
-\r
/* Priorities for the demo application tasks. */\r
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
\r
-/* To toggle the single LED */\r
-#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 )\r
-\r
/* A block time of zero simply means "don't block". */\r
#define mainDONT_BLOCK ( 0UL )\r
\r
/* Start all the other standard demo/test tasks. The have not particular\r
functionality, but do demonstrate how to use the FreeRTOS API and test the\r
kernel port. */\r
- vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
vStartDynamicPriorityTasks();\r
- vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
vCreateBlockTimeTasks();\r
vStartCountingSemaphoreTasks();\r
vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
vStartRecursiveMutexTasks();\r
- vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
\r
xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
}\r
\r
- /* The set of tasks created by the following function call have to be \r
- created last as they keep account of the number of tasks they expect to see \r
- running. */\r
- vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
-\r
/* Start the scheduler. */\r
vTaskStartScheduler();\r
\r
ulErrorFound = pdTRUE;\r
}\r
\r
- if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound = pdTRUE;\r
- }\r
-\r
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
{\r
ulErrorFound = pdTRUE;\r
}\r
\r
- if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound = pdTRUE;\r
- }\r
-\r
if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
{\r
ulErrorFound = pdTRUE;\r
ulErrorFound = pdTRUE;\r
}\r
\r
- if( xIsCreateTaskStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound = pdTRUE;\r
- }\r
-\r
- if( xArePollingQueuesStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound = pdTRUE;\r
- }\r
-\r
if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
{\r
ulErrorFound = pdTRUE;\r
/* Toggle the check LED to give an indication of the system status. If\r
the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
everything is ok. A faster toggle indicates an error. */\r
- mainTOGGLE_LED(); \r
+ configTOGGLE_LED(); \r
\r
/* Have any errors been latch in ulErrorFound? If so, shorten the\r
period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.\r
--- /dev/null
+;*****************************************************************************/\r
+; * @file startup_XMC4200.s\r
+; * @brief CMSIS Cortex-M4 Core Device Startup File for\r
+; * Infineon XMC4200 Device Series\r
+; * @version V1.00\r
+; * @date 05. February 2013\r
+; *\r
+; * @note\r
+; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.\r
+; *\r
+; * @par\r
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+; * processor based microcontrollers. This file can be freely distributed\r
+; * within development tools that are supporting such ARM based processors.\r
+; *\r
+; * @par\r
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+; *\r
+; ******************************************************************************/\r
+\r
+;/* ********************* Version History *********************************** */\r
+;/* ***************************************************************************\r
+; V0.1 , September 2012, First version\r
+; V1.0 , February 2013, FIX for CPU prefetch bug implemented\r
+;**************************************************************************** */\r
+\r
+\r
+;* <<< Use Configuration Wizard in Context Menu >>>\r
+\r
+; Amount of memory (in bytes) allocated for Stack\r
+; Tailor this value to your application needs\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000400\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000000\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+\r
+;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */\r
+;/*\r
+; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).\r
+; * A veneer defined below will first\r
+; * be executed which in turn branches to the final exception handler.\r
+; *\r
+; * In addition to defining the veneers, the vector table must for these buggy\r
+; * devices contain the veneers.\r
+; */\r
+\r
+;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define\r
+;or use define below\r
+ GBLL WORKAROUND_PMU_CM001\r
+\r
+;/* A macro to setup a vector table entry based on STEP ID */\r
+ IF :DEF:WORKAROUND_PMU_CM001\r
+ MACRO\r
+ ExcpVector $Handler\r
+ DCD $Handler._Veneer\r
+ MEND\r
+ ELSE\r
+ MACRO\r
+ ExcpVector $Handler\r
+ DCD $Handler\r
+ MEND\r
+ ENDIF\r
+\r
+;/* A macro to ease definition of the various handlers based on STEP ID */\r
+ IF :DEF:WORKAROUND_PMU_CM001\r
+\r
+ ;/* First define the final exception handler */\r
+ MACRO\r
+ ExcpHandler $Handler_Func\r
+$Handler_Func\\r
+ PROC\r
+ EXPORT $Handler_Func [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+ ;/* And then define a veneer that will branch to the final excp handler */\r
+$Handler_Func._Veneer\\r
+ PROC\r
+ EXPORT $Handler_Func._Veneer [WEAK]\r
+ LDR R0, =$Handler_Func\r
+ PUSH {LR}\r
+ BLX R0\r
+ POP {PC}\r
+ ALIGN\r
+ LTORG\r
+ ENDP\r
+ MEND\r
+\r
+ ELSE\r
+\r
+ ;/* No prefetch bug, hence define only the final exception handler */\r
+ MACRO\r
+ ExcpHandler $Handler_Func\r
+$Handler_Func\\r
+ PROC\r
+ EXPORT $Handler_Func [WEAK]\r
+ B .\r
+ ENDP\r
+ MEND\r
+\r
+ ENDIF\r
+;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */\r
+\r
+\r
+;* ================== START OF VECTOR TABLE DEFINITION ====================== */\r
+;* Vector Table - This gets programed into VTOR register */\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __Vectors_End\r
+ EXPORT __Vectors_Size\r
+\r
+\r
+\r
+__Vectors\r
+ DCD __initial_sp ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+\r
+ ExcpVector NMI_Handler ; NMI Handler\r
+ ExcpVector HardFault_Handler ; Hard Fault Handler\r
+ ExcpVector MemManage_Handler ; MPU Fault Handler\r
+ ExcpVector BusFault_Handler ; Bus Fault Handler\r
+ ExcpVector UsageFault_Handler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ ExcpVector DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals\r
+ ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0\r
+ ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0\r
+ ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1\r
+ ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2\r
+ ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3\r
+ ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0\r
+ ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1\r
+ ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2\r
+ ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0\r
+ DCD 0 ; Reserved\r
+ ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0\r
+ ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1\r
+ ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1\r
+ ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3\r
+ ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0\r
+ ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1\r
+ ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2\r
+ ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3\r
+ ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0\r
+ ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1\r
+ ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2\r
+ ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0\r
+ ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1\r
+ ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0\r
+ ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1\r
+ ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2\r
+ ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3\r
+ ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0\r
+ ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1\r
+ ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2\r
+ ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0\r
+ ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1\r
+ ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2\r
+ ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0\r
+ ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ ExcpVector HRPWM_0_IRQHandler ; Handler name for SR HRPWM_0\r
+ ExcpVector HRPWM_1_IRQHandler ; Handler name for SR HRPWM_1\r
+ ExcpVector HRPWM_2_IRQHandler ; Handler name for SR HRPWM_2\r
+ ExcpVector HRPWM_3_IRQHandler ; Handler name for SR HRPWM_3\r
+ ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0\r
+ ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1\r
+ ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2\r
+ ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3\r
+ ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4\r
+ ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5\r
+ ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6\r
+ ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7\r
+ ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0\r
+ ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1\r
+ ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2\r
+ ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3\r
+ ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4\r
+ ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5\r
+ ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0\r
+ ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1\r
+ ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2\r
+ ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3\r
+ ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4\r
+ ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0\r
+ DCD 0 ; Reserved\r
+ ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0\r
+ ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0\r
+ DCD 0 ; Reserved\r
+ ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+__Vectors_End\r
+\r
+__Vectors_Size EQU __Vectors_End - __Vectors\r
+\r
+;* ================== END OF VECTOR TABLE DEFINITION ======================= */\r
+\r
+;* ================== START OF VECTOR ROUTINES ============================= */\r
+\r
+ AREA |.text|, CODE, READONLY\r
+\r
+;* Reset Handler */\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT SystemInit\r
+ IMPORT __main\r
+\r
+ ; Remap vector table\r
+ LDR R0, =__Vectors\r
+ LDR R1, =0xE000ED08 ;*VTOR register\r
+ STR R0,[R1]\r
+\r
+ ;* C routines are likely to be called. Setup the stack now\r
+ LDR SP,=__initial_sp\r
+\r
+ LDR R0, = SystemInit\r
+ BLX R0\r
+\r
+ ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is\r
+ ;weakly defined here though for a potential override.\r
+\r
+ LDR R0, = SystemInit_DAVE3\r
+ BLX R0\r
+\r
+ ;* Reset stack pointer before zipping off to user application\r
+ LDR SP,=__initial_sp\r
+\r
+ LDR R0, =__main\r
+ BX R0\r
+\r
+ ALIGN\r
+ ENDP\r
+\r
+\r
+\r
+\r
+;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */\r
+\r
+\r
+\r
+;/* Default exception Handlers - Users may override this default functionality by\r
+; defining handlers of the same name in their C code */\r
+\r
+ ExcpHandler NMI_Handler\r
+ ExcpHandler HardFault_Handler\r
+ ExcpHandler MemManage_Handler\r
+ ExcpHandler BusFault_Handler\r
+ ExcpHandler UsageFault_Handler\r
+ ExcpHandler SVC_Handler\r
+ ExcpHandler DebugMon_Handler\r
+ ExcpHandler PendSV_Handler\r
+ ExcpHandler SysTick_Handler\r
+\r
+;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */\r
+\r
+;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */\r
+\r
+;* IRQ Handlers */\r
+ ExcpHandler SCU_0_IRQHandler\r
+ ExcpHandler ERU0_0_IRQHandler\r
+ ExcpHandler ERU0_1_IRQHandler\r
+ ExcpHandler ERU0_2_IRQHandler\r
+ ExcpHandler ERU0_3_IRQHandler\r
+ ExcpHandler ERU1_0_IRQHandler\r
+ ExcpHandler ERU1_1_IRQHandler\r
+ ExcpHandler ERU1_2_IRQHandler\r
+ ExcpHandler ERU1_3_IRQHandler\r
+ ExcpHandler PMU0_0_IRQHandler\r
+ ExcpHandler VADC0_C0_0_IRQHandler\r
+ ExcpHandler VADC0_C0_1_IRQHandler\r
+ ExcpHandler VADC0_C0_2_IRQHandler\r
+ ExcpHandler VADC0_C0_3_IRQHandler\r
+ ExcpHandler VADC0_G0_0_IRQHandler\r
+ ExcpHandler VADC0_G0_1_IRQHandler\r
+ ExcpHandler VADC0_G0_2_IRQHandler\r
+ ExcpHandler VADC0_G0_3_IRQHandler\r
+ ExcpHandler VADC0_G1_0_IRQHandler\r
+ ExcpHandler VADC0_G1_1_IRQHandler\r
+ ExcpHandler VADC0_G1_2_IRQHandler\r
+ ExcpHandler VADC0_G1_3_IRQHandler\r
+ ExcpHandler DAC0_0_IRQHandler\r
+ ExcpHandler DAC0_1_IRQHandler\r
+ ExcpHandler CCU40_0_IRQHandler\r
+ ExcpHandler CCU40_1_IRQHandler\r
+ ExcpHandler CCU40_2_IRQHandler\r
+ ExcpHandler CCU40_3_IRQHandler\r
+ ExcpHandler CCU41_0_IRQHandler\r
+ ExcpHandler CCU41_1_IRQHandler\r
+ ExcpHandler CCU41_2_IRQHandler\r
+ ExcpHandler CCU41_3_IRQHandler\r
+ ExcpHandler CCU80_0_IRQHandler\r
+ ExcpHandler CCU80_1_IRQHandler\r
+ ExcpHandler CCU80_2_IRQHandler\r
+ ExcpHandler CCU80_3_IRQHandler\r
+ ExcpHandler POSIF0_0_IRQHandler\r
+ ExcpHandler POSIF0_1_IRQHandler\r
+ ExcpHandler HRPWM_0_IRQHandler\r
+ ExcpHandler HRPWM_1_IRQHandler\r
+ ExcpHandler HRPWM_2_IRQHandler\r
+ ExcpHandler HRPWM_3_IRQHandler\r
+ ExcpHandler CAN0_0_IRQHandler\r
+ ExcpHandler CAN0_1_IRQHandler\r
+ ExcpHandler CAN0_2_IRQHandler\r
+ ExcpHandler CAN0_3_IRQHandler\r
+ ExcpHandler CAN0_4_IRQHandler\r
+ ExcpHandler CAN0_5_IRQHandler\r
+ ExcpHandler CAN0_6_IRQHandler\r
+ ExcpHandler CAN0_7_IRQHandler\r
+ ExcpHandler USIC0_0_IRQHandler\r
+ ExcpHandler USIC0_1_IRQHandler\r
+ ExcpHandler USIC0_2_IRQHandler\r
+ ExcpHandler USIC0_3_IRQHandler\r
+ ExcpHandler USIC0_4_IRQHandler\r
+ ExcpHandler USIC0_5_IRQHandler\r
+ ExcpHandler USIC1_0_IRQHandler\r
+ ExcpHandler USIC1_1_IRQHandler\r
+ ExcpHandler USIC1_2_IRQHandler\r
+ ExcpHandler USIC1_3_IRQHandler\r
+ ExcpHandler USIC1_4_IRQHandler\r
+ ExcpHandler USIC1_5_IRQHandler\r
+ ExcpHandler LEDTS0_0_IRQHandler\r
+ ExcpHandler FCE0_0_IRQHandler\r
+ ExcpHandler GPDMA0_0_IRQHandler\r
+ ExcpHandler USB0_0_IRQHandler\r
+\r
+;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */\r
+\r
+;* Definition of the default weak SystemInit_DAVE3 function.\r
+;* This function will be called by the CMSIS SystemInit function.\r
+;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3\r
+;* which will overule this weak definition\r
+SystemInit_DAVE3 PROC\r
+ EXPORT SystemInit_DAVE3 [WEAK]\r
+ NOP\r
+ BX LR\r
+ ENDP\r
+\r
+;* Definition of the default weak DAVE3 function for clock App usage.\r
+;* AllowPLLInitByStartup Handler */\r
+AllowPLLInitByStartup PROC\r
+ EXPORT AllowPLLInitByStartup [WEAK]\r
+ MOV R0,#1\r
+ BX LR\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+;*******************************************************************************\r
+; User Stack and Heap initialization\r
+;*******************************************************************************\r
+ IF :DEF:__MICROLIB\r
+\r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+\r
+ ELSE\r
+\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+\r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+ END\r
+\r
+;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE*****\r
--- /dev/null
+;*****************************************************************************/\r
+; * @file startup_XMC4400.s\r
+; * @brief CMSIS Cortex-M4 Core Device Startup File for\r
+; * Infineon XMC4400 Device Series\r
+; * @version V1.00\r
+; * @date 05. February 2013\r
+; *\r
+; * @note\r
+; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.\r
+; *\r
+; * @par\r
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+; * processor based microcontrollers. This file can be freely distributed\r
+; * within development tools that are supporting such ARM based processors.\r
+; *\r
+; * @par\r
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+; *\r
+; ******************************************************************************/\r
+\r
+;/* ********************* Version History *********************************** */\r
+;/* ***************************************************************************\r
+; V0.2 , August 2012, First version\r
+; V1.0 , February 2013, FIX for CPU prefetch bug implemented\r
+;**************************************************************************** */\r
+\r
+\r
+;* <<< Use Configuration Wizard in Context Menu >>>\r
+\r
+; Amount of memory (in bytes) allocated for Stack\r
+; Tailor this value to your application needs\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000400\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000200\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+\r
+;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */\r
+;/*\r
+; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).\r
+; * A veneer defined below will first\r
+; * be executed which in turn branches to the final exception handler.\r
+; *\r
+; * In addition to defining the veneers, the vector table must for these buggy\r
+; * devices contain the veneers.\r
+; */\r
+\r
+;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define\r
+;or use define below\r
+ GBLL WORKAROUND_PMU_CM001\r
+\r
+;/* A macro to setup a vector table entry based on STEP ID */\r
+ IF :DEF:WORKAROUND_PMU_CM001\r
+ MACRO\r
+ ExcpVector $Handler\r
+ DCD $Handler._Veneer\r
+ MEND\r
+ ELSE\r
+ MACRO\r
+ ExcpVector $Handler\r
+ DCD $Handler\r
+ MEND\r
+ ENDIF\r
+\r
+;/* A macro to ease definition of the various handlers based on STEP ID */\r
+ IF :DEF:WORKAROUND_PMU_CM001\r
+\r
+ ;/* First define the final exception handler */\r
+ MACRO\r
+ ExcpHandler $Handler_Func\r
+$Handler_Func\\r
+ PROC\r
+ EXPORT $Handler_Func [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+ ;/* And then define a veneer that will branch to the final excp handler */\r
+$Handler_Func._Veneer\\r
+ PROC\r
+ EXPORT $Handler_Func._Veneer [WEAK]\r
+ LDR R0, =$Handler_Func\r
+ PUSH {LR}\r
+ BLX R0\r
+ POP {PC}\r
+ ALIGN\r
+ LTORG\r
+ ENDP\r
+ MEND\r
+\r
+ ELSE\r
+\r
+ ;/* No prefetch bug, hence define only the final exception handler */\r
+ MACRO\r
+ ExcpHandler $Handler_Func\r
+$Handler_Func\\r
+ PROC\r
+ EXPORT $Handler_Func [WEAK]\r
+ B .\r
+ ENDP\r
+ MEND\r
+\r
+ ENDIF\r
+;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */\r
+\r
+\r
+;* ================== START OF VECTOR TABLE DEFINITION ====================== */\r
+;* Vector Table - This gets programed into VTOR register */\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __Vectors_End\r
+ EXPORT __Vectors_Size\r
+\r
+\r
+\r
+__Vectors\r
+ DCD __initial_sp ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+\r
+ ExcpVector NMI_Handler ; NMI Handler\r
+ ExcpVector HardFault_Handler ; Hard Fault Handler\r
+ ExcpVector MemManage_Handler ; MPU Fault Handler\r
+ ExcpVector BusFault_Handler ; Bus Fault Handler\r
+ ExcpVector UsageFault_Handler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ ExcpVector DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; Interrupt Handlers for Service Requests (SR) from XMC4400 Peripherals\r
+ ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0\r
+ ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0\r
+ ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1\r
+ ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2\r
+ ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3\r
+ ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0\r
+ ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1\r
+ ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2\r
+ ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0\r
+ DCD 0 ; Reserved\r
+ ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0\r
+ ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1\r
+ ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1\r
+ ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3\r
+ ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0\r
+ ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1\r
+ ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2\r
+ ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3\r
+ ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0\r
+ ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1\r
+ ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2\r
+ ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3\r
+ ExcpVector VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0\r
+ ExcpVector VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1\r
+ ExcpVector VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2\r
+ ExcpVector VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3\r
+ ExcpVector VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0\r
+ ExcpVector VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1\r
+ ExcpVector VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2\r
+ ExcpVector VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3\r
+ ExcpVector DSD0_0_IRQHandler ; Handler name for SR DSD0_0\r
+ ExcpVector DSD0_1_IRQHandler ; Handler name for SR DSD0_1\r
+ ExcpVector DSD0_2_IRQHandler ; Handler name for SR DSD0_2\r
+ ExcpVector DSD0_3_IRQHandler ; Handler name for SR DSD0_3\r
+ ExcpVector DSD0_4_IRQHandler ; Handler name for SR DSD0_4\r
+ ExcpVector DSD0_5_IRQHandler ; Handler name for SR DSD0_5\r
+ ExcpVector DSD0_6_IRQHandler ; Handler name for SR DSD0_6\r
+ ExcpVector DSD0_7_IRQHandler ; Handler name for SR DSD0_7\r
+ ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0\r
+ ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1\r
+ ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0\r
+ ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1\r
+ ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2\r
+ ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3\r
+ ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0\r
+ ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1\r
+ ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2\r
+ ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3\r
+ ExcpVector CCU42_0_IRQHandler ; Handler name for SR CCU42_0\r
+ ExcpVector CCU42_1_IRQHandler ; Handler name for SR CCU42_1\r
+ ExcpVector CCU42_2_IRQHandler ; Handler name for SR CCU42_2\r
+ ExcpVector CCU42_3_IRQHandler ; Handler name for SR CCU42_3\r
+ ExcpVector CCU43_0_IRQHandler ; Handler name for SR CCU43_0\r
+ ExcpVector CCU43_1_IRQHandler ; Handler name for SR CCU43_1\r
+ ExcpVector CCU43_2_IRQHandler ; Handler name for SR CCU43_2\r
+ ExcpVector CCU43_3_IRQHandler ; Handler name for SR CCU43_3\r
+ ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0\r
+ ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1\r
+ ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2\r
+ ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3\r
+ ExcpVector CCU81_0_IRQHandler ; Handler name for SR CCU81_0\r
+ ExcpVector CCU81_1_IRQHandler ; Handler name for SR CCU81_1\r
+ ExcpVector CCU81_2_IRQHandler ; Handler name for SR CCU81_2\r
+ ExcpVector CCU81_3_IRQHandler ; Handler name for SR CCU81_3\r
+ ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0\r
+ ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1\r
+ ExcpVector POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0\r
+ ExcpVector POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1\r
+ ExcpVector HRPWM_0_IRQHandler ; Handler name for SR HRPWM_0\r
+ ExcpVector HRPWM_1_IRQHandler ; Handler name for SR HRPWM_1\r
+ ExcpVector HRPWM_2_IRQHandler ; Handler name for SR HRPWM_2\r
+ ExcpVector HRPWM_3_IRQHandler ; Handler name for SR HRPWM_3\r
+ ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0\r
+ ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1\r
+ ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2\r
+ ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3\r
+ ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4\r
+ ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5\r
+ ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6\r
+ ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7\r
+ ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0\r
+ ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1\r
+ ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2\r
+ ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3\r
+ ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4\r
+ ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5\r
+ ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0\r
+ ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1\r
+ ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2\r
+ ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3\r
+ ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4\r
+ ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0\r
+ DCD 0 ; Reserved\r
+ ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0\r
+ ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0\r
+ DCD 0 ; Reserved\r
+ ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0\r
+ ExcpVector ETH0_0_IRQHandler ; Handler name for SR ETH0_0\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+__Vectors_End\r
+\r
+__Vectors_Size EQU __Vectors_End - __Vectors\r
+\r
+;* ================== END OF VECTOR TABLE DEFINITION ======================= */\r
+\r
+;* ================== START OF VECTOR ROUTINES ============================= */\r
+\r
+ AREA |.text|, CODE, READONLY\r
+\r
+;* Reset Handler */\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT SystemInit\r
+ IMPORT __main\r
+\r
+ ; Remap vector table\r
+ LDR R0, =__Vectors\r
+ LDR R1, =0xE000ED08 ;*VTOR register\r
+ STR R0,[R1]\r
+\r
+ ;* C routines are likely to be called. Setup the stack now\r
+ LDR SP,=__initial_sp\r
+\r
+ LDR R0, = SystemInit\r
+ BLX R0\r
+\r
+ ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is\r
+ ;weakly defined here though for a potential override.\r
+\r
+ LDR R0, = SystemInit_DAVE3\r
+ BLX R0\r
+\r
+ ;* Reset stack pointer before zipping off to user application\r
+ LDR SP,=__initial_sp\r
+\r
+ LDR R0, =__main\r
+ BX R0\r
+\r
+ ALIGN\r
+ ENDP\r
+\r
+\r
+\r
+\r
+;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */\r
+\r
+\r
+\r
+;/* Default exception Handlers - Users may override this default functionality by\r
+; defining handlers of the same name in their C code */\r
+\r
+ ExcpHandler NMI_Handler\r
+ ExcpHandler HardFault_Handler\r
+ ExcpHandler MemManage_Handler\r
+ ExcpHandler BusFault_Handler\r
+ ExcpHandler UsageFault_Handler\r
+ ExcpHandler SVC_Handler\r
+ ExcpHandler DebugMon_Handler\r
+ ExcpHandler PendSV_Handler\r
+ ExcpHandler SysTick_Handler\r
+\r
+;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */\r
+\r
+;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */\r
+\r
+;* IRQ Handlers */\r
+ ExcpHandler SCU_0_IRQHandler\r
+ ExcpHandler ERU0_0_IRQHandler\r
+ ExcpHandler ERU0_1_IRQHandler\r
+ ExcpHandler ERU0_2_IRQHandler\r
+ ExcpHandler ERU0_3_IRQHandler\r
+ ExcpHandler ERU1_0_IRQHandler\r
+ ExcpHandler ERU1_1_IRQHandler\r
+ ExcpHandler ERU1_2_IRQHandler\r
+ ExcpHandler ERU1_3_IRQHandler\r
+ ExcpHandler PMU0_0_IRQHandler\r
+ ExcpHandler VADC0_C0_0_IRQHandler\r
+ ExcpHandler VADC0_C0_1_IRQHandler\r
+ ExcpHandler VADC0_C0_2_IRQHandler\r
+ ExcpHandler VADC0_C0_3_IRQHandler\r
+ ExcpHandler VADC0_G0_0_IRQHandler\r
+ ExcpHandler VADC0_G0_1_IRQHandler\r
+ ExcpHandler VADC0_G0_2_IRQHandler\r
+ ExcpHandler VADC0_G0_3_IRQHandler\r
+ ExcpHandler VADC0_G1_0_IRQHandler\r
+ ExcpHandler VADC0_G1_1_IRQHandler\r
+ ExcpHandler VADC0_G1_2_IRQHandler\r
+ ExcpHandler VADC0_G1_3_IRQHandler\r
+ ExcpHandler VADC0_G2_0_IRQHandler\r
+ ExcpHandler VADC0_G2_1_IRQHandler\r
+ ExcpHandler VADC0_G2_2_IRQHandler\r
+ ExcpHandler VADC0_G2_3_IRQHandler\r
+ ExcpHandler VADC0_G3_0_IRQHandler\r
+ ExcpHandler VADC0_G3_1_IRQHandler\r
+ ExcpHandler VADC0_G3_2_IRQHandler\r
+ ExcpHandler VADC0_G3_3_IRQHandler\r
+ ExcpHandler DSD0_0_IRQHandler\r
+ ExcpHandler DSD0_1_IRQHandler\r
+ ExcpHandler DSD0_2_IRQHandler\r
+ ExcpHandler DSD0_3_IRQHandler\r
+ ExcpHandler DSD0_4_IRQHandler\r
+ ExcpHandler DSD0_5_IRQHandler\r
+ ExcpHandler DSD0_6_IRQHandler\r
+ ExcpHandler DSD0_7_IRQHandler\r
+ ExcpHandler DAC0_0_IRQHandler\r
+ ExcpHandler DAC0_1_IRQHandler\r
+ ExcpHandler CCU40_0_IRQHandler\r
+ ExcpHandler CCU40_1_IRQHandler\r
+ ExcpHandler CCU40_2_IRQHandler\r
+ ExcpHandler CCU40_3_IRQHandler\r
+ ExcpHandler CCU41_0_IRQHandler\r
+ ExcpHandler CCU41_1_IRQHandler\r
+ ExcpHandler CCU41_2_IRQHandler\r
+ ExcpHandler CCU41_3_IRQHandler\r
+ ExcpHandler CCU42_0_IRQHandler\r
+ ExcpHandler CCU42_1_IRQHandler\r
+ ExcpHandler CCU42_2_IRQHandler\r
+ ExcpHandler CCU42_3_IRQHandler\r
+ ExcpHandler CCU43_0_IRQHandler\r
+ ExcpHandler CCU43_1_IRQHandler\r
+ ExcpHandler CCU43_2_IRQHandler\r
+ ExcpHandler CCU43_3_IRQHandler\r
+ ExcpHandler CCU80_0_IRQHandler\r
+ ExcpHandler CCU80_1_IRQHandler\r
+ ExcpHandler CCU80_2_IRQHandler\r
+ ExcpHandler CCU80_3_IRQHandler\r
+ ExcpHandler CCU81_0_IRQHandler\r
+ ExcpHandler CCU81_1_IRQHandler\r
+ ExcpHandler CCU81_2_IRQHandler\r
+ ExcpHandler CCU81_3_IRQHandler\r
+ ExcpHandler POSIF0_0_IRQHandler\r
+ ExcpHandler POSIF0_1_IRQHandler\r
+ ExcpHandler POSIF1_0_IRQHandler\r
+ ExcpHandler POSIF1_1_IRQHandler\r
+ ExcpHandler HRPWM_0_IRQHandler\r
+ ExcpHandler HRPWM_1_IRQHandler\r
+ ExcpHandler HRPWM_2_IRQHandler\r
+ ExcpHandler HRPWM_3_IRQHandler\r
+ ExcpHandler CAN0_0_IRQHandler\r
+ ExcpHandler CAN0_1_IRQHandler\r
+ ExcpHandler CAN0_2_IRQHandler\r
+ ExcpHandler CAN0_3_IRQHandler\r
+ ExcpHandler CAN0_4_IRQHandler\r
+ ExcpHandler CAN0_5_IRQHandler\r
+ ExcpHandler CAN0_6_IRQHandler\r
+ ExcpHandler CAN0_7_IRQHandler\r
+ ExcpHandler USIC0_0_IRQHandler\r
+ ExcpHandler USIC0_1_IRQHandler\r
+ ExcpHandler USIC0_2_IRQHandler\r
+ ExcpHandler USIC0_3_IRQHandler\r
+ ExcpHandler USIC0_4_IRQHandler\r
+ ExcpHandler USIC0_5_IRQHandler\r
+ ExcpHandler USIC1_0_IRQHandler\r
+ ExcpHandler USIC1_1_IRQHandler\r
+ ExcpHandler USIC1_2_IRQHandler\r
+ ExcpHandler USIC1_3_IRQHandler\r
+ ExcpHandler USIC1_4_IRQHandler\r
+ ExcpHandler USIC1_5_IRQHandler\r
+ ExcpHandler LEDTS0_0_IRQHandler\r
+ ExcpHandler FCE0_0_IRQHandler\r
+ ExcpHandler GPDMA0_0_IRQHandler\r
+ ExcpHandler USB0_0_IRQHandler\r
+ ExcpHandler ETH0_0_IRQHandler\r
+\r
+;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */\r
+\r
+;* Definition of the default weak SystemInit_DAVE3 function.\r
+;* This function will be called by the CMSIS SystemInit function.\r
+;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3\r
+;* which will overule this weak definition\r
+SystemInit_DAVE3 PROC\r
+ EXPORT SystemInit_DAVE3 [WEAK]\r
+ NOP\r
+ BX LR\r
+ ENDP\r
+\r
+;* Definition of the default weak DAVE3 function for clock App usage.\r
+;* AllowPLLInitByStartup Handler */\r
+AllowPLLInitByStartup PROC\r
+ EXPORT AllowPLLInitByStartup [WEAK]\r
+ MOV R0,#1\r
+ BX LR\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+;*******************************************************************************\r
+; User Stack and Heap initialization\r
+;*******************************************************************************\r
+ IF :DEF:__MICROLIB\r
+\r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+\r
+ ELSE\r
+\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+\r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+ END\r
+\r
+;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE*****\r
-;*****************************************************************************/
+;*****************************************************************************/\r
; * @file startup_XMC4500.s\r
; * @brief CMSIS Cortex-M4 Core Device Startup File for\r
; * Infineon XMC4500 Device Series\r
-; * @version V1.03\r
-; * @date 16. Jan. 2012\r
+; * @version V1.20\r
+; * @date 05. February 2013\r
; *\r
; * @note\r
-; * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.\r
; *\r
; * @par\r
; * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
; *\r
; ******************************************************************************/\r
-
-
-;* <<< Use Configuration Wizard in Context Menu >>>
-
+\r
+;/* ********************* Version History *********************************** */\r
+;/* ***************************************************************************\r
+; V1.00 , February 2012, First version\r
+; V1.10 , August 2012, Adding Dave3 init function call\r
+; V1.20 , February 2013, FIX for CPU prefetch bug implemented\r
+;**************************************************************************** */\r
+\r
+\r
+;* <<< Use Configuration Wizard in Context Menu >>>\r
+\r
; Amount of memory (in bytes) allocated for Stack\r
; Tailor this value to your application needs\r
; <h> Stack Configuration\r
PRESERVE8\r
THUMB\r
\r
-
-;* ================== START OF VECTOR TABLE DEFINITION ====================== */
-;* Vector Table - This gets programed into VTOR register */
+\r
+;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */\r
+;/*\r
+; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).\r
+; * A veneer defined below will first\r
+; * be executed which in turn branches to the final exception handler.\r
+; *\r
+; * In addition to defining the veneers, the vector table must for these buggy\r
+; * devices contain the veneers.\r
+; */\r
+\r
+;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define\r
+;or use define below\r
+ GBLL WORKAROUND_PMU_CM001\r
+\r
+;/* A macro to setup a vector table entry based on STEP ID */\r
+ IF :DEF:WORKAROUND_PMU_CM001\r
+ MACRO\r
+ ExcpVector $Handler\r
+ DCD $Handler._Veneer\r
+ MEND\r
+ ELSE\r
+ MACRO\r
+ ExcpVector $Handler\r
+ DCD $Handler\r
+ MEND\r
+ ENDIF\r
+\r
+;/* A macro to ease definition of the various handlers based on STEP ID */\r
+ IF :DEF:WORKAROUND_PMU_CM001\r
+\r
+ ;/* First define the final exception handler */\r
+ MACRO\r
+ ExcpHandler $Handler_Func\r
+$Handler_Func\\r
+ PROC\r
+ EXPORT $Handler_Func [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+ ;/* And then define a veneer that will branch to the final excp handler */\r
+$Handler_Func._Veneer\\r
+ PROC\r
+ EXPORT $Handler_Func._Veneer [WEAK]\r
+ LDR R0, =$Handler_Func\r
+ PUSH {LR}\r
+ BLX R0\r
+ POP {PC}\r
+ ALIGN\r
+ LTORG\r
+ ENDP\r
+ MEND\r
+\r
+ ELSE\r
+\r
+ ;/* No prefetch bug, hence define only the final exception handler */\r
+ MACRO\r
+ ExcpHandler $Handler_Func\r
+$Handler_Func\\r
+ PROC\r
+ EXPORT $Handler_Func [WEAK]\r
+ B .\r
+ ENDP\r
+ MEND\r
+\r
+ ENDIF\r
+;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */\r
+\r
+\r
+;* ================== START OF VECTOR TABLE DEFINITION ====================== */\r
+;* Vector Table - This gets programed into VTOR register */\r
AREA RESET, DATA, READONLY\r
EXPORT __Vectors\r
EXPORT __Vectors_End\r
EXPORT __Vectors_Size\r
\r
\r
-
-__Vectors
- DCD __initial_sp ;* Top of Stack */
- DCD Reset_Handler ;* Reset Handler */
- DCD NMI_Handler ;* NMI Handler */
- DCD HardFault_Handler ;* Hard Fault Handler */
- DCD MemManage_Handler ;* MPU Fault Handler */
- DCD BusFault_Handler ;* Bus Fault Handler */
- DCD UsageFault_Handler ;* Usage Fault Handler */
- DCD 0 ;* Reserved */
- DCD 0 ;* Reserved */
- DCD 0 ;* Reserved */
- DCD 0 ;* Reserved */
- DCD SVC_Handler ;* SVCall Handler */
- DCD DebugMon_Handler ;* Debug Monitor Handler */
- DCD 0 ;* Reserved */
- DCD PendSV_Handler ;* PendSV Handler */
- DCD SysTick_Handler ;* SysTick Handler */
-
- ;* Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals */
- DCD SCU_0_IRQHandler ;* Handler name for SR SCU_0 */
- DCD ERU0_0_IRQHandler ;* Handler name for SR ERU0_0 */
- DCD ERU0_1_IRQHandler ;* Handler name for SR ERU0_1 */
- DCD ERU0_2_IRQHandler ;* Handler name for SR ERU0_2 */
- DCD ERU0_3_IRQHandler ;* Handler name for SR ERU0_3 */
- DCD ERU1_0_IRQHandler ;* Handler name for SR ERU1_0 */
- DCD ERU1_1_IRQHandler ;* Handler name for SR ERU1_1 */
- DCD ERU1_2_IRQHandler ;* Handler name for SR ERU1_2 */
- DCD ERU1_3_IRQHandler ;* Handler name for SR ERU1_3 */
- DCD 0 ;* Not Available */
- DCD 0 ;* Not Available */
- DCD 0 ;* Not Available */
- DCD PMU0_0_IRQHandler ;* Handler name for SR PMU0_0 */
- DCD 0 ;* Not Available */
- DCD VADC0_C0_0_IRQHandler ;* Handler name for SR VADC0_C0_0 */
- DCD VADC0_C0_1_IRQHandler ;* Handler name for SR VADC0_C0_1 */
- DCD VADC0_C0_2_IRQHandler ;* Handler name for SR VADC0_C0_1 */
- DCD VADC0_C0_3_IRQHandler ;* Handler name for SR VADC0_C0_3 */
- DCD VADC0_G0_0_IRQHandler ;* Handler name for SR VADC0_G0_0 */
- DCD VADC0_G0_1_IRQHandler ;* Handler name for SR VADC0_G0_1 */
- DCD VADC0_G0_2_IRQHandler ;* Handler name for SR VADC0_G0_2 */
- DCD VADC0_G0_3_IRQHandler ;* Handler name for SR VADC0_G0_3 */
- DCD VADC0_G1_0_IRQHandler ;* Handler name for SR VADC0_G1_0 */
- DCD VADC0_G1_1_IRQHandler ;* Handler name for SR VADC0_G1_1 */
- DCD VADC0_G1_2_IRQHandler ;* Handler name for SR VADC0_G1_2 */
- DCD VADC0_G1_3_IRQHandler ;* Handler name for SR VADC0_G1_3 */
- DCD VADC0_G2_0_IRQHandler ;* Handler name for SR VADC0_G2_0 */
- DCD VADC0_G2_1_IRQHandler ;* Handler name for SR VADC0_G2_1 */
- DCD VADC0_G2_2_IRQHandler ;* Handler name for SR VADC0_G2_2 */
- DCD VADC0_G2_3_IRQHandler ;* Handler name for SR VADC0_G2_3 */
- DCD VADC0_G3_0_IRQHandler ;* Handler name for SR VADC0_G3_0 */
- DCD VADC0_G3_1_IRQHandler ;* Handler name for SR VADC0_G3_1 */
- DCD VADC0_G3_2_IRQHandler ;* Handler name for SR VADC0_G3_2 */
- DCD VADC0_G3_3_IRQHandler ;* Handler name for SR VADC0_G3_3 */
- DCD DSD0_0_IRQHandler ;* Handler name for SR DSD0_0 */
- DCD DSD0_1_IRQHandler ;* Handler name for SR DSD0_1 */
- DCD DSD0_2_IRQHandler ;* Handler name for SR DSD0_2 */
- DCD DSD0_3_IRQHandler ;* Handler name for SR DSD0_3 */
- DCD DSD0_4_IRQHandler ;* Handler name for SR DSD0_4 */
- DCD DSD0_5_IRQHandler ;* Handler name for SR DSD0_5 */
- DCD DSD0_6_IRQHandler ;* Handler name for SR DSD0_6 */
- DCD DSD0_7_IRQHandler ;* Handler name for SR DSD0_7 */
- DCD DAC0_0_IRQHandler ;* Handler name for SR DAC0_0 */
- DCD DAC0_1_IRQHandler ;* Handler name for SR DAC0_0 */
- DCD CCU40_0_IRQHandler ;* Handler name for SR CCU40_0 */
- DCD CCU40_1_IRQHandler ;* Handler name for SR CCU40_1 */
- DCD CCU40_2_IRQHandler ;* Handler name for SR CCU40_2 */
- DCD CCU40_3_IRQHandler ;* Handler name for SR CCU40_3 */
- DCD CCU41_0_IRQHandler ;* Handler name for SR CCU41_0 */
- DCD CCU41_1_IRQHandler ;* Handler name for SR CCU41_1 */
- DCD CCU41_2_IRQHandler ;* Handler name for SR CCU41_2 */
- DCD CCU41_3_IRQHandler ;* Handler name for SR CCU41_3 */
- DCD CCU42_0_IRQHandler ;* Handler name for SR CCU42_0 */
- DCD CCU42_1_IRQHandler ;* Handler name for SR CCU42_1 */
- DCD CCU42_2_IRQHandler ;* Handler name for SR CCU42_2 */
- DCD CCU42_3_IRQHandler ;* Handler name for SR CCU42_3 */
- DCD CCU43_0_IRQHandler ;* Handler name for SR CCU43_0 */
- DCD CCU43_1_IRQHandler ;* Handler name for SR CCU43_1 */
- DCD CCU43_2_IRQHandler ;* Handler name for SR CCU43_2 */
- DCD CCU43_3_IRQHandler ;* Handler name for SR CCU43_3 */
- DCD CCU80_0_IRQHandler ;* Handler name for SR CCU80_0 */
- DCD CCU80_1_IRQHandler ;* Handler name for SR CCU80_1 */
- DCD CCU80_2_IRQHandler ;* Handler name for SR CCU80_2 */
- DCD CCU80_3_IRQHandler ;* Handler name for SR CCU80_3 */
- DCD CCU81_0_IRQHandler ;* Handler name for SR CCU81_0 */
- DCD CCU81_1_IRQHandler ;* Handler name for SR CCU81_1 */
- DCD CCU81_2_IRQHandler ;* Handler name for SR CCU81_2 */
- DCD CCU81_3_IRQHandler ;* Handler name for SR CCU81_3 */
- DCD POSIF0_0_IRQHandler ;* Handler name for SR POSIF0_0 */
- DCD POSIF0_1_IRQHandler ;* Handler name for SR POSIF0_1 */
- DCD POSIF1_0_IRQHandler ;* Handler name for SR POSIF1_0 */
- DCD POSIF1_1_IRQHandler ;* Handler name for SR POSIF1_1 */
- DCD 0 ;* Not Available */
- DCD 0 ;* Not Available */
- DCD 0 ;* Not Available */
- DCD 0 ;* Not Available */
- DCD CAN0_0_IRQHandler ;* Handler name for SR CAN0_0 */
- DCD CAN0_1_IRQHandler ;* Handler name for SR CAN0_1 */
- DCD CAN0_2_IRQHandler ;* Handler name for SR CAN0_2 */
- DCD CAN0_3_IRQHandler ;* Handler name for SR CAN0_3 */
- DCD CAN0_4_IRQHandler ;* Handler name for SR CAN0_4 */
- DCD CAN0_5_IRQHandler ;* Handler name for SR CAN0_5 */
- DCD CAN0_6_IRQHandler ;* Handler name for SR CAN0_6 */
- DCD CAN0_7_IRQHandler ;* Handler name for SR CAN0_7 */
- DCD USIC0_0_IRQHandler ;* Handler name for SR USIC0_0 */
- DCD USIC0_1_IRQHandler ;* Handler name for SR USIC0_1 */
- DCD USIC0_2_IRQHandler ;* Handler name for SR USIC0_2 */
- DCD USIC0_3_IRQHandler ;* Handler name for SR USIC0_3 */
- DCD USIC0_4_IRQHandler ;* Handler name for SR USIC0_4 */
- DCD USIC0_5_IRQHandler ;* Handler name for SR USIC0_5 */
- DCD USIC1_0_IRQHandler ;* Handler name for SR USIC1_0 */
- DCD USIC1_1_IRQHandler ;* Handler name for SR USIC1_1 */
- DCD USIC1_2_IRQHandler ;* Handler name for SR USIC1_2 */
- DCD USIC1_3_IRQHandler ;* Handler name for SR USIC1_3 */
- DCD USIC1_4_IRQHandler ;* Handler name for SR USIC1_4 */
- DCD USIC1_5_IRQHandler ;* Handler name for SR USIC1_5 */
- DCD USIC2_0_IRQHandler ;* Handler name for SR USIC2_0 */
- DCD USIC2_1_IRQHandler ;* Handler name for SR USIC2_1 */
- DCD USIC2_2_IRQHandler ;* Handler name for SR USIC2_2 */
- DCD USIC2_3_IRQHandler ;* Handler name for SR USIC2_3 */
- DCD USIC2_4_IRQHandler ;* Handler name for SR USIC2_4 */
- DCD USIC2_5_IRQHandler ;* Handler name for SR USIC2_5 */
- DCD LEDTS0_0_IRQHandler ;* Handler name for SR LEDTS0_0 */
- DCD 0 ;* Not Available */
- DCD FCE0_0_IRQHandler ;* Handler name for SR FCE0_0 */
- DCD GPDMA0_0_IRQHandler ;* Handler name for SR GPDMA0_0 */
- DCD SDMMC0_0_IRQHandler ;* Handler name for SR SDMMC0_0 */
- DCD USB0_0_IRQHandler ;* Handler name for SR USB0_0 */
- DCD ETH0_0_IRQHandler ;* Handler name for SR ETH0_0 */
- DCD 0 ;* Not Available */
- DCD GPDMA1_0_IRQHandler ;* Handler name for SR GPDMA1_0 */
- DCD 0 ;* Not Available */
+\r
+__Vectors\r
+ DCD __initial_sp ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+\r
+ ExcpVector NMI_Handler ; NMI Handler\r
+ ExcpVector HardFault_Handler ; Hard Fault Handler\r
+ ExcpVector MemManage_Handler ; MPU Fault Handler\r
+ ExcpVector BusFault_Handler ; Bus Fault Handler\r
+ ExcpVector UsageFault_Handler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ ExcpVector DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals\r
+ ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0\r
+ ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0\r
+ ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1\r
+ ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2\r
+ ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3\r
+ ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0\r
+ ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1\r
+ ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2\r
+ ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0\r
+ DCD 0 ; Reserved\r
+ ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0\r
+ ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1\r
+ ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1\r
+ ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3\r
+ ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0\r
+ ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1\r
+ ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2\r
+ ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3\r
+ ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0\r
+ ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1\r
+ ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2\r
+ ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3\r
+ ExcpVector VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0\r
+ ExcpVector VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1\r
+ ExcpVector VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2\r
+ ExcpVector VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3\r
+ ExcpVector VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0\r
+ ExcpVector VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1\r
+ ExcpVector VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2\r
+ ExcpVector VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3\r
+ ExcpVector DSD0_0_IRQHandler ; Handler name for SR DSD0_0\r
+ ExcpVector DSD0_1_IRQHandler ; Handler name for SR DSD0_1\r
+ ExcpVector DSD0_2_IRQHandler ; Handler name for SR DSD0_2\r
+ ExcpVector DSD0_3_IRQHandler ; Handler name for SR DSD0_3\r
+ ExcpVector DSD0_4_IRQHandler ; Handler name for SR DSD0_4\r
+ ExcpVector DSD0_5_IRQHandler ; Handler name for SR DSD0_5\r
+ ExcpVector DSD0_6_IRQHandler ; Handler name for SR DSD0_6\r
+ ExcpVector DSD0_7_IRQHandler ; Handler name for SR DSD0_7\r
+ ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0\r
+ ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1\r
+ ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0\r
+ ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1\r
+ ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2\r
+ ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3\r
+ ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0\r
+ ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1\r
+ ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2\r
+ ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3\r
+ ExcpVector CCU42_0_IRQHandler ; Handler name for SR CCU42_0\r
+ ExcpVector CCU42_1_IRQHandler ; Handler name for SR CCU42_1\r
+ ExcpVector CCU42_2_IRQHandler ; Handler name for SR CCU42_2\r
+ ExcpVector CCU42_3_IRQHandler ; Handler name for SR CCU42_3\r
+ ExcpVector CCU43_0_IRQHandler ; Handler name for SR CCU43_0\r
+ ExcpVector CCU43_1_IRQHandler ; Handler name for SR CCU43_1\r
+ ExcpVector CCU43_2_IRQHandler ; Handler name for SR CCU43_2\r
+ ExcpVector CCU43_3_IRQHandler ; Handler name for SR CCU43_3\r
+ ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0\r
+ ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1\r
+ ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2\r
+ ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3\r
+ ExcpVector CCU81_0_IRQHandler ; Handler name for SR CCU81_0\r
+ ExcpVector CCU81_1_IRQHandler ; Handler name for SR CCU81_1\r
+ ExcpVector CCU81_2_IRQHandler ; Handler name for SR CCU81_2\r
+ ExcpVector CCU81_3_IRQHandler ; Handler name for SR CCU81_3\r
+ ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0\r
+ ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1\r
+ ExcpVector POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0\r
+ ExcpVector POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0\r
+ ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1\r
+ ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2\r
+ ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3\r
+ ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4\r
+ ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5\r
+ ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6\r
+ ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7\r
+ ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0\r
+ ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1\r
+ ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2\r
+ ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3\r
+ ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4\r
+ ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5\r
+ ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0\r
+ ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1\r
+ ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2\r
+ ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3\r
+ ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4\r
+ ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5\r
+ ExcpVector USIC2_0_IRQHandler ; Handler name for SR USIC2_0\r
+ ExcpVector USIC2_1_IRQHandler ; Handler name for SR USIC2_1\r
+ ExcpVector USIC2_2_IRQHandler ; Handler name for SR USIC2_2\r
+ ExcpVector USIC2_3_IRQHandler ; Handler name for SR USIC2_3\r
+ ExcpVector USIC2_4_IRQHandler ; Handler name for SR USIC2_4\r
+ ExcpVector USIC2_5_IRQHandler ; Handler name for SR USIC2_5\r
+ ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0\r
+ DCD 0 ; Reserved\r
+ ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0\r
+ ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0\r
+ ExcpVector SDMMC0_0_IRQHandler ; Handler name for SR SDMMC0_0\r
+ ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0\r
+ ExcpVector ETH0_0_IRQHandler ; Handler name for SR ETH0_0\r
+ DCD 0 ; Reserved\r
+ ExcpVector GPDMA1_0_IRQHandler ; Handler name for SR GPDMA1_0\r
+ DCD 0 ; Reserved\r
__Vectors_End\r
\r
-__Vectors_Size EQU __Vectors_End - __Vectors
-
-;* ================== END OF VECTOR TABLE DEFINITION ======================= */
-
+__Vectors_Size EQU __Vectors_End - __Vectors\r
+\r
+;* ================== END OF VECTOR TABLE DEFINITION ======================= */\r
+\r
;* ================== START OF VECTOR ROUTINES ============================= */\r
-
+\r
AREA |.text|, CODE, READONLY\r
-
-;* Reset Handler */
+\r
+;* Reset Handler */\r
Reset_Handler PROC\r
EXPORT Reset_Handler [WEAK]\r
- IMPORT SystemInit \r
+ IMPORT SystemInit\r
IMPORT __main\r
\r
- ; Remap vector table
- LDR R0, =__Vectors
+ ; Remap vector table\r
+ LDR R0, =__Vectors\r
LDR R1, =0xE000ED08 ;*VTOR register\r
- STR R0,[R1]
-
- ; switch off branch prediction required in A11 step to use cached memory
- LDR R0,=0x58004000 ;PREF_PCON
- LDR R1,[R0]
- ORR R1,R1,#0x00010000
- STR R1,[R0]\r
-\r
- ; Clear existing parity errors if any required in A11 step
- LDR R0,=0x50004150 ;SCU_GCU_PEFLAG
- LDR R1,=0xFFFFFFFF
- STR R1,[R0]
-
- ; Disable parity required in A11 step
- LDR R0,=0x5000413C ; SCU_GCU_PEEN
- MOV R1,#0
- STR R1,[R0]
-
- ;enable un-aligned memory access \r
- LDR R1, =0xE000ED14 \r
- LDR.W R0,[R1,#0x0]\r
- BIC R0,R0,#0x8\r
- STR.W R0,[R1,#0x0]\r
-\r
-\r
- ;* C routines are likely to be called. Setup the stack now \r
+ STR R0,[R1]\r
+\r
+ ;* C routines are likely to be called. Setup the stack now\r
LDR SP,=__initial_sp\r
\r
-
- LDR R0, = SystemInit
- BLX R0
-
- \r
- ;* Reset stack pointer before zipping off to user application
+ LDR R0, = SystemInit\r
+ BLX R0\r
+\r
+ ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is\r
+ ;weakly defined here though for a potential override.\r
+\r
+ LDR R0, = SystemInit_DAVE3\r
+ BLX R0\r
+\r
+ ;* Reset stack pointer before zipping off to user application\r
LDR SP,=__initial_sp\r
-
- LDR R0, =__main
+\r
+ LDR R0, =__main\r
BX R0\r
\r
+ ALIGN\r
ENDP\r
-
-
-;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
-
-;* Default exception Handlers - Users may override this default functionality by
-
-NMI_Handler PROC\r
- EXPORT NMI_Handler [WEAK]\r
- B .\r
- ENDP\r
-HardFault_Handler\\r
- PROC\r
- EXPORT HardFault_Handler [WEAK]\r
- B .\r
- ENDP\r
-MemManage_Handler\\r
- PROC\r
- EXPORT MemManage_Handler [WEAK]\r
- B .\r
- ENDP\r
-BusFault_Handler\\r
- PROC\r
- EXPORT BusFault_Handler [WEAK]\r
- B .\r
- ENDP\r
-UsageFault_Handler\\r
- PROC\r
- EXPORT UsageFault_Handler [WEAK]\r
- B .\r
- ENDP\r
-SVC_Handler PROC\r
- EXPORT SVC_Handler [WEAK]\r
- B .\r
- ENDP\r
-DebugMon_Handler\\r
- PROC\r
- EXPORT DebugMon_Handler [WEAK]\r
- B .\r
- ENDP\r
-PendSV_Handler PROC\r
- EXPORT PendSV_Handler [WEAK]\r
- B .\r
- ENDP\r
-SysTick_Handler PROC\r
- EXPORT SysTick_Handler [WEAK]\r
- B .\r
- ENDP\r
-
-;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
-
-;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
-
-;* IRQ Handlers */
- EXPORT SCU_0_IRQHandler [WEAK]
- EXPORT ERU0_0_IRQHandler [WEAK]
- EXPORT ERU0_1_IRQHandler [WEAK]
- EXPORT ERU0_2_IRQHandler [WEAK]
- EXPORT ERU0_3_IRQHandler [WEAK]
- EXPORT ERU1_0_IRQHandler [WEAK]
- EXPORT ERU1_1_IRQHandler [WEAK]
- EXPORT ERU1_2_IRQHandler [WEAK]
- EXPORT ERU1_3_IRQHandler [WEAK]
- EXPORT PMU0_0_IRQHandler [WEAK]
- EXPORT VADC0_C0_0_IRQHandler [WEAK]
- EXPORT VADC0_C0_1_IRQHandler [WEAK]
- EXPORT VADC0_C0_2_IRQHandler [WEAK]
- EXPORT VADC0_C0_3_IRQHandler [WEAK]
- EXPORT VADC0_G0_0_IRQHandler [WEAK]
- EXPORT VADC0_G0_1_IRQHandler [WEAK]
- EXPORT VADC0_G0_2_IRQHandler [WEAK]
- EXPORT VADC0_G0_3_IRQHandler [WEAK]
- EXPORT VADC0_G1_0_IRQHandler [WEAK]
- EXPORT VADC0_G1_1_IRQHandler [WEAK]
- EXPORT VADC0_G1_2_IRQHandler [WEAK]
- EXPORT VADC0_G1_3_IRQHandler [WEAK]
- EXPORT VADC0_G2_0_IRQHandler [WEAK]
- EXPORT VADC0_G2_1_IRQHandler [WEAK]
- EXPORT VADC0_G2_2_IRQHandler [WEAK]
- EXPORT VADC0_G2_3_IRQHandler [WEAK]
- EXPORT VADC0_G3_0_IRQHandler [WEAK]
- EXPORT VADC0_G3_1_IRQHandler [WEAK]
- EXPORT VADC0_G3_2_IRQHandler [WEAK]
- EXPORT VADC0_G3_3_IRQHandler [WEAK]
- EXPORT DSD0_0_IRQHandler [WEAK]
- EXPORT DSD0_1_IRQHandler [WEAK]
- EXPORT DSD0_2_IRQHandler [WEAK]
- EXPORT DSD0_3_IRQHandler [WEAK]
- EXPORT DSD0_4_IRQHandler [WEAK]
- EXPORT DSD0_5_IRQHandler [WEAK]
- EXPORT DSD0_6_IRQHandler [WEAK]
- EXPORT DSD0_7_IRQHandler [WEAK]
- EXPORT DAC0_0_IRQHandler [WEAK]
- EXPORT DAC0_1_IRQHandler [WEAK]
- EXPORT CCU40_0_IRQHandler [WEAK]
- EXPORT CCU40_1_IRQHandler [WEAK]
- EXPORT CCU40_2_IRQHandler [WEAK]
- EXPORT CCU40_3_IRQHandler [WEAK]
- EXPORT CCU41_0_IRQHandler [WEAK]
- EXPORT CCU41_1_IRQHandler [WEAK]
- EXPORT CCU41_2_IRQHandler [WEAK]
- EXPORT CCU41_3_IRQHandler [WEAK]
- EXPORT CCU42_0_IRQHandler [WEAK]
- EXPORT CCU42_1_IRQHandler [WEAK]
- EXPORT CCU42_2_IRQHandler [WEAK]
- EXPORT CCU42_3_IRQHandler [WEAK]
- EXPORT CCU43_0_IRQHandler [WEAK]
- EXPORT CCU43_1_IRQHandler [WEAK]
- EXPORT CCU43_2_IRQHandler [WEAK]
- EXPORT CCU43_3_IRQHandler [WEAK]
- EXPORT CCU80_0_IRQHandler [WEAK]
- EXPORT CCU80_1_IRQHandler [WEAK]
- EXPORT CCU80_2_IRQHandler [WEAK]
- EXPORT CCU80_3_IRQHandler [WEAK]
- EXPORT CCU81_0_IRQHandler [WEAK]
- EXPORT CCU81_1_IRQHandler [WEAK]
- EXPORT CCU81_2_IRQHandler [WEAK]
- EXPORT CCU81_3_IRQHandler [WEAK]
- EXPORT POSIF0_0_IRQHandler [WEAK]
- EXPORT POSIF0_1_IRQHandler [WEAK]
- EXPORT POSIF1_0_IRQHandler [WEAK]
- EXPORT POSIF1_1_IRQHandler [WEAK]
- EXPORT CAN0_0_IRQHandler [WEAK]
- EXPORT CAN0_1_IRQHandler [WEAK]
- EXPORT CAN0_2_IRQHandler [WEAK]
- EXPORT CAN0_3_IRQHandler [WEAK]
- EXPORT CAN0_4_IRQHandler [WEAK]
- EXPORT CAN0_5_IRQHandler [WEAK]
- EXPORT CAN0_6_IRQHandler [WEAK]
- EXPORT CAN0_7_IRQHandler [WEAK]
- EXPORT USIC0_0_IRQHandler [WEAK]
- EXPORT USIC0_1_IRQHandler [WEAK]
- EXPORT USIC0_2_IRQHandler [WEAK]
- EXPORT USIC0_3_IRQHandler [WEAK]
- EXPORT USIC0_4_IRQHandler [WEAK]
- EXPORT USIC0_5_IRQHandler [WEAK]
- EXPORT USIC1_0_IRQHandler [WEAK]
- EXPORT USIC1_1_IRQHandler [WEAK]
- EXPORT USIC1_2_IRQHandler [WEAK]
- EXPORT USIC1_3_IRQHandler [WEAK]
- EXPORT USIC1_4_IRQHandler [WEAK]
- EXPORT USIC1_5_IRQHandler [WEAK]
- EXPORT USIC2_0_IRQHandler [WEAK]
- EXPORT USIC2_1_IRQHandler [WEAK]
- EXPORT USIC2_2_IRQHandler [WEAK]
- EXPORT USIC2_3_IRQHandler [WEAK]
- EXPORT USIC2_4_IRQHandler [WEAK]
- EXPORT USIC2_5_IRQHandler [WEAK]
- EXPORT LEDTS0_0_IRQHandler [WEAK]
- EXPORT FCE0_0_IRQHandler [WEAK]
- EXPORT GPDMA0_0_IRQHandler [WEAK]
- EXPORT SDMMC0_0_IRQHandler [WEAK]
- EXPORT USB0_0_IRQHandler [WEAK]
- EXPORT ETH0_0_IRQHandler [WEAK]
- EXPORT GPDMA1_0_IRQHandler [WEAK]\r
-\r
-
-SCU_0_IRQHandler
-ERU0_0_IRQHandler
-ERU0_1_IRQHandler
-ERU0_2_IRQHandler
-ERU0_3_IRQHandler
-ERU1_0_IRQHandler
-ERU1_1_IRQHandler
-ERU1_2_IRQHandler
-ERU1_3_IRQHandler
-PMU0_0_IRQHandler
-VADC0_C0_0_IRQHandler
-VADC0_C0_1_IRQHandler
-VADC0_C0_2_IRQHandler
-VADC0_C0_3_IRQHandler
-VADC0_G0_0_IRQHandler
-VADC0_G0_1_IRQHandler
-VADC0_G0_2_IRQHandler
-VADC0_G0_3_IRQHandler
-VADC0_G1_0_IRQHandler
-VADC0_G1_1_IRQHandler
-VADC0_G1_2_IRQHandler
-VADC0_G1_3_IRQHandler
-VADC0_G2_0_IRQHandler
-VADC0_G2_1_IRQHandler
-VADC0_G2_2_IRQHandler
-VADC0_G2_3_IRQHandler
-VADC0_G3_0_IRQHandler
-VADC0_G3_1_IRQHandler
-VADC0_G3_2_IRQHandler
-VADC0_G3_3_IRQHandler
-DSD0_0_IRQHandler
-DSD0_1_IRQHandler
-DSD0_2_IRQHandler
-DSD0_3_IRQHandler
-DSD0_4_IRQHandler
-DSD0_5_IRQHandler
-DSD0_6_IRQHandler
-DSD0_7_IRQHandler
-DAC0_0_IRQHandler
-DAC0_1_IRQHandler
-CCU40_0_IRQHandler
-CCU40_1_IRQHandler
-CCU40_2_IRQHandler
-CCU40_3_IRQHandler
-CCU41_0_IRQHandler
-CCU41_1_IRQHandler
-CCU41_2_IRQHandler
-CCU41_3_IRQHandler
-CCU42_0_IRQHandler
-CCU42_1_IRQHandler
-CCU42_2_IRQHandler
-CCU42_3_IRQHandler
-CCU43_0_IRQHandler
-CCU43_1_IRQHandler
-CCU43_2_IRQHandler
-CCU43_3_IRQHandler
-CCU80_0_IRQHandler
-CCU80_1_IRQHandler
-CCU80_2_IRQHandler
-CCU80_3_IRQHandler
-CCU81_0_IRQHandler
-CCU81_1_IRQHandler
-CCU81_2_IRQHandler
-CCU81_3_IRQHandler
-POSIF0_0_IRQHandler
-POSIF0_1_IRQHandler
-POSIF1_0_IRQHandler
-POSIF1_1_IRQHandler
-CAN0_0_IRQHandler
-CAN0_1_IRQHandler
-CAN0_2_IRQHandler
-CAN0_3_IRQHandler
-CAN0_4_IRQHandler
-CAN0_5_IRQHandler
-CAN0_6_IRQHandler
-CAN0_7_IRQHandler
-USIC0_0_IRQHandler
-USIC0_1_IRQHandler
-USIC0_2_IRQHandler
-USIC0_3_IRQHandler
-USIC0_4_IRQHandler
-USIC0_5_IRQHandler
-USIC1_0_IRQHandler
-USIC1_1_IRQHandler
-USIC1_2_IRQHandler
-USIC1_3_IRQHandler
-USIC1_4_IRQHandler
-USIC1_5_IRQHandler
-USIC2_0_IRQHandler
-USIC2_1_IRQHandler
-USIC2_2_IRQHandler
-USIC2_3_IRQHandler
-USIC2_4_IRQHandler
-USIC2_5_IRQHandler
-LEDTS0_0_IRQHandler
-FCE0_0_IRQHandler
-GPDMA0_0_IRQHandler
-SDMMC0_0_IRQHandler
-USB0_0_IRQHandler
-ETH0_0_IRQHandler
-GPDMA1_0_IRQHandler \r
-
-
-;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
-
-;* Definition of the default weak SystemInit_DAVE3 function.
-;* This function will be called by the CMSIS SystemInit function.
-;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3
-;* which will overule this weak definition
-
-;*SystemInit_DAVE3
-;* NOP
-;* BX LR
-
+\r
+\r
+\r
+\r
+;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */\r
+\r
+\r
+\r
+;/* Default exception Handlers - Users may override this default functionality by\r
+; defining handlers of the same name in their C code */\r
+\r
+ ExcpHandler NMI_Handler\r
+ ExcpHandler HardFault_Handler\r
+ ExcpHandler MemManage_Handler\r
+ ExcpHandler BusFault_Handler\r
+ ExcpHandler UsageFault_Handler\r
+ ExcpHandler SVC_Handler\r
+ ExcpHandler DebugMon_Handler\r
+ ExcpHandler PendSV_Handler\r
+ ExcpHandler SysTick_Handler\r
+\r
+;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */\r
+\r
+;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */\r
+\r
+;* IRQ Handlers */\r
+ ExcpHandler SCU_0_IRQHandler\r
+ ExcpHandler ERU0_0_IRQHandler\r
+ ExcpHandler ERU0_1_IRQHandler\r
+ ExcpHandler ERU0_2_IRQHandler\r
+ ExcpHandler ERU0_3_IRQHandler\r
+ ExcpHandler ERU1_0_IRQHandler\r
+ ExcpHandler ERU1_1_IRQHandler\r
+ ExcpHandler ERU1_2_IRQHandler\r
+ ExcpHandler ERU1_3_IRQHandler\r
+ ExcpHandler PMU0_0_IRQHandler\r
+ ExcpHandler VADC0_C0_0_IRQHandler\r
+ ExcpHandler VADC0_C0_1_IRQHandler\r
+ ExcpHandler VADC0_C0_2_IRQHandler\r
+ ExcpHandler VADC0_C0_3_IRQHandler\r
+ ExcpHandler VADC0_G0_0_IRQHandler\r
+ ExcpHandler VADC0_G0_1_IRQHandler\r
+ ExcpHandler VADC0_G0_2_IRQHandler\r
+ ExcpHandler VADC0_G0_3_IRQHandler\r
+ ExcpHandler VADC0_G1_0_IRQHandler\r
+ ExcpHandler VADC0_G1_1_IRQHandler\r
+ ExcpHandler VADC0_G1_2_IRQHandler\r
+ ExcpHandler VADC0_G1_3_IRQHandler\r
+ ExcpHandler VADC0_G2_0_IRQHandler\r
+ ExcpHandler VADC0_G2_1_IRQHandler\r
+ ExcpHandler VADC0_G2_2_IRQHandler\r
+ ExcpHandler VADC0_G2_3_IRQHandler\r
+ ExcpHandler VADC0_G3_0_IRQHandler\r
+ ExcpHandler VADC0_G3_1_IRQHandler\r
+ ExcpHandler VADC0_G3_2_IRQHandler\r
+ ExcpHandler VADC0_G3_3_IRQHandler\r
+ ExcpHandler DSD0_0_IRQHandler\r
+ ExcpHandler DSD0_1_IRQHandler\r
+ ExcpHandler DSD0_2_IRQHandler\r
+ ExcpHandler DSD0_3_IRQHandler\r
+ ExcpHandler DSD0_4_IRQHandler\r
+ ExcpHandler DSD0_5_IRQHandler\r
+ ExcpHandler DSD0_6_IRQHandler\r
+ ExcpHandler DSD0_7_IRQHandler\r
+ ExcpHandler DAC0_0_IRQHandler\r
+ ExcpHandler DAC0_1_IRQHandler\r
+ ExcpHandler CCU40_0_IRQHandler\r
+ ExcpHandler CCU40_1_IRQHandler\r
+ ExcpHandler CCU40_2_IRQHandler\r
+ ExcpHandler CCU40_3_IRQHandler\r
+ ExcpHandler CCU41_0_IRQHandler\r
+ ExcpHandler CCU41_1_IRQHandler\r
+ ExcpHandler CCU41_2_IRQHandler\r
+ ExcpHandler CCU41_3_IRQHandler\r
+ ExcpHandler CCU42_0_IRQHandler\r
+ ExcpHandler CCU42_1_IRQHandler\r
+ ExcpHandler CCU42_2_IRQHandler\r
+ ExcpHandler CCU42_3_IRQHandler\r
+ ExcpHandler CCU43_0_IRQHandler\r
+ ExcpHandler CCU43_1_IRQHandler\r
+ ExcpHandler CCU43_2_IRQHandler\r
+ ExcpHandler CCU43_3_IRQHandler\r
+ ExcpHandler CCU80_0_IRQHandler\r
+ ExcpHandler CCU80_1_IRQHandler\r
+ ExcpHandler CCU80_2_IRQHandler\r
+ ExcpHandler CCU80_3_IRQHandler\r
+ ExcpHandler CCU81_0_IRQHandler\r
+ ExcpHandler CCU81_1_IRQHandler\r
+ ExcpHandler CCU81_2_IRQHandler\r
+ ExcpHandler CCU81_3_IRQHandler\r
+ ExcpHandler POSIF0_0_IRQHandler\r
+ ExcpHandler POSIF0_1_IRQHandler\r
+ ExcpHandler POSIF1_0_IRQHandler\r
+ ExcpHandler POSIF1_1_IRQHandler\r
+ ExcpHandler CAN0_0_IRQHandler\r
+ ExcpHandler CAN0_1_IRQHandler\r
+ ExcpHandler CAN0_2_IRQHandler\r
+ ExcpHandler CAN0_3_IRQHandler\r
+ ExcpHandler CAN0_4_IRQHandler\r
+ ExcpHandler CAN0_5_IRQHandler\r
+ ExcpHandler CAN0_6_IRQHandler\r
+ ExcpHandler CAN0_7_IRQHandler\r
+ ExcpHandler USIC0_0_IRQHandler\r
+ ExcpHandler USIC0_1_IRQHandler\r
+ ExcpHandler USIC0_2_IRQHandler\r
+ ExcpHandler USIC0_3_IRQHandler\r
+ ExcpHandler USIC0_4_IRQHandler\r
+ ExcpHandler USIC0_5_IRQHandler\r
+ ExcpHandler USIC1_0_IRQHandler\r
+ ExcpHandler USIC1_1_IRQHandler\r
+ ExcpHandler USIC1_2_IRQHandler\r
+ ExcpHandler USIC1_3_IRQHandler\r
+ ExcpHandler USIC1_4_IRQHandler\r
+ ExcpHandler USIC1_5_IRQHandler\r
+ ExcpHandler USIC2_0_IRQHandler\r
+ ExcpHandler USIC2_1_IRQHandler\r
+ ExcpHandler USIC2_2_IRQHandler\r
+ ExcpHandler USIC2_3_IRQHandler\r
+ ExcpHandler USIC2_4_IRQHandler\r
+ ExcpHandler USIC2_5_IRQHandler\r
+ ExcpHandler LEDTS0_0_IRQHandler\r
+ ExcpHandler FCE0_0_IRQHandler\r
+ ExcpHandler GPDMA0_0_IRQHandler\r
+ ExcpHandler SDMMC0_0_IRQHandler\r
+ ExcpHandler USB0_0_IRQHandler\r
+ ExcpHandler ETH0_0_IRQHandler\r
+ ExcpHandler GPDMA1_0_IRQHandler\r
+\r
+;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */\r
+\r
+;* Definition of the default weak SystemInit_DAVE3 function.\r
+;* This function will be called by the CMSIS SystemInit function.\r
+;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3\r
+;* which will overule this weak definition\r
+SystemInit_DAVE3 PROC\r
+ EXPORT SystemInit_DAVE3 [WEAK]\r
+ NOP\r
+ BX LR\r
+ ENDP\r
+\r
+;* Definition of the default weak DAVE3 function for clock App usage.\r
+;* AllowPLLInitByStartup Handler */\r
+AllowPLLInitByStartup PROC\r
+ EXPORT AllowPLLInitByStartup [WEAK]\r
+ MOV R0,#1\r
+ BX LR\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
;*******************************************************************************\r
; User Stack and Heap initialization\r
;*******************************************************************************\r
- IF :DEF:__MICROLIB \r
- \r
+ IF :DEF:__MICROLIB\r
+\r
EXPORT __initial_sp\r
EXPORT __heap_base\r
EXPORT __heap_limit\r
- \r
+\r
ELSE\r
- \r
+\r
IMPORT __use_two_region_memory\r
EXPORT __user_initial_stackheap\r
- \r
+\r
__user_initial_stackheap\r
\r
LDR R0, = Heap_Mem\r
LDR R3, = Stack_Mem\r
BX LR\r
\r
+ ALIGN\r
\r
ENDIF\r
\r
- ALIGN\r
END\r
\r
-;******************* (C) COPYRIGHT 2011 Infineon Techonlogies *****END OF FILE*****\r
-\r
-
+;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE*****\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_XMC4200.c\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
+ * for the Infineon XMC4000 Device Series\r
+ * @version V3.0.1 Alpha\r
+ * @date 26. September 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <system_XMC4200.h>\r
+#include <XMC4200.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+/* clock definitions, do not modify! */\r
+#define SCU_CLOCK_CRYSTAL 1\r
+#define SCU_CLOCK_BACK_UP_FACTORY 2\r
+#define SCU_CLOCK_BACK_UP_AUTOMATIC 3\r
+\r
+\r
+#define HIB_CLOCK_FOSI 1\r
+#define HIB_CLOCK_OSCULP 2\r
+\r
+\r
+\r
+\r
+/*\r
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+*/\r
+\r
+\r
+\r
+/*--------------------- Watchdog Configuration -------------------------------\r
+//\r
+// <e> Watchdog Configuration\r
+// <o1.0> Disable Watchdog\r
+//\r
+// </e>\r
+*/\r
+#define WDT_SETUP 1\r
+#define WDTENB_nVal 0x00000001\r
+\r
+/*--------------------- CLOCK Configuration -------------------------------\r
+//\r
+// <e> Main Clock Configuration\r
+// <o1.0..1> CPU clock divider\r
+// <0=> fCPU = fSYS\r
+// <1=> fCPU = fSYS / 2\r
+// <o2.0..1> Peripheral Bus clock divider\r
+// <0=> fPB = fCPU\r
+// <1=> fPB = fCPU / 2\r
+// <o3.0..1> CCU Bus clock divider\r
+// <0=> fCCU = fCPU\r
+// <1=> fCCU = fCPU / 2\r
+//\r
+// </e>\r
+//\r
+*/\r
+\r
+#define SCU_CLOCK_SETUP 1\r
+#define SCU_CPUCLKCR_DIV 0x00000000\r
+#define SCU_PBCLKCR_DIV 0x00000000\r
+#define SCU_CCUCLKCR_DIV 0x00000000\r
+/* not avalible in config wizzard*/\r
+/*\r
+* mandatory clock parameters **************************************************\r
+*\r
+* source for clock generation\r
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)\r
+*\r
+**************************************************************************************/\r
+// Selection of imput lock for PLL\r
+/*************************************************************************************/\r
+#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC\r
+\r
+/*************************************************************************************/\r
+// Standby clock selection for Backup clock source trimming\r
+/*************************************************************************************/\r
+#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP\r
+//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI\r
+\r
+/*************************************************************************************/\r
+// Global clock parameters\r
+/*************************************************************************************/\r
+#define CLOCK_FSYS 80000000\r
+#define CLOCK_CRYSTAL_FREQUENCY 12000000\r
+#define CLOCK_BACK_UP 24000000\r
+\r
+/*************************************************************************************/\r
+/* OSC_HP setup parameters */\r
+/*************************************************************************************/\r
+#define SCU_OSC_HP_MODE 0xF0\r
+#define SCU_OSCHPWDGDIV 2\r
+\r
+/*************************************************************************************/\r
+/* MAIN PLL setup parameters */\r
+/*************************************************************************************/\r
+//Divider settings for external crystal @ 12 MHz\r
+/*************************************************************************************/\r
+#define SCU_PLL_K1DIV 1\r
+#define SCU_PLL_K1DIV 1\r
+#define SCU_PLL_K2DIV 5\r
+#define SCU_PLL_PDIV 1\r
+#define SCU_PLL_NDIV 79\r
+\r
+/*************************************************************************************/\r
+//Divider settings for use of backup clock source trimmed\r
+/*************************************************************************************/\r
+//#define SCU_PLL_K1DIV 1\r
+//#define SCU_PLL_K2DIV 5\r
+//#define SCU_PLL_PDIV 3\r
+//#define SCU_PLL_NDIV 79\r
+/*************************************************************************************/\r
+\r
+\r
+/*--------------------- USB CLOCK Configuration ---------------------------\r
+//\r
+// <e> USB Clock Configuration\r
+//\r
+// </e>\r
+//\r
+*/\r
+\r
+#define SCU_USB_CLOCK_SETUP 0\r
+/* not avalible in config wizzard*/\r
+#define SCU_USBPLL_PDIV 0\r
+#define SCU_USBPLL_NDIV 31\r
+#define SCU_USBDIV 3\r
+\r
+/*--------------------- Flash Wait State Configuration -------------------------------\r
+//\r
+// <e> Flash Wait State Configuration\r
+// <o1.0..3> Flash Wait State\r
+// <0=> 3 WS\r
+// <1=> 4 WS\r
+// <2=> 5 WS\r
+// <3=> 6 WS\r
+// </e>\r
+//\r
+*/\r
+\r
+#define PMU_FLASH 1\r
+#define PMU_FLASH_WS 0x00000000\r
+\r
+\r
+/*--------------------- CLOCKOUT Configuration -------------------------------\r
+//\r
+// <e> Clock OUT Configuration\r
+// <o1.0..1> Clockout Source Selection\r
+// <0=> System Clock\r
+// <2=> Divided value of USB PLL output\r
+// <3=> Divided value of PLL Clock\r
+// <o2.0..4> Clockout divider <1-10><#-1>\r
+// <o3.0..1> Clockout Pin Selection\r
+// <0=> P1.15\r
+// <1=> P0.8\r
+//\r
+//\r
+// </e>\r
+//\r
+*/\r
+\r
+#define SCU_CLOCKOUT_SETUP 0\r
+#define SCU_CLOCKOUT_SOURCE 0x00000000\r
+#define SCU_CLOCKOUT_DIV 0x00000009\r
+#define SCU_CLOCKOUT_PIN 0x00000001\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+#if SCU_CLOCK_SETUP\r
+uint32_t SystemCoreClock = CLOCK_FSYS;\r
+#else\r
+uint32_t SystemCoreClock = CLOCK_BACK_UP;\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ static functions declarations\r
+ *----------------------------------------------------------------------------*/\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void);\r
+#endif\r
+\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void);\r
+#endif\r
+\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the PLL and update the\r
+ * SystemCoreClock variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+int temp;\r
+\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */\r
+ (3UL << 11*2) ); /* set CP11 Full Access */\r
+#endif\r
+\r
+/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */\r
+SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);\r
+\r
+/* Setup the WDT */\r
+#if WDT_SETUP\r
+\r
+WDT->CTR &= ~WDTENB_nVal;\r
+\r
+#endif\r
+\r
+\r
+/* Setup the Flash Wait State */\r
+#if PMU_FLASH\r
+temp = FLASH0->FCON;\r
+temp &= ~FLASH_FCON_WSPFLASH_Msk;\r
+temp |= PMU_FLASH_WS+3;\r
+FLASH0->FCON = temp;\r
+#endif\r
+\r
+\r
+/* Setup the clockout */\r
+#if SCU_CLOCKOUT_SETUP\r
+\r
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;\r
+/*set PLL div for clkout */\r
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;\r
+\r
+if (SCU_CLOCKOUT_PIN) {\r
+ PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */\r
+ PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
+ PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */\r
+ }\r
+else {\r
+ PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */\r
+ PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */\r
+ }\r
+\r
+#endif\r
+\r
+\r
+/* Setup the System clock */\r
+#if SCU_CLOCK_SETUP\r
+SystemClockSetup();\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
+/* Setup the USB PL */\r
+#if SCU_USB_CLOCK_SETUP\r
+USBClockSetup();\r
+#endif\r
+\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note -\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+unsigned int PDIV;\r
+unsigned int NDIV;\r
+unsigned int K2DIV;\r
+unsigned int long VCO;\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+if (SCU_CLK->SYSCLKCR == 0x00010000)\r
+{\r
+ if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){\r
+ /* check if PLL is locked */\r
+ /* read back divider settings */\r
+ PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;\r
+ NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;\r
+ K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;\r
+\r
+ if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){\r
+ /* the selected clock is the Backup clock fofi */\r
+ VCO = (CLOCK_BACK_UP/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+\r
+ }\r
+ else\r
+ {\r
+ /* the selected clock is the PLL external oscillator */\r
+ VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+ }\r
+\r
+\r
+ }\r
+}\r
+else\r
+{\r
+SystemCoreClock = CLOCK_BACK_UP;\r
+}\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief -\r
+ * @note -\r
+ * @param None\r
+ * @retval None\r
+ */\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void)\r
+{\r
+int temp;\r
+unsigned int long VCO;\r
+int stepping_K2DIV;\r
+\r
+/* this weak function enables DAVE3 clock App usage */\r
+if(AllowPLLInitByStartup()){\r
+\r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+/* enable PLL first */\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+\r
+}\r
+\r
+/* Enable OSC_HP if not already on*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use external crystal for PLL clock input */\r
+ /********************************************************************************************************************/\r
+\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
+ /* setup OSC WDG devider */\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);\r
+ /* select external OSC as PLL input */\r
+ SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ /* restart OSC Watchdog */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;\r
+\r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ do\r
+ {\r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));\r
+\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
+\r
+ }\r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use factory trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+\r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use automatic trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* check for HIB Domain enabled */\r
+ if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)\r
+ SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/\r
+\r
+ /* check for HIB Domain is not in reset state */\r
+ if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)\r
+ SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/\r
+\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+\r
+ if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fOSI as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ }\r
+ else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fULP as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ /*check OSCUL if running correct*/\r
+ if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)\r
+ {\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);\r
+\r
+ SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/\r
+ /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/\r
+ /* select OSCUL clock for RTC*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*enable OSCULP WDG Alarm Enable*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*wait now for clock is stable */\r
+ do\r
+ {\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ }\r
+ while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);\r
+\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ }\r
+ // now OSCULP is running and can be used\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+ }\r
+ }\r
+\r
+ /********************************************************************************************************************/\r
+ /* Setup and look the main PLL */\r
+ /********************************************************************************************************************/\r
+\r
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){\r
+ /* Systen is still running from internal clock */\r
+ /* select FOFI as system clock */\r
+ if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/\r
+\r
+\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+ stepping_K2DIV = (VCO/24000000)-1;\r
+ /* Go to bypass the Main PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ /* disconnect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ /* we may have to set OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+ /* connect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* restart PLL Lock detection */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
+ /* wait for PLL Lock */\r
+ /* setup time out loop */\r
+ /* Timeout for wait loo ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+\r
+ while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+\r
+ if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)\r
+ {\r
+ /* Go back to the Main PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ }\r
+ else return(0);\r
+\r
+\r
+ /*********************************************************\r
+ here we need to setup the system clock divider\r
+ *********************************************************/\r
+\r
+ SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
+ SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;\r
+ SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
+\r
+\r
+ /* Switch system clock to PLL */\r
+ SCU_CLK->SYSCLKCR |= 0x00010000;\r
+\r
+ /* we may have to reset OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+\r
+\r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+\r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /*********************************************************/\r
+\r
+ /*********************************************************\r
+ here the ramp up of the system clock starts FSys < 60MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 60000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+ stepping_K2DIV = (VCO/60000000)-1;\r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+\r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+\r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+\r
+ /*********************************************************\r
+ here the ramp up of the system clock starts FSys < 90MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 90000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+ stepping_K2DIV = (VCO/90000000)-1;\r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+\r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+\r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ }\r
+ }/* end this weak function enables DAVE3 clock App usage */\r
+ return(1);\r
+\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief -\r
+ * @note -\r
+ * @param None\r
+ * @retval None\r
+ */\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void)\r
+{\r
+/* this weak function enables DAVE3 clock App usage */\r
+if(AllowPLLInitByStartup()){\r
+\r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
+}\r
+\r
+/* check and if not already running enable OSC_HP */\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ /* check if Main PLL is switched on for OSC WD*/\r
+ if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+ }\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
+ /* setup OSC WDG devider */\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);\r
+ /* restart OSC Watchdog */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;\r
+\r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ do\r
+ {\r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));\r
+\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
+\r
+ }\r
+\r
+\r
+/* Setup USB PLL */\r
+ /* Go to bypass the Main PLL */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;\r
+ /* disconnect OSC_FI to PLL */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));\r
+ /* Setup USBDIV settings USB clock */\r
+ SCU_CLK->USBCLKCR = SCU_USBDIV;\r
+ /* we may have to set OSCDISCDIS */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
+ /* connect OSC_FI to PLL */\r
+ SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+ /* restart PLL Lock detection */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
+ /* wait for PLL Lock */\r
+ while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
+\r
+ }/* end this weak function enables DAVE3 clock App usage */\r
+ return(1);\r
+\r
+}\r
+#endif\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_XMC4200.h\r
+ * @brief Header file for the XMC4200-Series systeminit\r
+ * \r
+ * @version V1.0\r
+ * @date 27. August 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon\92s microcontrollers. \r
+ * This file can be freely distributed within development tools that are supporting such microcontrollers. \r
+\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __SYSTEM_XMC4200_H\r
+#define __SYSTEM_XMC4200_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System.\r
+ */\r
+extern void SystemInit (void);\r
+\r
+\r
+/**\r
+ * Update SystemCoreClock variable\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Updates the SystemCoreClock with current core Clock\r
+ * retrieved from cpu registers.\r
+ */\r
+extern void SystemCoreClockUpdate (void);\r
+\r
+/* this weak function enables DAVE3 clock App usage */ \r
+extern uint32_t AllowPLLInitByStartup(void); \r
+ \r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_XMC4400.c\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
+ * for the Infineon XMC4500 Device Series\r
+ * @version V3.0.1 Alpha\r
+ * @date 17. September 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <system_XMC4400.h>\r
+#include <XMC4400.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+/* clock definitions, do not modify! */\r
+#define SCU_CLOCK_CRYSTAL 1\r
+#define SCU_CLOCK_BACK_UP_FACTORY 2\r
+#define SCU_CLOCK_BACK_UP_AUTOMATIC 3\r
+\r
+\r
+#define HIB_CLOCK_FOSI 1\r
+#define HIB_CLOCK_OSCULP 2\r
+\r
+\r
+\r
+\r
+/*\r
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+*/\r
+\r
+\r
+\r
+/*--------------------- Watchdog Configuration -------------------------------\r
+//\r
+// <e> Watchdog Configuration\r
+// <o1.0> Disable Watchdog\r
+//\r
+// </e>\r
+*/\r
+#define WDT_SETUP 1\r
+#define WDTENB_nVal 0x00000001\r
+\r
+/*--------------------- CLOCK Configuration -------------------------------\r
+//\r
+// <e> Main Clock Configuration\r
+// <o1.0..1> CPU clock divider\r
+// <0=> fCPU = fSYS\r
+// <1=> fCPU = fSYS / 2\r
+// <o2.0..1> Peripheral Bus clock divider\r
+// <0=> fPB = fCPU\r
+// <1=> fPB = fCPU / 2\r
+// <o3.0..1> CCU Bus clock divider\r
+// <0=> fCCU = fCPU\r
+// <1=> fCCU = fCPU / 2\r
+//\r
+// </e>\r
+//\r
+*/\r
+\r
+#define SCU_CLOCK_SETUP 1\r
+#define SCU_CPUCLKCR_DIV 0x00000000\r
+#define SCU_PBCLKCR_DIV 0x00000000\r
+#define SCU_CCUCLKCR_DIV 0x00000000\r
+/* not avalible in config wizzard*/\r
+/*\r
+* mandatory clock parameters **************************************************\r
+*\r
+* source for clock generation\r
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)\r
+*\r
+**************************************************************************************/\r
+// Selection of imput lock for PLL\r
+/*************************************************************************************/\r
+#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC\r
+\r
+/*************************************************************************************/\r
+// Standby clock selection for Backup clock source trimming\r
+/*************************************************************************************/\r
+#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP\r
+//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI\r
+\r
+/*************************************************************************************/\r
+// Global clock parameters\r
+/*************************************************************************************/\r
+#define CLOCK_FSYS 120000000\r
+#define CLOCK_CRYSTAL_FREQUENCY 12000000\r
+#define CLOCK_BACK_UP 24000000\r
+\r
+/*************************************************************************************/\r
+/* OSC_HP setup parameters */\r
+/*************************************************************************************/\r
+#define SCU_OSC_HP_MODE 0xF0\r
+#define SCU_OSCHPWDGDIV 2\r
+\r
+/*************************************************************************************/\r
+/* MAIN PLL setup parameters */\r
+/*************************************************************************************/\r
+//Divider settings for external crystal @ 12 MHz\r
+/*************************************************************************************/\r
+#define SCU_PLL_K1DIV 1\r
+#define SCU_PLL_K2DIV 3\r
+#define SCU_PLL_PDIV 1\r
+#define SCU_PLL_NDIV 79\r
+\r
+/*************************************************************************************/\r
+//Divider settings for use of backup clock source trimmed\r
+/*************************************************************************************/\r
+//#define SCU_PLL_K1DIV 1\r
+//#define SCU_PLL_K2DIV 3\r
+//#define SCU_PLL_PDIV 3\r
+//#define SCU_PLL_NDIV 79\r
+/*************************************************************************************/\r
+\r
+\r
+/*--------------------- USB CLOCK Configuration ---------------------------\r
+//\r
+// <e> USB Clock Configuration\r
+//\r
+// </e>\r
+//\r
+*/\r
+\r
+#define SCU_USB_CLOCK_SETUP 0\r
+/* not avalible in config wizzard*/\r
+#define SCU_USBPLL_PDIV 0\r
+#define SCU_USBPLL_NDIV 31\r
+#define SCU_USBDIV 3\r
+\r
+/*--------------------- Flash Wait State Configuration -------------------------------\r
+//\r
+// <e> Flash Wait State Configuration\r
+// <o1.0..3> Flash Wait State\r
+// <0=> 3 WS\r
+// <1=> 4 WS\r
+// <2=> 5 WS\r
+// <3=> 6 WS\r
+// </e>\r
+//\r
+*/\r
+\r
+#define PMU_FLASH 1\r
+#define PMU_FLASH_WS 0x00000000\r
+\r
+\r
+/*--------------------- CLOCKOUT Configuration -------------------------------\r
+//\r
+// <e> Clock OUT Configuration\r
+// <o1.0..1> Clockout Source Selection\r
+// <0=> System Clock\r
+// <2=> Divided value of USB PLL output\r
+// <3=> Divided value of PLL Clock\r
+// <o2.0..4> Clockout divider <1-10><#-1>\r
+// <o3.0..1> Clockout Pin Selection\r
+// <0=> P1.15\r
+// <1=> P0.8\r
+//\r
+//\r
+// </e>\r
+//\r
+*/\r
+\r
+#define SCU_CLOCKOUT_SETUP 0\r
+#define SCU_CLOCKOUT_SOURCE 0x00000000\r
+#define SCU_CLOCKOUT_DIV 0x00000009\r
+#define SCU_CLOCKOUT_PIN 0x00000001\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+#if SCU_CLOCK_SETUP\r
+uint32_t SystemCoreClock = CLOCK_FSYS;\r
+#else\r
+uint32_t SystemCoreClock = CLOCK_BACK_UP;\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ static functions declarations\r
+ *----------------------------------------------------------------------------*/\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void);\r
+#endif\r
+\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void);\r
+#endif\r
+\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the PLL and update the\r
+ * SystemCoreClock variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+int temp;\r
+\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */\r
+ (3UL << 11*2) ); /* set CP11 Full Access */\r
+#endif\r
+\r
+/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */\r
+SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);\r
+\r
+/* Setup the WDT */\r
+#if WDT_SETUP\r
+\r
+WDT->CTR &= ~WDTENB_nVal;\r
+\r
+#endif\r
+\r
+\r
+/* Setup the Flash Wait State */\r
+#if PMU_FLASH\r
+temp = FLASH0->FCON;\r
+temp &= ~FLASH_FCON_WSPFLASH_Msk;\r
+temp |= PMU_FLASH_WS+3;\r
+FLASH0->FCON = temp;\r
+#endif\r
+\r
+\r
+/* Setup the clockout */\r
+#if SCU_CLOCKOUT_SETUP\r
+\r
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;\r
+/*set PLL div for clkout */\r
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;\r
+\r
+if (SCU_CLOCKOUT_PIN) {\r
+ PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */\r
+ PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
+ PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */\r
+ }\r
+else {\r
+ PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */\r
+ PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */\r
+ }\r
+\r
+#endif\r
+\r
+\r
+/* Setup the System clock */\r
+#if SCU_CLOCK_SETUP\r
+SystemClockSetup();\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
+/* Setup the USB PL */\r
+#if SCU_USB_CLOCK_SETUP\r
+USBClockSetup();\r
+#endif\r
+\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note -\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+unsigned int PDIV;\r
+unsigned int NDIV;\r
+unsigned int K2DIV;\r
+unsigned int long VCO;\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+if (SCU_CLK->SYSCLKCR == 0x00010000)\r
+{\r
+ if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){\r
+ /* check if PLL is locked */\r
+ /* read back divider settings */\r
+ PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;\r
+ NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;\r
+ K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;\r
+\r
+ if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){\r
+ /* the selected clock is the Backup clock fofi */\r
+ VCO = (CLOCK_BACK_UP/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+\r
+ }\r
+ else\r
+ {\r
+ /* the selected clock is the PLL external oscillator */\r
+ VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+ }\r
+\r
+\r
+ }\r
+}\r
+else\r
+{\r
+SystemCoreClock = CLOCK_BACK_UP;\r
+}\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief -\r
+ * @note -\r
+ * @param None\r
+ * @retval None\r
+ */\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void)\r
+{\r
+int temp;\r
+unsigned int long VCO;\r
+int stepping_K2DIV;\r
+\r
+/* this weak function enables DAVE3 clock App usage */\r
+if(AllowPLLInitByStartup()){\r
+\r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+/* enable PLL first */\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+\r
+}\r
+\r
+/* Enable OSC_HP if not already on*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use external crystal for PLL clock input */\r
+ /********************************************************************************************************************/\r
+\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
+ /* setup OSC WDG devider */\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);\r
+ /* select external OSC as PLL input */\r
+ SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ /* restart OSC Watchdog */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;\r
+\r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ do\r
+ {\r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));\r
+\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
+\r
+ }\r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use factory trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+\r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use automatic trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* check for HIB Domain enabled */\r
+ if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)\r
+ SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/\r
+\r
+ /* check for HIB Domain is not in reset state */\r
+ if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)\r
+ SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/\r
+\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+\r
+ if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fOSI as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ }\r
+ else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fULP as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ /*check OSCUL if running correct*/\r
+ if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)\r
+ {\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);\r
+\r
+ SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/\r
+ /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/\r
+ /* select OSCUL clock for RTC*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*enable OSCULP WDG Alarm Enable*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*wait now for clock is stable */\r
+ do\r
+ {\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ }\r
+ while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);\r
+\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ }\r
+ // now OSCULP is running and can be used\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+ }\r
+ }\r
+\r
+ /********************************************************************************************************************/\r
+ /* Setup and look the main PLL */\r
+ /********************************************************************************************************************/\r
+\r
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){\r
+ /* Systen is still running from internal clock */\r
+ /* select FOFI as system clock */\r
+ if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/\r
+\r
+\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+ stepping_K2DIV = (VCO/24000000)-1;\r
+ /* Go to bypass the Main PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ /* disconnect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ /* we may have to set OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+ /* connect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* restart PLL Lock detection */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
+ /* wait for PLL Lock */\r
+ /* setup time out loop */\r
+ /* Timeout for wait loo ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+\r
+ while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+\r
+ if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)\r
+ {\r
+ /* Go back to the Main PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ }\r
+ else return(0);\r
+\r
+\r
+ /*********************************************************\r
+ here we need to setup the system clock divider\r
+ *********************************************************/\r
+\r
+ SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
+ SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;\r
+ SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
+\r
+\r
+ /* Switch system clock to PLL */\r
+ SCU_CLK->SYSCLKCR |= 0x00010000;\r
+\r
+ /* we may have to reset OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+\r
+\r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+\r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /*********************************************************/\r
+\r
+ /*********************************************************\r
+ here the ramp up of the system clock starts FSys < 60MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 60000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+ stepping_K2DIV = (VCO/60000000)-1;\r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+\r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+\r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+\r
+ /*********************************************************\r
+ here the ramp up of the system clock starts FSys < 90MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 90000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+ stepping_K2DIV = (VCO/90000000)-1;\r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+\r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+\r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ }\r
+ }/* end this weak function enables DAVE3 clock App usage */\r
+ return(1);\r
+\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief -\r
+ * @note -\r
+ * @param None\r
+ * @retval None\r
+ */\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void)\r
+{\r
+/* this weak function enables DAVE3 clock App usage */\r
+if(AllowPLLInitByStartup()){\r
+\r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
+}\r
+\r
+/* check and if not already running enable OSC_HP */\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ /* check if Main PLL is switched on for OSC WD*/\r
+ if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+ }\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
+ /* setup OSC WDG devider */\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);\r
+ /* restart OSC Watchdog */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;\r
+\r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ do\r
+ {\r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));\r
+\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
+\r
+ }\r
+\r
+\r
+/* Setup USB PLL */\r
+ /* Go to bypass the Main PLL */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;\r
+ /* disconnect OSC_FI to PLL */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));\r
+ /* Setup USBDIV settings USB clock */\r
+ SCU_CLK->USBCLKCR = SCU_USBDIV;\r
+ /* we may have to set OSCDISCDIS */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
+ /* connect OSC_FI to PLL */\r
+ SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+ /* restart PLL Lock detection */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
+ /* wait for PLL Lock */\r
+ while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
+\r
+ }/* end this weak function enables DAVE3 clock App usage */\r
+ return(1);\r
+\r
+}\r
+#endif\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_XMC4400.h\r
+ * @brief Header file for the XMC4400-Series systeminit\r
+ * \r
+ * @version V1.0\r
+ * @date 17. August 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon\92s microcontrollers. \r
+ * This file can be freely distributed within development tools that are supporting such microcontrollers. \r
+\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __SYSTEM_XMC4400_H\r
+#define __SYSTEM_XMC4400_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System.\r
+ */\r
+extern void SystemInit (void);\r
+\r
+\r
+/**\r
+ * Update SystemCoreClock variable\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Updates the SystemCoreClock with current core Clock\r
+ * retrieved from cpu registers.\r
+ */\r
+extern void SystemCoreClockUpdate (void);\r
+\r
+/* this weak function enables DAVE3 clock App usage */ \r
+extern uint32_t AllowPLLInitByStartup(void); \r
+ \r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif\r
projects / freertos / commitdiff