+++ /dev/null
-/*\r
- FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
- \r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
- * *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
- * *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
- >>>NOTE<<< The modification to the GPL is included to allow you to\r
- distribute a combined work that includes FreeRTOS without being obliged to\r
- provide the source code for proprietary components outside of the FreeRTOS\r
- kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
- more details. You should have received a copy of the GNU General Public\r
- License and the FreeRTOS license exception along with FreeRTOS; if not it\r
- can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
- by writing to Richard Barry, contact details for whom are available on the\r
- FreeRTOS WEB site.\r
-\r
- 1 tab == 4 spaces!\r
-\r
- http://www.FreeRTOS.org - Documentation, latest information, license and\r
- contact details.\r
-\r
- http://www.SafeRTOS.com - A version that is certified for use in safety\r
- critical systems.\r
-\r
- http://www.OpenRTOS.com - Commercial support, development, porting,\r
- licensing and training services.\r
-*/\r
-\r
-\r
-#include <p32xxxx.h>\r
-#include <sys/asm.h>\r
- \r
- .set nomips16\r
- .set noreorder\r
- \r
- \r
- .global vRegTest1\r
- .global vRegTest2\r
-\r
-\r
- #if (__C32_VERSION__ >= 2 )\r
- .section .FreeRTOS, code\r
- #else\r
- .section .FreeRTOS, "ax", @progbits\r
- #endif\r
- .set noreorder\r
- .set noat\r
- .ent vRegTest1\r
-\r
-/* Address of $4 ulStatus1 is held in A0, so don't mess with the value of $4 */\r
-\r
-vRegTest1:\r
- addiu $1, $0, 0x11\r
- addiu $2, $0, 0x12 \r
- addiu $3, $0, 0x13 \r
- addiu $5, $0, 0x15 \r
- addiu $6, $0, 0x16 \r
- addiu $7, $0, 0x17 \r
- addiu $8, $0, 0x18 \r
- addiu $9, $0, 0x19 \r
- addiu $10, $0, 0x110 \r
- addiu $11, $0, 0x111 \r
- addiu $12, $0, 0x112 \r
- addiu $13, $0, 0x113 \r
- addiu $14, $0, 0x114 \r
- addiu $15, $0, 0x115 \r
- addiu $16, $0, 0x116 \r
- addiu $17, $0, 0x117 \r
- addiu $18, $0, 0x118 \r
- addiu $19, $0, 0x119 \r
- addiu $20, $0, 0x120 \r
- addiu $21, $0, 0x121 \r
- addiu $22, $0, 0x122 \r
- addiu $23, $0, 0x123 \r
- addiu $24, $0, 0x124 \r
- addiu $25, $0, 0x125 \r
- addiu $30, $0, 0x130 \r
-\r
- addiu $1, $1, -0x11\r
- beq $1, $0, .+12\r
- nop\r
- sw $0, 0($4) \r
- addiu $2, $2, -0x12 \r
- beq $2, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $3, $3, -0x13 \r
- beq $3, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $5, $5, -0x15 \r
- beq $5, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $6, $6, -0x16 \r
- beq $6, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $7, $7, -0x17 \r
- beq $7, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $8, $8, -0x18 \r
- beq $8, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $9, $9, -0x19 \r
- beq $9, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $10, $10, -0x110 \r
- beq $10, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $11, $11, -0x111 \r
- beq $11, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $12, $12, -0x112 \r
- beq $12, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $13, $13, -0x113 \r
- beq $13, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $14, $14, -0x114 \r
- beq $14, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $15, $15, -0x115 \r
- beq $15, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $16, $16, -0x116 \r
- beq $16, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $17, $17, -0x117 \r
- beq $17, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $18, $18, -0x118 \r
- beq $18, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $19, $19, -0x119 \r
- beq $19, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $20, $20, -0x120 \r
- beq $20, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $21, $21, -0x121 \r
- beq $21, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $22, $22, -0x122 \r
- beq $22, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $23, $23, -0x123 \r
- beq $23, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $24, $24, -0x124 \r
- beq $24, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $25, $25, -0x125 \r
- beq $25, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $30, $30, -0x130 \r
- beq $30, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- jr $31\r
- nop\r
-\r
- .end vRegTest1\r
-\r
-\r
- #if (__C32_VERSION__ >= 2 )\r
- .section .FreeRTOS, code\r
- #else\r
- .section .FreeRTOS, "ax", @progbits\r
- #endif\r
- .set noreorder\r
- .set noat\r
- .ent vRegTest2\r
-\r
-vRegTest2:\r
-\r
- addiu $1, $0, 0x10\r
- addiu $2, $0, 0x20 \r
- addiu $3, $0, 0x30 \r
- addiu $5, $0, 0x50 \r
- addiu $6, $0, 0x60 \r
- addiu $7, $0, 0x70 \r
- addiu $8, $0, 0x80 \r
- addiu $9, $0, 0x90 \r
- addiu $10, $0, 0x100 \r
- addiu $11, $0, 0x110 \r
- addiu $12, $0, 0x120 \r
- addiu $13, $0, 0x130 \r
- addiu $14, $0, 0x140 \r
- addiu $15, $0, 0x150 \r
- addiu $16, $0, 0x160 \r
- addiu $17, $0, 0x170 \r
- addiu $18, $0, 0x180 \r
- addiu $19, $0, 0x190 \r
- addiu $20, $0, 0x200 \r
- addiu $21, $0, 0x210 \r
- addiu $22, $0, 0x220 \r
- addiu $23, $0, 0x230 \r
- addiu $24, $0, 0x240 \r
- addiu $25, $0, 0x250 \r
- addiu $30, $0, 0x300 \r
-\r
- addiu $1, $1, -0x10\r
- beq $1, $0, .+12\r
- nop\r
- sw $0, 0($4) \r
- addiu $2, $2, -0x20 \r
- beq $2, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $3, $3, -0x30 \r
- beq $3, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $5, $5, -0x50 \r
- beq $5, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $6, $6, -0x60 \r
- beq $6, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $7, $7, -0x70 \r
- beq $7, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $8, $8, -0x80 \r
- beq $8, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $9, $9, -0x90 \r
- beq $9, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $10, $10, -0x100 \r
- beq $10, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $11, $11, -0x110 \r
- beq $11, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $12, $12, -0x120 \r
- beq $12, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $13, $13, -0x130 \r
- beq $13, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $14, $14, -0x140 \r
- beq $14, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $15, $15, -0x150 \r
- beq $15, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $16, $16, -0x160 \r
- beq $16, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $17, $17, -0x170 \r
- beq $17, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $18, $18, -0x180 \r
- beq $18, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $19, $19, -0x190 \r
- beq $19, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $20, $20, -0x200 \r
- beq $20, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $21, $21, -0x210 \r
- beq $21, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $22, $22, -0x220 \r
- beq $22, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $23, $23, -0x230 \r
- beq $23, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $24, $24, -0x240 \r
- beq $24, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $25, $25, -0x250 \r
- beq $25, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- addiu $30, $30, -0x300 \r
- beq $30, $0, .+12 \r
- nop \r
- sw $0, 0($4) \r
- jr $31\r
- nop\r
-\r
- .end vRegTest2\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+#include <p32xxxx.h>\r
+#include <sys/asm.h>\r
+ \r
+ .set nomips16\r
+ .set noreorder\r
+ \r
+ \r
+ .global vRegTest1\r
+ .global vRegTest2\r
+\r
+\r
+ #if (__C32_VERSION__ >= 2 )\r
+ .section .FreeRTOS, code\r
+ #else\r
+ .section .FreeRTOS, "ax", @progbits\r
+ #endif\r
+ .set noreorder\r
+ .set noat\r
+ .ent vRegTest1\r
+\r
+/* Address of $4 ulStatus1 is held in A0, so don't mess with the value of $4 */\r
+\r
+vRegTest1:\r
+ addiu $1, $0, 0x11\r
+ addiu $2, $0, 0x12 \r
+ addiu $3, $0, 0x13 \r
+ addiu $5, $0, 0x15 \r
+ addiu $6, $0, 0x16 \r
+ addiu $7, $0, 0x17 \r
+ addiu $8, $0, 0x18 \r
+ addiu $9, $0, 0x19 \r
+ addiu $10, $0, 0x110 \r
+ addiu $11, $0, 0x111 \r
+ addiu $12, $0, 0x112 \r
+ addiu $13, $0, 0x113 \r
+ addiu $14, $0, 0x114 \r
+ addiu $15, $0, 0x115 \r
+ addiu $16, $0, 0x116 \r
+ addiu $17, $0, 0x117 \r
+ addiu $18, $0, 0x118 \r
+ addiu $19, $0, 0x119 \r
+ addiu $20, $0, 0x120 \r
+ addiu $21, $0, 0x121 \r
+ addiu $22, $0, 0x122 \r
+ addiu $23, $0, 0x123 \r
+ addiu $24, $0, 0x124 \r
+ addiu $25, $0, 0x125 \r
+ addiu $30, $0, 0x130 \r
+\r
+ addiu $1, $1, -0x11\r
+ beq $1, $0, .+12\r
+ nop\r
+ sw $0, 0($4) \r
+ addiu $2, $2, -0x12 \r
+ beq $2, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $3, $3, -0x13 \r
+ beq $3, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $5, $5, -0x15 \r
+ beq $5, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $6, $6, -0x16 \r
+ beq $6, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $7, $7, -0x17 \r
+ beq $7, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $8, $8, -0x18 \r
+ beq $8, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $9, $9, -0x19 \r
+ beq $9, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $10, $10, -0x110 \r
+ beq $10, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $11, $11, -0x111 \r
+ beq $11, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $12, $12, -0x112 \r
+ beq $12, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $13, $13, -0x113 \r
+ beq $13, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $14, $14, -0x114 \r
+ beq $14, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $15, $15, -0x115 \r
+ beq $15, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $16, $16, -0x116 \r
+ beq $16, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $17, $17, -0x117 \r
+ beq $17, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $18, $18, -0x118 \r
+ beq $18, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $19, $19, -0x119 \r
+ beq $19, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $20, $20, -0x120 \r
+ beq $20, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $21, $21, -0x121 \r
+ beq $21, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $22, $22, -0x122 \r
+ beq $22, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $23, $23, -0x123 \r
+ beq $23, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $24, $24, -0x124 \r
+ beq $24, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $25, $25, -0x125 \r
+ beq $25, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $30, $30, -0x130 \r
+ beq $30, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ jr $31\r
+ nop\r
+\r
+ .end vRegTest1\r
+\r
+\r
+ #if (__C32_VERSION__ >= 2 )\r
+ .section .FreeRTOS, code\r
+ #else\r
+ .section .FreeRTOS, "ax", @progbits\r
+ #endif\r
+ .set noreorder\r
+ .set noat\r
+ .ent vRegTest2\r
+\r
+vRegTest2:\r
+\r
+ addiu $1, $0, 0x10\r
+ addiu $2, $0, 0x20 \r
+ addiu $3, $0, 0x30 \r
+ addiu $5, $0, 0x50 \r
+ addiu $6, $0, 0x60 \r
+ addiu $7, $0, 0x70 \r
+ addiu $8, $0, 0x80 \r
+ addiu $9, $0, 0x90 \r
+ addiu $10, $0, 0x100 \r
+ addiu $11, $0, 0x110 \r
+ addiu $12, $0, 0x120 \r
+ addiu $13, $0, 0x130 \r
+ addiu $14, $0, 0x140 \r
+ addiu $15, $0, 0x150 \r
+ addiu $16, $0, 0x160 \r
+ addiu $17, $0, 0x170 \r
+ addiu $18, $0, 0x180 \r
+ addiu $19, $0, 0x190 \r
+ addiu $20, $0, 0x200 \r
+ addiu $21, $0, 0x210 \r
+ addiu $22, $0, 0x220 \r
+ addiu $23, $0, 0x230 \r
+ addiu $24, $0, 0x240 \r
+ addiu $25, $0, 0x250 \r
+ addiu $30, $0, 0x300 \r
+\r
+ addiu $1, $1, -0x10\r
+ beq $1, $0, .+12\r
+ nop\r
+ sw $0, 0($4) \r
+ addiu $2, $2, -0x20 \r
+ beq $2, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $3, $3, -0x30 \r
+ beq $3, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $5, $5, -0x50 \r
+ beq $5, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $6, $6, -0x60 \r
+ beq $6, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $7, $7, -0x70 \r
+ beq $7, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $8, $8, -0x80 \r
+ beq $8, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $9, $9, -0x90 \r
+ beq $9, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $10, $10, -0x100 \r
+ beq $10, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $11, $11, -0x110 \r
+ beq $11, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $12, $12, -0x120 \r
+ beq $12, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $13, $13, -0x130 \r
+ beq $13, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $14, $14, -0x140 \r
+ beq $14, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $15, $15, -0x150 \r
+ beq $15, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $16, $16, -0x160 \r
+ beq $16, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $17, $17, -0x170 \r
+ beq $17, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $18, $18, -0x180 \r
+ beq $18, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $19, $19, -0x190 \r
+ beq $19, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $20, $20, -0x200 \r
+ beq $20, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $21, $21, -0x210 \r
+ beq $21, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $22, $22, -0x220 \r
+ beq $22, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $23, $23, -0x230 \r
+ beq $23, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $24, $24, -0x240 \r
+ beq $24, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $25, $25, -0x250 \r
+ beq $25, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ addiu $30, $30, -0x300 \r
+ beq $30, $0, .+12 \r
+ nop \r
+ sw $0, 0($4) \r
+ jr $31\r
+ nop\r
+\r
+ .end vRegTest2\r
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