int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
{
FNC_INFO;
- int retval;
u32 dscr_local_tmp_copy;
if (!dscr)
{
dscr = &dscr_local_tmp_copy;
- if ((retval=arm11_read_DSCR(arm11, dscr))!=ERROR_OK)
- return retval;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
}
if (!(*dscr & ARM11_DSCR_MODE_SELECT))
}}
/* Save DSCR */
- int retval;
- if ((retval=arm11_read_DSCR(arm11, &R(DSCR)))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
/* Save wDTR */
otherwise our programming would be sloppy */
{
u32 DSCR;
- int retval;
- if ((retval=arm11_read_DSCR(arm11, &DSCR))!=ERROR_OK)
- {
- return retval;
- }
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
{
return ERROR_OK;
u32 dscr;
- int retval;
- if ((retval=arm11_read_DSCR(arm11, &dscr))!=ERROR_OK)
- return retval;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
LOG_DEBUG("DSCR %08x", dscr);
- if ((retval=arm11_check_init(arm11, &dscr))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_check_init(arm11, &dscr));
if (dscr & ARM11_DSCR_CORE_HALTED)
{
/* target execution control */
int arm11_halt(struct target_s *target)
{
- int retval = ERROR_OK;
-
FNC_INFO;
arm11_common_t * arm11 = target->arch_info;
arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
- if((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
u32 dscr;
while (1)
{
- int retval;
- retval = arm11_read_DSCR(arm11, &dscr);
- if (retval!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
if (dscr & ARM11_DSCR_CORE_HALTED)
break;
target->state = TARGET_HALTED;
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
- if((retval = target_call_event_callbacks(target,
- old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(
+ target_call_event_callbacks(target,
+ old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
return ERROR_OK;
}
int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
{
- int retval = ERROR_OK;
-
FNC_INFO;
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
- if((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
while (1)
{
u32 dscr;
- retval = arm11_read_DSCR(arm11, &dscr);
- if (retval!=ERROR_OK)
- return retval;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
LOG_DEBUG("DSCR %08x", dscr);
target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
- if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
}
else
{
target->state = TARGET_DEBUG_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
- if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
- {
- return retval;
- }
+
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
}
return ERROR_OK;
int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
{
- int retval = ERROR_OK;
-
FNC_INFO;
LOG_DEBUG("target->state: %s",
u32 next_instruction;
- if ((arm11_read_memory_word(arm11, R(PC), &next_instruction))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
/* skip over BKPT */
if ((next_instruction & 0xFFF00070) == 0xe1200070)
brp[1].address = ARM11_SC7_BCR0;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
- if ((retval=arm11_sc7_run(arm11, brp, asizeof(brp)))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
/* resume */
R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
- if ((retval=arm11_leave_debug_state(arm11))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_leave_debug_state(arm11));
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
- if((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
/** \todo TODO: add a timeout */
while (1)
{
u32 dscr;
- retval = arm11_read_DSCR(arm11, &dscr);
- if (retval!=ERROR_OK)
- return retval;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
LOG_DEBUG("DSCR %08x", dscr);
arm11_sc7_clear_vbw(arm11);
/* save state */
- if((retval = arm11_on_enter_debug_state(arm11))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
/* restore default state */
R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
// target->state = TARGET_HALTED;
target->debug_reason = DBG_REASON_SINGLESTEP;
- if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
return ERROR_OK;
}
if (target->reset_halt)
{
- int retval;
- if ((retval = target_halt(target))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(target_halt(target));
}
return ERROR_OK;
}
// no debug, otherwise breakpoint is not set
- if((retval = target_resume(target, 0, entry_point, 1, 0)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
- if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
if (target->state != TARGET_HALTED)
{
- if ((retval=target_halt(target))!=ERROR_OK)
- return retval;
- if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_halt(target));
+
+ CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
+
retval = ERROR_TARGET_TIMEOUT;
+
goto del_breakpoint;
}
int arm11_target_create(struct target_s *target, Jim_Interp *interp)
{
- int retval = ERROR_OK;
FNC_INFO;
NEW(arm11_common_t, arm11, 1);
arm11->jtag_info.tap = target->tap;
arm11->jtag_info.scann_size = 5;
- if((retval = arm_jtag_setup_connection(&arm11->jtag_info)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(arm_jtag_setup_connection(&arm11->jtag_info));
if (target->tap==NULL)
return ERROR_FAIL;
int arm11_examine(struct target_s *target)
{
FNC_INFO;
- int retval;
arm11_common_t * arm11 = target->arch_info;
arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
-
+ CHECK_RETVAL(jtag_execute_queue());
switch (arm11->device_id & 0x0FFFF000)
{
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
if (arm11->last_dscr != dscr)
JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
*value=dscr;
- return retval;
+ return ERROR_OK;
}
/** Write the Debug Status and Control Register (DSCR)
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(jtag_execute_queue());
if (flag)
break;
Data = *data;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
+
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
}
Data = 0;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
+
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(jtag_execute_queue());
size_t error_count = 0;
do
{
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
+
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
+
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
}
*/
int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
{
- int retval;
arm11_run_instr_data_prepare(arm11);
/* MRC p14,0,r0,c0,c5,0 (r0 = address) */
- if ((retval=arm11_run_instr_data_to_core1(arm11, 0xee100e15, address))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address));
/* LDC p14,c5,[R0],#4 (DTR = [r0]) */
- if ((retval=arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1));
arm11_run_instr_data_finish(arm11);