Correct interrupt priority assignment.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@822 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/FreeRTOSConfig.h b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/FreeRTOSConfig.h
index 1458e9e7351d3af50b8f9c399103a829fcc6a34d..2ce1eaab7fe33f1db47c049bcf3754db8ba0e7f9 100644 (file)
--- a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/FreeRTOSConfig.h
+++ b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/FreeRTOSConfig.h
@@ -132,7 +132,9 @@ to exclude the API function. */
 /* Priority 5, or 160 as only the top three bits are implemented. */\r
 #define configMAX_SYSCALL_INTERRUPT_PRIORITY   ( 5 << (8 - configPRIO_BITS) )\r
 \r
-\r
+/* Priorities passed to NVIC_SetPriority() do not require shifting as the\r
+function does the shifting itself. */\r
+#define configEMAC_INTERRUPT_PRIORITY          5\r
 \r
 \r
 \r

diff --git a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/webserver/uIP_Task.c b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/webserver/uIP_Task.c
index 6f56b92cd1fb6b125050d9c884fe0cc6cf9ad02a..71ad5ce3d3121dbd4f22b08dc928599eff71215d 100644 (file)
--- a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/webserver/uIP_Task.c
+++ b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/webserver/uIP_Task.c
@@ -142,7 +142,7 @@ extern void ( vEMAC_ISR_Wrapper )( void );
 \r
                /* Set the interrupt priority to the max permissible to cause some\r
                interrupt nesting. */\r
-               NVIC_SetPriority( ENET_IRQn, configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
+               NVIC_SetPriority( ENET_IRQn, configEMAC_INTERRUPT_PRIORITY );\r
 \r
                /* Enable the interrupt. */\r
                NVIC_EnableIRQ( ENET_IRQn );\r

diff --git a/Demo/CORTEX_LPC1768_GCC_Rowley/FreeRTOSConfig.h b/Demo/CORTEX_LPC1768_GCC_Rowley/FreeRTOSConfig.h
index 1458e9e7351d3af50b8f9c399103a829fcc6a34d..f632705521d99f79d670251eb213b18089877f39 100644 (file)
--- a/Demo/CORTEX_LPC1768_GCC_Rowley/FreeRTOSConfig.h
+++ b/Demo/CORTEX_LPC1768_GCC_Rowley/FreeRTOSConfig.h
@@ -132,6 +132,9 @@ to exclude the API function. */
 /* Priority 5, or 160 as only the top three bits are implemented. */\r
 #define configMAX_SYSCALL_INTERRUPT_PRIORITY   ( 5 << (8 - configPRIO_BITS) )\r
 \r
+/* Priorities passed to NVIC_SetPriority() do not require shifting as the\r
+function does the shifting itself. */\r
+#define configEMAC_INTERRUPT_PRIORITY          5\r
 \r
 \r
 \r

diff --git a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c
index ea9e43e35e089fde88278644fa98070faaff08be..deab7e8f87b31efb921f11a96100a61706edaab1 100644 (file)
--- a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c
+++ b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c
@@ -142,7 +142,7 @@ extern void ( vEMAC_ISR_Wrapper )( void );
 \r
                /* Set the interrupt priority to the max permissible to cause some\r
                interrupt nesting. */\r
-               NVIC_SetPriority( ENET_IRQn, configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
+               NVIC_SetPriority( ENET_IRQn, configEMAC_INTERRUPT_PRIORITY );\r
 \r
                /* Enable the interrupt. */\r
                NVIC_EnableIRQ( ENET_IRQn );\r